Fixes bug in verilog name generation logic

src/passes/analysis/verilog.cpp

@@ -1130,12 +1130,9 @@ Passes::Verilog::compileModuleBody(
   for (auto instance : instances) {
     Module* instance_module = instance.second->getModuleRef();
     std::string module_name = instance_module->getLongName();
-    if (instance_module->isGenerated()) {
-      if (instance_module->getGenerator()->getMetaData().count("verilog") > 0) {
-        json verilog_json = instance_module->getGenerator()
-                              ->getMetaData()["verilog"];
-        module_name = make_name(instance_module->getName(), verilog_json);
-      }
+    if (instance_module->isGenerated() && instance_module->getGenerator()->getMetaData().count("verilog") > 0) {
+      json verilog_json = instance_module->getGenerator()->getMetaData()["verilog"];
+      module_name = make_name(instance_module->getName(), verilog_json);
     }
     else if (instance_module->getMetaData().count("verilog") > 0) {
       json verilog_json = instance_module->getMetaData()["verilog"];

tests/gtest/CMakeLists.txt

@@ -29,6 +29,10 @@ add_executable(test_verilog test_verilog.cpp)
 target_link_libraries(test_verilog gtest_main coreir coreir-commonlib)
 add_test(NAME test_verilog COMMAND test_verilog WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests/gtest)
 
+add_executable(test_verilog_metadata test_verilog_metadata.cpp)
+target_link_libraries(test_verilog_metadata gtest_main coreir coreir-commonlib)
+add_test(NAME test_verilog_metadata COMMAND test_verilog_metadata WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests/gtest)
+
 add_executable(test_inline_wires test_inline_wires.cpp)
 target_link_libraries(test_inline_wires gtest_main coreir coreir-commonlib)
 add_test(NAME test_inline_wires COMMAND test_inline_wires WORKING_DIRECTORY ${CMAKE_SOURCE_DIR}/tests/gtest)

tests/gtest/golds/Add5.json

@@ -0,0 +1,49 @@
+{"top":"global.top",
+"namespaces":{
+  "global":{
+    "modules":{
+      "top":{
+        "type":["Record",[
+
+        ]],
+        "instances":{
+          "inst":{
+            "genref":"global.addN",
+            "genargs":{"width":["Int",5]}
+          }
+        },
+        "connections":[
+          ["inst.out","inst.in"]
+        ]
+      }
+    },
+    "generators":{
+      "addN":{
+        "typegen":"global.wgen",
+        "genparams":{"width":"Int"},
+        "modules":[
+          [
+            {"width":["Int",5]},
+            {
+              "type":["Record",[
+                ["in",["Array",5,"BitIn"]],
+                ["out",["Array",5,"Bit"]]
+              ]],
+              "metadata":{"verilog_name":"Add5"}
+            }
+          ]
+        ]
+      }
+    },
+    "typegens":{
+      "wgen":[
+        {"width":"Int"},
+        "sparse",
+        [
+          [{"width":["Int",5]},["Record",[["in",["Array",5,"BitIn"]],["out",["Array",5,"Bit"]]]]]
+        ]
+      ]
+    }
+  }
+}
+}

tests/gtest/golds/Add5.v

@@ -0,0 +1,11 @@
+// Module `Add5` defined externally
+module top (
+
+);
+wire [4:0] inst_out;
+Add5 inst (
+    .in(inst_out),
+    .out(inst_out)
+);
+endmodule
+

tests/gtest/test_verilog_metadata.cpp

@@ -0,0 +1,55 @@
+#include "gtest/gtest.h"
+#include "assert_pass.h"
+#include "coreir.h"
+#include "coreir/definitions/coreVerilog.hpp"
+#include "coreir/definitions/corebitVerilog.hpp"
+#include "coreir/libs/commonlib.h"
+
+using namespace CoreIR;
+
+namespace {
+
+TEST(VerilogMetaData, TestGeneratedModule) {
+  Context* c = newContext();
+
+  Namespace* g = c->getGlobal();
+
+  // Declare a TypeGenerator (in global) for addN
+  g->newTypeGen(
+    "wgen",  // name for the typegen
+    {{"width", c->Int()}},
+    [](Context* c, Values args) {  // Function to compute type
+    Json width = args.at("width")->get<Json>();
+    return c->Record(
+      {{"in", c->BitIn()->Arr(width)}, {"out", c->Bit()->Arr(width)}});
+    }
+    );
+
+  g->newGeneratorDecl(
+    "addN",
+    g->getTypeGen("wgen"),
+    {{"width", c->Int()}});
+
+  Module* top = g->newModuleDecl("top", c->Record());
+  ModuleDef* def = top->newModuleDef();
+  auto inst = def->addInstance("inst", "global.addN", {{"width", Const::make(c, 5)}});
+  def->connect(inst->sel("in"), inst->sel("out"));
+  top->setDef(def);
+  c->setTop(top);
+
+  Module* gen_module = inst->getModuleRef();
+  gen_module->getMetaData()["verilog_name"] = "Add5";
+
+  serializeToFile(c, "build/Add5.json");
+  assertFileEq("build/Add5.json", "golds/Add5.json");
+
+  const std::vector<std::string> passes = {
+    "rungenerators",
+    "verilog"};
+  c->runPasses(passes, {});
+  assertPassEq(c, "verilog", "golds/Add5.v");
+  deleteContext(c);
+
+}
+
+}