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rdaly525
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coreir
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Fixes bug in verilog name generation logic
- #1016
#1016
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rdaly525
wants to merge 5 commits into
master
rdaly525/coreir:master
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verilog-name
rdaly525/coreir:verilog-name
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Fixes bug in verilog name generation logic
#1016
rdaly525
wants to merge 5 commits into
master
rdaly525/coreir:master
from
verilog-name
rdaly525/coreir:verilog-name
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Commits
Commits on Jul 1, 2021
Update coreir_to_dot to output op instead of names
jeffsetter
committed
48e218c
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Remove unneeded comments
jeffsetter
committed
48997c8
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Commits on Jul 6, 2021
Trigger Build
rdaly525
committed
6b4d796
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Commits on Jul 22, 2021
Fixes bug with verilog name on a generated module
rdaly525
committed
143925b
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Merge branch 'master' into verilog-name
rdaly525
authored
d3bb116
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