Switch from widening_mul to carrying_mul

crates/contracts/core/ab-contract-file/src/lib.rs

@@ -34,12 +34,12 @@
     const_default,
     const_index,
     const_trait_impl,
-    maybe_uninit_fill,
-    trusted_len,
     const_try,
     const_try_residual,
-    try_blocks,
-    widening_mul
+    maybe_uninit_fill,
+    signed_bigint_helpers,
+    trusted_len,
+    try_blocks
 )]
 #![expect(incomplete_features, reason = "generic_const_exprs")]
 // TODO: This feature is not actually used in this crate, but is added as a workaround for

crates/execution/ab-riscv-act4-runner/src/main.rs

@@ -6,8 +6,8 @@
     const_try_residual,
     generic_const_exprs,
     iter_array_chunks,
-    try_blocks,
-    widening_mul
+    signed_bigint_helpers,
+    try_blocks
 )]
 
 mod abundance_rv32i_max;

crates/execution/ab-riscv-coremark-runner/src/main.rs

@@ -3,8 +3,8 @@
     const_trait_impl,
     const_try,
     const_try_residual,
-    try_blocks,
-    widening_mul
+    signed_bigint_helpers,
+    try_blocks
 )]
 #![expect(incomplete_features, reason = "generic_const_exprs")]
 // TODO: This feature is not actually used in this crate, but is added as a workaround for

crates/execution/ab-riscv-interpreter/src/lib.rs

@@ -64,7 +64,7 @@
     const_trait_impl,
     generic_const_exprs,
     result_option_map_or_default,
-    widening_mul
+    signed_bigint_helpers
 )]
 #![cfg_attr(
     not(any(

crates/execution/ab-riscv-interpreter/src/rv32/m.rs

@@ -53,10 +53,10 @@ where
                 Ok(ControlFlow::Continue((rd, value)))
             }
             Self::Mulh { rd, rs1: _, rs2: _ } => {
-                // Signed × signed: widen to i64, take upper 32 bits
+                // Signed × signed: multiply and take upper 32 bits
                 let (_lo, prod) = rs1_value
                     .cast_signed()
-                    .widening_mul(rs2_value.cast_signed());
+                    .carrying_mul(rs2_value.cast_signed(), 0);
                 Ok(ControlFlow::Continue((rd, prod.cast_unsigned())))
             }
             Self::Mulhsu { rd, rs1: _, rs2: _ } => {

crates/execution/ab-riscv-interpreter/src/rv64/m.rs

@@ -53,10 +53,10 @@ where
                 Ok(ControlFlow::Continue((rd, value)))
             }
             Self::Mulh { rd, rs1: _, rs2: _ } => {
-                // Signed × signed: widen to i128, take upper 64 bits
+                // Signed × signed: multiply and take upper 64 bits
                 let (_lo, prod) = rs1_value
                     .cast_signed()
-                    .widening_mul(rs2_value.cast_signed());
+                    .carrying_mul(rs2_value.cast_signed(), 0);
                 Ok(ControlFlow::Continue((rd, prod.cast_unsigned())))
             }
             Self::Mulhsu { rd, rs1: _, rs2: _ } => {

crates/execution/ab-riscv-interpreter/src/rv64/m/tests.rs

@@ -32,7 +32,7 @@ fn test_mulh() {
 
     execute(&mut state).unwrap();
 
-    let (_, hi) = i64::MAX.widening_mul(2);
+    let (_, hi) = i64::MAX.carrying_mul(2, 0);
     assert_eq!(state.regs.read(Reg::A2), hi.cast_unsigned());
 }