[X86] use vdivph for i8 integer division on avx512fp16

[AryanBhirud]

Closes #214431

This patch enables lowering of i8 vector integer divisions through FP16 vector division when the target has fast vector FP16 division support.

For i8 vector divisions, the existing lowering path can require widening through larger integer types before converting to floating point, introducing unnecessary conversions and preventing generation of the native vdivph instruction available on AVX512FP16 targets.

This change:

• Adds a new X86 tuning feature TuningFastVectorFP16Div.
• Updates X86ISelLowering to use FP16 vector division for eligible i8 vector operations.

[github-actions]

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[llvmorg-github-actions]

@llvm/pr-subscribers-backend-x86

Author: Aryan Bhirud (AryanBhirud)

Changes

Closes #214431

This patch enables lowering of i8 vector integer divisions through FP16 vector division when the target has fast vector FP16 division support.

For i8 vector divisions, the existing lowering path can require widening through larger integer types before converting to floating point, introducing unnecessary conversions and preventing generation of the native vdivph instruction available on AVX512FP16 targets.

This change:

• Adds a new X86 tuning feature TuningFastVectorFP16Div.
• Updates X86ISelLowering to use FP16 vector division for eligible i8 vector operations.

---

Full diff: https://github.com/llvm/llvm-project/pull/215131.diff

2 Files Affected:

• (modified) llvm/lib/Target/X86/X86.td (+4)
• (modified) llvm/lib/Target/X86/X86ISelLowering.cpp (+12-2)

diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index f40b937efa74b..299950c061356 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -798,6 +798,10 @@ def TuningFastDPWSSD
           "Prefer vpdpwssd instruction over vpmaddwd+vpaddd instruction sequence",
           [], InlineIgnore>;
 
+def TuningFastVectorFP16Div
+    : SubtargetFeature<"fast-vector-fp16-div", "HasFastFP16Div", "true",
+                        "Vector FP16 division is fast",
+                        [], InlineIgnore>;
 def TuningPreferNoGather
     : SubtargetFeature<"prefer-no-gather", "PreferGather", "false",
                        "Prefer no gather instructions",
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c74d342fed1cb..d12b14861bb56 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -50669,7 +50669,10 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
 
   // f32 recovers the quotient exactly when both operands fit in 24 bits
   MVT FPSclVT = MVT::f64;
-  if (EltBits <= 16 || BothFitFP(APFloat::IEEEsingle()))
+  if (EltBits == 8 && Subtarget.hasFastFP16Div() &&
+      BothFitFP(APFloat::IEEEhalf()))
+    FPSclVT = MVT::f16;
+  else if (EltBits <= 16 || BothFitFP(APFloat::IEEEsingle()))
     FPSclVT = MVT::f32;
   EVT FPVT = VT.changeVectorElementType(*DAG.getContext(), FPSclVT);
 
@@ -50728,8 +50731,15 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
     Q = IsSigned ? DAG.getSExtOrTrunc(Q, DL, VT)
                  : DAG.getZExtOrTrunc(Q, DL, VT);
   } else {
+    SDValue FPQuot = DAG.getNode(ISD::FDIV, DL, FPVT, X, Y);
     unsigned FromFP = IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
-    Q = DAG.getNode(FromFP, DL, VT, DAG.getNode(ISD::FDIV, DL, FPVT, X, Y));
+    if (FPSclVT == MVT::f16 && EltBits == 8) {
+      EVT I16VT = VT.changeVectorElementType(*DAG.getContext(), MVT::i16);
+      SDValue Q16 = DAG.getNode(FromFP, DL, I16VT, FPQuot);
+      Q = DAG.getNode(ISD::TRUNCATE, DL, VT, Q16);
+    } else {
+      Q = DAG.getNode(FromFP, DL, VT, FPQuot);
+    }
   }
   if (!IsRem)
     return Q;

[Andarwinux]

(EltBits == 8 || BothFitFP(APFloat::IEEEhalf())) && Subtarget.hasFastFP16Div()

[Andarwinux]

test coverage?