Fix BramFactor co-sim and enable it for io_parallel

hls4ml/templates/vivado/myproject_test.cpp

@@ -23,6 +23,8 @@ size_t trace_type_size = sizeof(double);
 int main(int argc, char **argv) {
     // hls-fpga-machine-learning insert namespace
 
+    // hls-fpga-machine-learning insert load weights
+
     // load input data from text file
     std::ifstream fin("tb_data/tb_input_features.dat");
     // load predictions from text file

hls4ml/writer/vivado_writer.py

@@ -220,6 +220,8 @@ def write_project_cpp(self, model):
                     newline += indent + '#pragma HLS INTERFACE ap_vld port={},{} \n'.format(
                         ','.join(all_inputs), ','.join(all_outputs)
                     )
+                    if all_brams:
+                        newline += indent + '#pragma HLS INTERFACE bram port={} \n'.format(','.join(all_brams))
                     newline += pipeline_pragma
 
                 if io_type == 'io_stream':
@@ -586,6 +588,14 @@ def write_test_bench(self, model):
                 for bram in model_brams:
                     newline += f'#include "firmware/weights/{bram.name}.h"\n'
 
+            elif '// hls-fpga-machine-learning insert load weights' in line:
+                newline = line
+                if model_brams and model.config.get_writer_config()['WriteWeightsTxt']:
+                    for bram in model_brams:
+                        newline += indent + 'nnet::load_weights_from_txt<{}, {}>({}, "{}.txt");\n'.format(
+                            bram.type.name, bram.data_length, bram.name, bram.name
+                        )
+
             elif '// hls-fpga-machine-learning insert data' in line:
                 newline = line
                 offset = 0