Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework

Overview

• Verilog AST Based Augmentation
• Verilog Auto Splitting
• EDA Tool Script Data Augmentation
• LLM for Verilog Automatic benchmark Tool

Use mkdocs in docs folder for more information.

Prerequist

• antlr4
• python

Team Members

Authors: Kaiyan Chang, Kun Wang, Nan Yang, Ying Wang*(Corresponding Author, Advisor), Dantong Jin, Wenlong Zhu, Zhirong Chen, Cangyuan Li, Hao Yan, Yunhao Zhou, Zhuoliang Zhao, Yuan Cheng, Yudong Pan, Yiqi Liu, Mengdi Wang, Shengwen Liang, yinhe Han, Huawei Li and Xiaowei Li

Affiliate: Institute of Computing Technology, Chinese Academy of Science

Dataset Link

https://modelscope.cn/datasets/changkaiyan/chipgptseries

Model Link

https://www.modelscope.cn/models/changkaiyan/ChipGPT-Llama2-SFT-7B (Comprehensive Version for Verilog Generation, Siliconcompiler and Verilog Repair.)

https://www.modelscope.cn/models/changkaiyan/ChipGPT-Llama3.1-8B-SFT (Extended Verilog Generation Version.)

Reference

@misc{chang2024chipgptft,
  title = {Data is all you need:  Finetuning LLMs for Chip Design via an Automated design-data augmentation framework},
  author = {Kaiyan Chang and Kun Wang and Nan Yang and Ying Wang and Dantong Jin and Wenlong Zhu and Zhirong Chen and Cangyuan Li and Hao Yan and Yunhao Zhou and Zhuoliang Zhao and Yuan Cheng and Yudong Pan and Yiqi Liu and Mengdi Wang and Shengwen Liang and yinhe han and Huawei Li and Xiaowei Li},
  booktitle = {61th Design Automation Conference (DAC)},
  year = {2024},
  url = {}
}

Email

If you have any question, please contact changkaiyan@live.com