Verilog Equivalence Checkiing

Author: Yunhao Zhou
Date: 2024-10-21

1. Introduction

This is a framework for Verilog code automated equivalence checking.

2. Requirements

Please install Yosys before using this framework.

2. Usage

from Verilog_equivalence_checking import *
res = Verilog_equivalence_checking(rtl1_path, rtl2_path)

Where rtl1_path and rtl2_path are the paths of two RTL files for equivalence checking, the res is to save the result of equivalence checking.