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drm: panel: jd9365da: add 2lane configuration for radxa_display_8hd_ad002 #597

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drm: panel: jd9365da: add 2lane configuration for radxa_display_8hd_ad002 #597

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153780f
drm: panel: jd9365da: add 2lane configuration for radxa_display_8hd_a…
skljfi Aug 21, 2026
0413dc3
drm/msm/dpu: change the LM allocation method
skljfi Aug 21, 2026
8b9bbc7
drm: panel: jd9365da: adjust the command writing method for radxa_dis…
skljfi Aug 24, 2026
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6 changes: 3 additions & 3 deletions drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1367,7 +1367,6 @@ static int dpu_crtc_reassign_planes(struct drm_crtc *crtc, struct drm_crtc_state
}

#define MAX_CHANNELS_PER_CRTC PIPES_PER_PLANE
#define MAX_HDISPLAY_SPLIT 1080

static struct msm_display_topology dpu_crtc_get_topology(
struct drm_crtc *crtc,
Expand Down Expand Up @@ -1403,7 +1402,7 @@ static struct msm_display_topology dpu_crtc_get_topology(
* count both the WB and real-time phys encoders.
*
* For non-DSC CWB usecases, have the num_lm be decided by the
* (mode->hdisplay > MAX_HDISPLAY_SPLIT) check.
* platform's maximum mixer width.
*/

if (topology.num_intf == 2 && !topology.cwb_enabled)
Expand All @@ -1412,7 +1411,8 @@ static struct msm_display_topology dpu_crtc_get_topology(
topology.num_lm = 2;
else if (dpu_kms->catalog->caps->has_3d_merge &&
topology.num_dsc == 0)
topology.num_lm = (mode->hdisplay > MAX_HDISPLAY_SPLIT) ? 2 : 1;
topology.num_lm =
(mode->hdisplay > dpu_kms->catalog->caps->max_mixer_width) ? 2 : 1;
else
topology.num_lm = 1;

Expand Down
215 changes: 215 additions & 0 deletions drivers/gpu/drm/panel/panel-jadard-jd9365da-h3.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -402,6 +402,217 @@ static const struct jadard_panel_desc radxa_display_8hd_ad002_desc = {
.format = MIPI_DSI_FMT_RGB888,
.init = radxa_display_8hd_ad002_init_cmds,
};
static int radxa_display_8hd_ad002_2lane_init_cmds(struct jadard *jadard)
{
struct mipi_dsi_multi_context dsi_ctx = { .dsi = jadard->dsi };

jd9365da_switch_page(&dsi_ctx, 0x00);
jadard_enable_standard_cmds(&dsi_ctx);

jd9365da_switch_page(&dsi_ctx, 0x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x72);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x65);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x74);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0xB7);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0xB7);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0xFE);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x37, 0x19);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x38, 0x05);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x39, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3A, 0x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3B, 0x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3C, 0x70);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3D, 0xFF);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3E, 0xFF);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x3F, 0xFF);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x40, 0x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x41, 0xA0);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x43, 0x1E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x44, 0x0F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x45, 0x28);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x4B, 0x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x55, 0x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x56, 0x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x57, 0xA9);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x0A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x0A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x37);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x19);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x78);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x63);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x54);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x48);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x45);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x38);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x3D);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x28);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x43);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x41);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x43);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x62);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x50);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x57);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x49);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x44);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x37);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x23);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x10);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x78);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x63);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x54);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x49);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x45);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0x38);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x3D);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0x28);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x43);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x41);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x43);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x62);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x50);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x57);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x49);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7F, 0x44);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x37);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x81, 0x23);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x82, 0x10);

jd9365da_switch_page(&dsi_ctx, 0x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x47);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x01, 0x47);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0x45);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x03, 0x45);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x04, 0x4B);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x05, 0x4B);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x06, 0x49);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x07, 0x49);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x08, 0x41);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0A, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0B, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0C, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0D, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0F, 0x5F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x10, 0x5F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x11, 0x57);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x12, 0x77);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x13, 0x35);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x14, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x15, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x16, 0x46);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x17, 0x46);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x18, 0x44);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x19, 0x44);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1A, 0x4A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1B, 0x4A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1C, 0x48);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1D, 0x48);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1E, 0x40);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x1F, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x20, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x21, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x22, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x23, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x24, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x25, 0x5F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x26, 0x5F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x27, 0x57);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x28, 0x77);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x29, 0x35);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2A, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x2B, 0x1F);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x58, 0x40);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x59, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5A, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5B, 0x10);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5C, 0x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5D, 0x40);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5E, 0x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x5F, 0x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x60, 0x30);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x61, 0x01);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x62, 0x02);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x63, 0x03);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x64, 0x6B);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x65, 0x05);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x66, 0x0C);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x67, 0x73);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x68, 0x09);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x69, 0x03);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6A, 0x56);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6B, 0x08);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6C, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6D, 0x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6E, 0x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x6F, 0x88);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x70, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x71, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x72, 0x06);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x73, 0x7B);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x74, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x75, 0xF8);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x76, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x77, 0xD5);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x78, 0x2E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x79, 0x12);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7A, 0x03);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7B, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7C, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7D, 0x03);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x7E, 0x7B);

jd9365da_switch_page(&dsi_ctx, 0x04);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x00, 0x0E);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x02, 0xB3);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x09, 0x60);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x0E, 0x2A);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x36, 0x59);

jd9365da_switch_page(&dsi_ctx, 0x00);
mipi_dsi_dcs_write_seq_multi(&dsi_ctx, 0x80, 0x01);
jd9365da_switch_page(&dsi_ctx, 0x00);

mipi_dsi_msleep(&dsi_ctx, 120);

mipi_dsi_dcs_exit_sleep_mode_multi(&dsi_ctx);

mipi_dsi_dcs_set_display_on_multi(&dsi_ctx);

return dsi_ctx.accum_err;
};

static const struct jadard_panel_desc radxa_display_8hd_ad002_2lane_desc = {
.mode = {
.clock = 70000,

.hdisplay = 800,
.hsync_start = 800 + 40,
.hsync_end = 800 + 40 + 20,
.htotal = 800 + 40 + 20 + 20,

.vdisplay = 1280,
.vsync_start = 1280 + 30,
.vsync_end = 1280 + 30 + 4,
.vtotal = 1280 + 30 + 4 + 28,

.width_mm = 107,
.height_mm = 199,
.type = DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED,
.flags = DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC,
},
.lanes = 2,
.format = MIPI_DSI_FMT_RGB888,
.init = radxa_display_8hd_ad002_2lane_init_cmds,
.mode_flags = MIPI_DSI_MODE_VIDEO | MIPI_DSI_MODE_VIDEO_BURST |
MIPI_DSI_MODE_LPM | MIPI_DSI_MODE_NO_EOT_PACKET,
};

static int cz101b4001_init_cmds(struct jadard *jadard)
{
Expand Down Expand Up @@ -1475,6 +1686,10 @@ static const struct of_device_id jadard_of_match[] = {
.compatible = "radxa,display-8hd-ad002",
.data = &radxa_display_8hd_ad002_desc
},
{
.compatible = "radxa,display-8hd-ad002-2lane",
.data = &radxa_display_8hd_ad002_2lane_desc
},
{ /* sentinel */ }
};
MODULE_DEVICE_TABLE(of, jadard_of_match);
Expand Down