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feat: generate full default SDC with PDK-driven output load - #206

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feat: generate full default SDC with PDK-driven output load#206
Emin017 wants to merge 2 commits into
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emin/enhance-sdc

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@Emin017 Emin017 commented Aug 11, 2026

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Rewrite create_default_sdc as a template that adds IO delay, clock uncertainty/transition and max-fanout constraints on top of the clock definition. Clock name/port, frequency and max fanout come from workspace parameters; the new PDK field sdc_load (set to 0.001 for ics55, also readable from external pdk.json) gates the optional set_load section.

What Changed

Scope

Select the areas touched by this PR:

  • CLI - command behavior, Typer command surface, output formats, or workspace commands.
  • Flow/runtime - workspace lifecycle, EngineFlow, step execution, logs, metrics, or artifacts.
  • EDA integration - Yosys, ECC-Tools, DreamPlace, KLayout, PDKs, or native/runtime wrappers.
  • Build/package - Nix, PyInstaller, wheels, uv.lock, or release artifacts.
  • CI/release - GitHub Actions, version checks, changelog, or release automation.
  • Tests/docs only

Runtime And Packaging Impact

  • No runtime or packaging impact
  • CLI output or machine-readable contract changed
  • Workspace layout, flow state, or artifact paths changed
  • Native toolchain or wrapper behavior changed
  • ecc-tools or ecc-dreamplace dependency changed
  • PyInstaller, Nix, or release artifact changed

Notes:

Validation

List the commands you ran. Mark checks that are not applicable as N/A.

  • uv run pytest test/
  • uv run ruff check chipcompiler test
  • uv run ruff format --check chipcompiler test
  • PyInstaller smoke: ecc --help, ecc --version, ecc version --json
  • Nix smoke: nix run .#cli -- --help
  • Manual flow smoke:
  • Other:

Skipped checks and reason:

Checklist

  • I kept the change scoped to ECC.
  • I updated docs or user-facing CLI text where behavior changed.
  • I included lockfile or version metadata updates when dependencies changed.
  • I documented any submodule updates and why they are needed.
  • I did not include local caches, virtual environments, or generated build outputs.
  • I explained skipped validation and remaining risk.

Rewrite create_default_sdc as a template that adds IO delay, clock
uncertainty/transition and max-fanout constraints on top of the clock
definition. Clock name/port, frequency and max fanout come from
workspace parameters; the new PDK field sdc_load (set to 0.001 for
ics55, also readable from external pdk.json) gates the optional
set_load section.
A design without a clock port previously produced a broken
'get_ports ""' constraint; generate a __VIRTUAL_CLK__ create_clock
without a source port instead so downstream tools still have a clock
object as timing reference.

Also move SDC generation from the oversized workspace/__init__.py into
a new workspace/sdc.py module, restructured as complete per-branch
template constants instead of hole-filled f-string assembly.
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