feat: generate full default SDC with PDK-driven output load - #206
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feat: generate full default SDC with PDK-driven output load#206Emin017 wants to merge 2 commits into
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Rewrite create_default_sdc as a template that adds IO delay, clock uncertainty/transition and max-fanout constraints on top of the clock definition. Clock name/port, frequency and max fanout come from workspace parameters; the new PDK field sdc_load (set to 0.001 for ics55, also readable from external pdk.json) gates the optional set_load section.
A design without a clock port previously produced a broken 'get_ports ""' constraint; generate a __VIRTUAL_CLK__ create_clock without a source port instead so downstream tools still have a clock object as timing reference. Also move SDC generation from the oversized workspace/__init__.py into a new workspace/sdc.py module, restructured as complete per-branch template constants instead of hole-filled f-string assembly.
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Rewrite create_default_sdc as a template that adds IO delay, clock uncertainty/transition and max-fanout constraints on top of the clock definition. Clock name/port, frequency and max fanout come from workspace parameters; the new PDK field sdc_load (set to 0.001 for ics55, also readable from external pdk.json) gates the optional set_load section.
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ecc-toolsorecc-dreamplacedependency changedNotes:
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uv run pytest test/uv run ruff check chipcompiler testuv run ruff format --check chipcompiler testecc --help,ecc --version,ecc version --jsonnix run .#cli -- --helpSkipped checks and reason:
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