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docs: update SystemVerilog version reference to 2017 #94

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2 changes: 1 addition & 1 deletion VerilogCodingStyle.md
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Expand Up @@ -3095,7 +3095,7 @@ body for explanations examples, and exceptions.

### Basic Style Elements

* Use SystemVerilog-2012 conventions, files named as module.sv, one file
* Use SystemVerilog-2017 conventions, files named as module.sv, one file
per module
* Only ASCII, **100** chars per line, **no** tabs, **two** spaces per
indent for all paired keywords.
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