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Integrate new Ethernet #693

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471ce39
[rtl,eth] Delete old Ethernet peripheral
Jul 29, 2026
8001b77
[fpga,vendor] Integrate new Ethernet IP
Jul 29, 2026
c834feb
[sw] Ethernet HAL + smoke test
Jul 29, 2026
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2 changes: 1 addition & 1 deletion hw/top_chip/chip_mocha_genesys2.core
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Expand Up @@ -9,7 +9,7 @@ filesets:
depend:
- lowrisc:mocha:top_chip_system
- lowrisc:prim_xilinx:all
- lowrisc::ethernet
- lowrisc:ethernet:axi_top
- lowrisc:mocha:rng
- pulp-platform.org::axi
files:
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4 changes: 0 additions & 4 deletions hw/top_chip/data/placement_genesys2.xdc
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@@ -1,7 +1,3 @@
## Copyright lowRISC contributors (COSMIC project).
## Licensed under the Apache License, Version 2.0, see LICENSE for details.
## SPDX-License-Identifier: Apache-2.0

## Ethernet MAC Placement Constraints
## Helps to pass timing reliably for a path with 2ns setup requirement
set_property LOC SLICE_X152Y75 [get_cells u_eth_wrapper/u_framing_top/rgmii_soc1/core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_2_reg]
6 changes: 6 additions & 0 deletions hw/top_chip/data/timing_genesys2.xdc
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Expand Up @@ -16,6 +16,12 @@ create_clock -period 8.000 -waveform {0 4} -name eth_rxck_pin [get_ports eth_rx_
## Ethernet PHY Rx Clock Asynchronous with All Other Clocks
set_clock_groups -asynchronous -group [get_clocks eth_rxck_pin -include_generated_clocks];

## Ethernet logic/TX clock
create_clock -period 8.000 -waveform {0 4} -name eth_main_clk [get_nets clk_125m];

# Prevent synthesis tool from trying to time the crossing from clk_125m to the main system clock (50MHz)
set_clock_groups -asynchronous -group [get_clocks eth_main_clk -include_generated_clocks];

## Tag Controller to MIG AXI CDC Constraints
## Removed since the custom attribute async cannot be used to select pins,
## and the CDC paths can be timed without difficulty
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6 changes: 6 additions & 0 deletions hw/top_chip/ip/gen_xilinx_ip.tcl
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Expand Up @@ -2,8 +2,14 @@
# Licensed under the Apache License, Version 2.0, see LICENSE for details.
# SPDX-License-Identifier: Apache-2.0

# Enable XPMs to be used for instantiating Xilinx FPGA primitives
auto_detect_xpm

## MIG IP
# Generate the MIG IP for the Genessys2 board to interface with off-chip memory
create_ip -name mig_7series -vendor xilinx.com -library ip -version 4.2 -module_name u_xlnx_mig_7_ddr3

# Workaround because FuseSoC expects a different file structure to Vivado
exec cp ./src/lowrisc_mocha_chip_mocha_genesys2_0/ip/mig_genesys2_mocha.prj ./lowrisc_mocha_chip_mocha_genesys2_0.srcs/sources_1/ip/u_xlnx_mig_7_ddr3/mig_genesys2_mocha.prj

set_property -dict [list \
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9 changes: 4 additions & 5 deletions hw/top_chip/rtl/chip_mocha_genesys2.sv
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Expand Up @@ -572,10 +572,6 @@ module chip_mocha_genesys2 #(
.default_mst_port_i ('0)
);

// Async reset for ethernet PHY
// NOTE: Using eth_rst_n_sync_125m to reset the PHY breaks Tx
assign eth_phyrst_n = fpga_rst_n_sync_cfg;

// Ethernet MAC wrapper
ethernet_wrapper u_eth_wrapper (
// Clocking and reset
Expand All @@ -601,7 +597,10 @@ module chip_mocha_genesys2 #(
.eth_rgmii_tx_en_o (eth_tx_en),
.eth_rgmii_tx_d_o (eth_tx_d),
.eth_rgmii_mdio_io (eth_mdio),
.eth_rgmii_mdc_o (eth_mdc)
.eth_rgmii_mdc_o (eth_mdc),

// Ethernet PHY reset
.eth_phy_reset_no (eth_phyrst_n)
);

// SW-DV window: read-only HW_ID register.
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161 changes: 68 additions & 93 deletions hw/top_chip/rtl/ethernet_wrapper.sv
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Expand Up @@ -28,28 +28,20 @@ module ethernet_wrapper (
output logic eth_rgmii_tx_en_o,
output logic [3:0] eth_rgmii_tx_d_o,
inout logic eth_rgmii_mdio_io,
output logic eth_rgmii_mdc_o
output logic eth_rgmii_mdc_o,

// PHY reset
output logic eth_phy_reset_no
);
// AXI signals from CDC FIFO to axi_to_mem, synchronous to clk_125m
top_pkg::axi_dev_req_t eth_125m_req;
top_pkg::axi_dev_resp_t eth_125m_resp;

// Framing top 64-bit memory format signals
logic eth_en;
logic [ top_pkg::AxiAddrWidth-1:0] eth_addr;
logic [ top_pkg::AxiDataWidth-1:0] eth_wdata;
logic [top_pkg::AxiDataWidth/8-1:0] eth_be;
logic eth_we_d;
logic eth_we_q;
logic eth_rvalid;
logic [ top_pkg::AxiDataWidth-1:0] eth_rdata;
top_pkg::axi_dev_req_t axi_125m_req;
top_pkg::axi_dev_resp_t axi_125m_rsp;

// MDIO buffer control signals
logic eth_mdio_i;
logic eth_mdio_o;
logic eth_mdio_oe;
///////////////////////////////
// CDC to the Ethernet clock //
///////////////////////////////

// Async AXI FIFO from clk_axi_i to clk_125m_i
// Synchronise AXI bus from clk_axi_i to clk_125m_i
axi_cdc #(
.aw_chan_t ( top_pkg::axi_dev_aw_chan_t ),
.w_chan_t ( top_pkg::axi_w_chan_t ),
Expand All @@ -67,93 +59,76 @@ module ethernet_wrapper (
.src_resp_o (axi_resp_o),
.dst_clk_i (clk_125m_i),
.dst_rst_ni (rst_eth_ni),
.dst_req_o (eth_125m_req),
.dst_resp_i (eth_125m_resp)
.dst_req_o (axi_125m_req),
.dst_resp_i (axi_125m_rsp)
);

// AXI to mem for framing top
axi_to_mem #(
.axi_req_t ( top_pkg::axi_dev_req_t ),
.axi_resp_t ( top_pkg::axi_dev_resp_t ),
.AddrWidth ( top_pkg::AxiAddrWidth ),
.DataWidth ( top_pkg::AxiDataWidth ),
.IdWidth ( top_pkg::AxiDevIdWidth ),
.NumBanks ( 1 )
) u_eth_axi_to_mem (
// The interrupt line needs to be synchronised back to the main clock domain
logic ethernet_irq_125m_q; // First flop the IRQ on source domain to deglitch
prim_flop u_eth_irq_flop (
.clk_i (clk_125m_i),
.rst_ni (rst_eth_ni),

// AXI interface.
.busy_o ( ),
.axi_req_i (eth_125m_req),
.axi_resp_o (eth_125m_resp),

// Memory interface.
.mem_req_o (eth_en),
.mem_gnt_i (1'b1),
.mem_addr_o (eth_addr),
.mem_wdata_o (eth_wdata),
.mem_strb_o (eth_be),
.mem_atop_o ( ),
.mem_we_o (eth_we_d),
.mem_rvalid_i (eth_rvalid),
.mem_rdata_i (eth_we_q ? 64'hBADDBADDBADDBADD : eth_rdata)
.d_i (ethernet_irq_125m),
.q_o (ethernet_irq_125m_q)
);
prim_flop_2sync #(
.Width (1),
.ResetValue (1'b0)
) u_eth_irq_sync (
.clk_i (clk_axi_i),
.rst_ni (rst_axi_ni),
.d_i (ethernet_irq_125m_q),
.q_o (ethernet_irq_o)
);

// Single-cycle read response.
always_ff @(posedge clk_125m_i or negedge rst_eth_ni) begin
if (!rst_eth_ni) begin
eth_rvalid <= '0;
eth_we_q <= '0;
end else begin
eth_rvalid <= eth_en; // Generate rvalid strobes even for writes
eth_we_q <= eth_we_d;
end
end

// Packet framing top
framing_top u_framing_top (
// Memory interface.
.msoc_clk (clk_125m_i), // Some internal logic assumes msoc_clk == clk_int
.core_lsu_addr (eth_addr[14:0]),
.core_lsu_wdata (eth_wdata),
.core_lsu_be (eth_be),
.ce_d (eth_en),
.we_d (eth_en & eth_we_d),
.framing_sel (eth_en),
.framing_rdata (eth_rdata),
.rst_int (!rst_eth_ni),

// Clocks.
.clk_int (clk_125m_i), // 125 MHz in-phase
.clk90_int (clk_125m_quad_i), // 125 MHz quadrature
.clk_200_int (clk_200m_i),
//////////////////////////////
// Instantiate ethernet_top //
///////////////////////////////

// 1000BASE-T RGMII PHY interface.
.phy_rx_clk (eth_rgmii_rx_clk_i),
.phy_rxd (eth_rgmii_rx_d_i),
.phy_rx_ctl (eth_rgmii_rx_ctl_i),
.phy_tx_clk (eth_rgmii_tx_clk_o),
.phy_txd (eth_rgmii_tx_d_o),
.phy_tx_ctl (eth_rgmii_tx_en_o),
.phy_reset_n ( ), // Do not use rst_int for PHY reset
.phy_int_n ( ),
.phy_pme_n ( ),
.phy_mdc (eth_rgmii_mdc_o),
.phy_mdio_i (eth_mdio_i),
.phy_mdio_o (eth_mdio_o),
.phy_mdio_oe (eth_mdio_oe),
ethernet_pkg::eth_rgmii_rx_t eth_rgmii_rx;
ethernet_pkg::eth_rgmii_tx_t eth_rgmii_tx;
ethernet_pkg::eth_rgmii_mdio_in_t eth_mdio_in; // actually just an alias for logic but I like the consistent naming convention
ethernet_pkg::eth_rgmii_mdio_out_t eth_mdio_out;

// Interrupt out.
.eth_irq (ethernet_irq)
ethernet_top_axi #(
.TARGET ( "XILINX" ),
.axi_req_t ( top_pkg::axi_dev_req_t ),
.axi_rsp_t ( top_pkg::axi_dev_resp_t )
) ethernet_inst (
// Clocking and reset
.clk_125M_i (clk_125m_i), // Main clock - used by memory interface and as 125 MHz ethernet in-phase clock
.rst_ni (rst_eth_ni), // Main reset, deassertion synchronous to clk_125m_i
.clk_125M_quad_i (clk_125m_quad_i), // 125 MHz ethernet quadrature clock (used by MAC)
.clk_200M_i (clk_200m_i), // 200 MHz IDELAYCTRL reference clock
.axi_req_i (axi_125m_req), // Synchronous to clk_125M_i
.axi_rsp_o (axi_125m_rsp), // Synchronous to clk_125M_i
.eth_rgmii_rx_i (eth_rgmii_rx),
.eth_rgmii_tx_o (eth_rgmii_tx),
.eth_rgmii_mdio_i (eth_mdio_in),
.eth_rgmii_mdio_o (eth_mdio_out),
.ethernet_irq_o (ethernet_irq_125m),
.phy_reset_no (eth_phy_reset_no)
);

// MDIO bidirectional IO buffer
//////////////////////////
// RGMII signal mapping //
//////////////////////////
assign eth_rgmii_rx.clk = eth_rgmii_rx_clk_i;
assign eth_rgmii_rx.ctl = eth_rgmii_rx_ctl_i;
assign eth_rgmii_rx.d = eth_rgmii_rx_d_i;
assign eth_rgmii_tx_clk_o = eth_rgmii_tx.clk;
assign eth_rgmii_tx_en_o = eth_rgmii_tx.en;
assign eth_rgmii_tx_d_o = eth_rgmii_tx.d;

//////////////////////////////////
// MDIO bidirectional IO buffer //
//////////////////////////////////
IOBUF u_mdio_iobuf (
.O (eth_mdio_i), // Buffer output
.O (eth_mdio_in), // Buffer output
.IO (eth_rgmii_mdio_io), // Buffer inout port (connect directly to top-level port)
.I (eth_mdio_o), // Buffer input
.T (~eth_mdio_oe) // 3-state enable input, high=input, low=output
.I (eth_mdio_out.o), // Buffer input
.T (~eth_mdio_out.oen) // 3-state enable input, high=input, low=output
);
assign eth_rgmii_mdc_o = eth_mdio_out.c;

endmodule
35 changes: 0 additions & 35 deletions hw/vendor/ethernet.core
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4 changes: 2 additions & 2 deletions hw/vendor/ethernet.lock.hjson
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Expand Up @@ -8,7 +8,7 @@
{
upstream:
{
url: https://github.com/lowRISC/ariane-ethernet.git
rev: 1a14e8d98a0160f06e31e7a903082d0c8d293720
url: https://github.com/lowRISC/ethernet.git
rev: 2dc3a8b12da4006f343d6be82872dd80990cab6f
}
}
27 changes: 20 additions & 7 deletions hw/vendor/ethernet.vendor.hjson
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Expand Up @@ -2,13 +2,26 @@
// Licensed under the Apache License, Version 2.0, see LICENSE for details.
// SPDX-License-Identifier: Apache-2.0
{
name: "ethernet",
target_dir: "ethernet",
name: "ethernet",
target_dir: "ethernet",

upstream: {
url: "https://github.com/lowRISC/ariane-ethernet.git",
rev: "master",
},
upstream: {
url: "https://github.com/lowRISC/ethernet.git",
rev: "master",
},

exclude_from_upstream: []
# Only bring in the hardware, RDL, and README
# This excludes software, dev utilities, tests, and documentation
mapping: [
{from: "src/hw", to: "hw"},
{from: "src/ethernet.rdl", to: "ethernet.rdl"},
{from: "README.md", to: "README.md"}
],

exclude_from_upstream: [
"*.svg",
"*.md",
"*hw/*_eth/synth", # exclude trial synth flow
"*hw/*_eth/verif", # exclude verif
]
}
2 changes: 0 additions & 2 deletions hw/vendor/ethernet/.gitignore
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