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[fpga] Add clock constraints for SPI device #681

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[fpga] Add clock constraints for SPI device #681

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5 changes: 5 additions & 0 deletions hw/top_chip/data/placement_genesys2.xdc
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Original file line number Diff line number Diff line change
Expand Up @@ -5,3 +5,8 @@
## Ethernet MAC Placement Constraints
## Helps to pass timing reliably for a path with 2ns setup requirement
set_property LOC SLICE_X152Y75 [get_cells u_eth_wrapper/u_framing_top/rgmii_soc1/core_inst/eth_mac_inst/eth_mac_1g_rgmii_inst/rgmii_phy_if_inst/rgmii_tx_clk_2_reg]

## SPI Device Clock Buffer Placement Constraints
## Reduces clock skew to help pass timing
set_property LOC BUFR_X0Y6 [get_cells u_top_chip_system/u_spi_device/u_clk_spi_in_buf/gen_fpga_buf.gen_bufr.bufr_i]
set_property LOC BUFR_X0Y7 [get_cells u_top_chip_system/u_spi_device/u_clk_spi_out_buf/gen_fpga_buf.gen_bufr.bufr_i]
22 changes: 22 additions & 0 deletions hw/top_chip/data/timing_genesys2.xdc
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Expand Up @@ -38,3 +38,25 @@ set_clock_groups -asynchronous -group [get_clocks jtag_tck_pin];
set_max_delay -datapath_only 20 \
-from [get_pins -hierarchical -regexp .*/i_dmi_cdc/.*/data_wr_q_reg.*/C] \
-to [get_pins -hierarchical -regexp .*/i_dmi_cdc/.*/data_rd_q_reg.*/D]

## SPI Device Clock (Max 30 MHz)
create_clock -period 33.333 -waveform {0 16.667} -name spi_dev_sck_pin [get_ports spi_device_sck_i];

## SPI input and output clocks are driven by different BUFRs and should be treated as different clocks
create_generated_clock -name clk_spi_in -divide_by 1 -add \
-source [get_ports spi_device_sck_i] \
-master_clock [get_clocks spi_dev_sck_pin] \
[get_pins u_top_chip_system/u_spi_device/u_clk_spi_in_buf/gen_fpga_buf.gen_bufr.bufr_i/O]
create_generated_clock -name clk_spi_out -divide_by 1 -invert -add \
-source [get_ports spi_device_sck_i] \
-master_clock [get_clocks spi_dev_sck_pin] \
[get_pins u_top_chip_system/u_spi_device/u_clk_spi_out_buf/gen_fpga_buf.gen_bufr.bufr_i/O]

## SPI Device Clock asynchronous with all other clocks
set_clock_groups -asynchronous -group [get_clocks spi_dev_sck_pin -include_generated_clocks];

## SPI Device CSB pins is used for clocking (Max 15 MHz)
create_clock -period 66.667 -waveform {0 33.333} -name spi_dev_csb_pin [get_ports spi_device_csb_i];

## SPI Device CSB asynchronous with all other clocks
set_clock_groups -asynchronous -group [get_clocks spi_dev_csb_pin -include_generated_clocks];