[NFC][AMDGPU] Use brackets in decode-err.txt by shiltian · Pull Request #215148 · llvm/llvm-project

shiltian · 2026-08-09T20:46:46Z

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shiltian · 2026-08-09T20:46:46Z

This stack of pull requests is managed by sgh.

llvmorg-github-actions · 2026-08-09T20:47:22Z

@llvm/pr-subscribers-backend-amdgpu

Author: Shilei Tian (shiltian)

Changes

Full diff: https://github.com/llvm/llvm-project/pull/215148.diff

1 Files Affected:

(modified) llvm/test/MC/Disassembler/AMDGPU/decode-err.txt (+65-61)

diff --git a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
index e9537d1ec6c24..a849cbb334992 100644
--- a/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
+++ b/llvm/test/MC/Disassembler/AMDGPU/decode-err.txt
@@ -1,130 +1,134 @@
-# RUN: llvm-mc -triple=amdgpu9.00 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GCN-ERR %s
-# RUN: llvm-mc -triple=amdgpu9.50 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX950-ERR %s
-# RUN: llvm-mc -triple=amdgpu11.00 -disassemble -show-encoding < %s | FileCheck -check-prefixes=W32 %s
-# RUN: llvm-mc -triple=amdgpu11.00 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=W64 %s
-# RUN: llvm-mc -triple=amdgpu12.00 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s
-# RUN: llvm-mc -triple=amdgpu12.50 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX1250-ERR %s
+# RUN: not llvm-mc -triple=amdgpu9.00 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GCN-ERR %s
+# RUN: not llvm-mc -triple=amdgpu9.50 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX950-ERR %s
+# RUN: not llvm-mc -triple=amdgpu11.00 -disassemble -show-encoding < %s | FileCheck -check-prefixes=W32 %s
+# RUN: not llvm-mc -triple=amdgpu11.00 -mattr=+wavefrontsize64 -disassemble -show-encoding < %s 2>&1 | FileCheck -check-prefixes=W64 %s
+# RUN: not llvm-mc -triple=amdgpu12.00 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX12-ERR %s
+# RUN: not llvm-mc -triple=amdgpu12.50 -disassemble -filetype=null < %s 2>&1 | FileCheck -check-prefix=GFX1250-ERR %s
 
-# GCN-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xdf,0x00,0x00,0x02
+# Each encoding is bracketed so that it is decoded as an independent unit. An
+# encoding that is invalid for one of the targets above would otherwise consume
+# bytes from the following one and shift every subsequent encoding.
+
+# GCN-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xdf,0x00,0x00,0x02]
 
 # This is v_readfirstlane_b32 with an SGPR destination that does not fit the
 # 7-bit scalar register encoding of the 8-bit VOP1 vdst field.
-# GCN-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x05,0xf4,0x7f
+# GCN-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0x05,0xf4,0x7f]
 
 # This is v_s_exp_f32 with an SGPR destination that does not fit the 7-bit
 # scalar register encoding of the 8-bit VOP3 vdst field.
-# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xfa,0x00,0x80,0xd6,0x01,0x00,0x01,0x02
+# GFX12-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xfa,0x00,0x80,0xd6,0x01,0x00,0x01,0x02]
 
 # this is s_waitcnt_vscnt exec_hi, 0x1234, which is valid on gfx11, but not on gfx12
-# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x34,0x12,0x7f,0xbc
+# GFX12-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x34,0x12,0x7f,0xbc]
 
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xa0,0x4e,0x80,0xbe
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xa0,0x4e,0x80,0xbe]
 
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xc5,0x4e,0x80,0xbe
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xc5,0x4e,0x80,0xbe]
 
 # Literal constants are invalid for split barrier operands.
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xff,0x4e,0x80,0xbe,0xbe,0x00,0x00,0x00
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xff,0x4e,0x80,0xbe,0xbe,0x00,0x00,0x00]
 
 # src_private_base (237) and src_private_limit (238) are reserved on targets
 # with globally addressable scratch. Both the 32-bit and the 64-bit operand
 # forms are covered here.
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xed,0x0e,0x80,0xbe
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xed,0x0e,0x80,0xbe]
 
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xed,0x01,0xfe,0xbe
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xed,0x01,0xfe,0xbe]
 
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xee,0x0e,0x80,0xbe
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0x0e,0x80,0xbe]
 
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xee,0x01,0xfe,0xbe
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xee,0x01,0xfe,0xbe]
 
 # src_pops_exiting_wave_id (239) is only available on targets that support
 # POPS.
-# GFX12-ERR: [[@LINE+2]]:1: warning: invalid instruction encoding
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0xef,0x0c,0xbf
+# GFX12-ERR: [[@LINE+2]]:2: warning: invalid instruction encoding
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0xef,0x0c,0xbf]
 
 # src_vccz (251) and src_execz (252) are reserved on GFX11+.
-# GFX12-ERR: [[@LINE+2]]:1: warning: invalid instruction encoding
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xfb,0x0e,0x80,0xbe
+# GFX12-ERR: [[@LINE+2]]:2: warning: invalid instruction encoding
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xfb,0x0e,0x80,0xbe]
 
-# GFX12-ERR: [[@LINE+2]]:1: warning: invalid instruction encoding
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xfc,0x0e,0x80,0xbe
+# GFX12-ERR: [[@LINE+2]]:2: warning: invalid instruction encoding
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xfc,0x0e,0x80,0xbe]
 
 # W32: v_dual_add_f32 v5, 0xaf123456, v2 :: v_dual_fmaak_f32 v6, v3, v1, 0xaf123456 ; encoding: [0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
-# W64: [[@LINE+1]]:1: warning: invalid instruction encoding
-0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf
+# W64: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0xff,0x04,0x02,0xc9,0x03,0x03,0x06,0x05,0x56,0x34,0x12,0xaf]
 
 # GFX11: v_swap_b16 v5.h, s1/*Invalid register, operand has 'VGPR_16_Lo128' register class*/ ; encoding: [0x01,0xcc,0x0a,0x7f]
 # GFX12: v_swap_b16 v5.h, s1/*Invalid register, operand has 'VGPR_16_Lo128' register class*/ ; encoding: [0x01,0xcc,0x0a,0x7f]
-0x01,0xcc,0x0a,0x7f
+[0x01,0xcc,0x0a,0x7f]
 
 # GFX11: v_swap_b16 v5.h, 0x3c00/*Invalid immediate*/ ; encoding: [0x00,0xcc,0x0a,0x7f]
 # GFX12: v_swap_b16 v5.h, 0x3c00/*Invalid immediate*/ ; encoding: [0x00,0xcc,0x0a,0x7f]
-0xf2,0xcc,0x0a,0x7f
+[0xf2,0xcc,0x0a,0x7f]
 
 # GFX11: v_swap_b16 v5.h, 0x78563412/*Invalid immediate*/ ; encoding: [0x12,0xcc,0x0a,0x7f]
 # GFX12: v_swap_b16 v5.h, 0x78563412/*Invalid immediate*/ ; encoding: [0x12,0xcc,0x0a,0x7f]
-0xff,0xcc,0x0a,0x7f,0x12,0x34,0x56,0x78
+[0xff,0xcc,0x0a,0x7f,0x12,0x34,0x56,0x78]
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
-0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c
+[0x10,0x40,0x40,0xcc,0x00,0x11,0x42,0x1c]
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], 1.0/*Invalid immediate*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], 1.0/*Invalid immediate*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c # src0 1.0
+[0x10,0x40,0x40,0xcc,0xf2,0x10,0x42,0x1c] # src0 1.0
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:23] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/, v[8:15], v[16:19] ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c]
-0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c # src0 sgpr0
+[0x10,0x40,0x40,0xcc,0x00,0x10,0x42,0x1c] # src0 sgpr0
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], 1.0 ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b]
-0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b # src2 1.0
+[0x10,0x40,0x40,0xcc,0x00,0x11,0xca,0x1b] # src2 1.0
 
 # W32: v_wmma_f32_16x16x16_f16 v[16:23], v[0:7], v[8:15], s[0:7]/*Invalid register, operand has 'VReg_256' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
 # W64: v_wmma_f32_16x16x16_f16 v[16:19], v[0:7], v[8:15], s[0:3]/*Invalid register, operand has 'VReg_128' register class*/ ; encoding: [0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18]
-0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18 # src2 sgpr0
+[0x10,0x40,0x40,0xcc,0x00,0x11,0x02,0x18] # src2 sgpr0
 
 # this is ds_add_f32 with gds bit which is not valid on gfx12+
-# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00
+# GFX12-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0x00,0x56,0xd8,0x00,0x01,0x00,0x00]
 
 # this is image_msaa_load where samp field for gfx12 VSAMPLE is not all zeros
-# GFX12-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x06,0x00,0x46,0xe4,0x01,0x10,0x80,0x00,0x05,0x06,0x07,0x00
+# GFX12-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x06,0x00,0x46,0xe4,0x01,0x10,0x80,0x00,0x05,0x06,0x07,0x00]
 
 # This is ds_read_b32 with gds bit which is not valid on gfx90a.
-# GFX90A: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00
+# GFX90A: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0x00,0x6d,0xd8,0x01,0x00,0x00,0x00]
 
 # The f8f6f4 source tuples are narrowed down according to cbsz/blgp, but ttmp
 # registers have no 192-bit tuple.
-# GFX950-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0xae,0xd3,0x00,0xe9,0x00,0x64
+# GFX950-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0x00,0xae,0xd3,0x00,0xe9,0x00,0x64]
 
 # Same, except that the source selector is an inline constant, which is not a
 # register at all.
-# GFX950-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0xae,0xd3,0xf2,0x00,0x02,0x64
+# GFX950-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0x00,0xae,0xd3,0xf2,0x00,0x02,0x64]
 
 # The wmma source tuples are narrowed down according to the matrix formats, but
 # scalar registers have no 384-bit tuple.
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x18,0x33,0xcc,0x08,0x30,0xa2,0x04
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0x18,0x33,0xcc,0x08,0x30,0xa2,0x04]
 
 # This encoding references a missing trailing literal.
-# GFX1250-ERR: [[@LINE+1]]:1: warning: invalid instruction encoding
-0x00,0x00,0x33,0xcc,0xff,0x68,0x02,0x02
+# GFX1250-ERR: [[@LINE+1]]:2: warning: invalid instruction encoding
+[0x00,0x00,0x33,0xcc,0xff,0x68,0x02,0x02]

rampitec · 2026-08-09T22:13:16Z

I have previously caught couple pretty tricky bugs because we had no these brackets. What's the reason?

shiltian · 2026-08-10T02:08:03Z

I have previously caught couple pretty tricky bugs because we had no these brackets. What's the reason?

llvm-mc treats [...] as an atomic block. In this way, we can put more tests in one file; otherwise it depends on how errors are handled in llvm-mc. That's why the tests in https://github.com/llvm/llvm-project/pull/215147/changes#diff-ac80af65c2c09f49f96072e6e3e64e6ca9383827889ad985c51f616d5de06248R113 were added there instead of the end of the file.

shiltian · 2026-08-10T02:35:30Z

This is probably not needed after #215168. @rampitec Do you prefer that?

shiltian mentioned this pull request Aug 9, 2026

[AMDGPU][MC] Fix out-of-range MFMA tuple register-name assertion #215147

Merged

shiltian requested review from arsenm, broxigarchen and jayfoad August 9, 2026 20:46

llvmorg-github-actions Bot added the backend:AMDGPU label Aug 9, 2026

shiltian requested a review from rampitec August 9, 2026 20:47

arsenm approved these changes Aug 9, 2026

View reviewed changes

Base automatically changed from users/shiltian/fix-disam-out-of-range-mfma-tuple to main August 10, 2026 02:04

[NFC][AMDGPU] Use brackets in decode-err.txt

6c4c03b

shiltian force-pushed the users/shiltian/nfc-add-brackets-to-decode-err-test branch from c1119e9 to 6c4c03b Compare August 10, 2026 02:05

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[NFC][AMDGPU] Use brackets in decode-err.txt - #215148

[NFC][AMDGPU] Use brackets in decode-err.txt#215148
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