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[AMDGPU][MC] Return fail when it is not a VGPR in the decoder #215136

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[AMDGPU][MC] Return fail when it is not a VGPR in the decoder #215136

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8 changes: 8 additions & 0 deletions llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -265,6 +265,10 @@ static DecodeStatus decodeSrcReg9(MCInst &Inst, unsigned Imm,
template <unsigned OpWidth>
static DecodeStatus decodeSrcA9(MCInst &Inst, unsigned Imm, uint64_t /* Addr */,
const MCDisassembler *Decoder) {
// A clear Imm{8} names an SGPR or an inline constant, which this
// register-only operand cannot hold.
if (!(Imm & AMDGPU::EncValues::IS_VGPR))
return MCDisassembler::Fail;
return decodeSrcOp(Inst, 9, OpWidth, Imm, Imm | 512, Decoder);
}

Expand All @@ -274,6 +278,10 @@ template <unsigned OpWidth>
static DecodeStatus decodeSrcAV10(MCInst &Inst, unsigned Imm,
uint64_t /* Addr */,
const MCDisassembler *Decoder) {
// A clear Imm{8} names an SGPR or an inline constant, which this
// register-only operand cannot hold.
if (!(Imm & AMDGPU::EncValues::IS_VGPR))
return MCDisassembler::Fail;
return decodeSrcOp(Inst, 10, OpWidth, Imm, Imm, Decoder);
}

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26 changes: 26 additions & 0 deletions llvm/test/MC/Disassembler/AMDGPU/gfx9_dasm_mai_err.txt
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@@ -0,0 +1,26 @@
# NOTE: Assertions have been autogenerated by utils/update_mc_test_checks.py UTC_ARGS: --version 6
# RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx908 -disassemble -show-encoding < %s 2>&1 | FileCheck --implicit-check-not=warning: %s
# RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx90a -disassemble -show-encoding < %s 2>&1 | FileCheck --implicit-check-not=warning: %s
# RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx942 -disassemble -show-encoding < %s 2>&1 | FileCheck --implicit-check-not=warning: %s
# RUN: llvm-mc -triple=amdgcn-amd-amdhsa -mcpu=gfx950 -disassemble -show-encoding < %s 2>&1 | FileCheck --implicit-check-not=warning: %s

# The AV and AGPR source operands below only accept vector registers, so an
# encoding naming an SGPR or an inline constant must be rejected. -show-encoding
# is required: re-encoding the decoded instruction is what used to assert on the
# non-register operand.

# This is v_mfma_f32_16x16x1_4b_f32 with s0 as src0.
0x00,0x00,0xc1,0xd3,0x00,0x00,0x02,0x04
# CHECK: :[[@LINE-1]]:1: warning: invalid instruction encoding

# This is v_mfma_f32_16x16x1_4b_f32 with the inline constant 0 as src1.
0x00,0x00,0xc1,0xd3,0x00,0x01,0x01,0x04
# CHECK: :[[@LINE-1]]:1: warning: invalid instruction encoding

# This is v_accvgpr_read_b32 with s0 as src0.
0x02,0x40,0xd8,0xd3,0x00,0x00,0x00,0x18
# CHECK: :[[@LINE-1]]:1: warning: invalid instruction encoding

# This is v_accvgpr_read_b32 with the inline constant 0 as src0.
0x02,0x40,0xd8,0xd3,0x80,0x00,0x00,0x18
# CHECK: :[[@LINE-1]]:1: warning: invalid instruction encoding
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