Pinned Loading

1. SHA-256-Hardware-Accelerator SHA-256-Hardware-Accelerator Public

   A hardware SHA-256 hashing core in SystemVerilog as part of a Bitcoin style block hashing pipeline. Includes message scheduling, compression rounds, and control logic. Verified correctness using kn…

   SystemVerilog 1

2. 5-Stage-RISC-V-CPU-Core 5-Stage-RISC-V-CPU-Core Public

   5-stage RV32I SystemVerilog pipeline (IF/ID/EX/MEM/WB) with stall/flush logic, hazard detection, full forwarding, and memory-mapped I/O. Achieved 110 MHz Fmax and ~0.7 IPC. Implemented ALU, decoder…

   SystemVerilog

3. Mandarin-to-English-Transformer Mandarin-to-English-Transformer Public

   Neural machine translation model built with PyTorch. Includes data preprocessing, vocabulary construction, and training pipeline.

   Python

4. cf_ai_web_security_header_analyzer cf_ai_web_security_header_analyzer Public

   TypeScript

5. ETH-Sim ETH-Sim Public

   Fast dual-server price feed simulator for testing MEV bots and liquidation strategies with graph visualizer

   HTML