Vitis Unified Backend

MANIFEST.in

@@ -7,3 +7,4 @@ recursive-include hls4ml *.py
 recursive-include hls4ml/contrib *
 global-exclude .git .gitmodules .gitlab-ci.yml *.pyc
 include hls4ml/backends/vivado_accelerator/supported_boards.json
+include hls4ml/backends/vitis_unified/supported_boards.json

hls4ml/backends/__init__.py

@@ -13,11 +13,14 @@
 
 from hls4ml.backends.vitis.vitis_backend import VitisBackend  # isort: skip
 
+from hls4ml.backends.vitis_unified.vitis_unified_backend import VitisUnifiedBackend  # isort: skip
+
 
 def _register_builtin_backends():
     register_backend('Vivado', VivadoBackend)
     register_backend('VivadoAccelerator', VivadoAcceleratorBackend)
     register_backend('Vitis', VitisBackend)
+    register_backend('VitisUnified', VitisUnifiedBackend)
     register_backend('Quartus', QuartusBackend)
     register_backend('Catapult', CatapultBackend)
     register_backend('SymbolicExpression', SymbolicExpressionBackend)

hls4ml/backends/vitis_unified/passes/fifo_depth_optimization.py

@@ -0,0 +1,114 @@
+# we inherit it from vitis
+import re
+import zipfile
+
+from hls4ml.backends.vitis.passes.fifo_depth_optimization import (
+    generate_depths_file,
+    initialize_large_fifos,
+    set_optimized_fifo_depths,
+)
+from hls4ml.model.optimizer.optimizer import ConfigurableOptimizerPass, ModelOptimizerPass
+
+
+def get_vitis_optimized_fifo_depths(model, cus_hls_prj_path=None):
+    """Parse the files generated by the co-simulation to retrieve the optimized depths for the FIFOs.
+    Attention, only the FIFOs between the layers are profiled!
+
+    Args:
+        model (ModelGraph): The model to which FIFO depth optimization is applied.
+
+    Returns:
+        Dict[str, int]: A dictionary that contains the FIFO names as keys and the optimized depths as values.
+    """
+    # channel.zip is generated after the co-simulation and contains the chan_status*.csv files
+    # in the chan_status*.csv files the max depth achieved during co-simulation can be found at the last (4th) line
+
+    if cus_hls_prj_path is None:
+        cus_hls_prj_path = model.config.get_output_dir() + '/' + model.config.get_project_name() + '/_prj/solution1'
+
+    path_to_zip_file = cus_hls_prj_path + '/.autopilot/db/channel_depth_info/'
+
+    with zipfile.ZipFile(f'{path_to_zip_file}channel.zip', 'r') as zip_ref:
+        zip_ref.extractall(path_to_zip_file)
+
+    # the channel_info.csv file contains the mapping of each fifo name (i.e layer4_out_U) to the respective
+    # chan_status*.csv file
+    names_file_path = cus_hls_prj_path + '/.autopilot/db/channel_info.csv'
+
+    csv_fifo_depth_files = {}
+    with open(names_file_path) as names_file:
+        for line in names_file:
+            slitted_line = line.split(',')
+            if len(slitted_line[0]) == 0:
+                continue
+            layer_name = slitted_line[1]
+            csv_file_name = slitted_line[3][:-1]
+            csv_fifo_depth_files[layer_name] = csv_file_name
+
+    optmized_fifo_depths = {}
+    for layer_name, file_name in csv_fifo_depth_files.items():
+        with open(path_to_zip_file + file_name) as chan_status_file:
+            lines = chan_status_file.readlines()
+            cleaned_layer_name = re.sub(r'(_i)?_U$', '', layer_name)
+            optmized_fifo_depths[cleaned_layer_name] = int(
+                lines[-1]
+            )  # remove "_i_U" (axis) or "_U" (axim) from the layer name
+            # string and keep the last line of the file that contains the max depth
+
+    return optmized_fifo_depths
+
+
+def execute_cosim_to_profile_fifos(model):
+    model.write()
+    model.build(
+        reset=False,
+        csim=False,
+        synth=True,
+        cosim=False,
+        vsynth=False,
+        fifo_opt=True,
+        bitfile=False,
+        log_to_stdout=False,
+    )
+
+
+class FifoDepthOptimization(ConfigurableOptimizerPass, ModelOptimizerPass):
+    def __init__(self):
+        self.profiling_fifo_depth = 100_000
+
+    def transform(self, model):
+        """Perform FIFO depth optimization between the FIFOs of all layers to reduce resource utilization as the
+        initial FIFOs set by hls4ml might be larger than required. At the end of the optimization the FIFOs will
+        have the largest depths achieved during co-simulation without causing any deadlocks between the layers
+        (producer-consumer), thus no additional delays between the layers. In some cases, this optimization
+        might lead to bigger FIFOs than initially set by the hls4ml tool in order to prevent deadlocks.
+
+        Args:
+            model (ModelGraph): The model to which FIFO depth optimization is applied.
+
+        Raises:
+            ValueError: If the FIFO depth for profiling provided by the user is not a non-negative integer.
+            RuntimeError: If the IO type is not set to "io_stream".
+
+        Returns:
+            bool: The execution state of the Optimizer Pass
+        """
+
+        if not isinstance(self.profiling_fifo_depth, int) or self.profiling_fifo_depth <= 0:
+            raise ValueError('The FIFO depth for profiling (profiling_fifo_depth variable) must be a non-negative integer.')
+
+        # check axi-stream or io-stream
+        if not (model.config.get_config_value('IOType') == 'io_stream'):
+            raise RuntimeError('To use this optimization you have to set `IOType` field to `io_stream` in the HLS config.')
+
+        hlsPrjPath = model.config.backend.writer.get_vitis_hls_exec_dir(model)
+
+        initial_fifo_depths = initialize_large_fifos(model, self.profiling_fifo_depth)
+        execute_cosim_to_profile_fifos(model)
+        optimized_fifo_depths = get_vitis_optimized_fifo_depths(model, cus_hls_prj_path=hlsPrjPath + '/hls')
+        generate_depths_file(model, initial_fifo_depths, optimized_fifo_depths)
+        set_optimized_fifo_depths(model, optimized_fifo_depths)
+
+        print('FIFO optimization completed')
+
+        return False

hls4ml/backends/vitis_unified/supported_boards.json

@@ -0,0 +1,33 @@
+{
+  "zcu102": {
+    "part": "xczu9eg-ffvb1156-2-e",
+    "axi_master": {
+      "platform_file": "base_platforms/xilinx_zcu102_base_202320_1/xilinx_zcu102_base_202320_1.xpfm",
+      "python_driver": "axi_master_driver.py",
+      "c_drivers": ""
+    },
+    "axi_stream": {
+      "platform_generator_tcl": "zcu102/tcl_scripts/create_xsa.tcl",
+      "platform_output": "zcu102/tcl_scripts/output/zcu102_axi_stream_platform.xsa",
+      "python_driver": "axi_stream_driver.py",
+      "c_drivers": ""
+    }
+  },
+
+  "kv260": {
+    "part": "sk-kv260-g",
+    "axi_master": {
+      "platform_generator_tcl": "kv260/tcl_scripts/create_xsa.tcl",
+      "platform_output": "kv260/tcl_scripts/output/kv260_axi_all_platform.xsa",
+      "python_driver": "axi_master_driver.py",
+      "c_drivers": ""
+    },
+    "axi_stream": {
+      "platform_generator_tcl": "kv260/tcl_scripts/create_xsa.tcl",
+      "platform_output": "kv260/tcl_scripts/output/kv260_axi_all_platform.xsa",
+      "python_driver": "axi_stream_driver.py",
+      "c_drivers": ""
+    }
+  }
+
+}

hls4ml/backends/vitis_unified/vitis_unified_backend.py

@@ -0,0 +1,162 @@
+import os
+import subprocess
+import sys
+from shutil import copy2
+
+from hls4ml.backends import VitisBackend, VivadoBackend
+from hls4ml.model.flow import register_flow
+
+
+class VitisUnifiedBackend(VitisBackend):
+    def __init__(self):
+        super(VivadoBackend, self).__init__(name='VitisUnified')
+        self._register_layer_attributes()
+        self._register_flows()
+
+    def build(
+        self,
+        model,
+        reset=False,
+        csim=False,
+        synth=False,
+        cosim=False,
+        vsynth=False,
+        fifo_opt=False,
+        bitfile=False,
+        log_to_stdout=True,
+    ):
+        # it builds and return vivado reports
+        if 'linux' in sys.platform:
+            found = os.system('command -v v++ > /dev/null')
+            if found != 0:
+                raise Exception('Vitis installation not found. Make sure "vitis" is on PATH.')
+
+            found = os.system('command -v vitis-run > /dev/null')
+            if found != 0:
+                raise Exception('Vitis installation not found. Make sure "vitis-run" is on PATH.')
+
+        output_dir = model.config.get_output_dir()
+
+        hls_config_file = os.path.join(output_dir, 'hls_kernel_config.cfg')
+        # build command
+        csynth_cmd = ('v++ -c --mode hls --config {configPath} --work_dir vitis_unified_project').format(
+            configPath=hls_config_file
+        )
+        # util template (used in csim/cosim/package)
+        util_command = 'vitis-run --mode hls --{op} --config {configPath} --work_dir vitis_unified_project'
+
+        # command for each configuration
+        vitis_hls_dir = model.config.backend.writer.get_vitis_hls_dir(model)
+        package_cmd = util_command.format(op='package', configPath=hls_config_file)
+        cosim_cmd = util_command.format(op='cosim', configPath=hls_config_file)
+        csim_cmd = util_command.format(op='csim', configPath=hls_config_file)
+
+        kerlink_cmd = './link_system.sh'
+        kerlink_cwd = model.config.backend.writer.get_vitis_linker_dir(model)
+
+        commands = []
+        if synth:
+            self.prepare_sim_config_file(model, True)
+            commands.append(('csynth', csynth_cmd, vitis_hls_dir))
+            commands.append(('package', package_cmd, vitis_hls_dir))
+
+        if csim:
+            self.prepare_sim_config_file(model, True)
+            commands.append(('csim', csim_cmd, vitis_hls_dir))
+
+        if cosim or fifo_opt:
+            self.prepare_sim_config_file(model, False)
+            commands.append(('cosim', cosim_cmd, vitis_hls_dir))
+
+        if bitfile:
+            commands.append(('kerlink', kerlink_cmd, kerlink_cwd))
+
+        for task_name, command, cwd in commands:
+            stdout_log = os.path.join(output_dir, f'{task_name}_stdout.log')
+            stderr_log = os.path.join(output_dir, f'{task_name}_stderr.log')
+            stdout_target = None if log_to_stdout else open(stdout_log, 'w')
+            stderr_target = None if log_to_stdout else open(stderr_log, 'w')
+
+            try:
+                process = subprocess.Popen(
+                    command, shell=True, cwd=cwd, stdout=stdout_target, stderr=stderr_target, text=True
+                )
+                process.communicate()
+
+                if process.returncode != 0:
+                    raise Exception(f'Build failed for {model.config.get_project_name()} during task "{task_name}".')
+            finally:
+                if not log_to_stdout:
+                    stdout_target.close()
+                    stderr_target.close()
+
+    def prepare_sim_config_file(self, model, is_csim):
+        suffix = 'csim' if is_csim else 'cosim'
+        src = f'{model.config.get_output_dir()}/hls_kernel_config_{suffix}.cfg'
+        des = f'{model.config.get_output_dir()}/hls_kernel_config.cfg'
+        copy2(src, des)
+        return des
+
+    def create_initial_config(
+        self,
+        board='zcu102',
+        part=None,
+        clock_period=5,
+        clock_uncertainty='12.5%',
+        io_type='io_stream',
+        driver='python',
+        input_type='float',
+        output_type='float',
+        in_stream_buf_size=128,
+        out_stream_buf_size=128,
+        axi_mode='axi_master',
+        **_,
+    ):
+        supported_boards_path = os.path.join(os.path.dirname(__file__), 'supported_boards.json')
+        if os.path.exists(supported_boards_path):
+            import json
+
+            with open(supported_boards_path) as f:
+                supported_boards = json.load(f)
+            if board in supported_boards:
+                part = part or supported_boards[board]['part']
+        if part is None:
+            part = 'xczu9eg-ffvb1156-2-e'
+
+        config = super().create_initial_config(part, clock_period, clock_uncertainty, io_type)
+
+        config['VitisUnifiedConfig'] = {}
+        config['VitisUnifiedConfig']['Board'] = board
+        config['VitisUnifiedConfig']['axi_mode'] = axi_mode
+        config['VitisUnifiedConfig']['in_stream_buf_size'] = in_stream_buf_size
+        config['VitisUnifiedConfig']['out_stream_buf_size'] = out_stream_buf_size
+
+        config['VitisUnifiedConfig']['Driver'] = driver
+        config['VitisUnifiedConfig']['InputDtype'] = input_type  # float, double or ap_fixed<a,b>
+        config['VitisUnifiedConfig']['OutputDtype'] = output_type  # float, double or ap_fixed<a,b>
+
+        if io_type != 'io_stream':
+            raise Exception('io_type must be io_stream')
+        if input_type not in ['double', 'float']:
+            raise Exception('input_type must be float or double')
+        if output_type not in ['double', 'float']:
+            raise Exception('output_type must be float or double')
+
+        return config
+
+    def get_default_flow(self):
+        return self._default_flow
+
+    def get_writer_flow(self):
+        return self._writer_flow
+
+    def _register_flows(self):
+        vitis_ip = 'vitis:ip'
+        writer_passes = ['make_stamp', 'vitisunified:write_hls']
+        self._writer_flow = register_flow('write', writer_passes, requires=['vitis:ip'], backend=self.name)
+        self._default_flow = vitis_ip
+
+        # register fifo depth optimization
+        fifo_depth_opt_passes = ['vitisunified:fifo_depth_optimization'] + writer_passes
+
+        register_flow('fifo_depth_optimization', fifo_depth_opt_passes, requires=['vitis:ip'], backend=self.name)