fix(spi): take register block pointer via ptr() instead of regs()

esp-alloc/src/lib.rs

@@ -475,23 +475,19 @@ impl EspHeapInner {
         }
 
         cfg_select! {
-            feature = "internal-heap-stats" => {
-                HeapStats {
-                    region_stats,
-                    size: free + used,
-                    current_usage: used,
-                    max_usage: self.internal_heap_stats.max_usage,
-                    total_allocated: self.internal_heap_stats.total_allocated,
-                    total_freed: self.internal_heap_stats.total_freed,
-                }
-            }
-            _ => {
-                HeapStats {
-                    region_stats,
-                    size: free + used,
-                    current_usage: used,
-                }
-            }
+            feature = "internal-heap-stats" => HeapStats {
+                region_stats,
+                size: free + used,
+                current_usage: used,
+                max_usage: self.internal_heap_stats.max_usage,
+                total_allocated: self.internal_heap_stats.total_allocated,
+                total_freed: self.internal_heap_stats.total_freed,
+            },
+            _ => HeapStats {
+                region_stats,
+                size: free + used,
+                current_usage: used,
+            },
         }
     }
 

esp-bootloader-esp-idf/src/partitions.rs

@@ -350,9 +350,7 @@ impl<'a> PartitionTable<'a> {
         // See <https://github.com/espressif/esp-idf/blob/758939caecb16e5542b3adfba0bc85025517db45/components/hal/mmu_hal.c#L124>
         cfg_select! {
             feature = "esp32" => {
-                let paddr = unsafe {
-                    ((0x3FF10000 as *const u32).read_volatile() & 0xff) << 16
-                };
+                let paddr = unsafe { ((0x3FF10000 as *const u32).read_volatile() & 0xff) << 16 };
             }
             feature = "esp32s2" => {
                 let paddr = unsafe {
@@ -361,14 +359,10 @@ impl<'a> PartitionTable<'a> {
             }
             feature = "esp32s3" => {
                 // Revisit this once we support XiP from PSRAM for ESP32-S3
-                let paddr = unsafe {
-                    ((0x600C5000 as *const u32).read_volatile() & 0xff) << 16
-                };
+                let paddr = unsafe { ((0x600C5000 as *const u32).read_volatile() & 0xff) << 16 };
             }
             any(feature = "esp32c2", feature = "esp32c3") => {
-                let paddr = unsafe {
-                    ((0x600c5000 as *const u32).read_volatile() & 0xff) << 16
-                };
+                let paddr = unsafe { ((0x600c5000 as *const u32).read_volatile() & 0xff) << 16 };
             }
             feature = "esp32p4" => {
                 // DR_REG_FLASH_SPI0_BASE : 0x5008C000 = DR_REG_HPPERIPH0_BASE + 0x8C000
@@ -386,7 +380,12 @@ impl<'a> PartitionTable<'a> {
                     (((0x20500000 + 0x37c) as *const u32).read_volatile() & 0x7ff) << 16 // SPI_MEM_C_MMU_ITEM_CONTENT_REG
                 };
             }
-            any(feature = "esp32c5", feature = "esp32c6", feature = "esp32c61", feature = "esp32h2") => {
+            any(
+                feature = "esp32c5",
+                feature = "esp32c6",
+                feature = "esp32c61",
+                feature = "esp32h2"
+            ) => {
                 let paddr = unsafe {
                     ((0x60002000 + 0x380) as *mut u32).write_volatile(0);
                     (((0x60002000 + 0x37c) as *const u32).read_volatile() & 0xff) << 16

esp-hal/src/aes/mod.rs

@@ -203,12 +203,8 @@ impl<'d> Aes<'d> {
 
     fn is_idle(&mut self) -> bool {
         cfg_select! {
-            esp32 => {
-                self.regs().idle().read().idle().bit_is_set()
-            }
-            _ => {
-                self.regs().state().read().state().bits() == 0
-            }
+            esp32 => self.regs().idle().read().idle().bit_is_set(),
+            _ => self.regs().state().read().state().bits() == 0,
         }
     }
 

esp-hal/src/analog/adc/riscv.rs

@@ -567,12 +567,8 @@ pub(super) fn acquire_async_adc() {
 
 pub(super) fn release_async_adc() -> bool {
     cfg_select! {
-        all(adc_adc1, adc_adc2) => {
-            ASYNC_ADC_COUNT.fetch_sub(1, Ordering::Relaxed) == 1
-        }
-        _ => {
-            true
-        }
+        all(adc_adc1, adc_adc2) => ASYNC_ADC_COUNT.fetch_sub(1, Ordering::Relaxed) == 1,
+        _ => true,
     }
 }
 

esp-hal/src/clock/mod.rs

@@ -112,24 +112,12 @@ impl CpuClock {
     /// ```
     pub const fn max() -> Self {
         cfg_select! {
-            esp32c2 => {
-                Self::_120MHz
-            }
-            any(esp32c3, esp32c6, esp32c61) => {
-                Self::_160MHz
-            }
-            esp32h2 => {
-                Self::_96MHz
-            }
-            esp32p4 => {
-                Self::_400MHz
-            }
-            esp32s31 => {
-                Self::_320MHz
-            }
-            _ => {
-                Self::_240MHz
-            }
+            esp32c2 => Self::_120MHz,
+            any(esp32c3, esp32c6, esp32c61) => Self::_160MHz,
+            esp32h2 => Self::_96MHz,
+            esp32p4 => Self::_400MHz,
+            esp32s31 => Self::_320MHz,
+            _ => Self::_240MHz,
         }
     }
 }
@@ -335,7 +323,8 @@ impl RtcClock {
         // Make sure we measure the crystal.
         cfg_select! {
             soc_has_clock_node_timg_function_clock => {
-                let current_function_clock = clocks::TimgInstance::Timg0.function_clock_config(clocks);
+                let current_function_clock =
+                    clocks::TimgInstance::Timg0.function_clock_config(clocks);
                 clocks::TimgInstance::Timg0.configure_function_clock(clocks, function_clock);
                 clocks::TimgInstance::Timg0.request_function_clock(clocks);
             }

esp-hal/src/debugger.rs

@@ -3,20 +3,14 @@
 /// Checks if a debugger is connected.
 pub fn debugger_connected() -> bool {
     cfg_select! {
-        xtensa => {
-            xtensa_lx::is_debugger_attached()
-        }
-        all(riscv, soc_has_assist_debug) => {
-            crate::peripherals::ASSIST_DEBUG::regs()
-                .cpu(0)
-                .debug_mode()
-                .read()
-                .debug_module_active()
-                .bit_is_set()
-        }
-        _ => {
-            false
-        }
+        xtensa => xtensa_lx::is_debugger_attached(),
+        all(riscv, soc_has_assist_debug) => crate::peripherals::ASSIST_DEBUG::regs()
+            .cpu(0)
+            .debug_mode()
+            .read()
+            .debug_module_active()
+            .bit_is_set(),
+        _ => false,
     }
 }
 
@@ -50,9 +44,9 @@ pub unsafe fn set_stack_watchpoint(addr: usize) {
                     );
                 }
             }
-            _ => {
-                unsafe { set_watchpoint(0, addr, 4); }
-            }
+            _ => unsafe {
+                set_watchpoint(0, addr, 4);
+            },
         }
     }
 }

esp-hal/src/dma/aligned.rs

@@ -85,11 +85,13 @@ pub(crate) fn region_dma_alignment(addr: usize) -> Option<usize> {
     #[cfg(dma_can_access_psram)]
     if is_valid_psram_address(addr) {
         return Some(cfg_select! {
-            // TODO(esp32p4): PSRAM is cached through the L2 cache, whose line size is
-            // configurable (64 or 128 bytes) and is not encoded anywhere yet. Assume the
-            // larger, always-safe value until the L2 line size is available.
+            // TODO(esp32p4): PSRAM is cached through the L2 cache,
+            // whose line size is configurable (64 or 128
+            // bytes) and is not encoded anywhere yet. Assume the
+            // larger, always-safe value until the L2 line size is
+            // available.
             soc_internal_memory_cached => 128,
-            any(esp32, esp32c5, esp32c61) => 32, // TODO: fixed 32-bytes, metadata-ify
+            any(esp32, esp32c5, esp32c61) => 32, /* TODO: fixed 32-bytes, metadata-ify */
             _ => crate::soc::CONFIG_DATA_CACHE_LINE_SIZE,
         });
     }

esp-hal/src/dma/buffers/mod.rs

@@ -325,7 +325,10 @@ impl BurstConfig {
             dma_can_access_psram => {
                 let mut alignment = alignment;
                 if is_valid_psram_address(_buffer.as_ptr() as usize) {
-                    alignment = max(alignment, self.external_memory.min_psram_alignment(direction));
+                    alignment = max(
+                        alignment,
+                        self.external_memory.min_psram_alignment(direction),
+                    );
                 }
             }
             _ => {}
@@ -1997,15 +2000,13 @@ pub(crate) unsafe fn prepare_for_rx(
     let data_len = if data_in_psram {
         cfg_select! {
             dma_can_access_psram => {
-                // This could use a better API, but right now we'll have to build the descriptor list by
-                // hand.
-                let consumed_bytes = build_descriptor_list_for_psram(
-                    &mut descriptors,
-                    align_buffers,
-                    data,
-                );
+                // This could use a better API, but right now we'll have to build the descriptor
+                // list by hand.
+                let consumed_bytes =
+                    build_descriptor_list_for_psram(&mut descriptors, align_buffers, data);
 
-                // Invalidate data written by the DMA. As this likely affects more data than we touched, write back first.
+                // Invalidate data written by the DMA. As this likely affects more data than we
+                // touched, write back first.
                 unsafe {
                     crate::soc::cache_writeback_addr(data_addr as u32, consumed_bytes as u32);
                     crate::soc::cache_invalidate_addr(data_addr as u32, consumed_bytes as u32);

esp-hal/src/dma/engine/axi_gdma.rs

@@ -559,7 +559,7 @@ fn init_axi_dma_racey() {
                 .write(|w| unsafe { w.access_extr_mem_start_addr().bits(0x4000_0000) });
             regs.extr_mem_end_addr()
                 .write(|w| unsafe { w.access_extr_mem_end_addr().bits(0x53FF_FFFF) });
-        },
+        }
         _ => {
             regs.intr_mem_start_addr()
                 .write(|w| unsafe { w.access_intr_mem_start_addr().bits(0x4FC0_0000) });

esp-hal/src/dma/engine/gdma/ahb_v1.rs

@@ -113,12 +113,18 @@ impl RegisterAccess for AhbGdmaTxChannel<'_> {
 impl TxRegisterAccess for AhbGdmaTxChannel<'_> {
     fn is_fifo_empty(&self) -> bool {
         cfg_select! {
-            esp32s3 => {
-                 self.ch().outfifo_status().read().outfifo_empty_l3().bit_is_set()
-            }
-            _ => {
-                 self.ch().outfifo_status().read().outfifo_empty().bit_is_set()
-            }
+            esp32s3 => self
+                .ch()
+                .outfifo_status()
+                .read()
+                .outfifo_empty_l3()
+                .bit_is_set(),
+            _ => self
+                .ch()
+                .outfifo_status()
+                .read()
+                .outfifo_empty()
+                .bit_is_set(),
         }
     }
 
@@ -220,12 +226,12 @@ impl InterruptAccess<DmaTxInterrupt> for AhbGdmaTxChannel<'_> {
 
     fn is_async(&self) -> bool {
         cfg_select! {
-            any(esp32c2, esp32c3) => {
-                self.0.state.tx_is_async.load(portable_atomic::Ordering::Acquire)
-            }
-            _ => {
-                true
-            }
+            any(esp32c2, esp32c3) => self
+                .0
+                .state
+                .tx_is_async
+                .load(portable_atomic::Ordering::Acquire),
+            _ => true,
         }
     }
 
@@ -447,12 +453,12 @@ impl InterruptAccess<DmaRxInterrupt> for AhbGdmaRxChannel<'_> {
 
     fn is_async(&self) -> bool {
         cfg_select! {
-            any(esp32c2, esp32c3) => {
-                self.0.state.rx_is_async.load(portable_atomic::Ordering::Acquire)
-            }
-            _ => {
-                true
-            }
+            any(esp32c2, esp32c3) => self
+                .0
+                .state
+                .rx_is_async
+                .load(portable_atomic::Ordering::Acquire),
+            _ => true,
         }
     }
 

esp-hal/src/dma/engine/i2s.rs

@@ -149,12 +149,8 @@ impl RegisterAccess for I2sDmaTxChannel<'_> {
 impl TxRegisterAccess for I2sDmaTxChannel<'_> {
     fn is_fifo_empty(&self) -> bool {
         cfg_select! {
-            esp32 => {
-                self.regs().lc_state0().read().bits() & 0x80000000 != 0
-            }
-            _ => {
-                self.regs().lc_state0().read().out_empty().bit_is_set()
-            }
+            esp32 => self.regs().lc_state0().read().bits() & 0x80000000 != 0,
+            _ => self.regs().lc_state0().read().out_empty().bit_is_set(),
         }
     }
 

esp-hal/src/dma/engine/spi.rs

@@ -161,12 +161,13 @@ impl RegisterAccess for SpiDmaTxChannel<'_> {
 impl TxRegisterAccess for SpiDmaTxChannel<'_> {
     fn is_fifo_empty(&self) -> bool {
         cfg_select! {
-            esp32 => {
-                self.regs().dma_rstatus().read().dma_out_status().bits() & 0x80000000 != 0
-            }
-            _ => {
-                self.regs().dma_outstatus().read().dma_outfifo_empty().bit_is_set()
-            }
+            esp32 => self.regs().dma_rstatus().read().dma_out_status().bits() & 0x80000000 != 0,
+            _ => self
+                .regs()
+                .dma_outstatus()
+                .read()
+                .dma_outfifo_empty()
+                .bit_is_set(),
         }
     }
 

esp-hal/src/ecc.rs

@@ -619,34 +619,22 @@ impl Info {
 
     fn qx_mem(&self) -> *mut u32 {
         cfg_select! {
-            ecc_separate_jacobian_point_memory => {
-                self.regs.qx_mem(0).as_ptr()
-            }
-            _ => {
-                self.regs.px_mem(0).as_ptr()
-            }
+            ecc_separate_jacobian_point_memory => self.regs.qx_mem(0).as_ptr(),
+            _ => self.regs.px_mem(0).as_ptr(),
         }
     }
 
     fn qy_mem(&self) -> *mut u32 {
         cfg_select! {
-            ecc_separate_jacobian_point_memory => {
-                self.regs.qy_mem(0).as_ptr()
-            }
-            _ => {
-                self.regs.py_mem(0).as_ptr()
-            }
+            ecc_separate_jacobian_point_memory => self.regs.qy_mem(0).as_ptr(),
+            _ => self.regs.py_mem(0).as_ptr(),
         }
     }
 
     fn qz_mem(&self) -> *mut u32 {
         cfg_select! {
-            ecc_separate_jacobian_point_memory => {
-                self.regs.qz_mem(0).as_ptr()
-            }
-            _ => {
-                self.regs.k_mem(0).as_ptr()
-            }
+            ecc_separate_jacobian_point_memory => self.regs.qz_mem(0).as_ptr(),
+            _ => self.regs.k_mem(0).as_ptr(),
         }
     }