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Verilog: preserve genvars while elaborating module instances - #2067

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kroening wants to merge 2 commits into
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kroening:dk-logikbench-output-part-selects
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kroening wants to merge 2 commits into
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kroening:dk-logikbench-output-part-selects

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@kroening kroening commented Aug 9, 2026

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This fixes LogikBench failures caused by genvars being dropped while elaborating parameterized module instances.

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kroening marked this pull request as draft August 9, 2026 18:41
This extracts the code that turns the data in verilog_set_genvarst into a
map into a method.
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kroening force-pushed the dk-logikbench-output-part-selects branch from 320affc to c36f819 Compare August 11, 2026 02:15
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kroening force-pushed the dk-logikbench-output-part-selects branch from c36f819 to 5e2c45a Compare August 11, 2026 08:54
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kroening marked this pull request as ready for review August 11, 2026 08:55
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