Do not review - #2064

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kroening wants to merge 21 commits into

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Commits on Aug 21, 2026

extract verilog_set_genvarst::build_map()
kroening
committed
1765a5e
Verilog: tests for array-typed parameters
kroening
committed
a96ef5a
Verilog: accept struct/array/union as constant expressions
kroening
committed
9a7d0df
Verilog: fold Verilog-specific constructs when propagating constants in synthesis

kroening
and
claude
committed
b2bd912
Verilog: don't treat 'integer' loop counters as driver conflicts

kroening
and
claude
committed
d40b745
Support reading source files from .f command files
kroening
committed
bba8bb8
Verilog: modport selection in interface port connections
kroening
committed
15ad839
Verilog: virtual interface declarations
kroening
committed
87ffbd3
Verilog: parameterized interface port connections
kroening
committed
a25c333
fixup KNOWNBUG tests
kroening
committed
0bc378e
Verilog: interface ports no longer depend on declaration order
kroening
committed
7f750ad
Verilog: arrays of interface ports
kroening
committed
13b95ec
Verilog: parse packages before the files that import them
kroening
committed
ad84e35
Verilog: elaborate library files
kroening
committed
ea515d5
Verilog: arrays of interface ports
kroening
committed
8b98b8e
Verilog: simulation time system functions
kroening
committed
5d2f570
Verilog: loop-local genvar scoping
kroening
committed
b0c4bcf
Verilog: loop-local genvars take precedence over enclosing scopes
kroening
committed
4c7cfb5
Verilog: genvars while elaborating module instances
kroening
committed
77168d3
Verilog: generate-inst3 is now a CORE test
kroening
committed
71920f3
Verilog: test for a genvar-indexed output port connection
kroening
committed
7900e88

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Do not review - #2064

Do not review#2064
kroening wants to merge 21 commits into
mainfrom
dk

Commits on Aug 21, 2026

extract verilog_set_genvarst::build_map()

Verilog: tests for array-typed parameters

Verilog: accept struct/array/union as constant expressions

Verilog: fold Verilog-specific constructs when propagating constants in synthesis

Verilog: don't treat 'integer' loop counters as driver conflicts

Support reading source files from .f command files

Verilog: modport selection in interface port connections

Verilog: virtual interface declarations

Verilog: parameterized interface port connections

fixup KNOWNBUG tests

Verilog: interface ports no longer depend on declaration order

Verilog: arrays of interface ports

Verilog: parse packages before the files that import them

Verilog: elaborate library files

Verilog: arrays of interface ports

Verilog: simulation time system functions

Verilog: loop-local genvar scoping

Verilog: loop-local genvars take precedence over enclosing scopes

Verilog: genvars while elaborating module instances

Verilog: generate-inst3 is now a CORE test

Verilog: test for a genvar-indexed output port connection