drivers/touch/cst816: take the i2c lock around the hardware reset - #2042
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cst816_hw_reset toggles the chip's reset pin with no synchronisation against the bus: touch_sensor_set_enabled is reached synchronously from arbitrary tasks (subscribe/unsubscribe callbacks, the backlight and system-hold toggles) and calls the reset as its first statement, while the system task may be mid-transfer inside prv_read_data clocking the same chip. A chip hit by reset mid-byte stops ACKing and corrupts the in-flight transfer. Take s_i2c_lock inside cst816_hw_reset, the same per-transfer lock the read/write paths use. No caller holds it already -- the only lock-takers are prv_read_data and prv_write_data, neither of which resets -- so the acquisition cannot self-deadlock, and the bootmode/fw-update sequences keep their existing per-operation interleaving. Not unit-testable: the driver has no test target (it sits on real I2C, GPIO and EXTI), and the race is a cross-task timing window against hardware. Validated by call-site audit and a full firmware build. Co-Authored-By: Claude <noreply@anthropic.com> Signed-off-by: Joseph Mearman <joseph@mearman.co.uk> Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
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Supersedes #1896 (originally by @Mearman) with review feedback applied: the verbose inline comment explaining the race is dropped, since the same rationale is already in the commit message.
cst816_hw_reset toggles the chip's reset pin with no synchronisation against the bus: touch_sensor_set_enabled is reached synchronously from arbitrary tasks (subscribe/unsubscribe callbacks, the backlight and system-hold toggles) and calls the reset as its first statement, while the system task may be mid-transfer inside prv_read_data clocking the same chip. A chip hit by reset mid-byte stops ACKing and corrupts the in-flight transfer.
This takes s_i2c_lock inside cst816_hw_reset, the same per-transfer lock the read/write paths use. No caller holds it already, so the acquisition cannot self-deadlock, and the bootmode/fw-update sequences keep their existing per-operation interleaving.
No unit test: the driver has no test target (it sits on real I2C, GPIO and EXTI) and the race is a cross-task timing window against hardware.
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