[EXTERNAL][AMDGPU] Fold constant offset into SV form addressing in SVS

[bogdan-petkovic]

Motivation

Padded attention kernels that use the double-buffer direct-to-LDS schedule produce NaNs on gfx950. The root cause is an AMDGPU backend miscompile, not an MLIR codegen issue. This PR backports the upstream LLVM fix so those configurations are numerically correct on gfx950 and no MLIR-side workaround (gating double-buffer to single-buffer when padding is present) is needed.

Technical Details

Clean backport of two upstream llvm/llvm-project commits (external subtree only):

• [AMDGPU] Fold constant offset into SV form addressing in SVS frame index fallback llvm/llvm-project#208629 — 5f371b2add3e [AMDGPU] Fold constant offset into SV form addressing in SVS (the fix)
• [NFC][AMDGPU] Simplify scratch address materialization in SVS frame index fallback llvm/llvm-project#208624 — 6ce86d47ca09 [NFC][AMDGPU] Simplify scratch address materialization in SVS (prerequisite refactor + test)
  Under extreme VGPR pressure (~512), the double-buffer direct-to-LDS schedule hit a bad frame-index elimination for the flat-scratch SVS (scalar+vector+scalar) addressing form: the constant offset was not correctly folded/materialized into the scavenged vaddr VGPR, producing wrong scratch addresses and NaNs. The fix folds as much of the constant offset as possible into the instruction's immediate offset field and materializes the remainder (plus the frame register, if any) into the scavenged VGPR.
  Files touched: external/llvm-project/llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp and the added upstream regression test external/llvm-project/llvm/test/CodeGen/AMDGPU/eliminate-frame-index-flat-scratch-svs.mir.

Test Plan

Built a standalone O0-vs-O3 reproducer of the failing gfx950 padded-attention kernel (extracted LLVM IR + HIP harness), run against the June LLVM bump with and without this patch. The upstream .mir regression test (eliminate-frame-index-flat-scratch-svs.mir) is also included and runs as part of the LLVM test suite.

Test Result

• Without the patch the O3 build diverges from the O0 baseline and emits NaNs (FAIL). With the patch applied, O3 matches O0 and the reproducer passes 3/3. The added upstream .mir test passes.
• Weekly CI (parameterSweeps)
• Nightly CI
• PR CI

Submission Checklist

• Look over the contributing guidelines at https://github.com/ROCm/ROCm/blob/develop/CONTRIBUTING.md#pull-requests.

[codecov]

Codecov Report

✅ All modified and coverable lines are covered by tests.

Additional details and impacted files

@@             Coverage Diff             @@
##           develop    #2435      +/-   ##
===========================================
+ Coverage    82.57%   83.65%   +1.08%     
===========================================
  Files          120      120              
  Lines        42852    42933      +81     
  Branches      7110     7139      +29     
===========================================
+ Hits         35381    35912     +531     
+ Misses        4815     4487     -328     
+ Partials      2656     2534     -122     

Flag	Coverage Δ
gfx120x	83.46% <ø> (+0.94%)	⬆️
gfx950	83.36% <ø> (+1.02%)	⬆️
mfma	83.37% <ø> (?)

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see 33 files with indirect coverage changes

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[umangyadav]

Make sure to run nightly CI too