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[Ascend] Port T.Parallel ST suite (SV/CF/SP) onto pto-dev - #2
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Tree-copy examples/ascend/st_simtvf_parallel from Wenbo tip 3828bbcf onto PTO-ISA pto-dev (3d70ede). Adapt imports to tilelang.ascend.language and harness SimtVF FFI; document CANN MicroAPI opsim blocker on pto-b10.
Co-authored-by: peanutchan <peanutchan@users.noreply.github.com>
peanutchan
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SP4d walks every expert row and zeros pad holes with a full-lane vsel. SP5d sideband gathers V and Sf; interleave gathers one Pack slot then splits the scale tail. Oneshot, README, and SUMMARY now list 21+21. VF numbers for the new twins stay TODO. Co-authored-by: peanutchan <peanutchan@users.noreply.github.com>
SP4d pad25 VF=265 (1.98us); SP5d sideband VF=583 (1.87us), interleave VF=699 (1.94us). All PASS maxabs=0 on tip fa8ffee.
KurrinQu
reviewed
Oct 9, 2026
| out_ub = T.alloc_shared((E,), "float32") | ||
| T.copy(A, s) | ||
| T.copy(Thresh, thr_ub) | ||
| with T.SimtVF(threads=threads): |
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目前kernels是SimtVF形态，我们最终验证的路径是SimdVF→PTO，入库前是否需要调整成SimdVF？
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同意最终验证路径是 SimdVF→PTO，但入库前不打算把整套 T.Parallel ST 直接改成只留 SimdVF。
计划是：同一套 T.Parallel case 通过环境变量切换 T.SimtVF / T.SimdVF（例如 ST_VF_MODE=simt|simd），再跑 regress 汇总各 case PASS/FAIL（哪些 SimdVF 已通、哪些还挂）。现有 kernels_ptodsl/*d（手写 PTO-DSL）仍保留，作为 sensitivity 对照，不是替代这条开关路径。
正在往本 PR 分支落地。
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| ```bash | ||
| # Env (typical pto-b10 paths) | ||
| export ASCEND_HOME_PATH=/mnt/fluxdata/Ascend/cann_91b3/cann-9.1.0-beta.3 |
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已参数化：oneshot / harness 通过 PY、ASCEND_HOME_PATH、TILELANG_DEPS 等环境变量取值，未设置则直接报错退出（见 tip 1006caa）。
README 里仍有一段 pto-b10 示例绝对路径；按你的意见会再清掉，只保留占位符说明，不再写死 /mnt/fluxdata/Ascend/...。
Oneshots and harnesses take PY, ASCEND_HOME_PATH, and the existing dependency prefixes from the environment so a reviewer can run the suite without editing pto-b10 lab paths. Co-authored-by: Cursor Agent <cursoragent@cursor.com> Co-authored-by: peanutchan <peanutchan@users.noreply.github.com>
Keep one T.Parallel source for the Ascend ST kernels and choose the VF frame from ST_VF_MODE. Add a simt/simd PASS/FAIL regress and drop checked-in lab absolute paths from the suite README. Co-authored-by: Cursor Agent <cursoragent@cursor.com> Co-authored-by: peanutchan <peanutchan@users.noreply.github.com>
ST_VF_MODE now chooses SimtVF or SimdVF and compile target ascend or pto. simt and simd stay as aliases for the ascend modes. The VF-mode regress runs all four by default and records PASS/FAIL, including a PTO compile failure, without remapping that compile to ascend. Co-authored-by: Cursor Agent <cursoragent@cursor.com> Co-authored-by: peanutchan <peanutchan@users.noreply.github.com>
Document tested versions and live VF-mode rollup (simt-asc 56/61, simt-pto 33/61, simd-pto 0/61; keep alloc_fragment). README + SUMMARY only; no kernel changes.
jimmychou0
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Oct 12, 2026
Per review: the example came in only as an import dependency of test_simdvf_vecadd_pto_run.py from the ported vectorize commit. Element-wise device coverage stays with the self-contained test_vectorize_parallel_pto_run.py (vecadd 1D/2D, tail masks, casts, auto-schedule kept enabled); the element-wise example from PR PTO-ISA#2 (t_parallel_st_suite sv1) becomes the canonical showcase once that suite lands.
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Summary
Ascend SimtVF sensitivity suite at
examples/ascend/t_parallel_st_suiteon PTO-ISA/tilelangpto-dev.3828bbcfpto-dev@3d70ede9Reviewer links
Primary metric in SUMMARY/deck: total VF cycles (Simt
T.Parallelvs best SIMD (PTO-DSL) schedule).Live VF-mode regress (cann_92b2 + PTOAS nightly 0.67, 2026-10-10)
Four-way
ST_VF_MODEswitch is on this tip (simt-asc/simt-pto/simd-asc/simd-pto). Live arms:/mnt/fluxdata/Ascend/cann_92b2/cann-9.2.0-beta.2(Ascend-cann-toolkit 9.2.0-beta.2)314834389d0e0472629702827ddf4d0b1aa5f740onfeat/st-simtvf-parallel-sv1-sv9(basepto-dev@3d70ede9)ptoas0.67 in.camodel_deps_nightly067— not CANN-bundled PTOAS; not the older camodelptoas-vmi 0.1.8(that stack was 0/61 on simt-pto via missingpto.max)ST_VF_MODE/mnt/fluxdata/happybot/st_out_cann92b2_20261010_104824. MicroAPI wall cleared vs cann_91b3. Residuals:sv4 remat_idx(eval_vec_), sv6/sv7 harness alias rows. VF vs Wenbo:/mnt/fluxdata/happybot/WENBO_VS_CANN92B2_SIMT_ASC_VF_20261010.md/mnt/fluxdata/happybot/st_out_nightly067_simt_pto_20261010_170837· tableVF_MODE_PASS_TABLE.txt. Was 0/61 on ptoas-vmi 0.1.8 (pto.max). Remaining FAIL compile: f16→f32EmitInlineSimtVF(~11), sv4 keep_idxllvm.store(~8), SV9 store arity (~3),eval_vec_/ SP5 / SP3 e8m0. VF vs Wenbo + simt-asc:/mnt/fluxdata/happybot/NIGHTLY067_SIMT_PTO_VS_BASELINES_20261010.md/mnt/fluxdata/happybot/st_out_simd_pto_20261010_163238(and SV1 recheck under nightly067). All FAIL compile. Dominant:Unsupported storage scope in PTO pointer emission: localfrom STT.alloc_fragment→ RF/localunder SimdVF→PTO (codegen_pto.cc). Decision: keep fragment RF as-is (do not rewrite kernels to shared-only); simd-pto needs a TileLang codegen fix forlocal/ SimdVF→PTO. Nightly 0.67 does not unblock SV1 here.kernels_ptodsl/(hand-written SIMD PTO-DSL) unchanged — SUMMARY SIMD VF numbers still come from that path.Test case PASS / FAIL (opsim Ascend950PR_9599)
Status key: PASS = compile + camodel gold OK on recorded tip.
Simt / most SIMD VF: Wenbo tip
3828bbcf(2026-10-07–08). Historical note: Simt oneshots oncann_91b3/92b1hit missing CANN MicroAPI; cleared on cann_92b2 forsimt-asc(see Live VF-mode section above).Exception (live on this tip): SP4d / SP5d SIMD PASS @
fa8ffeeb(2026-10-08).SV1–SV9
CF1–CF6
SP1–SP6
Rollup
Adaptations (examples only)
import tilelang.language as T→import tilelang.ascend.language as Tcommon_asc_harness.patch_simtvf_ffiuses stock Ascend 3-argSimtVF(no missingtilelang.language.vf)TILELANG_DEPSoverride for in-treelibtilelang.soNo broad
src// compiler patches. ST kernels keepT.alloc_fragment(RF/local) — shared-only rewrite is out of scope; simd-pto unblock is codegen.Test plan
simt-ptoon PTOAS nightly 0.67 — 33/61 PASS (was 0/61 on 0.1.8)oneshot_ptodsl_sp1d_sp6d.shrefresh on this tip.39gold=got when reachablesimd-ptoVF-mode regress — 0/61 PASS (localstorage scope / SimdVF→PTO; keepalloc_fragment)simd-ascVF-mode regress on cann_92b2