Simplify memory and loop control scenario benches

[zhoubot]

Replace expanded conditional forests in the memory-banks and loop-control system benches with immutable typed scenario Tables using existing source constructs. Memory shrinks from 4,848 to 545 lines; loop control from 4,520 to 706 lines. DUTs, drivers, oracles, configuration, cycle counts and timeouts remain unchanged; no compiler or API change.

Preserve every original field value, full-u64 clamp/tail/wrap and rule-registration order. Memory retains all five bitwise expected-valid response masks: invalid payload assertions are neither strengthened nor weakened, and logs remain unconditional. Its frozen terminal expectations are preserved without claiming they describe later physical outputs. Loop retains all repeated final rows and expected_ready=0 in the tail. Refresh verified module receipts and navigation.

Validation:

• Independent proofs cover memory’s 8,360 values / 223 full-domain intervals and loop’s 6,350 values / 373 intervals. Full frozen-AST comparison preserves assertion operators/targets/messages, masks, logs, advance logic, imports, declarations and registrations; 14 memory and 12 loop mutations are rejected.
• All five focused CTests pass: memory module/system 2/2; loop module/system/four-state 3/3. Memory retains 883 module samples and 10,560 system observations; loop retains 1,272 known / 19,458 XZ module samples and 6,350 system observations. Native workers 1/2, Verilator and loop’s genuine Icarus checks remain.
• Eight source-import/transformed stage records reproduce published units byte-for-byte. Twenty complete traces per example agree, excluding only changed AST site/registration metadata. Measured/public runs use identical final IR and every generated output.
• Catalog tests 19/19, changed-file pre-commit and strict docs pass.

This is an authoring/frontend improvement with backend costs. Bench compilation falls 6.70→3.46 s for memory and 4.42→2.07 s for loop. Three alternating paired warm native runs show medians 2.069→2.199 s (+6.3%) and 1.760→1.902 s (+8.1%). Generated C++ grows 21.8% / 26.6%; RTL grows 3.8% / 8.3%; both final IR sizes decrease. RTL runtime is approximately unchanged. README tables disclose all costs and the limited same-machine LLVM 22 / -O0 measurement scope.

The existing C++ emitter reconstructs constant table field planes during Work. Proven constant-plane materialization is a separate generic optimization follow-up in #265; no future speedup is assumed for this acceptance. Full catalog/nightly/platform coverage, arbitrary injected X/Z phase equivalence and simulated u64 rollover are not claimed. Remaining migration stays in #272. Proof tools, intermediate experiments, reviews and raw candidate-bound evidence remain ignored under docs/gates/logs/memory-loop-benches-20261010/; tests do not depend on those files.

[zhoubot]

Final candidate 0322c547adbea981a6825d5d34afc04a5e5f28d5: independent code review APPROVE, architecture CLEAR, both required GitHub checks passed. Implementation, independent tests and review used separate instances.

Both full-domain preservation proofs, 26 rejected mutations, five focused gates, eight stage records and twenty matching traces per example are verified. The independent reviewer checked 261 gate input hashes and execution receipts. An initial proof-tool structural gap was repaired before acceptance; final tools compare complete frozen normalized check/advance ASTs, masks, logs and registrations.

READMEs disclose native runtime regressions 6.30%/8.05% and generated-file growth. This is a bounded authoring/frontend improvement, not an overall performance improvement. Constant-plane materialization remains a separate generic emitter task with independent design/tests; acceptance assumes no future speedup. No full nightly, arbitrary X/Z phase equivalence or simulated u64 rollover claim.