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[doc] Remove SBSA reference #1559

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c74a8fe
docs
kuqin12 Jun 7, 2026
00aa8f0
core/patina_debugger/README.md
kuqin12 Jun 7, 2026
c8cc0b9
components/patina_smbios/README.md
kuqin12 Jun 7, 2026
0faf7d7
core/patina_stacktrace/
kuqin12 Jun 7, 2026
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7 changes: 3 additions & 4 deletions components/patina_smbios/README.md
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Expand Up @@ -98,10 +98,9 @@ Only SMBIOS 3.x versions are supported.

If you want to develop your own Patina-based platform SMBIOS component, remove
your platform's existing SMBIOS driver (e.g., `SmbiosPlatformDxe`,
`SbsaQemuSmbiosDxe`, `ProcessorSubClassDxe`) from your DSC and FDF files, then
create a platform-specific component that populates your SMBIOS tables. This
component uses the `#[component]` macro and receives the `Smbios` service as a
parameter:
`ProcessorSubClassDxe`) from your DSC and FDF files, then create a
platform-specific component that populates your SMBIOS tables. This component
uses the `#[component]` macro and receives the `Smbios` service as a parameter:

```rust
use patina::component::{component, service::Service};
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2 changes: 1 addition & 1 deletion core/patina_debugger/README.md
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Expand Up @@ -62,7 +62,7 @@ In addition, active examples are available in the
- [QEMU Q35](https://github.com/OpenDevicePartnership/patina-dxe-core-qemu/blob/main/bin/q35_dxe_core.rs)
- Intel platform with serial debug over UART 16550 with I/O port access

- [QEMU SBSA](https://github.com/OpenDevicePartnership/patina-dxe-core-qemu/blob/main/bin/sbsa_dxe_core.rs)
- [QEMU ArmVirt](https://github.com/OpenDevicePartnership/patina-dxe-core-qemu/blob/main/bin/arm_virt_dxe_core.rs)
- AArch64 platform with serial debug over UART PL011 with MMIO access

## Feature flags
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44 changes: 22 additions & 22 deletions core/patina_stacktrace/README.md
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6 changes: 3 additions & 3 deletions core/patina_stacktrace/src/aarch64/runtime_function.rs
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Expand Up @@ -228,12 +228,12 @@
// and retry the lookup. This ensures that we correctly resolve
// unwind data even when the return address falls inside such
// synthetic code.
// qemu_sbsa_dxe_core!patina_samples::component::hello_world::func3:
// qemu_armvirt_dxe_core!patina_samples::component::hello_world::func3:

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Unknown word (armvirt)
// 00000100`0006aebc f81f0ffe str lr,[sp,#-0x10]!
// 00000100`0006aec0 d100c3ff sub sp,sp,#0x30
// ....
// 00000100`0006aeec 97fffb26 bl qemu_sbsa_dxe_core!core::panicking::panic_fmt (00000100`00069b84)
// qemu_sbsa_dxe_core!weak.default._ZN118_$LT$$u5b$core..mem..maybe_uninit..MaybeUninit$LT$T$GT$$u5d$$u20$as$u20$core..array..iter..iter_inner..PartialDrop$GT$12partial_drop17hc3d15e0976616072E:
// 00000100`0006aeec 97fffb26 bl qemu_armvirt_dxe_core!core::panicking::panic_fmt (00000100`00069b84)

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Unknown word (armvirt)
// qemu_armvirt_dxe_core!weak.default._ZN118_$LT$$u5b$core..mem..maybe_uninit..MaybeUninit$LT$T$GT$$u5d$$u20$as$u20$core..array..iter..iter_inner..PartialDrop$GT$12partial_drop17hc3d15e0976616072E:

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Unknown word (armvirt)
// 00000100`0006aef0 d37cedf0 lsl xip0,x15,#4
// 00000100`0006aef4 910003f1 mov xip1,sp
// 00000100`0006aef8 d1400631 sub xip1,xip1,#1,lsl #0xC
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16 changes: 8 additions & 8 deletions core/patina_stacktrace/src/lib.rs
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Expand Up @@ -125,15 +125,15 @@
//! /// # Child-SP Return Address Call Site
//! /// 0 0000010078885D50 000001007AB12770 Shell+66ED0
//! /// 1 0000010078885E90 0000010007B98DCC Shell+6770
//! /// 2 0000010078885FF0 0000010007B98E54 qemu_sbsa_dxe_core+18DCC
//! /// 3 0000010007FFF4C0 0000010007B98F48 qemu_sbsa_dxe_core+18E54
//! /// 4 0000010007FFF800 000001007AF54D08 qemu_sbsa_dxe_core+18F48
//! /// 2 0000010078885FF0 0000010007B98E54 qemu_armvirt_dxe_core+18DCC

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Unknown word (armvirt)

@kuqin12 kuqin12 Jun 7, 2026

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This needs double checking.

//! /// 3 0000010007FFF4C0 0000010007B98F48 qemu_armvirt_dxe_core+18E54

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Unknown word (armvirt)
//! /// 4 0000010007FFF800 000001007AF54D08 qemu_armvirt_dxe_core+18F48
//! /// 5 0000010007FFFA90 0000010007BAC388 BdsDxe+8D08
//! /// 6 0000010007FFFF80 0000000010008878 qemu_sbsa_dxe_core+2C388 --.
//! /// |
//! /// 0:000> u qemu_sbsa_dxe_core!patina_dxe_core::call_bds |
//! /// 00000000`1002c1b0 f81f0ff3 str x19,[sp,#-0x10]! |
//! /// 00000000`1002c1b4 f90007fe str lr,[sp,#8] <---------------------------'
//! /// 6 0000010007FFFF80 0000000010008878 qemu_armvirt_dxe_core+2C388 --.
//! /// |
//! /// 0:000> u qemu_armvirt_dxe_core!patina_dxe_core::call_bds |
//! /// 00000000`1002c1b0 f81f0ff3 str x19,[sp,#-0x10]! |
//! /// 00000000`1002c1b4 f90007fe str lr,[sp,#8] <------------------------------'
//! /// 00000000`1002c1b8 d10183ff sub sp,sp,#0x60
//! ///
//! /// The FP is not saved, so the return address in frame #6 is garbage.
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16 changes: 8 additions & 8 deletions core/patina_stacktrace/src/stacktrace.rs
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Expand Up @@ -218,15 +218,15 @@ impl StackTrace {
/// # Child-SP Return Address Call Site
/// 0 0000010078885D50 000001007AB12770 Shell+66ED0
/// 1 0000010078885E90 0000010007B98DCC Shell+6770
/// 2 0000010078885FF0 0000010007B98E54 qemu_sbsa_dxe_core+18DCC
/// 3 0000010007FFF4C0 0000010007B98F48 qemu_sbsa_dxe_core+18E54
/// 4 0000010007FFF800 000001007AF54D08 qemu_sbsa_dxe_core+18F48
/// 2 0000010078885FF0 0000010007B98E54 qemu_armvirt_dxe_core+18DCC
/// 3 0000010007FFF4C0 0000010007B98F48 qemu_armvirt_dxe_core+18E54
/// 4 0000010007FFF800 000001007AF54D08 qemu_armvirt_dxe_core+18F48
/// 5 0000010007FFFA90 0000010007BAC388 BdsDxe+8D08
/// 6 0000010007FFFF80 0000000010008878 qemu_sbsa_dxe_core+2C388 --.
/// |
/// 0:000> u qemu_sbsa_dxe_core!patina_dxe_core::call_bds |
/// 00000000`1002c1b0 f81f0ff3 str x19,[sp,#-0x10]! |
/// 00000000`1002c1b4 f90007fe str lr,[sp,#8] <---------------------------'
/// 6 0000010007FFFF80 0000000010008878 qemu_armvirt_dxe_core+2C388 --.
/// |
/// 0:000> u qemu_armvirt_dxe_core!patina_dxe_core::call_bds |
/// 00000000`1002c1b0 f81f0ff3 str x19,[sp,#-0x10]! |
/// 00000000`1002c1b4 f90007fe str lr,[sp,#8] <------------------------------'
/// 00000000`1002c1b8 d10183ff sub sp,sp,#0x60
///
/// The FP is not saved, so the return address in frame #6 is garbage.
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6 changes: 3 additions & 3 deletions docs/src/dev/testing/qemu_pr_validation.md
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Expand Up @@ -46,7 +46,7 @@ The workflow relies on several repositories and components:
| Platform | Host Operating System | Architecture |
|:---------|:----------------------|:-------------|
| Q35 | Linux | x86_64 |
| SBSA | Linux | aarch64 |
| ArmVirt | Linux | aarch64 |
| Q35 | Windows | x86_64 |

At any given time, a subset of these platforms may be disabled due to known issues or maintenance work. The PR comment
Expand Down Expand Up @@ -123,15 +123,15 @@ The workflow is organized into the following jobs:
```mermaid
flowchart TD
N["Post In-Progress Notification Comment"] --> P["Preflight Checks"]
P -->|Ready| L["Validate QEMU (Linux): Q35 + SBSA"]
P -->|Ready| L["Validate QEMU (Linux): Q35 + ArmVirt"]
P -->|Ready| W["Validate QEMU (Windows): Q35"]
L --> M["Emit PR Metadata (Transfer State)"]
W --> M
M --> Post["Post-Processing Workflow"]
```

The Linux and Windows jobs run in parallel. Additionally, a matrix is used within the Linux job to further parallelize
validation across the Q35 and SBSA platforms.
validation across the Q35 and ArmVirt platforms.

While full support is available for building and running on Linux and Windows hosts, there is not a significant
advantage for doing so from a Patina firmware validation perspective. It may be decided to focus on Linux hosts in the
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6 changes: 3 additions & 3 deletions docs/src/integrate/dxe_core.md
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Expand Up @@ -121,14 +121,14 @@ Reference: [q35_dxe_core.rs](https://github.com/OpenDevicePartnership/patina-dxe

### For AARCH64 Platforms

Copy the SBSA reference implementation:
Copy the ArmVirt reference implementation:

```txt
> mkdir -p bin
> cp <path-to-patina-dxe-core-qemu>/bin/sbsa_dxe_core.rs bin/platform_patina_dxe_core.rs
> cp <path-to-patina-dxe-core-qemu>/bin/arm_virt_dxe_core.rs bin/platform_patina_dxe_core.rs
```

Reference: [sbsa_dxe_core.rs](https://github.com/OpenDevicePartnership/patina-dxe-core-qemu/blob/main/bin/sbsa_dxe_core.rs)
Reference: [arm_virt_dxe_core.rs](https://github.com/OpenDevicePartnership/patina-dxe-core-qemu/blob/main/bin/arm_virt_dxe_core.rs)

> While the QEMU Patina DXE Core implementations provide a good starting point, you need to modify the copied file to
> suit your platform's specific requirements.
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2 changes: 1 addition & 1 deletion docs/src/introduction.md
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Expand Up @@ -100,7 +100,7 @@ flowchart TD
| [patina-fw-patcher](https://github.com/OpenDevicePartnership/patina-fw-patcher) | A developer tool to quickly patch a new patina-dxe-core binary into a platform's firmware |
| [patina-mtrr](https://github.com/OpenDevicePartnership/patina-mtrr) | A x86_64 MTRR solution we believe is generic enough to be useful outside of Patina. |
| [patina-paging](https://github.com/OpenDevicePartnership/patina-paging) | A paging solution we believe is generic enough to be useful outside of Patina. |
| [patina-qemu](https://github.com/OpenDevicePartnership/patina-qemu/) | Two reference virtual platforms (Q35, SBSA) |
| [patina-qemu](https://github.com/OpenDevicePartnership/patina-qemu/) | Two reference virtual platforms (Q35, ArmVirt) |
| [patina-readiness-tool](https://github.com/OpenDevicePartnership/patina-readiness-tool) | A DXE core replacement binary that reviews HOBs passed from PEI to DXE to validate your platform is ready to use the Patina DXE Core. |
| [patina](https://github.com/OpenDevicePartnership/patina) | Core codebase for Patina containing Patina-only crates. |
<!-- markdownlint-enable MD013 -->
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2 changes: 1 addition & 1 deletion docs/src/patina.md
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Expand Up @@ -180,7 +180,7 @@ definition but many of the services are still implemented in C so it is orange.
#### Notable DXE Core Features

- AARCH64 and x86/64 support.
- Support for QEMU (Q35 and SBSA).
- Support for QEMU (Q35 and ArmVirt).
- Tested and developed on physical Intel and Arm hardware.
- Boots to Windows and Linux on these platforms.
- Performance record (FBPT) support.
Expand Down
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