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Implement the exact PTO ISA 0.57.1 Tile transaction contract - #42
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The emulator decoded an incomplete legacy surface and exposed descriptor, capacity, ACC, and source-lifetime effects before legality was known. Import the exact 761-form ISA map, implement canonical 98/9/13 identities, and route Tile commit through fail-closed preflight, dry-run, snapshot, and publication gates with real CPULinxState atomicity evidence. Constraint: Generic or retired Tile decodes must never alias a canonical 0.57.1 operation Rejected: Materialize outputs during B.IOT append | later legality faults would leak architectural state Rejected: Throw from TEPL dry-run arithmetic | longjmp would bypass snapshot restoration Confidence: high Scope-risk: broad Directive: Keep all faultable Tile legality ahead of publication and extend transaction tests for every new state effect Tested: linx32/linx64 builds; 728/728 mnemonics and 761/761 forms; exact 98/9/13 inventory; 20 Python tests; 9 transaction subtests; 11 PTO-Kernel CTests; opcode metadata sync; git diff check Not-tested: non-S32 CUBE hardware numeric conformance, explicitly tracked as unproven
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added 4 commits
July 31, 2026 03:46
Execute every ordinary and microscaled matrix type through a shared production core, preserve implicit ACC transactionally, and make ACCCVT rounding, saturation, NaN, signed-zero, and packed-lane behavior deterministic with QEMU SoftFloat. Constraint: PTO-ISA/pto-spec 0141ec89 is the sole normative source and freezes 24 ordinary rows, 8 MX ordered pairs, and 75 canonical numeric vectors. Rejected: Host fma/nearbyint implementation | architectural results changed with the host floating-point environment. Rejected: Shared-header vector tests alone | they did not exercise CPULinxState publication, shape metadata, or production fault behavior. Confidence: high Scope-risk: broad Directive: Keep CUBE and ACCCVT arithmetic in tile_cube_057.c and extend the native production test whenever the numeric profile changes. Tested: linx32+linx64 system builds; production numeric 9/9; transaction 9/9; v0.57 Python 19/19 including 75/75 canonical vectors; external PTO 11/11; checkpatch; git diff --check; three independent review rounds Not-tested: one guest assembly program for every individual 24 ordinary and 8 MX combination; production-core matrix tests cover all combinations directly
PTO ISA 0.57.1 carries TSTORE's extent in the bound source Tile rather than an output-size field. Resolve the frozen binding once through a shared contract so preflight and execution derive the same exact allocation size and reject noncanonical size-bearing descriptors. Constraint: PTO-ISA/pto-spec 0141ec89 defines TSTORE operands as address plus source0 only Rejected: Increase the AVS timeout | masks deterministic illegal-trap replay Rejected: Accept absent descriptor size as zero | rejects every canonical TSTORE Confidence: high Scope-risk: narrow Reversibility: clean Directive: Keep TSTORE transfer extent derived from the frozen source Tile; do not add a pseudo destination size Tested: linx32 and linx64 system builds; CUBE numeric 9/9; transaction 10/10; v0.57 Python 19/19; external PTO 11/11; focused AVS test 0x1701 PASS; checkpatch; git diff --check; independent code review Not-tested: full deepseek suite is blocked by workload S32 unary THISTOGRAM contrary to pto-spec; all-suites is blocked by missing mamulb catalog entry
TCVT preflight now validates the source logical rows, columns, and stride without requiring its physical carrier row count to equal the destination carrier, allowing the frozen FP32-to-INT8 conversion while retaining precise insufficient-shape rejection. Constraint: Packed and width-changing conversions keep logical shape even when source and destination storage footprints differ. Rejected: Bypass TCVT preflight entirely | Logical source coverage must still be checked before publication. Confidence: high Scope-risk: moderate Directive: Conversion legality compares logical extents; never infer equality from physical carrier rows across DataTypes. Tested: qemu-system-linx64 incremental build; tile transaction unit suite 11/11 including accept/reject carrier-shape regression. Not-tested: Full numeric, transaction, and superproject QEMU gates rerun after repinning.
TEPL scalar operations now resolve their operand directly from B.IOR in both 32-bit and 64-bit execution and preflight, removing the retired B.ARG mode dependency that silently turned TDIVS into a zero-valued unary fallback. Constraint: PTO ISA 0.57.1 has no executable legacy Tile descriptor header or scalar B.ARG selector. Rejected: Reintroduce B.ARG in compiler output | The locked operation schema plus B.IOR is authoritative. Confidence: high Scope-risk: broad Directive: Determine scalar versus Tile arity from the canonical operation schema; never gate it on tile_arg_format. Tested: qemu-system-linx64 incremental build; Tile transaction suite 11/11; full DeepSeek AVS suite passes within the fixed 10-second bound. Not-tested: Clean recursive build and full superproject QEMU contract rerun after repinning.
This was referenced Jul 30, 2026
zhoubot
marked this pull request as ready for review
August 2, 2026 12:09
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Caution The consumer version of Gemini Code Assist on GitHub has been sunset. All code review activity has officially ceased. |
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Summary
Depends on PTO-ISA/pto-spec#19, LinxISA/linx-isa#161, and LinxISA/PTO-Kernel#10.
Validation
git diff --checkCanonical numeric vector hash:
b9f908deb9cfec412388e95f4532563cf4e462032b43d15996f0f7b4b93b4ec9.Final merged-source refresh (2026-08-02)