Upgrade the Linx ISA projection to PTO 0.57.1

avs/compiler/linx-llvm/tests/analyze_coverage.py

@@ -75,19 +75,11 @@ def canonicalize_mnemonic(mnemonic: str) -> str:
 def derived_selector_mnemonics(mnemonic: str, operands: list[str]) -> Set[str]:
     """Recover strict current-profile aliases from selector-style objdump output."""
     selector = canonicalize_mnemonic(mnemonic)
-    if selector == "B.DATR":
-        return {"B.ARG"}
     if not operands:
         return set()
 
     tileop = canonicalize_mnemonic(operands[0])
     aliases = {
-        ("BSTART.CUBE", "ACCCVT"): "BSTART.ACCCVT",
-        ("BSTART.CUBE", "TMATMUL"): "BSTART.TMATMUL",
-        ("BSTART.CUBE", "TMATMUL.ACC"): "BSTART.TMATMUL.ACC",
-        ("BSTART.TMA", "TLOAD"): "BSTART.TLOAD",
-        ("BSTART.TMA", "TSTORE"): "BSTART.TSTORE",
-        ("BSTART.TMA", "TMOV"): "BSTART.TMOV",
         ("BSTART.TEPL", "ERCOV"): "ERCOV",
         ("BSTART.TEPL", "ESAVE"): "ESAVE",
     }
@@ -166,6 +158,13 @@ def map_emitted_to_spec(emitted_mnem: str, spec_mnemonics: Set[str]) -> Optional
         return None
     if cur in spec_mnemonics:
         return cur
+    # TEPL has one raw carrier form in the architectural catalog while the
+    # disassembler prints the selected direct operation (for example,
+    # BSTART.TDIVS).  Those friendly spellings are execution evidence for the
+    # BSTART.TEPL carrier, not for the unrelated generic BSTART form reached by
+    # suffix stripping.
+    if cur.startswith("BSTART.T") and "BSTART.TEPL" in spec_mnemonics:
+        return "BSTART.TEPL"
     while "." in cur:
         cur = cur.rsplit(".", 1)[0]
         if cur in spec_mnemonics:

avs/compiler/linx-llvm/tests/asm/41_v057_isa_forms.s

@@ -1,11 +1,9 @@
 .text
 v057_isa_forms:
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.DIM sp, 129, ->lb1
     B.IOR [sp,sp,sp],[a0]
     BSTART.ACCCVT FP32
-    BSTART.CUBE 3, FP32
-    BSTART.FIXP 31, FP32
     BSTART.TLOAD FP32
     BSTART.TSTORE FP32
     BSTART.TMATMUL FP16

avs/compiler/linx-llvm/tests/c/32_descriptor_marker.c

@@ -1,5 +1,5 @@
-// Emit a canonical B.ARG descriptor header opcode so mnemonic coverage includes
-// descriptor-only metadata instructions in strict v0.57.
-void emit_barg_marker(void) {
-  __asm__ volatile(".long 0x180221a3" ::: "memory");
+// Emit canonical B.DATR NORM/FP32/Zero defaults so mnemonic coverage includes
+// descriptor-only metadata instructions in strict v0.57.1.
+void emit_bdatr_marker(void) {
+  __asm__ volatile(".long 0x00001023" ::: "memory");
 }

avs/compiler/linx-llvm/tests/gen_disasm_vectors.py

@@ -47,7 +47,23 @@ def _field_width(field: dict[str, object]) -> int:
 def _default_field_value(field_name: str, width: int, mnemonic: str) -> int:
     lower = field_name.lower()
     upper_mnemonic = mnemonic.upper()
-    if width > 5:
+    frame_template = upper_mnemonic in {
+        "FENTRY",
+        "FEXIT",
+        "FRET.RA",
+        "FRET.STK",
+    }
+    if lower in {"dstbegin", "dstend"} and frame_template:
+        # Architectural RA is register encoding 10 in frame-template range
+        # syntax; arbitrary register 1 is not a legal single-register restore
+        # range for these forms.
+        value = 10
+    elif lower == "uimm" and frame_template:
+        # Frame templates require an aligned, range-compatible stack size.
+        # The generic wide-field seed (129) encodes as 128 after the implicit
+        # low three zero bits and is illegal for a one-register range.
+        value = 8
+    elif width > 5:
         if lower == "regdst":
             value = (4 << 5) | 1  # vt#1
         elif lower == "srcl":

avs/compiler/linx-llvm/tests/neg/tepl_tileop_range.s

@@ -1,3 +1,3 @@
     .text
 bad_tepl:
-    BSTART.TEPL 1024, FP16
+    BSTART.TEPL 4, 0, FP16

avs/compiler/linx-llvm/tests/run.sh

@@ -285,12 +285,10 @@ if [[ -d "$ASM_DIR" ]]; then
         python3 "$ROOT/check_required_mnemonics.py" \
           --objdump "$OUT/$BASE.objdump" \
           --label "$BASE" \
-          --require B.ARG \
+          --require B.DATR \
           --require B.DIM \
           --require B.IOR \
           --require BSTART.ACCCVT \
-          --require BSTART.CUBE \
-          --require BSTART.FIXP \
           --require BSTART.TLOAD \
           --require BSTART.TMATMUL \
           --require BSTART.TMATMUL.ACC \
@@ -392,8 +390,8 @@ if [[ -d "$NEG_DIR" ]]; then
     echo "error: TEPL range negative test unexpectedly assembled" >&2
     exit 1
   fi
-  if ! grep -Eq "TileOp10 must be in range 0\\.\\.1023|TileOpcode must be in range 0\\.\\.1023|Match Instruction Error!" "$NEG_OUT/tepl_tileop_range.err"; then
-    echo "error: TEPL range negative test did not report a range/match failure" >&2
+  if ! grep -Eq "BSTART\\.TEPL requires Mode 0\\.\\.3 and Function 0\\.\\.31|Match Instruction Error!" "$NEG_OUT/tepl_tileop_range.err"; then
+    echo "error: TEPL range negative test did not report the Mode/Function range failure" >&2
     cat "$NEG_OUT/tepl_tileop_range.err" >&2
     exit 1
   fi

avs/compiler/linx-llvm/tests/test_analyze_coverage.py

@@ -15,6 +15,12 @@
 coverage = importlib.util.module_from_spec(SPEC)
 SPEC.loader.exec_module(coverage)
 
+VECTOR_SCRIPT = Path(__file__).with_name("gen_disasm_vectors.py")
+VECTOR_SPEC = importlib.util.spec_from_file_location("gen_disasm_vectors", VECTOR_SCRIPT)
+assert VECTOR_SPEC and VECTOR_SPEC.loader
+vectors = importlib.util.module_from_spec(VECTOR_SPEC)
+VECTOR_SPEC.loader.exec_module(vectors)
+
 
 class AnalyzeCoverageTest(unittest.TestCase):
     def write_spec(self, root: Path, *mnemonics: str) -> Path:
@@ -159,6 +165,28 @@ def test_grouped_encoding_words_are_skipped_before_mnemonic(self) -> None:
             self.assertEqual(report["covered_spec_mnemonics"], 1)
             self.assertEqual(report["unmapped_emitted_mnemonics"], [])
 
+    def test_tepl_friendly_alias_covers_raw_carrier_not_generic_bstart(self) -> None:
+        with tempfile.TemporaryDirectory() as temp:
+            root = Path(temp)
+            spec_data = coverage.load_isa_spec(
+                self.write_spec(root, "BSTART", "BSTART.TEPL")
+            )
+            self.write_objdump(root / "out", "tepl", "BSTART.TDIVS")
+
+            report = coverage.analyze_coverage(spec_data, root / "out")
+
+            self.assertEqual(report["covered_spec_mnemonics"], 1)
+            self.assertEqual(report["missing_mnemonics"], ["BSTART"])
+            self.assertEqual(report["mapped_by_test"]["tepl"], ["BSTART.TEPL"])
+
+    def test_frame_vector_seed_uses_legal_minimum_stack_size(self) -> None:
+        for mnemonic in ("FENTRY", "FEXIT", "FRET.RA", "FRET.STK"):
+            self.assertEqual(
+                vectors._default_field_value("DstBegin", 5, mnemonic), 10
+            )
+            self.assertEqual(vectors._default_field_value("DstEnd", 5, mnemonic), 10)
+            self.assertEqual(vectors._default_field_value("uimm", 12, mnemonic), 8)
+
     def test_fail_under_returns_two_for_incomplete_observed_coverage(self) -> None:
         with tempfile.TemporaryDirectory() as temp:
             root = Path(temp)