Raising: privatize lane-local scratch - #2996
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A thread-private array inside the lane-batched parallel was modeled as one shared buffer; a store whose index map does not involve the lane axes looks uniform, so every lane read back lane zero's value (mfem's dynamic 2D grad kernels accumulate grad[3] in a per-thread array and produced frozen derivatives). Give the buffer one leading dimension per lane axis and index every access with the lane IVs. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_016zErYp7upmqr4NHfhod9UD
The 65k-element budget silently skipped mfem's 3D register-blocked kernels' per-lane tensors (24x24 lanes x 126 registers): the un-privatized scratch raised as a single shared tensor and every lane read the wrong values, while the statically-specialized instantiations that never hit the budget were exact. Raise the budget to 4M elements. Also rewrite the lit test to use affine loops only so it runs on this branch without the scf.for raising. Co-Authored-By: Claude Fable 5 <noreply@anthropic.com> Claude-Session: https://claude.ai/code/session_016zErYp7upmqr4NHfhod9UD
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Pushed two fixes found running the MFEM suite end-to-end:
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A thread-private array inside the lane-batched parallel (mfem's
real_t grad[3]accumulators in the dynamic 2D grad kernels) was modeled as one shared buffer. A store whose index map does not involve the lane axes looks uniform to the raising, so every lane read back lane zero's value — QuadratureInterpolator's tensor PhysDerivatives froze the qy axis (caught via a PJRT harness oracle against a numpy reference, minimized to a 40-line kernel).Fix: a new preprocessing normalization gives such buffers one leading dimension per lane axis and indexes every access with the lane IVs (bounded to the batched extents, small-buffer-gated). Lit test included; the minimized kernel raises and computes bit-exact results.
Part of #2968.
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https://claude.ai/code/session_016zErYp7upmqr4NHfhod9UD