pre-commit: autoupdate hooks - #117
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Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Filip Go¿a¿ <filip.golas@3mdeb.com> Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Filip Go¿a¿ <filip.golas@3mdeb.com> Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
…he INF file Fix build complaining on missing ParseVBootWorkbuf. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Add PlatformGopPolicy to use external GOP driver Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Use PlatformGopPolicy in place of GraphicsOutputDxe if command line param passed Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This is a port of upstream commits c248802 and bfefdc2 On modern platforms with TBT devices the coreboot resource allocator opens large PCI bridge MMIO windows above 4GiB to place hotplugable PCI BARs there as they won't fit below 4GiB. In addition modern GPGPU devices have very big PCI bars that doesn't fit below 4GiB. The PciHostBridgeLib made lots of assumptions about the coreboot resource allocator that were not verified at runtime and are no longer true. Remove all of the 'coreboot specific' code and implement the same logic as OvmfPkg's ScanForRootBridges. Fixes assertion "ASSERT [PciHostBridgeDxe] Bridge->Mem.Limit < 0x0000000100000000ULL". Co-authored-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Tcg2PhysicalPresenceLibSubmitRequestToPreOSFunction writes to TPM2 physical presence PPI provided by coreboot (a memory region preserved across reboots). CPU caches must be explicitly flushed prior to platform reboot or request written to PPI will be lost. It's important to lush cache not only when placing request in PPI, but also after clearing old request from PPI (avoids a bootloop). Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
It has been observed on MinnowBoard Turbot that the detected CPU count is lower than the number of all cores. In the tested unit, CPU is dual core, so only the BSP is detected. However, similar situation is observed on MTL laptop, where a total of 22 cores should be reported, but only 1 is detected. After EDK2 rebase a new PCD has been added, PcdFirstTimeWakeUpAPsBySipi which, when enabled (by default), sends only SIPI to APs. When disabled sends full INIT-SIPI-SIPI sequence. Only the latter case causes all the APs to wake up and be detected. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Signed-off-by: Wiktor Mowinski <wiktor.mowinski@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
…hout spaces Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Match the help text string with what can actually be set at runtime. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Display certificate Common Name instead of GUIDs when attempting to delete KEK or DB certificates. Display currently enrolled PK Common Name at the top of PK Options menu. Signed-off-by: Filip Golas <filip.golas@3mdeb.com>
Make the OVMF build again by copying CbParseLib from DasharoModulePkg and stripping the coreboot specific code. BlParseLib is required by LogoDxe. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Calling BS->ConnectController on LPC device to populate all SIO devices caused the ConPlatformDxe to set up the consoles before the PrepareLpcBridgeDevicePath updated the console variables. This resulted in a bug which required 2 resets before the serial console redirection for port 1 got disabled. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Certain platform like VP2410 can not keep RAM contents between reboots which results in TPM PPI to not work. Add an option to let platform use UEFI variable backed TPM PPI. It will let firmware menu PPI requests to be processed properly at the cost of not working OS runtime PPI requests which did not work anyway. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Use firmware information passed by coreboot in CBMEM to make a single-element ESRT. Later on ESRT will likely be constructed by EsrtDxe from data provided by FMP instances, but until then this should be good enough for viewing this information in an OS and posting of capsules. Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Make those added for BootGuard consistent with the rest and get rid of tabulation characters. Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
…led: check if KM is valid Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Fixes an issue where entering FUM twice in a row is prevented by the Request variable being the same as the Active variable, being volatile and without runtime write access. Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
…OPSWAP exists Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
…OTBLOCK and COREBOOT if TS is enabled Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Add a note that the `Keep IOMMU enabled(...)` option is incompatible with Windows, making the OS unable to boot. Signed-off-by: Filip Lewinski <filip.lewinski@3mdeb.com>
Apply https://edk2.groups.io/g/devel/message/100548 in order to fix SD cards not listing as bootable devices/mountable volumes. Signed-off-by: Filip Lewinski <filip.lewinski@3mdeb.com>
Add a library for interacting with CMOS options exposed by coreboot. Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
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On AMD server systems there are multiple PCI root bridges. The root bridge scanning in UEFI Payload is not sufficient to detect the memory and I/O apertures properly. For example, on Turin system, the I/O aperture on the first root bridge containing the FCH may not have any I/O resources detected on the PCI devices. This results in the I/O decoding to be disabled on the root bridge, effectively breaking the I/O-based serial ports, e.g. on Super I/Os and BMCs. Populate the root bridge info from CB_TAG_RB_INFO which contains data compatible with the Universal Payload PCI Root Bridges Info HOB. Make the PciHostBridgeLib pick the HOB up, if available, and populate proper root bridge apertures for AMD systems. Otherwise, fall back to root bridge scanning. Relevant coreboot patches: https://review.coreboot.org/c/coreboot/+/89486 https://review.coreboot.org/c/coreboot/+/89487 TEST=Boot UEFI Payload and see the serial console no longer breaks after PCI enumeration in UEFI Payload on Gigabyte MZ33-AR1. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Mark the range 0x1000-0xa0000 as tested. It caused the payload to mark this range as reserved. As a result, Linux kernel could not allocate memory for real mode and panicked. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Upstream-Status: Pending
There was a dirty hack for Intel platforms that read TOLUD register to determine the boundary between MMIO and DRAM. It caused problems on AMD platforms such as apu2, which does not have TOLUD register. As a result, regions which held reserved memory were incorrectly reported as RAM buffers or RAM itself and the OS allocated DMA there. It could be observed with many IO_PAGE_FAULTs occurring in the OS. See: Dasharo/dasharo-issues#1134 FWTS complains on ECAM MMCONF not being reserved in the memory map. So carve it out of the memory map and report it as reserved. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Upstream-Status: Pending
FWTS complains on MMCONF not being reseved in memory map. So reserve it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Upstream-Status: Pending
…ve 4G RAM Do not clear testd attribute from above 4G RAM memory. It caused the payload to mark above 4G ranges as reserved. As a result, Linux kernel had only as much memory, as there is available memory below 4G reported by coreboot. It caused out of memory processes kills in Linux. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Upstream-Status: Pending
…MMIO Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Upstream-Status: Pending
coreboot always uses TSC for timestamps, force correct timer library so measurements are accurate. A mismatch of timers will result in incorrect tick and nanosecond calculations due to different timer frequency. Add a copy of BaseCpuTimerLib from UefiCpuPkg and replace TSC frequency calculation with the value obtained from coreboot timestamp table. On Intel systems where the UefiCpuPkg/CpuTimerLib is used, there is no mismatch. However, AMD systems do not have the required CPUID, so the default timer is HPET, not TSC. TEST=Boot Gigabyte MZ33-AR1 and use systemd-analyze. The firmware boot time is no longer 19 minutes, but indicates correct time spent in firmware. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
…ties The timer/counter start and end value were hardcoded instead of being read from the performance protocol. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Upstream-Status: Pending
…read Add an override from openSIL/amd-edk2-platforms repo for USB mass storage. On Gigabyte MZ33-AR1 there are lots of errors from virtual CD-ROM from BMC. These additional resets help a bit in USB enumeration during boot. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
AMD silicon has different definitions for SLP_Sx states written to the ACPI PM register than Intel. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
coreboot always uses TSC for timestamps, force correct timer library so measurements are accurate. A mismatch of timers will result in incorrect tick and nanosecond calculations due to different timer frequency. Add a copy of BaseCpuTimerLib from UefiCpuPkg and replace TSC frequency calculation with the value obtained from coreboot timestamp table. On Intel systems where the UefiCpuPkg/CpuTimerLib is used, there is no mismatch. However, AMD systems do not have the required CPUID, so the default timer is HPET, not TSC. TEST=Boot Gigabyte MZ33-AR1 and use systemd-analyze. The firmware boot time is no longer 19 minutes, but indicates correct time spent in firmware. Upstream-Status: Pending Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Modern AMD platforms cannot initialize graphics in 32bit mode (using PEI GOP or VBIOS), because of UMA memory allocation above 4G by default. One would have to force the recovery path so that UMA is allocated below 4G. To allow running AMD x64 GOP, some modifications are needed. Firstly, the GOP still needs VBIOS, so PCI IO must provide it from FFS. Then, the GOP driver must also be included in the FFS, so that DXE dispatcher picks it up and runs it. TEST=Successfully initialize integrated graphics on MSI PRO B850-P WIFI. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This makes capsule PKCS#7 signatures reproducible. openssl smime -sign embeds a signingTime signed attribute (current UTCTime) by default. Because the attribute is inside the signed digest, the resulting RSA signature differs on every invocation even when the key and payload are identical, breaking reproducible builds of signed FMP capsules. Pass -noattr to drop all signed attributes from the SignerInfo. The signature is then computed directly over the content, producing byte-identical output across runs. The FMP update path is unaffected: FmpAuthenticationLibPkcs7 calls Pkcs7Verify() without extracting signed attributes, and rollback protection uses FwVersion / LowestSupportedVersion in FMP_PAYLOAD_HEADER plus the auth header MonotonicCount, not signingTime. signingTime is only consumed by DxeImageVerificationLib for Secure Boot dbt checks on PE/COFF images, which is a separate code path. Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
The PR #282 broke builds where TPM_ENABLE is FALSE. The calls to the TPM2 command libraries querying supported PCR banks do not have a null library implementation, thus an attempt to build PlatformBootManagerLib without TPM fails due to the PCR bank checks. Compile out the PCR bank check if TPM is not enabled in the build. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
RELEASE payloads embed the absolute build directory and are therefore not bit-for-bit reproducible: the EDK II workspace lives under the coreboot tree at payloads/external/edk2/workspace, so the path varies with the coreboot checkout location (e.g. /build/coreboot vs /home/coreboot/coreboot). Two mechanisms leak it into the image: - GenFw writes the full path of the input .dll into the PE/COFF debug directory (NB10/RSDS CodeView entry) of every module. - With the console enabled (USE_CBMEM_FOR_CONSOLE == TRUE) ASSERT() stays compiled in and embeds the absolute __FILE__ source path of each module. Strip both in RELEASE builds: - RELEASE_*_*_GENFW_FLAGS = --zero zeroes the debug data fields and the timestamp in the PE image. This mirrors upstream OvmfPkg, which does exactly the same in its release DSCs; see commit f037af6 ("OvmfPkg: strip build paths in release builds", TianoCore PR #1513, tianocore/edk2#1513). - GCC:RELEASE_*_*_CC_FLAGS = -ffile-prefix-map=$(WORKSPACE)/= remaps the workspace prefix so the __FILE__ strings become relative. This is only needed when the console keeps ASSERT compiled in; otherwise MDEPKG_NDEBUG already drops them. Signed-off-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com> Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Flushing only when buffer overflows or when newline is encountered often produces some parts of the text being cut off, because EDK2 often writes by placing the cursor on a specific row&column, not necessarily by replacing the whole line. Flushing on every write solves that, but because the EC flushes take a lot of time and with them, scrolling down a single line in multiscreen menus takes about a second, vs about 0.3s with full buffering, which is unacceptable. Using a gBS event the flushes can be performed on a contant time interbal. It allows for buffering and high responsiveneess due to not wasting time on EC flush busy-waits while simultaneously ensuring everything is flushed in a set amount of time. Signed-off-by: Filip Gołaś <filip.golas@3mdeb.com>
Depend on the TPM2 ACPI table published by coreboot to get the AMD fTPM control area address. If the address is not in the standard TPM address space, assume it is AMD fTPM. Ensure the TPM2 and TCPA tables are not installed in the Platform ACPI driver. This will ensure the event log is properly populated and TPM2 ACPI table is installed by Tcg2Acpi even if coreboot publishes ACPI TPM2/TCPA tables. Add handling of CRB command processing in the TPM2 device library and omit touching registers that do not exist on AMD fTPM. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
updates: - [github.com/pre-commit/pre-commit-hooks: v4.4.0 → v6.0.0](pre-commit/pre-commit-hooks@v4.4.0...v6.0.0) - [github.com/talos-systems/conform: v0.1.0-alpha.27 → v0.1.0-alpha.31](siderolabs/conform@v0.1.0-alpha.27...v0.1.0-alpha.31) - [github.com/codespell-project/codespell: v2.2.5 → v2.4.3](codespell-project/codespell@v2.2.5...v2.4.3)
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