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Pin gpu-kernels e85b7547: m128_w8_f2_sb prefill tiles + raster groups (27B pp +1.6..2.5%) - #490

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Oct 21, 2026
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gpu-kernels e85b7547 (squash of #10 on top of 8f26d1f4) adds, since eb97e1dc:

Measured on strixhalo gfx1151, performance mode, private build (llama.cpp 5dcf6623 +
hrx-system 82804197 + the add-on, the hw-gate configuration), interleaved llama-bench
A/B against the 8f26d1f4 add-on, 3 passes, medians:
Qwen3.8-27B UD-Q4_K_XL pp512 597.4 -> 611.7 (+2.4%), pp2048 602.0 -> 616.2 (+2.4%),
pp4096 589.8 -> 604.4 (+2.5%) at ub 512; pp4096 563.2 -> 572.3 (+1.6%) at ub 2048;
tg64 12.2 -> 12.2.
Qwen3-4B Q5_K_M pp2048 3122.5 -> 3215.8 (+3.0%) and pp4096 2094.2 -> 2137.8 (+2.1%)
at ub 2048.
Correctness: test-backend-ops MUL_MAT 359/359 (x3 default, x2 tile forced, raster
forced); dense-prefill-bench vs CPU bad = 0 (T 256..4097); KLD vs base 0.000000 on
27B (c512 ub512, c4096 ub2048) and ZAYA1-8B (c512, all logits through the ragged
q6_K lm_head).

Auto-merge is off on purpose: merge by hand after the hw_gate job passes.

🤖 Generated with Claude Code

… (Qwen3.8-27B pp +1.6..2.5%)

gpu-kernels e85b7547 (squash of #10 on top of 8f26d1f4) adds, since eb97e1dc:
- #18: one header for the kqt workgroup geometry (values unchanged).
- #10: m128_w8_f2_sb dense prefill tiles for Q4_K/Q5_K/Q6_K and group_m raster
  groups for inputs above 32 MiB of f16 (output-identical).

Measured on strixhalo gfx1151, performance mode, private build (llama.cpp 5dcf6623 +
hrx-system 82804197 + the add-on, the hw-gate configuration), interleaved llama-bench
A/B against the 8f26d1f4 add-on, 3 passes, medians:
  Qwen3.8-27B UD-Q4_K_XL pp512 597.4 -> 611.7 (+2.4%), pp2048 602.0 -> 616.2 (+2.4%),
  pp4096 589.8 -> 604.4 (+2.5%) at ub 512; pp4096 563.2 -> 572.3 (+1.6%) at ub 2048;
  tg64 12.2 -> 12.2.
  Qwen3-4B Q5_K_M pp2048 3122.5 -> 3215.8 (+3.0%) and pp4096 2094.2 -> 2137.8 (+2.1%)
  at ub 2048.
Correctness: test-backend-ops MUL_MAT 359/359 (x3 default, x2 tile forced, raster
forced); dense-prefill-bench vs CPU bad = 0 (T 256..4097); KLD vs base 0.000000 on
27B (c512 ub512, c4096 ub2048) and ZAYA1-8B (c512, all logits through the ragged
q6_K lm_head).

Co-Authored-By: Claude Opus 5.5 <noreply@anthropic.com>
@bong-water-water-bong bong-water-water-bong added the hw-gate Run the HRX hardware gate on Strix Halo (docs/hw-gate.md) label Oct 21, 2026
@bong-water-water-bong
bong-water-water-bong merged commit fa2e627 into main Oct 21, 2026
9 of 10 checks passed
@bong-water-water-bong
bong-water-water-bong deleted the 1bit/pin-gpu-kernels-e85b7547 branch October 21, 2026 15:02
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