[bong-water-water-bong]

README.md and docs/ (which 1bit.gg publishes) brought to the current narrative. Pairs with 1bit-MONSTER/site branch 1bit/site-narrative-2026-10-21.

• README: lead with the census (43/43 configurations on the GPU, Pin gpu-kernels be68256d and llama.cpp b14a2836: census gaps G1, G3-G6 on HRX #476/Census G7-G9 pinned: K-only q8, L2_NORM, --parallel on the qwen35 family #480/Pin gpu-kernels fcf526ea: jina attention (G10), softmax sinks fix, startup ABI check - census 43/43 on HRX #481) and Qwen3.8-27B MTP 36.0/26.8/29.9 tok/s (Pin gpu-kernels eb97e1dc: 2..8-token K-quant verify kernels (Qwen3.8-27B --mtp +31-39%) #487); one hop (One hop from Lemonade: serve --print-backend, Lemonade starts llama-server directly #475), strict placement (Strict device placement by default on HRX; hw-gate fails a node off HRX #482), hw-gate builds our kernels and checks placement (hw-gate: build the private HIP kernels, as the release does #478/hw-gate: q8_0 KV cache rows, the add-on fa-decode q8 check, and the GPU token #484), allocation safety (Pin llama.cpp 5dcf6623: HRX allocation safety (pool budget, poisoned device, coherent host reads) #486), Ubuntu 26.04 PPA lemond (Ubuntu 26.04 install path: the PPA's lemond runs our HRX llama-server #483), ONNX on the NPU through the user's Ryzen AI install (onnx: Linux NPU route via Ryzen AI SW (RyzenAI EP), non-invasive #386). Vulkan/ROCm/CUDA/ZINC/ComfyUI/MLX/Windows listed as cut (Core engine: HRX + HIP + NPU only (strip Vulkan, ROCm, ZINC, CUDA, ComfyUI; move site and kernel out) #306), not as routes. No release date or weekly schedule: the first release goes out when the checklist is done. Thank-you table: XRT and xdna-driver rows reworded neutrally; ODS first, then Lemonade/AMD, unchanged.
• docs/npu.md: rewritten as a status page with the public parts only (Q4NX format credited to FastFlowLM, GGUF repack and its scale checks, serving, the add-on hook, how to build against the binary drop or a prebuilt runtime library, the xdna-driver pin). No runtime method, no NPU speed numbers.
• docs/releases.md: "Releases"; package checks described without naming the runtime they exclude; "The release run" instead of "The Sunday run".
• lemonade.md: lead with the 29/29 LLM suite on HRX and one hop; Vulkan row marked removed; NPU row without speeds.
• serve.md: lead with one hop and the census; --mtp row and section lead with the HRX measurement (Pin gpu-kernels eb97e1dc: 2..8-token K-quant verify kernels (Qwen3.8-27B --mtp +31-39%) #487), the Vulkan sweep kept as history; add-on wording.
• hrx.md: lead with the census and Pin gpu-kernels eb97e1dc: 2..8-token K-quant verify kernels (Qwen3.8-27B --mtp +31-39%) #487 instead of 335 tok/s and the Vulkan comparison; the MTP bullet notes Pin gpu-kernels eb97e1dc: 2..8-token K-quant verify kernels (Qwen3.8-27B --mtp +31-39%) #487; no private repository name.
• laya.md, PORTING.md, registry.md: the NPU encoder and NPU rows without speeds, private repository names or dev-box paths; ZAYA1 row notes ~90 tok/s on HRX.

Checked: the site builds from this branch and the site branch together (37 pages), one h1 per page, no dead internal links or anchors, every meta title <= 65 and description <= 160 characters; tools/copyright.py --check clean.

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[github-actions]

PR Reviewer Guide 🔍

Here are some key observations to aid the review process:

🎫 Ticket compliance analysis 🔶 476 - Partially compliant Compliant requirements: Takes the census-gap fixes (pi goal mvgdshw8) into the engine G1 q8_0 KV cache: gpu-kernels Steps 1-2: embedded Lemonade, and HRX + Vulkan in one llama.cpp build #6 G3 LFM2 --parallel 4: gpu-kernels Step 2: HRX + Vulkan in one llama.cpp build, wired into Lemonade #7 G4 ZAYA logits: gpu-kernels Step 3a: NPU full ELFs generated in C++ — no xclbin, no per-context files #8 + llama.cpp MoE streaming: traces, cache policies, the expert cache, the three-way split, the sweet spot per model #113 G5 27B MTP PAD: gpu-kernels Steps 3b-3c: NPU fast lane runtime on full ELFs, served through Lemonade #9 + llama.cpp Zyphra Zamba2 on Vulkan: carry ggml-org#21412, and a d_state-64 Mamba-2 scan #114 G6 27B MTP 8K prompt: llama.cpp HRX: flash-attention decode-split template resolution fails ("all_rejected") at longer context (~3800+ tokens) #115 hw-gate label runs the full gate (5 models incl. MoE + IQ4_XS) on these pins registry regenerated, pins check clean Non-compliant requirements: G2 is already on main (serve: the placement report covers every graph, and --strict-device reads it #473) - not directly addressed in this PR G7 (K-only q8) follows once rebased - not addressed in this PR G10 (jina rerank) is parked - not addressed in this PR Requires further human verification: Verification of G2 fix on main Verification of G7 and G10 fixes in future PRs 480 - Partially compliant Compliant requirements: Takes the last census-gap fixes into the engine (pi goal mvgdshw8) G7 K-only q8 KV (-ctk q8_0, V f16) keeps flash attention: gpu-kernels HRX: follow AMD's live ggml-hrx, pinned to AMD's tested pair and kept current #11 G8 L2_NORM f32 (27B --dflash target): gpu-kernels XDNA: pin upstream amd/xdna-driver (and its XRT), build it privately, keep it current #12 G9 --parallel on qwen35/qwen35moe/qwen3next: llama.cpp Zyphra Zamba v1 on Vulkan, and a converter fix for SentencePiece-style tokenizer.json vocabs #117 (GDN up to 8 sequences) + serve no longer refuses Pins: llama.cpp cefbfc07, gpu-kernels 421d7a4e Registry regenerated; check-pins and copyright clean docs/hrx.md updated Non-compliant requirements: None Requires further human verification: None 481 - Partially compliant Compliant requirements: Pins gpu-kernels ZINC: pin upstream, serve it through Lemonade, NVIDIA verified on an RTX 5090 #14 (strided batched matmul + ALiBi softmax for jina-bert) With it, the 20 Oct HRX census closes: 43 of 43 runnable cells (chat, long, q8 KV, --parallel 4, MTP, embedding, rerank across Qwen3 0.6B/4B, LFM2, MiniCPM, ZAYA, Coder-30B, GLM, Qwen3.8-27B, nomic, jina, bge) with 0 nodes off HRX, 1 graph split, every request answered (pi goal mvgdshw8, evidence strixhalo ~/wt/HRX-GAPS-PROGRESS.md) hw-gate label builds our kernels and runs the full gate Non-compliant requirements: merged by hand after it passes - not directly addressed in this PR Requires further human verification: Verification of merge by hand

⏱️ Estimated effort to review: 3 🔵🔵🔵⚪⚪

🧪 No relevant tests

🔒 No security concerns identified

⚡ Recommended focus areas for review Outdated Documentation The documentation in docs/npu.md has been significantly rewritten to reflect the current state of the NPU engine. However, some sections still reference outdated information or historical paths, such as the mention of xclbin and the old full ELF generation process. These sections should be carefully reviewed to ensure they accurately reflect the current implementation and do not mislead users about the NPU engine's architecture. # NPU engine The NPU engine is in progress: correctness first, speed next. Its kernels, built from source, match an fp64 reference on Qwen3-0.6B, 1.7B and 4B. The layer kernel and lm head reach cosine similarity 0.9999 or better at every tested position, and greedy decoding matches the reference token for token. They are not merged into this repository yet. The release carries the NPU runtime, compiled into `1bit`, and the `npu` backend of Lemonade's `onebit` recipe; until the kernels land, a release package serves GGUF models on HRX, not NPU models ([releases.md](releases.md#the-npu-engine)). The NPU runtime and the NPU kernels are proprietary and closed source ([releases.md](releases.md#private-components)). This page covers the public parts: the model format, how `1bit serve` runs an NPU model, and how to build. AMD's own NPU stack is a separate route that ships today: `1bit serve --device onnx` runs Ryzen AI Software's ONNX Runtime GenAI (the RyzenAI provider) on the NPU, on Linux too, from the user's own install of it ([ONNX Runtime, Linux NPU](onnx.md#linux-npu)). ## A model directory Inconsistent Model Type Reference The documentation in docs/npu.md refers to qwen3 as the model type for the NPU engine, but the actual implementation may differ. This inconsistency should be verified to ensure that the documentation accurately reflects the current model type used by the NPU engine. decodes the first layout. MTP Speed Numbers The documentation in docs/serve.md provides specific speed numbers for MTP on HRX (36.0 / 26.8 / 29.9 tok/s), but these numbers are based on measurements taken on the removed Vulkan build and have not been repeated on HRX. This could mislead users about the actual performance on HRX. On HRX, Qwen3.8-27B UD-Q4_K_XL with its MTP head (default draft length 3, greedy 256-token chats, medians of 3 fresh servers) decodes at **36.0 / 26.8 / 29.9 tok/s** on code / prose / short, up from 25.9 / 20.5 / 21.9, since our HIP kernels check 2 to 8 drafted tokens in one pass: the 4-token verify step went from 121.5 to 88.0 ms ([#487](https://github.com/1bit-MONSTER/engine/pull/487)).

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⚠️ Review coverage: The following files were not included in this review because of the token budget:

• docs/lemonade.md
• docs/hrx.md