diff --git a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
index e70edd5b04b5..254b0965f3a9 100644
--- a/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace15_mtpm.dtsi
@@ -26,6 +26,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <1>;
 			cpu-power-states = <&d3>;
+			zephyr,deferred-start;
 		};
 
 		cpu2: cpu@2 {
@@ -33,6 +34,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <2>;
 			cpu-power-states = <&d3>;
+			zephyr,deferred-start;
 		};
 
 		power-states {
diff --git a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi
index 4de61e3f3975..950158356b84 100644
--- a/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace20_lnl.dtsi
@@ -26,6 +26,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <1>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 
 		cpu2: cpu@2 {
@@ -33,6 +34,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <2>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 
 		cpu3: cpu@3 {
@@ -40,6 +42,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <3>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 
 		cpu4: cpu@4 {
@@ -47,6 +50,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <4>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 
 		power-states {
diff --git a/dts/xtensa/intel/intel_adsp_ace30.dtsi b/dts/xtensa/intel/intel_adsp_ace30.dtsi
index 761fc3b74760..cee8791a0819 100644
--- a/dts/xtensa/intel/intel_adsp_ace30.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace30.dtsi
@@ -26,6 +26,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <1>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 
 		cpu2: cpu@2 {
@@ -33,6 +34,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <2>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 
 		power-states {
diff --git a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
index fbc1339546ff..656e5b988953 100644
--- a/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace30_ptl.dtsi
@@ -13,6 +13,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <3>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 
 		cpu4: cpu@4 {
@@ -20,6 +21,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <4>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 	};
 
diff --git a/dts/xtensa/intel/intel_adsp_ace40.dtsi b/dts/xtensa/intel/intel_adsp_ace40.dtsi
index 69fab0b7c906..e29671792c70 100644
--- a/dts/xtensa/intel/intel_adsp_ace40.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace40.dtsi
@@ -26,6 +26,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <1>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 
 		power-states {
diff --git a/dts/xtensa/intel/intel_adsp_ace40_nvl.dtsi b/dts/xtensa/intel/intel_adsp_ace40_nvl.dtsi
index 3428b207d4ed..13bc7cd9109b 100644
--- a/dts/xtensa/intel/intel_adsp_ace40_nvl.dtsi
+++ b/dts/xtensa/intel/intel_adsp_ace40_nvl.dtsi
@@ -13,6 +13,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <2>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 
 		cpu3: cpu@3 {
@@ -20,6 +21,7 @@
 			compatible = "cdns,tensilica-xtensa-lx7";
 			reg = <3>;
 			cpu-power-states = <&d0i3 &d3>;
+			zephyr,deferred-start;
 		};
 	};
 
diff --git a/dts/xtensa/intel/intel_adsp_cavs25.dtsi b/dts/xtensa/intel/intel_adsp_cavs25.dtsi
index fe95613e9fca..91dfac8d245f 100644
--- a/dts/xtensa/intel/intel_adsp_cavs25.dtsi
+++ b/dts/xtensa/intel/intel_adsp_cavs25.dtsi
@@ -26,6 +26,7 @@
 			compatible = "cdns,tensilica-xtensa-lx6";
 			reg = <1>;
 			cpu-power-states = <&d3>;
+			zephyr,deferred-start;
 		};
 
 		cpu2: cpu@2 {
@@ -33,6 +34,7 @@
 			compatible = "cdns,tensilica-xtensa-lx6";
 			reg = <2>;
 			cpu-power-states = <&d3>;
+			zephyr,deferred-start;
 		};
 
 		cpu3: cpu@3 {
@@ -40,6 +42,7 @@
 			compatible = "cdns,tensilica-xtensa-lx6";
 			reg = <3>;
 			cpu-power-states = <&d3>;
+			zephyr,deferred-start;
 		};
 
 		power-states {
diff --git a/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi b/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi
index 4a50211f11d1..e81e155f5f03 100644
--- a/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi
+++ b/dts/xtensa/intel/intel_adsp_cavs25_tgph.dtsi
@@ -26,6 +26,7 @@
 			compatible = "cdns,tensilica-xtensa-lx6";
 			reg = <1>;
 			cpu-power-states = <&d3>;
+			zephyr,deferred-start;
 		};
 
 		power-states {