From 67915e861e93ec8d1f35cb3eb6330c56d3d0c111 Mon Sep 17 00:00:00 2001 From: TruongSinh Tran-Nguyen Date: Thu, 16 Jul 2026 11:28:42 -0700 Subject: [PATCH] Add Xtensa (ESP32-S2/S3) target support - map CONFIG_XTENSA SoC series to xtensa-*-none-elf rust targets (these exist upstream as tier 3 but need the esp-rs toolchain's LLVM backend) - allow RUST_SUPPORTED on XTENSA - kconfig codegen: emit hex values wider than 32 bits as u64 (ESP32-S3 GPIO masks overflow usize on 32-bit targets) Verified on heltec_wireless_tracker/esp32s3/procpu hardware: hello_world boots and logs, built with the esp 1.93 toolchain and CARGO_UNSTABLE_BUILD_STD=core,alloc. Signed-off-by: TruongSinh Tran-Nguyen --- CMakeLists.txt | 13 +++++++++++++ Kconfig | 1 + zephyr-build/src/lib.rs | 6 +++++- 3 files changed, 19 insertions(+), 1 deletion(-) diff --git a/CMakeLists.txt b/CMakeLists.txt index be31379d..0c5b4eac 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -49,6 +49,19 @@ function(_rust_map_target) else() message(FATAL_ERROR "Rust: Unsupported riscv ISA") endif() + elseif(CONFIG_XTENSA) + # Xtensa targets exist upstream as tier 3 (rust-lang/rust #125141) but + # official rustc ships without the Xtensa LLVM backend; these require + # the esp-rs Rust toolchain on PATH. + if(CONFIG_SOC_SERIES_ESP32S3) + set(RUST_TARGET "xtensa-esp32s3-none-elf" PARENT_SCOPE) + elseif(CONFIG_SOC_SERIES_ESP32S2) + set(RUST_TARGET "xtensa-esp32s2-none-elf" PARENT_SCOPE) + elseif(CONFIG_SOC_SERIES_ESP32) + set(RUST_TARGET "xtensa-esp32-none-elf" PARENT_SCOPE) + else() + message(FATAL_ERROR "Rust: Unsupported Xtensa SoC series") + endif() elseif(CONFIG_ARCH_POSIX AND CONFIG_64BIT AND (${CMAKE_HOST_SYSTEM_PROCESSOR} MATCHES "x86_64")) set(RUST_TARGET "x86_64-unknown-none" PARENT_SCOPE) elseif(CONFIG_ARCH_POSIX AND CONFIG_64BIT AND (${CMAKE_HOST_SYSTEM_PROCESSOR} MATCHES "aarch64")) diff --git a/Kconfig b/Kconfig index 0b2d057b..f84862cf 100644 --- a/Kconfig +++ b/Kconfig @@ -9,6 +9,7 @@ config RUST_SUPPORTED bool default y if ((CPU_CORTEX_M || \ (RISCV && !RISCV_ISA_RV32E && !RISCV_ISA_RV128I) || \ + XTENSA || \ (ARCH_POSIX && 64BIT)) && \ !TIMER_READS_ITS_FREQUENCY_AT_RUNTIME) help diff --git a/zephyr-build/src/lib.rs b/zephyr-build/src/lib.rs index 6fd4f772..5af2be14 100644 --- a/zephyr-build/src/lib.rs +++ b/zephyr-build/src/lib.rs @@ -78,7 +78,11 @@ pub fn build_kconfig_mod() { let line = line.expect("reading line from dotconfig"); if let Some(caps) = config_hex.captures(&line) { writeln!(&mut f, "#[allow(dead_code)]").unwrap(); - writeln!(&mut f, "pub const {}: usize = {};", &caps[1], &caps[2]).unwrap(); + // Hex values wider than 32 bits (e.g. ESP32-S3 GPIO masks) don't + // fit usize on 32-bit targets; widen the type to match the value. + let value = u64::from_str_radix(&caps[2][2..], 16).unwrap_or(u64::MAX); + let ty = if value > u32::MAX as u64 { "u64" } else { "usize" }; + writeln!(&mut f, "pub const {}: {} = {};", &caps[1], ty, &caps[2]).unwrap(); } else if let Some(caps) = config_int.captures(&line) { writeln!(&mut f, "#[allow(dead_code)]").unwrap(); writeln!(&mut f, "pub const {}: isize = {};", &caps[1], &caps[2]).unwrap();