diff --git a/.gitmodules b/.gitmodules index 1150a53..557e4d3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -1,4 +1,4 @@ [submodule "src"] path = src - url = https://github.com/gregkh/linux.git - branch = linux-6.16.y + url = https://github.com/radxa/kernel.git + branch = linux-6.17.1 diff --git a/debian/patches/linux/0002-arm64-dts-qcom-qcs6490-audioreach-Add-gpr-node.patch b/debian/patches/linux/0002-arm64-dts-qcom-qcs6490-audioreach-Add-gpr-node.patch deleted file mode 100644 index a692094..0000000 --- a/debian/patches/linux/0002-arm64-dts-qcom-qcs6490-audioreach-Add-gpr-node.patch +++ /dev/null @@ -1,102 +0,0 @@ -From b0f281dc4866874c963443d345130f67fe8a4363 Mon Sep 17 00:00:00 2001 -From: Mohammad Rafi Shaik -Date: Sun, 20 Jul 2025 23:02:07 +0530 -Subject: [PATCH 02/49] arm64: dts: qcom: qcs6490-audioreach: Add gpr node - -Add GPR(Generic Pack router) node along with -APM(Audio Process Manager) and PRM(Proxy resource -Manager) audio services. - -A new qcs6490-audioreach.dtsi file has been added to -update AudioReach specific device tree configurations. -The existing audio nodes in sc7280.dtsi, which were designed -for the ADSP Bypass solution. The audio nodes now being updated -in qcs6490-audioreach.dtsi to support the ADSP-based AudioReach -architecture. - -Signed-off-by: Mohammad Rafi Shaik -Co-developed-by: Prasad Kumpatla -Signed-off-by: Prasad Kumpatla -Reviewed-by: Konrad Dybcio ---- - .../boot/dts/qcom/qcs6490-audioreach.dtsi | 54 +++++++++++++++++++ - arch/arm64/boot/dts/qcom/sc7280.dtsi | 2 +- - 2 files changed, 55 insertions(+), 1 deletion(-) - create mode 100644 arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi - -diff --git a/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi -new file mode 100644 -index 000000000000..282938c042f7 ---- /dev/null -+++ b/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi -@@ -0,0 +1,54 @@ -+// SPDX-License-Identifier: BSD-3-Clause -+/* -+ * qcs6490 device tree source for Audioreach Solution. -+ * This file will configure and manage nodes from sc7280.dtsi to -+ * support the AudioReach solution. -+ * -+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. -+ */ -+ -+#include -+#include -+#include -+#include -+ -+&remoteproc_adsp_glink { -+ /delete-node/ apr; -+ -+ gpr { -+ compatible = "qcom,gpr"; -+ qcom,glink-channels = "adsp_apps"; -+ qcom,domain = ; -+ qcom,intents = <512 20>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ q6apm: service@1 { -+ compatible = "qcom,q6apm"; -+ reg = ; -+ #sound-dai-cells = <0>; -+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; -+ -+ q6apmdai: dais { -+ compatible = "qcom,q6apm-dais"; -+ iommus = <&apps_smmu 0x1801 0x0>; -+ }; -+ -+ q6apmbedai: bedais { -+ compatible = "qcom,q6apm-lpass-dais"; -+ #sound-dai-cells = <1>; -+ }; -+ }; -+ -+ q6prm: service@2 { -+ compatible = "qcom,q6prm"; -+ reg = ; -+ qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; -+ -+ q6prmcc: clock-controller { -+ compatible = "qcom,q6prm-lpass-clocks"; -+ #clock-cells = <2>; -+ }; -+ }; -+ }; -+}; -diff --git a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -index b1cc3bc1aec8..708df3f08984 100644 ---- a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -+++ b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -@@ -3814,7 +3814,7 @@ remoteproc_adsp: remoteproc@3700000 { - - status = "disabled"; - -- glink-edge { -+ remoteproc_adsp_glink: glink-edge { - interrupts-extended = <&ipcc IPCC_CLIENT_LPASS - IPCC_MPROC_SIGNAL_GLINK_QMP - IRQ_TYPE_EDGE_RISING>; --- -2.50.1 - diff --git a/debian/patches/linux/0051-feat-Radxa-custom-kernel-config.patch b/debian/patches/linux/0002-feat-Radxa-custom-kernel-config.patch similarity index 80% rename from debian/patches/linux/0051-feat-Radxa-custom-kernel-config.patch rename to debian/patches/linux/0002-feat-Radxa-custom-kernel-config.patch index ba7addf..a748989 100644 --- a/debian/patches/linux/0051-feat-Radxa-custom-kernel-config.patch +++ b/debian/patches/linux/0002-feat-Radxa-custom-kernel-config.patch @@ -5,8 +5,8 @@ Subject: [PATCH] feat: Radxa custom kernel config Signed-off-by: HE Zhengyu --- - arch/arm64/configs/radxa_custom.config | 8 ++++++++ - 1 file changed, 8 insertions(+) + arch/arm64/configs/radxa_custom.config | 4 ++++ + 1 file changed, 4 insertions(+) create mode 100644 arch/arm64/configs/radxa_custom.config diff --git a/src/arch/arm64/configs/radxa_custom.config b/src/arch/arm64/configs/radxa_custom.config @@ -14,15 +14,11 @@ new file mode 100644 index 000000000000..4e8c56c4c5cd --- /dev/null +++ b/src/arch/arm64/configs/radxa_custom.config -@@ -0,0 +1,8 @@ +@@ -0,0 +1,4 @@ +# Kernel modules build by portage and XZ compressed fail to load with latest kmod tools. +# DKMS: https://bugs.gentoo.org/920837 +CONFIG_MODULE_COMPRESS_XZ=n +CONFIG_MODULE_COMPRESS_ZSTD=y -+ -+# fix: WCD Playback: codec dai not found -+CONFIG_SOUND=y -+CONFIG_SND=y -- 2.50.1 diff --git a/debian/patches/linux/0003-dt-bindings-pinctrl-qcom-sc7280-lpass-lpi-pinctrl-Do.patch b/debian/patches/linux/0003-dt-bindings-pinctrl-qcom-sc7280-lpass-lpi-pinctrl-Do.patch deleted file mode 100644 index 3a683b7..0000000 --- a/debian/patches/linux/0003-dt-bindings-pinctrl-qcom-sc7280-lpass-lpi-pinctrl-Do.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 5a4b57af6a18ad49df40200b5a8f4df253f598eb Mon Sep 17 00:00:00 2001 -From: Mohammad Rafi Shaik -Date: Sun, 20 Jul 2025 23:02:08 +0530 -Subject: [PATCH 03/49] dt-bindings: pinctrl: qcom,sc7280-lpass-lpi-pinctrl: - Document the clock property - -Document the clock property in sc7280 LPASS LPI pinctrl node. -Clock settings required for Audioreach solution. - -The existing SC7280 platform only supports non-ADSP audio solutions. -To enable audio functionality on ADSP with the AudioReach solution. -additional core and audio hardware clocks must be configured. -Without these clocks, the ADSP will crash. - -Signed-off-by: Mohammad Rafi Shaik -Co-developed-by: Prasad Kumpatla -Signed-off-by: Prasad Kumpatla ---- - .../pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml | 16 ++++++++++++++++ - 1 file changed, 16 insertions(+) - -diff --git a/src/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/src/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml -index 08801cc4e476..bc7b8dda8837 100644 ---- a/src/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml -+++ b/src/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml -@@ -20,6 +20,16 @@ properties: - reg: - maxItems: 2 - -+ clocks: -+ items: -+ - description: LPASS Core voting clock -+ - description: LPASS Audio voting clock -+ -+ clock-names: -+ items: -+ - const: core -+ - const: audio -+ - patternProperties: - "-state$": - oneOf: -@@ -70,10 +80,16 @@ unevaluatedProperties: false - - examples: - - | -+ #include - lpass_tlmm: pinctrl@33c0000 { - compatible = "qcom,sc7280-lpass-lpi-pinctrl"; - reg = <0x33c0000 0x20000>, - <0x3550000 0x10000>; -+ -+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; -+ clock-names = "core", "audio"; -+ - gpio-controller; - #gpio-cells = <2>; - gpio-ranges = <&lpass_tlmm 0 0 15>; --- -2.50.1 - diff --git a/debian/patches/linux/0004-arm64-dts-qcom-sc7280-Add-WSA-SoundWire-and-LPASS-su.patch b/debian/patches/linux/0004-arm64-dts-qcom-sc7280-Add-WSA-SoundWire-and-LPASS-su.patch deleted file mode 100644 index 7c25c0e..0000000 --- a/debian/patches/linux/0004-arm64-dts-qcom-sc7280-Add-WSA-SoundWire-and-LPASS-su.patch +++ /dev/null @@ -1,121 +0,0 @@ -From 28d77f827a907003c108cdc7b06bc9e2025364e1 Mon Sep 17 00:00:00 2001 -From: Mohammad Rafi Shaik -Date: Sun, 20 Jul 2025 23:02:10 +0530 -Subject: [PATCH 04/49] arm64: dts: qcom: sc7280: Add WSA SoundWire and LPASS - support - -Add WSA LPASS macro Codec along with SoundWire controller. - -Signed-off-by: Mohammad Rafi Shaik -Co-developed-by: Prasad Kumpatla -Signed-off-by: Prasad Kumpatla -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/sc7280.dtsi | 77 ++++++++++++++++++++++++++++ - 1 file changed, 77 insertions(+) - -diff --git a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -index 708df3f08984..1b210264bbe8 100644 ---- a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -+++ b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -@@ -28,6 +28,7 @@ - #include - #include - #include -+#include - #include - #include - -@@ -2636,6 +2637,66 @@ swr1: soundwire@3230000 { - status = "disabled"; - }; - -+ lpass_wsa_macro: codec@3240000 { -+ compatible = "qcom,sc7280-lpass-wsa-macro"; -+ reg = <0x0 0x03240000 0x0 0x1000>; -+ -+ clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, -+ <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, -+ <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&lpass_va_macro>; -+ clock-names = "mclk", -+ "npl", -+ "macro", -+ "dcodec", -+ "fsgen"; -+ -+ pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; -+ pinctrl-names = "default"; -+ -+ #clock-cells = <0>; -+ clock-output-names = "mclk"; -+ #sound-dai-cells = <1>; -+ -+ status = "disabled"; -+ }; -+ -+ swr2: soundwire@3250000 { -+ compatible = "qcom,soundwire-v1.6.0"; -+ reg = <0x0 0x03250000 0x0 0x2000>; -+ -+ interrupts = ; -+ clocks = <&lpass_wsa_macro>; -+ clock-names = "iface"; -+ -+ resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; -+ reset-names = "swr_audio_cgcr"; -+ -+ qcom,din-ports = <2>; -+ qcom,dout-ports = <6>; -+ -+ qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 -+ 0x1f 0x3f 0x0f 0x0f>; -+ qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; -+ qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; -+ qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; -+ qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; -+ qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; -+ qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 -+ 0xff 0xff>; -+ qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff -+ 0xff 0xff>; -+ qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff -+ 0xff 0xff>; -+ -+ #address-cells = <2>; -+ #size-cells = <0>; -+ #sound-dai-cells = <1>; -+ -+ status = "disabled"; -+ }; -+ - lpass_audiocc: clock-controller@3300000 { - compatible = "qcom,sc7280-lpassaudiocc"; - reg = <0 0x03300000 0 0x30000>, -@@ -2839,6 +2900,22 @@ lpass_tx_swr_data: tx-swr-data-state { - pins = "gpio1", "gpio2", "gpio14"; - function = "swr_tx_data"; - }; -+ -+ lpass_wsa_swr_clk: wsa-swr-clk-state { -+ pins = "gpio10"; -+ function = "wsa_swr_clk"; -+ drive-strength = <2>; -+ slew-rate = <1>; -+ bias-disable; -+ }; -+ -+ lpass_wsa_swr_data: wsa-swr-data-state { -+ pins = "gpio11"; -+ function = "wsa_swr_data"; -+ drive-strength = <2>; -+ slew-rate = <1>; -+ bias-bus-hold; -+ }; - }; - - gpu: gpu@3d00000 { --- -2.50.1 - diff --git a/debian/patches/linux/0005-arm64-dts-qcom-qcs6490-audioreach-Modify-LPASS-macro.patch b/debian/patches/linux/0005-arm64-dts-qcom-qcs6490-audioreach-Modify-LPASS-macro.patch deleted file mode 100644 index 31a5ea9..0000000 --- a/debian/patches/linux/0005-arm64-dts-qcom-qcs6490-audioreach-Modify-LPASS-macro.patch +++ /dev/null @@ -1,97 +0,0 @@ -From f7e9ee0d6fbcfda0bdbc2559769c54abff4e06fe Mon Sep 17 00:00:00 2001 -From: Mohammad Rafi Shaik -Date: Sun, 20 Jul 2025 23:02:11 +0530 -Subject: [PATCH 05/49] arm64: dts: qcom: qcs6490-audioreach: Modify LPASS - macros clock settings for audioreach - -Modify and enable WSA, VA, RX and TX lpass macros and lpass_tlmm clock -settings. For audioreach solution mclk, npl and fsgen clocks are enabled -through the q6prm clock driver. - -For qcs6490 RX drives clk from TX CORE which is mandated from DSP side, -Unlike dedicated core clocks. Core TX clk is used for both RX and -WSA as per DSP recommendations. - -Signed-off-by: Mohammad Rafi Shaik -Co-developed-by: Prasad Kumpatla -Signed-off-by: Prasad Kumpatla -Reviewed-by: Konrad Dybcio ---- - .../boot/dts/qcom/qcs6490-audioreach.dtsi | 61 +++++++++++++++++++ - 1 file changed, 61 insertions(+) - -diff --git a/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi -index 282938c042f7..6d3a9e171066 100644 ---- a/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi -+++ b/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi -@@ -12,6 +12,67 @@ - #include - #include - -+&lpass_rx_macro { -+ /delete-property/ power-domains; -+ /delete-property/ power-domain-names; -+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&lpass_va_macro>; -+ clock-names = "mclk", -+ "npl", -+ "macro", -+ "dcodec", -+ "fsgen"; -+}; -+ -+&lpass_tlmm { -+ clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; -+ clock-names = "core", -+ "audio"; -+}; -+ -+&lpass_tx_macro { -+ /delete-property/ power-domains; -+ /delete-property/ power-domain-names; -+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&lpass_va_macro>; -+ clock-names = "mclk", -+ "npl", -+ "macro", -+ "dcodec", -+ "fsgen"; -+}; -+ -+&lpass_va_macro { -+ /delete-property/ power-domains; -+ /delete-property/ power-domain-names; -+ clocks = <&q6prmcc LPASS_CLK_ID_VA_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; -+ clock-names = "mclk", -+ "macro", -+ "dcodec"; -+}; -+ -+&lpass_wsa_macro { -+ clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_CLK_ID_TX_CORE_NPL_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, -+ <&lpass_va_macro>; -+ clock-names = "mclk", -+ "npl", -+ "macro", -+ "dcodec", -+ "fsgen"; -+}; -+ - &remoteproc_adsp_glink { - /delete-node/ apr; - --- -2.50.1 - diff --git a/debian/patches/linux/0006-arm64-dts-qcom-qcs6490-rb3gen2-Add-WSA8830-speakers-.patch b/debian/patches/linux/0006-arm64-dts-qcom-qcs6490-rb3gen2-Add-WSA8830-speakers-.patch deleted file mode 100644 index 835445b..0000000 --- a/debian/patches/linux/0006-arm64-dts-qcom-qcs6490-rb3gen2-Add-WSA8830-speakers-.patch +++ /dev/null @@ -1,132 +0,0 @@ -From 220e9df5c49cf1659ff594609c521a371daabcb3 Mon Sep 17 00:00:00 2001 -From: Mohammad Rafi Shaik -Date: Sun, 20 Jul 2025 23:02:12 +0530 -Subject: [PATCH 06/49] arm64: dts: qcom: qcs6490-rb3gen2: Add WSA8830 speakers - amplifier - -Add nodes for WSA8830 speakers amplifier on qcs6490-rb3gen2 board. - -Enable lpass_wsa and lpass_va macros along with pinctrl settings -for audio. - -Signed-off-by: Mohammad Rafi Shaik -Co-developed-by: Prasad Kumpatla -Signed-off-by: Prasad Kumpatla ---- - .../boot/dts/qcom/qcs6490-audioreach.dtsi | 6 ++++ - arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 35 +++++++++++++++++++ - arch/arm64/boot/dts/qcom/sc7280.dtsi | 6 ++++ - 3 files changed, 47 insertions(+) - -diff --git a/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi b/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi -index 6d3a9e171066..078936237e20 100644 ---- a/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi -+++ b/src/arch/arm64/boot/dts/qcom/qcs6490-audioreach.dtsi -@@ -58,6 +58,12 @@ &lpass_va_macro { - clock-names = "mclk", - "macro", - "dcodec"; -+ -+ pinctrl-0 = <&lpass_dmic01_clk>, <&lpass_dmic01_data>, -+ <&lpass_dmic23_clk>, <&lpass_dmic23_data>; -+ pinctrl-names = "default"; -+ -+ qcom,dmic-sample-rate = <4800000>; - }; - - &lpass_wsa_macro { -diff --git a/src/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/src/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts -index 5fbcd48f2e2d..82aa69d715d9 100644 ---- a/src/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts -+++ b/src/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts -@@ -19,6 +19,7 @@ - #include "pm7325.dtsi" - #include "pm8350c.dtsi" - #include "pmk8350.dtsi" -+#include "qcs6490-audioreach.dtsi" - - /delete-node/ &ipa_fw_mem; - /delete-node/ &rmtfs_mem; -@@ -765,6 +766,14 @@ redriver_usb_con_sbu: endpoint { - }; - }; - -+&lpass_va_macro { -+ status = "okay"; -+}; -+ -+&lpass_wsa_macro { -+ status = "okay"; -+}; -+ - &mdss { - status = "okay"; - }; -@@ -1039,6 +1048,32 @@ &sdhc_2 { - status = "okay"; - }; - -+&swr2 { -+ status = "okay"; -+ -+ left_spkr: speaker@0,1 { -+ compatible = "sdw10217020200"; -+ reg = <0 1>; -+ reset-gpios = <&tlmm 158 GPIO_ACTIVE_LOW>; -+ #sound-dai-cells = <0>; -+ sound-name-prefix = "SpkrLeft"; -+ #thermal-sensor-cells = <0>; -+ vdd-supply = <&vreg_l18b_1p8>; -+ qcom,port-mapping = <1 2 3 7>; -+ }; -+ -+ right_spkr: speaker@0,2 { -+ compatible = "sdw10217020200"; -+ reg = <0 2>; -+ reset-gpios = <&tlmm 158 GPIO_ACTIVE_LOW>; -+ #sound-dai-cells = <0>; -+ sound-name-prefix = "SpkrRight"; -+ #thermal-sensor-cells = <0>; -+ vdd-supply = <&vreg_l18b_1p8>; -+ qcom,port-mapping = <4 5 6 8>; -+ }; -+}; -+ - &tlmm { - gpio-reserved-ranges = <32 2>, /* ADSP */ - <48 4>; /* NFC */ -diff --git a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -index 1b210264bbe8..059a428ee0b3 100644 ---- a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -+++ b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -@@ -2864,21 +2864,27 @@ lpass_tlmm: pinctrl@33c0000 { - lpass_dmic01_clk: dmic01-clk-state { - pins = "gpio6"; - function = "dmic1_clk"; -+ drive-strength = <8>; -+ bias-disable; - }; - - lpass_dmic01_data: dmic01-data-state { - pins = "gpio7"; - function = "dmic1_data"; -+ bias-pull-down; - }; - - lpass_dmic23_clk: dmic23-clk-state { - pins = "gpio8"; - function = "dmic2_clk"; -+ drive-strength = <8>; -+ bias-disable; - }; - - lpass_dmic23_data: dmic23-data-state { - pins = "gpio9"; - function = "dmic2_data"; -+ bias-pull-down; - }; - - lpass_rx_swr_clk: rx-swr-clk-state { --- -2.50.1 - diff --git a/debian/patches/linux/0007-arm64-dts-qcom-qcs6490-rb3gen2-Add-sound-card.patch b/debian/patches/linux/0007-arm64-dts-qcom-qcs6490-rb3gen2-Add-sound-card.patch deleted file mode 100644 index 2e7ce52..0000000 --- a/debian/patches/linux/0007-arm64-dts-qcom-qcs6490-rb3gen2-Add-sound-card.patch +++ /dev/null @@ -1,76 +0,0 @@ -From 690a3c52b6f7605f9e5b06c08c25ffbfcc99636f Mon Sep 17 00:00:00 2001 -From: Mohammad Rafi Shaik -Date: Sun, 20 Jul 2025 23:02:13 +0530 -Subject: [PATCH 07/49] arm64: dts: qcom: qcs6490-rb3gen2: Add sound card - -Add the sound card node with tested playback over WSA8835 speakers -and digital on-board mics. - -Signed-off-by: Mohammad Rafi Shaik -Co-developed-by: Prasad Kumpatla -Signed-off-by: Prasad Kumpatla -Reviewed-by: Konrad Dybcio -Reviewed-by: Dmitry Baryshkov ---- - arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts | 45 ++++++++++++++++++++ - 1 file changed, 45 insertions(+) - -diff --git a/src/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts b/src/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts -index 82aa69d715d9..d2876ff21251 100644 ---- a/src/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts -+++ b/src/arch/arm64/boot/dts/qcom/qcs6490-rb3gen2.dts -@@ -1048,6 +1048,51 @@ &sdhc_2 { - status = "okay"; - }; - -+&sound { -+ compatible = "qcom,qcs6490-rb3gen2-sndcard"; -+ model = "QCS6490-RB3Gen2"; -+ -+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", -+ "SpkrRight IN", "WSA_SPK2 OUT", -+ "VA DMIC0", "vdd-micb", -+ "VA DMIC1", "vdd-micb", -+ "VA DMIC2", "vdd-micb", -+ "VA DMIC3", "vdd-micb"; -+ -+ wsa-dai-link { -+ link-name = "WSA Playback"; -+ -+ codec { -+ sound-dai = <&left_spkr>, <&right_spkr>, -+ <&swr2 0>, <&lpass_wsa_macro 0>; -+ }; -+ -+ cpu { -+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; -+ }; -+ -+ platform { -+ sound-dai = <&q6apm>; -+ }; -+ }; -+ -+ va-dai-link { -+ link-name = "VA Capture"; -+ -+ codec { -+ sound-dai = <&lpass_va_macro 0>; -+ }; -+ -+ cpu { -+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; -+ }; -+ -+ platform { -+ sound-dai = <&q6apm>; -+ }; -+ }; -+}; -+ - &swr2 { - status = "okay"; - --- -2.50.1 - diff --git a/debian/patches/linux/0008-arm64-dts-qcom-qcm6490-idp-Add-WSA8830-speakers-and-.patch b/debian/patches/linux/0008-arm64-dts-qcom-qcm6490-idp-Add-WSA8830-speakers-and-.patch deleted file mode 100644 index b85dd52..0000000 --- a/debian/patches/linux/0008-arm64-dts-qcom-qcm6490-idp-Add-WSA8830-speakers-and-.patch +++ /dev/null @@ -1,222 +0,0 @@ -From c019f4369a6839e4192ef1d66efdf10348ea3d8d Mon Sep 17 00:00:00 2001 -From: Mohammad Rafi Shaik -Date: Sun, 20 Jul 2025 23:02:14 +0530 -Subject: [PATCH 08/49] arm64: dts: qcom: qcm6490-idp: Add WSA8830 speakers and - WCD9370 headset codec - -Add nodes for WSA8830 speakers and WCD9370 headset codec -on qcm6490-idp board. - -Enable lpass macros along with audio support pin controls. - -Signed-off-by: Mohammad Rafi Shaik -Co-developed-by: Prasad Kumpatla -Signed-off-by: Prasad Kumpatla ---- - arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 123 +++++++++++++++++++++++ - arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 +++ - 2 files changed, 135 insertions(+) - -diff --git a/src/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/src/arch/arm64/boot/dts/qcom/qcm6490-idp.dts -index 7a155ef6492e..468f5f9c0779 100644 ---- a/src/arch/arm64/boot/dts/qcom/qcm6490-idp.dts -+++ b/src/arch/arm64/boot/dts/qcom/qcm6490-idp.dts -@@ -18,6 +18,7 @@ - #include "pm7325.dtsi" - #include "pm8350c.dtsi" - #include "pmk8350.dtsi" -+#include "qcs6490-audioreach.dtsi" - - /delete-node/ &ipa_fw_mem; - /delete-node/ &rmtfs_mem; -@@ -169,6 +170,30 @@ vph_pwr: vph-pwr-regulator { - regulator-min-microvolt = <3700000>; - regulator-max-microvolt = <3700000>; - }; -+ -+ wcd9370: audio-codec-0 { -+ compatible = "qcom,wcd9370-codec"; -+ -+ pinctrl-0 = <&wcd_default>; -+ pinctrl-names = "default"; -+ -+ reset-gpios = <&tlmm 83 GPIO_ACTIVE_HIGH>; -+ -+ vdd-buck-supply = <&vreg_l17b_1p7>; -+ vdd-rxtx-supply = <&vreg_l18b_1p8>; -+ vdd-px-supply = <&vreg_l18b_1p8>; -+ vdd-mic-bias-supply = <&vreg_bob_3p296>; -+ -+ qcom,micbias1-microvolt = <1800000>; -+ qcom,micbias2-microvolt = <1800000>; -+ qcom,micbias3-microvolt = <1800000>; -+ qcom,micbias4-microvolt = <1800000>; -+ -+ qcom,rx-device = <&wcd937x_rx>; -+ qcom,tx-device = <&wcd937x_tx>; -+ -+ #sound-dai-cells = <1>; -+ }; - }; - - &apps_rsc { -@@ -536,6 +561,22 @@ &gpu_zap_shader { - firmware-name = "qcom/qcm6490/a660_zap.mbn"; - }; - -+&lpass_rx_macro { -+ status = "okay"; -+}; -+ -+&lpass_tx_macro { -+ status = "okay"; -+}; -+ -+&lpass_va_macro { -+ status = "okay"; -+}; -+ -+&lpass_wsa_macro { -+ status = "okay"; -+}; -+ - &mdss { - status = "okay"; - }; -@@ -716,6 +757,81 @@ &sdhc_2 { - cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; - }; - -+&swr0 { -+ status = "okay"; -+ -+ wcd937x_rx: codec@0,4 { -+ compatible = "sdw20217010a00"; -+ reg = <0 4>; -+ -+ /* -+ * WCD9370 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R) -+ * WCD9370 RX Port 2 (CLSH) <==> SWR1 Port 2 (CLSH) -+ * WCD9370 RX Port 3 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R) -+ * WCD9370 RX Port 4 (LO) <==> SWR1 Port 4 (LO) -+ * WCD9370 RX Port 5 (DSD_L/R) <==> SWR1 Port 5 (DSD) -+ */ -+ qcom,rx-port-mapping = <1 2 3 4 5>; -+ -+ /* -+ * Static channels mapping between slave and master rx port channels. -+ * In the order of slave port channels, which is -+ * hph_l, hph_r, clsh, comp_l, comp_r, lo, dsd_r, dsd_l. -+ */ -+ qcom,rx-channel-mapping = /bits/ 8 <1 2 1 1 2 1 1 2>; -+ }; -+}; -+ -+&swr1 { -+ status = "okay"; -+ -+ wcd937x_tx: codec@0,3 { -+ compatible = "sdw20217010a00"; -+ reg = <0 3>; -+ -+ /* -+ * WCD9370 TX Port 1 (ADC1) <=> SWR2 Port 2 -+ * WCD9370 TX Port 2 (ADC2, 3) <=> SWR2 Port 2 -+ * WCD9370 TX Port 3 (DMIC0,1,2,3 & MBHC) <=> SWR2 Port 3 -+ * WCD9370 TX Port 4 (DMIC4,5,6,7) <=> SWR2 Port 4 -+ */ -+ qcom,tx-port-mapping = <1 1 2 3>; -+ -+ /* -+ * Static channel mapping between slave and master tx port channels. -+ * In the order of slave port channels which is adc1, adc2, adc3, -+ * mic0, dmic1, mbhc, dmic2, dmic3, dmci4, dmic5, dmic6, dmic7. -+ */ -+ qcom,tx-channel-mapping = /bits/ 8 <1 2 1 1 2 3 3 4 1 2 3 4>; -+ }; -+}; -+ -+&swr2 { -+ status = "okay"; -+ -+ left_spkr: speaker@0,1 { -+ compatible = "sdw10217020200"; -+ reg = <0 1>; -+ powerdown-gpios = <&tlmm 63 GPIO_ACTIVE_LOW>; -+ #sound-dai-cells = <0>; -+ sound-name-prefix = "SpkrLeft"; -+ #thermal-sensor-cells = <0>; -+ vdd-supply = <&vreg_l18b_1p8>; -+ qcom,port-mapping = <1 2 3 7>; -+ }; -+ -+ right_spkr: speaker@0,2 { -+ compatible = "sdw10217020200"; -+ reg = <0 2>; -+ powerdown-gpios = <&tlmm 62 GPIO_ACTIVE_LOW>; -+ #sound-dai-cells = <0>; -+ sound-name-prefix = "SpkrRight"; -+ #thermal-sensor-cells = <0>; -+ vdd-supply = <&vreg_l18b_1p8>; -+ qcom,port-mapping = <4 5 6 8>; -+ }; -+}; -+ - &tlmm { - gpio-reserved-ranges = <32 2>, /* ADSP */ - <48 4>; /* NFC */ -@@ -725,6 +841,13 @@ sd_cd: sd-cd-state { - function = "gpio"; - bias-pull-up; - }; -+ -+ wcd_default: wcd-reset-n-active-state { -+ pins = "gpio83"; -+ function = "gpio"; -+ drive-strength = <16>; -+ bias-disable; -+ }; - }; - - &uart5 { -diff --git a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -index 059a428ee0b3..57e9f32311b2 100644 ---- a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -+++ b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -@@ -2890,21 +2890,33 @@ lpass_dmic23_data: dmic23-data-state { - lpass_rx_swr_clk: rx-swr-clk-state { - pins = "gpio3"; - function = "swr_rx_clk"; -+ drive-strength = <2>; -+ slew-rate = <1>; -+ bias-disable; - }; - - lpass_rx_swr_data: rx-swr-data-state { - pins = "gpio4", "gpio5"; - function = "swr_rx_data"; -+ drive-strength = <2>; -+ slew-rate = <1>; -+ bias-bus-hold; - }; - - lpass_tx_swr_clk: tx-swr-clk-state { - pins = "gpio0"; - function = "swr_tx_clk"; -+ drive-strength = <2>; -+ slew-rate = <1>; -+ bias-disable; - }; - - lpass_tx_swr_data: tx-swr-data-state { - pins = "gpio1", "gpio2", "gpio14"; - function = "swr_tx_data"; -+ drive-strength = <2>; -+ slew-rate = <1>; -+ bias-bus-hold; - }; - - lpass_wsa_swr_clk: wsa-swr-clk-state { --- -2.50.1 - diff --git a/debian/patches/linux/0009-arm64-dts-qcom-qcm6490-idp-Add-sound-card.patch b/debian/patches/linux/0009-arm64-dts-qcom-qcm6490-idp-Add-sound-card.patch deleted file mode 100644 index 1eff0f1..0000000 --- a/debian/patches/linux/0009-arm64-dts-qcom-qcm6490-idp-Add-sound-card.patch +++ /dev/null @@ -1,114 +0,0 @@ -From 308e7c4d6d01cadeb39dbb4e955b00bc8c26ddaa Mon Sep 17 00:00:00 2001 -From: Mohammad Rafi Shaik -Date: Sun, 20 Jul 2025 23:02:15 +0530 -Subject: [PATCH 09/49] arm64: dts: qcom: qcm6490-idp: Add sound card - -Add the sound card node with tested playback over WSA8835 speakers, -digital on-board mics along with wcd9370 headset playabck and record. - -Signed-off-by: Mohammad Rafi Shaik -Co-developed-by: Prasad Kumpatla -Signed-off-by: Prasad Kumpatla -Reviewed-by: Konrad Dybcio ---- - arch/arm64/boot/dts/qcom/qcm6490-idp.dts | 84 ++++++++++++++++++++++++ - 1 file changed, 84 insertions(+) - -diff --git a/src/arch/arm64/boot/dts/qcom/qcm6490-idp.dts b/src/arch/arm64/boot/dts/qcom/qcm6490-idp.dts -index 468f5f9c0779..d434f9340e38 100644 ---- a/src/arch/arm64/boot/dts/qcom/qcm6490-idp.dts -+++ b/src/arch/arm64/boot/dts/qcom/qcm6490-idp.dts -@@ -757,6 +757,90 @@ &sdhc_2 { - cd-gpios = <&tlmm 91 GPIO_ACTIVE_LOW>; - }; - -+&sound { -+ compatible = "qcom,qcm6490-idp-sndcard"; -+ model = "QCM6490-IDP"; -+ -+ audio-routing = "SpkrLeft IN", "WSA_SPK1 OUT", -+ "SpkrRight IN", "WSA_SPK2 OUT", -+ "IN1_HPHL", "HPHL_OUT", -+ "IN2_HPHR", "HPHR_OUT", -+ "AMIC2", "MIC BIAS2", -+ "TX DMIC0", "MIC BIAS1", -+ "TX DMIC1", "MIC BIAS2", -+ "TX DMIC2", "MIC BIAS3", -+ "TX SWR_ADC1", "ADC2_OUTPUT", -+ "VA DMIC0", "VA MIC BIAS3", -+ "VA DMIC1", "VA MIC BIAS3", -+ "VA DMIC2", "VA MIC BIAS1", -+ "VA DMIC3", "VA MIC BIAS1"; -+ -+ wsa-dai-link { -+ link-name = "WSA Playback"; -+ -+ codec { -+ sound-dai = <&left_spkr>, <&right_spkr>, -+ <&swr2 0>, <&lpass_wsa_macro 0>; -+ }; -+ -+ cpu { -+ sound-dai = <&q6apmbedai WSA_CODEC_DMA_RX_0>; -+ }; -+ -+ platform { -+ sound-dai = <&q6apm>; -+ }; -+ }; -+ -+ wcd-playback-dai-link { -+ link-name = "WCD Playback"; -+ -+ codec { -+ sound-dai = <&wcd9370 0>, <&swr0 0>, <&lpass_rx_macro 0>; -+ }; -+ -+ cpu { -+ sound-dai = <&q6apmbedai RX_CODEC_DMA_RX_0>; -+ }; -+ -+ platform { -+ sound-dai = <&q6apm>; -+ }; -+ }; -+ -+ wcd-capture-dai-link { -+ link-name = "WCD Capture"; -+ -+ codec { -+ sound-dai = <&wcd9370 1>, <&swr1 0>, <&lpass_tx_macro 0>; -+ }; -+ -+ cpu { -+ sound-dai = <&q6apmbedai TX_CODEC_DMA_TX_3>; -+ }; -+ -+ platform { -+ sound-dai = <&q6apm>; -+ }; -+ }; -+ -+ va-dai-link { -+ link-name = "VA Capture"; -+ -+ codec { -+ sound-dai = <&lpass_va_macro 0>; -+ }; -+ -+ cpu { -+ sound-dai = <&q6apmbedai VA_CODEC_DMA_TX_0>; -+ }; -+ -+ platform { -+ sound-dai = <&q6apm>; -+ }; -+ }; -+}; -+ - &swr0 { - status = "okay"; - --- -2.50.1 - diff --git a/debian/patches/linux/0010-arm64-qcom-sc7280-Add-PCIe0-controller.patch b/debian/patches/linux/0010-arm64-qcom-sc7280-Add-PCIe0-controller.patch deleted file mode 100644 index 53bb775..0000000 --- a/debian/patches/linux/0010-arm64-qcom-sc7280-Add-PCIe0-controller.patch +++ /dev/null @@ -1,166 +0,0 @@ -From 0e26af70b4a19430cf62364a5c8791d53fc6f7c5 Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Fri, 23 May 2025 21:10:39 +0800 -Subject: [PATCH 10/49] arm64: qcom: sc7280: Add PCIe0 controller - -Signed-off-by: Xilin Wu ---- - arch/arm64/boot/dts/qcom/sc7280.dtsi | 128 ++++++++++++++++++++++++++- - 1 file changed, 127 insertions(+), 1 deletion(-) - -diff --git a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -index 57e9f32311b2..6149b1ddc85b 100644 ---- a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -+++ b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -@@ -971,7 +971,7 @@ gcc: clock-controller@100000 { - reg = <0 0x00100000 0 0x1f0000>; - clocks = <&rpmhcc RPMH_CXO_CLK>, - <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, -- <0>, <&pcie1_phy>, -+ <&pcie0_phy>, <&pcie1_phy>, - <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, - <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; - clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", -@@ -2201,6 +2201,127 @@ wifi: wifi@17a10040 { - qcom,smem-state-names = "wlan-smp2p-out"; - }; - -+ pcie0: pcie@1c00000 { -+ compatible = "qcom,pcie-sc7280"; -+ reg = <0 0x01c00000 0 0x3000>, -+ <0 0x60000000 0 0xf1d>, -+ <0 0x60000f20 0 0xa8>, -+ <0 0x60001000 0 0x1000>, -+ <0 0x60100000 0 0x100000>; -+ -+ reg-names = "parf", "dbi", "elbi", "atu", "config"; -+ device_type = "pci"; -+ linux,pci-domain = <0>; -+ bus-range = <0x00 0xff>; -+ num-lanes = <1>; -+ -+ #address-cells = <3>; -+ #size-cells = <2>; -+ -+ ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, -+ <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; -+ -+ interrupts = ; -+ interrupt-names = "msi"; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 0x7>; -+ interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, -+ <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; -+ -+ clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, -+ <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, -+ <&pcie0_phy>, -+ <&rpmhcc RPMH_CXO_CLK>, -+ <&gcc GCC_PCIE_0_AUX_CLK>, -+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>, -+ <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, -+ <&gcc GCC_PCIE_0_SLV_AXI_CLK>, -+ <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, -+ <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, -+ <&gcc GCC_DDRSS_PCIE_SF_CLK>, -+ <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, -+ <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; -+ -+ clock-names = "pipe", -+ "pipe_mux", -+ "phy_pipe", -+ "ref", -+ "aux", -+ "cfg", -+ "bus_master", -+ "bus_slave", -+ "slave_q2a", -+ "tbu", -+ "ddrss_sf_tbu", -+ "aggre0", -+ "aggre1"; -+ -+ assigned-clocks = <&gcc GCC_PCIE_0_AUX_CLK>; -+ assigned-clock-rates = <19200000>; -+ -+ resets = <&gcc GCC_PCIE_0_BCR>; -+ reset-names = "pci"; -+ -+ power-domains = <&gcc GCC_PCIE_0_GDSC>; -+ -+ phys = <&pcie0_phy>; -+ phy-names = "pciephy"; -+ -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pcie0_clkreq_n>; -+ -+ dma-coherent; -+ -+ interconnects = <&aggre1_noc MASTER_PCIE_0 0 &mc_virt SLAVE_EBI1 0>, -+ <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_PCIE_0 0>; -+ interconnect-names = "pcie-mem", "cpu-pcie"; -+ -+ iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, -+ <0x100 &apps_smmu 0x1c01 0x1>; -+ -+ status = "disabled"; -+ -+ pcie@0 { -+ device_type = "pci"; -+ reg = <0x0 0x0 0x0 0x0 0x0>; -+ bus-range = <0x01 0xff>; -+ -+ #address-cells = <3>; -+ #size-cells = <2>; -+ ranges; -+ }; -+ }; -+ -+ pcie0_phy: phy@1c06000 { -+ compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; -+ reg = <0 0x01c06000 0 0x1c0>; -+ clocks = <&gcc GCC_PCIE_0_AUX_CLK>, -+ <&gcc GCC_PCIE_0_CFG_AHB_CLK>, -+ <&gcc GCC_PCIE_CLKREF_EN>, -+ <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, -+ <&gcc GCC_PCIE_0_PIPE_CLK>; -+ clock-names = "aux", -+ "cfg_ahb", -+ "ref", -+ "refgen", -+ "pipe"; -+ -+ clock-output-names = "pcie_0_pipe_clk"; -+ #clock-cells = <0>; -+ -+ #phy-cells = <0>; -+ -+ resets = <&gcc GCC_PCIE_0_PHY_BCR>; -+ reset-names = "phy"; -+ -+ assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; -+ assigned-clock-rates = <100000000>; -+ -+ status = "disabled"; -+ }; -+ - pcie1: pcie@1c08000 { - compatible = "qcom,pcie-sc7280"; - reg = <0 0x01c08000 0 0x3000>, -@@ -5372,6 +5493,11 @@ mi2s1_ws: mi2s1-ws-state { - function = "mi2s1_ws"; - }; - -+ pcie0_clkreq_n: pcie0-clkreq-n-state { -+ pins = "gpio88"; -+ function = "pcie0_clkreqn"; -+ }; -+ - pcie1_clkreq_n: pcie1-clkreq-n-state { - pins = "gpio79"; - function = "pcie1_clkreqn"; --- -2.50.1 - diff --git a/debian/patches/linux/0011-phy-qcom-qmp-combo-temporarily-fix-the-orientation-t.patch b/debian/patches/linux/0011-phy-qcom-qmp-combo-temporarily-fix-the-orientation-t.patch deleted file mode 100644 index e40f3e7..0000000 --- a/debian/patches/linux/0011-phy-qcom-qmp-combo-temporarily-fix-the-orientation-t.patch +++ /dev/null @@ -1,40 +0,0 @@ -From 14bdf2054339a2c60d398f17d5da0309f4fe8166 Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Sat, 24 May 2025 15:50:14 +0800 -Subject: [PATCH 11/49] phy: qcom: qmp-combo: temporarily fix the orientation - to reverse - ---- - drivers/phy/qualcomm/phy-qcom-qmp-combo.c | 9 ++++++++- - 1 file changed, 8 insertions(+), 1 deletion(-) - -diff --git a/src/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/src/drivers/phy/qualcomm/phy-qcom-qmp-combo.c -index b09fa00e9fe7..419c1eed18af 100644 ---- a/src/drivers/phy/qualcomm/phy-qcom-qmp-combo.c -+++ b/src/drivers/phy/qualcomm/phy-qcom-qmp-combo.c -@@ -2424,6 +2424,13 @@ static bool qmp_combo_configure_dp_mode(struct qmp_combo *qmp) - const struct phy_configure_opts_dp *dp_opts = &qmp->dp_opts; - u32 val; - -+ struct device *dev = qmp->dev; -+ -+ if (reverse) -+ dev_info(dev, "Configuring DP for reverse orientation\n"); -+ else -+ dev_info(dev, "Configuring DP for normal orientation\n"); -+ - val = DP_PHY_PD_CTL_PWRDN | DP_PHY_PD_CTL_AUX_PWRDN | - DP_PHY_PD_CTL_PLL_PWRDN | DP_PHY_PD_CTL_DP_CLAMP_EN; - -@@ -3771,7 +3778,7 @@ static int qmp_combo_probe(struct platform_device *pdev) - qmp->dev = dev; - dev_set_drvdata(dev, qmp); - -- qmp->orientation = TYPEC_ORIENTATION_NORMAL; -+ qmp->orientation = TYPEC_ORIENTATION_REVERSE; - - qmp->cfg = of_device_get_match_data(dev); - if (!qmp->cfg) --- -2.50.1 - diff --git a/debian/patches/linux/0012-dt-bindings-qcom-se-common-Add-QUP-Peripheral-specif.patch b/debian/patches/linux/0012-dt-bindings-qcom-se-common-Add-QUP-Peripheral-specif.patch deleted file mode 100644 index 6083008..0000000 --- a/debian/patches/linux/0012-dt-bindings-qcom-se-common-Add-QUP-Peripheral-specif.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 11bd66763a2ccb707e288561f164fec6cfd0fc8e Mon Sep 17 00:00:00 2001 -From: Viken Dadhaniya -Date: Tue, 24 Jun 2025 15:20:58 +0530 -Subject: [PATCH 12/49] dt-bindings: qcom: se-common: Add QUP - Peripheral-specific properties for I2C, SPI, and SERIAL bus - -Introduce a new YAML schema for QUP-supported peripherals. Define common -properties used across QUP-supported peripherals. - -Add property `qcom,enable-gsi-dma` to configure the Serial Engine (SE) for -QCOM GPI DMA mode. - -Reference the common schema YAML in the GENI I2C, SPI, and SERIAL YAML -files. - -Reviewed-by: Krzysztof Kozlowski -Co-developed-by: Mukesh Kumar Savaliya -Signed-off-by: Mukesh Kumar Savaliya -Signed-off-by: Viken Dadhaniya ---- - .../bindings/i2c/qcom,i2c-geni-qcom.yaml | 1 + - .../serial/qcom,serial-geni-qcom.yaml | 1 + - .../soc/qcom/qcom,se-common-props.yaml | 26 +++++++++++++++++++ - .../bindings/spi/qcom,spi-geni-qcom.yaml | 1 + - 4 files changed, 29 insertions(+) - create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml - -diff --git a/src/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/src/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml -index 9f66a3bb1f80..51534953a69c 100644 ---- a/src/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml -+++ b/src/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml -@@ -75,6 +75,7 @@ required: - - allOf: - - $ref: /schemas/i2c/i2c-controller.yaml# -+ - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# - - if: - properties: - compatible: -diff --git a/src/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/src/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml -index dd33794b3534..ed7b3909d87d 100644 ---- a/src/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml -+++ b/src/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml -@@ -12,6 +12,7 @@ maintainers: - - allOf: - - $ref: /schemas/serial/serial.yaml# -+ - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# - - properties: - compatible: -diff --git a/src/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml b/src/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml -new file mode 100644 -index 000000000000..6a34f05a07e8 ---- /dev/null -+++ b/src/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml -@@ -0,0 +1,26 @@ -+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) -+%YAML 1.2 -+--- -+$id: http://devicetree.org/schemas/soc/qcom/qcom,se-common-props.yaml# -+$schema: http://devicetree.org/meta-schemas/core.yaml# -+ -+title: QUP Peripheral-specific properties for I2C, SPI and SERIAL bus -+ -+description: -+ The Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) is -+ a programmable module that supports a wide range of serial interfaces -+ such as UART, SPI, I2C, I3C, etc. This defines the common properties used -+ across QUP-supported peripherals. -+ -+maintainers: -+ - Mukesh Kumar Savaliya -+ - Viken Dadhaniya -+ -+properties: -+ qcom,enable-gsi-dma: -+ $ref: /schemas/types.yaml#/definitions/flag -+ description: -+ Configure the Serial Engine (SE) to transfer data in QCOM GPI DMA mode. -+ By default, FIFO mode (PIO/CPU DMA) will be selected. -+ -+additionalProperties: true -diff --git a/src/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/src/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml -index 2e20ca313ec1..d12c5a060ed0 100644 ---- a/src/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml -+++ b/src/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml -@@ -25,6 +25,7 @@ description: - - allOf: - - $ref: /schemas/spi/spi-controller.yaml# -+ - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# - - properties: - compatible: --- -2.50.1 - diff --git a/debian/patches/linux/0013-soc-qcom-geni-se-Add-support-to-load-QUP-SE-Firmware.patch b/debian/patches/linux/0013-soc-qcom-geni-se-Add-support-to-load-QUP-SE-Firmware.patch deleted file mode 100644 index 6c9611d..0000000 --- a/debian/patches/linux/0013-soc-qcom-geni-se-Add-support-to-load-QUP-SE-Firmware.patch +++ /dev/null @@ -1,737 +0,0 @@ -From df421f0c8e35f55d8e9cac4a8311dcadd764094b Mon Sep 17 00:00:00 2001 -From: Viken Dadhaniya -Date: Tue, 24 Jun 2025 15:20:59 +0530 -Subject: [PATCH 13/49] soc: qcom: geni-se: Add support to load QUP SE Firmware - via Linux subsystem - -In Qualcomm SoCs, firmware loading for Serial Engines (SE) within the QUP -hardware has traditionally been managed by TrustZone (TZ). This restriction -poses a significant challenge for developers, as it limits their ability to -enable various protocols on any of the SEs from the Linux side, reducing -flexibility. - -Load the firmware to QUP SE based on the 'firmware-name' property specified -in devicetree at bootup time. - -Co-developed-by: Mukesh Kumar Savaliya -Signed-off-by: Mukesh Kumar Savaliya -Signed-off-by: Viken Dadhaniya ---- - drivers/soc/qcom/qcom-geni-se.c | 407 +++++++++++++++++++++++++-- - include/linux/soc/qcom/geni-se.h | 32 ++- - include/linux/soc/qcom/qup-fw-load.h | 93 ++++++ - 3 files changed, 510 insertions(+), 22 deletions(-) - create mode 100644 include/linux/soc/qcom/qup-fw-load.h - -diff --git a/src/drivers/soc/qcom/qcom-geni-se.c b/src/drivers/soc/qcom/qcom-geni-se.c -index 4cb959106efa..ef4997a5fd63 100644 ---- a/src/drivers/soc/qcom/qcom-geni-se.c -+++ b/src/drivers/soc/qcom/qcom-geni-se.c -@@ -1,11 +1,15 @@ - // SPDX-License-Identifier: GPL-2.0 --// Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. -+/* -+ * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. -+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. -+ */ - - /* Disable MMIO tracing to prevent excessive logging of unwanted MMIO traces */ - #define __DISABLE_TRACE_MMIO__ - - #include - #include -+#include - #include - #include - #include -@@ -15,6 +19,7 @@ - #include - #include - #include -+#include - - /** - * DOC: Overview -@@ -80,9 +85,9 @@ - * common to all the serial engines and are independent of serial interfaces. - */ - --#define MAX_CLK_PERF_LEVEL 32 --#define MAX_CLKS 2 -- -+#define MAX_CLK_PERF_LEVEL 32 -+#define MAX_CLKS 2 -+#define MAX_PROTOCOL 6 - /** - * struct geni_wrapper - Data structure to represent the QUP Wrapper Core - * @dev: Device pointer of the QUP wrapper core -@@ -110,28 +115,23 @@ struct geni_se_desc { - static const char * const icc_path_names[] = {"qup-core", "qup-config", - "qup-memory"}; - -+static const char * const protocol_name[MAX_PROTOCOL] = { "None", "SPI", "UART", -+ "I2C", "I3C", "SPI SLAVE"}; -+ - #define QUP_HW_VER_REG 0x4 - - /* Common SE registers */ --#define GENI_INIT_CFG_REVISION 0x0 --#define GENI_S_INIT_CFG_REVISION 0x4 --#define GENI_OUTPUT_CTRL 0x24 --#define GENI_CGC_CTRL 0x28 - #define GENI_CLK_CTRL_RO 0x60 --#define GENI_FW_S_REVISION_RO 0x6c - #define SE_GENI_BYTE_GRAN 0x254 - #define SE_GENI_TX_PACKING_CFG0 0x260 - #define SE_GENI_TX_PACKING_CFG1 0x264 - #define SE_GENI_RX_PACKING_CFG0 0x284 - #define SE_GENI_RX_PACKING_CFG1 0x288 --#define SE_GENI_M_GP_LENGTH 0x910 --#define SE_GENI_S_GP_LENGTH 0x914 - #define SE_DMA_TX_PTR_L 0xc30 - #define SE_DMA_TX_PTR_H 0xc34 - #define SE_DMA_TX_ATTR 0xc38 - #define SE_DMA_TX_LEN 0xc3c - #define SE_DMA_TX_IRQ_EN 0xc48 --#define SE_DMA_TX_IRQ_EN_SET 0xc4c - #define SE_DMA_TX_IRQ_EN_CLR 0xc50 - #define SE_DMA_TX_LEN_IN 0xc54 - #define SE_DMA_TX_MAX_BURST 0xc5c -@@ -140,9 +140,7 @@ static const char * const icc_path_names[] = {"qup-core", "qup-config", - #define SE_DMA_RX_ATTR 0xd38 - #define SE_DMA_RX_LEN 0xd3c - #define SE_DMA_RX_IRQ_EN 0xd48 --#define SE_DMA_RX_IRQ_EN_SET 0xd4c - #define SE_DMA_RX_IRQ_EN_CLR 0xd50 --#define SE_DMA_RX_LEN_IN 0xd54 - #define SE_DMA_RX_MAX_BURST 0xd5c - #define SE_DMA_RX_FLUSH 0xd60 - #define SE_GSI_EVENT_EN 0xe18 -@@ -179,7 +177,7 @@ static const char * const icc_path_names[] = {"qup-core", "qup-config", - /* SE_DMA_GENERAL_CFG */ - #define DMA_RX_CLK_CGC_ON BIT(0) - #define DMA_TX_CLK_CGC_ON BIT(1) --#define DMA_AHB_SLV_CFG_ON BIT(2) -+#define DMA_AHB_SLV_CLK_CGC_ON BIT(2) - #define AHB_SEC_SLV_CLK_CGC_ON BIT(3) - #define DUMMY_RX_NON_BUFFERABLE BIT(4) - #define RX_DMA_ZERO_PADDING_EN BIT(5) -@@ -220,12 +218,12 @@ static void geni_se_io_init(void __iomem *base) - { - u32 val; - -- val = readl_relaxed(base + GENI_CGC_CTRL); -+ val = readl_relaxed(base + SE_GENI_CGC_CTRL); - val |= DEFAULT_CGC_EN; -- writel_relaxed(val, base + GENI_CGC_CTRL); -+ writel_relaxed(val, base + SE_GENI_CGC_CTRL); - - val = readl_relaxed(base + SE_DMA_GENERAL_CFG); -- val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CFG_ON; -+ val |= AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON; - val |= DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; - writel_relaxed(val, base + SE_DMA_GENERAL_CFG); - -@@ -891,6 +889,379 @@ int geni_icc_disable(struct geni_se *se) - } - EXPORT_SYMBOL_GPL(geni_icc_disable); - -+/** -+ * geni_read_elf() - Read an ELF file. -+ * @se: Pointer to the SE resources structure. -+ * @fw: Pointer to the firmware buffer. -+ * @pelfseg: Pointer to the SE-specific ELF header. -+ * -+ * Read the ELF file and output a pointer to the header data, which -+ * contains the firmware data and any other details. -+ * -+ * Return: 0 if successful, otherwise return an error value. -+ */ -+static int geni_read_elf(struct geni_se *se, const struct firmware *fw, struct se_fw_hdr **pelfseg) -+{ -+ const struct elf32_hdr *ehdr; -+ struct elf32_phdr *phdrs, *phdr; -+ const struct se_fw_hdr *elfseg; -+ const u8 *addr; -+ int i; -+ -+ if (!fw || fw->size < sizeof(struct elf32_hdr)) -+ return -EINVAL; -+ -+ ehdr = (struct elf32_hdr *)fw->data; -+ phdrs = (struct elf32_phdr *)(ehdr + 1); -+ -+ if (ehdr->e_phnum < 2) -+ return -EINVAL; -+ -+ for (i = 0; i < ehdr->e_phnum; i++) { -+ phdr = &phdrs[i]; -+ -+ if (fw->size < phdr->p_offset + phdr->p_filesz) -+ return -EINVAL; -+ -+ if (phdr->p_type != PT_LOAD || !phdr->p_memsz) -+ continue; -+ -+ if (MI_PBT_PAGE_MODE_VALUE(phdr->p_flags) != MI_PBT_NON_PAGED_SEGMENT || -+ MI_PBT_SEGMENT_TYPE_VALUE(phdr->p_flags) == MI_PBT_HASH_SEGMENT || -+ MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) == MI_PBT_NOTUSED_SEGMENT || -+ MI_PBT_ACCESS_TYPE_VALUE(phdr->p_flags) == MI_PBT_SHARED_SEGMENT) -+ continue; -+ -+ if (phdr->p_filesz < sizeof(struct se_fw_hdr)) -+ continue; -+ -+ addr = fw->data + phdr->p_offset; -+ elfseg = (const struct se_fw_hdr *)addr; -+ -+ if (cpu_to_le32(elfseg->magic) != MAGIC_NUM_SE || elfseg->version != 1) -+ continue; -+ -+ if (phdr->p_filesz < elfseg->fw_offset + -+ elfseg->fw_size_in_items * sizeof(u32) || -+ phdr->p_filesz < elfseg->cfg_idx_offset + -+ elfseg->cfg_size_in_items * sizeof(u8) || -+ phdr->p_filesz < elfseg->cfg_val_offset + -+ elfseg->cfg_size_in_items * sizeof(u32)) -+ continue; -+ -+ if (elfseg->serial_protocol != se->protocol) -+ continue; -+ -+ *pelfseg = (struct se_fw_hdr *)addr; -+ return 0; -+ } -+ return -EINVAL; -+} -+ -+/** -+ * geni_configure_xfer_mode() - Set the transfer mode. -+ * @se: Pointer to a structure representing SE-related resources. -+ * -+ * Set the transfer mode to either FIFO or DMA according to the mode specified by the protocol -+ * driver. -+ * -+ * Return: 0 if successful, otherwise return an error value. -+ */ -+static int geni_configure_xfer_mode(struct geni_se *se) -+{ -+ /* Configure SE FIFO, DMA or GSI mode. */ -+ switch (se->mode) { -+ case GENI_GPI_DMA: -+ geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN); -+ writel_relaxed(0x0, se->base + SE_IRQ_EN); -+ writel_relaxed(DMA_RX_EVENT_EN | DMA_TX_EVENT_EN | -+ GENI_M_EVENT_EN | GENI_S_EVENT_EN, -+ se->base + SE_GSI_EVENT_EN); -+ break; -+ -+ case GENI_SE_FIFO: -+ geni_clrbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN); -+ writel_relaxed(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN, -+ se->base + SE_IRQ_EN); -+ writel_relaxed(0x0, se->base + SE_GSI_EVENT_EN); -+ break; -+ -+ case GENI_SE_DMA: -+ geni_setbits32(se->base + SE_GENI_DMA_MODE_EN, GENI_DMA_MODE_EN); -+ writel_relaxed(DMA_RX_IRQ_EN | DMA_TX_IRQ_EN | GENI_M_IRQ_EN | GENI_S_IRQ_EN, -+ se->base + SE_IRQ_EN); -+ writel_relaxed(0x0, se->base + SE_GSI_EVENT_EN); -+ break; -+ -+ default: -+ dev_err(se->dev, "Invalid geni-se transfer mode: %d\n", se->mode); -+ return -EINVAL; -+ } -+ return 0; -+} -+ -+/** -+ * geni_enable_interrupts() - Enable interrupts. -+ * @se: Pointer to a structure representing SE-related resources. -+ * -+ * Enable the required interrupts during the firmware load process. -+ * -+ */ -+static void geni_enable_interrupts(struct geni_se *se) -+{ -+ u32 reg_value; -+ -+ /* Enable required interrupts. */ -+ writel_relaxed(M_COMMON_GENI_M_IRQ_EN, se->base + SE_GENI_M_IRQ_EN); -+ -+ reg_value = S_CMD_OVERRUN_EN | S_ILLEGAL_CMD_EN | -+ S_CMD_CANCEL_EN | S_CMD_ABORT_EN | -+ S_GP_IRQ_0_EN | S_GP_IRQ_1_EN | -+ S_GP_IRQ_2_EN | S_GP_IRQ_3_EN | -+ S_RX_FIFO_WR_ERR_EN | S_RX_FIFO_RD_ERR_EN; -+ writel_relaxed(reg_value, se->base + SE_GENI_S_IRQ_ENABLE); -+ -+ /* DMA mode configuration. */ -+ reg_value = RESET_DONE_EN | SBE_EN | DMA_DONE_EN; -+ writel_relaxed(reg_value, se->base + SE_DMA_TX_IRQ_EN_SET); -+ reg_value = FLUSH_DONE_EN | RESET_DONE_EN | SBE_EN | DMA_DONE_EN; -+ writel_relaxed(reg_value, se->base + SE_DMA_RX_IRQ_EN_SET); -+} -+ -+/** -+ * geni_write_fw_revision() - Write the firmware revision. -+ * @se: Pointer to a structure representing SE-related resources. -+ * @serial_protocol: serial protocol type. -+ * @fw_version: QUP firmware version. -+ * -+ * Write the firmware revision and protocol into the respective register. -+ * -+ * Return: None. -+ */ -+static void geni_write_fw_revision(struct geni_se *se, u16 serial_protocol, u16 fw_version) -+{ -+ u32 reg_value; -+ -+ reg_value = FIELD_PREP(FW_REV_PROTOCOL_MSK, serial_protocol); -+ reg_value |= FIELD_PREP(FW_REV_VERSION_MSK, fw_version); -+ -+ writel_relaxed(reg_value, se->base + SE_GENI_FW_REVISION); -+ writel_relaxed(reg_value, se->base + SE_S_FW_REVISION); -+} -+ -+/** -+ * geni_load_se_fw() - Load Serial Engine specific firmware. -+ * @se: Pointer to a structure representing SE-related resources. -+ * @fw: Pointer to the firmware structure. -+ * -+ * Load the protocol firmware into the IRAM of the Serial Engine. -+ * -+ * Return: 0 if successful, otherwise return an error value. -+ */ -+static int geni_load_se_fw(struct geni_se *se, const struct firmware *fw) -+{ -+ const u32 *fw_data, *cfg_val_arr; -+ const u8 *cfg_idx_arr; -+ u32 i, reg_value, ramn_cnt; -+ int ret; -+ struct se_fw_hdr *hdr; -+ -+ ret = geni_read_elf(se, fw, &hdr); -+ if (ret) { -+ dev_err(se->dev, "ELF parsing failed ret: %d\n", ret); -+ return ret; -+ } -+ -+ ramn_cnt = hdr->fw_size_in_items; -+ if (hdr->fw_size_in_items % 2 != 0) -+ ramn_cnt++; -+ -+ if (ramn_cnt >= MAX_GENI_CFG_RAMn_CNT) -+ return -EINVAL; -+ -+ ret = geni_icc_set_bw(se); -+ if (ret) -+ return ret; -+ -+ ret = geni_icc_enable(se); -+ if (ret) -+ return ret; -+ -+ ret = geni_se_resources_on(se); -+ if (ret) -+ goto err; -+ -+ ramn_cnt = hdr->fw_size_in_items; -+ if (hdr->fw_size_in_items % 2 != 0) -+ ramn_cnt++; -+ -+ if (ramn_cnt >= MAX_GENI_CFG_RAMn_CNT) -+ goto err_resource; -+ -+ fw_data = (const u32 *)((u8 *)hdr + hdr->fw_offset); -+ cfg_idx_arr = (const u8 *)hdr + hdr->cfg_idx_offset; -+ cfg_val_arr = (const u32 *)((u8 *)hdr + hdr->cfg_val_offset); -+ -+ /* Disable high priority interrupt until current low priority interrupts are handled. */ -+ geni_setbits32(se->wrapper->base + QUPV3_COMMON_CFG, FAST_SWITCH_TO_HIGH_DISABLE); -+ -+ /* Set AHB_M_CLK_CGC_ON to indicate hardware controls se-wrapper cgc clock. */ -+ geni_setbits32(se->wrapper->base + QUPV3_SE_AHB_M_CFG, AHB_M_CLK_CGC_ON); -+ -+ /* Let hardware to control common cgc. */ -+ geni_setbits32(se->wrapper->base + QUPV3_COMMON_CGC_CTRL, COMMON_CSR_SLV_CLK_CGC_ON); -+ -+ /* Allows to drive corresponding data according to hardware value. */ -+ writel_relaxed(0x0, se->base + GENI_OUTPUT_CTRL); -+ -+ /* Set SCLK and HCLK to program RAM */ -+ geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF); -+ writel_relaxed(0x0, se->base + SE_GENI_CLK_CTRL); -+ geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF); -+ -+ /* Enable required clocks for DMA CSR, TX and RX. */ -+ reg_value = AHB_SEC_SLV_CLK_CGC_ON | DMA_AHB_SLV_CLK_CGC_ON | -+ DMA_TX_CLK_CGC_ON | DMA_RX_CLK_CGC_ON; -+ geni_setbits32(se->base + SE_DMA_GENERAL_CFG, reg_value); -+ -+ /* Let hardware control CGC by default. */ -+ writel_relaxed(DEFAULT_CGC_EN, se->base + SE_GENI_CGC_CTRL); -+ -+ /* Set version of the configuration register part of firmware. */ -+ writel_relaxed(hdr->cfg_version, se->base + SE_GENI_INIT_CFG_REVISION); -+ writel_relaxed(hdr->cfg_version, se->base + SE_GENI_S_INIT_CFG_REVISION); -+ -+ /* Configure GENI primitive table. */ -+ for (i = 0; i < hdr->cfg_size_in_items; i++) -+ writel_relaxed(cfg_val_arr[i], -+ se->base + SE_GENI_CFG_REG0 + (cfg_idx_arr[i] * sizeof(u32))); -+ -+ /* Configure condition for assertion of RX_RFR_WATERMARK condition. */ -+ reg_value = geni_se_get_rx_fifo_depth(se); -+ writel_relaxed(reg_value - 2, se->base + SE_GENI_RX_RFR_WATERMARK_REG); -+ -+ /* Let hardware control CGC */ -+ geni_setbits32(se->base + GENI_OUTPUT_CTRL, DEFAULT_IO_OUTPUT_CTRL_MSK); -+ -+ ret = geni_configure_xfer_mode(se); -+ if (ret) -+ goto err_resource; -+ -+ geni_enable_interrupts(se); -+ -+ geni_write_fw_revision(se, hdr->serial_protocol, hdr->fw_version); -+ -+ ramn_cnt = hdr->fw_size_in_items; -+ if (hdr->fw_size_in_items % 2 != 0) -+ ramn_cnt++; -+ -+ if (ramn_cnt >= MAX_GENI_CFG_RAMn_CNT) -+ goto err_resource; -+ -+ /* Program RAM address space. */ -+ memcpy_toio(se->base + SE_GENI_CFG_RAMN, fw_data, ramn_cnt * sizeof(u32)); -+ -+ /* Put default values on GENI's output pads. */ -+ writel_relaxed(0x1, se->base + GENI_FORCE_DEFAULT_REG); -+ -+ /* High to low SCLK and HCLK to finish RAM. */ -+ geni_setbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF); -+ geni_setbits32(se->base + SE_GENI_CLK_CTRL, SER_CLK_SEL); -+ geni_clrbits32(se->base + SE_GENI_CGC_CTRL, PROG_RAM_SCLK_OFF | PROG_RAM_HCLK_OFF); -+ -+ /* Serial engine DMA interface is enabled. */ -+ geni_setbits32(se->base + SE_DMA_IF_EN, DMA_IF_EN); -+ -+ /* Enable or disable FIFO interface of the serial engine. */ -+ if (se->mode == GENI_SE_FIFO) -+ geni_clrbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE); -+ else -+ geni_setbits32(se->base + SE_FIFO_IF_DISABLE, FIFO_IF_DISABLE); -+ -+err_resource: -+ geni_se_resources_off(se); -+err: -+ geni_icc_disable(se); -+ return ret; -+} -+ -+/** -+ * qup_fw_load() - Initiate firmware load. -+ * @se: Pointer to a structure representing SE-related resources. -+ * @fw_name: Name of the firmware. -+ * -+ * Load the firmware into a specific SE. Read the associated ELF file, -+ * copy the data into a buffer in kernel space using the request_firmware API, write the -+ * data into the SE's IRAM register, and then free the buffers. Handle firmware loading -+ * and parsing for a specific protocol. -+ * -+ * Return: 0 if successful, otherwise return an error value. -+ */ -+static int qup_fw_load(struct geni_se *se, const char *fw_name) -+{ -+ int ret; -+ const struct firmware *fw; -+ struct device *dev = se->dev; -+ -+ ret = request_firmware(&fw, fw_name, dev); -+ if (ret) { -+ dev_err(dev, "request_firmware failed for %d: %d\n", se->protocol, ret); -+ return ret; -+ } -+ -+ ret = geni_load_se_fw(se, fw); -+ -+ release_firmware(fw); -+ -+ return ret; -+} -+ -+/** -+ * geni_load_se_firmware() - Initiate firmware loading. -+ * @se: Serial engine details. -+ * @protocol: Protocol (SPI, I2C, or UART) for which the firmware is to be loaded. -+ * -+ * If the device tree properties are configured to load QUP firmware and the firmware -+ * is not already loaded, start the firmware loading process. If the device tree properties -+ * are not defined, skip loading the firmware, assuming it is already loaded by TZ. -+ * -+ * Return: 0 if successful, otherwise return an error value. -+ */ -+int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol) -+{ -+ const char *fw_name; -+ int ret; -+ -+ if (protocol >= MAX_PROTOCOL) { -+ dev_err(se->dev, "Invalid geni-se protocol: %d", protocol); -+ return -EINVAL; -+ } -+ -+ ret = device_property_read_string(se->wrapper->dev, "firmware-name", &fw_name); -+ if (ret) -+ return -EINVAL; -+ -+ se->protocol = protocol; -+ -+ if (of_property_read_bool(se->dev->of_node, "qcom,enable-gsi-dma")) -+ se->mode = GENI_GPI_DMA; -+ else -+ se->mode = GENI_SE_FIFO; -+ -+ /* GSI mode is not supported by the UART driver; therefore, setting FIFO mode */ -+ if (protocol == GENI_SE_UART) -+ se->mode = GENI_SE_FIFO; -+ -+ ret = qup_fw_load(se, fw_name); -+ if (ret) -+ return ret; -+ -+ dev_dbg(se->dev, "Firmware load for %s protocol is successful for xfer mode %d\n", -+ protocol_name[se->protocol], se->mode); -+ return 0; -+} -+EXPORT_SYMBOL_GPL(geni_load_se_firmware); -+ - static int geni_se_probe(struct platform_device *pdev) - { - struct device *dev = &pdev->dev; -diff --git a/src/include/linux/soc/qcom/geni-se.h b/src/include/linux/soc/qcom/geni-se.h -index 2996a3c28ef3..6b75171d65ec 100644 ---- a/src/include/linux/soc/qcom/geni-se.h -+++ b/src/include/linux/soc/qcom/geni-se.h -@@ -1,11 +1,13 @@ - /* SPDX-License-Identifier: GPL-2.0 */ - /* - * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. -+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. - */ - - #ifndef _LINUX_QCOM_GENI_SE - #define _LINUX_QCOM_GENI_SE - -+#include - #include - - /** -@@ -36,6 +38,7 @@ enum geni_se_protocol_type { - GENI_SE_I2C, - GENI_SE_I3C, - GENI_SE_SPI_SLAVE, -+ GENI_SE_INVALID_PROTO = 255, - }; - - struct geni_wrapper; -@@ -61,6 +64,8 @@ struct geni_icc_path { - * @num_clk_levels: Number of valid clock levels in clk_perf_tbl - * @clk_perf_tbl: Table of clock frequency input to serial engine clock - * @icc_paths: Array of ICC paths for SE -+ * @mode: Transfer mode se fifo, dma or gsi. -+ * @protocol: Protocol spi or i2c or serial. - */ - struct geni_se { - void __iomem *base; -@@ -70,24 +75,32 @@ struct geni_se { - unsigned int num_clk_levels; - unsigned long *clk_perf_tbl; - struct geni_icc_path icc_paths[3]; -+ enum geni_se_xfer_mode mode; -+ enum geni_se_protocol_type protocol; - }; - - /* Common SE registers */ -+#define SE_GENI_INIT_CFG_REVISION 0x0 -+#define SE_GENI_S_INIT_CFG_REVISION 0x4 - #define GENI_FORCE_DEFAULT_REG 0x20 - #define GENI_OUTPUT_CTRL 0x24 -+#define SE_GENI_CGC_CTRL 0x28 - #define SE_GENI_STATUS 0x40 - #define GENI_SER_M_CLK_CFG 0x48 - #define GENI_SER_S_CLK_CFG 0x4c - #define GENI_IF_DISABLE_RO 0x64 --#define GENI_FW_REVISION_RO 0x68 -+#define SE_GENI_FW_REVISION_RO 0x68 -+#define SE_GENI_S_FW_REVISION_RO 0x6c - #define SE_GENI_CLK_SEL 0x7c - #define SE_GENI_CFG_SEQ_START 0x84 -+#define SE_GENI_CFG_REG0 0x100 - #define SE_GENI_DMA_MODE_EN 0x258 - #define SE_GENI_M_CMD0 0x600 - #define SE_GENI_M_CMD_CTRL_REG 0x604 - #define SE_GENI_M_IRQ_STATUS 0x610 - #define SE_GENI_M_IRQ_EN 0x614 - #define SE_GENI_M_IRQ_CLEAR 0x618 -+#define SE_GENI_S_IRQ_ENABLE 0x644 - #define SE_GENI_M_IRQ_EN_SET 0x61c - #define SE_GENI_M_IRQ_EN_CLEAR 0x620 - #define SE_GENI_S_CMD0 0x630 -@@ -109,13 +122,22 @@ struct geni_se { - #define SE_GENI_S_GP_LENGTH 0x914 - #define SE_DMA_TX_IRQ_STAT 0xc40 - #define SE_DMA_TX_IRQ_CLR 0xc44 -+#define SE_DMA_TX_IRQ_EN_SET 0xc4c - #define SE_DMA_TX_FSM_RST 0xc58 - #define SE_DMA_RX_IRQ_STAT 0xd40 - #define SE_DMA_RX_IRQ_CLR 0xd44 -+#define SE_DMA_RX_IRQ_EN_SET 0xd4c - #define SE_DMA_RX_LEN_IN 0xd54 - #define SE_DMA_RX_FSM_RST 0xd58 - #define SE_HW_PARAM_0 0xe24 - #define SE_HW_PARAM_1 0xe28 -+#define SE_DMA_GENERAL_CFG 0xe30 -+#define SE_GENI_FW_REVISION 0x1000 -+#define SE_S_FW_REVISION 0x1004 -+#define SE_GENI_CFG_RAMN 0x1010 -+#define SE_GENI_CLK_CTRL 0x2000 -+#define SE_DMA_IF_EN 0x2004 -+#define SE_FIFO_IF_DISABLE 0x2008 - - /* GENI_FORCE_DEFAULT_REG fields */ - #define FORCE_DEFAULT BIT(0) -@@ -137,7 +159,7 @@ struct geni_se { - - /* GENI_FW_REVISION_RO fields */ - #define FW_REV_PROTOCOL_MSK GENMASK(15, 8) --#define FW_REV_PROTOCOL_SHFT 8 -+#define FW_REV_VERSION_MSK GENMASK(7, 0) - - /* GENI_CLK_SEL fields */ - #define CLK_SEL_MSK GENMASK(2, 0) -@@ -325,9 +347,9 @@ static inline u32 geni_se_read_proto(struct geni_se *se) - { - u32 val; - -- val = readl_relaxed(se->base + GENI_FW_REVISION_RO); -+ val = readl_relaxed(se->base + SE_GENI_FW_REVISION_RO); - -- return (val & FW_REV_PROTOCOL_MSK) >> FW_REV_PROTOCOL_SHFT; -+ return FIELD_GET(FW_REV_PROTOCOL_MSK, val); - } - - /** -@@ -531,5 +553,7 @@ void geni_icc_set_tag(struct geni_se *se, u32 tag); - int geni_icc_enable(struct geni_se *se); - - int geni_icc_disable(struct geni_se *se); -+ -+int geni_load_se_firmware(struct geni_se *se, enum geni_se_protocol_type protocol); - #endif - #endif -diff --git a/src/include/linux/soc/qcom/qup-fw-load.h b/src/include/linux/soc/qcom/qup-fw-load.h -new file mode 100644 -index 000000000000..94a6c4c10bcf ---- /dev/null -+++ b/src/include/linux/soc/qcom/qup-fw-load.h -@@ -0,0 +1,93 @@ -+/* SPDX-License-Identifier: GPL-2.0 */ -+/* -+ * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. -+ */ -+#ifndef _LINUX_QCOM_QUP_FW_LOAD -+#define _LINUX_QCOM_QUP_FW_LOAD -+ -+#include -+ -+/*Magic numbers*/ -+#define MAGIC_NUM_SE 0x57464553 -+ -+#define MAX_GENI_CFG_RAMn_CNT 455 -+ -+#define MI_PBT_NON_PAGED_SEGMENT 0x0 -+#define MI_PBT_HASH_SEGMENT 0x2 -+#define MI_PBT_NOTUSED_SEGMENT 0x3 -+#define MI_PBT_SHARED_SEGMENT 0x4 -+ -+#define MI_PBT_FLAG_PAGE_MODE BIT(20) -+#define MI_PBT_FLAG_SEGMENT_TYPE GENMASK(26, 24) -+#define MI_PBT_FLAG_ACCESS_TYPE GENMASK(23, 21) -+ -+#define MI_PBT_PAGE_MODE_VALUE(x) FIELD_GET(MI_PBT_FLAG_PAGE_MODE, x) -+ -+#define MI_PBT_SEGMENT_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_SEGMENT_TYPE, x) -+ -+#define MI_PBT_ACCESS_TYPE_VALUE(x) FIELD_GET(MI_PBT_FLAG_ACCESS_TYPE, x) -+ -+#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \ -+ M_IO_DATA_DEASSERT_EN | \ -+ M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \ -+ M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \ -+ M_TX_FIFO_WR_ERR_EN) -+ -+/* DMA_TX/RX_IRQ_EN fields */ -+#define DMA_DONE_EN BIT(0) -+#define SBE_EN BIT(2) -+#define RESET_DONE_EN BIT(3) -+#define FLUSH_DONE_EN BIT(4) -+ -+/* GENI_CLK_CTRL fields */ -+#define SER_CLK_SEL BIT(0) -+ -+/* GENI_DMA_IF_EN fields */ -+#define DMA_IF_EN BIT(0) -+ -+#define QUPV3_COMMON_CFG 0x120 -+#define FAST_SWITCH_TO_HIGH_DISABLE BIT(0) -+ -+#define QUPV3_SE_AHB_M_CFG 0x118 -+#define AHB_M_CLK_CGC_ON BIT(0) -+ -+#define QUPV3_COMMON_CGC_CTRL 0x21C -+#define COMMON_CSR_SLV_CLK_CGC_ON BIT(0) -+ -+/* access ports */ -+#define geni_setbits32(_addr, _v) writel_relaxed(readl_relaxed(_addr) | (_v), _addr) -+#define geni_clrbits32(_addr, _v) writel_relaxed(readl_relaxed(_addr) & ~(_v), _addr) -+ -+/** -+ * struct se_fw_hdr - Serial Engine firmware configuration header -+ * -+ * This structure defines metadata for the Serial Engine (SE) firmware -+ * configuration. Although it is embedded within an ELF segment, it is -+ * not part of the ELF format itself. -+ * -+ * @magic: Set to 'SEFW' -+ * @version: Structure version number -+ * @core_version: QUPV3 hardware version -+ * @serial_protocol: Encoded in GENI_FW_REVISION -+ * @fw_version: Firmware version, from GENI_FW_REVISION -+ * @cfg_version: Configuration version, from GENI_INIT_CFG_REVISION -+ * @fw_size_in_items: Number of 32-bit words in GENI_FW_RAM -+ * @fw_offset: Byte offset to GENI_FW_RAM array -+ * @cfg_size_in_items: Number of GENI_FW_CFG index/value pairs -+ * @cfg_idx_offset: Byte offset to GENI_FW_CFG index array -+ * @cfg_val_offset: Byte offset to GENI_FW_CFG values array -+ */ -+struct se_fw_hdr { -+ __le32 magic; -+ u32 version; -+ u32 core_version; -+ u16 serial_protocol; -+ u16 fw_version; -+ u16 cfg_version; -+ u16 fw_size_in_items; -+ u16 fw_offset; -+ u16 cfg_size_in_items; -+ u16 cfg_idx_offset; -+ u16 cfg_val_offset; -+}; -+#endif /* _LINUX_QCOM_QUP_FW_LOAD */ --- -2.50.1 - diff --git a/debian/patches/linux/0014-i2c-qcom-geni-Load-i2c-qup-Firmware-from-linux-side.patch b/debian/patches/linux/0014-i2c-qcom-geni-Load-i2c-qup-Firmware-from-linux-side.patch deleted file mode 100644 index 9ef5420..0000000 --- a/debian/patches/linux/0014-i2c-qcom-geni-Load-i2c-qup-Firmware-from-linux-side.patch +++ /dev/null @@ -1,38 +0,0 @@ -From 59ca365cf368601dc6028e67f1b3000d18032fae Mon Sep 17 00:00:00 2001 -From: Viken Dadhaniya -Date: Tue, 24 Jun 2025 15:21:00 +0530 -Subject: [PATCH 14/49] i2c: qcom-geni: Load i2c qup Firmware from linux side - -Add provision to load firmware of Serial engine for I2C protocol from -Linux Execution Environment on running on APPS processor. - -Co-developed-by: Mukesh Kumar Savaliya -Signed-off-by: Mukesh Kumar Savaliya -Signed-off-by: Viken Dadhaniya -Acked-by: Andi Shyti ---- - drivers/i2c/busses/i2c-qcom-geni.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/src/drivers/i2c/busses/i2c-qcom-geni.c b/src/drivers/i2c/busses/i2c-qcom-geni.c -index 13889f52b6f7..11f1089edf37 100644 ---- a/src/drivers/i2c/busses/i2c-qcom-geni.c -+++ b/src/drivers/i2c/busses/i2c-qcom-geni.c -@@ -870,7 +870,13 @@ static int geni_i2c_probe(struct platform_device *pdev) - goto err_clk; - } - proto = geni_se_read_proto(&gi2c->se); -- if (proto != GENI_SE_I2C) { -+ if (proto == GENI_SE_INVALID_PROTO) { -+ ret = geni_load_se_firmware(&gi2c->se, GENI_SE_I2C); -+ if (ret) { -+ dev_err_probe(dev, ret, "i2c firmware load failed ret: %d\n", ret); -+ goto err_resources; -+ } -+ } else if (proto != GENI_SE_I2C) { - ret = dev_err_probe(dev, -ENXIO, "Invalid proto %d\n", proto); - goto err_resources; - } --- -2.50.1 - diff --git a/debian/patches/linux/0015-spi-geni-qcom-Load-spi-qup-Firmware-from-linux-side.patch b/debian/patches/linux/0015-spi-geni-qcom-Load-spi-qup-Firmware-from-linux-side.patch deleted file mode 100644 index e60e128..0000000 --- a/debian/patches/linux/0015-spi-geni-qcom-Load-spi-qup-Firmware-from-linux-side.patch +++ /dev/null @@ -1,35 +0,0 @@ -From 319a13b9fca592987fd266b87fbb2fea5f624708 Mon Sep 17 00:00:00 2001 -From: Viken Dadhaniya -Date: Tue, 24 Jun 2025 15:21:01 +0530 -Subject: [PATCH 15/49] spi: geni-qcom: Load spi qup Firmware from linux side - -Add provision to load firmware of Serial engine for SPI protocol from -Linux Execution Environment on running on APPS processor. - -Co-developed-by: Mukesh Kumar Savaliya -Signed-off-by: Mukesh Kumar Savaliya -Signed-off-by: Viken Dadhaniya ---- - drivers/spi/spi-geni-qcom.c | 6 ++++++ - 1 file changed, 6 insertions(+) - -diff --git a/src/drivers/spi/spi-geni-qcom.c b/src/drivers/spi/spi-geni-qcom.c -index 768d7482102a..a0d8d3425c6c 100644 ---- a/src/drivers/spi/spi-geni-qcom.c -+++ b/src/drivers/spi/spi-geni-qcom.c -@@ -671,6 +671,12 @@ static int spi_geni_init(struct spi_geni_master *mas) - goto out_pm; - } - spi_slv_setup(mas); -+ } else if (proto == GENI_SE_INVALID_PROTO) { -+ ret = geni_load_se_firmware(se, GENI_SE_SPI); -+ if (ret) { -+ dev_err(mas->dev, "spi master firmware load failed ret: %d\n", ret); -+ goto out_pm; -+ } - } else if (proto != GENI_SE_SPI) { - dev_err(mas->dev, "Invalid proto %d\n", proto); - goto out_pm; --- -2.50.1 - diff --git a/debian/patches/linux/0016-serial-qcom-geni-Load-UART-qup-Firmware-from-linux-s.patch b/debian/patches/linux/0016-serial-qcom-geni-Load-UART-qup-Firmware-from-linux-s.patch deleted file mode 100644 index b3f7d37..0000000 --- a/debian/patches/linux/0016-serial-qcom-geni-Load-UART-qup-Firmware-from-linux-s.patch +++ /dev/null @@ -1,38 +0,0 @@ -From b29889067647460832c27064e3be1d07f4f9f889 Mon Sep 17 00:00:00 2001 -From: Viken Dadhaniya -Date: Tue, 24 Jun 2025 15:21:02 +0530 -Subject: [PATCH 16/49] serial: qcom-geni: Load UART qup Firmware from linux - side - -Add provision to load firmware of Serial engine for UART protocol from -Linux Execution Environment on running on APPS processor. - -Co-developed-by: Mukesh Kumar Savaliya -Signed-off-by: Mukesh Kumar Savaliya -Signed-off-by: Viken Dadhaniya ---- - drivers/tty/serial/qcom_geni_serial.c | 8 +++++++- - 1 file changed, 7 insertions(+), 1 deletion(-) - -diff --git a/src/drivers/tty/serial/qcom_geni_serial.c b/src/drivers/tty/serial/qcom_geni_serial.c -index 0293b6210aa6..9f905ae3c127 100644 ---- a/src/drivers/tty/serial/qcom_geni_serial.c -+++ b/src/drivers/tty/serial/qcom_geni_serial.c -@@ -1161,7 +1161,13 @@ static int qcom_geni_serial_port_setup(struct uart_port *uport) - int ret; - - proto = geni_se_read_proto(&port->se); -- if (proto != GENI_SE_UART) { -+ if (proto == GENI_SE_INVALID_PROTO) { -+ ret = geni_load_se_firmware(&port->se, GENI_SE_UART); -+ if (ret) { -+ dev_err(uport->dev, "UART firmware load failed ret: %d\n", ret); -+ return ret; -+ } -+ } else if (proto != GENI_SE_UART) { - dev_err(uport->dev, "Invalid FW loaded, proto: %d\n", proto); - return -ENXIO; - } --- -2.50.1 - diff --git a/debian/patches/linux/0017-firmware-psci-Read-and-use-vendor-reset-types.patch b/debian/patches/linux/0017-firmware-psci-Read-and-use-vendor-reset-types.patch deleted file mode 100644 index b8c10c4..0000000 --- a/debian/patches/linux/0017-firmware-psci-Read-and-use-vendor-reset-types.patch +++ /dev/null @@ -1,176 +0,0 @@ -From 5afda70625d384bb445f97e0fb82f65331ccc006 Mon Sep 17 00:00:00 2001 -From: Elliot Berman -Date: Mon, 3 Mar 2025 13:08:31 -0800 -Subject: [PATCH 17/49] firmware: psci: Read and use vendor reset types - -SoC vendors have different types of resets and are controlled through -various registers. For instance, Qualcomm chipsets can reboot to a -"download mode" that allows a RAM dump to be collected. Another example -is they also support writing a cookie that can be read by bootloader -during next boot. PSCI offers a mechanism, SYSTEM_RESET2, for these -vendor reset types to be implemented without requiring drivers for every -register/cookie. - -Add support in PSCI to statically map reboot mode commands from -userspace to a vendor reset and cookie value using the device tree. - -A separate initcall is needed to parse the devicetree, instead of using -psci_dt_init because mm isn't sufficiently set up to allocate memory. - -Reboot mode framework is close but doesn't quite fit with the -design and requirements for PSCI SYSTEM_RESET2. Some of these issues can -be solved but doesn't seem reasonable in sum: - 1. reboot mode registers against the reboot_notifier_list, which is too - early to call SYSTEM_RESET2. PSCI would need to remember the reset - type from the reboot-mode framework callback and use it - psci_sys_reset. - 2. reboot mode assumes only one cookie/parameter is described in the - device tree. SYSTEM_RESET2 uses 2: one for the type and one for - cookie. - 3. psci cpuidle driver already registers a driver against the - arm,psci-1.0 compatible. Refactoring would be needed to have both a - cpuidle and reboot-mode driver. - -Signed-off-by: Elliot Berman -Reviewed-by: Florian Fainelli -Tested-by: Florian Fainelli ---- - drivers/firmware/psci/psci.c | 105 +++++++++++++++++++++++++++++++++++ - 1 file changed, 105 insertions(+) - -diff --git a/src/drivers/firmware/psci/psci.c b/src/drivers/firmware/psci/psci.c -index 38ca190d4a22..cbe28182dd64 100644 ---- a/src/drivers/firmware/psci/psci.c -+++ b/src/drivers/firmware/psci/psci.c -@@ -80,6 +80,14 @@ static u32 psci_cpu_suspend_feature; - static bool psci_system_reset2_supported; - static bool psci_system_off2_hibernate_supported; - -+struct psci_reset_param { -+ const char *mode; -+ u32 reset_type; -+ u32 cookie; -+}; -+static struct psci_reset_param *psci_reset_params __ro_after_init; -+static size_t num_psci_reset_params __ro_after_init; -+ - static inline bool psci_has_ext_power_state(void) - { - return psci_cpu_suspend_feature & -@@ -306,9 +314,39 @@ static int get_set_conduit_method(const struct device_node *np) - return 0; - } - -+static int psci_vendor_system_reset2(const char *cmd) -+{ -+ unsigned long ret; -+ size_t i; -+ -+ for (i = 0; i < num_psci_reset_params; i++) { -+ if (!strcmp(psci_reset_params[i].mode, cmd)) { -+ ret = invoke_psci_fn(PSCI_FN_NATIVE(1_1, SYSTEM_RESET2), -+ psci_reset_params[i].reset_type, -+ psci_reset_params[i].cookie, 0); -+ /* -+ * if vendor reset fails, log it and fall back to -+ * architecture reset types -+ */ -+ pr_err("failed to perform reset \"%s\": %ld\n", cmd, -+ (long)ret); -+ return 0; -+ } -+ } -+ -+ return -ENOENT; -+} -+ - static int psci_sys_reset(struct notifier_block *nb, unsigned long action, - void *data) - { -+ /* -+ * try to do the vendor system_reset2 -+ * If there wasn't a matching command, fall back to architectural resets -+ */ -+ if (data && !psci_vendor_system_reset2(data)) -+ return NOTIFY_DONE; -+ - if ((reboot_mode == REBOOT_WARM || reboot_mode == REBOOT_SOFT) && - psci_system_reset2_supported) { - /* -@@ -795,6 +833,73 @@ static const struct of_device_id psci_of_match[] __initconst = { - {}, - }; - -+#define REBOOT_PREFIX "mode-" -+ -+static int __init psci_init_system_reset2_modes(void) -+{ -+ const size_t len = strlen(REBOOT_PREFIX); -+ struct psci_reset_param *param; -+ struct device_node *psci_np __free(device_node) = NULL; -+ struct device_node *np __free(device_node) = NULL; -+ struct property *prop; -+ size_t count = 0; -+ u32 magic[2]; -+ int num; -+ -+ if (!psci_system_reset2_supported) -+ return 0; -+ -+ psci_np = of_find_matching_node(NULL, psci_of_match); -+ if (!psci_np) -+ return 0; -+ -+ np = of_find_node_by_name(psci_np, "reset-types"); -+ if (!np) -+ return 0; -+ -+ for_each_property_of_node(np, prop) { -+ if (strncmp(prop->name, REBOOT_PREFIX, len)) -+ continue; -+ num = of_property_count_u32_elems(np, prop->name); -+ if (num != 1 && num != 2) -+ continue; -+ -+ count++; -+ } -+ -+ param = psci_reset_params = -+ kcalloc(count, sizeof(*psci_reset_params), GFP_KERNEL); -+ if (!psci_reset_params) -+ return -ENOMEM; -+ -+ for_each_property_of_node(np, prop) { -+ if (strncmp(prop->name, REBOOT_PREFIX, len)) -+ continue; -+ -+ num = of_property_read_variable_u32_array(np, prop->name, magic, -+ 1, ARRAY_SIZE(magic)); -+ if (num < 0) { -+ pr_warn("Failed to parse vendor reboot mode %s\n", -+ param->mode); -+ kfree_const(param->mode); -+ continue; -+ } -+ -+ param->mode = kstrdup_const(prop->name + len, GFP_KERNEL); -+ if (!param->mode) -+ continue; -+ -+ /* Force reset type to be in vendor space */ -+ param->reset_type = PSCI_1_1_RESET_TYPE_VENDOR_START | magic[0]; -+ param->cookie = num > 1 ? magic[1] : 0; -+ param++; -+ num_psci_reset_params++; -+ } -+ -+ return 0; -+} -+arch_initcall(psci_init_system_reset2_modes); -+ - int __init psci_dt_init(void) - { - struct device_node *np; --- -2.50.1 - diff --git a/debian/patches/linux/0018-dt-bindings-display-simple-bridge-Add-ra620-compatib.patch b/debian/patches/linux/0018-dt-bindings-display-simple-bridge-Add-ra620-compatib.patch deleted file mode 100644 index 6fb35ec..0000000 --- a/debian/patches/linux/0018-dt-bindings-display-simple-bridge-Add-ra620-compatib.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 23281b6ebce699c89505d233260dd04b4ccc3f2d Mon Sep 17 00:00:00 2001 -From: Andy Yan -Date: Thu, 3 Apr 2025 11:37:32 +0800 -Subject: [PATCH 18/49] dt-bindings: display: simple-bridge: Add ra620 - compatible - -RA620 is a DP to HDMI bridge converter from RADXA, which first -found be used on ROCK 5 ITX. - -This chip can be used without involving software. - -Signed-off-by: Andy Yan - -Acked-by: Krzysztof Kozlowski ---- - .../devicetree/bindings/display/bridge/simple-bridge.yaml | 1 + - 1 file changed, 1 insertion(+) - -diff --git a/src/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml b/src/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml -index 43cf4df9811a..421f99ca42d9 100644 ---- a/src/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml -+++ b/src/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml -@@ -28,6 +28,7 @@ properties: - - enum: - - adi,adv7123 - - dumb-vga-dac -+ - radxa,ra620 - - ti,opa362 - - ti,ths8134 - - ti,ths8135 --- -2.50.1 - diff --git a/debian/patches/linux/0019-drm-birdge-simple-bridge-Add-support-for-radxa-ra620.patch b/debian/patches/linux/0019-drm-birdge-simple-bridge-Add-support-for-radxa-ra620.patch deleted file mode 100644 index 15ceb4a..0000000 --- a/debian/patches/linux/0019-drm-birdge-simple-bridge-Add-support-for-radxa-ra620.patch +++ /dev/null @@ -1,36 +0,0 @@ -From 00db540585aad7c29f73ce8e018cc0d90f5d8346 Mon Sep 17 00:00:00 2001 -From: Andy Yan -Date: Thu, 3 Apr 2025 11:37:33 +0800 -Subject: [PATCH 19/49] drm/birdge: simple-bridge: Add support for radxa ra620 - -The RA620 is an active DP to HDMI converter chip, basically -no software is involved to drive it. - -Add it to simple bridge to make it can be find by the drm bridge chain. - -Signed-off-by: Andy Yan - -Reviewed-by: Dmitry Baryshkov ---- - drivers/gpu/drm/bridge/simple-bridge.c | 5 +++++ - 1 file changed, 5 insertions(+) - -diff --git a/src/drivers/gpu/drm/bridge/simple-bridge.c b/src/drivers/gpu/drm/bridge/simple-bridge.c -index 70db5b99e5bb..df2d8106ee75 100644 ---- a/src/drivers/gpu/drm/bridge/simple-bridge.c -+++ b/src/drivers/gpu/drm/bridge/simple-bridge.c -@@ -261,6 +261,11 @@ static const struct of_device_id simple_bridge_match[] = { - .timings = &default_bridge_timings, - .connector_type = DRM_MODE_CONNECTOR_VGA, - }, -+ }, { -+ .compatible = "radxa,ra620", -+ .data = &(const struct simple_bridge_info) { -+ .connector_type = DRM_MODE_CONNECTOR_HDMIA, -+ }, - }, { - .compatible = "ti,opa362", - .data = &(const struct simple_bridge_info) { --- -2.50.1 - diff --git a/debian/patches/linux/0020-scsi-ufs-qcom-temporarily-force-to-rate-A.patch b/debian/patches/linux/0020-scsi-ufs-qcom-temporarily-force-to-rate-A.patch deleted file mode 100644 index 5b39f7e..0000000 --- a/debian/patches/linux/0020-scsi-ufs-qcom-temporarily-force-to-rate-A.patch +++ /dev/null @@ -1,25 +0,0 @@ -From f9ce874af21c8a59b3ab4597f76a07e6bf5fbf8b Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Mon, 9 Jun 2025 10:44:53 +0800 -Subject: [PATCH 20/49] scsi: ufs: qcom: temporarily force to rate A - ---- - drivers/ufs/host/ufs-qcom.c | 2 ++ - 1 file changed, 2 insertions(+) - -diff --git a/src/drivers/ufs/host/ufs-qcom.c b/src/drivers/ufs/host/ufs-qcom.c -index 18a978452001..632f54d8e785 100644 ---- a/src/drivers/ufs/host/ufs-qcom.c -+++ b/src/drivers/ufs/host/ufs-qcom.c -@@ -501,6 +501,8 @@ static int ufs_qcom_power_up_sequence(struct ufs_hba *hba) - host_params->hs_rate = PA_HS_MODE_B; - } - -+ host_params->hs_rate = PA_HS_MODE_A; -+ - mode = host_params->hs_rate == PA_HS_MODE_B ? PHY_MODE_UFS_HS_B : PHY_MODE_UFS_HS_A; - - /* Reset UFS Host Controller and PHY */ --- -2.50.1 - diff --git a/debian/patches/linux/0021-phy-qcom-qmp-ufs-Fix-HS-G4-PHY-init-table-for-sc7280.patch b/debian/patches/linux/0021-phy-qcom-qmp-ufs-Fix-HS-G4-PHY-init-table-for-sc7280.patch deleted file mode 100644 index 88739ee..0000000 --- a/debian/patches/linux/0021-phy-qcom-qmp-ufs-Fix-HS-G4-PHY-init-table-for-sc7280.patch +++ /dev/null @@ -1,36 +0,0 @@ -From e1a1aa0ccbd5768d22fdf3df6e8bcbebb4c9f270 Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Fri, 13 Jun 2025 22:41:48 +0800 -Subject: [PATCH 21/49] phy: qcom-qmp-ufs: Fix HS-G4 PHY init table for sc7280 - -The PHY is limited to operating in HS-G3 mode during the initial PCS -registers initialization. Extra PHY init sequence is required to allow -HS-G4 mode to work when needed. - -Fixes: 8abe9792d1ff ("phy: qcom-qmp-ufs: Add Phy Configuration support for SC7280") -Signed-off-by: Xilin Wu ---- - drivers/phy/qualcomm/phy-qcom-qmp-ufs.c | 7 +++++++ - 1 file changed, 7 insertions(+) - -diff --git a/src/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/src/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c -index b33e2e2b5014..7797be329d75 100644 ---- a/src/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c -+++ b/src/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c -@@ -570,6 +570,13 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = { - - static const struct qmp_phy_init_tbl sm8150_ufsphy_hs_g4_pcs[] = { - QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x10), -+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_PLL_CNTL, 0x0b), -+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB, 0x2d), -+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB, 0xb0), -+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND, 0xff), -+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND, 0x1b), -+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY, 0x04), -+ QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY, 0x04), - QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL, 0x0a), - }; - --- -2.50.1 - diff --git a/debian/patches/linux/0022-arm64-dts-qcom-sc7280-add-OPP-table-support-to-PCIe-.patch b/debian/patches/linux/0022-arm64-dts-qcom-sc7280-add-OPP-table-support-to-PCIe-.patch deleted file mode 100644 index 05e85f4..0000000 --- a/debian/patches/linux/0022-arm64-dts-qcom-sc7280-add-OPP-table-support-to-PCIe-.patch +++ /dev/null @@ -1,80 +0,0 @@ -From 07915d73191694ec1dfb186861ae31d439469808 Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Wed, 11 Jun 2025 23:24:20 +0800 -Subject: [PATCH 22/49] arm64: dts: qcom: sc7280: add OPP table support to PCIe - 1 - ---- - arch/arm64/boot/dts/qcom/sc7280.dtsi | 47 ++++++++++++++++++++++++++++ - 1 file changed, 47 insertions(+) - -diff --git a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -index 6149b1ddc85b..5e2cb173cd37 100644 ---- a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -+++ b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -@@ -2393,8 +2393,16 @@ pcie1: pcie@1c08000 { - resets = <&gcc GCC_PCIE_1_BCR>; - reset-names = "pci"; - -+ interconnects = <&aggre1_noc MASTER_PCIE_1 QCOM_ICC_TAG_ALWAYS -+ &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, -+ <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS -+ &cnoc2 SLAVE_PCIE_1 QCOM_ICC_TAG_ALWAYS>; -+ interconnect-names = "pcie-mem", "cpu-pcie"; -+ - power-domains = <&gcc GCC_PCIE_1_GDSC>; - -+ operating-points-v2 = <&pcie1_opp_table>; -+ - phys = <&pcie1_phy>; - phy-names = "pciephy"; - -@@ -2408,6 +2416,45 @@ pcie1: pcie@1c08000 { - - status = "disabled"; - -+ pcie1_opp_table: opp-table { -+ compatible = "operating-points-v2"; -+ -+ /* GEN 1 x1 */ -+ opp-2500000 { -+ opp-hz = /bits/ 64 <2500000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <250000 1>; -+ }; -+ -+ /* GEN 1 x2 and GEN 2 x1 */ -+ opp-5000000 { -+ opp-hz = /bits/ 64 <5000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <500000 1>; -+ }; -+ -+ /* GEN 2 x2 */ -+ opp-10000000 { -+ opp-hz = /bits/ 64 <10000000>; -+ required-opps = <&rpmhpd_opp_low_svs>; -+ opp-peak-kBps = <1000000 1>; -+ }; -+ -+ /* GEN 3 x1 */ -+ opp-8000000 { -+ opp-hz = /bits/ 64 <8000000>; -+ required-opps = <&rpmhpd_opp_nom>; -+ opp-peak-kBps = <984500 1>; -+ }; -+ -+ /* GEN 3 x2 */ -+ opp-16000000 { -+ opp-hz = /bits/ 64 <16000000>; -+ required-opps = <&rpmhpd_opp_svs>; -+ opp-peak-kBps = <1969000 1>; -+ }; -+ }; -+ - pcie@0 { - device_type = "pci"; - reg = <0x0 0x0 0x0 0x0 0x0>; --- -2.50.1 - diff --git a/debian/patches/linux/0023-drm-msm-dpu-Add-missing-caps-and-blocks-to-sc7280-ca.patch b/debian/patches/linux/0023-drm-msm-dpu-Add-missing-caps-and-blocks-to-sc7280-ca.patch deleted file mode 100644 index cc55450..0000000 --- a/debian/patches/linux/0023-drm-msm-dpu-Add-missing-caps-and-blocks-to-sc7280-ca.patch +++ /dev/null @@ -1,98 +0,0 @@ -From 1c3755dc1a1b0bb50d61e7e1240bb73785e77dee Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Mon, 9 Jun 2025 10:46:02 +0800 -Subject: [PATCH 23/49] drm/msm/dpu: Add missing caps and blocks to sc7280 - catalog - -This enables 4K@30 via DisplayPort. ---- - .../msm/disp/dpu1/catalog/dpu_7_2_sc7280.h | 28 +++++++++++++++---- - 1 file changed, 23 insertions(+), 5 deletions(-) - -diff --git a/src/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h b/src/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h -index e9625c48c567..dab60c59e84c 100644 ---- a/src/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h -+++ b/src/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_7_2_sc7280.h -@@ -9,9 +9,11 @@ - - static const struct dpu_caps sc7280_dpu_caps = { - .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, -- .max_mixer_blendstages = 0x7, -+ .max_mixer_blendstages = 0x9, -+ .has_src_split = true, - .has_dim_layer = true, - .has_idle_pc = true, -+ .has_3d_merge = true, - .max_linewidth = 2400, - .pixel_ram_size = DEFAULT_PIXEL_RAM_SIZE, - }; -@@ -25,6 +27,7 @@ static const struct dpu_mdp_cfg sc7280_mdp = { - [DPU_CLK_CTRL_DMA1] = { .reg_off = 0x2b4, .bit_off = 8 }, - [DPU_CLK_CTRL_DMA2] = { .reg_off = 0x2c4, .bit_off = 8 }, - [DPU_CLK_CTRL_WB2] = { .reg_off = 0x2bc, .bit_off = 16 }, -+ [DPU_CLK_CTRL_REG_DMA] = { .reg_off = 0x2bc, .bit_off = 20 }, - }, - }; - -@@ -128,32 +131,45 @@ static const struct dpu_pingpong_cfg sc7280_pp[] = { - .base = 0x69000, .len = 0, - .features = BIT(DPU_PINGPONG_DITHER), - .sblk = &sc7280_pp_sblk, -- .merge_3d = 0, -+ .merge_3d = MERGE_3D_0, - .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), - }, { - .name = "pingpong_1", .id = PINGPONG_1, - .base = 0x6a000, .len = 0, - .features = BIT(DPU_PINGPONG_DITHER), - .sblk = &sc7280_pp_sblk, -- .merge_3d = 0, -+ .merge_3d = MERGE_3D_0, - .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), - }, { - .name = "pingpong_2", .id = PINGPONG_2, - .base = 0x6b000, .len = 0, - .features = BIT(DPU_PINGPONG_DITHER), - .sblk = &sc7280_pp_sblk, -- .merge_3d = 0, -+ .merge_3d = MERGE_3D_1, - .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), - }, { - .name = "pingpong_3", .id = PINGPONG_3, - .base = 0x6c000, .len = 0, - .features = BIT(DPU_PINGPONG_DITHER), - .sblk = &sc7280_pp_sblk, -- .merge_3d = 0, -+ .merge_3d = MERGE_3D_1, - .intr_done = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), - }, - }; - -+static const struct dpu_merge_3d_cfg sc7280_merge_3d[] = { -+ { -+ .name = "merge_3d_0", .id = MERGE_3D_0, -+ .base = 0x4e000, .len = 0x8, -+ }, { -+ .name = "merge_3d_1", .id = MERGE_3D_1, -+ .base = 0x4f000, .len = 0x8, -+ }, { -+ .name = "merge_3d_2", .id = MERGE_3D_2, -+ .base = 0x50000, .len = 0x8, -+ }, -+}; -+ - /* NOTE: sc7280 only has one DSC hard slice encoder */ - static const struct dpu_dsc_cfg sc7280_dsc[] = { - { -@@ -261,6 +277,8 @@ const struct dpu_mdss_cfg dpu_sc7280_cfg = { - .pingpong = sc7280_pp, - .dsc_count = ARRAY_SIZE(sc7280_dsc), - .dsc = sc7280_dsc, -+ .merge_3d_count = ARRAY_SIZE(sc7280_merge_3d), -+ .merge_3d = sc7280_merge_3d, - .wb_count = ARRAY_SIZE(sc7280_wb), - .wb = sc7280_wb, - .intf_count = ARRAY_SIZE(sc7280_intf), --- -2.50.1 - diff --git a/debian/patches/linux/0024-remoteproc-core-Allow-auto-retry-of-rproc_start.patch b/debian/patches/linux/0024-remoteproc-core-Allow-auto-retry-of-rproc_start.patch deleted file mode 100644 index 5b0bd43..0000000 --- a/debian/patches/linux/0024-remoteproc-core-Allow-auto-retry-of-rproc_start.patch +++ /dev/null @@ -1,34 +0,0 @@ -From 9a6862b0c89d5a05fe440992fbf7ecb3627c0b1b Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Tue, 10 Jun 2025 12:44:00 +0800 -Subject: [PATCH 24/49] remoteproc: core: Allow auto retry of rproc_start() - -Sometimes the remoteproc just does not want to start for the first time. ---- - drivers/remoteproc/remoteproc_core.c | 10 +++++++--- - 1 file changed, 7 insertions(+), 3 deletions(-) - -diff --git a/src/drivers/remoteproc/remoteproc_core.c b/src/drivers/remoteproc/remoteproc_core.c -index 81b2ccf988e8..96450589144b 100644 ---- a/src/drivers/remoteproc/remoteproc_core.c -+++ b/src/drivers/remoteproc/remoteproc_core.c -@@ -1432,9 +1432,13 @@ static int rproc_fw_boot(struct rproc *rproc, const struct firmware *fw) - } - - ret = rproc_start(rproc, fw); -- if (ret) -- goto clean_up_resources; -- -+ if (ret) { -+ // HACK: try again -+ ret = rproc_start(rproc, fw); -+ if (ret) { -+ goto clean_up_resources; -+ } -+ } - return 0; - - clean_up_resources: --- -2.50.1 - diff --git a/debian/patches/linux/0025-scripts-Add-PKGBUILD-for-testing-on-Arch-Linux-ARM.patch b/debian/patches/linux/0025-scripts-Add-PKGBUILD-for-testing-on-Arch-Linux-ARM.patch deleted file mode 100644 index 4eab88b..0000000 --- a/debian/patches/linux/0025-scripts-Add-PKGBUILD-for-testing-on-Arch-Linux-ARM.patch +++ /dev/null @@ -1,170 +0,0 @@ -From 5a860dce21e397664864d87d672672a5eae89f39 Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Wed, 18 Jun 2025 18:27:27 +0800 -Subject: [PATCH 25/49] scripts: Add PKGBUILD for testing on Arch Linux ARM - ---- - scripts/Makefile.package | 13 ++++ - scripts/package/PKGBUILD-radxa | 119 +++++++++++++++++++++++++++++++++ - 2 files changed, 132 insertions(+) - create mode 100644 scripts/package/PKGBUILD-radxa - -diff --git a/src/scripts/Makefile.package b/src/scripts/Makefile.package -index 74bcb9e7f7a4..bc3d3b9342d6 100644 ---- a/src/scripts/Makefile.package -+++ b/src/scripts/Makefile.package -@@ -158,6 +158,18 @@ pacman-pkg: - KBUILD_REVISION="$(shell $(srctree)/scripts/build-version)" \ - makepkg $(MAKEPKGOPTS) - -+# pacman-radxa-pkg -+# --------------------------------------------------------------------------- -+ -+PHONY += pacman-radxa-pkg -+pacman-radxa-pkg: -+ @ln -srf $(srctree)/scripts/package/PKGBUILD-radxa $(objtree)/PKGBUILD -+ +BUILDDIR="$(realpath $(objtree))/pacman" \ -+ CARCH="$(UTS_MACHINE)" \ -+ KBUILD_MAKEFLAGS="$(MAKEFLAGS)" \ -+ KBUILD_REVISION="$(shell $(srctree)/scripts/build-version)" \ -+ makepkg $(MAKEPKGOPTS) -+ - # dir-pkg tar*-pkg - tarball targets - # --------------------------------------------------------------------------- - -@@ -239,6 +251,7 @@ help: - @echo ' snap-pkg - Build only the binary kernel snap package' - @echo ' (will connect to external hosts)' - @echo ' pacman-pkg - Build only the binary kernel pacman package' -+ @echo ' pacman-radxa-pkg - Build only the binary kernel pacman package for stable testing' - @echo ' dir-pkg - Build the kernel as a plain directory structure' - @echo ' tar-pkg - Build the kernel as an uncompressed tarball' - @echo ' targz-pkg - Build the kernel as a gzip compressed tarball' -diff --git a/src/scripts/package/PKGBUILD-radxa b/src/scripts/package/PKGBUILD-radxa -new file mode 100644 -index 000000000000..1588f1cb5940 ---- /dev/null -+++ b/src/scripts/package/PKGBUILD-radxa -@@ -0,0 +1,119 @@ -+# SPDX-License-Identifier: GPL-2.0-only -+# Maintainer: Thomas Weißschuh -+# Contributor: Jan Alexander Steffens (heftig) -+ -+pkgbase=${PACMAN_PKGBASE:-linux-radxa-qcom} -+pkgname=("${pkgbase}") -+ -+_extrapackages=${PACMAN_EXTRAPACKAGES-headers api-headers} -+for pkg in $_extrapackages; do -+ pkgname+=("${pkgbase}-${pkg}") -+done -+ -+pkgver="${KERNELRELEASE//-/_}" -+# The PKGBUILD is evaluated multiple times. -+# Running scripts/build-version from here would introduce inconsistencies. -+pkgrel="${KBUILD_REVISION}" -+pkgdesc='Upstream Linux Stable on Radxa Qualcomm platforms' -+url='https://www.kernel.org/' -+# Enable flexible cross-compilation -+arch=(${CARCH}) -+license=(GPL-2.0-only) -+makedepends=( -+ bc -+ bison -+ flex -+ gettext -+ kmod -+ libelf -+ openssl -+ pahole -+ perl -+ python -+ rsync -+ tar -+) -+options=(!debug !strip !buildflags !makeflags) -+ -+_prologue() { -+ # MAKEFLAGS from makepkg.conf override the ones inherited from kbuild. -+ # Bypass this override with a custom variable. -+ export MAKEFLAGS="${KBUILD_MAKEFLAGS}" -+ -+ # Kbuild works in the output directory, where this PKGBUILD is located. -+ cd "$(dirname "${BASH_SOURCE[0]}")" -+} -+ -+build() { -+ _prologue -+ -+ ${MAKE} KERNELRELEASE="${KERNELRELEASE}" KBUILD_BUILD_VERSION="${pkgrel}" -+} -+ -+_package() { -+ pkgdesc="The ${pkgdesc} kernel and modules" -+ -+ local modulesdir="${pkgdir}/usr/lib/modules/${KERNELRELEASE}" -+ -+ _prologue -+ -+ echo "Installing boot image..." -+ # systemd expects to find the kernel here to allow hibernation -+ # https://github.com/systemd/systemd/commit/edda44605f06a41fb86b7ab8128dcf99161d2344 -+ install -Dm644 "$(${MAKE} -s image_name)" "${modulesdir}/vmlinuz" -+ -+ # Used by mkinitcpio to name the kernel -+ echo "${pkgbase}" > "${modulesdir}/pkgbase" -+ -+ echo "Installing modules..." -+ ${MAKE} INSTALL_MOD_PATH="${pkgdir}/usr" INSTALL_MOD_STRIP=1 \ -+ DEPMOD=true modules_install -+ -+ if [ -d "${srctree}/arch/${SRCARCH}/boot/dts" ]; then -+ echo "Installing dtbs..." -+ ${MAKE} INSTALL_DTBS_PATH="${modulesdir}/dtb" dtbs_install -+ ${MAKE} INSTALL_DTBS_PATH="${pkgdir}/boot/dtb" dtbs_install -+ fi -+ -+ # remove build link, will be part of -headers package -+ rm -f "${modulesdir}/build" -+} -+ -+_package-headers() { -+ pkgdesc="Headers and scripts for building modules for the ${pkgdesc} kernel" -+ -+ local builddir="${pkgdir}/usr/lib/modules/${KERNELRELEASE}/build" -+ -+ _prologue -+ -+ if grep -q CONFIG_MODULES=y include/config/auto.conf; then -+ echo "Installing build files..." -+ "${srctree}/scripts/package/install-extmod-build" "${builddir}" -+ fi -+ -+ echo "Installing System.map and config..." -+ mkdir -p "${builddir}" -+ cp System.map "${builddir}/System.map" -+ cp .config "${builddir}/.config" -+ -+ echo "Adding symlink..." -+ mkdir -p "${pkgdir}/usr/src" -+ ln -sr "${builddir}" "${pkgdir}/usr/src/${pkgbase}" -+} -+ -+_package-api-headers() { -+ pkgdesc="Kernel headers sanitized for use in userspace" -+ provides=(linux-api-headers="${pkgver}") -+ conflicts=(linux-api-headers) -+ -+ _prologue -+ -+ ${MAKE} headers_install INSTALL_HDR_PATH="${pkgdir}/usr" -+} -+ -+for _p in "${pkgname[@]}"; do -+ eval "package_$_p() { -+ $(declare -f "_package${_p#$pkgbase}") -+ _package${_p#$pkgbase} -+ }" -+done --- -2.50.1 - diff --git a/debian/patches/linux/0026-soc-qcom-qcom_stats-Add-support-to-read-DDR-statisti.patch b/debian/patches/linux/0026-soc-qcom-qcom_stats-Add-support-to-read-DDR-statisti.patch deleted file mode 100644 index ed9cb8b..0000000 --- a/debian/patches/linux/0026-soc-qcom-qcom_stats-Add-support-to-read-DDR-statisti.patch +++ /dev/null @@ -1,174 +0,0 @@ -From c2183416d02a95b5e4e846dc8b70009dc1d481d4 Mon Sep 17 00:00:00 2001 -From: Maulik Shah -Date: Wed, 11 Jun 2025 11:33:45 +0530 -Subject: [PATCH 26/49] soc: qcom: qcom_stats: Add support to read DDR - statistic - -DDR statistic provide different DDR LPM and DDR frequency statistic. -Add support to read from MSGRAM and display via debugfs. - -Reviewed-by: Konrad Dybcio -Reviewed-by: Dmitry Baryshkov -Signed-off-by: Maulik Shah ---- - drivers/soc/qcom/qcom_stats.c | 99 +++++++++++++++++++++++++++++++++++ - 1 file changed, 99 insertions(+) - -diff --git a/src/drivers/soc/qcom/qcom_stats.c b/src/drivers/soc/qcom/qcom_stats.c -index 5de99cf59b9f..33fd2a157446 100644 ---- a/src/drivers/soc/qcom/qcom_stats.c -+++ b/src/drivers/soc/qcom/qcom_stats.c -@@ -1,8 +1,10 @@ - // SPDX-License-Identifier: GPL-2.0-only - /* - * Copyright (c) 2011-2021, The Linux Foundation. All rights reserved. -+ * Copyright (c) 2022-2025, Qualcomm Innovation Center, Inc. All rights reserved. - */ - -+#include - #include - #include - #include -@@ -24,6 +26,17 @@ - #define ACCUMULATED_OFFSET 0x18 - #define CLIENT_VOTES_OFFSET 0x20 - -+#define DDR_STATS_MAGIC_KEY 0xA1157A75 -+#define DDR_STATS_MAX_NUM_MODES 20 -+#define DDR_STATS_MAGIC_KEY_ADDR 0x0 -+#define DDR_STATS_NUM_MODES_ADDR 0x4 -+#define DDR_STATS_ENTRY_START_ADDR 0x8 -+ -+#define DDR_STATS_CP_IDX(data) FIELD_GET(GENMASK(4, 0), data) -+#define DDR_STATS_LPM_NAME(data) FIELD_GET(GENMASK(7, 0), data) -+#define DDR_STATS_TYPE(data) FIELD_GET(GENMASK(15, 8), data) -+#define DDR_STATS_FREQ(data) FIELD_GET(GENMASK(31, 16), data) -+ - struct subsystem_data { - const char *name; - u32 smem_item; -@@ -48,12 +61,19 @@ static const struct subsystem_data subsystems[] = { - - struct stats_config { - size_t stats_offset; -+ size_t ddr_stats_offset; - size_t num_records; - bool appended_stats_avail; - bool dynamic_offset; - bool subsystem_stats_in_smem; - }; - -+struct ddr_stats_entry { -+ u32 name; -+ u32 count; -+ u64 duration; -+}; -+ - struct stats_data { - bool appended_stats_avail; - void __iomem *base; -@@ -122,8 +142,85 @@ static int qcom_soc_sleep_stats_show(struct seq_file *s, void *unused) - return 0; - } - -+static void qcom_ddr_stats_print(struct seq_file *s, struct ddr_stats_entry *data) -+{ -+ u32 cp_idx; -+ -+ /* -+ * DDR statistic have two different types of details encoded. -+ * (1) DDR LPM Stats -+ * (2) DDR Frequency Stats -+ * -+ * The name field have details like which type of DDR stat (bits 8:15) -+ * along with other details as explained below -+ * -+ * In case of DDR LPM stat, name field will be encoded as, -+ * Bits - Meaning -+ * 0:7 - DDR LPM name, can be of 0xd4, 0xd3, 0x11 and 0xd0. -+ * 8:15 - 0x0 (indicates its a LPM stat) -+ * 16:31 - Unused -+ * -+ * In case of DDR FREQ stats, name field will be encoded as, -+ * Bits - Meaning -+ * 0:4 - DDR Clock plan index (CP IDX) -+ * 5:7 - Unused -+ * 8:15 - 0x1 (indicates its Freq stat) -+ * 16:31 - Frequency value in Mhz -+ */ -+ switch (DDR_STATS_TYPE(data->name)) { -+ case 0: -+ seq_printf(s, "DDR LPM Stat Name:0x%lx\tcount:%u\tDuration (ticks):%llu\n", -+ DDR_STATS_LPM_NAME(data->name), data->count, data->duration); -+ break; -+ case 1: -+ if (!data->count || !DDR_STATS_FREQ(data->name)) -+ return; -+ -+ cp_idx = DDR_STATS_CP_IDX(data->name); -+ seq_printf(s, "DDR Freq %luMhz:\tCP IDX:%u\tcount:%u\tDuration (ticks):%llu\n", -+ DDR_STATS_FREQ(data->name), cp_idx, data->count, data->duration); -+ break; -+ } -+} -+ -+static int qcom_ddr_stats_show(struct seq_file *s, void *d) -+{ -+ struct ddr_stats_entry data[DDR_STATS_MAX_NUM_MODES]; -+ void __iomem *reg = (void __iomem *)s->private; -+ u32 entry_count; -+ int i; -+ -+ entry_count = readl_relaxed(reg + DDR_STATS_NUM_MODES_ADDR); -+ if (entry_count > DDR_STATS_MAX_NUM_MODES) -+ return -EINVAL; -+ -+ reg += DDR_STATS_ENTRY_START_ADDR; -+ memcpy_fromio(data, reg, sizeof(struct ddr_stats_entry) * entry_count); -+ -+ for (i = 0; i < entry_count; i++) -+ qcom_ddr_stats_print(s, &data[i]); -+ -+ return 0; -+} -+ - DEFINE_SHOW_ATTRIBUTE(qcom_soc_sleep_stats); - DEFINE_SHOW_ATTRIBUTE(qcom_subsystem_sleep_stats); -+DEFINE_SHOW_ATTRIBUTE(qcom_ddr_stats); -+ -+static void qcom_create_ddr_stat_files(struct dentry *root, void __iomem *reg, -+ const struct stats_config *config) -+{ -+ u32 key; -+ -+ if (!config->ddr_stats_offset) -+ return; -+ -+ key = readl_relaxed(reg + config->ddr_stats_offset + DDR_STATS_MAGIC_KEY_ADDR); -+ if (key == DDR_STATS_MAGIC_KEY) -+ debugfs_create_file("ddr_stats", 0400, root, -+ (__force void *)reg + config->ddr_stats_offset, -+ &qcom_ddr_stats_fops); -+} - - static void qcom_create_soc_sleep_stat_files(struct dentry *root, void __iomem *reg, - struct stats_data *d, -@@ -212,6 +309,7 @@ static int qcom_stats_probe(struct platform_device *pdev) - - qcom_create_subsystem_stat_files(root, config); - qcom_create_soc_sleep_stat_files(root, reg, d, config); -+ qcom_create_ddr_stat_files(root, reg, config); - - platform_set_drvdata(pdev, root); - -@@ -254,6 +352,7 @@ static const struct stats_config rpmh_data_sdm845 = { - - static const struct stats_config rpmh_data = { - .stats_offset = 0x48, -+ .ddr_stats_offset = 0xb8, - .num_records = 3, - .appended_stats_avail = false, - .dynamic_offset = false, --- -2.50.1 - diff --git a/debian/patches/linux/0027-soc-qcom-qcom_stats-Add-QMP-support-for-syncing-ddr-.patch b/debian/patches/linux/0027-soc-qcom-qcom_stats-Add-QMP-support-for-syncing-ddr-.patch deleted file mode 100644 index bd410c5..0000000 --- a/debian/patches/linux/0027-soc-qcom-qcom_stats-Add-QMP-support-for-syncing-ddr-.patch +++ /dev/null @@ -1,94 +0,0 @@ -From fc7a62c3e002fe50c05a73fd9db0def9041fe8cf Mon Sep 17 00:00:00 2001 -From: Maulik Shah -Date: Wed, 11 Jun 2025 11:33:46 +0530 -Subject: [PATCH 27/49] soc: qcom: qcom_stats: Add QMP support for syncing ddr - stats - -Recent SoCs (SM8450 onwards) require QMP command to be sent before reading -ddr stats. The duration field of ddr stats will get populated only if QMP -command is sent. - -Add support to send ddr stats freqsync QMP command. - -Signed-off-by: Maulik Shah -Reviewed-by: Dmitry Baryshkov ---- - drivers/soc/qcom/qcom_stats.c | 36 ++++++++++++++++++++++++++++++++++- - 1 file changed, 35 insertions(+), 1 deletion(-) - -diff --git a/src/drivers/soc/qcom/qcom_stats.c b/src/drivers/soc/qcom/qcom_stats.c -index 33fd2a157446..2e380faf9080 100644 ---- a/src/drivers/soc/qcom/qcom_stats.c -+++ b/src/drivers/soc/qcom/qcom_stats.c -@@ -13,6 +13,7 @@ - #include - #include - -+#include - #include - #include - -@@ -37,6 +38,8 @@ - #define DDR_STATS_TYPE(data) FIELD_GET(GENMASK(15, 8), data) - #define DDR_STATS_FREQ(data) FIELD_GET(GENMASK(31, 16), data) - -+static struct qmp *qcom_stats_qmp; -+ - struct subsystem_data { - const char *name; - u32 smem_item; -@@ -188,12 +191,28 @@ static int qcom_ddr_stats_show(struct seq_file *s, void *d) - struct ddr_stats_entry data[DDR_STATS_MAX_NUM_MODES]; - void __iomem *reg = (void __iomem *)s->private; - u32 entry_count; -- int i; -+ int i, ret; - - entry_count = readl_relaxed(reg + DDR_STATS_NUM_MODES_ADDR); - if (entry_count > DDR_STATS_MAX_NUM_MODES) - return -EINVAL; - -+ if (qcom_stats_qmp) { -+ /* -+ * Recent SoCs (SM8450 onwards) do not have duration field -+ * populated from boot up onwards for both DDR LPM Stats -+ * and DDR Frequency Stats. -+ * -+ * Send QMP message to Always on processor which will -+ * populate duration field into MSG RAM area. -+ * -+ * Sent every time to read latest data. -+ */ -+ ret = qmp_send(qcom_stats_qmp, "{class: ddr, action: freqsync}"); -+ if (ret) -+ return ret; -+ } -+ - reg += DDR_STATS_ENTRY_START_ADDR; - memcpy_fromio(data, reg, sizeof(struct ddr_stats_entry) * entry_count); - -@@ -304,6 +323,21 @@ static int qcom_stats_probe(struct platform_device *pdev) - - for (i = 0; i < config->num_records; i++) - d[i].appended_stats_avail = config->appended_stats_avail; -+ /* -+ * QMP is used for DDR stats syncing to MSG RAM for recent SoCs (SM8450 onwards). -+ * The prior SoCs do not need QMP handle as the required stats are already present -+ * in MSG RAM, provided the DDR_STATS_MAGIC_KEY matches. -+ */ -+ qcom_stats_qmp = qmp_get(&pdev->dev); -+ if (IS_ERR(qcom_stats_qmp)) { -+ /* We ignore error if QMP is not defined/needed */ -+ if (!of_property_present(pdev->dev.of_node, "qcom,qmp")) -+ qcom_stats_qmp = NULL; -+ else if (PTR_ERR(qcom_stats_qmp) == -EPROBE_DEFER) -+ return -EPROBE_DEFER; -+ else -+ return PTR_ERR(qcom_stats_qmp); -+ } - - root = debugfs_create_dir("qcom_stats", NULL); - --- -2.50.1 - diff --git a/debian/patches/linux/0028-arm64-dts-qcom-sc7280-Add-support-for-two-additional.patch b/debian/patches/linux/0028-arm64-dts-qcom-sc7280-Add-support-for-two-additional.patch deleted file mode 100644 index 14d98c3..0000000 --- a/debian/patches/linux/0028-arm64-dts-qcom-sc7280-Add-support-for-two-additional.patch +++ /dev/null @@ -1,82 +0,0 @@ -From 9ead8abcbcc787a15e0f78d7cdbfc305dfa2b778 Mon Sep 17 00:00:00 2001 -From: Pushpendra Singh -Date: Wed, 2 Jul 2025 05:31:20 +0530 -Subject: [PATCH 28/49] arm64: dts: qcom: sc7280: Add support for two - additional DDR frequencies - -The SC7280 SoC now supports two additional frequencies. This patch -add those frequencies to the BWMON OPP table and updates the frequency -mapping table accordingly. - -These changes do not impact existing platforms, as the updated mapping -only affects the highest OPP. On any given platform, this will continue -to vote for the maximum available OPP. - -Signed-off-by: Pushpendra Singh -Reviewed-by: Dmitry Baryshkov ---- - arch/arm64/boot/dts/qcom/sc7280.dtsi | 18 ++++++++++++------ - 1 file changed, 12 insertions(+), 6 deletions(-) - -diff --git a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -index 5e2cb173cd37..4cd3f23bbbd1 100644 ---- a/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -+++ b/src/arch/arm64/boot/dts/qcom/sc7280.dtsi -@@ -621,12 +621,12 @@ cpu4_opp_2208mhz: opp-2208000000 { - - cpu4_opp_2400mhz: opp-2400000000 { - opp-hz = /bits/ 64 <2400000000>; -- opp-peak-kBps = <8532000 48537600>; -+ opp-peak-kBps = <12787200 48537600>; - }; - - cpu4_opp_2611mhz: opp-2611200000 { - opp-hz = /bits/ 64 <2611200000>; -- opp-peak-kBps = <8532000 48537600>; -+ opp-peak-kBps = <12787200 48537600>; - }; - }; - -@@ -686,22 +686,22 @@ cpu7_opp_2381mhz: opp-2380800000 { - - cpu7_opp_2400mhz: opp-2400000000 { - opp-hz = /bits/ 64 <2400000000>; -- opp-peak-kBps = <8532000 48537600>; -+ opp-peak-kBps = <12787200 48537600>; - }; - - cpu7_opp_2515mhz: opp-2515200000 { - opp-hz = /bits/ 64 <2515200000>; -- opp-peak-kBps = <8532000 48537600>; -+ opp-peak-kBps = <12787200 48537600>; - }; - - cpu7_opp_2707mhz: opp-2707200000 { - opp-hz = /bits/ 64 <2707200000>; -- opp-peak-kBps = <8532000 48537600>; -+ opp-peak-kBps = <12787200 48537600>; - }; - - cpu7_opp_3014mhz: opp-3014400000 { - opp-hz = /bits/ 64 <3014400000>; -- opp-peak-kBps = <8532000 48537600>; -+ opp-peak-kBps = <12787200 48537600>; - }; - }; - -@@ -4268,6 +4268,12 @@ opp-6 { - opp-7 { - opp-peak-kBps = <8532000>; - }; -+ opp-8 { -+ opp-peak-kBps = <10944000>; -+ }; -+ opp-9 { -+ opp-peak-kBps = <12787200>; -+ }; - }; - }; - --- -2.50.1 - diff --git a/debian/patches/linux/0029-configs-Add-qcom_module_defconfig.patch b/debian/patches/linux/0029-configs-Add-qcom_module_defconfig.patch deleted file mode 100644 index a461f0a..0000000 --- a/debian/patches/linux/0029-configs-Add-qcom_module_defconfig.patch +++ /dev/null @@ -1,2209 +0,0 @@ -From 1e32cc30fa785be7374f9705e45ebb2ca45cda16 Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Wed, 18 Jun 2025 18:29:38 +0800 -Subject: [PATCH 29/49] configs: Add qcom_module_defconfig - -Signed-off-by: Xilin Wu ---- - arch/arm64/configs/qcom_module_defconfig | 2189 ++++++++++++++++++++++ - 1 file changed, 2189 insertions(+) - create mode 100644 arch/arm64/configs/qcom_module_defconfig - -diff --git a/src/arch/arm64/configs/qcom_module_defconfig b/src/arch/arm64/configs/qcom_module_defconfig -new file mode 100644 -index 000000000000..22f17f1ab5b5 ---- /dev/null -+++ b/src/arch/arm64/configs/qcom_module_defconfig -@@ -0,0 +1,2189 @@ -+# CONFIG_LOCALVERSION_AUTO is not set -+CONFIG_DEFAULT_HOSTNAME="radxa-qcom" -+CONFIG_SYSVIPC=y -+CONFIG_POSIX_MQUEUE=y -+CONFIG_WATCH_QUEUE=y -+CONFIG_NO_HZ_FULL=y -+CONFIG_NO_HZ=y -+CONFIG_HIGH_RES_TIMERS=y -+CONFIG_BPF_JIT=y -+CONFIG_BPF_JIT_ALWAYS_ON=y -+CONFIG_PREEMPT=y -+CONFIG_PREEMPT_DYNAMIC=y -+CONFIG_SCHED_CORE=y -+CONFIG_IRQ_TIME_ACCOUNTING=y -+CONFIG_BSD_PROCESS_ACCT=y -+CONFIG_BSD_PROCESS_ACCT_V3=y -+CONFIG_TASKSTATS=y -+CONFIG_TASK_DELAY_ACCT=y -+CONFIG_TASK_XACCT=y -+CONFIG_TASK_IO_ACCOUNTING=y -+CONFIG_PSI=y -+CONFIG_RCU_EXPERT=y -+CONFIG_RCU_BOOST=y -+CONFIG_RCU_LAZY=y -+CONFIG_RCU_DOUBLE_CHECK_CB_TIME=y -+CONFIG_IKCONFIG=y -+CONFIG_IKCONFIG_PROC=y -+CONFIG_IKHEADERS=m -+CONFIG_PRINTK_INDEX=y -+CONFIG_UCLAMP_TASK=y -+CONFIG_NUMA_BALANCING=y -+CONFIG_MEMCG=y -+CONFIG_BLK_CGROUP=y -+CONFIG_CFS_BANDWIDTH=y -+CONFIG_UCLAMP_TASK_GROUP=y -+CONFIG_CGROUP_PIDS=y -+CONFIG_CGROUP_RDMA=y -+CONFIG_CGROUP_DMEM=y -+CONFIG_CGROUP_FREEZER=y -+CONFIG_CGROUP_HUGETLB=y -+CONFIG_CPUSETS=y -+CONFIG_CGROUP_DEVICE=y -+CONFIG_CGROUP_CPUACCT=y -+CONFIG_CGROUP_PERF=y -+CONFIG_CGROUP_BPF=y -+CONFIG_CGROUP_MISC=y -+CONFIG_USER_NS=y -+CONFIG_CHECKPOINT_RESTORE=y -+CONFIG_SCHED_AUTOGROUP=y -+CONFIG_KALLSYMS_ALL=y -+CONFIG_PROFILING=y -+CONFIG_RUST=y -+CONFIG_KEXEC=y -+CONFIG_KEXEC_FILE=y -+CONFIG_ARCH_QCOM=y -+CONFIG_ARM64_ERRATUM_2441007=y -+CONFIG_SCHED_MC=y -+CONFIG_SCHED_CLUSTER=y -+CONFIG_SCHED_SMT=y -+CONFIG_NUMA=y -+CONFIG_HZ_1000=y -+CONFIG_PARAVIRT_TIME_ACCOUNTING=y -+CONFIG_ARM64_SW_TTBR0_PAN=y -+CONFIG_COMPAT=y -+CONFIG_COMPAT_ALIGNMENT_FIXUPS=y -+CONFIG_ARMV8_DEPRECATED=y -+CONFIG_SWP_EMULATION=y -+CONFIG_CP15_BARRIER_EMULATION=y -+CONFIG_SETEND_EMULATION=y -+CONFIG_ARM64_PMEM=y -+CONFIG_ARM64_PSEUDO_NMI=y -+CONFIG_RANDOMIZE_BASE=y -+CONFIG_COMPRESSED_INSTALL=y -+CONFIG_HIBERNATION=y -+CONFIG_WQ_POWER_EFFICIENT_DEFAULT=y -+CONFIG_ENERGY_MODEL=y -+CONFIG_CPU_IDLE_GOV_LADDER=y -+CONFIG_CPU_IDLE_GOV_MENU=y -+CONFIG_CPU_IDLE_GOV_TEO=y -+CONFIG_ARM_PSCI_CPUIDLE=y -+CONFIG_CPU_FREQ=y -+CONFIG_CPU_FREQ_STAT=y -+CONFIG_CPU_FREQ_GOV_POWERSAVE=m -+CONFIG_CPU_FREQ_GOV_USERSPACE=y -+CONFIG_CPU_FREQ_GOV_ONDEMAND=y -+CONFIG_CPU_FREQ_GOV_CONSERVATIVE=m -+CONFIG_CPUFREQ_DT=y -+CONFIG_ARM_SCPI_CPUFREQ=y -+CONFIG_ARM_QCOM_CPUFREQ_NVMEM=y -+CONFIG_ARM_QCOM_CPUFREQ_HW=y -+CONFIG_ARM_SCMI_CPUFREQ=y -+CONFIG_ACPI_CPPC_CPUFREQ=m -+CONFIG_ACPI=y -+CONFIG_ACPI_FPDT=y -+CONFIG_ACPI_EC=y -+CONFIG_ACPI_EC_DEBUGFS=m -+CONFIG_ACPI_VIDEO=m -+CONFIG_ACPI_TAD=m -+CONFIG_ACPI_DOCK=y -+CONFIG_ACPI_IPMI=m -+CONFIG_ACPI_DEBUG=y -+CONFIG_ACPI_PCI_SLOT=y -+CONFIG_ACPI_HOTPLUG_MEMORY=y -+CONFIG_ACPI_BGRT=y -+CONFIG_ACPI_NFIT=m -+CONFIG_ACPI_HMAT=y -+CONFIG_ACPI_APEI=y -+CONFIG_ACPI_APEI_GHES=y -+CONFIG_ACPI_APEI_PCIEAER=y -+CONFIG_ACPI_APEI_MEMORY_FAILURE=y -+CONFIG_ACPI_APEI_EINJ=y -+CONFIG_ACPI_APEI_ERST_DEBUG=m -+CONFIG_ACPI_CONFIGFS=m -+CONFIG_ACPI_PFRUT=m -+CONFIG_ACPI_FFH=y -+CONFIG_VIRTUALIZATION=y -+CONFIG_KVM=y -+CONFIG_KPROBES=y -+CONFIG_RANDOMIZE_KSTACK_OFFSET_DEFAULT=y -+CONFIG_LOCK_EVENT_COUNTS=y -+# CONFIG_GCC_PLUGINS is not set -+CONFIG_MODULES=y -+CONFIG_MODULE_FORCE_LOAD=y -+CONFIG_MODULE_UNLOAD=y -+CONFIG_MODULE_FORCE_UNLOAD=y -+CONFIG_MODULE_UNLOAD_TAINT_TRACKING=y -+CONFIG_MODULE_COMPRESS=y -+CONFIG_MODULE_COMPRESS_ZSTD=y -+CONFIG_MODULE_DECOMPRESS=y -+CONFIG_MODULE_ALLOW_MISSING_NAMESPACE_IMPORTS=y -+CONFIG_BLK_DEV_ZONED=y -+CONFIG_BLK_DEV_THROTTLING=y -+CONFIG_BLK_WBT=y -+CONFIG_BLK_CGROUP_IOLATENCY=y -+CONFIG_BLK_CGROUP_FC_APPID=y -+CONFIG_BLK_CGROUP_IOCOST=y -+CONFIG_BLK_CGROUP_IOPRIO=y -+CONFIG_BLK_SED_OPAL=y -+CONFIG_BLK_INLINE_ENCRYPTION=y -+CONFIG_BLK_INLINE_ENCRYPTION_FALLBACK=y -+CONFIG_PARTITION_ADVANCED=y -+CONFIG_LDM_PARTITION=y -+CONFIG_OF_PARTITION=y -+CONFIG_BINFMT_MISC=y -+CONFIG_ZSWAP=y -+CONFIG_ZSWAP_DEFAULT_ON=y -+CONFIG_ZSWAP_SHRINKER_DEFAULT_ON=y -+CONFIG_ZSWAP_COMPRESSOR_DEFAULT_ZSTD=y -+CONFIG_ZSMALLOC_STAT=y -+CONFIG_SLAB_FREELIST_RANDOM=y -+CONFIG_SLAB_FREELIST_HARDENED=y -+# CONFIG_COMPAT_BRK is not set -+CONFIG_MEMORY_HOTPLUG=y -+CONFIG_MHP_DEFAULT_ONLINE_TYPE_ONLINE_AUTO=y -+CONFIG_MEMORY_HOTREMOVE=y -+CONFIG_KSM=y -+CONFIG_DEFAULT_MMAP_MIN_ADDR=65536 -+CONFIG_MEMORY_FAILURE=y -+CONFIG_HWPOISON_INJECT=m -+CONFIG_TRANSPARENT_HUGEPAGE=y -+CONFIG_READ_ONLY_THP_FOR_FS=y -+CONFIG_CMA=y -+CONFIG_CMA_DEBUGFS=y -+CONFIG_CMA_SYSFS=y -+CONFIG_IDLE_PAGE_TRACKING=y -+CONFIG_ZONE_DEVICE=y -+CONFIG_DEVICE_PRIVATE=y -+CONFIG_ANON_VMA_NAME=y -+CONFIG_USERFAULTFD=y -+CONFIG_LRU_GEN=y -+CONFIG_LRU_GEN_ENABLED=y -+CONFIG_DAMON=y -+CONFIG_DAMON_VADDR=y -+CONFIG_DAMON_PADDR=y -+CONFIG_DAMON_SYSFS=y -+CONFIG_DAMON_RECLAIM=y -+CONFIG_DAMON_LRU_SORT=y -+CONFIG_NET=y -+CONFIG_PACKET=y -+CONFIG_PACKET_DIAG=m -+CONFIG_UNIX_DIAG=m -+CONFIG_TLS_DEVICE=y -+CONFIG_XFRM_USER=m -+CONFIG_XFRM_INTERFACE=m -+CONFIG_XFRM_SUB_POLICY=y -+CONFIG_XFRM_STATISTICS=y -+CONFIG_NET_KEY=m -+CONFIG_NET_KEY_MIGRATE=y -+CONFIG_XFRM_IPTFS=m -+CONFIG_SMC=m -+CONFIG_SMC_DIAG=m -+CONFIG_SMC_LO=y -+CONFIG_XDP_SOCKETS=y -+CONFIG_XDP_SOCKETS_DIAG=m -+CONFIG_IP_MULTICAST=y -+CONFIG_IP_ADVANCED_ROUTER=y -+CONFIG_IP_FIB_TRIE_STATS=y -+CONFIG_IP_MULTIPLE_TABLES=y -+CONFIG_IP_ROUTE_MULTIPATH=y -+CONFIG_IP_ROUTE_VERBOSE=y -+CONFIG_NET_IPIP=m -+CONFIG_NET_IPGRE_DEMUX=m -+CONFIG_NET_IPGRE=m -+CONFIG_NET_IPGRE_BROADCAST=y -+CONFIG_IP_MROUTE=y -+CONFIG_IP_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IP_PIMSM_V1=y -+CONFIG_IP_PIMSM_V2=y -+CONFIG_NET_IPVTI=m -+CONFIG_NET_FOU_IP_TUNNELS=y -+CONFIG_INET_AH=m -+CONFIG_INET_ESP=m -+CONFIG_INET_ESP_OFFLOAD=m -+CONFIG_INET_ESPINTCP=y -+CONFIG_INET_IPCOMP=m -+CONFIG_INET_DIAG=m -+CONFIG_INET_UDP_DIAG=m -+CONFIG_INET_RAW_DIAG=m -+CONFIG_INET_DIAG_DESTROY=y -+CONFIG_TCP_CONG_ADVANCED=y -+CONFIG_TCP_CONG_HSTCP=m -+CONFIG_TCP_CONG_HYBLA=m -+CONFIG_TCP_CONG_NV=m -+CONFIG_TCP_CONG_SCALABLE=m -+CONFIG_TCP_CONG_LP=m -+CONFIG_TCP_CONG_VENO=m -+CONFIG_TCP_CONG_YEAH=m -+CONFIG_TCP_CONG_ILLINOIS=m -+CONFIG_TCP_CONG_DCTCP=m -+CONFIG_TCP_CONG_CDG=m -+CONFIG_TCP_CONG_BBR=m -+CONFIG_TCP_AO=y -+CONFIG_TCP_MD5SIG=y -+CONFIG_IPV6_ROUTER_PREF=y -+CONFIG_IPV6_ROUTE_INFO=y -+CONFIG_IPV6_OPTIMISTIC_DAD=y -+CONFIG_INET6_AH=m -+CONFIG_INET6_ESP=m -+CONFIG_INET6_ESP_OFFLOAD=m -+CONFIG_INET6_ESPINTCP=y -+CONFIG_INET6_IPCOMP=m -+CONFIG_IPV6_MIP6=m -+CONFIG_IPV6_ILA=m -+CONFIG_IPV6_VTI=m -+CONFIG_IPV6_SIT=m -+CONFIG_IPV6_SIT_6RD=y -+CONFIG_IPV6_GRE=m -+CONFIG_IPV6_SUBTREES=y -+CONFIG_IPV6_MROUTE=y -+CONFIG_IPV6_MROUTE_MULTIPLE_TABLES=y -+CONFIG_IPV6_PIMSM_V2=y -+CONFIG_IPV6_SEG6_LWTUNNEL=y -+CONFIG_IPV6_SEG6_HMAC=y -+CONFIG_IPV6_RPL_LWTUNNEL=y -+CONFIG_IPV6_IOAM6_LWTUNNEL=y -+CONFIG_MPTCP=y -+CONFIG_NETWORK_PHY_TIMESTAMPING=y -+CONFIG_NETFILTER=y -+CONFIG_BRIDGE_NETFILTER=m -+CONFIG_NETFILTER_NETLINK_HOOK=m -+CONFIG_NF_CONNTRACK=m -+CONFIG_NF_CONNTRACK_SECMARK=y -+CONFIG_NF_CONNTRACK_ZONES=y -+CONFIG_NF_CONNTRACK_PROCFS=y -+CONFIG_NF_CONNTRACK_EVENTS=y -+CONFIG_NF_CONNTRACK_TIMEOUT=y -+CONFIG_NF_CONNTRACK_TIMESTAMP=y -+CONFIG_NF_CONNTRACK_AMANDA=m -+CONFIG_NF_CONNTRACK_FTP=m -+CONFIG_NF_CONNTRACK_H323=m -+CONFIG_NF_CONNTRACK_IRC=m -+CONFIG_NF_CONNTRACK_NETBIOS_NS=m -+CONFIG_NF_CONNTRACK_SNMP=m -+CONFIG_NF_CONNTRACK_PPTP=m -+CONFIG_NF_CONNTRACK_SANE=m -+CONFIG_NF_CONNTRACK_SIP=m -+CONFIG_NF_CONNTRACK_TFTP=m -+CONFIG_NF_CT_NETLINK=m -+CONFIG_NF_CT_NETLINK_TIMEOUT=m -+CONFIG_NF_CT_NETLINK_HELPER=m -+CONFIG_NETFILTER_NETLINK_GLUE_CT=y -+CONFIG_NF_TABLES=m -+CONFIG_NF_TABLES_INET=y -+CONFIG_NF_TABLES_NETDEV=y -+CONFIG_NFT_NUMGEN=m -+CONFIG_NFT_CT=m -+CONFIG_NFT_FLOW_OFFLOAD=m -+CONFIG_NFT_CONNLIMIT=m -+CONFIG_NFT_LOG=m -+CONFIG_NFT_LIMIT=m -+CONFIG_NFT_MASQ=m -+CONFIG_NFT_REDIR=m -+CONFIG_NFT_NAT=m -+CONFIG_NFT_TUNNEL=m -+CONFIG_NFT_QUEUE=m -+CONFIG_NFT_QUOTA=m -+CONFIG_NFT_REJECT=m -+CONFIG_NFT_COMPAT=m -+CONFIG_NFT_HASH=m -+CONFIG_NFT_FIB_INET=m -+CONFIG_NFT_XFRM=m -+CONFIG_NFT_SOCKET=m -+CONFIG_NFT_OSF=m -+CONFIG_NFT_TPROXY=m -+CONFIG_NFT_SYNPROXY=m -+CONFIG_NFT_DUP_NETDEV=m -+CONFIG_NFT_FWD_NETDEV=m -+CONFIG_NFT_FIB_NETDEV=m -+CONFIG_NFT_REJECT_NETDEV=m -+CONFIG_NF_FLOW_TABLE_INET=m -+CONFIG_NF_FLOW_TABLE=m -+CONFIG_NF_FLOW_TABLE_PROCFS=y -+CONFIG_NETFILTER_XTABLES_COMPAT=y -+CONFIG_NETFILTER_XT_SET=m -+CONFIG_NETFILTER_XT_TARGET_AUDIT=m -+CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m -+CONFIG_NETFILTER_XT_TARGET_CLASSIFY=m -+CONFIG_NETFILTER_XT_TARGET_CONNMARK=m -+CONFIG_NETFILTER_XT_TARGET_CONNSECMARK=m -+CONFIG_NETFILTER_XT_TARGET_DSCP=m -+CONFIG_NETFILTER_XT_TARGET_HMARK=m -+CONFIG_NETFILTER_XT_TARGET_IDLETIMER=m -+CONFIG_NETFILTER_XT_TARGET_LED=m -+CONFIG_NETFILTER_XT_TARGET_LOG=m -+CONFIG_NETFILTER_XT_TARGET_MARK=m -+CONFIG_NETFILTER_XT_TARGET_NFLOG=m -+CONFIG_NETFILTER_XT_TARGET_NFQUEUE=m -+CONFIG_NETFILTER_XT_TARGET_NOTRACK=m -+CONFIG_NETFILTER_XT_TARGET_TEE=m -+CONFIG_NETFILTER_XT_TARGET_TPROXY=m -+CONFIG_NETFILTER_XT_TARGET_TRACE=m -+CONFIG_NETFILTER_XT_TARGET_SECMARK=m -+CONFIG_NETFILTER_XT_TARGET_TCPMSS=m -+CONFIG_NETFILTER_XT_TARGET_TCPOPTSTRIP=m -+CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m -+CONFIG_NETFILTER_XT_MATCH_BPF=m -+CONFIG_NETFILTER_XT_MATCH_CGROUP=m -+CONFIG_NETFILTER_XT_MATCH_CLUSTER=m -+CONFIG_NETFILTER_XT_MATCH_COMMENT=m -+CONFIG_NETFILTER_XT_MATCH_CONNBYTES=m -+CONFIG_NETFILTER_XT_MATCH_CONNLABEL=m -+CONFIG_NETFILTER_XT_MATCH_CONNLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_CONNMARK=m -+CONFIG_NETFILTER_XT_MATCH_CONNTRACK=m -+CONFIG_NETFILTER_XT_MATCH_CPU=m -+CONFIG_NETFILTER_XT_MATCH_DCCP=m -+CONFIG_NETFILTER_XT_MATCH_DEVGROUP=m -+CONFIG_NETFILTER_XT_MATCH_DSCP=m -+CONFIG_NETFILTER_XT_MATCH_ESP=m -+CONFIG_NETFILTER_XT_MATCH_HASHLIMIT=m -+CONFIG_NETFILTER_XT_MATCH_HELPER=m -+CONFIG_NETFILTER_XT_MATCH_IPCOMP=m -+CONFIG_NETFILTER_XT_MATCH_IPRANGE=m -+CONFIG_NETFILTER_XT_MATCH_IPVS=m -+CONFIG_NETFILTER_XT_MATCH_LENGTH=m -+CONFIG_NETFILTER_XT_MATCH_LIMIT=m -+CONFIG_NETFILTER_XT_MATCH_MAC=m -+CONFIG_NETFILTER_XT_MATCH_MARK=m -+CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m -+CONFIG_NETFILTER_XT_MATCH_NFACCT=m -+CONFIG_NETFILTER_XT_MATCH_OSF=m -+CONFIG_NETFILTER_XT_MATCH_OWNER=m -+CONFIG_NETFILTER_XT_MATCH_POLICY=m -+CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m -+CONFIG_NETFILTER_XT_MATCH_PKTTYPE=m -+CONFIG_NETFILTER_XT_MATCH_QUOTA=m -+CONFIG_NETFILTER_XT_MATCH_RATEEST=m -+CONFIG_NETFILTER_XT_MATCH_REALM=m -+CONFIG_NETFILTER_XT_MATCH_RECENT=m -+CONFIG_NETFILTER_XT_MATCH_SOCKET=m -+CONFIG_NETFILTER_XT_MATCH_STATE=m -+CONFIG_NETFILTER_XT_MATCH_STATISTIC=m -+CONFIG_NETFILTER_XT_MATCH_STRING=m -+CONFIG_NETFILTER_XT_MATCH_TCPMSS=m -+CONFIG_NETFILTER_XT_MATCH_TIME=m -+CONFIG_NETFILTER_XT_MATCH_U32=m -+CONFIG_IP_SET=m -+CONFIG_IP_SET_BITMAP_IP=m -+CONFIG_IP_SET_BITMAP_IPMAC=m -+CONFIG_IP_SET_BITMAP_PORT=m -+CONFIG_IP_SET_HASH_IP=m -+CONFIG_IP_SET_HASH_IPMARK=m -+CONFIG_IP_SET_HASH_IPPORT=m -+CONFIG_IP_SET_HASH_IPPORTIP=m -+CONFIG_IP_SET_HASH_IPPORTNET=m -+CONFIG_IP_SET_HASH_IPMAC=m -+CONFIG_IP_SET_HASH_MAC=m -+CONFIG_IP_SET_HASH_NETPORTNET=m -+CONFIG_IP_SET_HASH_NET=m -+CONFIG_IP_SET_HASH_NETNET=m -+CONFIG_IP_SET_HASH_NETPORT=m -+CONFIG_IP_SET_HASH_NETIFACE=m -+CONFIG_IP_SET_LIST_SET=m -+CONFIG_IP_VS=m -+CONFIG_IP_VS_IPV6=y -+CONFIG_IP_VS_TAB_BITS=15 -+CONFIG_IP_VS_PROTO_TCP=y -+CONFIG_IP_VS_PROTO_UDP=y -+CONFIG_IP_VS_PROTO_ESP=y -+CONFIG_IP_VS_PROTO_AH=y -+CONFIG_IP_VS_PROTO_SCTP=y -+CONFIG_IP_VS_RR=m -+CONFIG_IP_VS_WRR=m -+CONFIG_IP_VS_LC=m -+CONFIG_IP_VS_WLC=m -+CONFIG_IP_VS_FO=m -+CONFIG_IP_VS_OVF=m -+CONFIG_IP_VS_LBLC=m -+CONFIG_IP_VS_LBLCR=m -+CONFIG_IP_VS_DH=m -+CONFIG_IP_VS_SH=m -+CONFIG_IP_VS_MH=m -+CONFIG_IP_VS_SED=m -+CONFIG_IP_VS_NQ=m -+CONFIG_IP_VS_TWOS=m -+CONFIG_IP_VS_FTP=m -+CONFIG_IP_VS_PE_SIP=m -+CONFIG_NFT_DUP_IPV4=m -+CONFIG_NFT_FIB_IPV4=m -+CONFIG_NF_TABLES_ARP=y -+CONFIG_NF_LOG_ARP=m -+CONFIG_NF_LOG_IPV4=m -+CONFIG_IP_NF_IPTABLES=m -+CONFIG_IP_NF_MATCH_AH=m -+CONFIG_IP_NF_MATCH_ECN=m -+CONFIG_IP_NF_MATCH_RPFILTER=m -+CONFIG_IP_NF_MATCH_TTL=m -+CONFIG_IP_NF_FILTER=m -+CONFIG_IP_NF_TARGET_REJECT=m -+CONFIG_IP_NF_TARGET_SYNPROXY=m -+CONFIG_IP_NF_NAT=m -+CONFIG_IP_NF_TARGET_MASQUERADE=m -+CONFIG_IP_NF_TARGET_NETMAP=m -+CONFIG_IP_NF_TARGET_REDIRECT=m -+CONFIG_IP_NF_MANGLE=m -+CONFIG_IP_NF_TARGET_ECN=m -+CONFIG_IP_NF_TARGET_TTL=m -+CONFIG_IP_NF_RAW=m -+CONFIG_IP_NF_SECURITY=m -+CONFIG_IP_NF_ARPFILTER=m -+CONFIG_IP_NF_ARP_MANGLE=m -+CONFIG_NFT_DUP_IPV6=m -+CONFIG_NFT_FIB_IPV6=m -+CONFIG_IP6_NF_IPTABLES=m -+CONFIG_IP6_NF_MATCH_AH=m -+CONFIG_IP6_NF_MATCH_EUI64=m -+CONFIG_IP6_NF_MATCH_FRAG=m -+CONFIG_IP6_NF_MATCH_OPTS=m -+CONFIG_IP6_NF_MATCH_HL=m -+CONFIG_IP6_NF_MATCH_IPV6HEADER=m -+CONFIG_IP6_NF_MATCH_MH=m -+CONFIG_IP6_NF_MATCH_RPFILTER=m -+CONFIG_IP6_NF_MATCH_RT=m -+CONFIG_IP6_NF_MATCH_SRH=m -+CONFIG_IP6_NF_TARGET_HL=m -+CONFIG_IP6_NF_FILTER=m -+CONFIG_IP6_NF_TARGET_REJECT=m -+CONFIG_IP6_NF_TARGET_SYNPROXY=m -+CONFIG_IP6_NF_MANGLE=m -+CONFIG_IP6_NF_RAW=m -+CONFIG_IP6_NF_SECURITY=m -+CONFIG_IP6_NF_NAT=m -+CONFIG_IP6_NF_TARGET_MASQUERADE=m -+CONFIG_IP6_NF_TARGET_NPT=m -+CONFIG_NF_TABLES_BRIDGE=m -+CONFIG_NFT_BRIDGE_META=m -+CONFIG_NFT_BRIDGE_REJECT=m -+CONFIG_NF_CONNTRACK_BRIDGE=m -+CONFIG_BRIDGE_NF_EBTABLES=m -+CONFIG_BRIDGE_EBT_BROUTE=m -+CONFIG_BRIDGE_EBT_T_FILTER=m -+CONFIG_BRIDGE_EBT_T_NAT=m -+CONFIG_BRIDGE_EBT_802_3=m -+CONFIG_BRIDGE_EBT_AMONG=m -+CONFIG_BRIDGE_EBT_ARP=m -+CONFIG_BRIDGE_EBT_IP=m -+CONFIG_BRIDGE_EBT_IP6=m -+CONFIG_BRIDGE_EBT_LIMIT=m -+CONFIG_BRIDGE_EBT_MARK=m -+CONFIG_BRIDGE_EBT_PKTTYPE=m -+CONFIG_BRIDGE_EBT_STP=m -+CONFIG_BRIDGE_EBT_VLAN=m -+CONFIG_BRIDGE_EBT_ARPREPLY=m -+CONFIG_BRIDGE_EBT_DNAT=m -+CONFIG_BRIDGE_EBT_MARK_T=m -+CONFIG_BRIDGE_EBT_REDIRECT=m -+CONFIG_BRIDGE_EBT_SNAT=m -+CONFIG_BRIDGE_EBT_LOG=m -+CONFIG_BRIDGE_EBT_NFLOG=m -+CONFIG_SCTP_DEFAULT_COOKIE_HMAC_SHA1=y -+CONFIG_SCTP_COOKIE_HMAC_MD5=y -+CONFIG_RDS=m -+CONFIG_RDS_RDMA=m -+CONFIG_RDS_TCP=m -+CONFIG_TIPC=m -+CONFIG_TIPC_MEDIA_IB=y -+CONFIG_ATM=m -+CONFIG_ATM_CLIP=m -+CONFIG_ATM_LANE=m -+CONFIG_ATM_MPOA=m -+CONFIG_ATM_BR2684=m -+CONFIG_L2TP=m -+CONFIG_L2TP_DEBUGFS=m -+CONFIG_L2TP_V3=y -+CONFIG_L2TP_IP=m -+CONFIG_L2TP_ETH=m -+CONFIG_BRIDGE=m -+CONFIG_BRIDGE_VLAN_FILTERING=y -+CONFIG_BRIDGE_MRP=y -+CONFIG_BRIDGE_CFM=y -+CONFIG_NET_DSA=m -+CONFIG_NET_DSA_TAG_AR9331=m -+CONFIG_NET_DSA_TAG_HELLCREEK=m -+CONFIG_NET_DSA_TAG_GSWIP=m -+CONFIG_NET_DSA_TAG_DSA=m -+CONFIG_NET_DSA_TAG_EDSA=m -+CONFIG_NET_DSA_TAG_MTK=m -+CONFIG_NET_DSA_TAG_KSZ=m -+CONFIG_NET_DSA_TAG_OCELOT=m -+CONFIG_NET_DSA_TAG_OCELOT_8021Q=m -+CONFIG_NET_DSA_TAG_QCA=m -+CONFIG_NET_DSA_TAG_RTL4_A=m -+CONFIG_NET_DSA_TAG_RTL8_4=m -+CONFIG_NET_DSA_TAG_RZN1_A5PSW=m -+CONFIG_NET_DSA_TAG_LAN9303=m -+CONFIG_NET_DSA_TAG_SJA1105=m -+CONFIG_NET_DSA_TAG_TRAILER=m -+CONFIG_NET_DSA_TAG_VSC73XX_8021Q=m -+CONFIG_NET_DSA_TAG_XRS700X=m -+CONFIG_VLAN_8021Q=m -+CONFIG_VLAN_8021Q_GVRP=y -+CONFIG_VLAN_8021Q_MVRP=y -+CONFIG_LLC2=m -+CONFIG_ATALK=m -+CONFIG_PHONET=m -+CONFIG_6LOWPAN=m -+CONFIG_6LOWPAN_DEBUGFS=y -+CONFIG_6LOWPAN_GHC_EXT_HDR_HOP=m -+CONFIG_6LOWPAN_GHC_UDP=m -+CONFIG_6LOWPAN_GHC_ICMPV6=m -+CONFIG_6LOWPAN_GHC_EXT_HDR_DEST=m -+CONFIG_6LOWPAN_GHC_EXT_HDR_FRAG=m -+CONFIG_6LOWPAN_GHC_EXT_HDR_ROUTE=m -+CONFIG_IEEE802154=m -+CONFIG_IEEE802154_NL802154_EXPERIMENTAL=y -+CONFIG_IEEE802154_6LOWPAN=m -+CONFIG_MAC802154=m -+CONFIG_NET_SCHED=y -+CONFIG_NET_SCH_HTB=m -+CONFIG_NET_SCH_HFSC=m -+CONFIG_NET_SCH_PRIO=m -+CONFIG_NET_SCH_MULTIQ=m -+CONFIG_NET_SCH_RED=m -+CONFIG_NET_SCH_SFB=m -+CONFIG_NET_SCH_SFQ=m -+CONFIG_NET_SCH_TEQL=m -+CONFIG_NET_SCH_TBF=m -+CONFIG_NET_SCH_CBS=m -+CONFIG_NET_SCH_ETF=m -+CONFIG_NET_SCH_TAPRIO=m -+CONFIG_NET_SCH_GRED=m -+CONFIG_NET_SCH_NETEM=m -+CONFIG_NET_SCH_DRR=m -+CONFIG_NET_SCH_MQPRIO=m -+CONFIG_NET_SCH_SKBPRIO=m -+CONFIG_NET_SCH_CHOKE=m -+CONFIG_NET_SCH_QFQ=m -+CONFIG_NET_SCH_CODEL=m -+CONFIG_NET_SCH_FQ_CODEL=y -+CONFIG_NET_SCH_CAKE=m -+CONFIG_NET_SCH_FQ=m -+CONFIG_NET_SCH_HHF=m -+CONFIG_NET_SCH_PIE=m -+CONFIG_NET_SCH_FQ_PIE=m -+CONFIG_NET_SCH_INGRESS=m -+CONFIG_NET_SCH_PLUG=m -+CONFIG_NET_SCH_ETS=m -+CONFIG_NET_SCH_DEFAULT=y -+CONFIG_DEFAULT_FQ_CODEL=y -+CONFIG_NET_CLS_BASIC=m -+CONFIG_NET_CLS_ROUTE4=m -+CONFIG_NET_CLS_FW=m -+CONFIG_NET_CLS_U32=m -+CONFIG_CLS_U32_PERF=y -+CONFIG_CLS_U32_MARK=y -+CONFIG_NET_CLS_FLOW=m -+CONFIG_NET_CLS_CGROUP=m -+CONFIG_NET_CLS_BPF=m -+CONFIG_NET_CLS_FLOWER=m -+CONFIG_NET_CLS_MATCHALL=m -+CONFIG_NET_EMATCH=y -+CONFIG_NET_EMATCH_CMP=m -+CONFIG_NET_EMATCH_NBYTE=m -+CONFIG_NET_EMATCH_U32=m -+CONFIG_NET_EMATCH_META=m -+CONFIG_NET_EMATCH_TEXT=m -+CONFIG_NET_EMATCH_CANID=m -+CONFIG_NET_EMATCH_IPSET=m -+CONFIG_NET_EMATCH_IPT=m -+CONFIG_NET_CLS_ACT=y -+CONFIG_NET_ACT_POLICE=m -+CONFIG_NET_ACT_GACT=m -+CONFIG_GACT_PROB=y -+CONFIG_NET_ACT_MIRRED=m -+CONFIG_NET_ACT_SAMPLE=m -+CONFIG_NET_ACT_NAT=m -+CONFIG_NET_ACT_PEDIT=m -+CONFIG_NET_ACT_SIMP=m -+CONFIG_NET_ACT_SKBEDIT=m -+CONFIG_NET_ACT_CSUM=m -+CONFIG_NET_ACT_MPLS=m -+CONFIG_NET_ACT_VLAN=m -+CONFIG_NET_ACT_BPF=m -+CONFIG_NET_ACT_CONNMARK=m -+CONFIG_NET_ACT_CTINFO=m -+CONFIG_NET_ACT_SKBMOD=m -+CONFIG_NET_ACT_IFE=m -+CONFIG_NET_ACT_TUNNEL_KEY=m -+CONFIG_NET_ACT_CT=m -+CONFIG_NET_ACT_GATE=m -+CONFIG_NET_IFE_SKBMARK=m -+CONFIG_NET_IFE_SKBPRIO=m -+CONFIG_NET_IFE_SKBTCINDEX=m -+CONFIG_NET_TC_SKB_EXT=y -+CONFIG_DCB=y -+CONFIG_DNS_RESOLVER=y -+CONFIG_BATMAN_ADV=m -+CONFIG_BATMAN_ADV_NC=y -+CONFIG_OPENVSWITCH=m -+CONFIG_VSOCKETS=m -+CONFIG_VIRTIO_VSOCKETS=m -+CONFIG_NETLINK_DIAG=m -+CONFIG_MPLS_ROUTING=m -+CONFIG_MPLS_IPTUNNEL=m -+CONFIG_HSR=m -+CONFIG_QRTR_SMD=m -+CONFIG_QRTR_TUN=m -+CONFIG_NET_NCSI=y -+CONFIG_NCSI_OEM_CMD_GET_MAC=y -+CONFIG_NCSI_OEM_CMD_KEEP_PHY=y -+CONFIG_CGROUP_NET_PRIO=y -+CONFIG_BPF_STREAM_PARSER=y -+CONFIG_NET_PKTGEN=m -+CONFIG_NET_DROP_MONITOR=y -+CONFIG_CAN=m -+CONFIG_CAN_J1939=m -+CONFIG_CAN_ISOTP=m -+CONFIG_BT=m -+CONFIG_BT_RFCOMM=m -+CONFIG_BT_RFCOMM_TTY=y -+CONFIG_BT_BNEP=m -+CONFIG_BT_BNEP_MC_FILTER=y -+CONFIG_BT_BNEP_PROTO_FILTER=y -+CONFIG_BT_HIDP=m -+CONFIG_BT_6LOWPAN=m -+CONFIG_BT_LEDS=y -+CONFIG_BT_MSFTEXT=y -+CONFIG_BT_AOSPEXT=y -+CONFIG_BT_HCIBTUSB=m -+CONFIG_BT_HCIBTUSB_AUTOSUSPEND=y -+CONFIG_BT_HCIBTUSB_AUTO_ISOC_ALT=y -+CONFIG_BT_HCIBTUSB_MTK=y -+CONFIG_BT_HCIBTSDIO=m -+CONFIG_BT_HCIUART=m -+CONFIG_BT_HCIUART_NOKIA=m -+CONFIG_BT_HCIUART_BCSP=y -+CONFIG_BT_HCIUART_ATH3K=y -+CONFIG_BT_HCIUART_LL=y -+CONFIG_BT_HCIUART_INTEL=y -+CONFIG_BT_HCIUART_BCM=y -+CONFIG_BT_HCIUART_RTL=y -+CONFIG_BT_HCIUART_QCA=y -+CONFIG_BT_HCIUART_AG6XX=y -+CONFIG_BT_HCIUART_MRVL=y -+CONFIG_BT_HCIUART_AML=y -+CONFIG_BT_HCIBCM203X=m -+CONFIG_BT_HCIBCM4377=m -+CONFIG_BT_HCIBPA10X=m -+CONFIG_BT_HCIBFUSB=m -+CONFIG_BT_HCIVHCI=m -+CONFIG_BT_MRVL=m -+CONFIG_BT_MRVL_SDIO=m -+CONFIG_BT_ATH3K=m -+CONFIG_BT_MTKSDIO=m -+CONFIG_BT_MTKUART=m -+CONFIG_BT_VIRTIO=m -+CONFIG_BT_NXPUART=m -+CONFIG_BT_INTEL_PCIE=m -+CONFIG_AF_RXRPC=m -+CONFIG_AF_RXRPC_IPV6=y -+CONFIG_AF_RXRPC_DEBUG=y -+CONFIG_RXKAD=y -+CONFIG_AF_KCM=m -+CONFIG_MCTP=y -+CONFIG_CFG80211=m -+CONFIG_CFG80211_DEBUGFS=y -+CONFIG_CFG80211_WEXT=y -+CONFIG_MAC80211=m -+CONFIG_MAC80211_MESH=y -+CONFIG_MAC80211_DEBUGFS=y -+CONFIG_RFKILL=m -+CONFIG_RFKILL_GPIO=m -+CONFIG_NET_9P=y -+CONFIG_NET_9P_FD=m -+CONFIG_NET_9P_VIRTIO=m -+CONFIG_NET_9P_USBG=m -+CONFIG_NET_9P_RDMA=m -+CONFIG_CEPH_LIB_PRETTYDEBUG=y -+CONFIG_CEPH_LIB_USE_DNS_RESOLVER=y -+CONFIG_NFC=m -+CONFIG_NFC_DIGITAL=m -+CONFIG_NFC_NCI=m -+CONFIG_NFC_NCI_SPI=m -+CONFIG_NFC_NCI_UART=m -+CONFIG_NFC_HCI=m -+CONFIG_NFC_SHDLC=y -+CONFIG_NFC_TRF7970A=m -+CONFIG_NFC_SIM=m -+CONFIG_NFC_PORT100=m -+CONFIG_NFC_VIRTUAL_NCI=m -+CONFIG_NFC_FDP=m -+CONFIG_NFC_FDP_I2C=m -+CONFIG_NFC_PN544_I2C=m -+CONFIG_NFC_PN533_USB=m -+CONFIG_NFC_PN533_I2C=m -+CONFIG_NFC_PN532_UART=m -+CONFIG_NFC_MICROREAD_I2C=m -+CONFIG_NFC_MRVL_USB=m -+CONFIG_NFC_MRVL_UART=m -+CONFIG_NFC_MRVL_I2C=m -+CONFIG_NFC_MRVL_SPI=m -+CONFIG_NFC_ST21NFCA_I2C=m -+CONFIG_NFC_ST_NCI_I2C=m -+CONFIG_NFC_ST_NCI_SPI=m -+CONFIG_NFC_NXP_NCI=m -+CONFIG_NFC_NXP_NCI_I2C=m -+CONFIG_NFC_S3FWRN5_I2C=m -+CONFIG_NFC_S3FWRN82_UART=m -+CONFIG_NFC_ST95HF=m -+CONFIG_PAGE_POOL_STATS=y -+CONFIG_PCI=y -+CONFIG_PCIEAER=y -+CONFIG_PCIEAER_INJECT=m -+CONFIG_PCIE_ECRC=y -+CONFIG_PCIE_DPC=y -+CONFIG_PCIE_PTM=y -+CONFIG_PCIE_EDR=y -+CONFIG_PCI_STUB=y -+CONFIG_PCI_PF_STUB=m -+CONFIG_PCI_DOE=y -+CONFIG_PCI_IOV=y -+CONFIG_PCI_NPEM=y -+CONFIG_PCI_PRI=y -+CONFIG_PCI_PASID=y -+CONFIG_PCIE_TPH=y -+CONFIG_PCI_P2PDMA=y -+CONFIG_VGA_ARB_MAX_GPUS=10 -+CONFIG_HOTPLUG_PCI_ACPI=y -+CONFIG_HOTPLUG_PCI_SHPC=y -+CONFIG_PCI_HOST_GENERIC=y -+CONFIG_PCIE_DW_DEBUGFS=y -+CONFIG_PCIE_DW_PLAT_HOST=y -+CONFIG_PCIE_DW_PLAT_EP=y -+CONFIG_PCIE_QCOM=y -+CONFIG_PCIE_QCOM_EP=m -+CONFIG_PCI_ENDPOINT=y -+CONFIG_PCI_ENDPOINT_CONFIGFS=y -+CONFIG_PCI_EPF_TEST=m -+CONFIG_PCI_SW_SWITCHTEC=m -+CONFIG_PCI_PWRCTL_SLOT=y -+CONFIG_DEVTMPFS=y -+CONFIG_DEVTMPFS_MOUNT=y -+CONFIG_DEVTMPFS_SAFE=y -+CONFIG_RUST_FW_LOADER_ABSTRACTIONS=y -+CONFIG_FW_LOADER_USER_HELPER=y -+CONFIG_FW_LOADER_COMPRESS=y -+CONFIG_FW_LOADER_COMPRESS_ZSTD=y -+CONFIG_FW_UPLOAD=y -+# CONFIG_QCOM_EBI2 is not set -+CONFIG_MHI_BUS_PCI_GENERIC=m -+CONFIG_CONNECTOR=y -+CONFIG_ARM_SCMI_PROTOCOL=y -+CONFIG_ARM_SCMI_POWER_CONTROL=y -+CONFIG_ARM_SCPI_PROTOCOL=y -+CONFIG_DMI_SYSFS=y -+CONFIG_ISCSI_IBFT=m -+CONFIG_FW_CFG_SYSFS=m -+CONFIG_SYSFB_SIMPLEFB=y -+CONFIG_ARM_FFA_TRANSPORT=y -+CONFIG_EFI_VARS_PSTORE_DEFAULT_DISABLE=y -+CONFIG_EFI_ZBOOT=y -+CONFIG_EFI_BOOTLOADER_CONTROL=m -+CONFIG_EFI_CAPSULE_LOADER=m -+CONFIG_EFI_COCO_SECRET=y -+CONFIG_TEE_STMM_EFI=m -+CONFIG_QCOM_TZMEM_MODE_SHMBRIDGE=y -+CONFIG_QCOM_QSEECOM=y -+CONFIG_QCOM_QSEECOM_UEFISECAPP=y -+CONFIG_GNSS=m -+CONFIG_GNSS_MTK_SERIAL=m -+CONFIG_GNSS_SIRF_SERIAL=m -+CONFIG_GNSS_UBX_SERIAL=m -+CONFIG_GNSS_USB=m -+CONFIG_MTD=y -+CONFIG_MTD_BLOCK=m -+CONFIG_MTD_OOPS=m -+CONFIG_MTD_PSTORE=m -+CONFIG_MTD_PARTITIONED_MASTER=y -+CONFIG_MTD_ROM=m -+CONFIG_MTD_SPI_NAND=m -+CONFIG_MTD_NAND_ECC_SW_HAMMING=y -+CONFIG_MTD_NAND_ECC_SW_HAMMING_SMC=y -+CONFIG_MTD_NAND_ECC_SW_BCH=y -+CONFIG_MTD_NAND_ECC_MXIC=y -+CONFIG_MTD_SPI_NOR=y -+CONFIG_MTD_UBI=m -+CONFIG_MTD_UBI_NVMEM=m -+CONFIG_OF_OVERLAY=y -+CONFIG_BLK_DEV_NULL_BLK=m -+CONFIG_BLK_DEV_PCIESSD_MTIP32XX=m -+CONFIG_ZRAM=m -+CONFIG_ZRAM_BACKEND_LZ4=y -+CONFIG_ZRAM_BACKEND_LZ4HC=y -+CONFIG_ZRAM_BACKEND_ZSTD=y -+CONFIG_ZRAM_BACKEND_DEFLATE=y -+CONFIG_ZRAM_BACKEND_842=y -+CONFIG_ZRAM_BACKEND_LZO=y -+CONFIG_ZRAM_DEF_COMP_ZSTD=y -+CONFIG_ZRAM_WRITEBACK=y -+CONFIG_ZRAM_MEMORY_TRACKING=y -+CONFIG_ZRAM_MULTI_COMP=y -+CONFIG_BLK_DEV_LOOP=y -+CONFIG_BLK_DEV_DRBD=m -+CONFIG_BLK_DEV_NBD=m -+CONFIG_BLK_DEV_RAM=m -+CONFIG_BLK_DEV_RAM_SIZE=16384 -+CONFIG_ATA_OVER_ETH=m -+CONFIG_VIRTIO_BLK=y -+CONFIG_BLK_DEV_RBD=m -+CONFIG_BLK_DEV_UBLK=m -+CONFIG_BLK_DEV_RNBD_CLIENT=m -+CONFIG_BLK_DEV_RNBD_SERVER=m -+CONFIG_BLK_DEV_NVME=y -+CONFIG_NVME_MULTIPATH=y -+CONFIG_NVME_VERBOSE_ERRORS=y -+CONFIG_NVME_HWMON=y -+CONFIG_NVME_RDMA=m -+CONFIG_NVME_FC=m -+CONFIG_NVME_TCP=m -+CONFIG_NVME_TCP_TLS=y -+CONFIG_NVME_HOST_AUTH=y -+CONFIG_NVME_TARGET=m -+CONFIG_NVME_TARGET_DEBUGFS=y -+CONFIG_NVME_TARGET_PASSTHRU=y -+CONFIG_NVME_TARGET_LOOP=m -+CONFIG_NVME_TARGET_RDMA=m -+CONFIG_NVME_TARGET_FC=m -+CONFIG_NVME_TARGET_TCP=m -+CONFIG_NVME_TARGET_TCP_TLS=y -+CONFIG_NVME_TARGET_AUTH=y -+CONFIG_RPMB=y -+CONFIG_QCOM_COINCELL=m -+CONFIG_QCOM_FASTRPC=m -+CONFIG_SRAM=y -+CONFIG_PCI_ENDPOINT_TEST=m -+CONFIG_EEPROM_AT24=m -+CONFIG_EEPROM_AT25=m -+CONFIG_EEPROM_93CX6=y -+CONFIG_MISC_RTSX_PCI=m -+CONFIG_MISC_RTSX_USB=m -+CONFIG_UACCE=m -+CONFIG_RAID_ATTRS=m -+CONFIG_BLK_DEV_SD=y -+CONFIG_CHR_DEV_ST=m -+CONFIG_BLK_DEV_SR=m -+CONFIG_CHR_DEV_SG=m -+CONFIG_CHR_DEV_SCH=m -+CONFIG_SCSI_CONSTANTS=y -+CONFIG_SCSI_LOGGING=y -+CONFIG_SCSI_SCAN_ASYNC=y -+CONFIG_SCSI_SPI_ATTRS=m -+CONFIG_SCSI_FC_ATTRS=m -+CONFIG_SCSI_ISCSI_ATTRS=m -+CONFIG_SCSI_SAS_LIBSAS=m -+CONFIG_SCSI_SAS_ATA=y -+CONFIG_SCSI_SRP_ATTRS=m -+CONFIG_ATA=y -+CONFIG_SATA_AHCI=y -+CONFIG_SATA_AHCI_PLATFORM=y -+CONFIG_AHCI_DWC=m -+CONFIG_AHCI_CEVA=y -+CONFIG_SATA_SIL24=y -+CONFIG_PATA_OF_PLATFORM=y -+CONFIG_MD=y -+CONFIG_BLK_DEV_MD=m -+CONFIG_MD_RAID456=m -+CONFIG_BLK_DEV_DM=m -+CONFIG_DM_MIRROR=m -+CONFIG_DM_ZERO=m -+CONFIG_TARGET_CORE=m -+CONFIG_TCM_IBLOCK=m -+CONFIG_TCM_FILEIO=m -+CONFIG_TCM_PSCSI=m -+CONFIG_LOOPBACK_TARGET=m -+CONFIG_ISCSI_TARGET=m -+CONFIG_REMOTE_TARGET=m -+CONFIG_NETDEVICES=y -+CONFIG_BONDING=m -+CONFIG_DUMMY=m -+CONFIG_WIREGUARD=m -+CONFIG_EQUALIZER=m -+CONFIG_NET_FC=y -+CONFIG_IFB=m -+CONFIG_NET_TEAM=m -+CONFIG_NET_TEAM_MODE_BROADCAST=m -+CONFIG_NET_TEAM_MODE_ROUNDROBIN=m -+CONFIG_NET_TEAM_MODE_RANDOM=m -+CONFIG_NET_TEAM_MODE_ACTIVEBACKUP=m -+CONFIG_NET_TEAM_MODE_LOADBALANCE=m -+CONFIG_MACVLAN=m -+CONFIG_MACVTAP=m -+CONFIG_IPVLAN=m -+CONFIG_IPVTAP=m -+CONFIG_VXLAN=m -+CONFIG_GENEVE=m -+CONFIG_BAREUDP=m -+CONFIG_GTP=m -+CONFIG_PFCP=m -+CONFIG_AMT=m -+CONFIG_MACSEC=m -+CONFIG_NETCONSOLE=m -+CONFIG_NETCONSOLE_DYNAMIC=y -+CONFIG_NTB_NETDEV=m -+CONFIG_TUN=m -+CONFIG_VETH=m -+CONFIG_VIRTIO_NET=m -+CONFIG_NLMON=m -+CONFIG_NETKIT=y -+CONFIG_NET_VRF=m -+CONFIG_VSOCKMON=m -+CONFIG_MHI_NET=m -+CONFIG_B53_SRAB_DRIVER=m -+CONFIG_NET_DSA_BCM_SF2=m -+# CONFIG_NET_VENDOR_3COM is not set -+# CONFIG_NET_VENDOR_ADAPTEC is not set -+# CONFIG_NET_VENDOR_AGERE is not set -+# CONFIG_NET_VENDOR_ALACRITECH is not set -+# CONFIG_NET_VENDOR_ALTEON is not set -+# CONFIG_NET_VENDOR_AMAZON is not set -+# CONFIG_NET_VENDOR_AMD is not set -+# CONFIG_NET_VENDOR_AQUANTIA is not set -+# CONFIG_NET_VENDOR_ARC is not set -+# CONFIG_NET_VENDOR_ASIX is not set -+# CONFIG_NET_VENDOR_ATHEROS is not set -+# CONFIG_NET_VENDOR_BROADCOM is not set -+# CONFIG_NET_VENDOR_CADENCE is not set -+# CONFIG_NET_VENDOR_CAVIUM is not set -+# CONFIG_NET_VENDOR_CHELSIO is not set -+# CONFIG_NET_VENDOR_CISCO is not set -+# CONFIG_NET_VENDOR_CORTINA is not set -+# CONFIG_NET_VENDOR_DAVICOM is not set -+# CONFIG_NET_VENDOR_DEC is not set -+# CONFIG_NET_VENDOR_DLINK is not set -+# CONFIG_NET_VENDOR_EMULEX is not set -+# CONFIG_NET_VENDOR_ENGLEDER is not set -+# CONFIG_NET_VENDOR_EZCHIP is not set -+# CONFIG_NET_VENDOR_FUNGIBLE is not set -+# CONFIG_NET_VENDOR_GOOGLE is not set -+# CONFIG_NET_VENDOR_HISILICON is not set -+# CONFIG_NET_VENDOR_HUAWEI is not set -+# CONFIG_NET_VENDOR_INTEL is not set -+# CONFIG_NET_VENDOR_ADI is not set -+# CONFIG_NET_VENDOR_LITEX is not set -+# CONFIG_NET_VENDOR_MARVELL is not set -+# CONFIG_NET_VENDOR_MELLANOX is not set -+# CONFIG_NET_VENDOR_META is not set -+# CONFIG_NET_VENDOR_MICREL is not set -+# CONFIG_NET_VENDOR_MICROCHIP is not set -+# CONFIG_NET_VENDOR_MICROSEMI is not set -+# CONFIG_NET_VENDOR_MICROSOFT is not set -+# CONFIG_NET_VENDOR_MYRI is not set -+# CONFIG_NET_VENDOR_NI is not set -+# CONFIG_NET_VENDOR_NATSEMI is not set -+# CONFIG_NET_VENDOR_NETERION is not set -+# CONFIG_NET_VENDOR_NETRONOME is not set -+# CONFIG_NET_VENDOR_NVIDIA is not set -+# CONFIG_NET_VENDOR_OKI is not set -+# CONFIG_NET_VENDOR_PACKET_ENGINES is not set -+# CONFIG_NET_VENDOR_PENSANDO is not set -+# CONFIG_NET_VENDOR_QLOGIC is not set -+# CONFIG_NET_VENDOR_BROCADE is not set -+# CONFIG_NET_VENDOR_QUALCOMM is not set -+# CONFIG_NET_VENDOR_RDC is not set -+CONFIG_R8169=m -+# CONFIG_NET_VENDOR_RENESAS is not set -+# CONFIG_NET_VENDOR_ROCKER is not set -+# CONFIG_NET_VENDOR_SAMSUNG is not set -+# CONFIG_NET_VENDOR_SEEQ is not set -+# CONFIG_NET_VENDOR_SILAN is not set -+# CONFIG_NET_VENDOR_SIS is not set -+# CONFIG_NET_VENDOR_SOLARFLARE is not set -+# CONFIG_NET_VENDOR_SMSC is not set -+# CONFIG_NET_VENDOR_SOCIONEXT is not set -+# CONFIG_NET_VENDOR_STMICRO is not set -+# CONFIG_NET_VENDOR_SUN is not set -+# CONFIG_NET_VENDOR_SYNOPSYS is not set -+# CONFIG_NET_VENDOR_TEHUTI is not set -+# CONFIG_NET_VENDOR_TI is not set -+# CONFIG_NET_VENDOR_VERTEXCOM is not set -+# CONFIG_NET_VENDOR_VIA is not set -+# CONFIG_NET_VENDOR_WANGXUN is not set -+# CONFIG_NET_VENDOR_WIZNET is not set -+# CONFIG_NET_VENDOR_XILINX is not set -+CONFIG_PHYLIB=y -+CONFIG_AQUANTIA_PHY=y -+CONFIG_BROADCOM_PHY=m -+CONFIG_BCM54140_PHY=m -+CONFIG_MARVELL_PHY=m -+CONFIG_MARVELL_10G_PHY=y -+CONFIG_MARVELL_88Q2XXX_PHY=y -+CONFIG_MICREL_PHY=y -+CONFIG_MICROSEMI_PHY=m -+CONFIG_AT803X_PHY=y -+CONFIG_REALTEK_PHY=y -+CONFIG_ROCKCHIP_PHY=y -+CONFIG_DP83867_PHY=y -+CONFIG_DP83869_PHY=m -+CONFIG_DP83TD510_PHY=y -+CONFIG_VITESSE_PHY=y -+CONFIG_CAN_FLEXCAN=m -+CONFIG_CAN_M_CAN=m -+CONFIG_CAN_M_CAN_PLATFORM=m -+CONFIG_CAN_MCP251XFD=m -+CONFIG_MDIO_BITBANG=y -+CONFIG_MDIO_BCM_UNIMAC=y -+CONFIG_MDIO_GPIO=y -+CONFIG_MDIO_THUNDER=y -+CONFIG_MDIO_BUS_MUX_MULTIPLEXER=y -+CONFIG_MDIO_BUS_MUX_MMIOREG=y -+CONFIG_PCS_XPCS=m -+CONFIG_USB_PEGASUS=m -+CONFIG_USB_RTL8150=m -+CONFIG_USB_RTL8152=m -+CONFIG_USB_LAN78XX=m -+CONFIG_USB_USBNET=m -+CONFIG_USB_NET_DM9601=m -+CONFIG_USB_NET_SR9800=m -+CONFIG_USB_NET_SMSC75XX=m -+CONFIG_USB_NET_SMSC95XX=m -+CONFIG_USB_NET_PLUSB=m -+CONFIG_USB_NET_MCS7830=m -+# CONFIG_WLAN_VENDOR_ADMTEK is not set -+CONFIG_WLAN_VENDOR_AIC8800=y -+CONFIG_AIC8800_WLAN_SUPPORT=m -+CONFIG_AIC_LOADFW_SUPPORT=m -+CONFIG_ATH11K=m -+CONFIG_ATH11K_PCI=m -+CONFIG_ATH12K=m -+# CONFIG_WLAN_VENDOR_ATMEL is not set -+CONFIG_BRCMFMAC=m -+CONFIG_BRCMFMAC_USB=y -+CONFIG_BRCMFMAC_PCIE=y -+CONFIG_IWLWIFI=m -+CONFIG_IWLDVM=m -+CONFIG_IWLMVM=m -+CONFIG_IWLMLD=m -+# CONFIG_IWLWIFI_DEVICE_TRACING is not set -+# CONFIG_WLAN_VENDOR_INTERSIL is not set -+# CONFIG_WLAN_VENDOR_MARVELL is not set -+CONFIG_MT7601U=m -+CONFIG_MT76x0U=m -+CONFIG_MT76x0E=m -+CONFIG_MT76x2E=m -+CONFIG_MT76x2U=m -+CONFIG_MT7603E=m -+CONFIG_MT7615E=m -+CONFIG_MT7663U=m -+CONFIG_MT7663S=m -+CONFIG_MT7915E=m -+CONFIG_MT7921E=m -+CONFIG_MT7921S=m -+CONFIG_MT7921U=m -+CONFIG_MT7996E=m -+CONFIG_MT7925E=m -+CONFIG_MT7925U=m -+# CONFIG_WLAN_VENDOR_MICROCHIP is not set -+# CONFIG_WLAN_VENDOR_PURELIFI is not set -+# CONFIG_WLAN_VENDOR_RALINK is not set -+CONFIG_RTL8192CE=m -+CONFIG_RTL8192SE=m -+CONFIG_RTL8192DE=m -+CONFIG_RTL8723AE=m -+CONFIG_RTL8723BE=m -+CONFIG_RTL8188EE=m -+CONFIG_RTL8192EE=m -+CONFIG_RTL8821AE=m -+CONFIG_RTL8192CU=m -+CONFIG_RTL8192DU=m -+# CONFIG_RTLWIFI_DEBUG is not set -+CONFIG_RTL8XXXU=m -+CONFIG_RTL8XXXU_UNTESTED=y -+CONFIG_RTW88=m -+CONFIG_RTW88_8822BE=m -+CONFIG_RTW88_8822BS=m -+CONFIG_RTW88_8822BU=m -+CONFIG_RTW88_8822CE=m -+CONFIG_RTW88_8822CS=m -+CONFIG_RTW88_8822CU=m -+CONFIG_RTW88_8723DE=m -+CONFIG_RTW88_8723DS=m -+CONFIG_RTW88_8723CS=m -+CONFIG_RTW88_8723DU=m -+CONFIG_RTW88_8821CE=m -+CONFIG_RTW88_8821CS=m -+CONFIG_RTW88_8821CU=m -+CONFIG_RTW88_8821AU=m -+CONFIG_RTW88_8812AU=m -+CONFIG_RTW88_8814AE=m -+CONFIG_RTW88_8814AU=m -+CONFIG_RTW89=m -+CONFIG_RTW89_8851BE=m -+CONFIG_RTW89_8852AE=m -+CONFIG_RTW89_8852BE=m -+CONFIG_RTW89_8852BTE=m -+CONFIG_RTW89_8852CE=m -+CONFIG_RTW89_8922AE=m -+# CONFIG_WLAN_VENDOR_RSI is not set -+# CONFIG_WLAN_VENDOR_SILABS is not set -+# CONFIG_WLAN_VENDOR_ST is not set -+# CONFIG_WLAN_VENDOR_TI is not set -+# CONFIG_WLAN_VENDOR_ZYDAS is not set -+# CONFIG_WLAN_VENDOR_QUANTENNA is not set -+CONFIG_WWAN=m -+CONFIG_MHI_WWAN_CTRL=m -+CONFIG_MHI_WWAN_MBIM=m -+CONFIG_INPUT_SPARSEKMAP=m -+CONFIG_INPUT_MATRIXKMAP=m -+CONFIG_INPUT_MOUSEDEV=m -+CONFIG_INPUT_MOUSEDEV_PSAUX=y -+CONFIG_INPUT_JOYDEV=m -+CONFIG_INPUT_EVDEV=y -+CONFIG_KEYBOARD_ADC=m -+CONFIG_KEYBOARD_GPIO=y -+CONFIG_KEYBOARD_GPIO_POLLED=m -+CONFIG_KEYBOARD_MTK_PMIC=m -+CONFIG_MOUSE_ELAN_I2C=m -+CONFIG_INPUT_JOYSTICK=y -+CONFIG_INPUT_TABLET=y -+CONFIG_INPUT_TOUCHSCREEN=y -+CONFIG_TOUCHSCREEN_ATMEL_MXT=m -+CONFIG_TOUCHSCREEN_GOODIX=m -+CONFIG_TOUCHSCREEN_GOODIX_BERLIN_SPI=m -+CONFIG_TOUCHSCREEN_ELAN=m -+CONFIG_TOUCHSCREEN_EDT_FT5X06=m -+CONFIG_INPUT_MISC=y -+CONFIG_INPUT_PM8941_PWRKEY=y -+CONFIG_INPUT_PM8XXX_VIBRATOR=m -+CONFIG_INPUT_TPS65219_PWRBUTTON=m -+CONFIG_INPUT_PWM_BEEPER=m -+CONFIG_INPUT_PWM_VIBRA=m -+CONFIG_INPUT_RK805_PWRKEY=m -+CONFIG_INPUT_DA9063_ONKEY=m -+CONFIG_RMI4_CORE=m -+CONFIG_RMI4_I2C=m -+CONFIG_RMI4_SPI=m -+CONFIG_RMI4_SMB=m -+CONFIG_RMI4_F03=y -+CONFIG_RMI4_F11=y -+CONFIG_RMI4_F12=y -+CONFIG_RMI4_F30=y -+CONFIG_RMI4_F34=y -+CONFIG_RMI4_F3A=y -+CONFIG_RMI4_F55=y -+# CONFIG_SERIO_SERPORT is not set -+CONFIG_SERIO_AMBAKMI=y -+# CONFIG_LEGACY_PTYS is not set -+# CONFIG_LEGACY_TIOCSTI is not set -+CONFIG_SERIAL_8250=y -+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -+# CONFIG_SERIAL_8250_16550A_VARIANTS is not set -+CONFIG_SERIAL_8250_CONSOLE=y -+# CONFIG_SERIAL_8250_PCI is not set -+# CONFIG_SERIAL_8250_EXAR is not set -+CONFIG_SERIAL_8250_NR_UARTS=8 -+CONFIG_SERIAL_8250_EXTENDED=y -+CONFIG_SERIAL_8250_MANY_PORTS=y -+CONFIG_SERIAL_8250_SHARE_IRQ=y -+CONFIG_SERIAL_8250_DW=y -+# CONFIG_SERIAL_8250_PERICOM is not set -+CONFIG_SERIAL_OF_PLATFORM=y -+CONFIG_SERIAL_AMBA_PL011=y -+CONFIG_SERIAL_AMBA_PL011_CONSOLE=y -+CONFIG_SERIAL_QCOM_GENI=y -+CONFIG_SERIAL_QCOM_GENI_CONSOLE=y -+CONFIG_NULL_TTY=m -+CONFIG_RPMSG_TTY=m -+CONFIG_SERIAL_DEV_BUS=y -+CONFIG_VIRTIO_CONSOLE=y -+CONFIG_IPMI_HANDLER=m -+CONFIG_IPMI_DEVICE_INTERFACE=m -+CONFIG_IPMI_SI=m -+CONFIG_HW_RANDOM=y -+CONFIG_HW_RANDOM_VIRTIO=y -+CONFIG_HW_RANDOM_CN10K=y -+CONFIG_TCG_TPM=y -+CONFIG_TCG_TIS=m -+CONFIG_TCG_TIS_SPI=m -+CONFIG_TCG_TIS_SPI_CR50=y -+CONFIG_TCG_TIS_I2C_CR50=m -+CONFIG_TCG_TIS_I2C_INFINEON=y -+CONFIG_I2C_CHARDEV=y -+CONFIG_I2C_MUX=y -+CONFIG_I2C_MUX_PCA954x=y -+CONFIG_I2C_MUX_PINCTRL=m -+CONFIG_I2C_CADENCE=m -+CONFIG_I2C_DESIGNWARE_CORE=y -+CONFIG_I2C_GPIO=m -+CONFIG_I2C_QCOM_CCI=m -+CONFIG_I2C_QCOM_GENI=m -+CONFIG_I2C_QUP=y -+CONFIG_I2C_RK3X=y -+CONFIG_I2C_SLAVE=y -+CONFIG_SPI=y -+CONFIG_SPI_CADENCE_QUADSPI=y -+CONFIG_SPI_DESIGNWARE=m -+CONFIG_SPI_DW_DMA=y -+CONFIG_SPI_DW_MMIO=m -+CONFIG_SPI_PL022=y -+CONFIG_SPI_QCOM_QSPI=m -+CONFIG_SPI_QUP=y -+CONFIG_SPI_QCOM_GENI=m -+CONFIG_SPI_SPIDEV=m -+CONFIG_SPMI=y -+CONFIG_PINCTRL_DA9062=m -+CONFIG_PINCTRL_MAX77620=y -+CONFIG_PINCTRL_SINGLE=y -+# CONFIG_PINCTRL_TPS6594 is not set -+CONFIG_PINCTRL_MSM=y -+CONFIG_PINCTRL_QCS8300=y -+CONFIG_PINCTRL_SA8775P=y -+CONFIG_PINCTRL_SC7280=y -+CONFIG_PINCTRL_SM8550=y -+CONFIG_PINCTRL_X1E80100=y -+CONFIG_PINCTRL_QCOM_SPMI_PMIC=y -+CONFIG_PINCTRL_LPASS_LPI=m -+CONFIG_PINCTRL_SC7280_LPASS_LPI=m -+CONFIG_PINCTRL_SM6115_LPASS_LPI=m -+CONFIG_PINCTRL_SM8250_LPASS_LPI=m -+CONFIG_PINCTRL_SM8350_LPASS_LPI=m -+CONFIG_PINCTRL_SM8450_LPASS_LPI=m -+CONFIG_PINCTRL_SC8280XP_LPASS_LPI=m -+CONFIG_PINCTRL_SM8550_LPASS_LPI=m -+CONFIG_PINCTRL_SM8650_LPASS_LPI=m -+CONFIG_GPIO_ALTERA=m -+CONFIG_GPIO_DWAPB=y -+CONFIG_GPIO_GENERIC_PLATFORM=y -+CONFIG_GPIO_MB86S7X=y -+CONFIG_GPIO_PL061=y -+CONFIG_GPIO_SYSCON=y -+CONFIG_GPIO_WCD934X=m -+CONFIG_GPIO_XGENE=y -+CONFIG_GPIO_MAX732X=y -+CONFIG_GPIO_PCA953X=y -+CONFIG_GPIO_PCA953X_IRQ=y -+CONFIG_GPIO_PCF857X=m -+CONFIG_GPIO_ADP5585=m -+CONFIG_GPIO_BD9571MWV=m -+CONFIG_GPIO_MAX77620=y -+CONFIG_GPIO_AGGREGATOR=m -+CONFIG_POWER_RESET_MSM=y -+CONFIG_POWER_RESET_QCOM_PON=m -+CONFIG_POWER_RESET_SYSCON=y -+CONFIG_POWER_RESET_SYSCON_POWEROFF=y -+CONFIG_SYSCON_REBOOT_MODE=y -+CONFIG_NVMEM_REBOOT_MODE=m -+CONFIG_GENERIC_ADC_BATTERY=m -+CONFIG_BATTERY_QCOM_BATTMGR=m -+CONFIG_BATTERY_SBS=m -+CONFIG_BATTERY_BQ27XXX=y -+CONFIG_BATTERY_MAX17042=m -+CONFIG_CHARGER_MT6360=m -+CONFIG_CHARGER_BQ25890=m -+CONFIG_CHARGER_BQ25980=m -+CONFIG_CHARGER_RK817=m -+CONFIG_SENSORS_ARM_SCMI=y -+CONFIG_SENSORS_ARM_SCPI=y -+CONFIG_SENSORS_GPIO_FAN=m -+CONFIG_SENSORS_JC42=m -+CONFIG_SENSORS_LM75=m -+CONFIG_SENSORS_LM90=m -+CONFIG_SENSORS_PWM_FAN=m -+CONFIG_SENSORS_INA2XX=m -+CONFIG_SENSORS_INA3221=m -+CONFIG_THERMAL_NETLINK=y -+CONFIG_THERMAL_EMERGENCY_POWEROFF_DELAY_MS=100 -+CONFIG_THERMAL_GOV_FAIR_SHARE=y -+CONFIG_THERMAL_GOV_BANG_BANG=y -+CONFIG_THERMAL_GOV_USER_SPACE=y -+CONFIG_THERMAL_GOV_POWER_ALLOCATOR=y -+CONFIG_CPU_THERMAL=y -+CONFIG_DEVFREQ_THERMAL=y -+CONFIG_GENERIC_ADC_THERMAL=m -+CONFIG_QCOM_TSENS=y -+CONFIG_QCOM_SPMI_ADC_TM5=m -+CONFIG_QCOM_SPMI_TEMP_ALARM=m -+CONFIG_QCOM_LMH=m -+CONFIG_WATCHDOG=y -+CONFIG_WATCHDOG_SYSFS=y -+CONFIG_WATCHDOG_PRETIMEOUT_GOV=y -+CONFIG_WATCHDOG_PRETIMEOUT_GOV_NOOP=m -+CONFIG_SOFT_WATCHDOG=m -+CONFIG_ARM_SBSA_WATCHDOG=y -+CONFIG_DW_WATCHDOG=y -+CONFIG_QCOM_WDT=m -+CONFIG_ARM_SMC_WATCHDOG=y -+CONFIG_PM8916_WATCHDOG=m -+CONFIG_MFD_ADP5585=m -+CONFIG_MFD_BD9571MWV=y -+CONFIG_MFD_AXP20X_I2C=y -+CONFIG_MFD_DA9062=m -+CONFIG_MFD_HI6421_PMIC=y -+CONFIG_MFD_MAX77620=y -+CONFIG_MFD_MT6360=y -+CONFIG_MFD_MT6397=y -+CONFIG_MFD_SPMI_PMIC=y -+CONFIG_MFD_RK8XX_I2C=y -+CONFIG_MFD_RK8XX_SPI=y -+CONFIG_MFD_SEC_CORE=y -+CONFIG_MFD_TI_LP873X=m -+CONFIG_MFD_TPS65219=y -+CONFIG_MFD_TPS6594_I2C=m -+CONFIG_MFD_WM8994=m -+CONFIG_MFD_ROHM_BD718XX=y -+CONFIG_MFD_WCD934X=m -+CONFIG_REGULATOR_FIXED_VOLTAGE=y -+CONFIG_REGULATOR_ARM_SCMI=y -+CONFIG_REGULATOR_AXP20X=y -+CONFIG_REGULATOR_BD718XX=y -+CONFIG_REGULATOR_BD9571MWV=y -+CONFIG_REGULATOR_DA9211=m -+CONFIG_REGULATOR_FAN53555=y -+CONFIG_REGULATOR_GPIO=y -+CONFIG_REGULATOR_HI6421V530=y -+CONFIG_REGULATOR_LP873X=m -+CONFIG_REGULATOR_MAX77620=y -+CONFIG_REGULATOR_MAX8973=y -+CONFIG_REGULATOR_MAX20411=m -+CONFIG_REGULATOR_MP8859=y -+CONFIG_REGULATOR_MT6315=m -+CONFIG_REGULATOR_MT6357=y -+CONFIG_REGULATOR_MT6358=y -+CONFIG_REGULATOR_MT6359=y -+CONFIG_REGULATOR_MT6360=y -+CONFIG_REGULATOR_MT6397=y -+CONFIG_REGULATOR_PCA9450=y -+CONFIG_REGULATOR_PF8X00=y -+CONFIG_REGULATOR_PFUZE100=y -+CONFIG_REGULATOR_PWM=y -+CONFIG_REGULATOR_QCOM_REFGEN=m -+CONFIG_REGULATOR_QCOM_RPMH=y -+CONFIG_REGULATOR_QCOM_SPMI=y -+CONFIG_REGULATOR_QCOM_USB_VBUS=m -+CONFIG_REGULATOR_RAA215300=y -+CONFIG_REGULATOR_RK808=y -+CONFIG_REGULATOR_S2MPS11=y -+CONFIG_REGULATOR_TPS65132=m -+CONFIG_REGULATOR_TPS65219=y -+CONFIG_REGULATOR_VCTRL=m -+CONFIG_RC_CORE=m -+CONFIG_LIRC=y -+# CONFIG_RC_MAP is not set -+CONFIG_RC_DECODERS=y -+CONFIG_RC_DEVICES=y -+CONFIG_IR_GPIO_CIR=m -+CONFIG_MEDIA_CEC_SUPPORT=y -+CONFIG_CEC_NXP_TDA9950=m -+CONFIG_MEDIA_SUPPORT=m -+CONFIG_MEDIA_CAMERA_SUPPORT=y -+CONFIG_MEDIA_ANALOG_TV_SUPPORT=y -+CONFIG_MEDIA_DIGITAL_TV_SUPPORT=y -+CONFIG_MEDIA_SDR_SUPPORT=y -+CONFIG_MEDIA_PLATFORM_SUPPORT=y -+# CONFIG_DVB_NET is not set -+CONFIG_MEDIA_USB_SUPPORT=y -+CONFIG_USB_VIDEO_CLASS=m -+CONFIG_V4L_PLATFORM_DRIVERS=y -+CONFIG_SDR_PLATFORM_DRIVERS=y -+CONFIG_V4L_MEM2MEM_DRIVERS=y -+CONFIG_VIDEO_CADENCE_CSI2RX=m -+CONFIG_VIDEO_QCOM_CAMSS=m -+CONFIG_VIDEO_QCOM_IRIS=m -+CONFIG_VIDEO_QCOM_VENUS=m -+CONFIG_VIDEO_IMX219=m -+CONFIG_VIDEO_IMX412=m -+CONFIG_VIDEO_OV5640=m -+CONFIG_VIDEO_OV5645=m -+CONFIG_DRM=y -+CONFIG_DRM_PANIC=y -+CONFIG_DRM_PANIC_SCREEN="qr_code" -+CONFIG_DRM_PANIC_SCREEN_QR_CODE=y -+CONFIG_DRM_PANIC_SCREEN_QR_CODE_URL="https://panic.archlinux.org/panic_report#" -+CONFIG_DRM_CLIENT_LOG=y -+CONFIG_DRM_LOAD_EDID_FIRMWARE=y -+CONFIG_DRM_DISPLAY_DP_AUX_CEC=y -+CONFIG_DRM_DISPLAY_DP_AUX_CHARDEV=y -+CONFIG_DRM_MSM=y -+# CONFIG_DRM_MSM_DSI_28NM_PHY is not set -+# CONFIG_DRM_MSM_DSI_20NM_PHY is not set -+# CONFIG_DRM_MSM_DSI_28NM_8960_PHY is not set -+# CONFIG_DRM_MSM_DSI_14NM_PHY is not set -+# CONFIG_DRM_MSM_DSI_10NM_PHY is not set -+# CONFIG_DRM_MSM_HDMI is not set -+CONFIG_DRM_PANEL_BOE_TV101WUM_NL6=m -+CONFIG_DRM_PANEL_LVDS=m -+CONFIG_DRM_PANEL_ILITEK_ILI9882T=m -+CONFIG_DRM_PANEL_KHADAS_TS050=m -+CONFIG_DRM_PANEL_MANTIX_MLAF057WE51=m -+CONFIG_DRM_PANEL_NOVATEK_NT36672E=m -+CONFIG_DRM_PANEL_RAYDIUM_RM67191=m -+CONFIG_DRM_PANEL_SAMSUNG_ATNA33XC20=m -+CONFIG_DRM_PANEL_SITRONIX_ST7703=m -+CONFIG_DRM_PANEL_EDP=m -+CONFIG_DRM_PANEL_SIMPLE=m -+CONFIG_DRM_PANEL_TRULY_NT35597_WQXGA=m -+CONFIG_DRM_PANEL_VISIONOX_VTDR6130=m -+CONFIG_DRM_DISPLAY_CONNECTOR=y -+CONFIG_DRM_SIMPLE_BRIDGE=y -+CONFIG_DRM_SIMPLEDRM=y -+CONFIG_FB=y -+CONFIG_FB_EFI=y -+CONFIG_BACKLIGHT_CLASS_DEVICE=m -+CONFIG_BACKLIGHT_PWM=m -+CONFIG_BACKLIGHT_QCOM_WLED=m -+CONFIG_BACKLIGHT_LP855X=m -+CONFIG_BACKLIGHT_GPIO=m -+CONFIG_BACKLIGHT_LED=m -+CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y -+CONFIG_FRAMEBUFFER_CONSOLE_DEFERRED_TAKEOVER=y -+CONFIG_SOUND=y -+CONFIG_SND=y -+CONFIG_SND_ALOOP=m -+CONFIG_SND_SOC=y -+CONFIG_SND_SOC_FSL_ASRC=m -+CONFIG_SND_SOC_FSL_SAI=m -+CONFIG_SND_SOC_FSL_AUDMIX=m -+CONFIG_SND_SOC_FSL_SSI=m -+CONFIG_SND_SOC_FSL_SPDIF=m -+CONFIG_SND_SOC_FSL_ESAI=m -+CONFIG_SND_SOC_FSL_MICFIL=m -+CONFIG_SND_SOC_FSL_EASRC=m -+CONFIG_SND_SOC_IMX_AUDMUX=m -+CONFIG_SND_SOC_QCOM=m -+CONFIG_SND_SOC_SC8280XP=m -+CONFIG_SND_SOC_SC7280=m -+CONFIG_SND_SOC_X1E80100=m -+CONFIG_SND_SOC_SOF_TOPLEVEL=y -+CONFIG_SND_SOC_SOF_OF=y -+CONFIG_SND_SOC_SOF_MTK_TOPLEVEL=y -+CONFIG_SND_SOC_ADAU7002=m -+CONFIG_SND_SOC_AK4613=m -+CONFIG_SND_SOC_AK4619=m -+CONFIG_SND_SOC_BT_SCO=m -+CONFIG_SND_SOC_DA7213=m -+CONFIG_SND_SOC_DMIC=m -+CONFIG_SND_SOC_ES7134=m -+CONFIG_SND_SOC_ES7241=m -+CONFIG_SND_SOC_ES8316=m -+CONFIG_SND_SOC_ES8326=m -+CONFIG_SND_SOC_GTM601=m -+CONFIG_SND_SOC_MAX98927=m -+CONFIG_SND_SOC_MAX98390=m -+CONFIG_SND_SOC_MSM8916_WCD_ANALOG=m -+CONFIG_SND_SOC_MSM8916_WCD_DIGITAL=m -+CONFIG_SND_SOC_PCM3168A_I2C=m -+CONFIG_SND_SOC_RK817=m -+CONFIG_SND_SOC_RT5640=m -+CONFIG_SND_SOC_RT5659=m -+CONFIG_SND_SOC_SGTL5000=m -+CONFIG_SND_SOC_SIMPLE_AMPLIFIER=m -+CONFIG_SND_SOC_SIMPLE_MUX=m -+CONFIG_SND_SOC_SPDIF=m -+CONFIG_SND_SOC_TAS2552=m -+CONFIG_SND_SOC_TAS571X=m -+CONFIG_SND_SOC_TLV320AIC31XX=m -+CONFIG_SND_SOC_TLV320AIC32X4_I2C=m -+CONFIG_SND_SOC_TLV320AIC3X_I2C=m -+CONFIG_SND_SOC_TS3A227E=m -+CONFIG_SND_SOC_WCD9335=m -+CONFIG_SND_SOC_WCD934X=m -+CONFIG_SND_SOC_WCD939X_SDW=m -+CONFIG_SND_SOC_WM8524=m -+CONFIG_SND_SOC_WM8904=m -+CONFIG_SND_SOC_WM8960=m -+CONFIG_SND_SOC_WM8962=m -+CONFIG_SND_SOC_WM8978=m -+CONFIG_SND_SOC_WSA881X=m -+CONFIG_SND_SOC_WSA883X=m -+CONFIG_SND_SOC_WSA884X=m -+CONFIG_SND_SOC_MT6357=m -+CONFIG_SND_SOC_MT6358=m -+CONFIG_SND_SOC_NAU8315=m -+CONFIG_SND_SOC_NAU8822=m -+CONFIG_SND_SOC_LPASS_WSA_MACRO=m -+CONFIG_SND_SOC_LPASS_VA_MACRO=m -+CONFIG_SND_SIMPLE_CARD=m -+CONFIG_SND_AUDIO_GRAPH_CARD=m -+CONFIG_SND_AUDIO_GRAPH_CARD2=m -+CONFIG_HID_MICROSOFT=m -+CONFIG_HID_MULTITOUCH=m -+CONFIG_I2C_HID_ACPI=m -+CONFIG_I2C_HID_OF=m -+CONFIG_I2C_HID_OF_ELAN=m -+CONFIG_USB_LED_TRIG=y -+CONFIG_USB_ULPI_BUS=m -+CONFIG_USB_CONN_GPIO=m -+CONFIG_USB=y -+CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -+CONFIG_USB_LEDS_TRIGGER_USBPORT=m -+CONFIG_USB_MON=m -+CONFIG_USB_XHCI_HCD=y -+CONFIG_USB_XHCI_DBGCAP=y -+CONFIG_USB_XHCI_PCI_RENESAS=m -+CONFIG_USB_EHCI_HCD=y -+CONFIG_USB_EHCI_ROOT_HUB_TT=y -+CONFIG_USB_EHCI_HCD_PLATFORM=y -+CONFIG_USB_OHCI_HCD=y -+CONFIG_USB_OHCI_HCD_PLATFORM=y -+CONFIG_USB_ACM=m -+CONFIG_USB_PRINTER=m -+CONFIG_USB_WDM=m -+CONFIG_USB_TMC=m -+CONFIG_USB_STORAGE=y -+CONFIG_USB_STORAGE_REALTEK=m -+CONFIG_USB_STORAGE_DATAFAB=m -+CONFIG_USB_STORAGE_FREECOM=m -+CONFIG_USB_STORAGE_ISD200=m -+CONFIG_USB_STORAGE_USBAT=m -+CONFIG_USB_STORAGE_SDDR09=m -+CONFIG_USB_STORAGE_SDDR55=m -+CONFIG_USB_STORAGE_JUMPSHOT=m -+CONFIG_USB_STORAGE_ALAUDA=m -+CONFIG_USB_STORAGE_ONETOUCH=m -+CONFIG_USB_STORAGE_KARMA=m -+CONFIG_USB_STORAGE_CYPRESS_ATACB=m -+CONFIG_USB_STORAGE_ENE_UB6250=m -+CONFIG_USB_UAS=m -+CONFIG_USB_MDC800=m -+CONFIG_USB_MICROTEK=m -+CONFIG_USBIP_CORE=m -+CONFIG_USBIP_VHCI_HCD=m -+CONFIG_USBIP_HOST=m -+CONFIG_USBIP_VUDC=m -+CONFIG_USB_MUSB_HDRC=y -+CONFIG_USB_DWC3=y -+CONFIG_USB_SERIAL=y -+CONFIG_USB_SERIAL_CONSOLE=y -+CONFIG_USB_SERIAL_GENERIC=y -+CONFIG_USB_SERIAL_SIMPLE=m -+CONFIG_USB_SERIAL_CH341=m -+CONFIG_USB_SERIAL_CP210X=m -+CONFIG_USB_SERIAL_FTDI_SIO=m -+CONFIG_USB_SERIAL_QCAUX=m -+CONFIG_USB_SERIAL_QUALCOMM=m -+CONFIG_USB_SERIAL_OPTION=m -+CONFIG_USB_QCOM_EUD=y -+CONFIG_USB_ONBOARD_DEV=y -+CONFIG_NOP_USB_XCEIV=y -+CONFIG_USB_GPIO_VBUS=m -+CONFIG_USB_ULPI=y -+CONFIG_USB_GADGET=y -+CONFIG_U_SERIAL_CONSOLE=y -+CONFIG_USB_CONFIGFS=m -+CONFIG_USB_CONFIGFS_SERIAL=y -+CONFIG_USB_CONFIGFS_ACM=y -+CONFIG_USB_CONFIGFS_OBEX=y -+CONFIG_USB_CONFIGFS_NCM=y -+CONFIG_USB_CONFIGFS_ECM=y -+CONFIG_USB_CONFIGFS_ECM_SUBSET=y -+CONFIG_USB_CONFIGFS_RNDIS=y -+CONFIG_USB_CONFIGFS_EEM=y -+CONFIG_USB_CONFIGFS_PHONET=y -+CONFIG_USB_CONFIGFS_MASS_STORAGE=y -+CONFIG_USB_CONFIGFS_F_LB_SS=y -+CONFIG_USB_CONFIGFS_F_FS=y -+CONFIG_USB_CONFIGFS_F_UAC1=y -+CONFIG_USB_CONFIGFS_F_UAC1_LEGACY=y -+CONFIG_USB_CONFIGFS_F_UAC2=y -+CONFIG_USB_CONFIGFS_F_MIDI=y -+CONFIG_USB_CONFIGFS_F_MIDI2=y -+CONFIG_USB_CONFIGFS_F_HID=y -+CONFIG_USB_CONFIGFS_F_UVC=y -+CONFIG_USB_CONFIGFS_F_PRINTER=y -+CONFIG_USB_CONFIGFS_F_TCM=y -+CONFIG_USB_ZERO=m -+CONFIG_USB_AUDIO=m -+CONFIG_USB_ETH=m -+CONFIG_USB_ETH_EEM=y -+CONFIG_USB_G_NCM=m -+CONFIG_USB_GADGETFS=m -+CONFIG_USB_FUNCTIONFS=m -+CONFIG_USB_FUNCTIONFS_ETH=y -+CONFIG_USB_FUNCTIONFS_RNDIS=y -+CONFIG_USB_FUNCTIONFS_GENERIC=y -+CONFIG_USB_MASS_STORAGE=m -+CONFIG_USB_GADGET_TARGET=m -+CONFIG_USB_G_SERIAL=m -+CONFIG_USB_MIDI_GADGET=m -+CONFIG_USB_G_PRINTER=m -+CONFIG_USB_CDC_COMPOSITE=m -+CONFIG_USB_G_NOKIA=m -+CONFIG_USB_G_ACM_MS=m -+CONFIG_USB_G_MULTI=m -+CONFIG_USB_G_MULTI_CDC=y -+CONFIG_USB_G_HID=m -+CONFIG_USB_G_DBGP=m -+CONFIG_USB_G_WEBCAM=m -+CONFIG_USB_RAW_GADGET=m -+CONFIG_TYPEC=y -+CONFIG_TYPEC_TCPM=m -+CONFIG_TYPEC_TCPCI=m -+CONFIG_TYPEC_TCPCI_MAXIM=m -+CONFIG_TYPEC_FUSB302=m -+CONFIG_TYPEC_QCOM_PMIC=m -+CONFIG_TYPEC_UCSI=m -+CONFIG_UCSI_CCG=m -+CONFIG_UCSI_PMIC_GLINK=m -+CONFIG_TYPEC_TPS6598X=m -+CONFIG_TYPEC_HD3SS3220=m -+CONFIG_TYPEC_MUX_FSA4480=m -+CONFIG_TYPEC_MUX_GPIO_SBU=m -+CONFIG_TYPEC_MUX_NB7VPQ904M=m -+CONFIG_TYPEC_MUX_PS883X=m -+CONFIG_TYPEC_MUX_WCD939X_USBSS=m -+CONFIG_TYPEC_DP_ALTMODE=m -+CONFIG_MMC=y -+CONFIG_SDIO_UART=m -+CONFIG_MMC_CRYPTO=y -+CONFIG_MMC_ARMMMCI=y -+# CONFIG_MMC_STM32_SDMMC is not set -+CONFIG_MMC_SDHCI=y -+CONFIG_MMC_SDHCI_ACPI=y -+CONFIG_MMC_SDHCI_PLTFM=y -+CONFIG_MMC_SDHCI_OF_DWCMSHC=y -+CONFIG_MMC_SDHCI_MSM=y -+CONFIG_MMC_SPI=y -+CONFIG_MMC_HSQ=y -+CONFIG_SCSI_UFSHCD=y -+CONFIG_SCSI_UFS_BSG=y -+CONFIG_SCSI_UFS_CRYPTO=y -+CONFIG_SCSI_UFS_HWMON=y -+CONFIG_SCSI_UFSHCD_PLATFORM=y -+CONFIG_SCSI_UFS_QCOM=y -+CONFIG_NEW_LEDS=y -+CONFIG_LEDS_CLASS=y -+CONFIG_LEDS_CLASS_MULTICOLOR=m -+CONFIG_LEDS_LM3692X=m -+CONFIG_LEDS_PCA9532=m -+CONFIG_LEDS_GPIO=y -+CONFIG_LEDS_PWM=y -+CONFIG_LEDS_SYSCON=y -+CONFIG_LEDS_QCOM_LPG=m -+CONFIG_LEDS_TRIGGER_TIMER=y -+CONFIG_LEDS_TRIGGER_DISK=y -+CONFIG_LEDS_TRIGGER_HEARTBEAT=y -+CONFIG_LEDS_TRIGGER_CPU=y -+CONFIG_LEDS_TRIGGER_DEFAULT_ON=y -+CONFIG_LEDS_TRIGGER_PANIC=y -+CONFIG_INFINIBAND=m -+CONFIG_INFINIBAND_IPOIB=m -+CONFIG_INFINIBAND_RTRS_CLIENT=m -+CONFIG_INFINIBAND_RTRS_SERVER=m -+CONFIG_EDAC=y -+CONFIG_EDAC_GHES=y -+CONFIG_EDAC_SCRUB=y -+CONFIG_EDAC_ECS=y -+CONFIG_EDAC_MEM_REPAIR=y -+CONFIG_EDAC_QCOM=y -+CONFIG_RTC_CLASS=y -+CONFIG_RTC_DRV_DS1307=m -+CONFIG_RTC_DRV_HYM8563=m -+CONFIG_RTC_DRV_MAX77686=y -+CONFIG_RTC_DRV_RK808=m -+CONFIG_RTC_DRV_ISL1208=m -+CONFIG_RTC_DRV_PCF85063=m -+CONFIG_RTC_DRV_PCF85363=m -+CONFIG_RTC_DRV_PCF8563=m -+CONFIG_RTC_DRV_M41T80=m -+CONFIG_RTC_DRV_BQ32K=m -+CONFIG_RTC_DRV_RX8581=m -+CONFIG_RTC_DRV_RV3028=m -+CONFIG_RTC_DRV_RV8803=m -+CONFIG_RTC_DRV_S5M=y -+CONFIG_RTC_DRV_DS3232=y -+CONFIG_RTC_DRV_PCF2127=m -+CONFIG_RTC_DRV_DA9063=m -+CONFIG_RTC_DRV_EFI=y -+CONFIG_RTC_DRV_PL031=y -+CONFIG_RTC_DRV_PM8XXX=m -+CONFIG_RTC_DRV_MT6397=m -+CONFIG_DMADEVICES=y -+CONFIG_BCM_SBA_RAID=m -+CONFIG_FSL_EDMA=y -+CONFIG_MV_XOR_V2=y -+CONFIG_PL330_DMA=y -+CONFIG_QCOM_BAM_DMA=y -+CONFIG_QCOM_GPI_DMA=m -+CONFIG_QCOM_HIDMA_MGMT=y -+CONFIG_QCOM_HIDMA=y -+CONFIG_DW_EDMA=m -+CONFIG_UDMABUF=y -+CONFIG_DMABUF_HEAPS=y -+CONFIG_DMABUF_SYSFS_STATS=y -+CONFIG_DMABUF_HEAPS_SYSTEM=y -+CONFIG_DMABUF_HEAPS_CMA=y -+CONFIG_VFIO=y -+CONFIG_VFIO_PCI=y -+CONFIG_VIRTIO_PCI=y -+CONFIG_VIRTIO_BALLOON=y -+CONFIG_VIRTIO_MMIO=y -+CONFIG_VHOST_VSOCK=m -+CONFIG_STAGING=y -+# CONFIG_SURFACE_PLATFORMS is not set -+# CONFIG_ARM64_PLATFORM_DEVICES is not set -+CONFIG_COMMON_CLK_RK808=y -+CONFIG_COMMON_CLK_SCMI=y -+CONFIG_COMMON_CLK_SCPI=y -+CONFIG_COMMON_CLK_CS2000_CP=y -+CONFIG_COMMON_CLK_S2MPS11=y -+CONFIG_COMMON_CLK_XGENE=y -+CONFIG_COMMON_CLK_PWM=y -+CONFIG_COMMON_CLK_RS9_PCIE=y -+CONFIG_COMMON_CLK_VC3=y -+CONFIG_COMMON_CLK_VC5=y -+CONFIG_COMMON_CLK_BD718XX=m -+CONFIG_COMMON_CLK_QCOM=y -+CONFIG_CLK_X1E80100_CAMCC=m -+CONFIG_CLK_X1E80100_DISPCC=m -+CONFIG_CLK_X1E80100_GCC=y -+CONFIG_CLK_X1E80100_GPUCC=m -+CONFIG_CLK_X1E80100_TCSRCC=y -+CONFIG_QCOM_CLK_RPMH=y -+CONFIG_SA_CAMCC_8775P=m -+CONFIG_QCS_GCC_8300=y -+CONFIG_SC_CAMCC_7280=m -+CONFIG_SA_DISPCC_8775P=m -+CONFIG_SC_DISPCC_7280=y -+CONFIG_SC_DISPCC_8280XP=m -+CONFIG_SA_GCC_8775P=y -+CONFIG_SA_GPUCC_8775P=m -+CONFIG_SC_GCC_8280XP=y -+CONFIG_SC_GPUCC_7280=y -+CONFIG_SC_LPASSCC_7280=m -+CONFIG_SC_LPASS_CORECC_7280=m -+CONFIG_SC_VIDEOCC_7280=m -+CONFIG_SM_DISPCC_8550=m -+CONFIG_SM_GCC_8250=y -+CONFIG_SM_GCC_8550=y -+CONFIG_SM_GPUCC_8550=m -+CONFIG_SM_TCSRCC_8550=y -+CONFIG_SA_VIDEOCC_8775P=m -+CONFIG_SM_VIDEOCC_8550=m -+CONFIG_QCOM_HFPLL=y -+CONFIG_HWSPINLOCK=y -+CONFIG_HWSPINLOCK_QCOM=y -+CONFIG_ARM_TIMER_SP804=y -+CONFIG_ARM_MHU=y -+CONFIG_PLATFORM_MHU=y -+CONFIG_QCOM_APCS_IPC=y -+CONFIG_QCOM_IPCC=y -+CONFIG_IOMMU_IO_PGTABLE_ARMV7S=y -+CONFIG_ARM_SMMU=y -+CONFIG_ARM_SMMU_QCOM_DEBUG=y -+CONFIG_ARM_SMMU_V3=y -+CONFIG_QCOM_IOMMU=y -+CONFIG_REMOTEPROC=y -+CONFIG_REMOTEPROC_CDEV=y -+CONFIG_QCOM_Q6V5_ADSP=m -+CONFIG_QCOM_Q6V5_MSS=m -+CONFIG_QCOM_Q6V5_PAS=m -+CONFIG_QCOM_SYSMON=m -+CONFIG_QCOM_WCNSS_PIL=m -+CONFIG_RPMSG_CHAR=m -+CONFIG_RPMSG_CTRL=m -+CONFIG_RPMSG_NS=y -+CONFIG_RPMSG_QCOM_GLINK_RPM=y -+CONFIG_RPMSG_QCOM_GLINK_SMEM=m -+CONFIG_RPMSG_QCOM_SMD=y -+CONFIG_SOUNDWIRE=m -+CONFIG_SOUNDWIRE_QCOM=m -+CONFIG_QCOM_AOSS_QMP=y -+CONFIG_QCOM_COMMAND_DB=y -+CONFIG_QCOM_GENI_SE=y -+CONFIG_QCOM_LLCC=y -+CONFIG_QCOM_PMIC_PDCHARGER_ULOG=m -+CONFIG_QCOM_PMIC_GLINK=y -+CONFIG_QCOM_RMTFS_MEM=y -+CONFIG_QCOM_RPMH=y -+CONFIG_QCOM_SMEM=y -+CONFIG_QCOM_SMP2P=y -+CONFIG_QCOM_SOCINFO=y -+CONFIG_QCOM_STATS=y -+CONFIG_QCOM_APR=y -+CONFIG_QCOM_ICC_BWMON=y -+CONFIG_QCOM_PBS=y -+CONFIG_QCOM_CPR=y -+CONFIG_QCOM_RPMHPD=y -+CONFIG_DEVFREQ_GOV_USERSPACE=y -+CONFIG_DEVFREQ_GOV_PASSIVE=m -+CONFIG_EXTCON_PTN5150=m -+CONFIG_EXTCON_USB_GPIO=y -+CONFIG_IIO=y -+CONFIG_MAX9611=m -+CONFIG_QCOM_SPMI_VADC=m -+CONFIG_QCOM_SPMI_ADC5=m -+CONFIG_TI_ADS1015=m -+CONFIG_IIO_ST_LSM6DSX=m -+CONFIG_SENSORS_ISL29018=m -+CONFIG_VCNL4000=m -+CONFIG_IIO_ST_MAGN_3AXIS=m -+CONFIG_MPL3115=m -+CONFIG_NTB=m -+CONFIG_NTB_TRANSPORT=m -+CONFIG_PWM=y -+CONFIG_PWM_ADP5585=m -+CONFIG_QCOM_PDC=y -+CONFIG_QCOM_MPM=y -+CONFIG_RESET_GPIO=m -+CONFIG_RESET_QCOM_AOSS=y -+CONFIG_RESET_QCOM_PDC=m -+CONFIG_PHY_NXP_PTN3222=m -+CONFIG_PHY_QCOM_EDP=y -+CONFIG_PHY_QCOM_QMP=y -+# CONFIG_PHY_QCOM_QMP_PCIE_8996 is not set -+CONFIG_PHY_QCOM_SNPS_EUSB2=y -+CONFIG_PHY_QCOM_EUSB2_REPEATER=y -+CONFIG_PHY_QCOM_USB_SNPS_FEMTO_V2=y -+CONFIG_ARM_CCI_PMU=m -+CONFIG_ARM_CCN=m -+CONFIG_ARM_CMN=m -+CONFIG_ARM_SMMU_V3_PMU=m -+CONFIG_ARM_DSU_PMU=m -+CONFIG_QCOM_L2_PMU=y -+CONFIG_QCOM_L3_PMU=y -+CONFIG_ARM_SPE_PMU=m -+CONFIG_DWC_PCIE_PMU=m -+CONFIG_ARM_CORESIGHT_PMU_ARCH_SYSTEM_PMU=m -+CONFIG_USB4=m -+CONFIG_ANDROID_BINDER_IPC=y -+CONFIG_ANDROID_BINDERFS=y -+CONFIG_ANDROID_BINDER_DEVICES="" -+CONFIG_NVMEM_LAYOUT_U_BOOT_ENV=m -+CONFIG_NVMEM_QCOM_QFPROM=y -+CONFIG_NVMEM_QCOM_SEC_QFPROM=m -+CONFIG_NVMEM_RMEM=m -+CONFIG_NVMEM_SPMI_SDAM=m -+CONFIG_TEE=y -+CONFIG_OPTEE=m -+CONFIG_ARM_TSTEE=m -+CONFIG_MUX_GPIO=m -+CONFIG_MUX_MMIO=y -+CONFIG_SLIM_QCOM_CTRL=m -+CONFIG_SLIM_QCOM_NGD_CTRL=m -+CONFIG_INTERCONNECT_QCOM=y -+CONFIG_INTERCONNECT_QCOM_OSM_L3=y -+CONFIG_INTERCONNECT_QCOM_QCS8300=y -+CONFIG_INTERCONNECT_QCOM_SA8775P=y -+CONFIG_INTERCONNECT_QCOM_SC7280=y -+CONFIG_INTERCONNECT_QCOM_SM8550=y -+CONFIG_INTERCONNECT_QCOM_X1E80100=y -+CONFIG_VALIDATE_FS_PARSER=y -+CONFIG_EXT4_FS=y -+CONFIG_EXT4_FS_POSIX_ACL=y -+CONFIG_EXT4_FS_SECURITY=y -+CONFIG_BTRFS_FS=m -+CONFIG_BTRFS_FS_POSIX_ACL=y -+CONFIG_F2FS_FS=m -+CONFIG_F2FS_FS_SECURITY=y -+CONFIG_F2FS_CHECK_FS=y -+CONFIG_F2FS_FS_COMPRESSION=y -+CONFIG_F2FS_UNFAIR_RWSEM=y -+CONFIG_BCACHEFS_FS=m -+CONFIG_BCACHEFS_QUOTA=y -+CONFIG_BCACHEFS_POSIX_ACL=y -+CONFIG_BCACHEFS_LOCK_TIME_STATS=y -+CONFIG_ZONEFS_FS=m -+CONFIG_FS_DAX=y -+CONFIG_FS_ENCRYPTION=y -+CONFIG_FS_ENCRYPTION_INLINE_CRYPT=y -+CONFIG_FS_VERITY=y -+CONFIG_FS_VERITY_BUILTIN_SIGNATURES=y -+CONFIG_FANOTIFY=y -+CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y -+CONFIG_QUOTA_NETLINK_INTERFACE=y -+CONFIG_QFMT_V1=m -+CONFIG_QFMT_V2=m -+CONFIG_AUTOFS_FS=y -+CONFIG_FUSE_FS=y -+CONFIG_CUSE=m -+CONFIG_VIRTIO_FS=y -+CONFIG_OVERLAY_FS=m -+# CONFIG_OVERLAY_FS_REDIRECT_ALWAYS_FOLLOW is not set -+CONFIG_OVERLAY_FS_INDEX=y -+CONFIG_OVERLAY_FS_XINO_AUTO=y -+CONFIG_OVERLAY_FS_METACOPY=y -+CONFIG_NETFS_DEBUG=y -+CONFIG_FSCACHE_STATS=y -+CONFIG_CACHEFILES=m -+CONFIG_CACHEFILES_ONDEMAND=y -+CONFIG_ISO9660_FS=m -+CONFIG_JOLIET=y -+CONFIG_ZISOFS=y -+CONFIG_UDF_FS=m -+CONFIG_MSDOS_FS=m -+CONFIG_VFAT_FS=y -+CONFIG_FAT_DEFAULT_IOCHARSET="ascii" -+CONFIG_FAT_DEFAULT_UTF8=y -+CONFIG_EXFAT_FS=m -+CONFIG_NTFS3_LZX_XPRESS=y -+CONFIG_NTFS3_FS_POSIX_ACL=y -+CONFIG_NTFS_FS=m -+CONFIG_PROC_KCORE=y -+CONFIG_PROC_VMCORE_DEVICE_DUMP=y -+CONFIG_TMPFS_POSIX_ACL=y -+CONFIG_TMPFS_INODE64=y -+CONFIG_TMPFS_QUOTA=y -+CONFIG_HUGETLBFS=y -+CONFIG_EFIVAR_FS=y -+CONFIG_UBIFS_FS=m -+CONFIG_SQUASHFS=m -+CONFIG_SQUASHFS_FILE_DIRECT=y -+CONFIG_SQUASHFS_CHOICE_DECOMP_BY_MOUNT=y -+CONFIG_SQUASHFS_XATTR=y -+CONFIG_SQUASHFS_LZ4=y -+CONFIG_SQUASHFS_LZO=y -+CONFIG_SQUASHFS_XZ=y -+CONFIG_SQUASHFS_ZSTD=y -+CONFIG_PSTORE_RAM=m -+CONFIG_PSTORE_BLK=m -+CONFIG_NFS_FS=m -+CONFIG_NFS_V2=m -+CONFIG_NFS_V3_ACL=y -+CONFIG_NFS_V4=m -+CONFIG_NFS_SWAP=y -+CONFIG_NFS_V4_1=y -+CONFIG_NFS_V4_2=y -+CONFIG_NFS_FSCACHE=y -+# CONFIG_NFS_DISABLE_UDP_SUPPORT is not set -+# CONFIG_NFS_V4_2_READ_PLUS is not set -+CONFIG_NFSD=m -+CONFIG_NFSD_V3_ACL=y -+CONFIG_NFSD_V4=y -+CONFIG_NFSD_BLOCKLAYOUT=y -+CONFIG_NFSD_SCSILAYOUT=y -+CONFIG_NFSD_V4_2_INTER_SSC=y -+CONFIG_NFSD_V4_SECURITY_LABEL=y -+# CONFIG_NFSD_LEGACY_CLIENT_TRACKING is not set -+CONFIG_NFS_LOCALIO=y -+CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_CAMELLIA=y -+CONFIG_RPCSEC_GSS_KRB5_ENCTYPES_AES_SHA2=y -+CONFIG_SUNRPC_DEBUG=y -+CONFIG_CEPH_FS=m -+CONFIG_CEPH_FSCACHE=y -+CONFIG_CEPH_FS_POSIX_ACL=y -+CONFIG_CEPH_FS_SECURITY_LABEL=y -+CONFIG_CIFS=m -+# CONFIG_CIFS_STATS2 is not set -+CONFIG_CIFS_UPCALL=y -+CONFIG_CIFS_XATTR=y -+CONFIG_CIFS_POSIX=y -+CONFIG_CIFS_DFS_UPCALL=y -+CONFIG_CIFS_SWN_UPCALL=y -+CONFIG_CIFS_SMB_DIRECT=y -+CONFIG_CIFS_FSCACHE=y -+CONFIG_CIFS_COMPRESSION=y -+CONFIG_SMB_SERVER=m -+CONFIG_SMB_SERVER_SMBDIRECT=y -+CONFIG_9P_FS=m -+CONFIG_9P_FSCACHE=y -+CONFIG_9P_FS_POSIX_ACL=y -+CONFIG_9P_FS_SECURITY=y -+CONFIG_NLS_CODEPAGE_437=y -+CONFIG_NLS_CODEPAGE_737=m -+CONFIG_NLS_CODEPAGE_775=m -+CONFIG_NLS_CODEPAGE_850=m -+CONFIG_NLS_CODEPAGE_852=m -+CONFIG_NLS_CODEPAGE_855=m -+CONFIG_NLS_CODEPAGE_857=m -+CONFIG_NLS_CODEPAGE_860=m -+CONFIG_NLS_CODEPAGE_861=m -+CONFIG_NLS_CODEPAGE_862=m -+CONFIG_NLS_CODEPAGE_863=m -+CONFIG_NLS_CODEPAGE_864=m -+CONFIG_NLS_CODEPAGE_865=m -+CONFIG_NLS_CODEPAGE_866=m -+CONFIG_NLS_CODEPAGE_869=m -+CONFIG_NLS_CODEPAGE_936=y -+CONFIG_NLS_CODEPAGE_950=m -+CONFIG_NLS_CODEPAGE_932=m -+CONFIG_NLS_CODEPAGE_949=m -+CONFIG_NLS_CODEPAGE_874=m -+CONFIG_NLS_ISO8859_8=m -+CONFIG_NLS_CODEPAGE_1250=m -+CONFIG_NLS_CODEPAGE_1251=m -+CONFIG_NLS_ASCII=y -+CONFIG_NLS_ISO8859_1=y -+CONFIG_NLS_ISO8859_2=m -+CONFIG_NLS_ISO8859_3=m -+CONFIG_NLS_ISO8859_4=m -+CONFIG_NLS_ISO8859_5=m -+CONFIG_NLS_ISO8859_6=m -+CONFIG_NLS_ISO8859_7=m -+CONFIG_NLS_ISO8859_9=m -+CONFIG_NLS_ISO8859_13=m -+CONFIG_NLS_ISO8859_14=m -+CONFIG_NLS_ISO8859_15=m -+CONFIG_NLS_KOI8_R=m -+CONFIG_NLS_KOI8_U=m -+CONFIG_NLS_MAC_ROMAN=m -+CONFIG_NLS_MAC_CELTIC=m -+CONFIG_NLS_MAC_CENTEURO=m -+CONFIG_NLS_MAC_CROATIAN=m -+CONFIG_NLS_MAC_CYRILLIC=m -+CONFIG_NLS_MAC_GAELIC=m -+CONFIG_NLS_MAC_GREEK=m -+CONFIG_NLS_MAC_ICELAND=m -+CONFIG_NLS_MAC_INUIT=m -+CONFIG_NLS_MAC_ROMANIAN=m -+CONFIG_NLS_MAC_TURKISH=m -+CONFIG_DLM=m -+CONFIG_UNICODE=y -+CONFIG_KEYS_REQUEST_CACHE=y -+CONFIG_PERSISTENT_KEYRINGS=y -+CONFIG_BIG_KEYS=y -+CONFIG_TRUSTED_KEYS=m -+CONFIG_ENCRYPTED_KEYS=m -+CONFIG_KEY_DH_OPERATIONS=y -+CONFIG_KEY_NOTIFICATIONS=y -+CONFIG_SECURITY=y -+CONFIG_SECURITY_INFINIBAND=y -+CONFIG_SECURITY_NETWORK_XFRM=y -+CONFIG_LSM_MMAP_MIN_ADDR=65535 -+CONFIG_SECURITY_SELINUX=y -+CONFIG_SECURITY_SELINUX_BOOTPARAM=y -+CONFIG_SECURITY_SMACK=y -+CONFIG_SECURITY_SMACK_BRINGUP=y -+CONFIG_SECURITY_SMACK_NETFILTER=y -+CONFIG_SECURITY_SMACK_APPEND_SIGNALS=y -+CONFIG_SECURITY_TOMOYO=y -+CONFIG_SECURITY_TOMOYO_POLICY_LOADER="/usr/bin/tomoyo-init" -+CONFIG_SECURITY_TOMOYO_ACTIVATION_TRIGGER="/usr/lib/systemd/systemd" -+CONFIG_SECURITY_APPARMOR=y -+CONFIG_SECURITY_LOADPIN=y -+CONFIG_SECURITY_LOADPIN_ENFORCE=y -+CONFIG_SECURITY_YAMA=y -+CONFIG_SECURITY_SAFESETID=y -+CONFIG_SECURITY_LANDLOCK=y -+CONFIG_SECURITY_IPE=y -+CONFIG_INTEGRITY_SIGNATURE=y -+CONFIG_INTEGRITY_ASYMMETRIC_KEYS=y -+CONFIG_DEFAULT_SECURITY_DAC=y -+CONFIG_LSM="landlock,lockdown,yama,integrity,bpf" -+CONFIG_INIT_ON_ALLOC_DEFAULT_ON=y -+CONFIG_FORTIFY_SOURCE=y -+CONFIG_HARDENED_USERCOPY=y -+CONFIG_LIST_HARDENED=y -+CONFIG_CRYPTO_USER=m -+CONFIG_CRYPTO_PCRYPT=m -+CONFIG_CRYPTO_CRYPTD=m -+CONFIG_CRYPTO_TEST=m -+CONFIG_CRYPTO_ECDH=y -+CONFIG_CRYPTO_ECDSA=y -+CONFIG_CRYPTO_ECRDSA=m -+CONFIG_CRYPTO_CURVE25519=m -+CONFIG_CRYPTO_AES_TI=m -+CONFIG_CRYPTO_ARIA=m -+CONFIG_CRYPTO_BLOWFISH=m -+CONFIG_CRYPTO_CAST5=m -+CONFIG_CRYPTO_CAST6=m -+CONFIG_CRYPTO_DES=m -+CONFIG_CRYPTO_SERPENT=m -+CONFIG_CRYPTO_SM4_GENERIC=m -+CONFIG_CRYPTO_TWOFISH=m -+CONFIG_CRYPTO_HCTR2=m -+CONFIG_CRYPTO_LRW=m -+CONFIG_CRYPTO_AEGIS128=m -+CONFIG_CRYPTO_CHACHA20POLY1305=m -+CONFIG_CRYPTO_ESSIV=m -+CONFIG_CRYPTO_MD4=m -+CONFIG_CRYPTO_RMD160=m -+CONFIG_CRYPTO_SM3_GENERIC=m -+CONFIG_CRYPTO_WP512=m -+CONFIG_CRYPTO_XCBC=m -+CONFIG_CRYPTO_XXHASH=y -+CONFIG_CRYPTO_CRC32C=y -+CONFIG_CRYPTO_CRC32=m -+CONFIG_CRYPTO_842=m -+CONFIG_CRYPTO_LZ4=m -+CONFIG_CRYPTO_LZ4HC=m -+CONFIG_CRYPTO_ANSI_CPRNG=m -+CONFIG_CRYPTO_DRBG_HASH=y -+CONFIG_CRYPTO_DRBG_CTR=y -+CONFIG_CRYPTO_USER_API_HASH=m -+CONFIG_CRYPTO_USER_API_SKCIPHER=m -+CONFIG_CRYPTO_USER_API_RNG=m -+CONFIG_CRYPTO_USER_API_AEAD=m -+# CONFIG_CRYPTO_USER_API_ENABLE_OBSOLETE is not set -+CONFIG_CRYPTO_NHPOLY1305_NEON=y -+CONFIG_CRYPTO_GHASH_ARM64_CE=y -+CONFIG_CRYPTO_SHA1_ARM64_CE=y -+CONFIG_CRYPTO_SHA2_ARM64_CE=y -+CONFIG_CRYPTO_SHA512_ARM64_CE=m -+CONFIG_CRYPTO_SHA3_ARM64=m -+CONFIG_CRYPTO_SM3_NEON=y -+CONFIG_CRYPTO_SM3_ARM64_CE=m -+CONFIG_CRYPTO_POLYVAL_ARM64_CE=y -+CONFIG_CRYPTO_AES_ARM64=y -+CONFIG_CRYPTO_AES_ARM64_BS=m -+CONFIG_CRYPTO_SM4_ARM64_CE=y -+CONFIG_CRYPTO_SM4_ARM64_NEON_BLK=y -+CONFIG_CRYPTO_AES_ARM64_CE_CCM=y -+CONFIG_CRYPTO_SM4_ARM64_CE_CCM=y -+CONFIG_CRYPTO_SM4_ARM64_CE_GCM=y -+CONFIG_CRYPTO_DEV_QCE=m -+CONFIG_CRYPTO_DEV_QCOM_RNG=m -+CONFIG_PKCS8_PRIVATE_KEY_PARSER=m -+CONFIG_SIGNED_PE_FILE_VERIFICATION=y -+CONFIG_CRYPTO_KRB5=m -+# CONFIG_RAID6_PQ_BENCHMARK is not set -+CONFIG_CORDIC=m -+CONFIG_INDIRECT_PIO=y -+CONFIG_XZ_DEC_MICROLZMA=y -+CONFIG_DMA_RESTRICTED_POOL=y -+CONFIG_DMA_CMA=y -+CONFIG_CMA_SIZE_MBYTES=32 -+CONFIG_FONTS=y -+CONFIG_FONT_8x8=y -+CONFIG_FONT_8x16=y -+CONFIG_FONT_TER16x32=y -+CONFIG_PRINTK_TIME=y -+CONFIG_STACKTRACE_BUILD_ID=y -+CONFIG_CONSOLE_LOGLEVEL_DEFAULT=4 -+CONFIG_CONSOLE_LOGLEVEL_QUIET=1 -+CONFIG_BOOT_PRINTK_DELAY=y -+CONFIG_DYNAMIC_DEBUG=y -+CONFIG_DEBUG_KERNEL=y -+# CONFIG_DEBUG_MISC is not set -+CONFIG_DEBUG_INFO_DWARF5=y -+CONFIG_GDB_SCRIPTS=y -+CONFIG_STRIP_ASM_SYMS=y -+CONFIG_MAGIC_SYSRQ=y -+CONFIG_MAGIC_SYSRQ_DEFAULT_ENABLE=0x0 -+CONFIG_PAGE_POISONING=y -+CONFIG_DEBUG_RODATA_TEST=y -+CONFIG_DEBUG_WX=y -+CONFIG_SHRINKER_DEBUG=y -+CONFIG_SCHED_STACK_END_CHECK=y -+CONFIG_KFENCE=y -+CONFIG_KFENCE_DEFERRABLE=y -+CONFIG_DEBUG_SHIRQ=y -+CONFIG_SOFTLOCKUP_DETECTOR_INTR_STORM=y -+CONFIG_HARDLOCKUP_DETECTOR=y -+CONFIG_SCHEDSTATS=y -+CONFIG_RCU_CPU_STALL_TIMEOUT=60 -+# CONFIG_RCU_TRACE is not set -+CONFIG_BOOTTIME_TRACING=y -+CONFIG_FUNCTION_GRAPH_RETVAL=y -+CONFIG_FUNCTION_GRAPH_RETADDR=y -+CONFIG_FPROBE=y -+CONFIG_FUNCTION_PROFILER=y -+CONFIG_STACK_TRACER=y -+CONFIG_SCHED_TRACER=y -+CONFIG_HWLAT_TRACER=y -+CONFIG_TIMERLAT_TRACER=y -+CONFIG_FTRACE_SYSCALLS=y -+CONFIG_BLK_DEV_IO_TRACE=y -+CONFIG_USER_EVENTS=y -+CONFIG_HIST_TRIGGERS=y -+# CONFIG_STRICT_DEVMEM is not set -+CONFIG_CORESIGHT=m -+CONFIG_CORESIGHT_LINK_AND_SINK_TMC=m -+CONFIG_CORESIGHT_CATU=m -+CONFIG_CORESIGHT_SINK_TPIU=m -+CONFIG_CORESIGHT_SINK_ETBV10=m -+CONFIG_CORESIGHT_STM=m -+CONFIG_CORESIGHT_CPU_DEBUG=m -+CONFIG_CORESIGHT_CTI=m -+CONFIG_FUNCTION_ERROR_INJECTION=y -+CONFIG_ASYNC_RAID6_TEST=m -+CONFIG_MEMTEST=y --- -2.50.1 - diff --git a/debian/patches/linux/0031-spi-spi-qcom-qspi-Add-support-for-polling.patch b/debian/patches/linux/0031-spi-spi-qcom-qspi-Add-support-for-polling.patch deleted file mode 100644 index 3c7b62a..0000000 --- a/debian/patches/linux/0031-spi-spi-qcom-qspi-Add-support-for-polling.patch +++ /dev/null @@ -1,202 +0,0 @@ -From 9ce54b736b781bb4c09196701acdcf68a418a5ad Mon Sep 17 00:00:00 2001 -From: Xilin Wu -Date: Wed, 16 Jul 2025 19:22:42 +0800 -Subject: [PATCH 31/49] spi: spi-qcom-qspi: Add support for polling - -Signed-off-by: Xilin Wu ---- - drivers/spi/spi-qcom-qspi.c | 142 +++++++++++++++++++++++++++++++++++- - 1 file changed, 138 insertions(+), 4 deletions(-) - -diff --git a/src/drivers/spi/spi-qcom-qspi.c b/src/drivers/spi/spi-qcom-qspi.c -index 3aeddada58e1..217b98bbc815 100644 ---- a/src/drivers/spi/spi-qcom-qspi.c -+++ b/src/drivers/spi/spi-qcom-qspi.c -@@ -2,6 +2,7 @@ - // Copyright (c) 2017-2018, The Linux foundation. All rights reserved. - - #include -+#include - #include - #include - #include -@@ -177,6 +178,7 @@ struct qcom_qspi { - unsigned long last_speed; - /* Lock to protect data accessed by IRQs */ - spinlock_t lock; -+ bool is_polling; - }; - - static u32 qspi_buswidth_to_iomode(struct qcom_qspi *ctrl, -@@ -236,11 +238,15 @@ static void qcom_qspi_pio_xfer(struct qcom_qspi *ctrl) - /* Ack any previous interrupts that might be hanging around */ - writel(QSPI_ALL_IRQS, ctrl->base + MSTR_INT_STATUS); - -+ if (ctrl->is_polling) { -+ ints = 0; -+ } else { -+ if (ctrl->xfer.dir == QSPI_WRITE) -+ ints = QSPI_ERR_IRQS | WR_FIFO_EMPTY; -+ else -+ ints = QSPI_ERR_IRQS | RESP_FIFO_RDY; -+ } - /* Setup new interrupts */ -- if (ctrl->xfer.dir == QSPI_WRITE) -- ints = QSPI_ERR_IRQS | WR_FIFO_EMPTY; -- else -- ints = QSPI_ERR_IRQS | RESP_FIFO_RDY; - writel(ints, ctrl->base + MSTR_INT_EN); - - /* Kick off the transfer */ -@@ -411,6 +417,112 @@ static bool qcom_qspi_can_dma(struct spi_controller *ctlr, - return xfer->len > QSPI_MAX_BYTES_FIFO; - } - -+static int qcom_qspi_pio_read_polling(struct qcom_qspi *ctrl) -+{ -+ while (ctrl->xfer.rem_bytes > 0) { -+ u32 rd_fifo_status; -+ unsigned int wr_cnts; -+ -+ int timeout = 1000000; -+ do { -+ rd_fifo_status = readl(ctrl->base + RD_FIFO_STATUS); -+ if (rd_fifo_status & FIFO_RDY) -+ break; -+ udelay(1); -+ } while (--timeout); -+ -+ if (timeout == 0) { -+ dev_err(ctrl->dev, "Polling read timed out!\n"); -+ return -ETIMEDOUT; -+ } -+ -+ wr_cnts = (rd_fifo_status & WR_CNTS_MSK) >> WR_CNTS_SHFT; -+ wr_cnts = min(wr_cnts, ctrl->xfer.rem_bytes); -+ -+ if (wr_cnts == 0) { -+ if (ctrl->xfer.rem_bytes > 0) { -+ udelay(1); -+ continue; -+ } -+ break; -+ } -+ -+ unsigned int words_to_read = wr_cnts / QSPI_BYTES_PER_WORD; -+ unsigned int bytes_to_read = wr_cnts % QSPI_BYTES_PER_WORD; -+ u32 *word_buf; -+ u8 *byte_buf; -+ int i; -+ -+ if (words_to_read) { -+ word_buf = ctrl->xfer.rx_buf; -+ ctrl->xfer.rem_bytes -= words_to_read * QSPI_BYTES_PER_WORD; -+ ioread32_rep(ctrl->base + RD_FIFO, word_buf, words_to_read); -+ ctrl->xfer.rx_buf = word_buf + words_to_read; -+ } -+ -+ if (bytes_to_read) { -+ u32 rd_fifo; -+ byte_buf = ctrl->xfer.rx_buf; -+ rd_fifo = readl(ctrl->base + RD_FIFO); -+ ctrl->xfer.rem_bytes -= bytes_to_read; -+ for (i = 0; i < bytes_to_read; i++) -+ *byte_buf++ = rd_fifo >> (i * BITS_PER_BYTE); -+ ctrl->xfer.rx_buf = byte_buf; -+ } -+ } -+ return 0; -+} -+ -+static int qcom_qspi_pio_write_polling(struct qcom_qspi *ctrl) -+{ -+ while (ctrl->xfer.rem_bytes > 0) { -+ const void *xfer_buf = ctrl->xfer.tx_buf; -+ unsigned int wr_fifo_bytes; -+ -+ wr_fifo_bytes = readl(ctrl->base + PIO_XFER_STATUS); -+ wr_fifo_bytes >>= WR_FIFO_BYTES_SHFT; -+ -+ if (wr_fifo_bytes == 0) { -+ udelay(1); -+ continue; -+ } -+ -+ const int *word_buf; -+ const char *byte_buf; -+ unsigned int wr_size; -+ unsigned int rem_words; -+ -+ if (ctrl->xfer.rem_bytes < QSPI_BYTES_PER_WORD) { -+ wr_size = min(wr_fifo_bytes, ctrl->xfer.rem_bytes); -+ ctrl->xfer.rem_bytes -= wr_size; -+ byte_buf = xfer_buf; -+ while (wr_size--) -+ writel(*byte_buf++, ctrl->base + PIO_DATAOUT_1B); -+ ctrl->xfer.tx_buf = byte_buf; -+ } else { -+ rem_words = ctrl->xfer.rem_bytes / QSPI_BYTES_PER_WORD; -+ unsigned int wr_fifo_words = wr_fifo_bytes / QSPI_BYTES_PER_WORD; -+ wr_size = min(rem_words, wr_fifo_words); -+ if (wr_size > 0) { -+ ctrl->xfer.rem_bytes -= wr_size * QSPI_BYTES_PER_WORD; -+ word_buf = xfer_buf; -+ iowrite32_rep(ctrl->base + PIO_DATAOUT_4B, word_buf, wr_size); -+ ctrl->xfer.tx_buf = word_buf + wr_size; -+ } -+ } -+ } -+ -+ int timeout = 1000000; -+ while (--timeout) { -+ if (readl(ctrl->base + MSTR_INT_STATUS) & TRANSACTION_DONE) -+ return 0; -+ udelay(1); -+ } -+ -+ dev_err(ctrl->dev, "Polling write transaction done timed out!\n"); -+ return -ETIMEDOUT; -+} -+ - static int qcom_qspi_transfer_one(struct spi_controller *host, - struct spi_device *slv, - struct spi_transfer *xfer) -@@ -471,6 +583,24 @@ static int qcom_qspi_transfer_one(struct spi_controller *host, - } - qcom_qspi_pio_xfer(ctrl); - -+ if (ctrl->is_polling) { -+ if (ctrl->xfer.dir == QSPI_READ) { -+ ret = qcom_qspi_pio_read_polling(ctrl); -+ } else { -+ ret = qcom_qspi_pio_write_polling(ctrl); -+ } -+ -+ ctrl->xfer.rem_bytes = 0; -+ spin_unlock_irqrestore(&ctrl->lock, flags); -+ -+ if (ret) { -+ spi_finalize_current_transfer(host); -+ return ret; -+ } -+ -+ return 0; -+ } -+ - exit: - spin_unlock_irqrestore(&ctrl->lock, flags); - -@@ -773,6 +903,10 @@ static int qcom_qspi_probe(struct platform_device *pdev) - host->handle_err = qcom_qspi_handle_err; - if (of_property_present(pdev->dev.of_node, "iommus")) - host->can_dma = qcom_qspi_can_dma; -+ -+ if (of_property_present(pdev->dev.of_node, "use-polling")) -+ ctrl->is_polling = true; -+ - host->auto_runtime_pm = true; - host->mem_ops = &qcom_qspi_mem_ops; - --- -2.50.1 - diff --git a/debian/patches/linux/0032-drm-panel-Add-support-for-Orise-Tech-OTA7290B-DSI-Pa.patch b/debian/patches/linux/0032-drm-panel-Add-support-for-Orise-Tech-OTA7290B-DSI-Pa.patch deleted file mode 100644 index 8097ca9..0000000 --- a/debian/patches/linux/0032-drm-panel-Add-support-for-Orise-Tech-OTA7290B-DSI-Pa.patch +++ /dev/null @@ -1,344 +0,0 @@ -From 786375d51a2923c436e8abe07c6da26e4889595a Mon Sep 17 00:00:00 2001 -From: Stephen Chen -Date: Sun, 1 Jun 2025 14:14:15 +0800 -Subject: [PATCH 32/49] drm/panel: Add support for Orise Tech OTA7290B DSI - Panel Driver - -Signed-off-by: Stephen Chen ---- - drivers/gpu/drm/panel/Kconfig | 9 + - drivers/gpu/drm/panel/Makefile | 1 + - .../gpu/drm/panel/panel-orisetech-ota7290b.c | 289 ++++++++++++++++++ - 3 files changed, 299 insertions(+) - create mode 100644 drivers/gpu/drm/panel/panel-orisetech-ota7290b.c - -diff --git a/src/drivers/gpu/drm/panel/Kconfig b/src/drivers/gpu/drm/panel/Kconfig -index cfebb08e8a62..d60bc93a2fda 100644 ---- a/src/drivers/gpu/drm/panel/Kconfig -+++ b/src/drivers/gpu/drm/panel/Kconfig -@@ -560,6 +560,15 @@ config DRM_PANEL_ORISETECH_OTA5601A - Say Y here if you want to enable support for the panels built - around the Orise Technology OTA9601A display controller. - -+config DRM_PANEL_ORISETECH_OTA7290B -+ tristate "Orise Technology ota7290b dsi panel" -+ depends on OF -+ depends on DRM_MIPI_DSI -+ depends on BACKLIGHT_CLASS_DEVICE -+ help -+ Say Y here if you want to enable support for Orise Technology -+ ota7290b dsi panel. -+ - config DRM_PANEL_ORISETECH_OTM8009A - tristate "Orise Technology otm8009a 480x800 dsi 2dl panel" - depends on OF -diff --git a/src/drivers/gpu/drm/panel/Makefile b/src/drivers/gpu/drm/panel/Makefile -index 714cbac830e3..c614941a7d06 100644 ---- a/src/drivers/gpu/drm/panel/Makefile -+++ b/src/drivers/gpu/drm/panel/Makefile -@@ -56,6 +56,7 @@ obj-$(CONFIG_DRM_PANEL_NOVATEK_NT39016) += panel-novatek-nt39016.o - obj-$(CONFIG_DRM_PANEL_MANTIX_MLAF057WE51) += panel-mantix-mlaf057we51.o - obj-$(CONFIG_DRM_PANEL_OLIMEX_LCD_OLINUXINO) += panel-olimex-lcd-olinuxino.o - obj-$(CONFIG_DRM_PANEL_ORISETECH_OTA5601A) += panel-orisetech-ota5601a.o -+obj-$(CONFIG_DRM_PANEL_ORISETECH_OTA7290B) += panel-orisetech-ota7290b.o - obj-$(CONFIG_DRM_PANEL_ORISETECH_OTM8009A) += panel-orisetech-otm8009a.o - obj-$(CONFIG_DRM_PANEL_OSD_OSD101T2587_53TS) += panel-osd-osd101t2587-53ts.o - obj-$(CONFIG_DRM_PANEL_PANASONIC_VVX10F034N00) += panel-panasonic-vvx10f034n00.o -diff --git a/src/drivers/gpu/drm/panel/panel-orisetech-ota7290b.c b/src/drivers/gpu/drm/panel/panel-orisetech-ota7290b.c -new file mode 100644 -index 000000000000..3f4848cefd47 ---- /dev/null -+++ b/src/drivers/gpu/drm/panel/panel-orisetech-ota7290b.c -@@ -0,0 +1,289 @@ -+// SPDX-License-Identifier: GPL-2.0-only -+// Copyright (c) 2025 Radxa Computer (Shenzhen) Co., Ltd. -+ -+#include -+#include -+#include -+#include -+#include -+ -+#include -+#include -+#include -+ -+#include