diff --git a/doc/ref/dev_guide.md b/doc/ref/dev_guide.md index b18bf6d1e..034aac569 100644 --- a/doc/ref/dev_guide.md +++ b/doc/ref/dev_guide.md @@ -43,8 +43,6 @@ cmake -B build/sw -S sw cmake --build build/sw -j $(nproc) ``` -Outputs with the suffix "_sram" exist only for UVM-based tests, as they presently lack a DRAM backdoor-load mechanism. - The boot-ROM output with the "_scrambled" suffix is the only binary run through the ROM image scrambling script. Attempting to run any unscrambled binary from the scrambled ROM will be blocked by the in-hardware ROM checker. diff --git a/hw/top_chip/dv/common/sim_dram_axi/sim_dram_axi.core b/hw/top_chip/dv/common/sim_dram_axi/sim_dram_axi.core new file mode 100644 index 000000000..c6b95b7f6 --- /dev/null +++ b/hw/top_chip/dv/common/sim_dram_axi/sim_dram_axi.core @@ -0,0 +1,20 @@ +CAPI=2: +# Copyright lowRISC contributors (COSMIC project). +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +name: "lowrisc:mocha_dv:sim_dram_axi:0.1" +description: "DRAM simulation wrapper providing an AXI-accessible mock memory for chip-level simulation." +filesets: + files_dv: + depend: + - lowrisc:prim:ram_1p + - lowrisc:mocha:top_chip_system + files: + - sim_dram_wrapper.sv + file_type: systemVerilogSource + +targets: + default: + filesets: + - files_dv diff --git a/hw/top_chip/dv/verilator/dram_wrapper_sim.sv b/hw/top_chip/dv/common/sim_dram_axi/sim_dram_wrapper.sv similarity index 99% rename from hw/top_chip/dv/verilator/dram_wrapper_sim.sv rename to hw/top_chip/dv/common/sim_dram_axi/sim_dram_wrapper.sv index bb0b54535..aded1ab6a 100644 --- a/hw/top_chip/dv/verilator/dram_wrapper_sim.sv +++ b/hw/top_chip/dv/common/sim_dram_axi/sim_dram_wrapper.sv @@ -2,7 +2,7 @@ // Licensed under the Apache License, Version 2.0, see LICENSE for details. // SPDX-License-Identifier: Apache-2.0 -module dram_wrapper_sim ( +module sim_dram_wrapper ( // Clock and reset input logic clk_i, input logic rst_ni, diff --git a/hw/top_chip/dv/sim_sram_axi/README.md b/hw/top_chip/dv/common/sim_sram_axi/README.md similarity index 100% rename from hw/top_chip/dv/sim_sram_axi/README.md rename to hw/top_chip/dv/common/sim_sram_axi/README.md diff --git a/hw/top_chip/dv/sim_sram_axi/doc/sim_sram_axi.svg b/hw/top_chip/dv/common/sim_sram_axi/doc/sim_sram_axi.svg similarity index 99% rename from hw/top_chip/dv/sim_sram_axi/doc/sim_sram_axi.svg rename to hw/top_chip/dv/common/sim_sram_axi/doc/sim_sram_axi.svg index de1e44228..0c5c41a49 100644 --- a/hw/top_chip/dv/sim_sram_axi/doc/sim_sram_axi.svg +++ b/hw/top_chip/dv/common/sim_sram_axi/doc/sim_sram_axi.svg @@ -1 +1,3 @@ + + \ No newline at end of file diff --git a/hw/top_chip/dv/sim_sram_axi/sim_sram_axi.core b/hw/top_chip/dv/common/sim_sram_axi/sim_sram_axi.core similarity index 100% rename from hw/top_chip/dv/sim_sram_axi/sim_sram_axi.core rename to hw/top_chip/dv/common/sim_sram_axi/sim_sram_axi.core diff --git a/hw/top_chip/dv/sim_sram_axi/sim_sram_axi_if.sv b/hw/top_chip/dv/common/sim_sram_axi/sim_sram_axi_if.sv similarity index 100% rename from hw/top_chip/dv/sim_sram_axi/sim_sram_axi_if.sv rename to hw/top_chip/dv/common/sim_sram_axi/sim_sram_axi_if.sv diff --git a/hw/top_chip/dv/sim_sram_axi/sim_sram_axi_sink.sv b/hw/top_chip/dv/common/sim_sram_axi/sim_sram_axi_sink.sv similarity index 100% rename from hw/top_chip/dv/sim_sram_axi/sim_sram_axi_sink.sv rename to hw/top_chip/dv/common/sim_sram_axi/sim_sram_axi_sink.sv diff --git a/hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv b/hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv index 74c1bda3b..44580e0d7 100644 --- a/hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv +++ b/hw/top_chip/dv/env/seq_lib/top_chip_dv_base_vseq.sv @@ -29,20 +29,20 @@ class top_chip_dv_base_vseq extends uvm_sequence; // In the extended test vseq, add this function call to the start of body(). extern function void sw_symbol_backdoor_access(input string symbol, inout bit [7:0] data[], - input chip_mem_e mem = ChipMemSRAM, + input chip_mem_e mem = ChipMemDRAM, input bit does_not_exist_ok = 0, input bit is_write = 0); // Backdoor-read a const symbol in SW to make decisions based on SW constants. // Wrapper function for reads via sw_symbol_backdoor_access. extern function void sw_symbol_backdoor_read(input string symbol, inout bit [7:0] data[], - input chip_mem_e mem = ChipMemSRAM, + input chip_mem_e mem = ChipMemDRAM, input bit does_not_exist_ok = 0); // Backdoor-override a const symbol in SW to modify the behavior of the test. // Wrapper function for writes via sw_symbol_backdoor_access. extern function void sw_symbol_backdoor_overwrite(input string symbol, input bit [7:0] data[], - input chip_mem_e mem = ChipMemSRAM, + input chip_mem_e mem = ChipMemDRAM, input bit does_not_exist_ok = 0); // General-use function to backdoor write a byte of data to any selected memory type extern function void mem_bkdr_write8(input chip_mem_e mem, @@ -118,7 +118,7 @@ endtask : wait_for_sw_test_done function void top_chip_dv_base_vseq::sw_symbol_backdoor_access( input string symbol, inout bit [7:0] data[], - input chip_mem_e mem = ChipMemSRAM, + input chip_mem_e mem = ChipMemDRAM, input bit does_not_exist_ok = 0, input bit is_write = 0); @@ -179,7 +179,7 @@ endfunction : sw_symbol_backdoor_access function void top_chip_dv_base_vseq::sw_symbol_backdoor_read(input string symbol, inout bit [7:0] data[], - input chip_mem_e mem = ChipMemSRAM, + input chip_mem_e mem = ChipMemDRAM, input bit does_not_exist_ok = 0); sw_symbol_backdoor_access(symbol, data, mem, does_not_exist_ok, 0); @@ -188,7 +188,7 @@ endfunction : sw_symbol_backdoor_read function void top_chip_dv_base_vseq::sw_symbol_backdoor_overwrite(input string symbol, input bit [7:0] data[], - input chip_mem_e mem = ChipMemSRAM, + input chip_mem_e mem = ChipMemDRAM, input bit does_not_exist_ok = 0); sw_symbol_backdoor_access(symbol, data, mem, does_not_exist_ok, 1); @@ -198,7 +198,7 @@ function void top_chip_dv_base_vseq::mem_bkdr_write8(input chip_mem_e mem, input bit [bus_params_pkg::BUS_AW-1:0] addr, input byte data); byte prev_data; - if (mem == ChipMemSRAM) begin + if (mem inside {ChipMemSRAM, ChipMemDRAM}) begin prev_data = p_sequencer.mem_bkdr_util_h[mem].read8(addr); p_sequencer.mem_bkdr_util_h[mem].write8(addr, data); end else begin @@ -210,7 +210,7 @@ endfunction : mem_bkdr_write8 function void top_chip_dv_base_vseq::mem_bkdr_read8(input chip_mem_e mem, input bit [bus_params_pkg::BUS_AW-1:0] addr, output byte data); - if (mem == ChipMemSRAM) begin + if (mem inside {ChipMemSRAM, ChipMemDRAM}) begin data = p_sequencer.mem_bkdr_util_h[mem].read8(addr); end else begin `dv_fatal($sformatf("Backdoor %0s access not yet supported", mem.name())) diff --git a/hw/top_chip/dv/env/top_chip_dv_env_pkg.sv b/hw/top_chip/dv/env/top_chip_dv_env_pkg.sv index e65aaab3d..86af23e20 100644 --- a/hw/top_chip/dv/env/top_chip_dv_env_pkg.sv +++ b/hw/top_chip/dv/env/top_chip_dv_env_pkg.sv @@ -16,8 +16,9 @@ package top_chip_dv_env_pkg; `include "dv_macros.svh" typedef enum { + ChipMemROM, ChipMemSRAM, - ChipMemROM + ChipMemDRAM } chip_mem_e; typedef chip_mem_e chip_mem_list_t[$]; diff --git a/hw/top_chip/dv/tb/chip_hier_macros.svh b/hw/top_chip/dv/tb/chip_hier_macros.svh index 27da0c95a..ed351d76e 100644 --- a/hw/top_chip/dv/tb/chip_hier_macros.svh +++ b/hw/top_chip/dv/tb/chip_hier_macros.svh @@ -8,6 +8,7 @@ `define SRAM_MEM_HIER `SYSTEM_HIER.u_axi_sram.u_ram.mem `define TAG_MEM_HIER `SYSTEM_HIER.u_axi_sram.u_tag_ram.mem `define ROM_MEM_HIER `SYSTEM_HIER.u_rom_ctrl.gen_rom_scramble_enabled.u_rom.u_rom.u_prim_rom.mem +`define DRAM_MEM_HIER tb.u_dram_wrapper.u_ext_mem.mem // Testbench related `define SIM_SRAM_IF u_sim_sram.u_sim_sram_if diff --git a/hw/top_chip/dv/tb/tb.sv b/hw/top_chip/dv/tb/tb.sv index f4b10a24f..beafa8473 100644 --- a/hw/top_chip/dv/tb/tb.sv +++ b/hw/top_chip/dv/tb/tb.sv @@ -60,7 +60,7 @@ module tb; top_pkg::axi_dram_req_t dram_req; top_pkg::axi_dram_resp_t dram_resp; - dram_wrapper_sim u_dram_wrapper ( + sim_dram_wrapper u_dram_wrapper ( // Clock and reset. .clk_i (dut.clkmgr_clocks.clk_main_infra), .rst_ni (dut.rstmgr_resets.rst_main_n[rstmgr_pkg::DomainMainSel]), @@ -210,21 +210,37 @@ module tb; .system_base_addr (top_pkg::SRAMBase ) ); - // Zero-initialising the SRAM ensures valid BSS. + // Zero-initialise SRAM to prevent X-propagation through its AXI path. m_mem_bkdr_util[ChipMemSRAM].clear_mem(); `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[ChipMemSRAM], `SRAM_MEM_HIER) m_mem_bkdr_util[ChipMemROM] = new( .name ("mem_bkdr_util[ChipMemROM]" ), - .path (`DV_STRINGIFY(`ROM_MEM_HIER) ), - .depth ($size(`ROM_MEM_HIER) ), - .n_bits ($bits(`ROM_MEM_HIER) ), + .path (`DV_STRINGIFY(`ROM_MEM_HIER) ), + .depth ($size(`ROM_MEM_HIER) ), + .n_bits ($bits(`ROM_MEM_HIER) ), .err_detection_scheme (mem_bkdr_util_pkg::ErrDetectionNone), - .system_base_addr (top_pkg::RomCtrlMemBase ) + .system_base_addr (top_pkg::RomCtrlMemBase ) ); `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[ChipMemROM], `ROM_MEM_HIER) + // Zero-init DRAM with a direct SV loop (not clear_mem) before loading the vmem: prim_ram_1p + // starts as X, and reads outside the binary range propagate into tag-controller FIFOs (DataKnown_A). + for (int unsigned dram_init_i = 0; dram_init_i < $size(`DRAM_MEM_HIER); dram_init_i++) begin + `DRAM_MEM_HIER[dram_init_i] = '0; + end + + m_mem_bkdr_util[ChipMemDRAM] = new( + .name ("mem_bkdr_util[ChipMemDRAM]" ), + .path (`DV_STRINGIFY(`DRAM_MEM_HIER) ), + .depth ($size(`DRAM_MEM_HIER) ), + .n_bits (longint'($size(`DRAM_MEM_HIER))*$bits(`DRAM_MEM_HIER[0])), + .err_detection_scheme (mem_bkdr_util_pkg::ErrDetectionNone), + .system_base_addr (top_pkg::DRAMBase ) + ); + + `MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[ChipMemDRAM], `DRAM_MEM_HIER) // TODO MVy, see if required // Zero-initialise the SRAM Capability tags, otherwise TL-UL FIFO assertions will fire; diff --git a/hw/top_chip/dv/top_chip_sim.core b/hw/top_chip/dv/top_chip_sim.core index 3f116816d..2d9c174c8 100644 --- a/hw/top_chip/dv/top_chip_sim.core +++ b/hw/top_chip/dv/top_chip_sim.core @@ -13,6 +13,7 @@ filesets: files_dv: depend: - lowrisc:mocha_dv:sim_sram_axi:0.1 + - lowrisc:mocha_dv:sim_dram_axi:0.1 - lowrisc:dv:sw_test_status - lowrisc:dv:sw_logger_if - lowrisc:mocha_dv:top_chip_dv_test @@ -29,7 +30,6 @@ filesets: files: - tb/tb.sv - tb/chip_hier_macros.svh: {is_include_file: true} - - verilator/dram_wrapper_sim.sv file_type: systemVerilogSource diff --git a/hw/top_chip/dv/top_chip_sim_cfg.hjson b/hw/top_chip/dv/top_chip_sim_cfg.hjson index 32a639fa2..ae3e44855 100644 --- a/hw/top_chip/dv/top_chip_sim_cfg.hjson +++ b/hw/top_chip/dv/top_chip_sim_cfg.hjson @@ -47,288 +47,288 @@ { name: uart_smoke uvm_test_seq: top_chip_dv_uart_base_vseq - sw_images: ["uart_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/uart_smoketest_vanilla_sram.vmem", + sw_images: ["uart_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/uart_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: uart_smoke_cheri uvm_test_seq: top_chip_dv_uart_base_vseq - sw_images: ["uart_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/uart_smoketest_cheri_sram.vmem", + sw_images: ["uart_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/uart_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_plic_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["plic_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/plic_smoketest_vanilla_sram.vmem", + sw_images: ["plic_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/plic_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_plic_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["plic_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/plic_smoketest_cheri_sram.vmem", + sw_images: ["plic_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/plic_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_timer_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["timer_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/timer_smoketest_vanilla_sram.vmem", + sw_images: ["timer_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_timer_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["timer_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/timer_smoketest_cheri_sram.vmem", + sw_images: ["timer_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_timer_irq uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["timer_interrupt_test_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/timer_interrupt_test_vanilla_sram.vmem", + sw_images: ["timer_interrupt_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_interrupt_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_timer_irq_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["timer_interrupt_test_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/timer_interrupt_test_cheri_sram.vmem", + sw_images: ["timer_interrupt_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/timer_interrupt_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: test_framework_exception_test uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["test_framework_exception_test_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/test_framework_exception_test_vanilla_sram.vmem", + sw_images: ["test_framework_exception_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_exception_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: test_framework_exception_test_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["test_framework_exception_test_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/test_framework_exception_test_cheri_sram.vmem", + sw_images: ["test_framework_exception_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/test_framework_exception_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: spi_device_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["spi_device_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/spi_device_smoketest_vanilla_sram.vmem", + sw_images: ["spi_device_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_device_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: spi_device_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["spi_device_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/spi_device_smoketest_cheri_sram.vmem", + sw_images: ["spi_device_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_device_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: spi_host_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["spi_host_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/spi_host_smoketest_vanilla_sram.vmem", + sw_images: ["spi_host_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_host_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: spi_host_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["spi_host_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/spi_host_smoketest_cheri_sram.vmem", + sw_images: ["spi_host_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/spi_host_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: i2c_host_tx_rx uvm_test_seq: top_chip_dv_i2c_host_tx_rx_vseq - sw_images: ["i2c_host_tx_rx_test_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/i2c_host_tx_rx_test_vanilla_sram.vmem", + sw_images: ["i2c_host_tx_rx_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/i2c_host_tx_rx_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: i2c_host_tx_rx_cheri uvm_test_seq: top_chip_dv_i2c_host_tx_rx_vseq - sw_images: ["i2c_host_tx_rx_test_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/i2c_host_tx_rx_test_cheri_sram.vmem", + sw_images: ["i2c_host_tx_rx_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/i2c_host_tx_rx_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: i2c_device_tx_rx uvm_test_seq: top_chip_dv_i2c_device_tx_rx_vseq - sw_images: ["i2c_device_tx_rx_test_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/i2c_device_tx_rx_test_vanilla_sram.vmem", + sw_images: ["i2c_device_tx_rx_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/i2c_device_tx_rx_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: gpio_smoke uvm_test_seq: top_chip_dv_gpio_smoke_vseq - sw_images: ["gpio_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/gpio_smoketest_vanilla_sram.vmem", + sw_images: ["gpio_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/gpio_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: gpio_smoke_cheri uvm_test_seq: top_chip_dv_gpio_smoke_vseq - sw_images: ["gpio_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/gpio_smoketest_cheri_sram.vmem", + sw_images: ["gpio_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/gpio_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rom_ctrl_integrity_check uvm_test_seq: top_chip_dv_rom_ctrl_integrity_check_vseq - sw_images: ["rom_ctrl_integrity_check_test_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/rom_ctrl_integrity_check_test_vanilla_sram.vmem", + sw_images: ["rom_ctrl_integrity_check_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/rom_ctrl_integrity_check_test_vanilla.vmem", "+ChipMemROM_image_file={proj_root}/sw/device/tests/rom_ctrl/mem_init_file.vmem"] } { name: rom_ctrl_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["rom_ctrl_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/rom_ctrl_smoketest_vanilla_sram.vmem", + sw_images: ["rom_ctrl_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/rom_ctrl_smoketest_vanilla.vmem", "+ChipMemROM_image_file={proj_root}/sw/device/tests/rom_ctrl/mem_init_file.vmem"] } { name: rom_ctrl_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["rom_ctrl_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/rom_ctrl_smoketest_cheri_sram.vmem", + sw_images: ["rom_ctrl_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/rom_ctrl_smoketest_cheri.vmem", "+ChipMemROM_image_file={proj_root}/sw/device/tests/rom_ctrl/mem_init_file.vmem"] } { name: rstmgr_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["rstmgr_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/rstmgr_smoketest_vanilla_sram.vmem", + sw_images: ["rstmgr_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/rstmgr_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rstmgr_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["rstmgr_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/rstmgr_smoketest_cheri_sram.vmem", + sw_images: ["rstmgr_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/rstmgr_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: clkmgr_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["clkmgr_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/clkmgr_smoketest_vanilla_sram.vmem", + sw_images: ["clkmgr_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/clkmgr_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: clkmgr_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["clkmgr_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/clkmgr_smoketest_cheri_sram.vmem", + sw_images: ["clkmgr_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/clkmgr_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: pwrmgr_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["pwrmgr_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/pwrmgr_smoketest_vanilla_sram.vmem", + sw_images: ["pwrmgr_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: pwrmgr_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["pwrmgr_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/pwrmgr_smoketest_cheri_sram.vmem", + sw_images: ["pwrmgr_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/pwrmgr_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_dm_ndm_reset_req uvm_test_seq: "top_chip_dv_rv_dm_ndm_reset_req_vseq" - sw_images: ["rv_dm_ndm_reset_req_test_vanilla_sram:5" "bootrom:5"] + sw_images: ["rv_dm_ndm_reset_req_test_vanilla:5" "bootrom:5"] run_opts: ["+en_scb_tl_err_chk=0", "+use_jtag_dmi=1", - "+ChipMemSRAM_image_file={run_dir}/rv_dm_ndm_reset_req_test_vanilla_sram.vmem", + "+ChipMemDRAM_image_file={run_dir}/rv_dm_ndm_reset_req_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_dm_ndm_reset_req_when_cpu_halted uvm_test_seq: "top_chip_dv_rv_dm_ndm_reset_req_when_cpu_halted_vseq" - sw_images: ["rv_dm_ndm_reset_req_when_cpu_halted_test_vanilla_sram:5" "bootrom:5"] + sw_images: ["rv_dm_ndm_reset_req_when_cpu_halted_test_vanilla:5" "bootrom:5"] run_opts: ["+use_jtag_dmi=1", - "+ChipMemSRAM_image_file={run_dir}/rv_dm_ndm_reset_req_when_cpu_halted_test_vanilla_sram.vmem", + "+ChipMemDRAM_image_file={run_dir}/rv_dm_ndm_reset_req_when_cpu_halted_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_dm_access_after_wakeup uvm_test_seq: top_chip_dv_rv_dm_access_after_wakeup_vseq - sw_images: ["rv_dm_access_after_wakeup_test_vanilla_sram:5" "bootrom:5"] + sw_images: ["rv_dm_access_after_wakeup_test_vanilla:5" "bootrom:5"] run_opts: ["+use_jtag_dmi=1", - "+ChipMemSRAM_image_file={run_dir}/rv_dm_access_after_wakeup_test_vanilla_sram.vmem", + "+ChipMemDRAM_image_file={run_dir}/rv_dm_access_after_wakeup_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: rv_dm_access_after_escalation_reset uvm_test_seq: "top_chip_dv_rv_dm_access_after_escalation_reset_vseq" - sw_images: ["rv_dm_access_after_escalation_reset_test_vanilla_sram:5" "bootrom:5"] + sw_images: ["rv_dm_access_after_escalation_reset_test_vanilla:5" "bootrom:5"] run_opts: ["+use_jtag_dmi=1", - "+ChipMemSRAM_image_file={run_dir}/rv_dm_access_after_escalation_reset_test_vanilla_sram.vmem", + "+ChipMemDRAM_image_file={run_dir}/rv_dm_access_after_escalation_reset_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: mailbox_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["mailbox_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/mailbox_smoketest_vanilla_sram.vmem", + sw_images: ["mailbox_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/mailbox_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: mailbox_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["mailbox_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/mailbox_smoketest_cheri_sram.vmem", + sw_images: ["mailbox_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/mailbox_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: axi_sram_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["axi_sram_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/axi_sram_smoketest_vanilla_sram.vmem", + sw_images: ["axi_sram_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: axi_sram_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["axi_sram_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/axi_sram_smoketest_cheri_sram.vmem", + sw_images: ["axi_sram_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: axi_sram_tag_test uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["axi_sram_tag_test_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/axi_sram_tag_test_vanilla_sram.vmem", + sw_images: ["axi_sram_tag_test_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_tag_test_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: axi_sram_tag_test_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["axi_sram_tag_test_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/axi_sram_tag_test_cheri_sram.vmem", + sw_images: ["axi_sram_tag_test_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/axi_sram_tag_test_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: entropy_src_smoke uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["entropy_src_smoketest_vanilla_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/entropy_src_smoketest_vanilla_sram.vmem", + sw_images: ["entropy_src_smoketest_vanilla:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/entropy_src_smoketest_vanilla.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } { name: entropy_src_smoke_cheri uvm_test_seq: top_chip_dv_base_vseq - sw_images: ["entropy_src_smoketest_cheri_sram:5" "bootrom:5"] - run_opts: ["+ChipMemSRAM_image_file={run_dir}/entropy_src_smoketest_cheri_sram.vmem", + sw_images: ["entropy_src_smoketest_cheri:5" "bootrom:5"] + run_opts: ["+ChipMemDRAM_image_file={run_dir}/entropy_src_smoketest_cheri.vmem", "+ChipMemROM_image_file={run_dir}/bootrom_scrambled.vmem"] } ] diff --git a/hw/top_chip/dv/verilator/top_chip_verilator.core b/hw/top_chip/dv/verilator/top_chip_verilator.core index 13b251042..977798618 100644 --- a/hw/top_chip/dv/verilator/top_chip_verilator.core +++ b/hw/top_chip/dv/verilator/top_chip_verilator.core @@ -26,13 +26,13 @@ filesets: - lowrisc:dv_dpi_c:jtagdpi:0.1 - lowrisc:dv_dpi_sv:jtagdpi:0.1 - lowrisc:mocha_dv:sim_sram_axi:0.1 + - lowrisc:mocha_dv:sim_dram_axi:0.1 - lowrisc:dv:sw_test_status - lowrisc:dv:dv_test_status - lowrisc:sonata:i2cdpi - lowrisc:sonata:spidevicedpi files: - - dram_wrapper_sim.sv: { file_type: systemVerilogSource } - top_chip_verilator.sv: { file_type: systemVerilogSource } - top_chip_verilator.cc: { file_type: cppSource } - top_chip_verilator.vlt: { file_type: vlt } diff --git a/hw/top_chip/dv/verilator/top_chip_verilator.sv b/hw/top_chip/dv/verilator/top_chip_verilator.sv index ae8c4d152..ff03821db 100644 --- a/hw/top_chip/dv/verilator/top_chip_verilator.sv +++ b/hw/top_chip/dv/verilator/top_chip_verilator.sv @@ -277,7 +277,7 @@ module top_chip_verilator ( `undef SIM_SRAM_IF // Mock AXI external memory - dram_wrapper_sim u_dram_wrapper( + sim_dram_wrapper u_dram_wrapper( .clk_i (u_top_chip_system.clkmgr_clocks.clk_main_infra), .rst_ni (u_top_chip_system.rstmgr_resets.rst_main_n[rstmgr_pkg::DomainMainSel]), diff --git a/sw/cmake/tests.cmake b/sw/cmake/tests.cmake index d413ac851..44b5143d8 100644 --- a/sw/cmake/tests.cmake +++ b/sw/cmake/tests.cmake @@ -102,19 +102,6 @@ function(mocha_add_test) # create artefacts mocha_add_executable_artefacts(NAME ${NAME}) - # TODO: Remove this when UVM tb can run tests from DRAM - if(TRUE) - add_executable(${NAME}_sram ${arg_SOURCES}) - target_compile_options(${NAME}_sram PUBLIC ${FLAGS}) - foreach(LIB ${arg_LIBRARIES}) - target_link_libraries(${NAME}_sram PUBLIC ${LIB}_${ARCH_NAME}) - endforeach() - target_link_options(${NAME}_sram PUBLIC - "-Tmocha_sram.ld" "-L${LDS_DIR}" - ) - mocha_add_executable_artefacts(NAME ${NAME}_sram) - endif() - if(NOT arg_SKIP_VERILATOR) mocha_add_verilator_test(NAME ${NAME} ROM bootrom TIMEOUT ${arg_VERILATOR_TIMEOUT}) endif()