How to read RTL files in order properly with yosys + slang plugin Ibex. (not expert, just new here)

[jio566588]

when i try to read all rtl files from ibex/rtl/*.sv , it shows errors like this:

../ibex/rtl/ibex_csr.sv:9:10: error: 'prim_assert.sv': No such file or directory
`include "prim_assert.sv"
         ^~~~~~~~~~~~~~~~
../ibex/rtl/ibex_csr.sv:55:3: error: unknown macro or compiler directive '`ASSERT_KNOWN'
  `ASSERT_KNOWN(IbexCSREnValid, wr_en_i)
  ^~~~~~~~~~~~~
../ibex/rtl/ibex_pmp.sv:5:10: error: 'dv_fcov_macros.svh': No such file or directory
`include "dv_fcov_macros.svh"
         ^~~~~~~~~~~~~~~~~~~~
../ibex/rtl/ibex_pmp.sv:255:5: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
    `DV_FCOV_SIGNAL(logic, pmp_region_override,
    ^~~~~~~~~~~~~~~
../ibex/rtl/ibex_cs_registers.sv:10:10: error: 'prim_assert.sv': No such file or directory
`include "prim_assert.sv"
         ^~~~~~~~~~~~~~~~
../ibex/rtl/ibex_cs_registers.sv:1214:7: error: unknown macro or compiler directive '`ASSERT_INIT'
      `ASSERT_INIT(PMPAddrRstLowBitsZero_A, PMPRstAddr[i][PMP_ADDR_MSB-PMPAddrWidth:0] == '0)
      ^~~~~~~~~~~~
../ibex/rtl/ibex_cs_registers.sv:1680:3: error: unknown macro or compiler directive '`ASSERT'
  `ASSERT(IbexCsrOpEnRequiresAccess, csr_op_en_i |-> csr_access_i)
  ^~~~~~~
../ibex/rtl/ibex_multdiv_slow.sv:12:10: error: 'prim_assert.sv': No such file or directory
`include "prim_assert.sv"
         ^~~~~~~~~~~~~~~~
../ibex/rtl/ibex_multdiv_slow.sv:369:3: error: unknown macro or compiler directive '`ASSERT'
  `ASSERT(IbexMultDivStateValid, md_state_q inside {
  ^~~~~~~
../ibex/rtl/ibex_controller.sv:10:10: error: 'prim_assert.sv': No such file or directory
`include "prim_assert.sv"
         ^~~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:11:10: error: 'dv_fcov_macros.svh': No such file or directory
`include "dv_fcov_macros.svh"
         ^~~~~~~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:207:3: error: unknown macro or compiler directive '`ASSERT'
  `ASSERT(IllegalInsnOnlyIfInsnValid, illegal_insn_i |-> instr_valid_i)
  ^~~~~~~
../ibex/rtl/ibex_controller.sv:295:3: error: unknown macro or compiler directive '`ASSERT_IF'
  `ASSERT_IF(IbexExceptionPrioOnehot,
  ^~~~~~~~~~
../ibex/rtl/ibex_controller.sv:898:3: error: unknown macro or compiler directive '`ASSERT'
  `ASSERT(PipeEmptyOnIrq, ctrl_fsm_cs != IRQ_TAKEN & ctrl_fsm_ns == IRQ_TAKEN |->
  ^~~~~~~
../ibex/rtl/ibex_controller.sv:905:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
  `DV_FCOV_SIGNAL(logic, all_debug_req, debug_req_i || debug_mode_q || debug_single_step_i)
  ^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:906:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
  `DV_FCOV_SIGNAL(logic, debug_wakeup, (ctrl_fsm_cs == SLEEP) & (ctrl_fsm_ns == FIRST_FETCH) &
  ^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:908:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
  `DV_FCOV_SIGNAL(logic, interrupt_taken, (ctrl_fsm_cs != IRQ_TAKEN) & (ctrl_fsm_ns == IRQ_TAKEN))
  ^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:909:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
  `DV_FCOV_SIGNAL(logic, debug_entry_if,
  ^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:911:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
  `DV_FCOV_SIGNAL(logic, debug_entry_id,
  ^~~~~~~~~~~~~~~
../ibex/rtl/ibex_controller.sv:913:3: error: unknown macro or compiler directive '`DV_FCOV_SIGNAL'
  `DV_FCOV_SIGNAL(logic, pipe_flush, (ctrl_fsm_cs != FLUSH) & (ctrl_fsm_ns == FLUSH))

in ibex/rtl there are many missing files and modules linked to the files available at Vendor/lowrisc_ip/ip/prim/rtl.

so how to read RTL files in proper manner for Ibex synthesis? there are also other RTL files inside Vendor/lowrisc_ip/ip/prim/rtl & prim_generic/rtl

which rtl files should read first?

using SLANG plugin to read systemverilog files, instead of converting SV2V.
(don't judge my English please}
i'm using read_slang
i'm also unable to understand proper order in which rtl files are written.

My Environment

EDA tool and version: yosys + slang

Operating system:

Version of the Ibex source code:

[h-filali]

Hi @jio566588, thanks for reaching out! And don't worry, your English is perfectly clear.

Based on the errors in your log, it looks like your read_slang command is missing a few flags and dependencies. If you are using a wildcard (like ibex/rtl/*.sv), it will cause these exact errors for three reasons:

• Missing Include Paths: The compiler doesn't know where to find the headers. You need to point it to the vendor folders using the -I flag.
• Missing Synthesis Macro: The ASSERT and DV_FCOV errors happen because Yosys is trying to synthesize simulation code. You have to pass the -DSYNTHESIS flag to turn these off.
• Wrong File Order: SystemVerilog requires packages (like prim_pkg.sv and ibex_pkg.sv) to be read before the modules that use them. Reading the folder alphabetically breaks this.