diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index f40b937efa74b..299950c061356 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -798,6 +798,10 @@ def TuningFastDPWSSD
           "Prefer vpdpwssd instruction over vpmaddwd+vpaddd instruction sequence",
           [], InlineIgnore>;
 
+def TuningFastVectorFP16Div
+    : SubtargetFeature<"fast-vector-fp16-div", "HasFastFP16Div", "true",
+                        "Vector FP16 division is fast",
+                        [], InlineIgnore>;
 def TuningPreferNoGather
     : SubtargetFeature<"prefer-no-gather", "PreferGather", "false",
                        "Prefer no gather instructions",
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index c74d342fed1cb..65980e8a30105 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -50669,10 +50669,21 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
 
   // f32 recovers the quotient exactly when both operands fit in 24 bits
   MVT FPSclVT = MVT::f64;
-  if (EltBits <= 16 || BothFitFP(APFloat::IEEEsingle()))
+  EVT FP16VT = VT.changeVectorElementType(*DAG.getContext(), MVT::f16);
+  bool FP16VTUsable =
+      DCI.isBeforeLegalize() || DAG.getTargetLoweringInfo().isTypeLegal(FP16VT);
+  if ((EltBits == 8 || BothFitFP(APFloat::IEEEhalf())) &&
+      Subtarget.hasFastFP16Div() && FP16VTUsable)
+    FPSclVT = MVT::f16;
+  else if (EltBits <= 16 || BothFitFP(APFloat::IEEEsingle()))
     FPSclVT = MVT::f32;
   EVT FPVT = VT.changeVectorElementType(*DAG.getContext(), FPSclVT);
 
+  // FP16-to-i32 SAE conversions consume half as many lanes as FP16-to-i16.
+  MVT StrictISclVT = FPSclVT == MVT::f16 && EltBits <= 16 ? MVT::i16 : MVT::i32;
+  unsigned MaxStrictElts = std::min(512 / FPSclVT.getSizeInBits(),
+                                    512 / StrictISclVT.getSizeInBits());
+
   bool IsStrict = DAG.getMachineFunction().getFunction().hasFnAttribute(
       Attribute::StrictFP);
   if (IsStrict) {
@@ -50690,7 +50701,7 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
   // Nothing will split an illegal FP type after type legalization and the
   // strict SAE divide is 512-bit only.
   bool FPVTUsable = IsStrict
-                        ? FPVT.getSizeInBits() <= 512
+                        ? VT.getVectorNumElements() <= MaxStrictElts
                         : DCI.isBeforeLegalize() ||
                               DAG.getTargetLoweringInfo().isTypeLegal(FPVT);
 
@@ -50711,25 +50722,35 @@ static SDValue combineIntDivRem(SDNode *N, SelectionDAG &DAG,
   if (IsStrict) {
     // The converts are exact so only the divide and the truncate can
     // raise flags.
-    unsigned WideElts = 512 / FPSclVT.getSizeInBits(); // 16 f32 or 8 f64
-    MVT WideFP = MVT::getVectorVT(FPSclVT, WideElts);
-    MVT WideIScl = MVT::i32;
-    MVT WideI = MVT::getVectorVT(WideIScl, WideElts);
+    unsigned WideFPElts = 512 / FPSclVT.getSizeInBits();
+    MVT WideFP = MVT::getVectorVT(FPSclVT, WideFPElts);
+    MVT WideI = MVT::getVectorVT(StrictISclVT, MaxStrictElts);
     SDValue RN = DAG.getTargetConstant(X86::STATIC_ROUNDING::TO_NEAREST_INT, DL,
                                        MVT::i32); // {rn-sae}
     SDValue Quot =
         DAG.getNode(X86ISD::FDIV_RND, DL, WideFP,
                     widenSubVector(X, false, Subtarget, DAG, DL, 512),
                     widenSubVector(Y, false, Subtarget, DAG, DL, 512), RN);
+    if (MaxStrictElts != WideFPElts) {
+      MVT CvtFP = MVT::getVectorVT(FPSclVT, MaxStrictElts);
+      Quot = extractSubVector(Quot, 0, DAG, DL, CvtFP.getSizeInBits());
+    }
     unsigned FromFP = IsSigned ? X86ISD::CVTTP2SI_SAE : X86ISD::CVTTP2UI_SAE;
-    Q = DAG.getNode(FromFP, DL, WideI, Quot); // vcvttp*2dq/qq {sae}
-    MVT NarrowI = MVT::getVectorVT(WideIScl, VT.getVectorNumElements());
+    Q = DAG.getNode(FromFP, DL, WideI, Quot);
+    MVT NarrowI = MVT::getVectorVT(StrictISclVT, VT.getVectorNumElements());
     Q = extractSubVector(Q, 0, DAG, DL, NarrowI.getSizeInBits());
     Q = IsSigned ? DAG.getSExtOrTrunc(Q, DL, VT)
                  : DAG.getZExtOrTrunc(Q, DL, VT);
   } else {
+    SDValue FPQuot = DAG.getNode(ISD::FDIV, DL, FPVT, X, Y);
     unsigned FromFP = IsSigned ? ISD::FP_TO_SINT : ISD::FP_TO_UINT;
-    Q = DAG.getNode(FromFP, DL, VT, DAG.getNode(ISD::FDIV, DL, FPVT, X, Y));
+    if (FPSclVT == MVT::f16 && EltBits == 8) {
+      EVT I16VT = VT.changeVectorElementType(*DAG.getContext(), MVT::i16);
+      SDValue Q16 = DAG.getNode(FromFP, DL, I16VT, FPQuot);
+      Q = DAG.getNode(ISD::TRUNCATE, DL, VT, Q16);
+    } else {
+      Q = DAG.getNode(FromFP, DL, VT, FPQuot);
+    }
   }
   if (!IsRem)
     return Q;
diff --git a/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll b/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
index 10d6877da7ed7..d28e43b32c0d8 100644
--- a/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
+++ b/llvm/test/CodeGen/X86/2011-10-19-LegelizeLoad.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mcpu=corei7 | FileCheck %s
+; RUN: llc < %s -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
 target triple = "x86_64-unknown-linux-gnu"
@@ -30,6 +31,19 @@ define dso_local i32 @main() nounwind uwtable {
 ; CHECK-NEXT:    pextrw $0, %xmm0, res(%rip)
 ; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: main:
+; AVX512FP16:       # %bb.0: # %entry
+; AVX512FP16-NEXT:    vpmovsxbw i(%rip), %xmm0
+; AVX512FP16-NEXT:    vcvtw2ph %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovsxbw j(%rip), %xmm1
+; AVX512FP16-NEXT:    vcvtw2ph %xmm1, %xmm1
+; AVX512FP16-NEXT:    vdivph %xmm0, %xmm1, %xmm0
+; AVX512FP16-NEXT:    vcvttph2w %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovwb %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpextrw $0, %xmm0, res(%rip)
+; AVX512FP16-NEXT:    xorl %eax, %eax
+; AVX512FP16-NEXT:    retq
 entry:
   %0 = load <2 x i8>, ptr @i, align 8
   %1 = load <2 x i8>, ptr @j, align 8
diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
index 5cfdbb7af38ad..bae21705e6f1a 100644
--- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
+++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown   -mattr=+sse,+sse2 | FileCheck %s --check-prefix=X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse,+sse2 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 ; If the target does not have a single div/rem operation,
 ; -div-rem-pairs pass will decompose the remainder calculation as:
@@ -27,6 +28,15 @@ define i8 @scalar_i8(i8 %x, i8 %y, ptr %divdst) nounwind {
 ; X64-NEXT:    movb %al, (%rdx)
 ; X64-NEXT:    movl %ecx, %eax
 ; X64-NEXT:    retq
+;
+; AVX512FP16-LABEL: scalar_i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    movsbl %dil, %eax
+; AVX512FP16-NEXT:    idivb %sil
+; AVX512FP16-NEXT:    movsbl %ah, %ecx
+; AVX512FP16-NEXT:    movb %al, (%rdx)
+; AVX512FP16-NEXT:    movl %ecx, %eax
+; AVX512FP16-NEXT:    retq
   %div = sdiv i8 %x, %y
   store i8 %div, ptr %divdst, align 4
   %t1 = mul i8 %div, %y
@@ -701,6 +711,22 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y, ptr %divdst) nounwi
 ; X64-NEXT:    packuswb %xmm4, %xmm1
 ; X64-NEXT:    psubb %xmm1, %xmm0
 ; X64-NEXT:    retq
+;
+; AVX512FP16-LABEL: vector_i128_i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %xmm1, %ymm2
+; AVX512FP16-NEXT:    vcvtw2ph %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm3
+; AVX512FP16-NEXT:    vcvtw2ph %ymm3, %ymm3
+; AVX512FP16-NEXT:    vdivph %ymm2, %ymm3, %ymm2
+; AVX512FP16-NEXT:    vcvttph2w %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpmovwb %ymm2, (%rdi)
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
+; AVX512FP16-NEXT:    vpmullw %ymm1, %ymm2, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %div = sdiv <16 x i8> %x, %y
   store <16 x i8> %div, ptr %divdst, align 16
   %t1 = mul <16 x i8> %div, %y
diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
index 488a6d5860c40..c3ff69cbea314 100644
--- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
+++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-unsigned.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown   -mattr=+sse,+sse2 | FileCheck %s --check-prefix=X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+sse,+sse2 | FileCheck %s --check-prefix=X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 ; If the target does not have a single div/rem operation,
 ; -div-rem-pairs pass will decompose the remainder calculation as:
@@ -27,6 +28,15 @@ define i8 @scalar_i8(i8 %x, i8 %y, ptr %divdst) nounwind {
 ; X64-NEXT:    movb %al, (%rdx)
 ; X64-NEXT:    movl %ecx, %eax
 ; X64-NEXT:    retq
+;
+; AVX512FP16-LABEL: scalar_i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    movzbl %dil, %eax
+; AVX512FP16-NEXT:    divb %sil
+; AVX512FP16-NEXT:    movzbl %ah, %ecx
+; AVX512FP16-NEXT:    movb %al, (%rdx)
+; AVX512FP16-NEXT:    movl %ecx, %eax
+; AVX512FP16-NEXT:    retq
   %div = udiv i8 %x, %y
   store i8 %div, ptr %divdst, align 4
   %t1 = mul i8 %div, %y
@@ -658,6 +668,21 @@ define <16 x i8> @vector_i128_i8(<16 x i8> %x, <16 x i8> %y, ptr %divdst) nounwi
 ; X64-NEXT:    packuswb %xmm4, %xmm1
 ; X64-NEXT:    psubb %xmm1, %xmm0
 ; X64-NEXT:    retq
+;
+; AVX512FP16-LABEL: vector_i128_i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
+; AVX512FP16-NEXT:    vcvtw2ph %ymm1, %ymm2
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vcvtw2ph %ymm3, %ymm3
+; AVX512FP16-NEXT:    vdivph %ymm2, %ymm3, %ymm2
+; AVX512FP16-NEXT:    vcvttph2uw %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpmovwb %ymm2, (%rdi)
+; AVX512FP16-NEXT:    vpmullw %ymm1, %ymm2, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %div = udiv <16 x i8> %x, %y
   store <16 x i8> %div, ptr %divdst, align 16
   %t1 = mul <16 x i8> %div, %y
diff --git a/llvm/test/CodeGen/X86/known-bits.ll b/llvm/test/CodeGen/X86/known-bits.ll
index 0fef1170112a1..766aed2074f47 100644
--- a/llvm/test/CodeGen/X86/known-bits.ll
+++ b/llvm/test/CodeGen/X86/known-bits.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefixes=CHECK,X64
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 define void @knownbits_zext_in_reg(ptr) nounwind {
 ; CHECK-LABEL: knownbits_zext_in_reg:
@@ -12,6 +13,16 @@ define void @knownbits_zext_in_reg(ptr) nounwind {
 ; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    jne .LBB0_1
 ; CHECK-NEXT:    jmp .LBB0_1
+;
+; AVX512FP16-LABEL: knownbits_zext_in_reg:
+; AVX512FP16:       # %bb.0: # %BB
+; AVX512FP16-NEXT:    xorl %eax, %eax
+; AVX512FP16-NEXT:    .p2align 4
+; AVX512FP16-NEXT:  .LBB0_1: # %CF237
+; AVX512FP16-NEXT:    # =>This Inner Loop Header: Depth=1
+; AVX512FP16-NEXT:    testb %al, %al
+; AVX512FP16-NEXT:    jne .LBB0_1
+; AVX512FP16-NEXT:    jmp .LBB0_1
 BB:
   %L5 = load i8, ptr %0
   %Sl9 = select i1 true, i8 %L5, i8 undef
diff --git a/llvm/test/CodeGen/X86/scalar_widen_div.ll b/llvm/test/CodeGen/X86/scalar_widen_div.ll
index f24d018aea88f..599000197b76c 100644
--- a/llvm/test/CodeGen/X86/scalar_widen_div.ll
+++ b/llvm/test/CodeGen/X86/scalar_widen_div.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse4.2 |  FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 ; Verify when widening a divide/remainder operation, we only generate a
 ; divide/rem per element since divide/remainder can trap.
@@ -57,6 +58,22 @@ define <3 x i8> @test_char_div(<3 x i8> %num, <3 x i8> %div) {
 ; CHECK-NEXT:    movl %esi, %edx
 ; CHECK-NEXT:    movl %edi, %ecx
 ; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_char_div:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    movsbl %dil, %eax
+; AVX512FP16-NEXT:    idivb %cl
+; AVX512FP16-NEXT:    movl %eax, %ecx
+; AVX512FP16-NEXT:    movsbl %sil, %eax
+; AVX512FP16-NEXT:    idivb %r8b
+; AVX512FP16-NEXT:    movl %eax, %esi
+; AVX512FP16-NEXT:    movsbl %dl, %eax
+; AVX512FP16-NEXT:    idivb %r9b
+; AVX512FP16-NEXT:    movl %eax, %edi
+; AVX512FP16-NEXT:    movl %ecx, %eax
+; AVX512FP16-NEXT:    movl %esi, %edx
+; AVX512FP16-NEXT:    movl %edi, %ecx
+; AVX512FP16-NEXT:    retq
   %div.r = sdiv <3 x i8> %num, %div
   ret <3 x i8>  %div.r
 }
@@ -77,6 +94,22 @@ define <3 x i8> @test_uchar_div(<3 x i8> %num, <3 x i8> %div) {
 ; CHECK-NEXT:    movl %esi, %edx
 ; CHECK-NEXT:    movl %edi, %ecx
 ; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_uchar_div:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    movzbl %dil, %eax
+; AVX512FP16-NEXT:    divb %cl
+; AVX512FP16-NEXT:    movl %eax, %ecx
+; AVX512FP16-NEXT:    movzbl %sil, %eax
+; AVX512FP16-NEXT:    divb %r8b
+; AVX512FP16-NEXT:    movl %eax, %esi
+; AVX512FP16-NEXT:    movzbl %dl, %eax
+; AVX512FP16-NEXT:    divb %r9b
+; AVX512FP16-NEXT:    movl %eax, %edi
+; AVX512FP16-NEXT:    movl %ecx, %eax
+; AVX512FP16-NEXT:    movl %esi, %edx
+; AVX512FP16-NEXT:    movl %edi, %ecx
+; AVX512FP16-NEXT:    retq
   %div.r = udiv <3 x i8> %num, %div
   ret <3 x i8>  %div.r
 }
@@ -227,6 +260,20 @@ define <4 x i8> @test_char_rem(<4 x i8> %num, <4 x i8> %rem) {
 ; CHECK-NEXT:    pshufb {{.*#+}} xmm1 = xmm1[0,2,4,6,u,u,u,u,u,u,u,u,u,u,u,u]
 ; CHECK-NEXT:    psubb %xmm1, %xmm0
 ; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_char_rem:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %xmm1, %xmm2
+; AVX512FP16-NEXT:    vcvtw2ph %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %xmm3
+; AVX512FP16-NEXT:    vcvtw2ph %xmm3, %xmm3
+; AVX512FP16-NEXT:    vdivph %xmm2, %xmm3, %xmm2
+; AVX512FP16-NEXT:    vcvttph2w %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX512FP16-NEXT:    vpmullw %xmm1, %xmm2, %xmm1
+; AVX512FP16-NEXT:    vpmovwb %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    retq
   %rem.r = srem <4 x i8> %num, %rem
   ret <4 x i8>  %rem.r
 }
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
index 92615c859ea72..8f3b40e6687ee 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-128.ll
@@ -4,6 +4,7 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=AVX2NOBW
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=AVX512BW
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 ;
 ; sdiv by 7
@@ -246,6 +247,23 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_div7_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpaddb %xmm0, %xmm1, %xmm0
+; AVX512FP16-NEXT:    vpsrlw $2, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpbroadcastb {{.*#+}} xmm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512FP16-NEXT:    vpternlogd {{.*#+}} xmm0 = xmm1 ^ (xmm0 & m32bcst)
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpcmpgtb %xmm0, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = sdiv <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <16 x i8> %res
 }
@@ -345,6 +363,23 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divconstant_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm0
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [65427,65409,57,103,65467,43,79,65427,65427,79,43,65467,103,57,57,65427]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm0
+; AVX512FP16-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpcmpgtb %xmm0, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = sdiv <16 x i8> %a, <i8 7, i8 8, i8 9, i8 10,i8 11, i8 12, i8 13, i8 14, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9,i8 9, i8 7>
   ret <16 x i8> %res
 }
@@ -653,6 +688,27 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_rem7_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpaddb %xmm0, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpsrlw $2, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpbroadcastb {{.*#+}} xmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512FP16-NEXT:    vpternlogd {{.*#+}} xmm1 = xmm2 ^ (xmm1 & m32bcst)
+; AVX512FP16-NEXT:    vpsubb %xmm2, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpcmpgtb %xmm1, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpsubb %xmm2, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpsllw $3, %xmm1, %xmm2
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpsubb %xmm2, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = srem <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <16 x i8> %res
 }
@@ -815,6 +871,27 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_remconstant_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm2
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [65427,65409,57,103,65467,43,79,65427,65427,79,43,65467,103,57,57,65427]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpmovwb %ymm2, %xmm2
+; AVX512FP16-NEXT:    vpaddb %xmm1, %xmm2, %xmm1
+; AVX512FP16-NEXT:    vpmovsxbw %xmm1, %ymm1
+; AVX512FP16-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpcmpgtb %xmm1, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpsubb %xmm2, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [7,8,9,10,11,12,13,14,14,13,12,11,10,9,9,7]
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = srem <16 x i8> %a, <i8 7, i8 8, i8 9, i8 10,i8 11, i8 12, i8 13, i8 14, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9,i8 9, i8 7>
   ret <16 x i8> %res
 }
@@ -1009,6 +1086,21 @@ define <16 x i8> @test_rem_variable_16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
 ; AVX512BW-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_rem_variable_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %xmm1, %ymm2
+; AVX512FP16-NEXT:    vcvtw2ph %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm3
+; AVX512FP16-NEXT:    vcvtw2ph %ymm3, %ymm3
+; AVX512FP16-NEXT:    vdivph %ymm2, %ymm3, %ymm2
+; AVX512FP16-NEXT:    vcvttph2w %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
+; AVX512FP16-NEXT:    vpmullw %ymm1, %ymm2, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = srem <16 x i8> %a, %b
   ret <16 x i8> %res
 }
@@ -1108,6 +1200,24 @@ define <16 x i8> @PR143238(<16 x i8> %a0) {
 ; AVX512BW-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: PR143238:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm1
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm0
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [65409,86,65409,103,43,65427,65409,57,103,65467,43,79,65427,65417,65409,121]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm0
+; AVX512FP16-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpcmpgtb %xmm0, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %sdiv = sdiv <16 x i8> %a0, <i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17>
   %mask = and <16 x i8> %sdiv, splat (i8 1)
   ret <16 x i8> %mask
@@ -1266,6 +1376,18 @@ define <16 x i8> @test_divv_16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
 ; AVX512BW-NEXT:    vpmovdb %zmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %xmm1, %ymm1
+; AVX512FP16-NEXT:    vcvtw2ph %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm0
+; AVX512FP16-NEXT:    vcvtw2ph %ymm0, %ymm0
+; AVX512FP16-NEXT:    vdivph %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vcvttph2w %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = sdiv <16 x i8> %a, %b
   ret <16 x i8> %res
 }
@@ -1634,3 +1756,276 @@ define <4 x i32> @test_divv_4i32_one_narrow(<4 x i32> %a, <4 x i32> %b) nounwind
   %res = sdiv <4 x i32> %aa, %b
   ret <4 x i32> %res
 }
+
+define <8 x i16> @test_divv_8i16_narrow(<8 x i16> %a, <8 x i16> %b) nounwind {
+; SSE2-LABEL: test_divv_8i16_narrow:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    psraw $6, %xmm0
+; SSE2-NEXT:    psraw $6, %xmm1
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
+; SSE2-NEXT:    psrad $16, %xmm2
+; SSE2-NEXT:    cvtdq2ps %xmm2, %xmm2
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-NEXT:    psrad $16, %xmm3
+; SSE2-NEXT:    cvtdq2ps %xmm3, %xmm3
+; SSE2-NEXT:    divps %xmm2, %xmm3
+; SSE2-NEXT:    cvttps2dq %xmm3, %xmm2
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    psrad $16, %xmm1
+; SSE2-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    psrad $16, %xmm0
+; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE2-NEXT:    divps %xmm1, %xmm0
+; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT:    packssdw %xmm2, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: test_divv_8i16_narrow:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    psraw $6, %xmm0
+; SSE41-NEXT:    psraw $6, %xmm1
+; SSE41-NEXT:    pmovsxwd %xmm1, %xmm2
+; SSE41-NEXT:    cvtdq2ps %xmm2, %xmm2
+; SSE41-NEXT:    pmovsxwd %xmm0, %xmm3
+; SSE41-NEXT:    cvtdq2ps %xmm3, %xmm3
+; SSE41-NEXT:    divps %xmm2, %xmm3
+; SSE41-NEXT:    cvttps2dq %xmm3, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; SSE41-NEXT:    pmovsxwd %xmm1, %xmm1
+; SSE41-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; SSE41-NEXT:    pmovsxwd %xmm0, %xmm0
+; SSE41-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE41-NEXT:    divps %xmm1, %xmm0
+; SSE41-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE41-NEXT:    packssdw %xmm0, %xmm2
+; SSE41-NEXT:    movdqa %xmm2, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: test_divv_8i16_narrow:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpsraw $6, %xmm0, %xmm0
+; AVX1-NEXT:    vpsraw $6, %xmm1, %xmm1
+; AVX1-NEXT:    vpmovsxwd %xmm1, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; AVX1-NEXT:    vpmovsxwd %xmm1, %xmm1
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; AVX1-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX1-NEXT:    vpmovsxwd %xmm0, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; AVX1-NEXT:    vpmovsxwd %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm2, %ymm0
+; AVX1-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX1-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX1-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vzeroupper
+; AVX1-NEXT:    retq
+;
+; AVX2NOBW-LABEL: test_divv_8i16_narrow:
+; AVX2NOBW:       # %bb.0:
+; AVX2NOBW-NEXT:    vpsraw $6, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vpsraw $6, %xmm1, %xmm1
+; AVX2NOBW-NEXT:    vpmovsxwd %xmm1, %ymm1
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vpmovsxwd %xmm0, %ymm0
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vzeroupper
+; AVX2NOBW-NEXT:    retq
+;
+; AVX512BW-LABEL: test_divv_8i16_narrow:
+; AVX512BW:       # %bb.0:
+; AVX512BW-NEXT:    vpsraw $6, %xmm0, %xmm0
+; AVX512BW-NEXT:    vpsraw $6, %xmm1, %xmm1
+; AVX512BW-NEXT:    vpmovsxwd %xmm1, %ymm1
+; AVX512BW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX512BW-NEXT:    vpmovsxwd %xmm0, %ymm0
+; AVX512BW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX512BW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX512BW-NEXT:    vpmovdw %zmm0, %ymm0
+; AVX512BW-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
+; AVX512BW-NEXT:    vzeroupper
+; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_8i16_narrow:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpsraw $6, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpsraw $6, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vcvtw2ph %xmm1, %xmm1
+; AVX512FP16-NEXT:    vcvtw2ph %xmm0, %xmm0
+; AVX512FP16-NEXT:    vdivph %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vcvttph2w %xmm0, %xmm0
+; AVX512FP16-NEXT:    retq
+  %aa = ashr <8 x i16> %a, splat (i16 6)
+  %bb = ashr <8 x i16> %b, splat (i16 6)
+  %res = sdiv <8 x i16> %aa, %bb
+  ret <8 x i16> %res
+}
+
+define <4 x i8> @test_divv_4i8(<4 x i8> %a, <4 x i8> %b) nounwind {
+; SSE2-LABEL: test_divv_4i8:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    psrad $24, %xmm1
+; SSE2-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    psrad $24, %xmm0
+; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE2-NEXT:    divps %xmm1, %xmm0
+; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT:    packssdw %xmm0, %xmm0
+; SSE2-NEXT:    packsswb %xmm0, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: test_divv_4i8:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    pmovsxbd %xmm1, %xmm1
+; SSE41-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE41-NEXT:    pmovsxbd %xmm0, %xmm0
+; SSE41-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE41-NEXT:    divps %xmm1, %xmm0
+; SSE41-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE41-NEXT:    packssdw %xmm0, %xmm0
+; SSE41-NEXT:    packsswb %xmm0, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: test_divv_4i8:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpmovsxbd %xmm1, %xmm1
+; AVX-NEXT:    vcvtdq2ps %xmm1, %xmm1
+; AVX-NEXT:    vpmovsxbd %xmm0, %xmm0
+; AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
+; AVX-NEXT:    vdivps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vcvttps2dq %xmm0, %xmm0
+; AVX-NEXT:    vpackssdw %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vpacksswb %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_4i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %xmm1, %xmm1
+; AVX512FP16-NEXT:    vcvtw2ph %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %xmm0
+; AVX512FP16-NEXT:    vcvtw2ph %xmm0, %xmm0
+; AVX512FP16-NEXT:    vdivph %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vcvttph2w %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovwb %xmm0, %xmm0
+; AVX512FP16-NEXT:    retq
+  %res = sdiv <4 x i8> %a, %b
+  ret <4 x i8> %res
+}
+
+define <8 x i8> @test_divv_8i8(<8 x i8> %a, <8 x i8> %b) nounwind {
+; SSE2-LABEL: test_divv_8i8:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm1[4],xmm2[5],xmm1[5],xmm2[6],xmm1[6],xmm2[7],xmm1[7]
+; SSE2-NEXT:    psrad $24, %xmm2
+; SSE2-NEXT:    cvtdq2ps %xmm2, %xmm2
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm0[4],xmm3[5],xmm0[5],xmm3[6],xmm0[6],xmm3[7],xmm0[7]
+; SSE2-NEXT:    psrad $24, %xmm3
+; SSE2-NEXT:    cvtdq2ps %xmm3, %xmm3
+; SSE2-NEXT:    divps %xmm2, %xmm3
+; SSE2-NEXT:    cvttps2dq %xmm3, %xmm2
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    psrad $24, %xmm1
+; SSE2-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3]
+; SSE2-NEXT:    psrad $24, %xmm0
+; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE2-NEXT:    divps %xmm1, %xmm0
+; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT:    packssdw %xmm2, %xmm0
+; SSE2-NEXT:    packsswb %xmm0, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: test_divv_8i8:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    pmovsxbd %xmm1, %xmm2
+; SSE41-NEXT:    cvtdq2ps %xmm2, %xmm2
+; SSE41-NEXT:    pmovsxbd %xmm0, %xmm3
+; SSE41-NEXT:    cvtdq2ps %xmm3, %xmm3
+; SSE41-NEXT:    divps %xmm2, %xmm3
+; SSE41-NEXT:    cvttps2dq %xmm3, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; SSE41-NEXT:    pmovsxbd %xmm1, %xmm1
+; SSE41-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; SSE41-NEXT:    pmovsxbd %xmm0, %xmm0
+; SSE41-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE41-NEXT:    divps %xmm1, %xmm0
+; SSE41-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE41-NEXT:    packssdw %xmm0, %xmm2
+; SSE41-NEXT:    packsswb %xmm2, %xmm2
+; SSE41-NEXT:    movdqa %xmm2, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: test_divv_8i8:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpmovsxbd %xmm1, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; AVX1-NEXT:    vpmovsxbd %xmm1, %xmm1
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; AVX1-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX1-NEXT:    vpmovsxbd %xmm0, %xmm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; AVX1-NEXT:    vpmovsxbd %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm2, %ymm0
+; AVX1-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX1-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX1-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpacksswb %xmm0, %xmm0, %xmm0
+; AVX1-NEXT:    vzeroupper
+; AVX1-NEXT:    retq
+;
+; AVX2NOBW-LABEL: test_divv_8i8:
+; AVX2NOBW:       # %bb.0:
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm1, %ymm1
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm0, %ymm0
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vpacksswb %xmm0, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vzeroupper
+; AVX2NOBW-NEXT:    retq
+;
+; AVX512BW-LABEL: test_divv_8i8:
+; AVX512BW:       # %bb.0:
+; AVX512BW-NEXT:    vpmovsxbd %xmm1, %ymm1
+; AVX512BW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX512BW-NEXT:    vpmovsxbd %xmm0, %ymm0
+; AVX512BW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX512BW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX512BW-NEXT:    vpmovdb %zmm0, %xmm0
+; AVX512BW-NEXT:    vzeroupper
+; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_8i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %xmm1, %xmm1
+; AVX512FP16-NEXT:    vcvtw2ph %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %xmm0
+; AVX512FP16-NEXT:    vcvtw2ph %xmm0, %xmm0
+; AVX512FP16-NEXT:    vdivph %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vcvttph2w %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovwb %xmm0, %xmm0
+; AVX512FP16-NEXT:    retq
+  %res = sdiv <8 x i8> %a, %b
+  ret <8 x i8> %res
+}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
index e42a3febbf041..bfd55480e35ea 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-256.ll
@@ -2,6 +2,8 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2 --check-prefix=AVX2NOBW
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX2 --check-prefix=AVX512BW
+; RUN: llc < %s -mtriple=x86_64 -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
+; RUN: llc -mtriple=x86_64 -mattr=+avx512fp16 < %s | FileCheck %s --check-prefix=NO-FAST-FP16
 
 ;
 ; sdiv by 7
@@ -244,6 +246,39 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpcmpgtb %ymm0, %ymm1, %ymm1
 ; AVX512BW-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_div7_32i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %ymm0, %zmm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpaddb %ymm0, %ymm1, %ymm0
+; AVX512FP16-NEXT:    vpsrlw $2, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpbroadcastb {{.*#+}} ymm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512FP16-NEXT:    vpternlogd {{.*#+}} ymm0 = ymm1 ^ (ymm0 & m32bcst)
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpcmpgtb %ymm0, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_div7_32i8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovsxbw %ymm0, %zmm1
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpaddb %ymm0, %ymm1, %ymm0
+; NO-FAST-FP16-NEXT:    vpsrlw $2, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpbroadcastb {{.*#+}} ymm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; NO-FAST-FP16-NEXT:    vpxor %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; NO-FAST-FP16-NEXT:    vpcmpgtb %ymm0, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    retq
   %res = sdiv <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <32 x i8> %res
 }
@@ -340,6 +375,38 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpcmpgtb %ymm0, %ymm1, %ymm1
 ; AVX512BW-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divconstant_32i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX512FP16-NEXT:    vpmovsxbw %ymm0, %zmm0
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [65427,65409,57,103,65467,43,79,65427,65417,65409,121,57,27,103,49,65467,65467,49,103,27,57,121,65409,65417,65427,79,43,65467,103,57,65409,65427]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; AVX512FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovsxbw %ymm0, %zmm0
+; AVX512FP16-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpcmpgtb %ymm0, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_divconstant_32i8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; NO-FAST-FP16-NEXT:    vpmovsxbw %ymm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [65427,65409,57,103,65467,43,79,65427,65417,65409,121,57,27,103,49,65467,65467,49,103,27,57,121,65409,65417,65427,79,43,65467,103,57,65409,65427]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpmovsxbw %ymm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; NO-FAST-FP16-NEXT:    vpcmpgtb %ymm0, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    retq
   %res = sdiv <32 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
   ret <32 x i8> %res
 }
@@ -642,6 +709,47 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
 ; AVX512BW-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_rem7_32i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %ymm0, %zmm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpaddb %ymm0, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpsrlw $2, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpbroadcastb {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512FP16-NEXT:    vpternlogd {{.*#+}} ymm1 = ymm2 ^ (ymm1 & m32bcst)
+; AVX512FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpcmpgtb %ymm1, %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpsllw $3, %ymm1, %ymm2
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_rem7_32i8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovsxbw %ymm0, %zmm1
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427,65427]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpaddb %ymm0, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsrlw $2, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpbroadcastb {{.*#+}} ymm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; NO-FAST-FP16-NEXT:    vpxor %ymm2, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; NO-FAST-FP16-NEXT:    vpcmpgtb %ymm1, %ymm2, %ymm2
+; NO-FAST-FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsllw $3, %ymm1, %ymm2
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; NO-FAST-FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    retq
   %res = srem <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <32 x i8> %res
 }
@@ -761,6 +869,46 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpmovwb %zmm1, %ymm1
 ; AVX512BW-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_remconstant_32i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; AVX512FP16-NEXT:    vpmovsxbw %ymm0, %zmm2
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2 # [65427,65409,57,103,65467,43,79,65427,65417,65409,121,57,27,103,49,65467,65467,49,103,27,57,121,65409,65417,65427,79,43,65467,103,57,65409,65427]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpmovwb %zmm2, %ymm2
+; AVX512FP16-NEXT:    vpaddb %ymm1, %ymm2, %ymm1
+; AVX512FP16-NEXT:    vpmovsxbw %ymm1, %zmm1
+; AVX512FP16-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpcmpgtb %ymm1, %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_remconstant_32i8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm1
+; NO-FAST-FP16-NEXT:    vpmovsxbw %ymm0, %zmm2
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2 # [65427,65409,57,103,65467,43,79,65427,65417,65409,121,57,27,103,49,65467,65467,49,103,27,57,121,65409,65417,65427,79,43,65467,103,57,65409,65427]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm2, %ymm2
+; NO-FAST-FP16-NEXT:    vpaddb %ymm1, %ymm2, %ymm1
+; NO-FAST-FP16-NEXT:    vpmovsxbw %ymm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpsravw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; NO-FAST-FP16-NEXT:    vpcmpgtb %ymm1, %ymm2, %ymm2
+; NO-FAST-FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    retq
   %res = srem <32 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
   ret <32 x i8> %res
 }
@@ -856,3 +1004,282 @@ define <8 x i32> @test_remv_8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
   %res = srem <8 x i32> %a, %b
   ret <8 x i32> %res
 }
+
+define <32 x i8> @test_sdiv_32i8_fast_fp16(<32 x i8> %a, <32 x i8> %b) nounwind {
+; AVX1-LABEL: test_sdiv_32i8_fast_fp16:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vpmovsxbd %xmm2, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
+; AVX1-NEXT:    vpmovsxbd %xmm4, %xmm4
+; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm3, %ymm3
+; AVX1-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT:    vpmovsxbd %xmm4, %xmm5
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm6 = xmm4[1,1,1,1]
+; AVX1-NEXT:    vpmovsxbd %xmm6, %xmm6
+; AVX1-NEXT:    vinsertf128 $1, %xmm6, %ymm5, %ymm5
+; AVX1-NEXT:    vcvtdq2ps %ymm5, %ymm5
+; AVX1-NEXT:    vdivps %ymm3, %ymm5, %ymm3
+; AVX1-NEXT:    vcvttps2dq %ymm3, %ymm3
+; AVX1-NEXT:    vextractf128 $1, %ymm3, %xmm5
+; AVX1-NEXT:    vpackssdw %xmm5, %xmm3, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm5 = xmm2[2,3,2,3]
+; AVX1-NEXT:    vpmovsxbd %xmm5, %xmm5
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[3,3,3,3]
+; AVX1-NEXT:    vpmovsxbd %xmm2, %xmm2
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm5, %ymm2
+; AVX1-NEXT:    vcvtdq2ps %ymm2, %ymm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; AVX1-NEXT:    vpmovsxbd %xmm5, %xmm5
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; AVX1-NEXT:    vpmovsxbd %xmm4, %xmm4
+; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm5, %ymm4
+; AVX1-NEXT:    vcvtdq2ps %ymm4, %ymm4
+; AVX1-NEXT:    vdivps %ymm2, %ymm4, %ymm2
+; AVX1-NEXT:    vcvttps2dq %ymm2, %ymm2
+; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm4
+; AVX1-NEXT:    vpackssdw %xmm4, %xmm2, %xmm2
+; AVX1-NEXT:    vpacksswb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT:    vpmovsxbd %xmm1, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm1[1,1,1,1]
+; AVX1-NEXT:    vpmovsxbd %xmm4, %xmm4
+; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm3, %ymm3
+; AVX1-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX1-NEXT:    vpmovsxbd %xmm0, %xmm4
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm5 = xmm0[1,1,1,1]
+; AVX1-NEXT:    vpmovsxbd %xmm5, %xmm5
+; AVX1-NEXT:    vinsertf128 $1, %xmm5, %ymm4, %ymm4
+; AVX1-NEXT:    vcvtdq2ps %ymm4, %ymm4
+; AVX1-NEXT:    vdivps %ymm3, %ymm4, %ymm3
+; AVX1-NEXT:    vcvttps2dq %ymm3, %ymm3
+; AVX1-NEXT:    vextractf128 $1, %ymm3, %xmm4
+; AVX1-NEXT:    vpackssdw %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm1[2,3,2,3]
+; AVX1-NEXT:    vpmovsxbd %xmm4, %xmm4
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[3,3,3,3]
+; AVX1-NEXT:    vpmovsxbd %xmm1, %xmm1
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm4, %ymm1
+; AVX1-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; AVX1-NEXT:    vpmovsxbd %xmm4, %xmm4
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; AVX1-NEXT:    vpmovsxbd %xmm0, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm4, %ymm0
+; AVX1-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX1-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX1-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpacksswb %xmm0, %xmm3, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2NOBW-LABEL: test_sdiv_32i8_fast_fp16:
+; AVX2NOBW:       # %bb.0:
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm1, %xmm2
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm2, %ymm3
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm4
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm4, %ymm5
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm5, %ymm5
+; AVX2NOBW-NEXT:    vdivps %ymm3, %ymm5, %ymm3
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm3, %ymm3
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm3, %xmm5
+; AVX2NOBW-NEXT:    vpackssdw %xmm5, %xmm3, %xmm3
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm1, %ymm5
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm5, %ymm5
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm0, %ymm6
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm6, %ymm6
+; AVX2NOBW-NEXT:    vdivps %ymm5, %ymm6, %ymm5
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm5, %ymm5
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm5, %xmm6
+; AVX2NOBW-NEXT:    vpackssdw %xmm6, %xmm5, %xmm5
+; AVX2NOBW-NEXT:    vinserti128 $1, %xmm3, %ymm5, %ymm3
+; AVX2NOBW-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm2, %ymm2
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm2, %ymm2
+; AVX2NOBW-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[2,3,2,3]
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm4, %ymm4
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm4, %ymm4
+; AVX2NOBW-NEXT:    vdivps %ymm2, %ymm4, %ymm2
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm2, %ymm2
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm2, %xmm4
+; AVX2NOBW-NEXT:    vpackssdw %xmm4, %xmm2, %xmm2
+; AVX2NOBW-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm1, %ymm1
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; AVX2NOBW-NEXT:    vpmovsxbd %xmm0, %ymm0
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vpacksswb %ymm0, %ymm3, %ymm0
+; AVX2NOBW-NEXT:    retq
+;
+; AVX512BW-LABEL: test_sdiv_32i8_fast_fp16:
+; AVX512BW:       # %bb.0:
+; AVX512BW-NEXT:    vpmovsxbd %xmm1, %zmm2
+; AVX512BW-NEXT:    vcvtdq2ps %zmm2, %zmm2
+; AVX512BW-NEXT:    vpmovsxbd %xmm0, %zmm3
+; AVX512BW-NEXT:    vcvtdq2ps %zmm3, %zmm3
+; AVX512BW-NEXT:    vdivps %zmm2, %zmm3, %zmm2
+; AVX512BW-NEXT:    vcvttps2dq %zmm2, %zmm2
+; AVX512BW-NEXT:    vpmovdb %zmm2, %xmm2
+; AVX512BW-NEXT:    vextracti128 $1, %ymm1, %xmm1
+; AVX512BW-NEXT:    vpmovsxbd %xmm1, %zmm1
+; AVX512BW-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; AVX512BW-NEXT:    vextracti128 $1, %ymm0, %xmm0
+; AVX512BW-NEXT:    vpmovsxbd %xmm0, %zmm0
+; AVX512BW-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; AVX512BW-NEXT:    vdivps %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT:    vcvttps2dq %zmm0, %zmm0
+; AVX512BW-NEXT:    vpmovdb %zmm0, %xmm0
+; AVX512BW-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm0
+; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_sdiv_32i8_fast_fp16:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %ymm1, %zmm1
+; AVX512FP16-NEXT:    vcvtw2ph %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovsxbw %ymm0, %zmm0
+; AVX512FP16-NEXT:    vcvtw2ph %zmm0, %zmm0
+; AVX512FP16-NEXT:    vdivph %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vcvttph2w %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_sdiv_32i8_fast_fp16:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovsxbd %xmm1, %zmm2
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm2, %zmm2
+; NO-FAST-FP16-NEXT:    vpmovsxbd %xmm0, %zmm3
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm3, %zmm3
+; NO-FAST-FP16-NEXT:    vdivps %zmm2, %zmm3, %zmm2
+; NO-FAST-FP16-NEXT:    vcvttps2dq %zmm2, %zmm2
+; NO-FAST-FP16-NEXT:    vpmovdb %zmm2, %xmm2
+; NO-FAST-FP16-NEXT:    vextracti128 $1, %ymm1, %xmm1
+; NO-FAST-FP16-NEXT:    vpmovsxbd %xmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vextracti128 $1, %ymm0, %xmm0
+; NO-FAST-FP16-NEXT:    vpmovsxbd %xmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vdivps %zmm1, %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vcvttps2dq %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpmovdb %zmm0, %xmm0
+; NO-FAST-FP16-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm0
+; NO-FAST-FP16-NEXT:    retq
+
+
+%res = sdiv <32 x i8> %a, %b
+ret <32 x i8> %res
+}
+
+define void @test_divv_16i16_sext8(ptr %dst, ptr %x, ptr %y) nounwind {
+; AVX1-LABEL: test_divv_16i16_sext8:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpmovsxbd 12(%rsi), %xmm0
+; AVX1-NEXT:    vpmovsxbd 8(%rsi), %xmm1
+; AVX1-NEXT:    vpmovsxbd 4(%rsi), %xmm2
+; AVX1-NEXT:    vpmovsxbd (%rsi), %xmm3
+; AVX1-NEXT:    vpmovsxbd 12(%rdx), %xmm4
+; AVX1-NEXT:    vpmovsxbd 8(%rdx), %xmm5
+; AVX1-NEXT:    vpmovsxbd 4(%rdx), %xmm6
+; AVX1-NEXT:    vpmovsxbd (%rdx), %xmm7
+; AVX1-NEXT:    vinsertf128 $1, %xmm6, %ymm7, %ymm6
+; AVX1-NEXT:    vcvtdq2ps %ymm6, %ymm6
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
+; AVX1-NEXT:    vcvtdq2ps %ymm2, %ymm2
+; AVX1-NEXT:    vdivps %ymm6, %ymm2, %ymm2
+; AVX1-NEXT:    vcvttps2dq %ymm2, %ymm2
+; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm3
+; AVX1-NEXT:    vpackssdw %xmm3, %xmm2, %xmm2
+; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm5, %ymm3
+; AVX1-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX1-NEXT:    vdivps %ymm3, %ymm0, %ymm0
+; AVX1-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vbroadcastss {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
+; AVX1-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpand %xmm1, %xmm2, %xmm1
+; AVX1-NEXT:    vpackuswb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vmovdqa %xmm0, (%rdi)
+; AVX1-NEXT:    vzeroupper
+; AVX1-NEXT:    retq
+;
+; AVX2NOBW-LABEL: test_divv_16i16_sext8:
+; AVX2NOBW:       # %bb.0:
+; AVX2NOBW-NEXT:    vpmovsxbd 8(%rsi), %ymm0
+; AVX2NOBW-NEXT:    vpmovsxbd (%rsi), %ymm1
+; AVX2NOBW-NEXT:    vpmovsxbd 8(%rdx), %ymm2
+; AVX2NOBW-NEXT:    vpmovsxbd (%rdx), %ymm3
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vdivps %ymm3, %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm1, %xmm3
+; AVX2NOBW-NEXT:    vpackssdw %xmm3, %xmm1, %xmm1
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm2, %ymm2
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vdivps %ymm2, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm2
+; AVX2NOBW-NEXT:    vpackssdw %xmm2, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vpbroadcastw {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
+; AVX2NOBW-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vpand %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT:    vpackuswb %xmm0, %xmm1, %xmm0
+; AVX2NOBW-NEXT:    vmovdqa %xmm0, (%rdi)
+; AVX2NOBW-NEXT:    vzeroupper
+; AVX2NOBW-NEXT:    retq
+;
+; AVX512BW-LABEL: test_divv_16i16_sext8:
+; AVX512BW:       # %bb.0:
+; AVX512BW-NEXT:    vpmovsxbd (%rsi), %zmm0
+; AVX512BW-NEXT:    vpmovsxbd (%rdx), %zmm1
+; AVX512BW-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; AVX512BW-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; AVX512BW-NEXT:    vdivps %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT:    vcvttps2dq %zmm0, %zmm0
+; AVX512BW-NEXT:    vpmovdb %zmm0, (%rdi)
+; AVX512BW-NEXT:    vzeroupper
+; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_16i16_sext8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw (%rsi), %ymm0
+; AVX512FP16-NEXT:    vpmovsxbw (%rdx), %ymm1
+; AVX512FP16-NEXT:    vcvtw2ph %ymm1, %ymm1
+; AVX512FP16-NEXT:    vcvtw2ph %ymm0, %ymm0
+; AVX512FP16-NEXT:    vdivph %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vcvttph2w %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, (%rdi)
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_divv_16i16_sext8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovsxbd (%rsi), %zmm0
+; NO-FAST-FP16-NEXT:    vpmovsxbd (%rdx), %zmm1
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vdivps %zmm1, %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vcvttps2dq %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpmovdb %zmm0, (%rdi)
+; NO-FAST-FP16-NEXT:    vzeroupper
+; NO-FAST-FP16-NEXT:    retq
+  %a8 = load <16 x i8>, ptr %x
+  %a = sext <16 x i8> %a8 to <16 x i16>
+  %b8 = load <16 x i8>, ptr %y
+  %b = sext <16 x i8> %b8 to <16 x i16>
+  %res = sdiv <16 x i16> %a, %b
+  %t = trunc <16 x i16> %res to <16 x i8>
+  store <16 x i8> %t, ptr %dst
+  ret void
+}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
index 3f82e99a3111e..cb8845c36fa95 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-sdiv-512.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512F
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX --check-prefix=AVX512BW
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 ;
 ; sdiv by 7
@@ -156,6 +157,27 @@ define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpmovm2b %k0, %zmm1
 ; AVX512BW-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_div7_64i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[12],zmm0[12],zmm1[13],zmm0[13],zmm1[14],zmm0[14],zmm1[15],zmm0[15],zmm1[24],zmm0[24],zmm1[25],zmm0[25],zmm1[26],zmm0[26],zmm1[27],zmm0[27],zmm1[28],zmm0[28],zmm1[29],zmm0[29],zmm1[30],zmm0[30],zmm1[31],zmm0[31],zmm1[40],zmm0[40],zmm1[41],zmm0[41],zmm1[42],zmm0[42],zmm1[43],zmm0[43],zmm1[44],zmm0[44],zmm1[45],zmm0[45],zmm1[46],zmm0[46],zmm1[47],zmm0[47],zmm1[56],zmm0[56],zmm1[57],zmm0[57],zmm1[58],zmm0[58],zmm1[59],zmm0[59],zmm1[60],zmm0[60],zmm1[61],zmm0[61],zmm1[62],zmm0[62],zmm1[63],zmm0[63]
+; AVX512FP16-NEXT:    vpbroadcastw {{.*#+}} zmm3 = [0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147]
+; AVX512FP16-NEXT:    vpmulhw %zmm3, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm1 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[16],zmm0[16],zmm1[17],zmm0[17],zmm1[18],zmm0[18],zmm1[19],zmm0[19],zmm1[20],zmm0[20],zmm1[21],zmm0[21],zmm1[22],zmm0[22],zmm1[23],zmm0[23],zmm1[32],zmm0[32],zmm1[33],zmm0[33],zmm1[34],zmm0[34],zmm1[35],zmm0[35],zmm1[36],zmm0[36],zmm1[37],zmm0[37],zmm1[38],zmm0[38],zmm1[39],zmm0[39],zmm1[48],zmm0[48],zmm1[49],zmm0[49],zmm1[50],zmm0[50],zmm1[51],zmm0[51],zmm1[52],zmm0[52],zmm1[53],zmm0[53],zmm1[54],zmm0[54],zmm1[55],zmm0[55]
+; AVX512FP16-NEXT:    vpmulhw %zmm3, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpaddb %zmm0, %zmm1, %zmm0
+; AVX512FP16-NEXT:    vpsrlw $2, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpbroadcastb {{.*#+}} zmm1 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512FP16-NEXT:    vpternlogd {{.*#+}} zmm0 = zmm1 ^ (zmm0 & m32bcst)
+; AVX512FP16-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovb2m %zmm0, %k0
+; AVX512FP16-NEXT:    vpmovm2b %k0, %zmm1
+; AVX512FP16-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    retq
   %res = sdiv <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <64 x i8> %res
 }
@@ -237,6 +259,32 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpmovm2b %k0, %zmm1
 ; AVX512BW-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divconstant_64i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[12],zmm0[12],zmm1[13],zmm0[13],zmm1[14],zmm0[14],zmm1[15],zmm0[15],zmm1[24],zmm0[24],zmm1[25],zmm0[25],zmm1[26],zmm0[26],zmm1[27],zmm0[27],zmm1[28],zmm0[28],zmm1[29],zmm0[29],zmm1[30],zmm0[30],zmm1[31],zmm0[31],zmm1[40],zmm0[40],zmm1[41],zmm0[41],zmm1[42],zmm0[42],zmm1[43],zmm0[43],zmm1[44],zmm0[44],zmm1[45],zmm0[45],zmm1[46],zmm0[46],zmm1[47],zmm0[47],zmm1[56],zmm0[56],zmm1[57],zmm0[57],zmm1[58],zmm0[58],zmm1[59],zmm0[59],zmm1[60],zmm0[60],zmm1[61],zmm0[61],zmm1[62],zmm0[62],zmm1[63],zmm0[63]
+; AVX512FP16-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2 # [0,137,0,129,0,121,0,57,0,27,0,103,0,49,0,187,0,133,0,129,0,125,0,121,0,59,0,57,0,111,0,27,0,137,0,71,0,147,0,19,0,79,0,41,0,43,0,179,0,147,0,79,0,43,0,187,0,103,0,57,0,129,0,147]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm1 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[16],zmm0[16],zmm1[17],zmm0[17],zmm1[18],zmm0[18],zmm1[19],zmm0[19],zmm1[20],zmm0[20],zmm1[21],zmm0[21],zmm1[22],zmm0[22],zmm1[23],zmm0[23],zmm1[32],zmm0[32],zmm1[33],zmm0[33],zmm1[34],zmm0[34],zmm1[35],zmm0[35],zmm1[36],zmm0[36],zmm1[37],zmm0[37],zmm1[38],zmm0[38],zmm1[39],zmm0[39],zmm1[48],zmm0[48],zmm1[49],zmm0[49],zmm1[50],zmm0[50],zmm1[51],zmm0[51],zmm1[52],zmm0[52],zmm1[53],zmm0[53],zmm1[54],zmm0[54],zmm1[55],zmm0[55]
+; AVX512FP16-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,147,0,129,0,57,0,103,0,187,0,43,0,79,0,147,0,179,0,43,0,41,0,79,0,19,0,147,0,71,0,137,0,27,0,111,0,57,0,59,0,121,0,125,0,129,0,133,0,187,0,49,0,103,0,27,0,57,0,121,0,129,0,137]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpaddb %zmm0, %zmm1, %zmm0
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm1 = zmm0[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
+; AVX512FP16-NEXT:    vpsraw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm0 = zmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; AVX512FP16-NEXT:    vpsraw $8, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpackuswb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovb2m %zmm0, %k0
+; AVX512FP16-NEXT:    vpmovm2b %k0, %zmm1
+; AVX512FP16-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    retq
   %res = sdiv <64 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
   ret <64 x i8> %res
 }
@@ -423,6 +471,31 @@ define <64 x i8> @test_rem7_64i8(<64 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsubb %zmm2, %zmm1, %zmm1
 ; AVX512BW-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_rem7_64i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[12],zmm0[12],zmm1[13],zmm0[13],zmm1[14],zmm0[14],zmm1[15],zmm0[15],zmm1[24],zmm0[24],zmm1[25],zmm0[25],zmm1[26],zmm0[26],zmm1[27],zmm0[27],zmm1[28],zmm0[28],zmm1[29],zmm0[29],zmm1[30],zmm0[30],zmm1[31],zmm0[31],zmm1[40],zmm0[40],zmm1[41],zmm0[41],zmm1[42],zmm0[42],zmm1[43],zmm0[43],zmm1[44],zmm0[44],zmm1[45],zmm0[45],zmm1[46],zmm0[46],zmm1[47],zmm0[47],zmm1[56],zmm0[56],zmm1[57],zmm0[57],zmm1[58],zmm0[58],zmm1[59],zmm0[59],zmm1[60],zmm0[60],zmm1[61],zmm0[61],zmm1[62],zmm0[62],zmm1[63],zmm0[63]
+; AVX512FP16-NEXT:    vpbroadcastw {{.*#+}} zmm3 = [0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147,0,147]
+; AVX512FP16-NEXT:    vpmulhw %zmm3, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm1 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[16],zmm0[16],zmm1[17],zmm0[17],zmm1[18],zmm0[18],zmm1[19],zmm0[19],zmm1[20],zmm0[20],zmm1[21],zmm0[21],zmm1[22],zmm0[22],zmm1[23],zmm0[23],zmm1[32],zmm0[32],zmm1[33],zmm0[33],zmm1[34],zmm0[34],zmm1[35],zmm0[35],zmm1[36],zmm0[36],zmm1[37],zmm0[37],zmm1[38],zmm0[38],zmm1[39],zmm0[39],zmm1[48],zmm0[48],zmm1[49],zmm0[49],zmm1[50],zmm0[50],zmm1[51],zmm0[51],zmm1[52],zmm0[52],zmm1[53],zmm0[53],zmm1[54],zmm0[54],zmm1[55],zmm0[55]
+; AVX512FP16-NEXT:    vpmulhw %zmm3, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpaddb %zmm0, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsrlw $2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpbroadcastb {{.*#+}} zmm2 = [32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32]
+; AVX512FP16-NEXT:    vpternlogd {{.*#+}} zmm1 = zmm2 ^ (zmm1 & m32bcst)
+; AVX512FP16-NEXT:    vpsubb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovb2m %zmm1, %k0
+; AVX512FP16-NEXT:    vpmovm2b %k0, %zmm2
+; AVX512FP16-NEXT:    vpsubb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsllw $3, %zmm1, %zmm2
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsubb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    retq
   %res = srem <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <64 x i8> %res
 }
@@ -522,6 +595,37 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpternlogd {{.*#+}} zmm1 = zmm1 | (zmm2 & m32bcst)
 ; AVX512BW-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_remconstant_64i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm1[8],zmm0[8],zmm1[9],zmm0[9],zmm1[10],zmm0[10],zmm1[11],zmm0[11],zmm1[12],zmm0[12],zmm1[13],zmm0[13],zmm1[14],zmm0[14],zmm1[15],zmm0[15],zmm1[24],zmm0[24],zmm1[25],zmm0[25],zmm1[26],zmm0[26],zmm1[27],zmm0[27],zmm1[28],zmm0[28],zmm1[29],zmm0[29],zmm1[30],zmm0[30],zmm1[31],zmm0[31],zmm1[40],zmm0[40],zmm1[41],zmm0[41],zmm1[42],zmm0[42],zmm1[43],zmm0[43],zmm1[44],zmm0[44],zmm1[45],zmm0[45],zmm1[46],zmm0[46],zmm1[47],zmm0[47],zmm1[56],zmm0[56],zmm1[57],zmm0[57],zmm1[58],zmm0[58],zmm1[59],zmm0[59],zmm1[60],zmm0[60],zmm1[61],zmm0[61],zmm1[62],zmm0[62],zmm1[63],zmm0[63]
+; AVX512FP16-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2 # [0,137,0,129,0,121,0,57,0,27,0,103,0,49,0,187,0,133,0,129,0,125,0,121,0,59,0,57,0,111,0,27,0,137,0,71,0,147,0,19,0,79,0,41,0,43,0,179,0,147,0,79,0,43,0,187,0,103,0,57,0,129,0,147]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm1 = zmm1[0],zmm0[0],zmm1[1],zmm0[1],zmm1[2],zmm0[2],zmm1[3],zmm0[3],zmm1[4],zmm0[4],zmm1[5],zmm0[5],zmm1[6],zmm0[6],zmm1[7],zmm0[7],zmm1[16],zmm0[16],zmm1[17],zmm0[17],zmm1[18],zmm0[18],zmm1[19],zmm0[19],zmm1[20],zmm0[20],zmm1[21],zmm0[21],zmm1[22],zmm0[22],zmm1[23],zmm0[23],zmm1[32],zmm0[32],zmm1[33],zmm0[33],zmm1[34],zmm0[34],zmm1[35],zmm0[35],zmm1[36],zmm0[36],zmm1[37],zmm0[37],zmm1[38],zmm0[38],zmm1[39],zmm0[39],zmm1[48],zmm0[48],zmm1[49],zmm0[49],zmm1[50],zmm0[50],zmm1[51],zmm0[51],zmm1[52],zmm0[52],zmm1[53],zmm0[53],zmm1[54],zmm0[54],zmm1[55],zmm0[55]
+; AVX512FP16-NEXT:    vpmulhw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,147,0,129,0,57,0,103,0,187,0,43,0,79,0,147,0,179,0,43,0,41,0,79,0,19,0,147,0,71,0,137,0,27,0,111,0,57,0,59,0,121,0,125,0,129,0,133,0,187,0,49,0,103,0,27,0,57,0,121,0,129,0,137]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpandq {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm2
+; AVX512FP16-NEXT:    vpaddb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm1[8,8,9,9,10,10,11,11,12,12,13,13,14,14,15,15,24,24,25,25,26,26,27,27,28,28,29,29,30,30,31,31,40,40,41,41,42,42,43,43,44,44,45,45,46,46,47,47,56,56,57,57,58,58,59,59,60,60,61,61,62,62,63,63]
+; AVX512FP16-NEXT:    vpsraw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm1 = zmm1[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7,16,16,17,17,18,18,19,19,20,20,21,21,22,22,23,23,32,32,33,33,34,34,35,35,36,36,37,37,38,38,39,39,48,48,49,49,50,50,51,51,52,52,53,53,54,54,55,55]
+; AVX512FP16-NEXT:    vpsraw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovb2m %zmm1, %k0
+; AVX512FP16-NEXT:    vpmovm2b %k0, %zmm2
+; AVX512FP16-NEXT:    vpsubb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm2 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
+; AVX512FP16-NEXT:    vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22,0,24,0,26,0,28,0,30,0,32,0,34,0,36,0,38,0,37,0,35,0,33,0,31,0,29,0,27,0,25,0,23,0,21,0,19,0,17,0,15,0,13,0,11,0,9,0,7]
+; AVX512FP16-NEXT:    vpsllw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpternlogd {{.*#+}} zmm1 = zmm1 | (zmm2 & m32bcst)
+; AVX512FP16-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    retq
   %res = srem <64 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
   ret <64 x i8> %res
 }
diff --git a/llvm/test/CodeGen/X86/vector-idiv-strictfp.ll b/llvm/test/CodeGen/X86/vector-idiv-strictfp.ll
index 7add2e5ac4d6c..4eaaf5eaa61d4 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-strictfp.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-strictfp.ll
@@ -1,5 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=CHECK
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 define <16 x i8> @test_divv_16i8_strictfp(<16 x i8> %a, <16 x i8> %b) nounwind strictfp {
 ; CHECK-LABEL: test_divv_16i8_strictfp:
@@ -13,6 +14,18 @@ define <16 x i8> @test_divv_16i8_strictfp(<16 x i8> %a, <16 x i8> %b) nounwind s
 ; CHECK-NEXT:    vpmovdb %zmm0, %xmm0
 ; CHECK-NEXT:    vzeroupper
 ; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_16i8_strictfp:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
+; AVX512FP16-NEXT:    vcvtw2ph %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vcvtw2ph %ymm0, %ymm0
+; AVX512FP16-NEXT:    vdivph {rn-sae}, %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vcvttph2uw {sae}, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = udiv <16 x i8> %a, %b
   ret <16 x i8> %res
 }
@@ -201,3 +214,216 @@ define void @test_divv_32i32_strictfp(<32 x i32> %a, <32 x i32> %b, ptr %p) noun
   store <32 x i32> %res, ptr %p
   ret void
 }
+
+define <32 x i8> @test_sdivv_32i8_strictfp(<32 x i8> %a, <32 x i8> %b) nounwind strictfp {
+; CHECK-LABEL: test_sdivv_32i8_strictfp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpmovsxbd %xmm1, %zmm2
+; CHECK-NEXT:    vcvtdq2ps %zmm2, %zmm2
+; CHECK-NEXT:    vpmovsxbd %xmm0, %zmm3
+; CHECK-NEXT:    vcvtdq2ps %zmm3, %zmm3
+; CHECK-NEXT:    vdivps {rn-sae}, %zmm2, %zmm3, %zmm2
+; CHECK-NEXT:    vcvttps2dq {sae}, %zmm2, %zmm2
+; CHECK-NEXT:    vpmovdb %zmm2, %xmm2
+; CHECK-NEXT:    vextracti128 $1, %ymm1, %xmm1
+; CHECK-NEXT:    vpmovsxbd %xmm1, %zmm1
+; CHECK-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; CHECK-NEXT:    vextracti128 $1, %ymm0, %xmm0
+; CHECK-NEXT:    vpmovsxbd %xmm0, %zmm0
+; CHECK-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    vcvttps2dq {sae}, %zmm0, %zmm0
+; CHECK-NEXT:    vpmovdb %zmm0, %xmm0
+; CHECK-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm0
+; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_sdivv_32i8_strictfp:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %ymm1, %zmm1
+; AVX512FP16-NEXT:    vcvtw2ph %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovsxbw %ymm0, %zmm0
+; AVX512FP16-NEXT:    vcvtw2ph %zmm0, %zmm0
+; AVX512FP16-NEXT:    vdivph {rn-sae}, %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vcvttph2w {sae}, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; AVX512FP16-NEXT:    retq
+  %res = sdiv <32 x i8> %a, %b
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_sremv_32i8_strictfp(<32 x i8> %a, <32 x i8> %b) nounwind strictfp {
+; CHECK-LABEL: test_sremv_32i8_strictfp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpmovsxbd %xmm1, %zmm2
+; CHECK-NEXT:    vcvtdq2ps %zmm2, %zmm2
+; CHECK-NEXT:    vpmovsxbd %xmm0, %zmm3
+; CHECK-NEXT:    vcvtdq2ps %zmm3, %zmm3
+; CHECK-NEXT:    vdivps {rn-sae}, %zmm2, %zmm3, %zmm2
+; CHECK-NEXT:    vcvttps2dq {sae}, %zmm2, %zmm2
+; CHECK-NEXT:    vpmovdb %zmm2, %xmm2
+; CHECK-NEXT:    vextracti128 $1, %ymm1, %xmm3
+; CHECK-NEXT:    vpmovsxbd %xmm3, %zmm3
+; CHECK-NEXT:    vcvtdq2ps %zmm3, %zmm3
+; CHECK-NEXT:    vextracti128 $1, %ymm0, %xmm4
+; CHECK-NEXT:    vpmovsxbd %xmm4, %zmm4
+; CHECK-NEXT:    vcvtdq2ps %zmm4, %zmm4
+; CHECK-NEXT:    vdivps {rn-sae}, %zmm3, %zmm4, %zmm3
+; CHECK-NEXT:    vcvttps2dq {sae}, %zmm3, %zmm3
+; CHECK-NEXT:    vpmovdb %zmm3, %xmm3
+; CHECK-NEXT:    vinserti128 $1, %xmm3, %ymm2, %ymm2
+; CHECK-NEXT:    vpmullw %ymm1, %ymm2, %ymm3
+; CHECK-NEXT:    vpbroadcastw {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; CHECK-NEXT:    vpand %ymm4, %ymm3, %ymm3
+; CHECK-NEXT:    vpandn %ymm1, %ymm4, %ymm1
+; CHECK-NEXT:    vpmaddubsw %ymm1, %ymm2, %ymm1
+; CHECK-NEXT:    vpsllw $8, %ymm1, %ymm1
+; CHECK-NEXT:    vpor %ymm1, %ymm3, %ymm1
+; CHECK-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_sremv_32i8_strictfp:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %ymm1, %zmm2
+; AVX512FP16-NEXT:    vcvtw2ph %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpmovsxbw %ymm0, %zmm3
+; AVX512FP16-NEXT:    vcvtw2ph %zmm3, %zmm3
+; AVX512FP16-NEXT:    vdivph {rn-sae}, %zmm2, %zmm3, %zmm2
+; AVX512FP16-NEXT:    vcvttph2w {sae}, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
+; AVX512FP16-NEXT:    vpmullw %zmm1, %zmm2, %zmm1
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    retq
+  %res = srem <32 x i8> %a, %b
+  ret <32 x i8> %res
+}
+
+define <32 x i8> @test_uremv_32i8_strictfp(<32 x i8> %a, <32 x i8> %b) nounwind strictfp {
+; CHECK-LABEL: test_uremv_32i8_strictfp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
+; CHECK-NEXT:    vcvtdq2ps %zmm2, %zmm2
+; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm3 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
+; CHECK-NEXT:    vcvtdq2ps %zmm3, %zmm3
+; CHECK-NEXT:    vdivps {rn-sae}, %zmm2, %zmm3, %zmm2
+; CHECK-NEXT:    vcvttps2udq {sae}, %zmm2, %zmm2
+; CHECK-NEXT:    vpmovdb %zmm2, %xmm2
+; CHECK-NEXT:    vextracti128 $1, %ymm1, %xmm3
+; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm3 = xmm3[0],zero,zero,zero,xmm3[1],zero,zero,zero,xmm3[2],zero,zero,zero,xmm3[3],zero,zero,zero,xmm3[4],zero,zero,zero,xmm3[5],zero,zero,zero,xmm3[6],zero,zero,zero,xmm3[7],zero,zero,zero,xmm3[8],zero,zero,zero,xmm3[9],zero,zero,zero,xmm3[10],zero,zero,zero,xmm3[11],zero,zero,zero,xmm3[12],zero,zero,zero,xmm3[13],zero,zero,zero,xmm3[14],zero,zero,zero,xmm3[15],zero,zero,zero
+; CHECK-NEXT:    vcvtdq2ps %zmm3, %zmm3
+; CHECK-NEXT:    vextracti128 $1, %ymm0, %xmm4
+; CHECK-NEXT:    vpmovzxbd {{.*#+}} zmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero,xmm4[4],zero,zero,zero,xmm4[5],zero,zero,zero,xmm4[6],zero,zero,zero,xmm4[7],zero,zero,zero,xmm4[8],zero,zero,zero,xmm4[9],zero,zero,zero,xmm4[10],zero,zero,zero,xmm4[11],zero,zero,zero,xmm4[12],zero,zero,zero,xmm4[13],zero,zero,zero,xmm4[14],zero,zero,zero,xmm4[15],zero,zero,zero
+; CHECK-NEXT:    vcvtdq2ps %zmm4, %zmm4
+; CHECK-NEXT:    vdivps {rn-sae}, %zmm3, %zmm4, %zmm3
+; CHECK-NEXT:    vcvttps2udq {sae}, %zmm3, %zmm3
+; CHECK-NEXT:    vpmovdb %zmm3, %xmm3
+; CHECK-NEXT:    vinserti128 $1, %xmm3, %ymm2, %ymm2
+; CHECK-NEXT:    vpmullw %ymm1, %ymm2, %ymm3
+; CHECK-NEXT:    vpbroadcastw {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255]
+; CHECK-NEXT:    vpand %ymm4, %ymm3, %ymm3
+; CHECK-NEXT:    vpandn %ymm1, %ymm4, %ymm1
+; CHECK-NEXT:    vpmaddubsw %ymm1, %ymm2, %ymm1
+; CHECK-NEXT:    vpsllw $8, %ymm1, %ymm1
+; CHECK-NEXT:    vpor %ymm1, %ymm3, %ymm1
+; CHECK-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_uremv_32i8_strictfp:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
+; AVX512FP16-NEXT:    vcvtw2ph %zmm1, %zmm2
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm3 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; AVX512FP16-NEXT:    vcvtw2ph %zmm3, %zmm3
+; AVX512FP16-NEXT:    vdivph {rn-sae}, %zmm2, %zmm3, %zmm2
+; AVX512FP16-NEXT:    vcvttph2uw {sae}, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpmullw %zmm1, %zmm2, %zmm1
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    retq
+  %res = urem <32 x i8> %a, %b
+  ret <32 x i8> %res
+}
+
+define <16 x i8> @test_masked_sdivv_16i8_strictfp(<16 x i8> %a, <16 x i8> %b, <16 x i1> %m) nounwind strictfp {
+; CHECK-LABEL: test_masked_sdivv_16i8_strictfp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpmovsxbd %xmm1, %zmm1
+; CHECK-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; CHECK-NEXT:    vpmovsxbd %xmm0, %zmm0
+; CHECK-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    vcvttps2dq {sae}, %zmm0, %zmm0
+; CHECK-NEXT:    vpmovdb %zmm0, %xmm0
+; CHECK-NEXT:    vzeroupper
+; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_masked_sdivv_16i8_strictfp:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovsxbw %xmm1, %ymm1
+; AVX512FP16-NEXT:    vcvtw2ph %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovsxbw %xmm0, %ymm0
+; AVX512FP16-NEXT:    vcvtw2ph %ymm0, %ymm0
+; AVX512FP16-NEXT:    vdivph {rn-sae}, %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vcvttph2w {sae}, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
+  %res = call <16 x i8> @llvm.masked.sdiv(<16 x i8> %a, <16 x i8> %b, <16 x i1> %m)
+  ret <16 x i8> %res
+}
+
+define <16 x i16> @test_sdivv_16i16_narrow_strictfp(<16 x i16> %a, <16 x i16> %b) nounwind strictfp {
+; CHECK-LABEL: test_sdivv_16i16_narrow_strictfp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpsraw $6, %ymm0, %ymm0
+; CHECK-NEXT:    vpsraw $6, %ymm1, %ymm1
+; CHECK-NEXT:    vpmovsxwd %ymm1, %zmm1
+; CHECK-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; CHECK-NEXT:    vpmovsxwd %ymm0, %zmm0
+; CHECK-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    vcvttps2dq {sae}, %zmm0, %zmm0
+; CHECK-NEXT:    vpmovdw %zmm0, %ymm0
+; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_sdivv_16i16_narrow_strictfp:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpsraw $6, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpsraw $6, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vcvtw2ph %ymm1, %ymm1
+; AVX512FP16-NEXT:    vcvtw2ph %ymm0, %ymm0
+; AVX512FP16-NEXT:    vdivph {rn-sae}, %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vcvttph2w {sae}, %zmm0, %zmm0
+; AVX512FP16-NEXT:    # kill: def $ymm0 killed $ymm0 killed $zmm0
+; AVX512FP16-NEXT:    retq
+  %aa = ashr <16 x i16> %a, splat (i16 6)
+  %bb = ashr <16 x i16> %b, splat (i16 6)
+  %res = sdiv <16 x i16> %aa, %bb
+  ret <16 x i16> %res
+}
+
+define <16 x i32> @test_sdivv_16i32_narrow_strictfp(<16 x i32> %a, <16 x i32> %b) nounwind strictfp {
+; CHECK-LABEL: test_sdivv_16i32_narrow_strictfp:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vpsrad $22, %zmm0, %zmm0
+; CHECK-NEXT:    vpsrad $22, %zmm1, %zmm1
+; CHECK-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; CHECK-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; CHECK-NEXT:    vdivps {rn-sae}, %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    vcvttps2dq {sae}, %zmm0, %zmm0
+; CHECK-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_sdivv_16i32_narrow_strictfp:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpsrad $22, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpsrad $22, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vcvtdq2ph %zmm1, %ymm1
+; AVX512FP16-NEXT:    vcvtdq2ph %zmm0, %ymm0
+; AVX512FP16-NEXT:    vdivph {rn-sae}, %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vcvttph2dq {sae}, %ymm0, %zmm0
+; AVX512FP16-NEXT:    retq
+  %aa = ashr <16 x i32> %a, splat (i32 22)
+  %bb = ashr <16 x i32> %b, splat (i32 22)
+  %res = sdiv <16 x i32> %aa, %bb
+  ret <16 x i32> %res
+}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
index 54e158d87e792..2ca47570dea01 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-128.ll
@@ -4,6 +4,7 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX --check-prefix=AVX1
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=AVX2NOBW
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX --check-prefix=AVX2 --check-prefix=AVX512BW
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 ;
 ; udiv by 7
@@ -254,6 +255,21 @@ define <16 x i8> @test_div7_16i8(<16 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_div7_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpsrlw $1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpsrlw $2, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = udiv <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <16 x i8> %res
 }
@@ -419,6 +435,25 @@ define <16 x i8> @test_divconstant_16i8(<16 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divconstant_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [37,32,57,205,117,171,79,147,147,79,171,117,205,57,57,37]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0 # [128,0,0,0,128,0,0,0,0,0,0,128,0,0,0,128]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = udiv <16 x i8> %a, <i8 7, i8 8, i8 9, i8 10,i8 11, i8 12, i8 13, i8 14, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9,i8 9, i8 7>
   ret <16 x i8> %res
 }
@@ -790,6 +825,18 @@ define <16 x i8> @test_divv_16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
 ; AVX512BW-NEXT:    vpmovdb %zmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
+; AVX512FP16-NEXT:    vcvtw2ph %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vcvtw2ph %ymm0, %ymm0
+; AVX512FP16-NEXT:    vdivph %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vcvttph2uw %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = udiv <16 x i8> %a, %b
   ret <16 x i8> %res
 }
@@ -1118,6 +1165,25 @@ define <16 x i8> @test_rem7_16i8(<16 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_rem7_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm2
+; AVX512FP16-NEXT:    vpsrlw $1, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpaddb %xmm1, %xmm2, %xmm1
+; AVX512FP16-NEXT:    vpaddw %xmm1, %xmm1, %xmm2
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm2
+; AVX512FP16-NEXT:    vpsrlw $2, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm2, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = urem <16 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <16 x i8> %res
 }
@@ -1308,6 +1374,27 @@ define <16 x i8> @test_remconstant_16i8(<16 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_remconstant_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [37,32,57,205,117,171,79,147,147,79,171,117,205,57,57,37]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm2
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm2 = xmm2[0],zero,xmm2[1],zero,xmm2[2],zero,xmm2[3],zero,xmm2[4],zero,xmm2[5],zero,xmm2[6],zero,xmm2[7],zero,xmm2[8],zero,xmm2[9],zero,xmm2[10],zero,xmm2[11],zero,xmm2[12],zero,xmm2[13],zero,xmm2[14],zero,xmm2[15],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2 # [128,0,0,0,128,0,0,0,0,0,0,128,0,0,0,128]
+; AVX512FP16-NEXT:    vpsrlw $8, %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpmovwb %ymm2, %xmm2
+; AVX512FP16-NEXT:    vpaddb %xmm1, %xmm2, %xmm1
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
+; AVX512FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1 # [7,8,9,10,11,12,13,14,14,13,12,11,10,9,9,7]
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = urem <16 x i8> %a, <i8 7, i8 8, i8 9, i8 10,i8 11, i8 12, i8 13, i8 14, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9,i8 9, i8 7>
   ret <16 x i8> %res
 }
@@ -1973,6 +2060,20 @@ define <16 x i8> @test_remv_16i8(<16 x i8> %a, <16 x i8> %b) nounwind {
 ; AVX512BW-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
 ; AVX512BW-NEXT:    vzeroupper
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_remv_16i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero,xmm1[8],zero,xmm1[9],zero,xmm1[10],zero,xmm1[11],zero,xmm1[12],zero,xmm1[13],zero,xmm1[14],zero,xmm1[15],zero
+; AVX512FP16-NEXT:    vcvtw2ph %ymm1, %ymm2
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm3 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero,xmm0[8],zero,xmm0[9],zero,xmm0[10],zero,xmm0[11],zero,xmm0[12],zero,xmm0[13],zero,xmm0[14],zero,xmm0[15],zero
+; AVX512FP16-NEXT:    vcvtw2ph %ymm3, %ymm3
+; AVX512FP16-NEXT:    vdivph %ymm2, %ymm3, %ymm2
+; AVX512FP16-NEXT:    vcvttph2uw %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpmullw %ymm1, %ymm2, %ymm1
+; AVX512FP16-NEXT:    vpmovwb %ymm1, %xmm1
+; AVX512FP16-NEXT:    vpsubb %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
   %res = urem <16 x i8> %a, %b
   ret <16 x i8> %res
 }
@@ -2203,3 +2304,274 @@ define <4 x i32> @test_remv_4i32(<4 x i32> %a, <4 x i32> %b) nounwind {
   %res = urem <4 x i32> %a, %b
   ret <4 x i32> %res
 }
+
+define <8 x i16> @test_divv_8i16_narrow(<8 x i16> %a, <8 x i16> %b) nounwind {
+; SSE2-LABEL: test_divv_8i16_narrow:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    psrlw $6, %xmm0
+; SSE2-NEXT:    psrlw $6, %xmm1
+; SSE2-NEXT:    pxor %xmm2, %xmm2
+; SSE2-NEXT:    movdqa %xmm1, %xmm3
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; SSE2-NEXT:    cvtdq2ps %xmm3, %xmm3
+; SSE2-NEXT:    movdqa %xmm0, %xmm4
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
+; SSE2-NEXT:    cvtdq2ps %xmm4, %xmm4
+; SSE2-NEXT:    divps %xmm3, %xmm4
+; SSE2-NEXT:    cvttps2dq %xmm4, %xmm3
+; SSE2-NEXT:    pslld $16, %xmm3
+; SSE2-NEXT:    psrad $16, %xmm3
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSE2-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE2-NEXT:    divps %xmm1, %xmm0
+; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT:    pslld $16, %xmm0
+; SSE2-NEXT:    psrad $16, %xmm0
+; SSE2-NEXT:    packssdw %xmm3, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: test_divv_8i16_narrow:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    psrlw $6, %xmm0
+; SSE41-NEXT:    psrlw $6, %xmm1
+; SSE41-NEXT:    pxor %xmm2, %xmm2
+; SSE41-NEXT:    pmovzxwd {{.*#+}} xmm3 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; SSE41-NEXT:    punpckhwd {{.*#+}} xmm1 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; SSE41-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE41-NEXT:    pmovzxwd {{.*#+}} xmm4 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; SSE41-NEXT:    punpckhwd {{.*#+}} xmm0 = xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE41-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE41-NEXT:    divps %xmm1, %xmm0
+; SSE41-NEXT:    cvttps2dq %xmm0, %xmm1
+; SSE41-NEXT:    cvtdq2ps %xmm3, %xmm0
+; SSE41-NEXT:    cvtdq2ps %xmm4, %xmm2
+; SSE41-NEXT:    divps %xmm0, %xmm2
+; SSE41-NEXT:    cvttps2dq %xmm2, %xmm0
+; SSE41-NEXT:    packusdw %xmm1, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: test_divv_8i16_narrow:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; AVX1-NEXT:    vpsrlw $6, %xmm1, %xmm1
+; AVX1-NEXT:    vpxor %xmm2, %xmm2, %xmm2
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm3 = xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm1, %ymm1
+; AVX1-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX1-NEXT:    vpunpckhwd {{.*#+}} xmm2 = xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; AVX1-NEXT:    vpmovzxwd {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX1-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX1-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vzeroupper
+; AVX1-NEXT:    retq
+;
+; AVX2NOBW-LABEL: test_divv_8i16_narrow:
+; AVX2NOBW:       # %bb.0:
+; AVX2NOBW-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vpsrlw $6, %xmm1, %xmm1
+; AVX2NOBW-NEXT:    vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vzeroupper
+; AVX2NOBW-NEXT:    retq
+;
+; AVX512BW-LABEL: test_divv_8i16_narrow:
+; AVX512BW:       # %bb.0:
+; AVX512BW-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; AVX512BW-NEXT:    vpsrlw $6, %xmm1, %xmm1
+; AVX512BW-NEXT:    vpmovzxwd {{.*#+}} ymm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX512BW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX512BW-NEXT:    vpmovzxwd {{.*#+}} ymm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX512BW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX512BW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX512BW-NEXT:    vpmovdw %zmm0, %ymm0
+; AVX512BW-NEXT:    # kill: def $xmm0 killed $xmm0 killed $ymm0
+; AVX512BW-NEXT:    vzeroupper
+; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_8i16_narrow:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpsrlw $6, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpsrlw $6, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vcvtuw2ph %xmm1, %xmm1
+; AVX512FP16-NEXT:    vcvtuw2ph %xmm0, %xmm0
+; AVX512FP16-NEXT:    vdivph %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vcvttph2uw %xmm0, %xmm0
+; AVX512FP16-NEXT:    retq
+  %aa = lshr <8 x i16> %a, splat (i16 6)
+  %bb = lshr <8 x i16> %b, splat (i16 6)
+  %res = udiv <8 x i16> %aa, %bb
+  ret <8 x i16> %res
+}
+
+define <4 x i8> @test_divv_4i8(<4 x i8> %a, <4 x i8> %b) nounwind {
+; SSE2-LABEL: test_divv_4i8:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    pxor %xmm2, %xmm2
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSE2-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE2-NEXT:    divps %xmm1, %xmm0
+; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT:    packuswb %xmm0, %xmm0
+; SSE2-NEXT:    packuswb %xmm0, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: test_divv_4i8:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; SSE41-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; SSE41-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE41-NEXT:    divps %xmm1, %xmm0
+; SSE41-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE41-NEXT:    packusdw %xmm0, %xmm0
+; SSE41-NEXT:    packuswb %xmm0, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX-LABEL: test_divv_4i8:
+; AVX:       # %bb.0:
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; AVX-NEXT:    vcvtdq2ps %xmm1, %xmm1
+; AVX-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX-NEXT:    vcvtdq2ps %xmm0, %xmm0
+; AVX-NEXT:    vdivps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vcvttps2dq %xmm0, %xmm0
+; AVX-NEXT:    vpackusdw %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    vpackuswb %xmm0, %xmm0, %xmm0
+; AVX-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_4i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX512FP16-NEXT:    vcvtw2ph %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX512FP16-NEXT:    vcvtw2ph %xmm0, %xmm0
+; AVX512FP16-NEXT:    vdivph %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vcvttph2uw %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovwb %xmm0, %xmm0
+; AVX512FP16-NEXT:    retq
+  %res = udiv <4 x i8> %a, %b
+  ret <4 x i8> %res
+}
+
+define <8 x i8> @test_divv_8i8(<8 x i8> %a, <8 x i8> %b) nounwind {
+; SSE2-LABEL: test_divv_8i8:
+; SSE2:       # %bb.0:
+; SSE2-NEXT:    pxor %xmm2, %xmm2
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3],xmm1[4],xmm2[4],xmm1[5],xmm2[5],xmm1[6],xmm2[6],xmm1[7],xmm2[7]
+; SSE2-NEXT:    movdqa %xmm1, %xmm3
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm3 = xmm3[4],xmm2[4],xmm3[5],xmm2[5],xmm3[6],xmm2[6],xmm3[7],xmm2[7]
+; SSE2-NEXT:    cvtdq2ps %xmm3, %xmm3
+; SSE2-NEXT:    punpcklbw {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3],xmm0[4],xmm2[4],xmm0[5],xmm2[5],xmm0[6],xmm2[6],xmm0[7],xmm2[7]
+; SSE2-NEXT:    movdqa %xmm0, %xmm4
+; SSE2-NEXT:    punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm2[4],xmm4[5],xmm2[5],xmm4[6],xmm2[6],xmm4[7],xmm2[7]
+; SSE2-NEXT:    cvtdq2ps %xmm4, %xmm4
+; SSE2-NEXT:    divps %xmm3, %xmm4
+; SSE2-NEXT:    cvttps2dq %xmm4, %xmm3
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1],xmm1[2],xmm2[2],xmm1[3],xmm2[3]
+; SSE2-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE2-NEXT:    punpcklwd {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1],xmm0[2],xmm2[2],xmm0[3],xmm2[3]
+; SSE2-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE2-NEXT:    divps %xmm1, %xmm0
+; SSE2-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE2-NEXT:    packssdw %xmm3, %xmm0
+; SSE2-NEXT:    packuswb %xmm0, %xmm0
+; SSE2-NEXT:    retq
+;
+; SSE41-LABEL: test_divv_8i8:
+; SSE41:       # %bb.0:
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; SSE41-NEXT:    cvtdq2ps %xmm2, %xmm2
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm3 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; SSE41-NEXT:    cvtdq2ps %xmm3, %xmm3
+; SSE41-NEXT:    divps %xmm2, %xmm3
+; SSE41-NEXT:    cvttps2dq %xmm3, %xmm2
+; SSE41-NEXT:    pshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; SSE41-NEXT:    cvtdq2ps %xmm1, %xmm1
+; SSE41-NEXT:    pshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; SSE41-NEXT:    pmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; SSE41-NEXT:    cvtdq2ps %xmm0, %xmm0
+; SSE41-NEXT:    divps %xmm1, %xmm0
+; SSE41-NEXT:    cvttps2dq %xmm0, %xmm0
+; SSE41-NEXT:    packssdw %xmm0, %xmm2
+; SSE41-NEXT:    packuswb %xmm2, %xmm2
+; SSE41-NEXT:    movdqa %xmm2, %xmm0
+; SSE41-NEXT:    retq
+;
+; AVX1-LABEL: test_divv_8i8:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[1,1,1,1]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm2, %ymm1
+; AVX1-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm2 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[1,1,1,1]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm2, %ymm0
+; AVX1-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX1-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX1-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpackuswb %xmm0, %xmm0, %xmm0
+; AVX1-NEXT:    vzeroupper
+; AVX1-NEXT:    retq
+;
+; AVX2NOBW-LABEL: test_divv_8i8:
+; AVX2NOBW:       # %bb.0:
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vpackuswb %xmm0, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vzeroupper
+; AVX2NOBW-NEXT:    retq
+;
+; AVX512BW-LABEL: test_divv_8i8:
+; AVX512BW:       # %bb.0:
+; AVX512BW-NEXT:    vpmovzxbd {{.*#+}} ymm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
+; AVX512BW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX512BW-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; AVX512BW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX512BW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX512BW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX512BW-NEXT:    vpmovdb %zmm0, %xmm0
+; AVX512BW-NEXT:    vzeroupper
+; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_8i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} xmm1 = xmm1[0],zero,xmm1[1],zero,xmm1[2],zero,xmm1[3],zero,xmm1[4],zero,xmm1[5],zero,xmm1[6],zero,xmm1[7],zero
+; AVX512FP16-NEXT:    vcvtw2ph %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} xmm0 = xmm0[0],zero,xmm0[1],zero,xmm0[2],zero,xmm0[3],zero,xmm0[4],zero,xmm0[5],zero,xmm0[6],zero,xmm0[7],zero
+; AVX512FP16-NEXT:    vcvtw2ph %xmm0, %xmm0
+; AVX512FP16-NEXT:    vdivph %xmm1, %xmm0, %xmm0
+; AVX512FP16-NEXT:    vcvttph2uw %xmm0, %xmm0
+; AVX512FP16-NEXT:    vpmovwb %xmm0, %xmm0
+; AVX512FP16-NEXT:    retq
+  %res = udiv <8 x i8> %a, %b
+  ret <8 x i8> %res
+}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
index 7ca985872b875..38e183fe02b95 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-256.ll
@@ -2,6 +2,8 @@
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx | FileCheck %s --check-prefix=AVX1
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx2 | FileCheck %s --check-prefix=AVX2 --check-prefix=AVX2NOBW
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX2 --check-prefix=AVX512BW
+; RUN: llc < %s -mtriple=x86_64 -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
+; RUN: llc -mtriple=x86_64 -mattr=+avx512fp16 < %s | FileCheck %s --check-prefix=NO-FAST-FP16
 
 ;
 ; udiv by 7
@@ -214,6 +216,34 @@ define <32 x i8> @test_div7_32i8(<32 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsrlw $2, %ymm0, %ymm0
 ; AVX512BW-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_div7_32i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpsrlw $1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpsrlw $2, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_div7_32i8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpsrlw $1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpsrlw $2, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    retq
   %res = udiv <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <32 x i8> %res
 }
@@ -341,6 +371,42 @@ define <32 x i8> @test_divconstant_32i8(<32 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
 ; AVX512BW-NEXT:    vpmovwb %zmm0, %ymm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divconstant_32i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; AVX512FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [37,32,57,205,117,171,79,147,137,16,241,57,27,205,135,187,187,135,205,27,57,241,16,137,147,79,171,117,205,57,32,37]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [128,0,0,0,128,0,0,0,0,0,0,0,0,0,128,0,0,128,0,0,0,0,0,0,0,0,0,128,0,0,0,128]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; AVX512FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; AVX512FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_divconstant_32i8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; NO-FAST-FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [37,32,57,205,117,171,79,147,137,16,241,57,27,205,135,187,187,135,205,27,57,241,16,137,147,79,171,117,205,57,32,37]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [128,0,0,0,128,0,0,0,0,0,0,0,0,0,128,0,0,128,0,0,0,0,0,0,0,0,0,128,0,0,0,128]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; NO-FAST-FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; NO-FAST-FP16-NEXT:    retq
   %res = udiv <32 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
   ret <32 x i8> %res
 }
@@ -712,6 +778,42 @@ define <32 x i8> @test_rem7_32i8(<32 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
 ; AVX512BW-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_rem7_32i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm2
+; AVX512FP16-NEXT:    vpsrlw $1, %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpaddb %ymm1, %ymm2, %ymm1
+; AVX512FP16-NEXT:    vpaddw %ymm1, %ymm1, %ymm2
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm2
+; AVX512FP16-NEXT:    vpsrlw $2, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; AVX512FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_rem7_32i8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37,37]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm2
+; NO-FAST-FP16-NEXT:    vpsrlw $1, %ymm2, %ymm2
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; NO-FAST-FP16-NEXT:    vpaddb %ymm1, %ymm2, %ymm1
+; NO-FAST-FP16-NEXT:    vpaddw %ymm1, %ymm1, %ymm2
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm2, %ymm2
+; NO-FAST-FP16-NEXT:    vpsrlw $2, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm2, %ymm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    retq
   %res = urem <32 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <32 x i8> %res
 }
@@ -860,6 +962,46 @@ define <32 x i8> @test_remconstant_32i8(<32 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpmovwb %zmm1, %ymm1
 ; AVX512BW-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_remconstant_32i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; AVX512FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [37,32,57,205,117,171,79,147,137,16,241,57,27,205,135,187,187,135,205,27,57,241,16,137,147,79,171,117,205,57,32,37]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm2
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm2 = ymm2[0],zero,ymm2[1],zero,ymm2[2],zero,ymm2[3],zero,ymm2[4],zero,ymm2[5],zero,ymm2[6],zero,ymm2[7],zero,ymm2[8],zero,ymm2[9],zero,ymm2[10],zero,ymm2[11],zero,ymm2[12],zero,ymm2[13],zero,ymm2[14],zero,ymm2[15],zero,ymm2[16],zero,ymm2[17],zero,ymm2[18],zero,ymm2[19],zero,ymm2[20],zero,ymm2[21],zero,ymm2[22],zero,ymm2[23],zero,ymm2[24],zero,ymm2[25],zero,ymm2[26],zero,ymm2[27],zero,ymm2[28],zero,ymm2[29],zero,ymm2[30],zero,ymm2[31],zero
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2 # [128,0,0,0,128,0,0,0,0,0,0,0,0,0,128,0,0,128,0,0,0,0,0,0,0,0,0,128,0,0,0,128]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpmovwb %zmm2, %ymm2
+; AVX512FP16-NEXT:    vpaddb %ymm1, %ymm2, %ymm1
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
+; AVX512FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
+; AVX512FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; AVX512FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_remconstant_32i8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; NO-FAST-FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [37,32,57,205,117,171,79,147,137,16,241,57,27,205,135,187,187,135,205,27,57,241,16,137,147,79,171,117,205,57,32,37]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm2
+; NO-FAST-FP16-NEXT:    vpmovzxbw {{.*#+}} zmm2 = ymm2[0],zero,ymm2[1],zero,ymm2[2],zero,ymm2[3],zero,ymm2[4],zero,ymm2[5],zero,ymm2[6],zero,ymm2[7],zero,ymm2[8],zero,ymm2[9],zero,ymm2[10],zero,ymm2[11],zero,ymm2[12],zero,ymm2[13],zero,ymm2[14],zero,ymm2[15],zero,ymm2[16],zero,ymm2[17],zero,ymm2[18],zero,ymm2[19],zero,ymm2[20],zero,ymm2[21],zero,ymm2[22],zero,ymm2[23],zero,ymm2[24],zero,ymm2[25],zero,ymm2[26],zero,ymm2[27],zero,ymm2[28],zero,ymm2[29],zero,ymm2[30],zero,ymm2[31],zero
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2 # [128,0,0,0,128,0,0,0,0,0,0,0,0,0,128,0,0,128,0,0,0,0,0,0,0,0,0,128,0,0,0,128]
+; NO-FAST-FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm2, %ymm2
+; NO-FAST-FP16-NEXT:    vpaddb %ymm1, %ymm2, %ymm1
+; NO-FAST-FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
+; NO-FAST-FP16-NEXT:    vpsrlvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
+; NO-FAST-FP16-NEXT:    vpmovwb %zmm1, %ymm1
+; NO-FAST-FP16-NEXT:    vpsubb %ymm1, %ymm0, %ymm0
+; NO-FAST-FP16-NEXT:    retq
   %res = urem <32 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
   ret <32 x i8> %res
 }
@@ -961,3 +1103,282 @@ define <8 x i32> @test_remv_8i32(<8 x i32> %a, <8 x i32> %b) nounwind {
   %res = urem <8 x i32> %a, %b
   ret <8 x i32> %res
 }
+
+define <32 x i8> @test_udiv_32i8_fast_fp16(<32 x i8> %a, <32 x i8> %b) nounwind {
+; AVX1-LABEL: test_udiv_32i8_fast_fp16:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vextractf128 $1, %ymm1, %xmm2
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm3 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero,xmm2[2],zero,zero,zero,xmm2[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm2[1,1,1,1]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm3, %ymm3
+; AVX1-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm4
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm5 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm6 = xmm4[1,1,1,1]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm6 = xmm6[0],zero,zero,zero,xmm6[1],zero,zero,zero,xmm6[2],zero,zero,zero,xmm6[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm6, %ymm5, %ymm5
+; AVX1-NEXT:    vcvtdq2ps %ymm5, %ymm5
+; AVX1-NEXT:    vdivps %ymm3, %ymm5, %ymm3
+; AVX1-NEXT:    vcvttps2dq %ymm3, %ymm3
+; AVX1-NEXT:    vextractf128 $1, %ymm3, %xmm5
+; AVX1-NEXT:    vpackssdw %xmm5, %xmm3, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm5 = xmm2[2,3,2,3]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm5 = xmm5[0],zero,zero,zero,xmm5[1],zero,zero,zero,xmm5[2],zero,zero,zero,xmm5[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[3,3,3,3]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero,xmm2[2],zero,zero,zero,xmm2[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm5, %ymm2
+; AVX1-NEXT:    vcvtdq2ps %ymm2, %ymm2
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm5 = xmm4[2,3,2,3]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm5 = xmm5[0],zero,zero,zero,xmm5[1],zero,zero,zero,xmm5[2],zero,zero,zero,xmm5[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[3,3,3,3]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm5, %ymm4
+; AVX1-NEXT:    vcvtdq2ps %ymm4, %ymm4
+; AVX1-NEXT:    vdivps %ymm2, %ymm4, %ymm2
+; AVX1-NEXT:    vcvttps2dq %ymm2, %ymm2
+; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm4
+; AVX1-NEXT:    vpackssdw %xmm4, %xmm2, %xmm2
+; AVX1-NEXT:    vpackuswb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm3 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm1[1,1,1,1]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm3, %ymm3
+; AVX1-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm4 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm5 = xmm0[1,1,1,1]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm5 = xmm5[0],zero,zero,zero,xmm5[1],zero,zero,zero,xmm5[2],zero,zero,zero,xmm5[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm5, %ymm4, %ymm4
+; AVX1-NEXT:    vcvtdq2ps %ymm4, %ymm4
+; AVX1-NEXT:    vdivps %ymm3, %ymm4, %ymm3
+; AVX1-NEXT:    vcvttps2dq %ymm3, %ymm3
+; AVX1-NEXT:    vextractf128 $1, %ymm3, %xmm4
+; AVX1-NEXT:    vpackssdw %xmm4, %xmm3, %xmm3
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm1[2,3,2,3]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[3,3,3,3]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm4, %ymm1
+; AVX1-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm4 = xmm0[2,3,2,3]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero
+; AVX1-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm4, %ymm0
+; AVX1-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX1-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX1-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpackuswb %xmm0, %xmm3, %xmm0
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm0, %ymm0
+; AVX1-NEXT:    retq
+;
+; AVX2NOBW-LABEL: test_udiv_32i8_fast_fp16:
+; AVX2NOBW:       # %bb.0:
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm1, %xmm2
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm3 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero,xmm2[2],zero,zero,zero,xmm2[3],zero,zero,zero,xmm2[4],zero,zero,zero,xmm2[5],zero,zero,zero,xmm2[6],zero,zero,zero,xmm2[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm4
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm5 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero,xmm4[4],zero,zero,zero,xmm4[5],zero,zero,zero,xmm4[6],zero,zero,zero,xmm4[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm5, %ymm5
+; AVX2NOBW-NEXT:    vdivps %ymm3, %ymm5, %ymm3
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm3, %ymm3
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm3, %xmm5
+; AVX2NOBW-NEXT:    vpackssdw %xmm5, %xmm3, %xmm3
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm5 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm5, %ymm5
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm6 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm6, %ymm6
+; AVX2NOBW-NEXT:    vdivps %ymm5, %ymm6, %ymm5
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm5, %ymm5
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm5, %xmm6
+; AVX2NOBW-NEXT:    vpackssdw %xmm6, %xmm5, %xmm5
+; AVX2NOBW-NEXT:    vinserti128 $1, %xmm3, %ymm5, %ymm3
+; AVX2NOBW-NEXT:    vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3]
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm2 = xmm2[0],zero,zero,zero,xmm2[1],zero,zero,zero,xmm2[2],zero,zero,zero,xmm2[3],zero,zero,zero,xmm2[4],zero,zero,zero,xmm2[5],zero,zero,zero,xmm2[6],zero,zero,zero,xmm2[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm2, %ymm2
+; AVX2NOBW-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[2,3,2,3]
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm4 = xmm4[0],zero,zero,zero,xmm4[1],zero,zero,zero,xmm4[2],zero,zero,zero,xmm4[3],zero,zero,zero,xmm4[4],zero,zero,zero,xmm4[5],zero,zero,zero,xmm4[6],zero,zero,zero,xmm4[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm4, %ymm4
+; AVX2NOBW-NEXT:    vdivps %ymm2, %ymm4, %ymm2
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm2, %ymm2
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm2, %xmm4
+; AVX2NOBW-NEXT:    vpackssdw %xmm4, %xmm2, %xmm2
+; AVX2NOBW-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[2,3,2,3]
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vdivps %ymm1, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm1
+; AVX2NOBW-NEXT:    vpackssdw %xmm1, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vinserti128 $1, %xmm2, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vpackuswb %ymm0, %ymm3, %ymm0
+; AVX2NOBW-NEXT:    retq
+;
+; AVX512BW-LABEL: test_udiv_32i8_fast_fp16:
+; AVX512BW:       # %bb.0:
+; AVX512BW-NEXT:    vpmovzxbd {{.*#+}} zmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
+; AVX512BW-NEXT:    vcvtdq2ps %zmm2, %zmm2
+; AVX512BW-NEXT:    vpmovzxbd {{.*#+}} zmm3 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
+; AVX512BW-NEXT:    vcvtdq2ps %zmm3, %zmm3
+; AVX512BW-NEXT:    vdivps %zmm2, %zmm3, %zmm2
+; AVX512BW-NEXT:    vcvttps2dq %zmm2, %zmm2
+; AVX512BW-NEXT:    vpmovdb %zmm2, %xmm2
+; AVX512BW-NEXT:    vextracti128 $1, %ymm1, %xmm1
+; AVX512BW-NEXT:    vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
+; AVX512BW-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; AVX512BW-NEXT:    vextracti128 $1, %ymm0, %xmm0
+; AVX512BW-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
+; AVX512BW-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; AVX512BW-NEXT:    vdivps %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT:    vcvttps2dq %zmm0, %zmm0
+; AVX512BW-NEXT:    vpmovdb %zmm0, %xmm0
+; AVX512BW-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm0
+; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_udiv_32i8_fast_fp16:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero,ymm1[8],zero,ymm1[9],zero,ymm1[10],zero,ymm1[11],zero,ymm1[12],zero,ymm1[13],zero,ymm1[14],zero,ymm1[15],zero,ymm1[16],zero,ymm1[17],zero,ymm1[18],zero,ymm1[19],zero,ymm1[20],zero,ymm1[21],zero,ymm1[22],zero,ymm1[23],zero,ymm1[24],zero,ymm1[25],zero,ymm1[26],zero,ymm1[27],zero,ymm1[28],zero,ymm1[29],zero,ymm1[30],zero,ymm1[31],zero
+; AVX512FP16-NEXT:    vcvtw2ph %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} zmm0 = ymm0[0],zero,ymm0[1],zero,ymm0[2],zero,ymm0[3],zero,ymm0[4],zero,ymm0[5],zero,ymm0[6],zero,ymm0[7],zero,ymm0[8],zero,ymm0[9],zero,ymm0[10],zero,ymm0[11],zero,ymm0[12],zero,ymm0[13],zero,ymm0[14],zero,ymm0[15],zero,ymm0[16],zero,ymm0[17],zero,ymm0[18],zero,ymm0[19],zero,ymm0[20],zero,ymm0[21],zero,ymm0[22],zero,ymm0[23],zero,ymm0[24],zero,ymm0[25],zero,ymm0[26],zero,ymm0[27],zero,ymm0[28],zero,ymm0[29],zero,ymm0[30],zero,ymm0[31],zero
+; AVX512FP16-NEXT:    vcvtw2ph %zmm0, %zmm0
+; AVX512FP16-NEXT:    vdivph %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vcvttph2uw %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpmovwb %zmm0, %ymm0
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_udiv_32i8_fast_fp16:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovzxbd {{.*#+}} zmm2 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm2, %zmm2
+; NO-FAST-FP16-NEXT:    vpmovzxbd {{.*#+}} zmm3 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm3, %zmm3
+; NO-FAST-FP16-NEXT:    vdivps %zmm2, %zmm3, %zmm2
+; NO-FAST-FP16-NEXT:    vcvttps2dq %zmm2, %zmm2
+; NO-FAST-FP16-NEXT:    vpmovdb %zmm2, %xmm2
+; NO-FAST-FP16-NEXT:    vextracti128 $1, %ymm1, %xmm1
+; NO-FAST-FP16-NEXT:    vpmovzxbd {{.*#+}} zmm1 = xmm1[0],zero,zero,zero,xmm1[1],zero,zero,zero,xmm1[2],zero,zero,zero,xmm1[3],zero,zero,zero,xmm1[4],zero,zero,zero,xmm1[5],zero,zero,zero,xmm1[6],zero,zero,zero,xmm1[7],zero,zero,zero,xmm1[8],zero,zero,zero,xmm1[9],zero,zero,zero,xmm1[10],zero,zero,zero,xmm1[11],zero,zero,zero,xmm1[12],zero,zero,zero,xmm1[13],zero,zero,zero,xmm1[14],zero,zero,zero,xmm1[15],zero,zero,zero
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vextracti128 $1, %ymm0, %xmm0
+; NO-FAST-FP16-NEXT:    vpmovzxbd {{.*#+}} zmm0 = xmm0[0],zero,zero,zero,xmm0[1],zero,zero,zero,xmm0[2],zero,zero,zero,xmm0[3],zero,zero,zero,xmm0[4],zero,zero,zero,xmm0[5],zero,zero,zero,xmm0[6],zero,zero,zero,xmm0[7],zero,zero,zero,xmm0[8],zero,zero,zero,xmm0[9],zero,zero,zero,xmm0[10],zero,zero,zero,xmm0[11],zero,zero,zero,xmm0[12],zero,zero,zero,xmm0[13],zero,zero,zero,xmm0[14],zero,zero,zero,xmm0[15],zero,zero,zero
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vdivps %zmm1, %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vcvttps2dq %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpmovdb %zmm0, %xmm0
+; NO-FAST-FP16-NEXT:    vinserti128 $1, %xmm0, %ymm2, %ymm0
+; NO-FAST-FP16-NEXT:    retq
+
+
+%res = udiv <32 x i8> %a, %b
+ret <32 x i8> %res
+}
+
+define void @test_divv_16i16_zext8(ptr %dst, ptr %x, ptr %y) nounwind {
+; AVX1-LABEL: test_divv_16i16_zext8:
+; AVX1:       # %bb.0:
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm2 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm3 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm4 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm5 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm6 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vpmovzxbd {{.*#+}} xmm7 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero
+; AVX1-NEXT:    vinsertf128 $1, %xmm6, %ymm7, %ymm6
+; AVX1-NEXT:    vcvtdq2ps %ymm6, %ymm6
+; AVX1-NEXT:    vinsertf128 $1, %xmm2, %ymm3, %ymm2
+; AVX1-NEXT:    vcvtdq2ps %ymm2, %ymm2
+; AVX1-NEXT:    vdivps %ymm6, %ymm2, %ymm2
+; AVX1-NEXT:    vcvttps2dq %ymm2, %ymm2
+; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm3
+; AVX1-NEXT:    vpackusdw %xmm3, %xmm2, %xmm2
+; AVX1-NEXT:    vinsertf128 $1, %xmm4, %ymm5, %ymm3
+; AVX1-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm1, %ymm0
+; AVX1-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX1-NEXT:    vdivps %ymm3, %ymm0, %ymm0
+; AVX1-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX1-NEXT:    vextractf128 $1, %ymm0, %xmm1
+; AVX1-NEXT:    vpackusdw %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vbroadcastss {{.*#+}} xmm1 = [255,255,255,255,255,255,255,255]
+; AVX1-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpand %xmm1, %xmm2, %xmm1
+; AVX1-NEXT:    vpackuswb %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vmovdqa %xmm0, (%rdi)
+; AVX1-NEXT:    vzeroupper
+; AVX1-NEXT:    retq
+;
+; AVX2NOBW-LABEL: test_divv_16i16_zext8:
+; AVX2NOBW:       # %bb.0:
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm2 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vpmovzxbd {{.*#+}} ymm3 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm3, %ymm3
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vdivps %ymm3, %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm1, %ymm1
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm1, %xmm3
+; AVX2NOBW-NEXT:    vpackusdw %xmm3, %xmm1, %xmm1
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm2, %ymm2
+; AVX2NOBW-NEXT:    vcvtdq2ps %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vdivps %ymm2, %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vcvttps2dq %ymm0, %ymm0
+; AVX2NOBW-NEXT:    vextracti128 $1, %ymm0, %xmm2
+; AVX2NOBW-NEXT:    vpackusdw %xmm2, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vpbroadcastw {{.*#+}} xmm2 = [255,255,255,255,255,255,255,255]
+; AVX2NOBW-NEXT:    vpand %xmm2, %xmm0, %xmm0
+; AVX2NOBW-NEXT:    vpand %xmm2, %xmm1, %xmm1
+; AVX2NOBW-NEXT:    vpackuswb %xmm0, %xmm1, %xmm0
+; AVX2NOBW-NEXT:    vmovdqa %xmm0, (%rdi)
+; AVX2NOBW-NEXT:    vzeroupper
+; AVX2NOBW-NEXT:    retq
+;
+; AVX512BW-LABEL: test_divv_16i16_zext8:
+; AVX512BW:       # %bb.0:
+; AVX512BW-NEXT:    vpmovzxbd {{.*#+}} zmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero,mem[8],zero,zero,zero,mem[9],zero,zero,zero,mem[10],zero,zero,zero,mem[11],zero,zero,zero,mem[12],zero,zero,zero,mem[13],zero,zero,zero,mem[14],zero,zero,zero,mem[15],zero,zero,zero
+; AVX512BW-NEXT:    vpmovzxbd {{.*#+}} zmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero,mem[8],zero,zero,zero,mem[9],zero,zero,zero,mem[10],zero,zero,zero,mem[11],zero,zero,zero,mem[12],zero,zero,zero,mem[13],zero,zero,zero,mem[14],zero,zero,zero,mem[15],zero,zero,zero
+; AVX512BW-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; AVX512BW-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; AVX512BW-NEXT:    vdivps %zmm1, %zmm0, %zmm0
+; AVX512BW-NEXT:    vcvttps2udq %zmm0, %zmm0
+; AVX512BW-NEXT:    vpmovdb %zmm0, (%rdi)
+; AVX512BW-NEXT:    vzeroupper
+; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divv_16i16_zext8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm0 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
+; AVX512FP16-NEXT:    vpmovzxbw {{.*#+}} ymm1 = mem[0],zero,mem[1],zero,mem[2],zero,mem[3],zero,mem[4],zero,mem[5],zero,mem[6],zero,mem[7],zero,mem[8],zero,mem[9],zero,mem[10],zero,mem[11],zero,mem[12],zero,mem[13],zero,mem[14],zero,mem[15],zero
+; AVX512FP16-NEXT:    vcvtuw2ph %ymm1, %ymm1
+; AVX512FP16-NEXT:    vcvtuw2ph %ymm0, %ymm0
+; AVX512FP16-NEXT:    vdivph %ymm1, %ymm0, %ymm0
+; AVX512FP16-NEXT:    vcvttph2uw %ymm0, %ymm0
+; AVX512FP16-NEXT:    vpmovwb %ymm0, (%rdi)
+; AVX512FP16-NEXT:    vzeroupper
+; AVX512FP16-NEXT:    retq
+;
+; NO-FAST-FP16-LABEL: test_divv_16i16_zext8:
+; NO-FAST-FP16:       # %bb.0:
+; NO-FAST-FP16-NEXT:    vpmovzxbd {{.*#+}} zmm0 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero,mem[8],zero,zero,zero,mem[9],zero,zero,zero,mem[10],zero,zero,zero,mem[11],zero,zero,zero,mem[12],zero,zero,zero,mem[13],zero,zero,zero,mem[14],zero,zero,zero,mem[15],zero,zero,zero
+; NO-FAST-FP16-NEXT:    vpmovzxbd {{.*#+}} zmm1 = mem[0],zero,zero,zero,mem[1],zero,zero,zero,mem[2],zero,zero,zero,mem[3],zero,zero,zero,mem[4],zero,zero,zero,mem[5],zero,zero,zero,mem[6],zero,zero,zero,mem[7],zero,zero,zero,mem[8],zero,zero,zero,mem[9],zero,zero,zero,mem[10],zero,zero,zero,mem[11],zero,zero,zero,mem[12],zero,zero,zero,mem[13],zero,zero,zero,mem[14],zero,zero,zero,mem[15],zero,zero,zero
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm1, %zmm1
+; NO-FAST-FP16-NEXT:    vcvtdq2ps %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vdivps %zmm1, %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vcvttps2udq %zmm0, %zmm0
+; NO-FAST-FP16-NEXT:    vpmovdb %zmm0, (%rdi)
+; NO-FAST-FP16-NEXT:    vzeroupper
+; NO-FAST-FP16-NEXT:    retq
+  %a8 = load <16 x i8>, ptr %x
+  %a = zext <16 x i8> %a8 to <16 x i16>
+  %b8 = load <16 x i8>, ptr %y
+  %b = zext <16 x i8> %b8 to <16 x i16>
+  %res = udiv <16 x i16> %a, %b
+  %t = trunc <16 x i16> %res to <16 x i8>
+  store <16 x i8> %t, ptr %dst
+  ret void
+}
diff --git a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
index 8da79b46a0baf..a68ece6ca3544 100644
--- a/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
+++ b/llvm/test/CodeGen/X86/vector-idiv-udiv-512.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512f | FileCheck %s --check-prefix=AVX --check-prefix=AVX512F
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw | FileCheck %s --check-prefix=AVX --check-prefix=AVX512BW
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512fp16,+avx512vl,+fast-vector-fp16-div | FileCheck %s --check-prefix=AVX512FP16
 
 ;
 ; udiv by 7
@@ -134,6 +135,25 @@ define <64 x i8> @test_div7_64i8(<64 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsrlw $2, %zmm0, %zmm0
 ; AVX512BW-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_div7_64i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
+; AVX512FP16-NEXT:    vpbroadcastw {{.*#+}} zmm3 = [37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0]
+; AVX512FP16-NEXT:    vpmullw %zmm3, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm1 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
+; AVX512FP16-NEXT:    vpmullw %zmm3, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpsrlw $1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpsrlw $2, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm0, %zmm0
+; AVX512FP16-NEXT:    retq
   %res = udiv <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <64 x i8> %res
 }
@@ -235,6 +255,38 @@ define <64 x i8> @test_divconstant_64i8(<64 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsrlw $8, %zmm0, %zmm0
 ; AVX512BW-NEXT:    vpackuswb %zmm2, %zmm0, %zmm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_divconstant_64i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2 # [137,0,16,0,241,0,57,0,27,0,205,0,135,0,187,0,9,0,8,0,249,0,241,0,235,0,57,0,111,0,27,0,137,0,27,0,37,0,19,0,79,0,41,0,171,0,101,0,147,0,79,0,171,0,117,0,205,0,57,0,32,0,37,0]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm3 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3 # [37,0,32,0,57,0,205,0,117,0,171,0,79,0,147,0,101,0,171,0,41,0,79,0,19,0,37,0,27,0,137,0,27,0,111,0,57,0,235,0,241,0,249,0,8,0,9,0,187,0,135,0,205,0,27,0,57,0,241,0,16,0,137,0]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm3, %zmm2
+; AVX512FP16-NEXT:    vpsubb %zmm2, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm3 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3 # [0,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0 # [128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpackuswb %zmm3, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpaddb %zmm2, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm0 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm0, %zmm0
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm0, %zmm0
+; AVX512FP16-NEXT:    retq
   %res = udiv <64 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
   ret <64 x i8> %res
 }
@@ -424,6 +476,29 @@ define <64 x i8> @test_rem7_64i8(<64 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpsubb %zmm2, %zmm1, %zmm1
 ; AVX512BW-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_rem7_64i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
+; AVX512FP16-NEXT:    vpbroadcastw {{.*#+}} zmm3 = [37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0,37,0]
+; AVX512FP16-NEXT:    vpmullw %zmm3, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm1 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
+; AVX512FP16-NEXT:    vpmullw %zmm3, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsubb %zmm1, %zmm0, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $1, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpaddb %zmm1, %zmm2, %zmm1
+; AVX512FP16-NEXT:    vpaddw %zmm1, %zmm1, %zmm2
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpandd {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to16}, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsubb %zmm2, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    retq
   %res = urem <64 x i8> %a, <i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7, i8 7,i8 7, i8 7, i8 7, i8 7>
   ret <64 x i8> %res
 }
@@ -543,6 +618,43 @@ define <64 x i8> @test_remconstant_64i8(<64 x i8> %a) nounwind {
 ; AVX512BW-NEXT:    vpternlogd {{.*#+}} zmm1 = zmm1 | (zmm2 & m32bcst)
 ; AVX512BW-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
 ; AVX512BW-NEXT:    retq
+;
+; AVX512FP16-LABEL: test_remconstant_64i8:
+; AVX512FP16:       # %bb.0:
+; AVX512FP16-NEXT:    vpxor %xmm1, %xmm1, %xmm1
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm2 = zmm0[8],zmm1[8],zmm0[9],zmm1[9],zmm0[10],zmm1[10],zmm0[11],zmm1[11],zmm0[12],zmm1[12],zmm0[13],zmm1[13],zmm0[14],zmm1[14],zmm0[15],zmm1[15],zmm0[24],zmm1[24],zmm0[25],zmm1[25],zmm0[26],zmm1[26],zmm0[27],zmm1[27],zmm0[28],zmm1[28],zmm0[29],zmm1[29],zmm0[30],zmm1[30],zmm0[31],zmm1[31],zmm0[40],zmm1[40],zmm0[41],zmm1[41],zmm0[42],zmm1[42],zmm0[43],zmm1[43],zmm0[44],zmm1[44],zmm0[45],zmm1[45],zmm0[46],zmm1[46],zmm0[47],zmm1[47],zmm0[56],zmm1[56],zmm0[57],zmm1[57],zmm0[58],zmm1[58],zmm0[59],zmm1[59],zmm0[60],zmm1[60],zmm0[61],zmm1[61],zmm0[62],zmm1[62],zmm0[63],zmm1[63]
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm2, %zmm2 # [137,0,16,0,241,0,57,0,27,0,205,0,135,0,187,0,9,0,8,0,249,0,241,0,235,0,57,0,111,0,27,0,137,0,27,0,37,0,19,0,79,0,41,0,171,0,101,0,147,0,79,0,171,0,117,0,205,0,57,0,32,0,37,0]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm2, %zmm2
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm3 = zmm0[0],zmm1[0],zmm0[1],zmm1[1],zmm0[2],zmm1[2],zmm0[3],zmm1[3],zmm0[4],zmm1[4],zmm0[5],zmm1[5],zmm0[6],zmm1[6],zmm0[7],zmm1[7],zmm0[16],zmm1[16],zmm0[17],zmm1[17],zmm0[18],zmm1[18],zmm0[19],zmm1[19],zmm0[20],zmm1[20],zmm0[21],zmm1[21],zmm0[22],zmm1[22],zmm0[23],zmm1[23],zmm0[32],zmm1[32],zmm0[33],zmm1[33],zmm0[34],zmm1[34],zmm0[35],zmm1[35],zmm0[36],zmm1[36],zmm0[37],zmm1[37],zmm0[38],zmm1[38],zmm0[39],zmm1[39],zmm0[48],zmm1[48],zmm0[49],zmm1[49],zmm0[50],zmm1[50],zmm0[51],zmm1[51],zmm0[52],zmm1[52],zmm0[53],zmm1[53],zmm0[54],zmm1[54],zmm0[55],zmm1[55]
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3 # [37,0,32,0,57,0,205,0,117,0,171,0,79,0,147,0,101,0,171,0,41,0,79,0,19,0,37,0,27,0,137,0,27,0,111,0,57,0,235,0,241,0,249,0,8,0,9,0,187,0,135,0,205,0,27,0,57,0,241,0,16,0,137,0]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpackuswb %zmm2, %zmm3, %zmm2
+; AVX512FP16-NEXT:    vpsubb %zmm2, %zmm0, %zmm3
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm4 = zmm3[8],zmm1[8],zmm3[9],zmm1[9],zmm3[10],zmm1[10],zmm3[11],zmm1[11],zmm3[12],zmm1[12],zmm3[13],zmm1[13],zmm3[14],zmm1[14],zmm3[15],zmm1[15],zmm3[24],zmm1[24],zmm3[25],zmm1[25],zmm3[26],zmm1[26],zmm3[27],zmm1[27],zmm3[28],zmm1[28],zmm3[29],zmm1[29],zmm3[30],zmm1[30],zmm3[31],zmm1[31],zmm3[40],zmm1[40],zmm3[41],zmm1[41],zmm3[42],zmm1[42],zmm3[43],zmm1[43],zmm3[44],zmm1[44],zmm3[45],zmm1[45],zmm3[46],zmm1[46],zmm3[47],zmm1[47],zmm3[56],zmm1[56],zmm3[57],zmm1[57],zmm3[58],zmm1[58],zmm3[59],zmm1[59],zmm3[60],zmm1[60],zmm3[61],zmm1[61],zmm3[62],zmm1[62],zmm3[63],zmm1[63]
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm4, %zmm4 # [0,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm4, %zmm4
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm3 = zmm3[0],zmm1[0],zmm3[1],zmm1[1],zmm3[2],zmm1[2],zmm3[3],zmm1[3],zmm3[4],zmm1[4],zmm3[5],zmm1[5],zmm3[6],zmm1[6],zmm3[7],zmm1[7],zmm3[16],zmm1[16],zmm3[17],zmm1[17],zmm3[18],zmm1[18],zmm3[19],zmm1[19],zmm3[20],zmm1[20],zmm3[21],zmm1[21],zmm3[22],zmm1[22],zmm3[23],zmm1[23],zmm3[32],zmm1[32],zmm3[33],zmm1[33],zmm3[34],zmm1[34],zmm3[35],zmm1[35],zmm3[36],zmm1[36],zmm3[37],zmm1[37],zmm3[38],zmm1[38],zmm3[39],zmm1[39],zmm3[48],zmm1[48],zmm3[49],zmm1[49],zmm3[50],zmm1[50],zmm3[51],zmm1[51],zmm3[52],zmm1[52],zmm3[53],zmm1[53],zmm3[54],zmm1[54],zmm3[55],zmm1[55]
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3 # [128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,128,0,0,0,128,0,0,0,0,0,0,0,0,0,0,0,0,0]
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpackuswb %zmm4, %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpaddb %zmm2, %zmm3, %zmm2
+; AVX512FP16-NEXT:    vpunpckhbw {{.*#+}} zmm3 = zmm2[8],zmm1[8],zmm2[9],zmm1[9],zmm2[10],zmm1[10],zmm2[11],zmm1[11],zmm2[12],zmm1[12],zmm2[13],zmm1[13],zmm2[14],zmm1[14],zmm2[15],zmm1[15],zmm2[24],zmm1[24],zmm2[25],zmm1[25],zmm2[26],zmm1[26],zmm2[27],zmm1[27],zmm2[28],zmm1[28],zmm2[29],zmm1[29],zmm2[30],zmm1[30],zmm2[31],zmm1[31],zmm2[40],zmm1[40],zmm2[41],zmm1[41],zmm2[42],zmm1[42],zmm2[43],zmm1[43],zmm2[44],zmm1[44],zmm2[45],zmm1[45],zmm2[46],zmm1[46],zmm2[47],zmm1[47],zmm2[56],zmm1[56],zmm2[57],zmm1[57],zmm2[58],zmm1[58],zmm2[59],zmm1[59],zmm2[60],zmm1[60],zmm2[61],zmm1[61],zmm2[62],zmm1[62],zmm2[63],zmm1[63]
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm3, %zmm3
+; AVX512FP16-NEXT:    vpunpcklbw {{.*#+}} zmm1 = zmm2[0],zmm1[0],zmm2[1],zmm1[1],zmm2[2],zmm1[2],zmm2[3],zmm1[3],zmm2[4],zmm1[4],zmm2[5],zmm1[5],zmm2[6],zmm1[6],zmm2[7],zmm1[7],zmm2[16],zmm1[16],zmm2[17],zmm1[17],zmm2[18],zmm1[18],zmm2[19],zmm1[19],zmm2[20],zmm1[20],zmm2[21],zmm1[21],zmm2[22],zmm1[22],zmm2[23],zmm1[23],zmm2[32],zmm1[32],zmm2[33],zmm1[33],zmm2[34],zmm1[34],zmm2[35],zmm1[35],zmm2[36],zmm1[36],zmm2[37],zmm1[37],zmm2[38],zmm1[38],zmm2[39],zmm1[39],zmm2[48],zmm1[48],zmm2[49],zmm1[49],zmm2[50],zmm1[50],zmm2[51],zmm1[51],zmm2[52],zmm1[52],zmm2[53],zmm1[53],zmm2[54],zmm1[54],zmm2[55],zmm1[55]
+; AVX512FP16-NEXT:    vpsllvw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpsrlw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpackuswb %zmm3, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm2 # [7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35,36,37,38,38,37,36,35,34,33,32,31,30,29,28,27,26,25,24,23,22,21,20,19,18,17,16,15,14,13,12,11,10,9,8,7]
+; AVX512FP16-NEXT:    vpmaddubsw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %zmm1, %zmm1 # [0,8,0,10,0,12,0,14,0,16,0,18,0,20,0,22,0,24,0,26,0,28,0,30,0,32,0,34,0,36,0,38,0,37,0,35,0,33,0,31,0,29,0,27,0,25,0,23,0,21,0,19,0,17,0,15,0,13,0,11,0,9,0,7]
+; AVX512FP16-NEXT:    vpsllw $8, %zmm1, %zmm1
+; AVX512FP16-NEXT:    vpternlogd {{.*#+}} zmm1 = zmm1 | (zmm2 & m32bcst)
+; AVX512FP16-NEXT:    vpsubb %zmm1, %zmm0, %zmm0
+; AVX512FP16-NEXT:    retq
   %res = urem <64 x i8> %a, <i8 7, i8 8, i8 9, i8 10, i8 11, i8 12, i8 13, i8 14, i8 15, i8 16, i8 17, i8 18, i8 19, i8 20, i8 21, i8 22, i8 23, i8 24, i8 25, i8 26, i8 27, i8 28, i8 29, i8 30, i8 31, i8 32, i8 33, i8 34, i8 35, i8 36, i8 37, i8 38, i8 38, i8 37, i8 36, i8 35, i8 34, i8 33, i8 32, i8 31, i8 30, i8 29, i8 28, i8 27, i8 26, i8 25, i8 24, i8 23, i8 22, i8 21, i8 20, i8 19, i8 18, i8 17, i8 16, i8 15, i8 14, i8 13, i8 12, i8 11, i8 10, i8 9, i8 8, i8 7>
   ret <64 x i8> %res
 }