Every hardware-level reference lives in this directory. Start with the chip architecture overview if you need the host/chip model, or jump to the cache-coherency and MMIO references when working on a data or notification path.
| Document | What it covers |
|---|---|
| Ascend Chip Architecture | Host, AICPU, and AICore execution tiers; chip generations; task flow; memory hierarchy |
| Cache Coherency | GM visibility across AICore, AICPU, DMA, and SDMA paths, including required barriers and cache operations |
| Document | What it covers |
|---|---|
| MMIO Performance | AIC control-register memory attributes, measured access costs, concurrency limits, and notification-channel tradeoffs |
| CANN Source References | Upstream driver, HCCL, and HCOMM source locations used to investigate hardware and communication behavior |
| Document | What it covers |
|---|---|
| Chip-Level Architecture | The three-program software model layered onto the host, AICPU, and AICore tiers |
| Task Flow | End-to-end callable, argument, and task flow across the execution tiers |
| AICore Kernel Programming | Kernel authoring rules for the compute tier described here |