Upgrade example deps and push v00x to use 48Mhz + 3Mbps baud rate (#30)

* update deps for v003 examples.

* update deps for v103 examples.

* update v00x examples and validate against OSC Dev V006 board. validated
at 48MHz / 3Mbps baud.

Author: aq1018

examples/ch32/v003/Cargo.lock

@@ -19,5 +19,5 @@ codegen-units = 1
 panic = "abort"
 
 [patch.crates-io]
-qingke = { git = "https://github.com/OpenServoCore/qingke", branch = "main" }
-qingke-rt = { git = "https://github.com/OpenServoCore/qingke", branch = "main" }
+qingke = { git = "https://github.com/ch32-rs/qingke", branch = "main" }
+qingke-rt = { git = "https://github.com/ch32-rs/qingke", branch = "main" }

examples/ch32/v003/Cargo.toml

@@ -8,7 +8,7 @@ tinyboot-ch32 = { path = "../../../../ch32", default-features = false }
 embedded-io = "0.7"
 critical-section = "1"
 ch32-hal = { git = "https://github.com/ch32-rs/ch32-hal", default-features = false }
-qingke-rt = { version = "0.6", features = ["v2"] }
+qingke-rt = { version = "0.7", features = ["v2"] }
 defmt = "1.0"
 defmt-rtt = "1.1"
 

examples/ch32/v003/app/Cargo.toml

@@ -20,5 +20,6 @@ codegen-units = 1
 panic = "abort"
 
 [patch.crates-io]
-qingke = { git = "https://github.com/OpenServoCore/qingke", branch = "main" }
-qingke-rt = { git = "https://github.com/OpenServoCore/qingke", branch = "main" }
+qingke = { git = "https://github.com/ch32-rs/qingke", branch = "main" }
+qingke-rt = { git = "https://github.com/ch32-rs/qingke", branch = "main" }
+

examples/ch32/v00x/Cargo.lock

@@ -7,8 +7,9 @@ edition.workspace = true
 tinyboot-ch32 = { path = "../../../../ch32", default-features = false }
 embedded-io = "0.7"
 critical-section = "1"
-ch32-hal = { git = "https://github.com/ch32-rs/ch32-hal", default-features = false }
-qingke-rt = { version = "0.6", features = ["v2"] }
+# See https://github.com/ch32-rs/ch32-hal/pull/169
+ch32-hal = { git = "https://github.com/ch32-rs/ch32-hal", branch = "fix/v00x-48mhz", default-features = false }
+qingke-rt = { version = "0.7", features = ["v2"] }
 defmt = "1.0"
 defmt-rtt = "1.1"
 

examples/ch32/v00x/Cargo.toml

@@ -11,7 +11,9 @@ fn main() {
         match (system_flash, user_flash) {
             (true, false) => "system-flash",
             (false, true) => "user-flash",
-            _ => panic!("Enable exactly one flash mode: `system-flash`, `user-flash`, or `standalone`"),
+            _ => panic!(
+                "Enable exactly one flash mode: `system-flash`, `user-flash`, or `standalone`"
+            ),
         }
     };
 

examples/ch32/v00x/app/Cargo.toml

@@ -34,7 +34,9 @@ static LED: Shared<Output<'static>> = Mutex::new(RefCell::new(None));
 
 #[qingke_rt::entry]
 fn main() -> ! {
-    let p = ch32_hal::init(Default::default());
+    let mut config = ch32_hal::Config::default();
+    config.rcc = ch32_hal::rcc::Config::SYSCLK_FREQ_48MHZ_HSI;
+    let p = ch32_hal::init(config);
 
     // LED blink via TIM2 interrupt (2 Hz toggle = 1 Hz blink)
     critical_section::with(|cs| {
@@ -54,7 +56,7 @@ fn main() -> ! {
     //   2: TX=PD0, RX=PD1
     //   3: TX=PC0, RX=PC1
     let mut uart_config = usart::Config::default();
-    uart_config.baudrate = 115200;
+    uart_config.baudrate = 3_000_000;
     let uart = Uart::new_blocking::<3>(p.USART1, p.PC1, p.PC0, uart_config).unwrap();
     let (tx, rx) = uart.split();
     let mut rx = transport::Rx(rx);

examples/ch32/v00x/app/build.rs

@@ -1,7 +1,13 @@
 //! embedded_io adapters for ch32-hal blocking UART with optional RS-485 DE/RE.
+//!
+//! RX bypasses ch32-hal's `blocking_read` and polls `STATR.RXNE` / `DATAR`
+//! directly — at 48 MHz with a 3 Mbps line, each byte arrives every ~160
+//! cycles and the per-byte overhead of `check_rx_flags` + the `embedded_io`
+//! adapter chain is enough to overrun.
 
 use ch32_hal::gpio::{Level, Output};
 use ch32_hal::mode::Blocking;
+use ch32_hal::pac;
 use ch32_hal::usart::{Instance, UartRx, UartTx};
 use core::convert::Infallible;
 use embedded_io::{ErrorType, Read, Write};
@@ -17,8 +23,12 @@ impl<T: Instance> Read for Rx<'_, T> {
         if buf.is_empty() {
             return Ok(0);
         }
-        let _ = self.0.blocking_read(&mut buf[..1]);
-        Ok(1)
+        let regs = pac::USART1;
+        for slot in buf.iter_mut() {
+            while !regs.statr().read().rxne() {}
+            *slot = regs.datar().read().dr() as u8;
+        }
+        Ok(buf.len())
     }
 }
 

examples/ch32/v00x/app/src/main.rs

@@ -13,9 +13,30 @@ use tinyboot_ch32_rt as _;
 tinyboot_ch32::boot::boot_version!();
 
 use tinyboot_ch32::boot::prelude::*;
+use tinyboot_ch32::pac::{
+    FLASH, RCC,
+    rcc::vals::{Hpre, Pllsrc, Sw},
+};
+
+fn init_48mhz_hsi_pll() {
+    FLASH.actlr().modify(|w| w.set_latency(2));
+
+    RCC.cfgr0().modify(|w| {
+        w.set_pllsrc(Pllsrc::HSI);
+        w.set_hpre(Hpre::DIV1);
+    });
+
+    RCC.ctlr().modify(|w| w.set_pllon(true));
+    while !RCC.ctlr().read().pllrdy() {}
+
+    RCC.cfgr0().modify(|w| w.set_sw(Sw::PLL));
+    while RCC.cfgr0().read().sws() != Sw::PLL {}
+}
 
 #[unsafe(export_name = "main")]
 fn main() -> ! {
+    init_48mhz_hsi_pll();
+
     // USART1 transport. Remap options (CH32V00x):
     //   Remap0 (default): TX=PD5, RX=PD6
     //   Remap1:           TX=PD6, RX=PD5
@@ -35,11 +56,14 @@ fn main() -> ! {
     //   tx_en: Some(TxEnConfig { pin: Pin::PC2, tx_level: Level::High }),
     let transport = Usart::new(&UsartConfig {
         duplex: Duplex::Full,
-        baud: BaudRate::B115200,
-        pclk: 8_000_000,
+        baud: BaudRate::B3000000,
+        pclk: 48_000_000,
         mapping: UsartMapping::Usart1Remap3,
         rx_pull: Pull::None,
-        tx_en: Some(TxEnConfig { pin: Pin::PC2, tx_level: Level::High }),
+        tx_en: Some(TxEnConfig {
+            pin: Pin::PC2,
+            tx_level: Level::High,
+        }),
     });
     tinyboot_ch32::boot::run(transport, BootCtl::new());
 }