diff --git a/avs/compiler/linx-llvm/tests/analyze_coverage.py b/avs/compiler/linx-llvm/tests/analyze_coverage.py
index ad8f9b4d..dd7b4e3b 100644
--- a/avs/compiler/linx-llvm/tests/analyze_coverage.py
+++ b/avs/compiler/linx-llvm/tests/analyze_coverage.py
@@ -75,19 +75,11 @@ def canonicalize_mnemonic(mnemonic: str) -> str:
 def derived_selector_mnemonics(mnemonic: str, operands: list[str]) -> Set[str]:
     """Recover strict current-profile aliases from selector-style objdump output."""
     selector = canonicalize_mnemonic(mnemonic)
-    if selector == "B.DATR":
-        return {"B.ARG"}
     if not operands:
         return set()
 
     tileop = canonicalize_mnemonic(operands[0])
     aliases = {
-        ("BSTART.CUBE", "ACCCVT"): "BSTART.ACCCVT",
-        ("BSTART.CUBE", "TMATMUL"): "BSTART.TMATMUL",
-        ("BSTART.CUBE", "TMATMUL.ACC"): "BSTART.TMATMUL.ACC",
-        ("BSTART.TMA", "TLOAD"): "BSTART.TLOAD",
-        ("BSTART.TMA", "TSTORE"): "BSTART.TSTORE",
-        ("BSTART.TMA", "TMOV"): "BSTART.TMOV",
         ("BSTART.TEPL", "ERCOV"): "ERCOV",
         ("BSTART.TEPL", "ESAVE"): "ESAVE",
     }
@@ -166,6 +158,13 @@ def map_emitted_to_spec(emitted_mnem: str, spec_mnemonics: Set[str]) -> Optional
         return None
     if cur in spec_mnemonics:
         return cur
+    # TEPL has one raw carrier form in the architectural catalog while the
+    # disassembler prints the selected direct operation (for example,
+    # BSTART.TDIVS).  Those friendly spellings are execution evidence for the
+    # BSTART.TEPL carrier, not for the unrelated generic BSTART form reached by
+    # suffix stripping.
+    if cur.startswith("BSTART.T") and "BSTART.TEPL" in spec_mnemonics:
+        return "BSTART.TEPL"
     while "." in cur:
         cur = cur.rsplit(".", 1)[0]
         if cur in spec_mnemonics:
diff --git a/avs/compiler/linx-llvm/tests/asm/41_v057_isa_forms.s b/avs/compiler/linx-llvm/tests/asm/41_v057_isa_forms.s
index 3a9a816d..334a49c4 100644
--- a/avs/compiler/linx-llvm/tests/asm/41_v057_isa_forms.s
+++ b/avs/compiler/linx-llvm/tests/asm/41_v057_isa_forms.s
@@ -1,11 +1,9 @@
 .text
 v057_isa_forms:
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.DIM sp, 129, ->lb1
     B.IOR [sp,sp,sp],[a0]
     BSTART.ACCCVT FP32
-    BSTART.CUBE 3, FP32
-    BSTART.FIXP 31, FP32
     BSTART.TLOAD FP32
     BSTART.TSTORE FP32
     BSTART.TMATMUL FP16
diff --git a/avs/compiler/linx-llvm/tests/c/32_descriptor_marker.c b/avs/compiler/linx-llvm/tests/c/32_descriptor_marker.c
index e1da71b0..dd804a6c 100644
--- a/avs/compiler/linx-llvm/tests/c/32_descriptor_marker.c
+++ b/avs/compiler/linx-llvm/tests/c/32_descriptor_marker.c
@@ -1,5 +1,5 @@
-// Emit a canonical B.ARG descriptor header opcode so mnemonic coverage includes
-// descriptor-only metadata instructions in strict v0.57.
-void emit_barg_marker(void) {
-  __asm__ volatile(".long 0x180221a3" ::: "memory");
+// Emit canonical B.DATR NORM/FP32/Zero defaults so mnemonic coverage includes
+// descriptor-only metadata instructions in strict v0.57.1.
+void emit_bdatr_marker(void) {
+  __asm__ volatile(".long 0x00001023" ::: "memory");
 }
diff --git a/avs/compiler/linx-llvm/tests/gen_disasm_vectors.py b/avs/compiler/linx-llvm/tests/gen_disasm_vectors.py
index 21004978..de75a43f 100644
--- a/avs/compiler/linx-llvm/tests/gen_disasm_vectors.py
+++ b/avs/compiler/linx-llvm/tests/gen_disasm_vectors.py
@@ -47,7 +47,23 @@ def _field_width(field: dict[str, object]) -> int:
 def _default_field_value(field_name: str, width: int, mnemonic: str) -> int:
     lower = field_name.lower()
     upper_mnemonic = mnemonic.upper()
-    if width > 5:
+    frame_template = upper_mnemonic in {
+        "FENTRY",
+        "FEXIT",
+        "FRET.RA",
+        "FRET.STK",
+    }
+    if lower in {"dstbegin", "dstend"} and frame_template:
+        # Architectural RA is register encoding 10 in frame-template range
+        # syntax; arbitrary register 1 is not a legal single-register restore
+        # range for these forms.
+        value = 10
+    elif lower == "uimm" and frame_template:
+        # Frame templates require an aligned, range-compatible stack size.
+        # The generic wide-field seed (129) encodes as 128 after the implicit
+        # low three zero bits and is illegal for a one-register range.
+        value = 8
+    elif width > 5:
         if lower == "regdst":
             value = (4 << 5) | 1  # vt#1
         elif lower == "srcl":
diff --git a/avs/compiler/linx-llvm/tests/neg/tepl_tileop_range.s b/avs/compiler/linx-llvm/tests/neg/tepl_tileop_range.s
index 65a22688..1201d7fb 100644
--- a/avs/compiler/linx-llvm/tests/neg/tepl_tileop_range.s
+++ b/avs/compiler/linx-llvm/tests/neg/tepl_tileop_range.s
@@ -1,3 +1,3 @@
     .text
 bad_tepl:
-    BSTART.TEPL 1024, FP16
+    BSTART.TEPL 4, 0, FP16
diff --git a/avs/compiler/linx-llvm/tests/run.sh b/avs/compiler/linx-llvm/tests/run.sh
index baa26022..7386a060 100755
--- a/avs/compiler/linx-llvm/tests/run.sh
+++ b/avs/compiler/linx-llvm/tests/run.sh
@@ -285,12 +285,10 @@ if [[ -d "$ASM_DIR" ]]; then
         python3 "$ROOT/check_required_mnemonics.py" \
           --objdump "$OUT/$BASE.objdump" \
           --label "$BASE" \
-          --require B.ARG \
+          --require B.DATR \
           --require B.DIM \
           --require B.IOR \
           --require BSTART.ACCCVT \
-          --require BSTART.CUBE \
-          --require BSTART.FIXP \
           --require BSTART.TLOAD \
           --require BSTART.TMATMUL \
           --require BSTART.TMATMUL.ACC \
@@ -392,8 +390,8 @@ if [[ -d "$NEG_DIR" ]]; then
     echo "error: TEPL range negative test unexpectedly assembled" >&2
     exit 1
   fi
-  if ! grep -Eq "TileOp10 must be in range 0\\.\\.1023|TileOpcode must be in range 0\\.\\.1023|Match Instruction Error!" "$NEG_OUT/tepl_tileop_range.err"; then
-    echo "error: TEPL range negative test did not report a range/match failure" >&2
+  if ! grep -Eq "BSTART\\.TEPL requires Mode 0\\.\\.3 and Function 0\\.\\.31|Match Instruction Error!" "$NEG_OUT/tepl_tileop_range.err"; then
+    echo "error: TEPL range negative test did not report the Mode/Function range failure" >&2
     cat "$NEG_OUT/tepl_tileop_range.err" >&2
     exit 1
   fi
diff --git a/avs/compiler/linx-llvm/tests/test_analyze_coverage.py b/avs/compiler/linx-llvm/tests/test_analyze_coverage.py
index bbb2c104..c31f9455 100644
--- a/avs/compiler/linx-llvm/tests/test_analyze_coverage.py
+++ b/avs/compiler/linx-llvm/tests/test_analyze_coverage.py
@@ -15,6 +15,12 @@
 coverage = importlib.util.module_from_spec(SPEC)
 SPEC.loader.exec_module(coverage)
 
+VECTOR_SCRIPT = Path(__file__).with_name("gen_disasm_vectors.py")
+VECTOR_SPEC = importlib.util.spec_from_file_location("gen_disasm_vectors", VECTOR_SCRIPT)
+assert VECTOR_SPEC and VECTOR_SPEC.loader
+vectors = importlib.util.module_from_spec(VECTOR_SPEC)
+VECTOR_SPEC.loader.exec_module(vectors)
+
 
 class AnalyzeCoverageTest(unittest.TestCase):
     def write_spec(self, root: Path, *mnemonics: str) -> Path:
@@ -159,6 +165,28 @@ def test_grouped_encoding_words_are_skipped_before_mnemonic(self) -> None:
             self.assertEqual(report["covered_spec_mnemonics"], 1)
             self.assertEqual(report["unmapped_emitted_mnemonics"], [])
 
+    def test_tepl_friendly_alias_covers_raw_carrier_not_generic_bstart(self) -> None:
+        with tempfile.TemporaryDirectory() as temp:
+            root = Path(temp)
+            spec_data = coverage.load_isa_spec(
+                self.write_spec(root, "BSTART", "BSTART.TEPL")
+            )
+            self.write_objdump(root / "out", "tepl", "BSTART.TDIVS")
+
+            report = coverage.analyze_coverage(spec_data, root / "out")
+
+            self.assertEqual(report["covered_spec_mnemonics"], 1)
+            self.assertEqual(report["missing_mnemonics"], ["BSTART"])
+            self.assertEqual(report["mapped_by_test"]["tepl"], ["BSTART.TEPL"])
+
+    def test_frame_vector_seed_uses_legal_minimum_stack_size(self) -> None:
+        for mnemonic in ("FENTRY", "FEXIT", "FRET.RA", "FRET.STK"):
+            self.assertEqual(
+                vectors._default_field_value("DstBegin", 5, mnemonic), 10
+            )
+            self.assertEqual(vectors._default_field_value("DstEnd", 5, mnemonic), 10)
+            self.assertEqual(vectors._default_field_value("uimm", 12, mnemonic), 8)
+
     def test_fail_under_returns_two_for_incomplete_observed_coverage(self) -> None:
         with tempfile.TemporaryDirectory() as temp:
             root = Path(temp)
diff --git a/avs/qemu/qemu_executable_coverage_manifest.json b/avs/qemu/qemu_executable_coverage_manifest.json
index e840a4a0..406b8e2d 100644
--- a/avs/qemu/qemu_executable_coverage_manifest.json
+++ b/avs/qemu/qemu_executable_coverage_manifest.json
@@ -5,18 +5,19 @@
     "L3": "available"
   },
   "producer": {
-    "refresh_command": "python3 tools/bringup/refresh_qemu_executable_coverage.py --run-id v057-d0e88a99-20260717-r1 --qemu emulator/qemu/build-v057-release/qemu-system-linx64 --apply",
+    "refresh_command": "python3 tools/bringup/refresh_qemu_executable_coverage.py --run-id v0571-cfc253e8-20260802-r2 --qemu-root emulator/qemu --qemu emulator/qemu/build-v0571-clean/qemu-system-linx64 --llvm-root /private/tmp/llvm-pto0571 --apply",
     "suite_commands": [
-      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite callret --out-dir docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1 --qemu emulator/qemu/build-v057-release/qemu-system-linx64 --clang compiler/llvm/build-linxisa-clang/bin/clang --clangxx compiler/llvm/build-linxisa-clang/bin/clang++ --lld compiler/llvm/build-linxisa-clang/bin/ld.lld --llvm-objdump compiler/llvm/build-linxisa-clang/bin/llvm-objdump --llc compiler/llvm/build-linxisa-clang/bin/llc --timeout 30.0 --require-test-id 0x0000140b --require-test-id 0x0000140c --require-test-id 0x0000140d --require-test-id 0x0000140f --require-test-id 0x00001410 --require-test-id 0x00001411 --evidence-out docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/run-evidence.json --evidence-pc 0x0000000000010fb4 --evidence-pc 0x0000000000010fca --evidence-pc 0x0000000000010fee --evidence-pc 0x0000000000010ffc --evidence-pc 0x0000000000011022 --evidence-pc 0x000000000001105a --evidence-pc 0x0000000000011070",
-      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite executable_memory --out-dir docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1 --qemu emulator/qemu/build-v057-release/qemu-system-linx64 --clang compiler/llvm/build-linxisa-clang/bin/clang --clangxx compiler/llvm/build-linxisa-clang/bin/clang++ --lld compiler/llvm/build-linxisa-clang/bin/ld.lld --llvm-objdump compiler/llvm/build-linxisa-clang/bin/llvm-objdump --llc compiler/llvm/build-linxisa-clang/bin/llc --timeout 30.0 --require-test-id 0x00002201 --require-test-id 0x00002202 --require-test-id 0x00002203 --require-test-id 0x00002204 --require-test-id 0x00002205 --require-test-id 0x00002206 --require-test-id 0x00002207 --require-test-id 0x00002208 --require-test-id 0x00002209 --require-test-id 0x0000220a --require-test-id 0x0000220b --require-test-id 0x0000220c --require-test-id 0x0000220d --evidence-out docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json --evidence-pc 0x0000000000010282 --evidence-pc 0x00000000000102bc --evidence-pc 0x0000000000010302 --evidence-pc 0x000000000001033c --evidence-pc 0x00000000000103a2 --evidence-pc 0x00000000000103f2 --evidence-pc 0x0000000000010442 --evidence-pc 0x000000000001049e --evidence-pc 0x00000000000104ec --evidence-pc 0x0000000000010544 --evidence-pc 0x00000000000105a6 --evidence-pc 0x0000000000010600 --evidence-pc 0x000000000001068a",
-      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite executable_scalar --out-dir docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1 --qemu emulator/qemu/build-v057-release/qemu-system-linx64 --clang compiler/llvm/build-linxisa-clang/bin/clang --clangxx compiler/llvm/build-linxisa-clang/bin/clang++ --lld compiler/llvm/build-linxisa-clang/bin/ld.lld --llvm-objdump compiler/llvm/build-linxisa-clang/bin/llvm-objdump --llc compiler/llvm/build-linxisa-clang/bin/llc --timeout 30.0 --require-test-id 0x00002501 --require-test-id 0x00002502 --require-test-id 0x00002503 --require-test-id 0x00002504 --require-test-id 0x00002505 --require-test-id 0x00002506 --require-test-id 0x00002507 --require-test-id 0x00002508 --require-test-id 0x00002509 --require-test-id 0x0000250a --require-test-id 0x0000250b --require-test-id 0x0000250c --require-test-id 0x0000250d --require-test-id 0x0000250e --require-test-id 0x0000250f --require-test-id 0x00002510 --evidence-out docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json --evidence-pc 0x0000000000010286 --evidence-pc 0x00000000000102a0 --evidence-pc 0x00000000000102b8 --evidence-pc 0x00000000000102d0 --evidence-pc 0x00000000000102e8 --evidence-pc 0x00000000000102fe --evidence-pc 0x0000000000010330 --evidence-pc 0x0000000000010346 --evidence-pc 0x000000000001035e --evidence-pc 0x0000000000010376 --evidence-pc 0x000000000001038e --evidence-pc 0x00000000000103a6 --evidence-pc 0x00000000000103de --evidence-pc 0x0000000000010456 --evidence-pc 0x00000000000104e8 --evidence-pc 0x0000000000010574",
-      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite executable_integer --out-dir docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1 --qemu emulator/qemu/build-v057-release/qemu-system-linx64 --clang compiler/llvm/build-linxisa-clang/bin/clang --clangxx compiler/llvm/build-linxisa-clang/bin/clang++ --lld compiler/llvm/build-linxisa-clang/bin/ld.lld --llvm-objdump compiler/llvm/build-linxisa-clang/bin/llvm-objdump --llc compiler/llvm/build-linxisa-clang/bin/llc --timeout 30.0 --require-test-id 0x00002601 --require-test-id 0x00002602 --require-test-id 0x00002603 --require-test-id 0x00002604 --require-test-id 0x00002605 --require-test-id 0x00002606 --require-test-id 0x00002607 --require-test-id 0x00002608 --require-test-id 0x00002609 --require-test-id 0x0000260a --require-test-id 0x0000260b --require-test-id 0x0000260c --require-test-id 0x0000260d --require-test-id 0x0000260e --require-test-id 0x0000260f --evidence-out docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json --evidence-pc 0x0000000000010284 --evidence-pc 0x000000000001029c --evidence-pc 0x00000000000102b4 --evidence-pc 0x00000000000102c6 --evidence-pc 0x00000000000102da --evidence-pc 0x00000000000102ee --evidence-pc 0x0000000000010302 --evidence-pc 0x0000000000010316 --evidence-pc 0x000000000001033e --evidence-pc 0x000000000001037e --evidence-pc 0x0000000000010390 --evidence-pc 0x00000000000103a2 --evidence-pc 0x00000000000103b4 --evidence-pc 0x00000000000103c6 --evidence-pc 0x000000000001040a",
-      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite v057_vector_ops --out-dir docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1 --qemu emulator/qemu/build-v057-release/qemu-system-linx64 --clang compiler/llvm/build-linxisa-clang/bin/clang --clangxx compiler/llvm/build-linxisa-clang/bin/clang++ --lld compiler/llvm/build-linxisa-clang/bin/ld.lld --llvm-objdump compiler/llvm/build-linxisa-clang/bin/llvm-objdump --llc compiler/llvm/build-linxisa-clang/bin/llc --timeout 30.0 --require-test-id 0x00001320 --require-test-id 0x00001370 --require-test-id 0x00001371 --require-test-id 0x00001372 --require-test-id 0x00001373 --require-test-id 0x00001374 --require-test-id 0x00001375 --evidence-out docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/run-evidence.json --evidence-pc 0x0000000000010278 --evidence-pc 0x0000000000010288 --evidence-pc 0x0000000000010290 --evidence-pc 0x0000000000010298 --evidence-pc 0x00000000000102b8 --evidence-pc 0x00000000000102c0 --evidence-pc 0x0000000000010324",
-      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite atomic --out-dir docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-d0e88a99-20260717-r1 --qemu emulator/qemu/build-v057-release/qemu-system-linx64 --clang compiler/llvm/build-linxisa-clang/bin/clang --clangxx compiler/llvm/build-linxisa-clang/bin/clang++ --lld compiler/llvm/build-linxisa-clang/bin/ld.lld --llvm-objdump compiler/llvm/build-linxisa-clang/bin/llvm-objdump --llc compiler/llvm/build-linxisa-clang/bin/llc --timeout 30.0 --require-test-id 0x00007162 --require-test-id 0x00007163 --evidence-out docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-d0e88a99-20260717-r1/run-evidence.json --evidence-pc 0x00000000000114aa --evidence-pc 0x00000000000114b4"
+      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite callret --out-dir docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2 --qemu emulator/qemu/build-v0571-clean/qemu-system-linx64 --clang /private/tmp/llvm-v0571-verify-build/bin/clang --clangxx /private/tmp/llvm-v0571-verify-build/bin/clang++ --lld /private/tmp/llvm-v0571-verify-build/bin/ld.lld --llvm-objdump /private/tmp/llvm-v0571-verify-build/bin/llvm-objdump --llc /private/tmp/llvm-v0571-verify-build/bin/llc --timeout 30.0 --require-test-id 0x0000140b --require-test-id 0x0000140c --require-test-id 0x0000140d --require-test-id 0x0000140f --require-test-id 0x00001410 --require-test-id 0x00001411 --evidence-out docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json --evidence-pc 0x0000000000010fb4 --evidence-pc 0x0000000000010fca --evidence-pc 0x0000000000010fee --evidence-pc 0x0000000000010ffc --evidence-pc 0x0000000000011022 --evidence-pc 0x000000000001105a --evidence-pc 0x0000000000011070",
+      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite executable_memory --out-dir docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2 --qemu emulator/qemu/build-v0571-clean/qemu-system-linx64 --clang /private/tmp/llvm-v0571-verify-build/bin/clang --clangxx /private/tmp/llvm-v0571-verify-build/bin/clang++ --lld /private/tmp/llvm-v0571-verify-build/bin/ld.lld --llvm-objdump /private/tmp/llvm-v0571-verify-build/bin/llvm-objdump --llc /private/tmp/llvm-v0571-verify-build/bin/llc --timeout 30.0 --require-test-id 0x00002201 --require-test-id 0x00002202 --require-test-id 0x00002203 --require-test-id 0x00002204 --require-test-id 0x00002205 --require-test-id 0x00002206 --require-test-id 0x00002207 --require-test-id 0x00002208 --require-test-id 0x00002209 --require-test-id 0x0000220a --require-test-id 0x0000220b --require-test-id 0x0000220c --require-test-id 0x0000220d --evidence-out docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json --evidence-pc 0x0000000000010282 --evidence-pc 0x00000000000102bc --evidence-pc 0x0000000000010302 --evidence-pc 0x000000000001033c --evidence-pc 0x00000000000103a2 --evidence-pc 0x00000000000103f2 --evidence-pc 0x0000000000010442 --evidence-pc 0x000000000001049e --evidence-pc 0x00000000000104ec --evidence-pc 0x0000000000010544 --evidence-pc 0x00000000000105a6 --evidence-pc 0x0000000000010600 --evidence-pc 0x000000000001068a",
+      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite executable_scalar --out-dir docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2 --qemu emulator/qemu/build-v0571-clean/qemu-system-linx64 --clang /private/tmp/llvm-v0571-verify-build/bin/clang --clangxx /private/tmp/llvm-v0571-verify-build/bin/clang++ --lld /private/tmp/llvm-v0571-verify-build/bin/ld.lld --llvm-objdump /private/tmp/llvm-v0571-verify-build/bin/llvm-objdump --llc /private/tmp/llvm-v0571-verify-build/bin/llc --timeout 30.0 --require-test-id 0x00002501 --require-test-id 0x00002502 --require-test-id 0x00002503 --require-test-id 0x00002504 --require-test-id 0x00002505 --require-test-id 0x00002506 --require-test-id 0x00002507 --require-test-id 0x00002508 --require-test-id 0x00002509 --require-test-id 0x0000250a --require-test-id 0x0000250b --require-test-id 0x0000250c --require-test-id 0x0000250d --require-test-id 0x0000250e --require-test-id 0x0000250f --require-test-id 0x00002510 --evidence-out docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json --evidence-pc 0x0000000000010286 --evidence-pc 0x00000000000102a0 --evidence-pc 0x00000000000102b8 --evidence-pc 0x00000000000102d0 --evidence-pc 0x00000000000102e8 --evidence-pc 0x00000000000102fe --evidence-pc 0x0000000000010330 --evidence-pc 0x0000000000010346 --evidence-pc 0x000000000001035e --evidence-pc 0x0000000000010376 --evidence-pc 0x000000000001038e --evidence-pc 0x00000000000103a6 --evidence-pc 0x00000000000103de --evidence-pc 0x0000000000010456 --evidence-pc 0x00000000000104e8 --evidence-pc 0x0000000000010574",
+      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite executable_integer --out-dir docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2 --qemu emulator/qemu/build-v0571-clean/qemu-system-linx64 --clang /private/tmp/llvm-v0571-verify-build/bin/clang --clangxx /private/tmp/llvm-v0571-verify-build/bin/clang++ --lld /private/tmp/llvm-v0571-verify-build/bin/ld.lld --llvm-objdump /private/tmp/llvm-v0571-verify-build/bin/llvm-objdump --llc /private/tmp/llvm-v0571-verify-build/bin/llc --timeout 30.0 --require-test-id 0x00002601 --require-test-id 0x00002602 --require-test-id 0x00002603 --require-test-id 0x00002604 --require-test-id 0x00002605 --require-test-id 0x00002606 --require-test-id 0x00002607 --require-test-id 0x00002608 --require-test-id 0x00002609 --require-test-id 0x0000260a --require-test-id 0x0000260b --require-test-id 0x0000260c --require-test-id 0x0000260d --require-test-id 0x0000260e --require-test-id 0x0000260f --evidence-out docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json --evidence-pc 0x0000000000010284 --evidence-pc 0x000000000001029c --evidence-pc 0x00000000000102b4 --evidence-pc 0x00000000000102c6 --evidence-pc 0x00000000000102da --evidence-pc 0x00000000000102ee --evidence-pc 0x0000000000010302 --evidence-pc 0x0000000000010316 --evidence-pc 0x000000000001033e --evidence-pc 0x000000000001037e --evidence-pc 0x0000000000010390 --evidence-pc 0x00000000000103a2 --evidence-pc 0x00000000000103b4 --evidence-pc 0x00000000000103c6 --evidence-pc 0x000000000001040a",
+      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite v057_vector_ops --out-dir docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2 --qemu emulator/qemu/build-v0571-clean/qemu-system-linx64 --clang /private/tmp/llvm-v0571-verify-build/bin/clang --clangxx /private/tmp/llvm-v0571-verify-build/bin/clang++ --lld /private/tmp/llvm-v0571-verify-build/bin/ld.lld --llvm-objdump /private/tmp/llvm-v0571-verify-build/bin/llvm-objdump --llc /private/tmp/llvm-v0571-verify-build/bin/llc --timeout 30.0 --require-test-id 0x00001320 --require-test-id 0x00001370 --require-test-id 0x00001371 --require-test-id 0x00001372 --require-test-id 0x00001373 --require-test-id 0x00001374 --require-test-id 0x00001375 --evidence-out docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json --evidence-pc 0x0000000000010278 --evidence-pc 0x0000000000010288 --evidence-pc 0x0000000000010290 --evidence-pc 0x0000000000010298 --evidence-pc 0x00000000000102b8 --evidence-pc 0x00000000000102c0 --evidence-pc 0x0000000000010324",
+      "LINX_VIRT_TEST_FINISHER=1 python3 avs/qemu/run_tests.py --suite atomic --out-dir docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2 --qemu emulator/qemu/build-v0571-clean/qemu-system-linx64 --clang /private/tmp/llvm-v0571-verify-build/bin/clang --clangxx /private/tmp/llvm-v0571-verify-build/bin/clang++ --lld /private/tmp/llvm-v0571-verify-build/bin/ld.lld --llvm-objdump /private/tmp/llvm-v0571-verify-build/bin/llvm-objdump --llc /private/tmp/llvm-v0571-verify-build/bin/llc --timeout 30.0 --require-test-id 0x00007162 --require-test-id 0x00007163 --evidence-out docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json --evidence-pc 0x000000000001151a --evidence-pc 0x000000000001152e"
     ],
-    "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-    "llvm_sha": "c39f7d86ce08489b8beb0f0da9f614445a4aa8e5",
-    "bundle_policy": "Never overwrite old evidence bundles; publish only after all six suites pass strict validation.",
+    "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+    "llvm_sha": "3feb50e4e1896105746a1831d3545d690518d3b3",
+    "llvm_source_dirty": false,
+    "bundle_policy": "Never overwrite old evidence bundles; publish only after all selected suites pass strict validation.",
     "report_command": "python3 tools/bringup/report_qemu_executable_coverage.py --require-nonzero --require-clean"
   },
   "evidence": [
@@ -31,8 +32,8 @@
       "suite": "callret",
       "suite_completion_test_id": "0x00001412",
       "test_id": "0x0000140b",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/obj/14_callret_templates.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
       "instruction": {
         "raw_bytes_le": "4100a504",
         "disassembly": "FENTRY [ra ~ ra], sp!, 16",
@@ -46,9 +47,9 @@
         "test_symbol": "test_fret_stk_uses_stack_ra",
         "target_symbol": "callret_tpl_fret_stk_slot_redirect"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "3d47f2018f383b2f30b6a0d5b726603ebbb75e6f05b30f9530c322ee499816f4",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "bef6f16326c012af9b9a7246546656845c5263c2283ff1f6997eb5b527d3e42a",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/14_callret.c",
@@ -70,8 +71,8 @@
       "suite": "callret",
       "suite_completion_test_id": "0x00001412",
       "test_id": "0x0000140b",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/obj/14_callret_templates.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
       "instruction": {
         "raw_bytes_le": "4130a504",
         "disassembly": "FRET.STK [ra ~ ra], sp!, 16",
@@ -85,9 +86,9 @@
         "test_symbol": "test_fret_stk_uses_stack_ra",
         "target_symbol": "callret_tpl_fret_stk_slot_redirect"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "3d47f2018f383b2f30b6a0d5b726603ebbb75e6f05b30f9530c322ee499816f4",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "bef6f16326c012af9b9a7246546656845c5263c2283ff1f6997eb5b527d3e42a",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/14_callret.c",
@@ -109,8 +110,8 @@
       "suite": "callret",
       "suite_completion_test_id": "0x00001412",
       "test_id": "0x0000140c",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/obj/14_callret_templates.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
       "instruction": {
         "raw_bytes_le": "4120a504",
         "disassembly": "FRET.RA [ra ~ ra], sp!, 16",
@@ -124,9 +125,9 @@
         "test_symbol": "test_fret_ra_uses_snapshot_ra",
         "target_symbol": "callret_tpl_fret_ra_slot_redirect"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "3d47f2018f383b2f30b6a0d5b726603ebbb75e6f05b30f9530c322ee499816f4",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "bef6f16326c012af9b9a7246546656845c5263c2283ff1f6997eb5b527d3e42a",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/14_callret.c",
@@ -148,8 +149,8 @@
       "suite": "callret",
       "suite_completion_test_id": "0x00001412",
       "test_id": "0x0000140d",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/obj/14_callret_templates.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
       "instruction": {
         "raw_bytes_le": "0038",
         "disassembly": "C.BSTART.STD RET",
@@ -163,9 +164,9 @@
         "test_symbol": "test_ret_error_trailer_returns_via_ra",
         "target_symbol": "callret_tpl_ret_error_trailer_success"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "3d47f2018f383b2f30b6a0d5b726603ebbb75e6f05b30f9530c322ee499816f4",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "bef6f16326c012af9b9a7246546656845c5263c2283ff1f6997eb5b527d3e42a",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/14_callret.c",
@@ -187,8 +188,8 @@
       "suite": "callret",
       "suite_completion_test_id": "0x00001412",
       "test_id": "0x0000140f",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/obj/14_callret_templates.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
       "instruction": {
         "raw_bytes_le": "8400",
         "disassembly": "C.BSTART COND, 0x11032",
@@ -202,9 +203,9 @@
         "test_symbol": "test_c_bstart_cond_paths",
         "target_symbol": "callret_tpl_c_bstart_cond_taken"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "3d47f2018f383b2f30b6a0d5b726603ebbb75e6f05b30f9530c322ee499816f4",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "bef6f16326c012af9b9a7246546656845c5263c2283ff1f6997eb5b527d3e42a",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/14_callret.c",
@@ -226,8 +227,8 @@
       "suite": "callret",
       "suite_completion_test_id": "0x00001412",
       "test_id": "0x00001410",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/obj/14_callret_templates.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
       "instruction": {
         "raw_bytes_le": "37000300",
         "disassembly": "j 6",
@@ -241,9 +242,9 @@
         "test_symbol": "test_j_isolated",
         "target_symbol": "callret_tpl_j_skip_poison"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "3d47f2018f383b2f30b6a0d5b726603ebbb75e6f05b30f9530c322ee499816f4",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "bef6f16326c012af9b9a7246546656845c5263c2283ff1f6997eb5b527d3e42a",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/14_callret.c",
@@ -265,8 +266,8 @@
       "suite": "callret",
       "suite_completion_test_id": "0x00001412",
       "test_id": "0x00001411",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/obj/14_callret_templates.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
       "instruction": {
         "raw_bytes_le": "0f06000001200000",
         "disassembly": "L.BSTART.STD DIRECT, 24",
@@ -280,9 +281,9 @@
         "test_symbol": "test_l_bstart_direct_positive",
         "target_symbol": "callret_tpl_l_bstart_direct_positive"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "3d47f2018f383b2f30b6a0d5b726603ebbb75e6f05b30f9530c322ee499816f4",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "bef6f16326c012af9b9a7246546656845c5263c2283ff1f6997eb5b527d3e42a",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/14_callret.c",
@@ -304,8 +305,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x00002201",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "3e1819611100",
         "disassembly": "hl.lwui.po [a0, 4], ->a0, a1",
@@ -319,9 +320,9 @@
         "test_symbol": "test_hl_lwui_po",
         "target_symbol": "executable_memory_hl_lwui_po"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -343,8 +344,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x00002202",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "2e1819611100",
         "disassembly": "hl.lwui.pr [a0, 4], ->a0, a1",
@@ -358,9 +359,9 @@
         "test_symbol": "test_hl_lwui_pr",
         "target_symbol": "executable_memory_hl_lwui_pr"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -382,8 +383,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002501",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "05814106",
         "disassembly": "add a1, a2, ->a0",
@@ -397,9 +398,9 @@
         "test_symbol": "test_add",
         "target_symbol": "executable_scalar_add"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -421,8 +422,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002502",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "05914106",
         "disassembly": "sub a1, a2, ->a0",
@@ -436,9 +437,9 @@
         "test_symbol": "test_sub",
         "target_symbol": "executable_scalar_sub"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -460,8 +461,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002503",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "05a14106",
         "disassembly": "and a1, a2, ->a0",
@@ -475,9 +476,9 @@
         "test_symbol": "test_and",
         "target_symbol": "executable_scalar_and"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -499,8 +500,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002504",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "05b14106",
         "disassembly": "or a1, a2, ->a0",
@@ -514,9 +515,9 @@
         "test_symbol": "test_or",
         "target_symbol": "executable_scalar_or"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -538,8 +539,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002505",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "05c14106",
         "disassembly": "xor a1, a2, ->a0",
@@ -553,9 +554,9 @@
         "test_symbol": "test_xor",
         "target_symbol": "executable_scalar_xor"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -577,8 +578,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002506",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "05f14100",
         "disassembly": "sll a1, a2, ->a0",
@@ -592,9 +593,9 @@
         "test_symbol": "test_sll",
         "target_symbol": "executable_scalar_sll"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -616,8 +617,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002507",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "05d14100",
         "disassembly": "srl a1, a2, ->a0",
@@ -631,9 +632,9 @@
         "test_symbol": "test_srl",
         "target_symbol": "executable_scalar_srl"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -655,8 +656,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002508",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "05e14100",
         "disassembly": "sra a1, a2, ->a0",
@@ -670,9 +671,9 @@
         "test_symbol": "test_sra",
         "target_symbol": "executable_scalar_sra"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -694,8 +695,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002509",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "09814106",
         "disassembly": "lb [a1, a2], ->a0",
@@ -709,9 +710,9 @@
         "test_symbol": "test_lb",
         "target_symbol": "executable_scalar_lb"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -733,8 +734,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x0000250a",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "09914106",
         "disassembly": "lh [a1, a2], ->a0",
@@ -748,9 +749,9 @@
         "test_symbol": "test_lh",
         "target_symbol": "executable_scalar_lh"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -772,8 +773,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x0000250b",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "09a14106",
         "disassembly": "lw [a1, a2], ->a0",
@@ -787,9 +788,9 @@
         "test_symbol": "test_lw",
         "target_symbol": "executable_scalar_lw"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -811,8 +812,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x0000250c",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "09b14106",
         "disassembly": "ld [a1, a2], ->a0",
@@ -826,9 +827,9 @@
         "test_symbol": "test_ld",
         "target_symbol": "executable_scalar_ld"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -850,8 +851,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x0000250d",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "4900411e",
         "disassembly": "sb a1, [a0, a2]",
@@ -865,9 +866,9 @@
         "test_symbol": "test_sb",
         "target_symbol": "executable_scalar_sb"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -889,8 +890,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x0000250e",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "4910411e",
         "disassembly": "sh a1, [a0, a2<<1]",
@@ -904,9 +905,9 @@
         "test_symbol": "test_sh",
         "target_symbol": "executable_scalar_sh"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -928,8 +929,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x0000250f",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "49205216",
         "disassembly": "sw a0, [a2, a3<<2]",
@@ -943,9 +944,9 @@
         "test_symbol": "test_sw",
         "target_symbol": "executable_scalar_sw"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -967,8 +968,8 @@
       "suite": "executable_scalar",
       "suite_completion_test_id": "0x00002510",
       "test_id": "0x00002510",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/obj/23_executable_scalar.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
       "instruction": {
         "raw_bytes_le": "4930521e",
         "disassembly": "sd a1, [a2, a3<<3]",
@@ -982,9 +983,9 @@
         "test_symbol": "test_sd",
         "target_symbol": "executable_scalar_sd"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "9bbe4fb53f08b2331c62eb5f3b8b6baa5338b47447995971ca7a60b7d5e193dc",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "96b1db9b614ac8ee7b82225fe57da7017079d3dfd8cbd7642aa73b31e966b552",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/23_executable_scalar.c",
@@ -1006,8 +1007,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x00002203",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "3e1829614100",
         "disassembly": "hl.lwui.upo [a0, 4], ->a0, a1",
@@ -1021,9 +1022,9 @@
         "test_symbol": "test_hl_lwui_upo",
         "target_symbol": "executable_memory_hl_lwui_upo"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1045,8 +1046,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x00002204",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "2e1829614100",
         "disassembly": "hl.lwui.upr [a0, 4], ->a0, a1",
@@ -1060,9 +1061,9 @@
         "test_symbol": "test_hl_lwui_upr",
         "target_symbol": "executable_memory_hl_lwui_upr"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1084,8 +1085,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x00002205",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "3e2859204102",
         "disassembly": "hl.swi.po a0, [a2, 4], ->a3",
@@ -1099,9 +1100,9 @@
         "test_symbol": "test_hl_swi_po",
         "target_symbol": "executable_memory_hl_swi_po"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1123,8 +1124,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x00002206",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "2e2059a02102",
         "disassembly": "hl.swi.pr a1, [a0, 4], ->a2",
@@ -1138,9 +1139,9 @@
         "test_symbol": "test_hl_swi_pr",
         "target_symbol": "executable_memory_hl_swi_pr"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1162,8 +1163,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x00002207",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "3e2059e02108",
         "disassembly": "hl.swi.upo a1, [a0, 4], ->a2",
@@ -1177,9 +1178,9 @@
         "test_symbol": "test_hl_swi_upo",
         "target_symbol": "executable_memory_hl_swi_upo"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1201,8 +1202,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x00002208",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "2e2859604108",
         "disassembly": "hl.swi.upr a0, [a2, 4], ->a3",
@@ -1216,9 +1217,9 @@
         "test_symbol": "test_hl_swi_upr",
         "target_symbol": "executable_memory_hl_swi_upr"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1240,8 +1241,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x00002209",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "1e2099e10100",
         "disassembly": "hl.lwuip [a1, 0], ->a1, a2",
@@ -1255,9 +1256,9 @@
         "test_symbol": "test_hl_lwuip",
         "target_symbol": "executable_memory_hl_lwuip"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1279,8 +1280,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x0000220a",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "9e0059a04200",
         "disassembly": "hl.swip a3, a0, [a2, 0]",
@@ -1294,9 +1295,9 @@
         "test_symbol": "test_hl_swip",
         "target_symbol": "executable_memory_hl_swip"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1318,8 +1319,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x0000220b",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "9e0059e04210",
         "disassembly": "hl.swip.u a3, a0, [a2, 8]",
@@ -1333,9 +1334,9 @@
         "test_symbol": "test_hl_swip_u",
         "target_symbol": "executable_memory_hl_swip_u"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1357,8 +1358,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x0000220c",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "1e2819320200",
         "disassembly": "hl.ldip [a2, 0], ->a2, a3",
@@ -1372,9 +1373,9 @@
         "test_symbol": "test_hl_ldip",
         "target_symbol": "executable_memory_hl_ldip"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1396,8 +1397,8 @@
       "suite": "executable_memory",
       "suite_completion_test_id": "0x0000220d",
       "test_id": "0x0000220d",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/obj/22_executable_memory.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
       "instruction": {
         "raw_bytes_le": "de0059305100",
         "disassembly": "hl.sdip a0, a1, [a3, 0]",
@@ -1411,9 +1412,9 @@
         "test_symbol": "test_hl_sdip",
         "target_symbol": "executable_memory_hl_sdip"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7d45dbfa511d803d261ead5e1eee5bae989d36f32bcfde6d95918e9979efbad0",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "4504e7a260a6fb61088530db6cf8c3bd8a9fe75b6196c8b4be75b7b3038f7ed7",
       "oracle": {
         "kind": "architectural_state",
         "source": "avs/qemu/tests/22_executable_memory.c",
@@ -1435,8 +1436,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x00002601",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "09c14106",
         "disassembly": "lbu [a1, a2], ->a0",
@@ -1450,9 +1451,9 @@
         "test_symbol": "test_lbu",
         "target_symbol": "executable_integer_lbu"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1474,8 +1475,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x00002602",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "09d14106",
         "disassembly": "lhu [a1, a2], ->a0",
@@ -1489,9 +1490,9 @@
         "test_symbol": "test_lhu",
         "target_symbol": "executable_integer_lhu"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1513,8 +1514,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x00002603",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "09e14106",
         "disassembly": "lwu [a1, a2], ->a0",
@@ -1528,9 +1529,9 @@
         "test_symbol": "test_lwu",
         "target_symbol": "executable_integer_lwu"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1552,8 +1553,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x00002604",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "47814100",
         "disassembly": "mul a1, a2, ->a0",
@@ -1567,9 +1568,9 @@
         "test_symbol": "test_mul",
         "target_symbol": "executable_integer_mul"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1591,8 +1592,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x00002605",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "57814100",
         "disassembly": "div a1, a2, ->a0",
@@ -1606,9 +1607,9 @@
         "test_symbol": "test_div",
         "target_symbol": "executable_integer_div"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1630,8 +1631,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x00002606",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "57914100",
         "disassembly": "divu a1, a2, ->a0",
@@ -1645,9 +1646,9 @@
         "test_symbol": "test_divu",
         "target_symbol": "executable_integer_divu"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1669,8 +1670,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x00002607",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "57c14100",
         "disassembly": "rem a1, a2, ->a0",
@@ -1684,9 +1685,9 @@
         "test_symbol": "test_rem",
         "target_symbol": "executable_integer_rem"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1708,8 +1709,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x00002608",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "57d14100",
         "disassembly": "remu a1, a2, ->a0",
@@ -1723,9 +1724,9 @@
         "test_symbol": "test_remu",
         "target_symbol": "executable_integer_remu"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1747,8 +1748,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x00002609",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "45813106",
         "disassembly": "cmp.eq a1, a1, ->a0",
@@ -1762,9 +1763,9 @@
         "test_symbol": "test_cmp_eq",
         "target_symbol": "executable_integer_cmp_eq"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1786,8 +1787,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x0000260a",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "45913206",
         "disassembly": "cmp.ne a3, a1, ->a0",
@@ -1801,9 +1802,9 @@
         "test_symbol": "test_cmp_ne",
         "target_symbol": "executable_integer_cmp_ne"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1825,8 +1826,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x0000260b",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "45c14106",
         "disassembly": "cmp.lt a1, a2, ->a0",
@@ -1840,9 +1841,9 @@
         "test_symbol": "test_cmp_lt",
         "target_symbol": "executable_integer_cmp_lt"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1864,8 +1865,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x0000260c",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "45e14106",
         "disassembly": "cmp.ltu a1, a2, ->a0",
@@ -1879,9 +1880,9 @@
         "test_symbol": "test_cmp_ltu",
         "target_symbol": "executable_integer_cmp_ltu"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1903,8 +1904,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x0000260d",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "45d14106",
         "disassembly": "cmp.ge a1, a2, ->a0",
@@ -1918,9 +1919,9 @@
         "test_symbol": "test_cmp_ge",
         "target_symbol": "executable_integer_cmp_ge"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1942,8 +1943,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x0000260e",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "45f14106",
         "disassembly": "cmp.geu a1, a2, ->a0",
@@ -1957,9 +1958,9 @@
         "test_symbol": "test_cmp_geu",
         "target_symbol": "executable_integer_cmp_geu"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -1981,8 +1982,8 @@
       "suite": "executable_integer",
       "suite_completion_test_id": "0x0000260f",
       "test_id": "0x0000260f",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/obj/24_executable_integer.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
       "instruction": {
         "raw_bytes_le": "f7015216",
         "disassembly": "csel a0, a2, a3, ->a1",
@@ -1996,9 +1997,9 @@
         "test_symbol": "test_csel",
         "target_symbol": "executable_integer_csel"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "7399701135f78e88620ac25f1c7369d5374e19f7c68f9531e753b9929667ec52",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "aeb7a6751ea48fd8a6e5bf785eefba5959a5c9739eacc6bd7d32f11a3cb19aa1",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/24_executable_integer.c",
@@ -2020,8 +2021,8 @@
       "suite": "v057_vector_ops",
       "suite_completion_test_id": "0x00001320",
       "test_id": "0x00001372",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/obj/13_v057_vector_ops_matrix.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
       "instruction": {
         "raw_bytes_le": "7fa2000009200000",
         "disassembly": "v.lw.brg [ri0, lc0<<2, zero], ->vt",
@@ -2035,9 +2036,9 @@
         "test_symbol": "test_v_lw_brg_evidence",
         "target_symbol": "__linx_v057_ops_add_sub_body"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "1bfef51ff666879da0e72b8c108dcb06b8ab13d828249d660fdd59a0ca9b8b66",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "7733960a4d93b4f789c5a87bdcdcb770510f5e6f69321a563d9bc406a833c4c5",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c",
@@ -2059,8 +2060,8 @@
       "suite": "v057_vector_ops",
       "suite_completion_test_id": "0x00001320",
       "test_id": "0x00001370",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/obj/13_v057_vector_ops_matrix.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
       "instruction": {
         "raw_bytes_le": "7f02520005801000",
         "disassembly": "v.add vt#1, vu#1.sw, ->vt",
@@ -2074,9 +2075,9 @@
         "test_symbol": "test_v_add_evidence",
         "target_symbol": "__linx_v057_ops_add_sub_body"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "1bfef51ff666879da0e72b8c108dcb06b8ab13d828249d660fdd59a0ca9b8b66",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "7733960a4d93b4f789c5a87bdcdcb770510f5e6f69321a563d9bc406a833c4c5",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c",
@@ -2098,8 +2099,8 @@
       "suite": "v057_vector_ops",
       "suite_completion_test_id": "0x00001320",
       "test_id": "0x00001373",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/obj/13_v057_vector_ops_matrix.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
       "instruction": {
         "raw_bytes_le": "7fa0002049200108",
         "disassembly": "v.sw.brg vt#1, [ri2, lc0<<2, zero<<2]",
@@ -2113,9 +2114,9 @@
         "test_symbol": "test_v_sw_brg_evidence",
         "target_symbol": "__linx_v057_ops_add_sub_body"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "1bfef51ff666879da0e72b8c108dcb06b8ab13d828249d660fdd59a0ca9b8b66",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "7733960a4d93b4f789c5a87bdcdcb770510f5e6f69321a563d9bc406a833c4c5",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c",
@@ -2137,8 +2138,8 @@
       "suite": "v057_vector_ops",
       "suite_completion_test_id": "0x00001320",
       "test_id": "0x00001371",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/obj/13_v057_vector_ops_matrix.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
       "instruction": {
         "raw_bytes_le": "7f02520005101100",
         "disassembly": "v.sub vt#2, vu#1.sw, ->vt",
@@ -2152,9 +2153,9 @@
         "test_symbol": "test_v_sub_evidence",
         "target_symbol": "__linx_v057_ops_add_sub_body"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "1bfef51ff666879da0e72b8c108dcb06b8ab13d828249d660fdd59a0ca9b8b66",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "7733960a4d93b4f789c5a87bdcdcb770510f5e6f69321a563d9bc406a833c4c5",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c",
@@ -2176,8 +2177,8 @@
       "suite": "v057_vector_ops",
       "suite_completion_test_id": "0x00001320",
       "test_id": "0x00001374",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/obj/13_v057_vector_ops_matrix.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
       "instruction": {
         "raw_bytes_le": "7f0212004b802000",
         "disassembly": "v.fadd vt#1, ri2, ->vt",
@@ -2191,9 +2192,9 @@
         "test_symbol": "test_v_fadd_evidence",
         "target_symbol": "__linx_v057_ops_float_body"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "1bfef51ff666879da0e72b8c108dcb06b8ab13d828249d660fdd59a0ca9b8b66",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "7733960a4d93b4f789c5a87bdcdcb770510f5e6f69321a563d9bc406a833c4c5",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c",
@@ -2215,8 +2216,8 @@
       "suite": "v057_vector_ops",
       "suite_completion_test_id": "0x00001320",
       "test_id": "0x00001375",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/obj/13_v057_vector_ops_matrix.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
       "instruction": {
         "raw_bytes_le": "7f0212004ba03000",
         "disassembly": "v.fmul vt#1, ri3, ->vt",
@@ -2230,9 +2231,9 @@
         "test_symbol": "test_v_fmul_evidence",
         "target_symbol": "__linx_v057_ops_float_body"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "1bfef51ff666879da0e72b8c108dcb06b8ab13d828249d660fdd59a0ca9b8b66",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "7733960a4d93b4f789c5a87bdcdcb770510f5e6f69321a563d9bc406a833c4c5",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c",
@@ -2254,8 +2255,8 @@
       "suite": "v057_vector_ops",
       "suite_completion_test_id": "0x00001320",
       "test_id": "0x00001320",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/obj/13_v057_vector_ops_matrix.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
       "instruction": {
         "raw_bytes_le": "7f82110045401000",
         "disassembly": "v.cmp.lt lc0, ri1, ->vt",
@@ -2269,9 +2270,9 @@
         "test_symbol": "test_v_mixed_scalar_vector_predicate",
         "target_symbol": "__linx_v057_ops_mixed_pred_body"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "1bfef51ff666879da0e72b8c108dcb06b8ab13d828249d660fdd59a0ca9b8b66",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "7733960a4d93b4f789c5a87bdcdcb770510f5e6f69321a563d9bc406a833c4c5",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c",
@@ -2293,14 +2294,14 @@
       "suite": "atomic",
       "suite_completion_test_id": "0x00007160",
       "test_id": "0x00007162",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-d0e88a99-20260717-r1/obj/07_atomic_lr_srczero.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.o",
       "instruction": {
         "raw_bytes_le": "0b01f121",
         "disassembly": "lr.w [a0, 0], ->a0",
         "object_offset": "0x42",
-        "elf_offset": "0x24aa",
-        "pc": "0x00000000000114aa",
+        "elf_offset": "0x251a",
+        "pc": "0x000000000001151a",
         "symbol": "atomic_lr_w_nonzero_srczero"
       },
       "reachability": {
@@ -2308,9 +2309,9 @@
         "test_symbol": "test_lr_w_nonzero_srczero",
         "target_symbol": "atomic_lr_w_nonzero_srczero"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "c386428a32b659e574d667e5d3233b0fcd70884a5222ff0faff869154efab22d",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "39ba0d2c2d487ef1c5715cd67a5480bb4a581e945c8c593095f5ff29da21336d",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/07_atomic.c",
@@ -2332,14 +2333,14 @@
       "suite": "atomic",
       "suite_completion_test_id": "0x00007160",
       "test_id": "0x00007163",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-d0e88a99-20260717-r1/linx-qemu-tests.elf",
-      "object": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-d0e88a99-20260717-r1/obj/07_atomic_lr_srczero.o",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "object": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.o",
       "instruction": {
         "raw_bytes_le": "0b011131",
         "disassembly": "lr.d [a0, 0], ->a0",
-        "object_offset": "0x4c",
-        "elf_offset": "0x24b4",
-        "pc": "0x00000000000114b4",
+        "object_offset": "0x56",
+        "elf_offset": "0x252e",
+        "pc": "0x000000000001152e",
         "symbol": "atomic_lr_d_nonzero_srczero"
       },
       "reachability": {
@@ -2347,9 +2348,9 @@
         "test_symbol": "test_lr_d_nonzero_srczero",
         "target_symbol": "atomic_lr_d_nonzero_srczero"
       },
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-d0e88a99-20260717-r1/run-evidence.json",
-      "run_evidence_sha256": "c386428a32b659e574d667e5d3233b0fcd70884a5222ff0faff869154efab22d",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "run_evidence_sha256": "39ba0d2c2d487ef1c5715cd67a5480bb4a581e945c8c593095f5ff29da21336d",
       "oracle": {
         "kind": "exact_value",
         "source": "avs/qemu/tests/07_atomic.c",
diff --git a/avs/qemu/run_tests.py b/avs/qemu/run_tests.py
index 0b8cedbd..bff31924 100644
--- a/avs/qemu/run_tests.py
+++ b/avs/qemu/run_tests.py
@@ -504,7 +504,6 @@ def _pto_kernel_src(name: str) -> str:
 
 PTO_TILE_KERNEL_NAMES = [
     "tload_store",
-    "mamulb",
     "tmatmul_acc",
     "gemm",
     "flash_attention",
@@ -513,7 +512,6 @@ def _pto_kernel_src(name: str) -> str:
 
 PTO_PARITY_KERNEL_NAMES = [
     "tload_store",
-    "mamulb",
     "tmatmul_acc",
     "gemm",
     "gemm_basic",
diff --git a/avs/qemu/test_run_tests.py b/avs/qemu/test_run_tests.py
index 9ebe9055..0a27f73d 100644
--- a/avs/qemu/test_run_tests.py
+++ b/avs/qemu/test_run_tests.py
@@ -12,6 +12,14 @@
 
 
 class StructuredEvidenceParsingTests(unittest.TestCase):
+    def test_selected_pto_kernel_names_are_current_and_catalogued(self) -> None:
+        selected = set(run_tests.PTO_TILE_KERNEL_NAMES) | set(
+            run_tests.PTO_PARITY_KERNEL_NAMES
+        )
+        self.assertNotIn("mamulb", selected)
+        catalog = run_tests._load_pto_kernel_catalog()
+        self.assertEqual(sorted(selected - set(catalog)), [])
+
     def test_every_declared_suite_source_exists(self) -> None:
         missing = {
             name: meta["src"]
diff --git a/avs/qemu/tests/10_tile_cube.cpp b/avs/qemu/tests/10_tile_cube.cpp
index 84e7e7af..96549d97 100644
--- a/avs/qemu/tests/10_tile_cube.cpp
+++ b/avs/qemu/tests/10_tile_cube.cpp
@@ -35,7 +35,7 @@ static void run_tmatmul_test()
 
     auto ta = pto::linx::tload<kTileSizeCode>(a);
     auto tb = pto::linx::tload<kTileSizeCode>(b);
-    auto tc = pto::linx::mamulb<8, 8, 8>(ta, tb);
+    auto tc = pto::linx::tmatmul<8, 8, 8>(ta, tb);
     pto::linx::tstore<kTileSizeCode>(c, tc);
 
     matmul_ref_i32_8x8(expected, a, b);
@@ -67,7 +67,7 @@ static void run_tmatmul_acc_test()
 
     auto ta = pto::linx::tload<kTileSizeCode>(a);
     auto tb = pto::linx::tload<kTileSizeCode>(b);
-    auto seed = pto::linx::mamulb<8, 8, 8>(ta, tb);
+    auto seed = pto::linx::tmatmul<8, 8, 8>(ta, tb);
     auto out = pto::linx::tmatmul_acc<8, 8, 8>(seed, ta, tb);
     pto::linx::tstore<kTileSizeCode>(c, out);
 
diff --git a/avs/qemu/tests/10_tile_cube_asm.S b/avs/qemu/tests/10_tile_cube_asm.S
index 7eea808a..9ef6ed97 100644
--- a/avs/qemu/tests/10_tile_cube_asm.S
+++ b/avs/qemu/tests/10_tile_cube_asm.S
@@ -13,7 +13,7 @@ linx_tmatmul_bias_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 8, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
 
@@ -21,7 +21,7 @@ linx_tmatmul_bias_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 8, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<512B>
 
@@ -29,7 +29,7 @@ linx_tmatmul_bias_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 1, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT last, ->t<512B>
 
@@ -37,17 +37,19 @@ linx_tmatmul_bias_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 8, ->lb1
     C.B.DIMI 8, ->lb2
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOT t#3, t#2
-    B.IOT t#1, last, ->acc<512B>
+    B.IOT t#1, last
 
     BSTART.ACCCVT INT32
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOT last, ->m<512B>
 
     BSTART.TSTORE INT32
     C.B.DIMI 8, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a3],[]
     B.IOT m#1, last, ->m<512B>
 
@@ -66,7 +68,7 @@ linx_tgemv_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 8, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
 
@@ -74,7 +76,7 @@ linx_tgemv_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 8, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<512B>
 
@@ -82,16 +84,18 @@ linx_tgemv_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 1, ->lb1
     C.B.DIMI 8, ->lb2
-    B.IOT t#2, t#1, last, ->acc<512B>
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
+    B.IOT t#2, t#1, last
 
     BSTART.ACCCVT INT32
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOT last, ->m<512B>
 
     BSTART.TSTORE INT32
     C.B.DIMI 8, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT m#1, last, ->m<512B>
 
@@ -107,7 +111,7 @@ linx_tgemv_acc_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 8, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
 
@@ -115,7 +119,7 @@ linx_tgemv_acc_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 8, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<512B>
 
@@ -123,25 +127,29 @@ linx_tgemv_acc_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 1, ->lb1
     C.B.DIMI 8, ->lb2
-    B.IOT t#2.reuse, t#1.reuse, last, ->acc<512B>
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
+    B.IOT t#2.reuse, t#1.reuse, last
 
     BSTART.ACCCVT INT32
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOT last, ->m<512B>
 
     BSTART.TGEMV.ACC INT32
     C.B.DIMI 8, ->lb0
     C.B.DIMI 1, ->lb1
     C.B.DIMI 8, ->lb2
-    B.IOT t#2, t#1, last, ->acc<512B>
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
+    B.IOT t#2, t#1, last
 
     BSTART.ACCCVT INT32
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOT last, ->m<512B>
 
     BSTART.TSTORE INT32
     C.B.DIMI 8, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT m#1, last, ->m<512B>
 
diff --git a/avs/qemu/tests/10_tile_integration.cpp b/avs/qemu/tests/10_tile_integration.cpp
index 7620baa5..9465e55a 100644
--- a/avs/qemu/tests/10_tile_integration.cpp
+++ b/avs/qemu/tests/10_tile_integration.cpp
@@ -26,14 +26,12 @@ extern "C" void run_tile_integration_tests(void)
 
 #if PTO_QEMU_SMOKE
     constexpr uint64_t kDigestTloadStore = UINT64_C(0xA1248F48FF3C7199);
-    constexpr uint64_t kDigestMamulb = UINT64_C(0x5400A6A0D6991D4D);
     constexpr uint64_t kDigestTmatmulAcc = UINT64_C(0x2A37199ED1CBD94D);
     constexpr uint64_t kDigestGemm = UINT64_C(0x5400A6A0D6991D4D);
     constexpr uint64_t kDigestFlash = UINT64_C(0x754D619AB6075DA1);
     constexpr uint64_t kDigestFlashMasked = UINT64_C(0xE56690EBAB5372C9);
 #else
     constexpr uint64_t kDigestTloadStore = UINT64_C(0xABFA311400C734C3);
-    constexpr uint64_t kDigestMamulb = UINT64_C(0xACA73824B88635A3);
     constexpr uint64_t kDigestTmatmulAcc = UINT64_C(0xBA7AB93F72C13823);
     constexpr uint64_t kDigestGemm = UINT64_C(0xACA73824B88635A3);
     constexpr uint64_t kDigestFlash = UINT64_C(0x88745CBAC7A57629);
@@ -75,14 +73,6 @@ extern "C" void run_tile_integration_tests(void)
               0x000A6001u);
     test_pass();
 
-    test_start(0x000A0007);
-    uart_puts("PTO kernel mamulb digest ... ");
-    zero(mat_c, kMatElems);
-    pto::kernels::pto_mamulb(mat_c, mat_a, mat_b, nullptr);
-    TEST_EQ64(fnv1a_bytes(mat_c, sizeof(mat_c)), kDigestMamulb,
-              0x000A7001u);
-    test_pass();
-
     test_start(0x000A0008);
     uart_puts("PTO kernel tmatmul_acc digest ... ");
     zero(mat_c, kMatElems);
diff --git a/avs/qemu/tests/10_tile_tepl_asm.S b/avs/qemu/tests/10_tile_tepl_asm.S
index ab5a5067..62ac341f 100644
--- a/avs/qemu/tests/10_tile_tepl_asm.S
+++ b/avs/qemu/tests/10_tile_tepl_asm.S
@@ -13,19 +13,18 @@
 
     ssrget 0x0033, ->a0
     BSTART.TLOAD \dtype
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<2KB>
 
     BSTART.\op \dtype
-    B.ARG VV
     B.IOT t#1, last, ->t<2KB>
 
     .globl \resume
 \resume:
     ssrget 0x0034, ->a0
     BSTART.TSTORE \dtype
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT t#1, last, ->t<2KB>
 
@@ -61,7 +60,7 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI \cols, ->lb0
     C.B.DIMI \rows, ->lb1
     C.B.DIMI \stride, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [\reg],[]
     B.IOT last, ->t<4KB>
     .endm
@@ -71,7 +70,7 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 4, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [\reg],[]
     B.IOT t#1, last, ->t<4KB>
     .endm
@@ -88,7 +87,6 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 4, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG VV
     B.IOT t#2, t#1, last, ->t<4KB>
 
     STORE_FP32 a2
@@ -107,7 +105,6 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 4, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG VV
     B.IOT t#1, last, ->t<4KB>
 
     STORE_FP32 a1
@@ -147,7 +144,7 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
 
@@ -155,7 +152,6 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG VV
     .if \emit_datr
     B.DATR normal, FP32, \pad, cmode0, rmode0
     .endif
@@ -165,7 +161,7 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI 4, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT t#1, last, ->t<512B>
 
@@ -188,7 +184,7 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
 
@@ -196,7 +192,6 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG VV
     B.DATR normal, \dtype, \pad, cmode0, rmode0
     B.IOT t#1, last, ->t<512B>
 
@@ -204,7 +199,7 @@ linx_tepl_reject_acr0_trap_handler:
     C.B.DIMI 4, ->lb0
     C.B.DIMI 128, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT t#1, last, ->t<512B>
 
@@ -225,20 +220,19 @@ linx_treshape_bytes:
     C.B.DIMI 4, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
     BSTART.TRESHAPE INT16
     C.B.DIMI 8, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG VV
     B.IOT t#1, last, ->t<512B>
     BSTART.TSTORE INT16
     C.B.DIMI 8, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT16, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT t#1, last, ->t<512B>
     FRET.STK [ra ~ ra], sp!, 8
@@ -252,27 +246,26 @@ linx_tconcat_f32:
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
     BSTART.TLOAD FP32
     C.B.DIMI 2, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<512B>
     BSTART.TCONCAT FP32
     C.B.DIMI 5, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG VV
     B.IOT t#2, t#1, last, ->t<512B>
     BSTART.TSTORE FP32
     C.B.DIMI 8, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<512B>
     FRET.STK [ra ~ ra], sp!, 8
@@ -284,21 +277,20 @@ linx_tgatherb_u8:
     FENTRY [ra ~ ra], sp!, 8
     BSTART.TLOAD UINT8
     C.B.DIMI 512, ->lb0
-    B.ARG NORM.normal
+    B.DATR normal, UINT8, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
     BSTART.TLOAD UINT32
     C.B.DIMI 8, ->lb0
-    B.ARG NORM.normal
+    B.DATR normal, UINT32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<512B>
     BSTART.TGATHERB UINT8
     C.B.DIMI 8, ->lb0
-    B.ARG VV
     B.IOT t#2, t#1, last, ->t<512B>
     BSTART.TSTORE UINT8
     C.B.DIMI 512, ->lb0
-    B.ARG NORM.normal
+    B.DATR normal, UINT8, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<512B>
     FRET.STK [ra ~ ra], sp!, 8
@@ -310,12 +302,11 @@ linx_tci_s32:
     FENTRY [ra ~ ra], sp!, 8
     BSTART.TCI INT32
     C.B.DIMI 8, ->lb0
-    B.ARG VS
     B.IOR [a0],[a1]
     B.IOT last, ->t<512B>
     BSTART.TSTORE INT32
     C.B.DIMI 128, ->lb0
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<512B>
     FRET.STK [ra ~ ra], sp!, 8
@@ -329,14 +320,13 @@ linx_ttri_s32:
     C.B.DIMI 4, ->lb0
     C.B.DIMI 4, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG VS
     B.IOR [a0],[a1]
     B.IOT last, ->t<512B>
     BSTART.TSTORE INT32
     C.B.DIMI 4, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<512B>
     FRET.STK [ra ~ ra], sp!, 8
@@ -350,21 +340,20 @@ linx_textract_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 4, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
     BSTART.TEXTRACT FP32
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG VS
     B.IOR [a1],[a2]
     B.IOT t#1, last, ->t<512B>
     BSTART.TSTORE FP32
     C.B.DIMI 4, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a3],[]
     B.IOT t#1, last, ->t<512B>
     FRET.STK [ra ~ ra], sp!, 8
@@ -378,28 +367,27 @@ linx_tdequant_s8_f32:
     C.B.DIMI 4, ->lb0
     C.B.DIMI 3, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT8, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
     BSTART.TLOAD FP32
     C.B.DIMI 1, ->lb0
     C.B.DIMI 3, ->lb1
     C.B.DIMI 1, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<512B>
     BSTART.TLOAD FP32
     C.B.DIMI 1, ->lb0
     C.B.DIMI 3, ->lb1
     C.B.DIMI 1, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT last, ->t<512B>
     BSTART.TDEQUANT FP32
     C.B.DIMI 4, ->lb0
     C.B.DIMI 3, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG VV
     B.DATR normal, INT8, ZERO, cmode0, rmode0
     B.IOT t#3, t#2
     B.IOT t#1, last, ->t<512B>
@@ -407,7 +395,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 4, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a3],[]
     B.IOT t#1, last, ->t<512B>
     FRET.STK [ra ~ ra], sp!, 8
@@ -423,7 +411,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
 
@@ -431,7 +419,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<512B>
 
@@ -439,7 +427,6 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG VV
     B.IOT t#1, t#2, ->t<512B>
     B.IOT last, ->t<512B>
 
@@ -448,7 +435,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<512B>
 
@@ -456,7 +443,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a3],[]
     B.IOT t#1, last, ->t<512B>
 
@@ -480,7 +467,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 4, ->lb0
     C.B.DIMI 3, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
 
@@ -488,7 +475,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 2, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<512B>
 
@@ -496,14 +483,13 @@ linx_tdequant_s8_f32:
     C.B.DIMI 4, ->lb0
     C.B.DIMI 3, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG VV
     B.IOT t#2, t#1, last, ->t<512B>
 
     BSTART.TSTORE FP32
     C.B.DIMI 4, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<512B>
 
@@ -526,7 +512,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<512B>
 
@@ -534,7 +520,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<512B>
 
@@ -542,7 +528,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, UINT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT last, ->t<512B>
 
@@ -550,7 +536,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, UINT32, ZERO, cmode0, rmode0
     B.IOR [a3],[]
     B.IOT last, ->t<512B>
 
@@ -558,7 +544,6 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG VV
     B.IOT t#4, t#3, ->t<512B>
     B.IOT t#2, t#1, last, ->u<512B>
 
@@ -566,7 +551,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
     B.IOR [a4],[]
     B.IOT t#1, last, ->t<512B>
 
@@ -574,7 +559,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, UINT32, ZERO, cmode0, rmode0
     B.IOR [a5],[]
     B.IOT u#1, last, ->u<512B>
 
@@ -600,7 +585,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<4KB>
 
@@ -608,7 +593,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<4KB>
 
@@ -616,7 +601,6 @@ linx_tdequant_s8_f32:
     C.B.DIMI 31, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG VV
     B.DATR normal, \dtype, ZERO, cmode\cmode, rmode0
     B.IOT t#2, t#1, last, ->t<4KB>
 
@@ -624,7 +608,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, UINT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<4KB>
 
@@ -642,7 +626,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<4KB>
 
@@ -650,7 +634,6 @@ linx_tdequant_s8_f32:
     C.B.DIMI 31, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG VS
     B.DATR normal, \dtype, ZERO, cmode\cmode, rmode0
     B.IOR [a1],[]
     B.IOT t#1, last, ->t<4KB>
@@ -659,7 +642,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, UINT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<4KB>
 
@@ -698,7 +681,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<\footprint>
 
@@ -706,7 +689,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<\footprint>
 
@@ -714,14 +697,13 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG VV
     B.IOT t#2, t#1, last, ->t<\footprint>
 
     BSTART.TSTORE \dtype
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<\footprint>
 
@@ -739,7 +721,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<\footprint>
 
@@ -747,14 +729,13 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG VV
     B.IOT t#1, last, ->t<\footprint>
 
     BSTART.TSTORE \dtype
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dtype, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT t#1, last, ->t<\footprint>
 
@@ -780,7 +761,7 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \src_dtype, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<\src_footprint>
 
@@ -788,14 +769,13 @@ linx_tdequant_s8_f32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG VV
     B.IOT t#1, last, ->t<\dst_footprint>
 
     BSTART.TSTORE \dst_dtype
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dst_dtype, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT t#1, last, ->t<\dst_footprint>
 
@@ -817,7 +797,7 @@ linx_trems_s32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<4KB>
 
@@ -825,7 +805,6 @@ linx_trems_s32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG VS
     B.IOR [a1],[]
     B.IOT t#1, last, ->t<4KB>
 
@@ -833,7 +812,7 @@ linx_trems_s32:
     C.B.DIMI 32, ->lb0
     C.B.DIMI 32, ->lb1
     C.B.DIMI 32, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<4KB>
 
@@ -853,7 +832,7 @@ linx_trems_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 8, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \src_dtype, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<4KB>
 
@@ -861,14 +840,13 @@ linx_trems_s32:
     C.B.DIMI 8, ->lb0
     C.B.DIMI 8, ->lb1
     C.B.DIMI 8, ->lb2
-    B.ARG VV
     B.IOT t#1, last, ->t<4KB>
 
     BSTART.TSTORE \dst_dtype
     C.B.DIMI \dst_cols, ->lb0
     C.B.DIMI \dst_rows, ->lb1
     C.B.DIMI \dst_stride, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, \dst_dtype, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT t#1, last, ->t<4KB>
 
@@ -895,7 +873,7 @@ linx_tsel_s32:
     C.B.DIMI 2, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 2, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, UINT32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<4KB>
 
@@ -903,7 +881,7 @@ linx_tsel_s32:
     C.B.DIMI 64, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 64, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<4KB>
 
@@ -911,7 +889,7 @@ linx_tsel_s32:
     C.B.DIMI 64, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 64, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT last, ->t<4KB>
 
@@ -919,7 +897,6 @@ linx_tsel_s32:
     C.B.DIMI 64, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 64, ->lb2
-    B.ARG VV
     B.IOT t#3, t#2
     B.IOT t#1, last, ->t<4KB>
 
@@ -927,7 +904,7 @@ linx_tsel_s32:
     C.B.DIMI 64, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 64, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a3],[]
     B.IOT t#1, last, ->t<4KB>
 
@@ -943,7 +920,7 @@ linx_tsels_s32:
     C.B.DIMI 2, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 2, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, UINT32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<4KB>
 
@@ -951,7 +928,7 @@ linx_tsels_s32:
     C.B.DIMI 64, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 64, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<4KB>
 
@@ -959,7 +936,6 @@ linx_tsels_s32:
     C.B.DIMI 64, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 64, ->lb2
-    B.ARG VS
     B.IOR [a2],[]
     B.IOT t#2, t#1, last, ->t<4KB>
 
@@ -967,7 +943,7 @@ linx_tsels_s32:
     C.B.DIMI 64, ->lb0
     C.B.DIMI 16, ->lb1
     C.B.DIMI 64, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a3],[]
     B.IOT t#1, last, ->t<4KB>
 
@@ -986,7 +962,7 @@ linx_tadd_rect_s32:
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a0],[]
     B.IOT last, ->t<4KB>
 
@@ -994,7 +970,7 @@ linx_tadd_rect_s32:
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a1],[]
     B.IOT last, ->t<4KB>
 
@@ -1002,14 +978,13 @@ linx_tadd_rect_s32:
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG VV
     B.IOT t#2, t#1, last, ->t<4KB>
 
     BSTART.TSTORE INT32
     C.B.DIMI 3, ->lb0
     C.B.DIMI 2, ->lb1
     C.B.DIMI 4, ->lb2
-    B.ARG NORM.normal
+    B.DATR normal, INT32, ZERO, cmode0, rmode0
     B.IOR [a2],[]
     B.IOT t#1, last, ->t<4KB>
 
diff --git a/avs/qemu/tests/16_pto_kernel_parity.cpp b/avs/qemu/tests/16_pto_kernel_parity.cpp
index 16a378c8..23bd70ee 100644
--- a/avs/qemu/tests/16_pto_kernel_parity.cpp
+++ b/avs/qemu/tests/16_pto_kernel_parity.cpp
@@ -29,7 +29,6 @@ using pto::fp16_t;
 #endif
 
 #define PTO_PARITY_STAGE_TLOAD_STORE 1
-#define PTO_PARITY_STAGE_MAMULB 2
 #define PTO_PARITY_STAGE_TMATMUL_ACC 3
 #define PTO_PARITY_STAGE_GEMM 4
 #define PTO_PARITY_STAGE_GEMM_BASIC 5
@@ -662,12 +661,6 @@ static void run_all_kernels_emit_digest() {
   if (finish_after_stage(PTO_PARITY_STAGE_TLOAD_STORE))
     return;
 
-  emit_stage("mamulb");
-  pto_mamulb(iC, iA, iB, &matmul_i32_cfg);
-  emit_digest("mamulb", fnv1a_bytes(iC, sizeof(iC)));
-  if (finish_after_stage(PTO_PARITY_STAGE_MAMULB))
-    return;
-
   zero_i32(iC, kMatElems);
   emit_stage("tmatmul_acc");
   pto_tmatmul_acc(iC, iA, iB, &matmul_i32_cfg);
diff --git a/compiler/llvm b/compiler/llvm
index 98e6173b..3feb50e4 160000
--- a/compiler/llvm
+++ b/compiler/llvm
@@ -1 +1 @@
-Subproject commit 98e6173b6bd02157feeaf998d8aba63bd5b844cc
+Subproject commit 3feb50e4e1896105746a1831d3545d690518d3b3
diff --git a/compiler/ptoas b/compiler/ptoas
index 6e107fb5..cf2d2870 160000
--- a/compiler/ptoas
+++ b/compiler/ptoas
@@ -1 +1 @@
-Subproject commit 6e107fb532d2a20714aad3576be1161075c0f885
+Subproject commit cf2d2870748023b15ba2c69fed7c7ee9542f173d
diff --git a/docs/architecture/README.md b/docs/architecture/README.md
index 64249b2c..c8018019 100644
--- a/docs/architecture/README.md
+++ b/docs/architecture/README.md
@@ -5,6 +5,7 @@ Architecture-facing documentation lives under `docs/architecture/`.
 ## Canonical contract pages
 
 - v0.57 canonical pages:
+  - `docs/architecture/pto-isa-v0.57.1-upgrade-plan.md` (accepted cross-repository implementation plan; pto-spec remains normative)
   - `docs/architecture/v0.57-architecture-contract.md`
   - `docs/architecture/v0.57-encoding-decisions.md`
   - `docs/architecture/v0.57-hardening-policy.md`
diff --git a/docs/architecture/isa-manual/src/chapters/02_isa_overview.adoc b/docs/architecture/isa-manual/src/chapters/02_isa_overview.adoc
index 45c53abb..193e92a2 100644
--- a/docs/architecture/isa-manual/src/chapters/02_isa_overview.adoc
+++ b/docs/architecture/isa-manual/src/chapters/02_isa_overview.adoc
@@ -63,9 +63,9 @@ these are treated as **standalone blocks** that map to hardware macro execution
 
 The catalog also defines header-driven accelerator families:
 
-* `BSTART.TMA` selector forms and aliases such as `BSTART.TLOAD`, `BSTART.TSTORE`, `BSTART.TMOV`,
-* `BSTART.CUBE` selector forms and aliases such as `BSTART.TMATMUL`, `BSTART.TMATMUL.ACC`, `BSTART.ACCCVT`,
-* `BSTART.TEPL` with `TileOpcode` as the first generic accelerator/template-op selector field; the canonical v0.57
-  profile packs TEPL `mode/function` into `TileOpcode[5:0]` and reserves `TileOpcode[9:6]=0`.
+* TMA-family typed forms such as `BSTART.TLOAD`, `BSTART.TSTORE`, and `BSTART.TMOV`,
+* CUBE-family typed forms such as `BSTART.TMATMUL`, `BSTART.TMATMUL.ACC`, and `BSTART.ACCCVT`,
+* `BSTART.TEPL`, whose raw header carries `Mode[1:0]` and `Function[4:0]`; the logical selector is
+  `(Mode << 5) | Function`.
 
 Selector values that are not explicitly assigned by the v0.57 catalog are reserved and must not acquire ad hoc semantics.
diff --git a/docs/architecture/isa-manual/src/chapters/03_programming_model.adoc b/docs/architecture/isa-manual/src/chapters/03_programming_model.adoc
index 13cc6253..6db46406 100644
--- a/docs/architecture/isa-manual/src/chapters/03_programming_model.adoc
+++ b/docs/architecture/isa-manual/src/chapters/03_programming_model.adoc
@@ -193,8 +193,8 @@ Vector reduction contract (`V.RD*` family):
 [[progmodel-tile]]
 === Tile registers (TAU)
 
-Linx defines a tile register file used by accelerator-oriented *tile blocks* (e.g. `BSTART.TMA`, `BSTART.CUBE`,
-`BSTART.MPAR`, `BSTART.MSEQ`, `BSTART.VPAR`, `BSTART.VSEQ`).
+Linx defines a tile register file used by accelerator-oriented *tile blocks* (for example `BSTART.TLOAD`,
+`BSTART.TMATMUL`, `BSTART.TEPL`, `BSTART.MPAR`, `BSTART.MSEQ`, `BSTART.VPAR`, and `BSTART.VSEQ`).
 
 Bring-up model:
 
diff --git a/docs/architecture/isa-manual/src/chapters/04_block_isa.adoc b/docs/architecture/isa-manual/src/chapters/04_block_isa.adoc
index 32a9028b..d53e8bd4 100644
--- a/docs/architecture/isa-manual/src/chapters/04_block_isa.adoc
+++ b/docs/architecture/isa-manual/src/chapters/04_block_isa.adoc
@@ -165,7 +165,7 @@ In the bring-up model, BARG includes (non-exhaustive):
 Additional bring-up fields used by tooling and trap recovery include:
 
 * block addresses (`BPC` / `BPCN`),
-* ordering/atomic qualifiers (e.g. `AQ`/`RL` from `B.CATR/B.DATR`), and
+* ordering/atomic qualifiers (`AQ`/`RL` from `B.CATR` only), and
 * output register mapping for split blocks.
 
 **BARG lifetime rules (bring-up):**
@@ -193,30 +193,28 @@ The bring-up profile constrains certain combinations (examples):
   memory-sequential execution modes.
 * `.FP` blocks mirror `.STD` transitions but mark a floating-point execution context.
 
-Block types beyond the scalar core (e.g. `.TMA`, `.CUBE`, `.TEPL`, `.VPAR`, `.VSEQ`, `.FIXP`) appear in the catalog as
-Block Split forms. `TMA`, `CUBE`, and `TEPL` selector/descriptor semantics are defined by the v0.57 catalog; selector
-space not explicitly assigned by the catalog is reserved and must not acquire ad hoc semantics.
+Block types beyond the scalar core use the named TMA and CUBE direct forms plus the raw TEPL Mode/Function form.
+Selector space not explicitly assigned by the PTO ISA 0.57.1 catalog is reserved and must not acquire ad hoc semantics.
 
 [[blockisa-tile]]
 === Tile blocks (TAU)
 
 Linx defines *tile blocks* for hardware-accelerated tile operations. A tile block is a basic block that:
 
-* starts with a typed tile/vector header (`BSTART.TMA`, `BSTART.CUBE`, `BSTART.TEPL`, `BSTART.MPAR`, `BSTART.MSEQ`,
-  `BSTART.VPAR`, `BSTART.VSEQ`), and
+* starts with a tile/vector header (for example `BSTART.TLOAD`, `BSTART.TMATMUL`, `BSTART.TEPL`,
+  `BSTART.MPAR`, `BSTART.MSEQ`, `BSTART.VPAR`, or `BSTART.VSEQ`), and
 * ends at `BSTOP` / `C.BSTOP` or the next block start marker.
 
 Tile blocks operate on **tile registers** (see <<progmodel-tile>>), and use explicit per-block descriptors:
 
 * `B.IOT` describes tile inputs/outputs (including relative tile references and transfer sizing)
 * `B.IOR` describes GPR inputs/outputs for the block
-* `B.ARG` carries TMA layout-format selection and pad policy for the block
+* `B.DATR` carries operation-applicable datatype, rounding, saturation, layout, comparison, and pad/byte controls
 * `B.DIM` / `C.B.DIM*` may be used to provide block-local dimensions and valid masks via `LB0..LB2`
 
 Bring-up contract (v0.57 current profile):
 
-* Typed block starts are canonical (`BSTART.TMA`, `BSTART.CUBE`, `BSTART.TEPL`, `BSTART.MPAR`, `BSTART.MSEQ`, `BSTART.VPAR`,
-  `BSTART.VSEQ`).
+* Typed operation starts are canonical for TMA and CUBE. TEPL uses `BSTART.TEPL Mode, Function, DataType`.
 * Retired PAR-style block-start spellings are illegal and MUST be rejected.
 * `TLOAD`/`TSTORE` are the canonical memory-tile baseline for AI and rendering bring-up.
 * `TMOV` is the canonical tile-state move baseline operation in the TMA family.
@@ -229,7 +227,7 @@ Bring-up contract (v0.57 current profile):
 **Immutability rule (design intent):** a tile block consumes input tiles and produces a new destination tile; it does
 not mutate the input tiles in-place.
 
-NOTE: In the strict profile contract, `B.IOT` prints transfer size in KiB (`->t<1KB>`, `->acc<4KB>`)
+NOTE: In the strict profile contract, `B.IOT` prints transfer size in KiB (for example `->t<1KB>`)
 and uses `last` to mark the terminal descriptor in a block header chain. Descriptor metadata may be carried by multiple
 `B.IOR` and `B.IOT` entries in the same header; descriptors are consumed in header order.
 
@@ -243,10 +241,8 @@ extended below):
 ** `m#k` → tile-id `16+(k-1)` (16..23)
 ** `n#k` → tile-id `24+(k-1)` (24..31)
   These tile-ids name positions within the corresponding hand’s architectural tile-register queue.
-* `B.IOT` `SizeCode` maps to bytes as `bytes = 2^(SizeCode+4)` with strict architectural clamp to `0B..512KB`.
-* `B.IOT` (dynamic-size form) uses `RegSrc` to carry runtime output size. v0.57 accepts only values that decode
-  to `0B..512KB` (either direct `SizeCode` style values `5..8` or equivalent power-of-two byte counts).
-  Compiler/runtime MUST fail fast on out-of-range dynamic sizes.
+* `B.IOT` size codes 3 through 9 map to 128 B through 8 KiB. Every other code is illegal.
+* A runtime-resolved size must equal one of those accepted footprints. Compiler/runtime MUST fail fast otherwise.
 * `S0V` / `S1V` semantics are *inverted*: `0` means the corresponding `SrcTile*` is present as an input; `1` means absent.
   When a source is absent, its corresponding `SrcTile*` field is ignored and SHOULD be encoded as `0` in canonical v0.57 output.
 * `DstTile` encodes the destination *kind* and controls where the tile-producing engine allocates the output:
@@ -254,65 +250,67 @@ extended below):
 ** `1`: `u` hand (U queue)
 ** `2`: `m` hand (M queue)
 ** `3`: `n` hand (N queue)
-** `4`: implicit accumulator (`acc`)
-  (`acc`) is a singleton architectural accumulator in v0.57 (no encoded ACC depth/index).
+** `4..6`: reserved
+** `7`: illegal
+  ACC is singleton implicit state selected by CUBE function identity; it has no `B.IOT` code or depth/index.
 * For destination kinds `t/u/m/n`, the destination tile register is allocated implicitly as a **queue push**:
 ** the output becomes the new `hand#1` definition (for example `->u<4KB>` allocates a new `u#1`),
 ** existing definitions in that hand shift down (`hand#1→hand#2`, `hand#2→hand#3`, …),
-** the oldest definition (`hand#8`) is evicted.
+** allocation that would exceed the architectural queue/capacity limit raises a precise fault; there is no eviction or spill.
 ** for `B.IOT`, the `SizeCode` updates the newly allocated (`hand#1`) tile register’s tracked byte-size.
 * Input tile references (`t#k`/`u#k`/`m#k`/`n#k`) name a position in the corresponding **tile register queue**, where `k=1`
   is the most recent definition and larger `k` values refer to older definitions.
-* `.reuse` is a staged hint bit carried on input operands. In this bring-up profile, it is required to disassemble and
-  re-encode deterministically, but it does not change the queue indexing rules defined above.
+* `.reuse=0` releases an input only after successful consumer commit; `.reuse=1` retains it. Fault, retry, and squash preserve it.
 * Each `B.IOR` descriptor carries up to three source GPR bindings plus one destination GPR binding.
 * Canonical shader-kernel scalar imports are the ordered namespace `ri0..ri11`:
 ** bindings are allocated from repeated `B.IOR` descriptors in header order,
 ** within one descriptor, imports are assigned in `RegSrc0`, `RegSrc1`, `RegSrc2` order.
 * Each `B.IOT` descriptor carries up to two source-tile references plus one destination tile kind.
-* `TMATMUL` / `TMATMUL.ACC` use `SrcTile0/SrcTile1` as the two tile inputs; the output is the implicit accumulator (`->acc<...>`).
+* `TMATMUL` / `TMATMUL.ACC` use `SrcTile0/SrcTile1` as the two tile inputs; the output is implicit ACC state.
 * `group=0` means the header descriptor chain continues.
 * `group=1` is the terminal descriptor form in bring-up streams and is rendered as `last` in disassembly.
 * Archived raw material that relies on other `group` values is not part of canonical v0.57 and remains reserved/illegal.
 * `B.IOR` disassembly omits zero GPR inputs/outputs and prints the input list in encoding order (`RegSrc0`, `RegSrc1`, `RegSrc2`)
   (for example, `[s0,a6],[]`).
 
-v0.57 tile header encoding families (the bit layout is inherited unchanged
-from v0.57):
+v0.57.1 tile header encoding families:
 
 * `BSTART.TMA`: `31..27=DataType`, `26..25=00`, `24..20=Function`, `19..15=00010`, `14..0` fixed block-split tail.
-* `BSTART.CUBE`: `31..27=DataType`, `26..25=00`, `24..20=Function`, `19..15=00110`, `14..0` fixed block-split tail.
-* `BSTART.TEPL`: `31..27=DataType`, `26..25=01`, `24..15=TileOpcode`, `14..0` fixed block-split tail.
+* CUBE-family typed forms: `31..27=DataType`, `26..25=00`, `24..20=Function`, `19..15=00110`, `14..0` fixed block-split tail.
+* TEPL-family typed forms: `31..27=DataType`, `26..25=Mode`, `24..20=Function`, `19..0` fixed block-split tail.
 * `BSTART.VPAR`: `26..25=Mode`, `19..15=00100` with fixed block-split tail.
 * `BSTART.VSEQ`: `26..25=Mode`, `19..15=00101` with fixed block-split tail.
 
 v0.57 tile `DataType` field assignments (u5, inherited unchanged):
 
-* Floating: `FP64=0`, `FP32=1`, `FP16=2`, `FP8=3`, `BF16=6`, `FPL8=7`, `FP4=11`, `FPL4=12`.
-* Signed integer: `INT64=16`, `INT32=17`, `INT16=18`, `INT8=19`, `INT4=20`.
-* Unsigned integer: `UINT64=24`, `UINT32=25`, `UINT16=26`, `UINT8=27`, `UINT4=28`.
-* Unassigned values are reserved and MUST NOT appear in canonical streams.
+* Floating: `FP64=0`, `FP32=1`, `TF32=2`, `HF32=3`, `FP16=4`, `BF16=5`,
+  `HiF8=6`, `E4M3=7`, `E5M2=8`, `E3M2=9`, `E2M3=10`,
+  `E2M1X2=11`, `E1M2X2=12`, `E8M0=13`, and `HiF4X2=14`.
+* Signed integer: `S64=16`, `S32=17`, `S16=18`, `S8=19`, `S4X2=20`.
+* Unsigned integer: `U64=24`, `U32=25`, `U16=26`, `U8=27`, `U4X2=28`.
+* Codes 15, 21-23, and 29-30 are reserved. Code 31 is illegal.
 
 v0.57 named-form policy (normative):
 
-* TMA, CUBE, and TEPL name binary encoding families. The TMA family has no
-  generic legal assembly form; each allocated function has an exact
-  `BSTART.<operation>` instruction form.
+* TMA, CUBE, and TEPL name binary encoding families. TMA and CUBE have no generic
+  legal assembly form; each allocated function has an exact `BSTART.<operation>` form.
+  TEPL has one legal `BSTART.TEPL Mode, Function, DataType` form whose accepted
+  mode/function pairs come from the locked catalog.
 * Named mnemonics are explicit v0.57 instruction forms in the golden catalog
   and resolve to encoding selectors:
-** `BSTART.TLOAD` -> `BSTART.TMA Function=0`
-** `BSTART.TSTORE` -> `BSTART.TMA Function=1`
-** `BSTART.TMOV` -> `BSTART.TMA Function=2`
-** `BSTART.TPREFETCH` -> `BSTART.TMA Function=3`
-** `BSTART.MGATHER` -> `BSTART.TMA Function=4`
-** `BSTART.MSCATTER` -> `BSTART.TMA Function=5`
-** `BSTART.MGATHER.MASK` -> `BSTART.TMA Function=6`
-** `BSTART.MSCATTER.MASK` -> `BSTART.TMA Function=7`
-** `BSTART.MGATHER.CAS` -> `BSTART.TMA Function=8`
-** `BSTART.TMATMUL` -> `BSTART.CUBE Function=0`
-** `BSTART.TMATMUL.ACC` -> `BSTART.CUBE Function=2`
-** `BSTART.ACCCVT` -> `BSTART.CUBE Function=8`
-** `BSTART.TADD`, `BSTART.TSUB`, `BSTART.TROWMAX`, ... -> `BSTART.TEPL TileOpcode=<assigned code>`
+** `BSTART.TLOAD` -> TMA `Function=0`
+** `BSTART.TSTORE` -> TMA `Function=1`
+** `BSTART.TMOV` -> TMA `Function=2`
+** `BSTART.TPREFETCH` -> TMA `Function=3`
+** `BSTART.MGATHER` -> TMA `Function=4`
+** `BSTART.MSCATTER` -> TMA `Function=5`
+** `BSTART.MGATHER.MASK` -> TMA `Function=6`
+** `BSTART.MSCATTER.MASK` -> TMA `Function=7`
+** `BSTART.MGATHER.CAS` -> TMA `Function=8`
+** `BSTART.TMATMUL` -> CUBE `Function=0`
+** `BSTART.TMATMUL.ACC` -> CUBE `Function=2`
+** `BSTART.ACCCVT` -> CUBE `Function=8`
+** `TADD`, `TSUB`, `TROWMAX`, ... -> `BSTART.TEPL Mode=<assigned mode>, Function=<assigned function>`
 * TMA `Function=9..31` encodings are reserved and MUST raise an
   illegal-instruction exception. They are not instruction forms and MUST NOT
   contribute to legal-form or executable-coverage denominators.
@@ -338,49 +336,33 @@ v0.57 CUBE named `Function` assignments:
 * `8` => `ACCCVT`
 * `16/17/18` => `TGEMV` / `TGEMV.BIAS` / `TGEMV.ACC`
 * `20/21/22` => `TGEMVMX` / `TGEMVMX.BIAS` / `TGEMVMX.ACC`
-* Other 5-bit CUBE values retain the generic
-  `BSTART.CUBE Function, DataType` spelling.
+* Other 5-bit CUBE values are reserved and raise an illegal-instruction exception.
 
-v0.57 TEPL tile opcode allocation policy:
+v0.57.1 TEPL mode/function allocation policy:
 
 * The authoritative machine-readable selector map is
   `isa/v0.57/state/pto_encoding_map.json`.
-* The inherited v0.57 assignments use a packed low-6-bit selector inside
-  the 10-bit `TileOpcode` field:
-** `TileOpcode[5]` is the 1-bit TEPL mode selector.
-** `TileOpcode[4:0]` is the TEPL function selector.
-** canonical packed rule: `TileOpcode = (Mode << 5) | Function`.
-* `Mode=0` defines the 32-entry base TEPL function set:
-** `0x00=TADD`, `0x01=TSUB`, `0x02=TMUL`, `0x03=TDIV`, `0x04=TMAX`, `0x05=TMIN`, `0x06=TAND`, `0x07=TOR`
-** `0x08=TXOR`, `0x09=TSHL`, `0x0A=TSHR`, `0x0B=TRELU`, `0x0C=TPRELU`, `0x0D=TCVT`, `0x0E=TEXP`, `0x0F=TLOG`
-** `0x10=TSQRT`, `0x11=TRSQRT`, `0x12=TROWMAX`, `0x13=TROWMIN`, `0x14=TROWSUM`, `0x15=TCOLMAX`, `0x16=TCOLMIN`,
-   `0x17=TCOLSUM`
-** `0x18=TRECIP`, `0x19=TEXPANDS`, `0x1A=TGATHER`, `0x1B=TSCATTER`, `0x1C=TRESHAPE`, `0x1D=TTRANSPOSE`,
-   `0x1E=TCOLEXPAND`, `0x1F=TROWEXPAND`
-* `Mode=1` defines the scalar-RHS TEPL extension window:
-** `0x20=TADDS`, `0x21=TSUBS`, `0x22=TMULS`, `0x23=TDIVS`, `0x24=TMAXS`, `0x25=TMINS`, `0x26=TANDS`,
-   `0x27=TORS`, `0x28=TXORS`, `0x29=TSHLS`, `0x2A=TSHRS`
-* v0.57 allocates every selector in `0x02B..0x048`, plus the explicitly
-  assigned banks `0x080..0x08B`, `0x0C0..0x0C8`, and `0x0E0..0x0E3`.
-  These values are direct 10-bit selectors and are not decoded through the
-  inherited Mode/Function interpretation.
+* The raw header carries `Mode[1:0]` and `Function[4:0]`.
+* The canonical logical selector is `(Mode << 5) | Function`.
+* The catalog assigns exactly 98 unique selectors across Modes 0 through 3;
+  the remaining 30 selector positions are reserved and illegal.
+* Canonical names include `TTRANS`; `TTRANSPOSE` and `TSORT32` are
+  migration-only source aliases and never decode as instruction identities.
 * Tile-scalar extension ops require `B.IOR` scalar RHS binding as defined by the op profile.
   - NOTE (toolchain convention): when a TEPL op requires scalar RHS data, place the binding in the first `B.IOR` entry
     where practical, even though implementations must accept any `B.IOR` position defined by the op profile.
 
-Unassigned tile opcode values are reserved/illegal in canonical v0.57.
+Unassigned TEPL mode/function pairs are reserved/illegal in canonical v0.57.1.
 Canonical toolchains MUST reject them and implementations MUST NOT assign ad
-hoc semantics. In particular, `0x049..0x07F`, `0x08C..0x0BF`,
-`0x0C9..0x0DF`, and `0x0E4..0x3FF` are reserved.
+hoc semantics.
 
 v0.57 `TMOV` contracts:
 
 * `TMOV` is a tile-state operation; it MUST NOT directly access GM memory.
 * For `DstTile` kinds `t/u/m/n`, destination allocation is queue-push only (new `hand#1`).
 * Explicit destination depth encoding (`->t#k`/`->u#k`/`->m#k`/`->n#k`) is not part of v0.57.
-* `B.IOT` size semantics for `TMOV` follow the same strict `SizeCode` clamp (`0B..512KB`) as `TLOAD/TSTORE`.
-* `B.ARG` provides TMOV mode selection in the canonical profile; `V2V` and `A2V` are defined, and all other modes are
-  reserved/illegal until a future catalog revision assigns them.
+* `B.IOT` size codes 3 through 9 select 128 B through 8 KiB; other codes are illegal.
+* Layout conversion is selected only by an operation-applicable `B.DATR.Layout` value and is capability gated.
 
 v0.57 TMA assignments:
 
@@ -401,40 +383,34 @@ v0.57 TMA assignments:
   checks and fault behavior required for the corresponding `TLOAD` footprint.
 * Generic mixed TMA textual forms remain illegal in canonical v0.57 sources. The legal public spelling is the assigned
   `BSTART.<alias>` form.
-* The expanded PTO map is frozen in `isa/v0.57/state/pto_encoding_map.json`: all 111 workbook rows have one TMA,
-  CUBE, or TEPL disposition, and review-only names are rejected.
-* v0.57 adds named CUBE aliases for Functions 1, 4-6, 16-18, and 20-22. The inherited generic
-  `BSTART.CUBE Function, DataType` form remains legal, so values without a named alias retain only the generic decode.
+* The PTO map is frozen in `isa/v0.57/state/pto_encoding_map.json`: exactly 120 operations have one TMA,
+  CUBE, or TEPL disposition, and deleted or review-only names are rejected.
+* CUBE Functions 1, 4-6, 16-18, and 20-22 have typed operation forms; every other unassigned function is illegal.
 
 v0.57 block split patterns and per-family constraints:
 
-* `BSTART.TLOAD` / `BSTART.TSTORE` (alias of `BSTART.TMA Function=0/1`):
-** require `B.ARG` for layout/pad selection.
+* `BSTART.TLOAD` / `BSTART.TSTORE` (named TMA Functions 0/1):
+** use operation-applicable `B.DATR` layout/pad controls; inapplicable non-zero fields are illegal.
 ** require at least one `B.IOR` binding carrying base/stride arguments (strict profile convention: stride and base are explicit scalar inputs).
 ** strict binding convention is `RegSrc0=stride/ld`, `RegSrc1=base` when both are present.
 ** require tile binding via `B.IOT`.
 ** are header-driven block commands (no SIMT body; do not use `B.TEXT`).
 * `BSTART.TMATMUL`, `BSTART.TMATMUL.BIAS`, `BSTART.TMATMUL.ACC`, `BSTART.TMATMULMX*`,
-  `BSTART.TGEMV*`, and `BSTART.TGEMVMX*` (named aliases of their assigned CUBE functions):
+  `BSTART.TGEMV*`, and `BSTART.TGEMVMX*` (assigned named CUBE-family functions):
 ** require `B.DIM`/`C.B.DIM*` with `LB0/LB1/LB2` bound as `m/n/k`.
-** require two source tile inputs via `B.IOT`.
-** both commands target the singleton implicit accumulator domain (`->acc`).
+** bind the exact source roles from `pto_ops.json` via `B.IOT` (left/right, plus bias or scale sources where applicable).
+** write the singleton implicit accumulator; B.IOT carries no ACC source or destination code.
 ** `TMATMUL` seeds/replaces accumulator state; `TMATMUL.ACC` accumulates into the current accumulator state.
 ** no explicit accumulator tile id is encoded in the inherited descriptors.
 ** strict chain contract: `TMATMUL` starts ACC state, `TMATMUL.ACC` may repeat, and `ACCCVT` materializes tile output.
 ** are header-driven block commands (no SIMT body; do not use `B.TEXT`).
-* `BSTART.ACCCVT` (alias of `BSTART.CUBE Function=8`):
-** requires quantization arguments.
-** quantization arguments are carried by `B.ARG` (quantization mode) plus `B.IOR` scalar bindings (`scale` and
-   `zero-point` are required; optional extra scalar controls are profile-defined).
+* `BSTART.ACCCVT` (named CUBE-family Function 8):
+** conversion controls are carried by the operation-applicable `B.DATR` fields `Sat`, `Canonicalize`, `DataType`, `RMode`, and `Layout`.
 ** consumes the singleton implicit accumulator state and writes a converted tile destination.
 ** descriptors bind only destination tile metadata (`->t/u/m/n<size>`); no accumulator source id is encoded.
 ** is header-driven (no SIMT body; do not use `B.TEXT`).
 * `BSTART.TEPL`:
-** operation is selected only by the tile opcode (`TileOpcode`).
-** inherited selectors through `0x02A` preserve the v0.57 packed
-   `Mode/Function` identity; v0.57 selectors above that range use their
-   explicit manifest values.
+** operation is selected only by the raw `Mode` and `Function` fields.
 ** descriptor requirements are op-profile-specific, but tile and scalar bindings MUST still be expressed through block descriptors.
 ** PTO template-op forms (`TADD`, `TSUB`, `TROWMAX`, etc.) are header-driven in v0.57 (no SIMT body).
 * `BSTART.VPAR` / `BSTART.VSEQ`:
@@ -448,9 +424,9 @@ Future encoding-space growth policy:
 ** `isa/v0.57/opcodes/lx_32.opc`
 ** the alias table above
 ** strict profile checks and regression tests.
-* TEPL uses a 10-bit tile opcode selector (`TileOpcode`, 0..1023). New
-  assignments MUST be added to the v0.57 manifest and MUST NOT occupy a
-  reserved hole implicitly.
+* TEPL uses a two-bit Mode and five-bit Function selector. New assignments
+  MUST be added to a later normative manifest and MUST NOT occupy a reserved
+  pair implicitly.
 * Future banks MUST be assigned explicitly by a later revision and carried by
   its machine-readable selector manifest.
 
@@ -474,12 +450,11 @@ The v0.57 catalog includes the following descriptor families:
   - `B.IOR`: binds GPR inputs/outputs for a block.
   - `B.IOT`: binds tile inputs/outputs for a block (including optional input reuse and transfer sizing).
 * **Block arguments**
-  - `B.ARG`: writes a per-block argument used by TMA tile load/store pipelines (layout format + pad policy).
   - `B.DIM`: writes a block argument register (`LB0`–`LB2`) used for loop bounds, dimensions, and valid masks.
 * **Block attributes and hints**
-  - `B.CATR/B.DATR`: full encoded fields are `{C, DR, DataLayout[4:0], DataType[4:0], PadValue[4:0], T, aq, atom, far, rl}`.
-    Strict TMA execution does not source dtype/layout/pad from `B.CATR/B.DATR`; layout/pad come from `B.ARG` and datatype from
-    `BSTART.<tile-header>`.
+  - `B.CATR`: controls dependency, trap/far, atomic, acquire, and release behavior.
+  - `B.DATR`: carries `CMode`, the PadValue/ByteId union, saturation, canonicalization,
+    datatype, rounding mode, and layout. Every non-zero field must be applicable to the selected operation.
   - `B.HINT`: sets performance hints (branch likelihood, temperature, prefetch sizing, trace markers).
 * **Text/offset annotations**
   - `B.TEXT`: in a decoupled block header, selects the out-of-line body entrypoint (`BodyTPC`). In coupled blocks it
@@ -517,25 +492,25 @@ AI-oriented behavior:
 The canonical v0.57 auto-mode profile maps PTO tile primitives to typed TAU block headers and descriptors:
 
 * `PTO TLOAD`:
-  `BSTART.TLOAD` + `B.DIM(LB0/LB1/LB2)` + `B.ARG` + `B.IOR*` + `B.IOT`
+  `BSTART.TLOAD` + `B.DIM(LB0/LB1/LB2)` + applicable `B.DATR` + `B.IOR*` + `B.IOT`
 * `PTO TSTORE`:
-  `BSTART.TSTORE` + `B.DIM(LB0/LB1/LB2)` + `B.ARG` + `B.IOR*` + `B.IOT`
+  `BSTART.TSTORE` + `B.DIM(LB0/LB1/LB2)` + applicable `B.DATR` + `B.IOR*` + `B.IOT`
 * `PTO TMOV`:
-  `BSTART.TMOV` + `B.ARG` + optional `B.DIM/B.IOR` + `B.IOT`
+  `BSTART.TMOV` + applicable `B.DATR` + optional `B.DIM/B.IOR` + `B.IOT`
 * `PTO TMATMUL`:
   `BSTART.TMATMUL` (+ ACC convert/output block when needed)
 * `PTO TMATMUL_ACC`:
   `BSTART.TMATMUL.ACC` (+ ACC convert/output block when needed)
-* `PTO vec template ops` (`TADD`, `TSUB`, `TROWMAX`, ...):
-  `BSTART.TEPL(<TileOpcode>)` + descriptor stream (`B.ARG`/`B.IOR`/`B.IOT`) as required by the op profile.
+* `PTO template ops` (`TADD`, `TSUB`, `TROWMAX`, ...):
+  `BSTART.TEPL` with assigned Mode/Function plus the descriptor stream required by the operation contract.
 
 Normative notes:
 
-* `B.ARG + B.IOR` are both required for descriptor-rich `TLOAD/TSTORE`.
+* `B.DATR + B.IOR` are required when their operation-specific contracts request datatype/layout/pad and scalar bindings.
 * `TLOAD/TSTORE` dtype comes from encoded `BSTART.TMA` selector state (surfaced as `BSTART.TLOAD/BSTART.TSTORE` aliases),
-  and pad policy comes from `B.ARG` (not `B.CATR/B.DATR`).
-* `TMOV` mode/convert policy comes from `B.ARG`; destination tile kind/size comes from `B.IOT`.
-* TEPL template-op selection is carried by `BSTART.TEPL TileOpcode`; no standalone `TVEC` header encoding exists.
+  and applicable pad/layout policy comes from `B.DATR`.
+* `TMOV` layout/convert policy comes from applicable `B.DATR` fields; destination tile kind/size comes from `B.IOT`.
+* TEPL template-op selection is carried by raw Mode/Function fields; no standalone `TVEC` header encoding exists.
 * Multiple `B.IOR` and `B.IOT` descriptors in one header are legal and consumed in order.
 * Strict CUBE chain: `TMATMUL` seeds ACC, zero or more `TMATMUL.ACC` update ACC, then `ACCCVT` materializes tile output.
 * Compiler strict checks MUST reject `TMATMUL.ACC`/`ACCCVT` when the accumulator dependency does not derive from
@@ -697,7 +672,7 @@ The architectural interface between the first and second layer is a block comman
    live-outs.
 ** `B.IOT`: performs tile rename, computes input/output tile base addresses, and packs those addresses into the command
    payload.
-** `B.ARG` / `B.CATR/B.DATR`: pack block-type-defined immediates/attributes.
+** `B.CATR/B.DATR`: pack block-type-defined control and data attributes.
 ** `B.DIM`: packs block dimensions (`LB0..LB2`) for SIMT/vector replay and for tile engines.
 ** `B.TEXT`: packs the out-of-line body `TPC` for decoupled blocks.
 * `BSTOP` (or an implicit boundary at the next block start marker) finalizes the command and dispatches it to the
@@ -714,9 +689,9 @@ The architectural interface between the first and second layer is a block comman
 `BSTART.TEPL` provides a generic extensible block type for implementation-defined in-core accelerators and for
 PTO template-op families (`TADD`, `TSUB`, `TROWMAX`, etc.).
 
-* `BSTART.TEPL` headers use the same descriptor families (`B.CATR/B.DATR`, `B.ARG`, `B.IOR`, `B.IOT`) as other decoupled
+* TEPL-family typed headers use the same descriptor families (`B.CATR/B.DATR`, `B.IOR`, `B.IOT`) as other decoupled
   blocks.
-* `TileOpcode` is the tile opcode selector; `DataType` is carried in the same header.
+* `Mode` and `Function` select the operation; `DataType` is carried in the same header.
 * TEPL template ops are header-driven and do not require a separate SIMT body selector.
 * `BSTART.TEPL` blocks must follow the same block-boundary legality rules and must not directly bypass the memory and
   privilege contracts defined in this manual.
diff --git a/docs/architecture/isa-manual/src/chapters/07_templates.adoc b/docs/architecture/isa-manual/src/chapters/07_templates.adoc
index 5984e09e..08ef97ee 100644
--- a/docs/architecture/isa-manual/src/chapters/07_templates.adoc
+++ b/docs/architecture/isa-manual/src/chapters/07_templates.adoc
@@ -27,7 +27,7 @@ For `TemplateKind.class=0` (marker/template opcodes), the following mnemonic-enu
 * `8 = ERCOV`
 * `9..255` reserved
 
-NOTE: For `TemplateKind.class=1` (TEPL templates), identification uses the tile opcode selector (`TileOpcode`), not this enum.
+NOTE: For `TemplateKind.class=1` (TEPL templates), identification uses `(Mode << 5) | Function`, not this enum.
 
 Template blocks execute via a **code-template generator** that emits a sequence of internal micro-operations
 (*micro-ops*) based on architectural register inputs.
diff --git a/docs/architecture/isa-manual/src/chapters/08_tile_blocks.adoc b/docs/architecture/isa-manual/src/chapters/08_tile_blocks.adoc
index f79c11bb..41792b6e 100644
--- a/docs/architecture/isa-manual/src/chapters/08_tile_blocks.adoc
+++ b/docs/architecture/isa-manual/src/chapters/08_tile_blocks.adoc
@@ -22,9 +22,9 @@ Unless stated otherwise:
 Tile/vector block headers use the standard descriptor families:
 
 * `B.DIM`  — dimension/loop counters and/or operand extents
-* `B.ARG`  — layout and per-op argument payload (layout defaults may exist per-op)
+* `B.DATR` — operation-applicable datatype, layout, rounding, comparison, and pad/byte controls
 * `B.IOR`  — stride/base/scalar register bindings (memory addressing)
-* `B.IOT` — tile binding and tile size (strict range `0B..512KB`)
+* `B.IOT` — tile binding and tile size (codes 3 through 9 select 128 B through 8 KiB)
 * `B.TEXT` — body pointer for SIMT vector blocks (group-granular kernel body)
 
 [[tileblocks-vvec]]
@@ -64,7 +64,7 @@ MissingDescFamily numeric IDs (from `TRAPARG0[7:0]`, for quick reference):
 * `0 = B.* (generic descriptor stream / non-family-specific)`
 * `1 = B.DIM`
 * `2 = B.TEXT`
-* `3 = B.ARG`
+* `3 = B.CATR/B.DATR`
 * `4 = B.IOR`
 * `5 = B.IOT`
 Other descriptors (tile inputs, register in/out bindings, etc.) are kernel-defined and may be mandatory for specific
@@ -79,7 +79,7 @@ The rendering-oriented v0.57 profile inherits the frozen v0.57 tile conventions
 * the canonical carrier is a 4KB `1024x1` row-major tile,
 * fragment and hot-state transport is SoA-oriented,
 * TAU operations are tile-to-tile only,
-* small or rarely-changing state is descriptor-driven (`B.ARG`, `B.IOR`), while hot/large state uses dedicated StateTiles,
+* small or rarely-changing state is descriptor-driven (`B.DATR`, `B.DIM`, `B.IOR`), while hot/large state uses dedicated StateTiles,
 * `MPAR` VEC kernels are the required functional fallback for rendering PTOs when no TAU hardening exists.
 
 [[tileblocks-tma]]
@@ -91,7 +91,7 @@ These blocks do not have a SIMT body (`B.TEXT` is not used).
 
 Mandatory header descriptors:
 
-* `B.ARG` is **mandatory** (layout/pad).
+* `B.DATR` is required when the operation uses non-default layout/pad controls.
 * `B.IOR` is **mandatory** (stride/base).
 * `B.IOT` is **mandatory** (tile binding + tile size).
 
@@ -111,14 +111,14 @@ Mandatory header descriptors:
 
 Optional descriptors:
 
-* `B.ARG` is optional when the layout is default **ND**.
-  - Normative defaulting: if `B.ARG` is absent, the layout is **ND**.
-* `B.ARG` is required when non-default layout/transform is requested (e.g. transpose/reshape).
+* `B.DATR` selects an operation-applicable layout conversion; NORM is the mandatory default and other layouts are capability gated.
 
 [[tileblocks-cube]]
 === CUBE / tensor blocks (`TMATMUL`, `TMATMUL.ACC`, `ACCCVT`)
 
-`BSTART.TMATMUL` / `BSTART.TMATMUL.ACC` / `BSTART.ACCCVT` are aliases of `BSTART.CUBE` selectors.
+`BSTART.TMATMUL`, `BSTART.TMATMUL.ACC`, and `BSTART.ACCCVT` are named
+CUBE-family forms. Their assigned function values are part of the frozen
+0.57.1 selector map; no generic executable `BSTART.CUBE` form exists.
 
 These blocks do not have a SIMT body (`B.TEXT` is not used).
 
@@ -128,7 +128,7 @@ Mandatory header descriptors:
 
 * `B.DIM` is **mandatory** and specifies `m/n/k` via `LB0/LB1/LB2`.
 * `B.IOT` is **mandatory** (bind operand tiles and sizes).
-* `B.ARG` is **mandatory** (CUBE uses a fixed layout contract for left/right matrices).
+* `B.DATR` is required when a non-default, supported matrix layout is selected.
 
 ==== `ACCCVT`
 
@@ -141,4 +141,4 @@ Mandatory header descriptors:
 
 * `B.DIM` is **mandatory**.
 * `B.IOT` is **mandatory** (bind destination tile + size).
-* `B.ARG` + `B.IOR` are **mandatory** (quantization arguments and scalar bindings).
+* Applicable `B.DATR` fields plus `B.IOR` are **mandatory** for quantization controls and scalar bindings.
diff --git a/docs/architecture/isa-manual/src/chapters/09_memory_operations.adoc b/docs/architecture/isa-manual/src/chapters/09_memory_operations.adoc
index 23e0d2b4..0939547c 100644
--- a/docs/architecture/isa-manual/src/chapters/09_memory_operations.adoc
+++ b/docs/architecture/isa-manual/src/chapters/09_memory_operations.adoc
@@ -63,7 +63,7 @@ Rules:
 
 * Address footprint is 2D and derived from descriptor state:
   - dimensions from `LB0/LB1/LB2` (`B.DIM` / `C.B.DIM*`)
-  - layout-conversion selector and pad policy from `B.ARG`
+  - layout-conversion selector and pad policy from `B.DATR`
   - GPR bindings from one-or-more `B.IOR` descriptors
   - tile IO bindings and transfer size from one-or-more `B.IOT`
   - element data type from `BSTART.TMA`
@@ -75,13 +75,11 @@ Layout and dimension contract (v0.57 current profile for TMA):
   - `DN` (column-major),
   - `NZ` (inner-block row-major + inter-block column-major),
   - `ZN` (inner-block column-major + inter-block row-major).
-* `B.ARG` encodes one unified format selector for the current TMA tile-memory operation.
-* The only legal format selectors are:
-  - `NORM.normal` (source and destination layout are the same),
-  - `ND2NZ.normal`,
-  - `ND2ZN.normal`,
-  - `DN2NZ.normal`,
-  - `DN2ZN.normal`.
+* `B.DATR.Layout` encodes the layout selector for the current TMA operation.
+* `NORM` (code 0) is mandatory. Accepted conversion codes are
+  `1, 3, 4, 6, 8, 9, 17, 18, 20, 27, 28, 30`; they require an advertised
+  capability and fault precisely before effects when unsupported. Layouts
+  involving `ZZ` or `NN` are reserved.
 * For both `TLOAD` and `TSTORE`, `NZ`/`ZN` always denotes the TR-side layout; GM-side layout is `ND` or `DN`.
 * `LB0/LB1/LB2` are interpreted for TLOAD/TSTORE as:
   - `LB0`: GM-side inner element count
@@ -110,7 +108,7 @@ Layout and dimension contract (v0.57 current profile for TMA):
 Padding contract (TLOAD):
 
 * If TR-side logical size is larger than GM-side logical size, elements outside the GM-side footprint are synthesized in
-  TR according to the pad policy encoded in `B.ARG`.
+  TR according to the operation-applicable pad policy encoded in `B.DATR`.
 * Required pad policies are:
   - `Null`: implementation-defined non-deterministic fill (bring-up model may use deterministic pseudo-random fill),
   - `Zero`: fill with numeric zero,
@@ -136,11 +134,10 @@ Bring-up (auto-mode) binding convention for `B.IOR` in `TLOAD/TSTORE`:
 
 Canonical v0.57 profile constraints:
 
-* `B.ARG + B.IOR` are mandatory in descriptor-rich `TLOAD/TSTORE` headers.
-* TMA execution state is not sourced from `B.CATR/B.DATR`; `TLOAD/TSTORE` consume only `BSTART/B.ARG/B.DIM/B.IOR/B.IOT`.
+* Applicable `B.DATR` fields plus `B.IOR` are mandatory in descriptor-rich `TLOAD/TSTORE` headers.
+* TMA execution consumes the typed block start and applicable `B.CATR/B.DATR/B.DIM/B.IOR/B.IOT` state.
 * Repeated `B.IOR` and repeated `B.IOT` are legal and are consumed in header order.
-* `B.IOT` dynamic-size descriptors are legal only when `RegSrc` resolves to strict `0B..512KB`; runtime rejects invalid
-  dynamic sizes.
+* A runtime-resolved `B.IOT` size is legal only when it equals an accepted 128 B through 8 KiB footprint.
 * For bring-up code size, emit `C.B.DIMI` for `LB0/LB1/LB2` when the value fits in `imm8` (and `RegSrc=zero`).
 * Raw `group=2` material and broad fixed-pipe/TCVT metadata flows are reserved/illegal in canonical v0.57 until a future
   catalog revision assigns explicit semantics.
@@ -155,7 +152,7 @@ For completeness: v0.57 also permits non-memory typed TMA headers `BSTART.TMOV <
 (encoding: `BSTART.TMA Function=2`), but those are governed by <<blockisa-tile>> (not by memory-operation semantics).
 
 `B.IOT` descriptor rendering uses `last` for the terminal descriptor and prints transfer footprints in KiB (for example
-`->t<1KB>`, `->acc<4KB>`). The strict architectural range is `0B..512KB`.
+`->t<1KB>`). ACC is implicit and is never encoded as a `B.IOT` identity.
 
 [[memory-mcall]]
 === Shader-kernel boundary semantics (`MPAR` / `MSEQ`)
diff --git a/docs/architecture/isa-manual/src/chapters/10_system_and_privilege.adoc b/docs/architecture/isa-manual/src/chapters/10_system_and_privilege.adoc
index e2c685be..811b2198 100644
--- a/docs/architecture/isa-manual/src/chapters/10_system_and_privilege.adoc
+++ b/docs/architecture/isa-manual/src/chapters/10_system_and_privilege.adoc
@@ -223,7 +223,7 @@ Template replay flags (bring-up):
 * Implementations SHOULD expose a single EBARG register `EBARG_TPLFLAGS_ACRm` with template trap/replay flags. The bit layout is defined in <<ssr-ebarg>> (see `EBARG_TPLFLAGS_ACRn`).
 * `TPL_ID` for marker templates (`TemplateKind.class=0`) uses the mnemonic-enum mapping in <<templates-tplid>>.
 * For marker templates (`TemplateKind.class=0`), `TPL_ID_PRESENT` MUST be `1` (reporting is required).
-* For TEPL templates (`TemplateKind.class=1`), `TPL_ID_PRESENT` MUST be `1` and `TPL_ID` MUST carry the raw tile opcode selector (`TileOpcode`).
+* For TEPL templates (`TemplateKind.class=1`), `TPL_ID_PRESENT` MUST be `1` and `TPL_ID` MUST carry `(Mode << 5) | Function`.
 * `TPL_REDO_OK=1`: handler may restart the template from the beginning only when no externally visible partial side effects exist.
 * `TPL_RESUME_OK=1`: template supports and permits resume via an `EBSTATE` snapshot.
 * `TPL_PHASE` standard meanings:
@@ -261,7 +261,7 @@ NOTE: Restartable body-fetch faults are represented by the underlying MMU transl
       - `0 = B.* (generic descriptor stream / non-family-specific)`
       - `1 = B.DIM`
       - `2 = B.TEXT`
-      - `3 = B.ARG`
+      - `3 = B.CATR/B.DATR`
       - `4 = B.IOR`
       - `5 = B.IOT`
     - `TRAPARG0[15:8] = MissingDetail` (standard meanings):
@@ -272,7 +272,7 @@ NOTE: Restartable body-fetch faults are represented by the underlying MMU transl
     - upper bits reserved `0`
   - If multiple mandatory descriptor families are missing, implementations MUST report exactly one missing family.
     The reporting priority order is:
-    1. `B.ARG`
+    1. `B.CATR/B.DATR`
     2. `B.TEXT`
     3. `B.IOT`
     4. `B.IOR`
@@ -346,7 +346,7 @@ NOTE: earlier draft text previously used `E_INST(EC_ILLEGAL)` and `E_INST(EC_PAR
 For system calls (`TRAPNUM=SCALL` in v0.2), routing is defined by the `ACRC` `request_type` rules above.
 
 [[system-template-integrity-fail]]
-====== Template-integrity `ASSERT_FAIL`
+===== Template-integrity `ASSERT_FAIL`
 
 `ASSERT_FAIL (52)` has two distinct producers in v0.57:
 
@@ -490,7 +490,7 @@ Unless otherwise specified, fields are **XLEN** wide. Addresses are byte address
 * `BSTATE.Template` (template blocks such as `FENTRY`/`FEXIT`/`FRET.*`/`MCOPY`/`MSET`):
 ** `TemplateKind`: which template is executing (packed `class,id`).
 *** `class=0`: marker/template opcodes (`FENTRY`/`FEXIT`/`FRET.*`/`MCOPY`/`MSET`/...) with `id` = opcode-specific enum.
-*** `class=1`: `BSTART.TEPL` templates with `id` = tile opcode (`TileOpcode`, 0..1023).
+*** `class=1`: TEPL templates with `id = (Mode << 5) | Function` (0..127).
 *** `class=2`: reserved for future (implementation-defined templates).
 *** `class=3`: reserved.
 ** `StepIndex`: micro-op progress cursor.
diff --git a/docs/architecture/isa-manual/src/chapters/15_bbd.adoc b/docs/architecture/isa-manual/src/chapters/15_bbd.adoc
index 0585c175..1e91147d 100644
--- a/docs/architecture/isa-manual/src/chapters/15_bbd.adoc
+++ b/docs/architecture/isa-manual/src/chapters/15_bbd.adoc
@@ -6,7 +6,7 @@
 
 The Block Boundary Delimiters (BBD) group defines the instructions that mark the beginning and end of template blocks and carry block-transition metadata. The block-structured control-flow model is defined in <<blockisa>>; this chapter documents the individual instruction forms.
 
-**Block start** (`BSTART.*`): a `BSTART.*` both terminates the current block and begins the next block. It encodes the target block type (`.STD`, `.SYS`, `.FP`, `.MPAR`, `.MSEQ`, `.VPAR`, `.VSEQ`, `.TMA`, `.CUBE`, `.TEPL`, `.FIXP`) and the transition kind (`FALL`, `DIRECT`, `COND`, `CALL`, `IND`, `ICALL`, `RET`). A bare `CALL` transition records only its branch target and preserves `ra`; a returning call is preceded immediately by `SETRET` or `C.SETRET` carrying an explicit return label. Compressed `C.BSTART.*` forms encode the most common transitions in 16 bits.
+**Block start** (`BSTART.*`): a `BSTART.*` both terminates the current block and begins the next block. It encodes a scalar (`.STD`, `.SYS`, `.FP`), parallel (`.MPAR`, `.MSEQ`, `.VPAR`, `.VSEQ`), named TMA/CUBE, or `.TEPL` target together with the transition kind (`FALL`, `DIRECT`, `COND`, `CALL`, `IND`, `ICALL`, `RET`). Generic executable `.TMA`/`.CUBE` and retired `.FIXP` spellings are not part of 0.57.1. A bare `CALL` transition records only its branch target and preserves `ra`; a returning call is preceded immediately by `SETRET` or `C.SETRET` carrying an explicit return label. Compressed `C.BSTART.*` forms encode the most common transitions in 16 bits.
 
 **Block stop** (`BSTOP` / `C.BSTOP`): terminates the current block and commits the block state in `BARG`. For decoupled blocks, this is the point where the PE receives and begins executing the command. Note: `C.BSTOP` is encoded as all-zeros in the 16-bit space; it also serves as an invalid/reserved encoding in some tooling conventions.
 
diff --git a/docs/architecture/isa-manual/src/chapters/17_cmd.adoc b/docs/architecture/isa-manual/src/chapters/17_cmd.adoc
index 2e7bba21..11d5671e 100644
--- a/docs/architecture/isa-manual/src/chapters/17_cmd.adoc
+++ b/docs/architecture/isa-manual/src/chapters/17_cmd.adoc
@@ -4,19 +4,18 @@
 [[chapter_cmd]]
 == CMD - Command and Control
 
-The Command (CMD) group covers the block-split instruction forms (typed `BSTART.*`, `BSTOP`), template blocks (`FENTRY`, `FEXIT`, `FRET.*`), memory-block operations (`MCOPY`, `MSET`), cross-block calls (`XB`), and the header-descriptor instructions (`B.IOT`, `B.IOR`, `B.ARG`, `B.DIM`, `B.TEXT`, `B.HINT`, `B.CATR`, `B.DATR`) that carry per-block metadata for accelerator execution.
+The Command (CMD) group covers the block-split instruction forms (typed `BSTART.*`, `BSTOP`), template blocks (`FENTRY`, `FEXIT`, `FRET.*`), memory-block operations (`MCOPY`, `MSET`), cross-block calls (`XB`), and the header-descriptor instructions (`B.IOT`, `B.IOR`, `B.DIM`, `B.TEXT`, `B.HINT`, `B.CATR`, `B.DATR`) that carry per-block metadata for accelerator execution.
 
 **Block split instructions** (`BSTART.*`, `BSTOP`): these are the canonical forms for block-structured control flow. The typed `BSTART.<type>` forms select the execution model:
 
 * `.STD` / `.SYS` / `.FP` -- scalar execution.
 * `.MPAR` / `.MSEQ` -- SIMT parallel/sequential shader kernel launch.
 * `.VPAR` / `.VSEQ` -- tile-parallel/sequential vector execution (TVEC-equivalent).
-* `.TMA` (with aliases `TLOAD`, `TSTORE`, `TMOV`) -- tile memory access.
-* `.CUBE` (with aliases `TMATMUL`, `TMATMUL.ACC`, `ACCCVT`) -- tile matrix multiply.
-* `.TEPL` -- generic template-op accelerator.
-* `.FIXP` -- fixed-point block type.
+* TMA-family typed starts such as `TLOAD`, `TSTORE`, and `TMOV` -- tile memory access.
+* CUBE-family typed starts such as `TMATMUL`, `TMATMUL.ACC`, and `ACCCVT` -- tile matrix operations.
+* `BSTART.TEPL` with Mode/Function selection -- template operations such as `TADD`.
 
-Block-start aliases are canonical spelling in documentation and tests; the encoded contract is always the base selector (`BSTART.TMA`, `BSTART.CUBE`, etc.) with the function/code field carrying the operation.
+Typed block starts are the only public spellings for TMA and CUBE operations. TEPL uses the public `BSTART.TEPL` raw form with Mode/Function fields; unassigned selectors are illegal instructions.
 
 **Header descriptors**: tile and scalar block metadata is conveyed by descriptor instructions that must appear immediately after a block-start marker. Descriptors are consumed in program order and do not affect the scalar execution path unless the platform profile specifies otherwise.
 
@@ -31,8 +30,6 @@ include::../generated/instructions/bstart_mseq.adoc[]
 include::../generated/instructions/bstart_mpar.adoc[]
 include::../generated/instructions/bstart_vseq.adoc[]
 include::../generated/instructions/bstart_vpar.adoc[]
-include::../generated/instructions/bstart_cube.adoc[]
-include::../generated/instructions/bstart_fixp.adoc[]
 include::../generated/instructions/bstart_acccvt.adoc[]
 include::../generated/instructions/bstart_tepl.adoc[]
 include::../generated/instructions/bstart_tload.adoc[]
@@ -77,7 +74,6 @@ include::../generated/instructions/xb.adoc[]
 
 include::../generated/instructions/b_iot.adoc[]
 include::../generated/instructions/b_ior.adoc[]
-include::../generated/instructions/b_arg.adoc[]
 include::../generated/instructions/b_catr.adoc[]
 include::../generated/instructions/b_datr.adoc[]
 include::../generated/instructions/b_hint.adoc[]
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deleted file mode 100644
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diff --git a/docs/architecture/isa-manual/src/generated/encodings/enc_b_arg_32_47e8ac50ac96.svg b/docs/architecture/isa-manual/src/generated/encodings/enc_b_arg_32_47e8ac50ac96.svg
deleted file mode 100644
index 5eb73b40..00000000
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diff --git a/docs/architecture/isa-manual/src/generated/encodings/enc_b_arg_32_5c8bfa662370.svg b/docs/architecture/isa-manual/src/generated/encodings/enc_b_arg_32_5c8bfa662370.svg
deleted file mode 100644
index e8b6fb9a..00000000
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+++ /dev/null
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diff --git a/docs/architecture/isa-manual/src/generated/encodings/enc_b_arg_32_95152c29a268.svg b/docs/architecture/isa-manual/src/generated/encodings/enc_b_arg_32_95152c29a268.svg
deleted file mode 100644
index 4f2fbe36..00000000
--- a/docs/architecture/isa-manual/src/generated/encodings/enc_b_arg_32_95152c29a268.svg
+++ /dev/null
@@ -1,33 +0,0 @@
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-  <rect x="783.000" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="824.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
-  <rect x="866.250" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="880.1" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">1</text>
-  <text x="6" y="64" font-size="9" fill="#aaaaaa" font-family="Helvetica Neue,Arial,sans-serif">32-bit encoding</text>
-</svg>
\ No newline at end of file
diff --git a/docs/isa/wavedrom/enc_b_iot_32_efa0fe3fe49a.svg b/docs/architecture/isa-manual/src/generated/encodings/enc_b_iot_32_a06b9b6c1965.svg
similarity index 72%
rename from docs/isa/wavedrom/enc_b_iot_32_efa0fe3fe49a.svg
rename to docs/architecture/isa-manual/src/generated/encodings/enc_b_iot_32_a06b9b6c1965.svg
index e25dd25b..5e439151 100644
--- a/docs/isa/wavedrom/enc_b_iot_32_efa0fe3fe49a.svg
+++ b/docs/architecture/isa-manual/src/generated/encodings/enc_b_iot_32_a06b9b6c1965.svg
@@ -15,19 +15,16 @@
   <text x="769.12" y="8" text-anchor="middle" font-size="8" fill="#999999">4</text>
   <text x="880.12" y="8" text-anchor="middle" font-size="8" fill="#999999">0</text>
   <rect x="6" y="24" width="888.00" height="28" fill="none" stroke="#999999" stroke-width="0.8"/>
-  <rect x="6.000" y="25" width="27.750" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="33.750" y="25" width="27.750" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="61.500" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="75.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">L</text>
-  <rect x="89.250" y="25" width="111.000" height="26" fill="#C62828" stroke="white" stroke-width="0.5"/>
-  <text x="144.8" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">imm4</text>
-  <rect x="200.250" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="241.9" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">DstTile</text>
-  <rect x="283.500" y="25" width="166.500" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="450.000" y="25" width="27.750" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
+  <rect x="6.000" y="25" width="333.000" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
+  <rect x="339.000" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="352.9" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">L</text>
+  <rect x="366.750" y="25" width="111.000" height="26" fill="#C62828" stroke="white" stroke-width="0.5"/>
+  <text x="422.2" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">imm4</text>
   <rect x="477.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
   <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">110</text>
-  <rect x="561.000" y="25" width="138.750" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
+  <rect x="561.000" y="25" width="55.500" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
+  <rect x="616.500" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="658.1" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">DstTile</text>
   <rect x="699.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
   <text x="741.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
   <rect x="783.000" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
diff --git a/docs/architecture/isa-manual/src/generated/encodings/enc_b_iot_32_c11eb189dd83.svg b/docs/architecture/isa-manual/src/generated/encodings/enc_b_iot_32_f1ca66bbcce1.svg
similarity index 68%
rename from docs/architecture/isa-manual/src/generated/encodings/enc_b_iot_32_c11eb189dd83.svg
rename to docs/architecture/isa-manual/src/generated/encodings/enc_b_iot_32_f1ca66bbcce1.svg
index dd43d79b..2e9e2967 100644
--- a/docs/architecture/isa-manual/src/generated/encodings/enc_b_iot_32_c11eb189dd83.svg
+++ b/docs/architecture/isa-manual/src/generated/encodings/enc_b_iot_32_f1ca66bbcce1.svg
@@ -15,21 +15,20 @@
   <text x="769.12" y="8" text-anchor="middle" font-size="8" fill="#999999">4</text>
   <text x="880.12" y="8" text-anchor="middle" font-size="8" fill="#999999">0</text>
   <rect x="6" y="24" width="888.00" height="28" fill="none" stroke="#999999" stroke-width="0.8"/>
-  <rect x="6.000" y="25" width="27.750" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="33.750" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="47.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">S0R</text>
-  <rect x="61.500" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="75.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">L</text>
-  <rect x="89.250" y="25" width="111.000" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="200.250" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="241.9" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">111</text>
-  <rect x="283.500" y="25" width="166.500" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="450.000" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="463.9" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Src…</text>
+  <rect x="6.000" y="25" width="166.500" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="89.2" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">SrcTile1</text>
+  <rect x="172.500" y="25" width="166.500" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="255.8" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">SrcTile0</text>
+  <rect x="339.000" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="352.9" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">L</text>
+  <rect x="366.750" y="25" width="111.000" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
   <rect x="477.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">101</text>
-  <rect x="561.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="630.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">SrcTile0</text>
+  <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">100</text>
+  <rect x="561.000" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="574.9" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">S1R</text>
+  <rect x="588.750" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="602.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">S0R</text>
+  <rect x="616.500" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
   <rect x="699.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
   <text x="741.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
   <rect x="783.000" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
diff --git a/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_cube.svg b/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_cube.svg
deleted file mode 100644
index 839d499a..00000000
--- a/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_cube.svg
+++ /dev/null
@@ -1,34 +0,0 @@
-<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 900 68" width="900" height="68">
-  <defs>
-    <style>
-      text { font-family: 'Courier New', monospace; }
-    </style>
-  </defs>
-  <text x="6" y="15" font-family="Helvetica Neue,Arial,sans-serif" font-weight="bold" font-size="14" fill="#1a1a1a">BSTART.CUBE</text>
-  <text x="19.88" y="8" text-anchor="middle" font-size="8" fill="#999999">31</text>
-  <text x="103.12" y="8" text-anchor="middle" font-size="8" fill="#999999">28</text>
-  <text x="214.12" y="8" text-anchor="middle" font-size="8" fill="#999999">24</text>
-  <text x="325.12" y="8" text-anchor="middle" font-size="8" fill="#999999">20</text>
-  <text x="436.12" y="8" text-anchor="middle" font-size="8" fill="#999999">16</text>
-  <text x="547.12" y="8" text-anchor="middle" font-size="8" fill="#999999">12</text>
-  <text x="658.12" y="8" text-anchor="middle" font-size="8" fill="#999999">8</text>
-  <text x="769.12" y="8" text-anchor="middle" font-size="8" fill="#999999">4</text>
-  <text x="880.12" y="8" text-anchor="middle" font-size="8" fill="#999999">0</text>
-  <rect x="6" y="24" width="888.00" height="28" fill="none" stroke="#999999" stroke-width="0.8"/>
-  <rect x="6.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="75.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">DataType</text>
-  <rect x="144.750" y="25" width="55.500" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="200.250" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="269.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Function</text>
-  <rect x="339.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="408.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x06</text>
-  <rect x="477.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
-  <rect x="561.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="630.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x03</text>
-  <rect x="699.750" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="783.000" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="866.250" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="880.1" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">1</text>
-  <text x="6" y="64" font-size="9" fill="#aaaaaa" font-family="Helvetica Neue,Arial,sans-serif">32-bit encoding</text>
-</svg>
\ No newline at end of file
diff --git a/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_fixp.svg b/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_fixp.svg
deleted file mode 100644
index 865a48e9..00000000
--- a/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_fixp.svg
+++ /dev/null
@@ -1,34 +0,0 @@
-<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 900 68" width="900" height="68">
-  <defs>
-    <style>
-      text { font-family: 'Courier New', monospace; }
-    </style>
-  </defs>
-  <text x="6" y="15" font-family="Helvetica Neue,Arial,sans-serif" font-weight="bold" font-size="14" fill="#1a1a1a">BSTART.FIXP</text>
-  <text x="19.88" y="8" text-anchor="middle" font-size="8" fill="#999999">31</text>
-  <text x="103.12" y="8" text-anchor="middle" font-size="8" fill="#999999">28</text>
-  <text x="214.12" y="8" text-anchor="middle" font-size="8" fill="#999999">24</text>
-  <text x="325.12" y="8" text-anchor="middle" font-size="8" fill="#999999">20</text>
-  <text x="436.12" y="8" text-anchor="middle" font-size="8" fill="#999999">16</text>
-  <text x="547.12" y="8" text-anchor="middle" font-size="8" fill="#999999">12</text>
-  <text x="658.12" y="8" text-anchor="middle" font-size="8" fill="#999999">8</text>
-  <text x="769.12" y="8" text-anchor="middle" font-size="8" fill="#999999">4</text>
-  <text x="880.12" y="8" text-anchor="middle" font-size="8" fill="#999999">0</text>
-  <rect x="6" y="24" width="888.00" height="28" fill="none" stroke="#999999" stroke-width="0.8"/>
-  <rect x="6.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="75.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">DataType</text>
-  <rect x="144.750" y="25" width="55.500" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="200.250" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="269.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Function</text>
-  <rect x="339.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="408.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x07</text>
-  <rect x="477.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
-  <rect x="561.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="630.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x03</text>
-  <rect x="699.750" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="783.000" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="866.250" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="880.1" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">1</text>
-  <text x="6" y="64" font-size="9" fill="#aaaaaa" font-family="Helvetica Neue,Arial,sans-serif">32-bit encoding</text>
-</svg>
\ No newline at end of file
diff --git a/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_tepl.svg b/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_tepl.svg
index c04f1ab1..7b89db94 100644
--- a/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_tepl.svg
+++ b/docs/architecture/isa-manual/src/generated/encodings/enc_bstart_tepl.svg
@@ -18,9 +18,11 @@
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   <text x="75.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">DataType</text>
   <rect x="144.750" y="25" width="55.500" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="172.5" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">01</text>
-  <rect x="200.250" y="25" width="277.500" height="26" fill="#6A1B9A" stroke="white" stroke-width="0.5"/>
-  <text x="339.0" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">TileOpco</text>
+  <text x="172.5" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Mode</text>
+  <rect x="200.250" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="269.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Function</text>
+  <rect x="339.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="408.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x03</text>
   <rect x="477.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
   <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
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diff --git a/docs/architecture/isa-manual/src/generated/instruction_details.adoc b/docs/architecture/isa-manual/src/generated/instruction_details.adoc
index 04ec13a5..931f7876 100644
--- a/docs/architecture/isa-manual/src/generated/instruction_details.adoc
+++ b/docs/architecture/isa-manual/src/generated/instruction_details.adoc
@@ -3,7 +3,7 @@
 [[insnref-details]]
 === Instruction descriptions (by mnemonic)
 
-This section provides per-mnemonic descriptions. The tables above remain the authoritative listing of encodable forms and decode layouts in the v0.57.0 catalog. Descriptions and pseudocode here are derived from mnemonic naming conventions plus catalog assembly templates/notes and are intended to be *informative*.
+This section provides per-mnemonic descriptions. The tables above remain the authoritative listing of encodable forms and decode layouts in the v0.57.1 catalog. Descriptions and pseudocode here are derived from mnemonic naming conventions plus catalog assembly templates/notes and are intended to be *informative*.
 
 [[insndesc-execution-control]]
 ==== Execution Control
@@ -1480,83 +1480,42 @@ off = (ZeroExtend(imm20) << 1)
 ra = base + off
 ----
 
-[[insndesc-block-argument]]
-==== Block Argument
+[[insndesc-block-control-attribute]]
+==== Block Control Attribute
 
-[[insndesc-block-argument-b-arg]]
-===== B.ARG
+[[insndesc-block-control-attribute-b-catr]]
+===== B.CATR
 
 Block metadata instruction (sub-operation selected by the mnemonic suffix).
 
-Catalog forms:: 6 form(s) (32 bits).
+Catalog forms:: 1 form(s) (32 bits).
 
 Assembly forms::
 +
-* `B.ARG NORM.normal`
-* `B.ARG format`
-* `B.ARG NZ2DN.canon`
-* `B.ARG ND2ZN.normal, FP16, Null`
-* `B.ARG DN2ZN.normal, FP16, Null`
-* `B.ARG DN2NZ.normal, FP32, Null`
+* `B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}`
 
 Encoding::
 +
-.`b_arg_32_374ec956affe` — `B.ARG NORM.normal`
-image::encodings/enc_b_arg_32_374ec956affe.svg[B.ARG encoding form b_arg_32_374ec956affe,align="center"]
-.`b_arg_32_47e8ac50ac96` — `B.ARG format`
-image::encodings/enc_b_arg_32_47e8ac50ac96.svg[B.ARG encoding form b_arg_32_47e8ac50ac96,align="center"]
-.`b_arg_32_5c8bfa662370` — `B.ARG NZ2DN.canon`
-image::encodings/enc_b_arg_32_5c8bfa662370.svg[B.ARG encoding form b_arg_32_5c8bfa662370,align="center"]
-.`b_arg_32_95152c29a268` — `B.ARG ND2ZN.normal, FP16, Null`
-image::encodings/enc_b_arg_32_95152c29a268.svg[B.ARG encoding form b_arg_32_95152c29a268,align="center"]
-.`b_arg_32_c6d5c49a4ad7` — `B.ARG DN2ZN.normal, FP16, Null`
-image::encodings/enc_b_arg_32_c6d5c49a4ad7.svg[B.ARG encoding form b_arg_32_c6d5c49a4ad7,align="center"]
-.`b_arg_32_f19d18f2126b` — `B.ARG DN2NZ.normal, FP32, Null`
-image::encodings/enc_b_arg_32_f19d18f2126b.svg[B.ARG encoding form b_arg_32_f19d18f2126b,align="center"]
-
-
-Operation (informative)::
-+
-[source]
-----
-UpdateBlockMetadata(/* fields as encoded */)
-----
-
-[[insndesc-block-argument-b-dim]]
-===== B.DIM
+.`b_catr_32_8f94bdb16d29` — `B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}`
+image::encodings/enc_b_catr.svg[B.CATR encoding form b_catr_32_8f94bdb16d29,align="center"]
 
-Sets a block loop bound/dimension register for structured execution.
-
-Catalog forms:: 3 form(s) (32 bits).
 
-Assembly forms::
-+
-* `B.DIM RegSrc, uimm, ->LB2`
-* `B.DIM RegSrc, uimm, ->LB0`
-* `B.DIM RegSrc, uimm, ->LB1`
-
-Encoding::
+Encoding notes (informative)::
 +
-.`b_dim_32_1caa1aa2944a` — `B.DIM RegSrc, uimm, ->LB2`
-image::encodings/enc_b_dim_32_1caa1aa2944a.svg[B.DIM encoding form b_dim_32_1caa1aa2944a,align="center"]
-.`b_dim_32_27602ab68929` — `B.DIM RegSrc, uimm, ->LB0`
-image::encodings/enc_b_dim_32_27602ab68929.svg[B.DIM encoding form b_dim_32_27602ab68929,align="center"]
-.`b_dim_32_4191099a5f4d` — `B.DIM RegSrc, uimm, ->LB1`
-image::encodings/enc_b_dim_32_4191099a5f4d.svg[B.DIM encoding form b_dim_32_4191099a5f4d,align="center"]
-
+* PTO ISA 0.57.1 control attributes. Only DR[26], trap[19], far[18], atom[17], aq[16], and rl[15] are variable.
 
 Operation (informative)::
 +
 [source]
 ----
-LBx = Read(RegSrc) + uimm  // x selected by encoding (LB0/LB1/LB2)
+UpdateBlockMetadata(/* fields as encoded */)
 ----
 
-[[insndesc-block-control-attribute]]
-==== Block Control Attribute
+[[insndesc-block-data-attribute]]
+==== Block Data Attribute
 
-[[insndesc-block-control-attribute-b-catr]]
-===== B.CATR
+[[insndesc-block-data-attribute-b-datr]]
+===== B.DATR
 
 Block metadata instruction (sub-operation selected by the mnemonic suffix).
 
@@ -1564,17 +1523,17 @@ Catalog forms:: 1 form(s) (32 bits).
 
 Assembly forms::
 +
-* `B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}`
+* `B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}`
 
 Encoding::
 +
-.`b_catr_32_e90bd52fa480` — `B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}`
-image::encodings/enc_b_catr.svg[B.CATR encoding form b_catr_32_e90bd52fa480,align="center"]
+.`b_datr_32_840f4b8d579d` — `B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}`
+image::encodings/enc_b_datr.svg[B.DATR encoding form b_datr_32_840f4b8d579d,align="center"]
 
 
 Encoding notes (informative)::
 +
-* canonical split of legacy B.CATR/B.DATR control fields. Bits 25:15 are reserved zero.
+* PTO ISA 0.57.1 data attributes. PadValueOrByteId is an opcode-defined two-bit union; bits 19:18 are reserved zero.
 
 Operation (informative)::
 +
@@ -1583,35 +1542,37 @@ Operation (informative)::
 UpdateBlockMetadata(/* fields as encoded */)
 ----
 
-[[insndesc-block-data-attribute]]
-==== Block Data Attribute
+[[insndesc-block-argument]]
+==== Block Argument
 
-[[insndesc-block-data-attribute-b-datr]]
-===== B.DATR
+[[insndesc-block-argument-b-dim]]
+===== B.DIM
 
-Block metadata instruction (sub-operation selected by the mnemonic suffix).
+Sets a block loop bound/dimension register for structured execution.
 
-Catalog forms:: 1 form(s) (32 bits).
+Catalog forms:: 3 form(s) (32 bits).
 
 Assembly forms::
 +
-* `B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat}`
+* `B.DIM RegSrc, uimm, ->LB2`
+* `B.DIM RegSrc, uimm, ->LB0`
+* `B.DIM RegSrc, uimm, ->LB1`
 
 Encoding::
 +
-.`b_datr_32_c161a042ff38` — `B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat}`
-image::encodings/enc_b_datr.svg[B.DATR encoding form b_datr_32_c161a042ff38,align="center"]
-
+.`b_dim_32_1caa1aa2944a` — `B.DIM RegSrc, uimm, ->LB2`
+image::encodings/enc_b_dim_32_1caa1aa2944a.svg[B.DIM encoding form b_dim_32_1caa1aa2944a,align="center"]
+.`b_dim_32_27602ab68929` — `B.DIM RegSrc, uimm, ->LB0`
+image::encodings/enc_b_dim_32_27602ab68929.svg[B.DIM encoding form b_dim_32_27602ab68929,align="center"]
+.`b_dim_32_4191099a5f4d` — `B.DIM RegSrc, uimm, ->LB1`
+image::encodings/enc_b_dim_32_4191099a5f4d.svg[B.DIM encoding form b_dim_32_4191099a5f4d,align="center"]
 
-Encoding notes (informative)::
-+
-* canonical split of legacy B.CATR/B.DATR data fields. CMode is 3 bits; RMode is 3 bits; Sat is bit 31.
 
 Operation (informative)::
 +
 [source]
 ----
-UpdateBlockMetadata(/* fields as encoded */)
+LBx = Read(RegSrc) + uimm  // x selected by encoding (LB0/LB1/LB2)
 ----
 
 [[insndesc-branch]]
@@ -1936,32 +1897,32 @@ Catalog forms:: 5 form(s) (32 bits).
 Assembly forms::
 +
 * `B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>`
-* `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>`
 * `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>`
 * `B.IOT SrcTile0<.reuse>, <last>`
 * `B.IOT <last>, ->DstTile<Size>`
+* `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>`
 
 Encoding::
 +
-.`b_iot_32_10db6db84f5d` — `B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>`
-image::encodings/enc_b_iot_32_10db6db84f5d.svg[B.IOT encoding form b_iot_32_10db6db84f5d,align="center"]
-.`b_iot_32_2c07e7177fad` — `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>`
-image::encodings/enc_b_iot_32_2c07e7177fad.svg[B.IOT encoding form b_iot_32_2c07e7177fad,align="center"]
-.`b_iot_32_8b8bce6bffe8` — `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>`
-image::encodings/enc_b_iot_32_8b8bce6bffe8.svg[B.IOT encoding form b_iot_32_8b8bce6bffe8,align="center"]
-.`b_iot_32_c11eb189dd83` — `B.IOT SrcTile0<.reuse>, <last>`
-image::encodings/enc_b_iot_32_c11eb189dd83.svg[B.IOT encoding form b_iot_32_c11eb189dd83,align="center"]
-.`b_iot_32_efa0fe3fe49a` — `B.IOT <last>, ->DstTile<Size>`
-image::encodings/enc_b_iot_32_efa0fe3fe49a.svg[B.IOT encoding form b_iot_32_efa0fe3fe49a,align="center"]
+.`b_iot_32_0f23e46d6176` — `B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>`
+image::encodings/enc_b_iot_32_0f23e46d6176.svg[B.IOT encoding form b_iot_32_0f23e46d6176,align="center"]
+.`b_iot_32_3a6945dec034` — `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>`
+image::encodings/enc_b_iot_32_3a6945dec034.svg[B.IOT encoding form b_iot_32_3a6945dec034,align="center"]
+.`b_iot_32_778f84340400` — `B.IOT SrcTile0<.reuse>, <last>`
+image::encodings/enc_b_iot_32_778f84340400.svg[B.IOT encoding form b_iot_32_778f84340400,align="center"]
+.`b_iot_32_a06b9b6c1965` — `B.IOT <last>, ->DstTile<Size>`
+image::encodings/enc_b_iot_32_a06b9b6c1965.svg[B.IOT encoding form b_iot_32_a06b9b6c1965,align="center"]
+.`b_iot_32_f1ca66bbcce1` — `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>`
+image::encodings/enc_b_iot_32_f1ca66bbcce1.svg[B.IOT encoding form b_iot_32_f1ca66bbcce1,align="center"]
 
 
 Encoding notes (informative)::
 +
-* canonical one-input immediate-size tile descriptor; function=101 means only SrcTile0 is valid. v0.57 excludes DstTile=111 from this destination-producing form.
-* v0.57 two-input source-only tile descriptor required by multi-descriptor PTO expansions. DstTile=111 denotes no output and the unused size field is canonically zero.
-* canonical two-input immediate-size tile descriptor. SrcTile0/1 are independent 6-bit fields; imm4 encodes 0B..512KB. v0.57 excludes DstTile=111 from this destination-producing form.
-* v0.57 one-input source-only tile descriptor required by multi-descriptor PTO expansions. DstTile=111 denotes no output and the unused size field is canonically zero.
-* canonical no-input immediate-size tile descriptor; function=110 means only the destination allocation is valid.
+* PTO ISA 0.57.1 one-source descriptor. Inactive source and reuse fields encode zero.
+* PTO ISA 0.57.1 two-source descriptor. imm4 3..9 selects 128B..8KiB; ACC is never encoded as DstTile.
+* PTO ISA 0.57.1 one-source destination-free descriptor. All inapplicable fields encode zero.
+* PTO ISA 0.57.1 zero-source destination descriptor. Inactive source and reuse fields encode zero.
+* PTO ISA 0.57.1 two-source destination-free descriptor. DstTile and imm4 encode zero; zero does not name an output.
 
 Operation (informative)::
 +
@@ -2629,61 +2590,7 @@ image::encodings/enc_bstart_acccvt.svg[BSTART.ACCCVT encoding form bstart_acccvt
 
 Encoding notes (informative)::
 +
-* Alias of BSTART.CUBE Function=8. ACCCVT requires quantization args via B.ARG+B.IOR (scale/zero-point required in strict profile).
-
-Operation (informative)::
-+
-[source]
-----
-EndBlock()
-BeginNextBlock(/* type/kind/target as encoded */)
-----
-
-[[insndesc-block-split-bstart-cube]]
-===== BSTART.CUBE
-
-Terminates the current block and begins the next block, encoding both block type and transition kind.
-
-Catalog forms:: 1 form(s) (32 bits).
-
-Assembly forms::
-+
-* `BSTART.CUBE Function, DataType`
-
-Encoding::
-+
-.`bstart_cube_32_bd3f337acb9d` — `BSTART.CUBE Function, DataType`
-image::encodings/enc_bstart_cube.svg[BSTART.CUBE encoding form bstart_cube_32_bd3f337acb9d,align="center"]
-
-
-Encoding notes (informative)::
-+
-* Generic CUBE selector form for unnamed functions. Functions 0/1/2/4/5/6/8/16/17/18/20/21/22 decode through their canonical named forms.
-
-Operation (informative)::
-+
-[source]
-----
-EndBlock()
-BeginNextBlock(/* type/kind/target as encoded */)
-----
-
-[[insndesc-block-split-bstart-fixp]]
-===== BSTART.FIXP
-
-Terminates the current block and begins the next block, encoding both block type and transition kind.
-
-Catalog forms:: 1 form(s) (32 bits).
-
-Assembly forms::
-+
-* `BSTART.FIXP TileOp, DataType`
-
-Encoding::
-+
-.`bstart_fixp_32_3b0ae11126a6` — `BSTART.FIXP TileOp, DataType`
-image::encodings/enc_bstart_fixp.svg[BSTART.FIXP encoding form bstart_fixp_32_3b0ae11126a6,align="center"]
-
+* Named CUBE-family Function=8. ACCCVT reads implicit ACC and uses B.DATR conversion controls before publishing an ordinary Tile.
 
 Operation (informative)::
 +
@@ -2759,7 +2666,7 @@ image::encodings/enc_bstart_mgather.svg[BSTART.MGATHER encoding form bstart_mgat
 
 Encoding notes (informative)::
 +
-* Named TMA-family Function=4. Memory gather uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57.
+* TMA Function=4. Memory gather uses B.DATR/B.IOR/B.IOT descriptor state.
 
 Operation (informative)::
 +
@@ -2871,7 +2778,7 @@ image::encodings/enc_bstart_mscatter.svg[BSTART.MSCATTER encoding form bstart_ms
 
 Encoding notes (informative)::
 +
-* Named TMA-family Function=5. Memory scatter uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57.
+* TMA Function=5. Memory scatter uses B.DATR/B.IOR/B.IOT descriptor state.
 
 Operation (informative)::
 +
@@ -3016,17 +2923,17 @@ Catalog forms:: 1 form(s) (32 bits).
 
 Assembly forms::
 +
-* `BSTART.TEPL TileOpcode, DataType`
+* `BSTART.TEPL Mode, Function, DataType`
 
 Encoding::
 +
-.`bstart_tepl_32_d022db6dacb3` — `BSTART.TEPL TileOpcode, DataType`
-image::encodings/enc_bstart_tepl.svg[BSTART.TEPL encoding form bstart_tepl_32_d022db6dacb3,align="center"]
+.`bstart_tepl_32_bff5143d4fe3` — `BSTART.TEPL Mode, Function, DataType`
+image::encodings/enc_bstart_tepl.svg[BSTART.TEPL encoding form bstart_tepl_32_bff5143d4fe3,align="center"]
 
 
 Encoding notes (informative)::
 +
-* Tile opcode selects PTO template ops. Canonical established assignments require TileOpcode[9:6]=0 and pack TileOpcode[5]=Mode with TileOpcode[4:0]=Function; unassigned values remain reserved for future template extension.
+* PTO ISA 0.57.1 TEPL selector: logical_selector=(Mode<<5)\|Function. There is no legacy 10-bit TileOpcode decode.
 
 Operation (informative)::
 +
@@ -3229,7 +3136,7 @@ image::encodings/enc_bstart_tload.svg[BSTART.TLOAD encoding form bstart_tload_32
 
 Encoding notes (informative)::
 +
-* Alias of BSTART.TMA Function=0. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding.
+* TMA Function=0. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding.
 
 Operation (informative)::
 +
@@ -3258,7 +3165,7 @@ image::encodings/enc_bstart_tmatmul.svg[BSTART.TMATMUL encoding form bstart_tmat
 
 Encoding notes (informative)::
 +
-* Alias of BSTART.CUBE Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
+* Named CUBE-family Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
 
 Operation (informative)::
 +
@@ -3287,7 +3194,7 @@ image::encodings/enc_bstart_tmatmul_acc.svg[BSTART.TMATMUL.ACC encoding form bst
 
 Encoding notes (informative)::
 +
-* Alias of BSTART.CUBE Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
+* Named CUBE-family Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
 
 Operation (informative)::
 +
@@ -3490,7 +3397,7 @@ image::encodings/enc_bstart_tstore.svg[BSTART.TSTORE encoding form bstart_tstore
 
 Encoding notes (informative)::
 +
-* Alias of BSTART.TMA Function=1. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding.
+* TMA Function=1. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding.
 
 Operation (informative)::
 +
diff --git a/docs/architecture/isa-manual/src/generated/instruction_group_summary.adoc b/docs/architecture/isa-manual/src/generated/instruction_group_summary.adoc
index fa6e0b67..ad155303 100644
--- a/docs/architecture/isa-manual/src/generated/instruction_group_summary.adoc
+++ b/docs/architecture/isa-manual/src/generated/instruction_group_summary.adoc
@@ -10,16 +10,16 @@
 |Arithmetic Operation 64bit |21 |21
 |Arithmetic Operation 32bit |21 |21
 |PC-Relative |4 |4
-|Block Argument |9 |2
 |Block Control Attribute |1 |1
 |Block Data Attribute |1 |1
+|Block Argument |3 |1
 |Branch |10 |10
 |Block Hint |2 |1
 |Block Input & Output |6 |2
 |Block Offset |1 |1
 |Cache Maintain |16 |16
 |Bit Operation |8 |8
-|Block Split |59 |45
+|Block Split |57 |43
 |BSTART |20 |8
 |Arithmetic Operation |20 |20
 |Arithmetic |1 |1
diff --git a/docs/architecture/isa-manual/src/generated/instruction_reference.adoc b/docs/architecture/isa-manual/src/generated/instruction_reference.adoc
index e0e3eb67..2633e858 100644
--- a/docs/architecture/isa-manual/src/generated/instruction_reference.adoc
+++ b/docs/architecture/isa-manual/src/generated/instruction_reference.adoc
@@ -88,39 +88,33 @@
 |`SETRET` |32 |- |`setret uimm, ->Ra` |-
 |===
 
-[[insnref-block-argument]]
-=== Block Argument
+[[insnref-block-control-attribute]]
+=== Block Control Attribute
 
 [cols="1,1,2,4,6",options="header"]
 |===
 |Mnemonic |Len |Decode |Assembly |Notes
-|`B.ARG` |32 |- |`B.ARG NORM.normal` |-
-|`B.ARG` |32 |- |`B.ARG format` |-
-|`B.ARG` |32 |- |`B.ARG NZ2DN.canon` |-
-|`B.ARG` |32 |- |`B.ARG ND2ZN.normal, FP16, Null` |-
-|`B.ARG` |32 |- |`B.ARG DN2ZN.normal, FP16, Null` |-
-|`B.ARG` |32 |- |`B.ARG DN2NZ.normal, FP32, Null` |-
-|`B.DIM` |32 |- |`B.DIM RegSrc, uimm, ->LB2` |-
-|`B.DIM` |32 |- |`B.DIM RegSrc, uimm, ->LB0` |-
-|`B.DIM` |32 |- |`B.DIM RegSrc, uimm, ->LB1` |-
+|`B.CATR` |32 |- |`B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}` |PTO ISA 0.57.1 control attributes. Only DR[26], trap[19], far[18], atom[17], aq[16], and rl[15] are variable.
 |===
 
-[[insnref-block-control-attribute]]
-=== Block Control Attribute
+[[insnref-block-data-attribute]]
+=== Block Data Attribute
 
 [cols="1,1,2,4,6",options="header"]
 |===
 |Mnemonic |Len |Decode |Assembly |Notes
-|`B.CATR` |32 |- |`B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}` |canonical split of legacy B.CATR/B.DATR control fields. Bits 25:15 are reserved zero.
+|`B.DATR` |32 |- |`B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}` |PTO ISA 0.57.1 data attributes. PadValueOrByteId is an opcode-defined two-bit union; bits 19:18 are reserved zero.
 |===
 
-[[insnref-block-data-attribute]]
-=== Block Data Attribute
+[[insnref-block-argument]]
+=== Block Argument
 
 [cols="1,1,2,4,6",options="header"]
 |===
 |Mnemonic |Len |Decode |Assembly |Notes
-|`B.DATR` |32 |- |`B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat}` |canonical split of legacy B.CATR/B.DATR data fields. CMode is 3 bits; RMode is 3 bits; Sat is bit 31.
+|`B.DIM` |32 |- |`B.DIM RegSrc, uimm, ->LB2` |-
+|`B.DIM` |32 |- |`B.DIM RegSrc, uimm, ->LB0` |-
+|`B.DIM` |32 |- |`B.DIM RegSrc, uimm, ->LB1` |-
 |===
 
 [[insnref-branch]]
@@ -158,11 +152,11 @@
 |===
 |Mnemonic |Len |Decode |Assembly |Notes
 |`B.IOR` |32 |- |`B.IOR [RegSrc0, RegSrc1, RegSrc2],[RegDst]` |-
-|`B.IOT` |32 |- |`B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>` |canonical one-input immediate-size tile descriptor; function=101 means only SrcTile0 is valid. v0.57 excludes DstTile=111 from this destination-producing form.
-|`B.IOT` |32 |- |`B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>` |v0.57 two-input source-only tile descriptor required by multi-descriptor PTO expansions. DstTile=111 denotes no output and the unused size field is canonically zero.
-|`B.IOT` |32 |- |`B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>` |canonical two-input immediate-size tile descriptor. SrcTile0/1 are independent 6-bit fields; imm4 encodes 0B..512KB. v0.57 excludes DstTile=111 from this destination-producing form.
-|`B.IOT` |32 |- |`B.IOT SrcTile0<.reuse>, <last>` |v0.57 one-input source-only tile descriptor required by multi-descriptor PTO expansions. DstTile=111 denotes no output and the unused size field is canonically zero.
-|`B.IOT` |32 |- |`B.IOT <last>, ->DstTile<Size>` |canonical no-input immediate-size tile descriptor; function=110 means only the destination allocation is valid.
+|`B.IOT` |32 |- |`B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>` |PTO ISA 0.57.1 one-source descriptor. Inactive source and reuse fields encode zero.
+|`B.IOT` |32 |- |`B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>` |PTO ISA 0.57.1 two-source descriptor. imm4 3..9 selects 128B..8KiB; ACC is never encoded as DstTile.
+|`B.IOT` |32 |- |`B.IOT SrcTile0<.reuse>, <last>` |PTO ISA 0.57.1 one-source destination-free descriptor. All inapplicable fields encode zero.
+|`B.IOT` |32 |- |`B.IOT <last>, ->DstTile<Size>` |PTO ISA 0.57.1 zero-source destination descriptor. Inactive source and reuse fields encode zero.
+|`B.IOT` |32 |- |`B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>` |PTO ISA 0.57.1 two-source destination-free descriptor. DstTile and imm4 encode zero; zero does not name an output.
 |===
 
 [[insnref-block-offset]]
@@ -222,9 +216,7 @@
 |Mnemonic |Len |Decode |Assembly |Notes
 |`BSTART` |32 |- |`BSTART {DIRECT, CALL}, <label>` |-
 |`BSTART` |32 |- |`BSTART COND, <label>` |-
-|`BSTART.ACCCVT` |32 |- |`BSTART.ACCCVT DataType` |Alias of BSTART.CUBE Function=8. ACCCVT requires quantization args via B.ARG+B.IOR (scale/zero-point required in strict profile).
-|`BSTART.CUBE` |32 |- |`BSTART.CUBE Function, DataType` |Generic CUBE selector form for unnamed functions. Functions 0/1/2/4/5/6/8/16/17/18/20/21/22 decode through their canonical named forms.
-|`BSTART.FIXP` |32 |- |`BSTART.FIXP TileOp, DataType` |-
+|`BSTART.ACCCVT` |32 |- |`BSTART.ACCCVT DataType` |Named CUBE-family Function=8. ACCCVT reads implicit ACC and uses B.DATR conversion controls before publishing an ordinary Tile.
 |`BSTART.FP` |32 |- |`BSTART.FP RET` |Bits 31:15 are reserved zero.
 |`BSTART.FP` |32 |- |`BSTART.FP ICALL` |Bits 31:15 are reserved zero.
 |`BSTART.FP` |32 |- |`BSTART.FP COND, <label>` |-
@@ -232,11 +224,11 @@
 |`BSTART.FP` |32 |- |`BSTART.FP DIRECT, <label>` |-
 |`BSTART.FP` |32 |- |`BSTART.FP CALL, <label>` |-
 |`BSTART.FP` |32 |- |`BSTART.FP FALL<, fixup_label>` |-
-|`BSTART.MGATHER` |32 |- |`BSTART.MGATHER DataType` |Named TMA-family Function=4. Memory gather uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57.
+|`BSTART.MGATHER` |32 |- |`BSTART.MGATHER DataType` |TMA Function=4. Memory gather uses B.DATR/B.IOR/B.IOT descriptor state.
 |`BSTART.MGATHER.CAS` |32 |- |`BSTART.MGATHER.CAS DataType` |Named TMA-family Function=8. Per-element atomic compare-and-swap gather; detailed PTO selector manifest is defined out-of-band for v0.57.
 |`BSTART.MGATHER.MASK` |32 |- |`BSTART.MGATHER.MASK DataType` |Named TMA-family Function=6. Masked memory gather; detailed PTO selector manifest is defined out-of-band for v0.57.
 |`BSTART.MPAR` |32 |- |`BSTART.MPAR <VS8, VS16>` |-
-|`BSTART.MSCATTER` |32 |- |`BSTART.MSCATTER DataType` |Named TMA-family Function=5. Memory scatter uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57.
+|`BSTART.MSCATTER` |32 |- |`BSTART.MSCATTER DataType` |TMA Function=5. Memory scatter uses B.DATR/B.IOR/B.IOT descriptor state.
 |`BSTART.MSCATTER.MASK` |32 |- |`BSTART.MSCATTER.MASK DataType` |Named TMA-family Function=7. Masked memory scatter; detailed PTO selector manifest is defined out-of-band for v0.57.
 |`BSTART.MSEQ` |32 |- |`BSTART.MSEQ <VS8, VS16>` |-
 |`BSTART.STD` |32 |- |`BSTART.STD COND, <label>` |-
@@ -247,23 +239,23 @@
 |`BSTART.STD` |32 |- |`BSTART.STD CALL, <label>` |-
 |`BSTART.STD` |32 |- |`BSTART.STD DIRECT, <label>` |-
 |`BSTART.SYS` |32 |- |`BSTART.SYS FALL<, fixup_label>` |-
-|`BSTART.TEPL` |32 |- |`BSTART.TEPL TileOpcode, DataType` |Tile opcode selects PTO template ops. Canonical established assignments require TileOpcode[9:6]=0 and pack TileOpcode[5]=Mode with TileOpcode[4:0]=Function; unassigned values remain reserved for future template extension.
+|`BSTART.TEPL` |32 |- |`BSTART.TEPL Mode, Function, DataType` |PTO ISA 0.57.1 TEPL selector: logical_selector=(Mode<<5)\|Function. There is no legacy 10-bit TileOpcode decode.
 |`BSTART.TGEMV` |32 |- |`BSTART.TGEMV DataType` |Named CUBE-family Function=16. Matrix-vector multiply; requires B.DIM and CUBE tile bindings.
 |`BSTART.TGEMV.ACC` |32 |- |`BSTART.TGEMV.ACC DataType` |Named CUBE-family Function=18. Matrix-vector multiply-accumulate; requires B.DIM and CUBE tile bindings.
 |`BSTART.TGEMV.BIAS` |32 |- |`BSTART.TGEMV.BIAS DataType` |Named CUBE-family Function=17. Matrix-vector multiply with bias; requires B.DIM and CUBE tile bindings.
 |`BSTART.TGEMVMX` |32 |- |`BSTART.TGEMVMX DataType` |Named CUBE-family Function=20. Micro-scaled matrix-vector multiply; requires B.DIM and CUBE tile bindings.
 |`BSTART.TGEMVMX.ACC` |32 |- |`BSTART.TGEMVMX.ACC DataType` |Named CUBE-family Function=22. Micro-scaled matrix-vector multiply-accumulate; requires B.DIM and CUBE tile bindings.
 |`BSTART.TGEMVMX.BIAS` |32 |- |`BSTART.TGEMVMX.BIAS DataType` |Named CUBE-family Function=21. Micro-scaled matrix-vector multiply with bias; requires B.DIM and CUBE tile bindings.
-|`BSTART.TLOAD` |32 |- |`BSTART.TLOAD DataType` |Alias of BSTART.TMA Function=0. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding.
-|`BSTART.TMATMUL` |32 |- |`BSTART.TMATMUL DataType` |Alias of BSTART.CUBE Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
-|`BSTART.TMATMUL.ACC` |32 |- |`BSTART.TMATMUL.ACC DataType` |Alias of BSTART.CUBE Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
+|`BSTART.TLOAD` |32 |- |`BSTART.TLOAD DataType` |TMA Function=0. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding.
+|`BSTART.TMATMUL` |32 |- |`BSTART.TMATMUL DataType` |Named CUBE-family Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
+|`BSTART.TMATMUL.ACC` |32 |- |`BSTART.TMATMUL.ACC DataType` |Named CUBE-family Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
 |`BSTART.TMATMUL.BIAS` |32 |- |`BSTART.TMATMUL.BIAS DataType` |Named CUBE-family Function=1. Matrix multiply with bias; requires B.DIM and CUBE tile bindings.
 |`BSTART.TMATMULMX` |32 |- |`BSTART.TMATMULMX DataType` |Named CUBE-family Function=4. Micro-scaled matrix multiply; requires B.DIM and CUBE tile bindings.
 |`BSTART.TMATMULMX.ACC` |32 |- |`BSTART.TMATMULMX.ACC DataType` |Named CUBE-family Function=6. Micro-scaled matrix multiply-accumulate; requires B.DIM and CUBE tile bindings.
 |`BSTART.TMATMULMX.BIAS` |32 |- |`BSTART.TMATMULMX.BIAS DataType` |Named CUBE-family Function=5. Micro-scaled matrix multiply with bias; requires B.DIM and CUBE tile bindings.
 |`BSTART.TMOV` |32 |- |`BSTART.TMOV DataType` |Alias of BSTART.TMA Function=2. TMOV is tile-state only (no GM memory access) and destination allocation is queue-push only.
 |`BSTART.TPREFETCH` |32 |- |`BSTART.TPREFETCH DataType` |Named TMA-family Function=3. TPREFETCH has the same address, layout, memory, fault, ordering, and restart contract as TLOAD, with destination binding/allocation/writeback effects removed.
-|`BSTART.TSTORE` |32 |- |`BSTART.TSTORE DataType` |Alias of BSTART.TMA Function=1. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding.
+|`BSTART.TSTORE` |32 |- |`BSTART.TSTORE DataType` |TMA Function=1. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding.
 |`BSTART.VPAR` |32 |- |`BSTART.VPAR <VS8, VS16>` |TVEC-equivalent parallel SIMT header; requires B.TEXT body target in decoupled form.
 |`BSTART.VSEQ` |32 |- |`BSTART.VSEQ <VS8, VS16>` |TVEC-equivalent sequential SIMT header; requires B.TEXT body target in decoupled form.
 |`BSTOP` |32 |- |`BSTOP` |-
diff --git a/docs/architecture/isa-manual/src/generated/instructions/b_arg.adoc b/docs/architecture/isa-manual/src/generated/instructions/b_arg.adoc
deleted file mode 100644
index b03f4fce..00000000
--- a/docs/architecture/isa-manual/src/generated/instructions/b_arg.adoc
+++ /dev/null
@@ -1,78 +0,0 @@
----
-// Auto-generated instruction documentation
-// Do not edit by hand
-
-[[inst_b_arg]]
-==== B.ARG
-
-*Description:* Block block argument: B.ARG.
-
-[[inst_b_arg_32_374ec956affe]]
-===== Form `b_arg_32_374ec956affe`
-
-*Syntax:* B.ARG NORM.normal
-
-*Encoding:*
-
-image::encodings/enc_b_arg_32_374ec956affe.svg[B.ARG encoding form b_arg_32_374ec956affe,width=800]
-
-*Compression:* L32 (len=32)
-
-[[inst_b_arg_32_47e8ac50ac96]]
-===== Form `b_arg_32_47e8ac50ac96`
-
-*Syntax:* B.ARG format
-
-*Encoding:*
-
-image::encodings/enc_b_arg_32_47e8ac50ac96.svg[B.ARG encoding form b_arg_32_47e8ac50ac96,width=800]
-
-*Compression:* L32 (len=32)
-
-[[inst_b_arg_32_5c8bfa662370]]
-===== Form `b_arg_32_5c8bfa662370`
-
-*Syntax:* B.ARG NZ2DN.canon
-
-*Encoding:*
-
-image::encodings/enc_b_arg_32_5c8bfa662370.svg[B.ARG encoding form b_arg_32_5c8bfa662370,width=800]
-
-*Compression:* L32 (len=32)
-
-[[inst_b_arg_32_95152c29a268]]
-===== Form `b_arg_32_95152c29a268`
-
-*Syntax:* B.ARG ND2ZN.normal, FP16, Null
-
-*Encoding:*
-
-image::encodings/enc_b_arg_32_95152c29a268.svg[B.ARG encoding form b_arg_32_95152c29a268,width=800]
-
-*Compression:* L32 (len=32)
-
-[[inst_b_arg_32_c6d5c49a4ad7]]
-===== Form `b_arg_32_c6d5c49a4ad7`
-
-*Syntax:* B.ARG DN2ZN.normal, FP16, Null
-
-*Encoding:*
-
-image::encodings/enc_b_arg_32_c6d5c49a4ad7.svg[B.ARG encoding form b_arg_32_c6d5c49a4ad7,width=800]
-
-*Compression:* L32 (len=32)
-
-[[inst_b_arg_32_f19d18f2126b]]
-===== Form `b_arg_32_f19d18f2126b`
-
-*Syntax:* B.ARG DN2NZ.normal, FP32, Null
-
-*Encoding:*
-
-image::encodings/enc_b_arg_32_f19d18f2126b.svg[B.ARG encoding form b_arg_32_f19d18f2126b,width=800]
-
-*Compression:* L32 (len=32)
-
-*Uop-Class:* CMD
-
-*Uop-Class payload:* `{"cmd_kind": "BLOCK_ARGUMENT", "note": "User confirmed A", "source": "group_rule", "uop_kind": "CMD"}`
diff --git a/docs/architecture/isa-manual/src/generated/instructions/b_catr.adoc b/docs/architecture/isa-manual/src/generated/instructions/b_catr.adoc
index 289efe98..caf30837 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/b_catr.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/b_catr.adoc
@@ -7,7 +7,7 @@
 
 *Syntax:* B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}
 
-*Description:* canonical split of legacy B.CATR/B.DATR control fields. Bits 25:15 are reserved zero.
+*Description:* PTO ISA 0.57.1 control attributes. Only DR[26], trap[19], far[18], atom[17], aq[16], and rl[15] are variable.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/b_datr.adoc b/docs/architecture/isa-manual/src/generated/instructions/b_datr.adoc
index fbb05f0d..7ee54629 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/b_datr.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/b_datr.adoc
@@ -5,9 +5,9 @@
 [[inst_b_datr]]
 ==== B.DATR
 
-*Syntax:* B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat}
+*Syntax:* B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}
 
-*Description:* canonical split of legacy B.CATR/B.DATR data fields. CMode is 3 bits; RMode is 3 bits; Sat is bit 31.
+*Description:* PTO ISA 0.57.1 data attributes. PadValueOrByteId is an opcode-defined two-bit union; bits 19:18 are reserved zero.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/b_iot.adoc b/docs/architecture/isa-manual/src/generated/instructions/b_iot.adoc
index 37857a60..5920df72 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/b_iot.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/b_iot.adoc
@@ -5,60 +5,60 @@
 [[inst_b_iot]]
 ==== B.IOT
 
-*Description:* canonical one-input immediate-size tile descriptor; function=101 means only SrcTile0 is valid. v0.57 excludes DstTile=111 from this destination-producing form.
+*Description:* PTO ISA 0.57.1 one-source descriptor. Inactive source and reuse fields encode zero.
 
-[[inst_b_iot_32_10db6db84f5d]]
-===== Form `b_iot_32_10db6db84f5d`
+[[inst_b_iot_32_0f23e46d6176]]
+===== Form `b_iot_32_0f23e46d6176`
 
 *Syntax:* B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>
 
 *Encoding:*
 
-image::encodings/enc_b_iot_32_10db6db84f5d.svg[B.IOT encoding form b_iot_32_10db6db84f5d,width=800]
+image::encodings/enc_b_iot_32_0f23e46d6176.svg[B.IOT encoding form b_iot_32_0f23e46d6176,width=800]
 
 *Compression:* L32 (len=32)
 
-[[inst_b_iot_32_2c07e7177fad]]
-===== Form `b_iot_32_2c07e7177fad`
+[[inst_b_iot_32_3a6945dec034]]
+===== Form `b_iot_32_3a6945dec034`
 
-*Syntax:* B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>
+*Syntax:* B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>
 
 *Encoding:*
 
-image::encodings/enc_b_iot_32_2c07e7177fad.svg[B.IOT encoding form b_iot_32_2c07e7177fad,width=800]
+image::encodings/enc_b_iot_32_3a6945dec034.svg[B.IOT encoding form b_iot_32_3a6945dec034,width=800]
 
 *Compression:* L32 (len=32)
 
-[[inst_b_iot_32_8b8bce6bffe8]]
-===== Form `b_iot_32_8b8bce6bffe8`
+[[inst_b_iot_32_778f84340400]]
+===== Form `b_iot_32_778f84340400`
 
-*Syntax:* B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>
+*Syntax:* B.IOT SrcTile0<.reuse>, <last>
 
 *Encoding:*
 
-image::encodings/enc_b_iot_32_8b8bce6bffe8.svg[B.IOT encoding form b_iot_32_8b8bce6bffe8,width=800]
+image::encodings/enc_b_iot_32_778f84340400.svg[B.IOT encoding form b_iot_32_778f84340400,width=800]
 
 *Compression:* L32 (len=32)
 
-[[inst_b_iot_32_c11eb189dd83]]
-===== Form `b_iot_32_c11eb189dd83`
+[[inst_b_iot_32_a06b9b6c1965]]
+===== Form `b_iot_32_a06b9b6c1965`
 
-*Syntax:* B.IOT SrcTile0<.reuse>, <last>
+*Syntax:* B.IOT <last>, ->DstTile<Size>
 
 *Encoding:*
 
-image::encodings/enc_b_iot_32_c11eb189dd83.svg[B.IOT encoding form b_iot_32_c11eb189dd83,width=800]
+image::encodings/enc_b_iot_32_a06b9b6c1965.svg[B.IOT encoding form b_iot_32_a06b9b6c1965,width=800]
 
 *Compression:* L32 (len=32)
 
-[[inst_b_iot_32_efa0fe3fe49a]]
-===== Form `b_iot_32_efa0fe3fe49a`
+[[inst_b_iot_32_f1ca66bbcce1]]
+===== Form `b_iot_32_f1ca66bbcce1`
 
-*Syntax:* B.IOT <last>, ->DstTile<Size>
+*Syntax:* B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>
 
 *Encoding:*
 
-image::encodings/enc_b_iot_32_efa0fe3fe49a.svg[B.IOT encoding form b_iot_32_efa0fe3fe49a,width=800]
+image::encodings/enc_b_iot_32_f1ca66bbcce1.svg[B.IOT encoding form b_iot_32_f1ca66bbcce1,width=800]
 
 *Compression:* L32 (len=32)
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_acccvt.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_acccvt.adoc
index 4ad01c15..2a5da7cd 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_acccvt.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/bstart_acccvt.adoc
@@ -7,7 +7,7 @@
 
 *Syntax:* BSTART.ACCCVT DataType
 
-*Description:* Alias of BSTART.CUBE Function=8. ACCCVT requires quantization args via B.ARG+B.IOR (scale/zero-point required in strict profile).
+*Description:* Named CUBE-family Function=8. ACCCVT reads implicit ACC and uses B.DATR conversion controls before publishing an ordinary Tile.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_cube.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_cube.adoc
deleted file mode 100644
index 90d10d6c..00000000
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_cube.adoc
+++ /dev/null
@@ -1,20 +0,0 @@
----
-// Auto-generated instruction documentation
-// Do not edit by hand
-
-[[inst_bstart_cube]]
-==== BSTART.CUBE
-
-*Syntax:* BSTART.CUBE Function, DataType
-
-*Description:* Generic CUBE selector form for unnamed functions. Functions 0/1/2/4/5/6/8/16/17/18/20/21/22 decode through their canonical named forms.
-
-*Encoding:*
-
-image::encodings/enc_bstart_cube.svg[BSTART.CUBE encoding,width=800]
-
-*Uop-Class:* CMD
-
-*Compression:* L32 (len=32)
-
-*Uop-Class payload:* `{"cmd_kind": "BLOCK_SPLIT", "note": "User corrected to A", "source": "group_rule", "uop_kind": "CMD"}`
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_fixp.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_fixp.adoc
deleted file mode 100644
index 6737ed8d..00000000
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_fixp.adoc
+++ /dev/null
@@ -1,20 +0,0 @@
----
-// Auto-generated instruction documentation
-// Do not edit by hand
-
-[[inst_bstart_fixp]]
-==== BSTART.FIXP
-
-*Syntax:* BSTART.FIXP TileOp, DataType
-
-*Description:* Block start marker: BSTART.FIXP with split semantics.
-
-*Encoding:*
-
-image::encodings/enc_bstart_fixp.svg[BSTART.FIXP encoding,width=800]
-
-*Uop-Class:* CMD
-
-*Compression:* L32 (len=32)
-
-*Uop-Class payload:* `{"cmd_kind": "BLOCK_SPLIT", "note": "User corrected to A", "source": "group_rule", "uop_kind": "CMD"}`
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_mgather.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_mgather.adoc
index 4f775ebf..f6cef428 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_mgather.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/bstart_mgather.adoc
@@ -7,7 +7,7 @@
 
 *Syntax:* BSTART.MGATHER DataType
 
-*Description:* Named TMA-family Function=4. Memory gather uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57.
+*Description:* TMA Function=4. Memory gather uses B.DATR/B.IOR/B.IOT descriptor state.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_mscatter.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_mscatter.adoc
index ee560bd3..b81a2edb 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_mscatter.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/bstart_mscatter.adoc
@@ -7,7 +7,7 @@
 
 *Syntax:* BSTART.MSCATTER DataType
 
-*Description:* Named TMA-family Function=5. Memory scatter uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57.
+*Description:* TMA Function=5. Memory scatter uses B.DATR/B.IOR/B.IOT descriptor state.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_tepl.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_tepl.adoc
index 43d55fe9..b8e53d1e 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_tepl.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/bstart_tepl.adoc
@@ -5,9 +5,9 @@
 [[inst_bstart_tepl]]
 ==== BSTART.TEPL
 
-*Syntax:* BSTART.TEPL TileOpcode, DataType
+*Syntax:* BSTART.TEPL Mode, Function, DataType
 
-*Description:* Tile opcode selects PTO template ops. Canonical established assignments require TileOpcode[9:6]=0 and pack TileOpcode[5]=Mode with TileOpcode[4:0]=Function; unassigned values remain reserved for future template extension.
+*Description:* PTO ISA 0.57.1 TEPL selector: logical_selector=(Mode<<5)|Function. There is no legacy 10-bit TileOpcode decode.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_tload.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_tload.adoc
index 0ad57f76..665f84a7 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_tload.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/bstart_tload.adoc
@@ -7,7 +7,7 @@
 
 *Syntax:* BSTART.TLOAD DataType
 
-*Description:* Alias of BSTART.TMA Function=0. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding.
+*Description:* TMA Function=0. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_tmatmul.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_tmatmul.adoc
index 1578f0dd..1fc45888 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_tmatmul.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/bstart_tmatmul.adoc
@@ -7,7 +7,7 @@
 
 *Syntax:* BSTART.TMATMUL DataType
 
-*Description:* Alias of BSTART.CUBE Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
+*Description:* Named CUBE-family Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_tmatmul_acc.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_tmatmul_acc.adoc
index 2258dc0d..ee069d59 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_tmatmul_acc.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/bstart_tmatmul_acc.adoc
@@ -7,7 +7,7 @@
 
 *Syntax:* BSTART.TMATMUL.ACC DataType
 
-*Description:* Alias of BSTART.CUBE Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
+*Description:* Named CUBE-family Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/instructions/bstart_tstore.adoc b/docs/architecture/isa-manual/src/generated/instructions/bstart_tstore.adoc
index 7dd2d369..ba86ce93 100644
--- a/docs/architecture/isa-manual/src/generated/instructions/bstart_tstore.adoc
+++ b/docs/architecture/isa-manual/src/generated/instructions/bstart_tstore.adoc
@@ -7,7 +7,7 @@
 
 *Syntax:* BSTART.TSTORE DataType
 
-*Description:* Alias of BSTART.TMA Function=1. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding.
+*Description:* TMA Function=1. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding.
 
 *Encoding:*
 
diff --git a/docs/architecture/isa-manual/src/generated/mnemonic_index.adoc b/docs/architecture/isa-manual/src/generated/mnemonic_index.adoc
index a2676381..bf9d8d73 100644
--- a/docs/architecture/isa-manual/src/generated/mnemonic_index.adoc
+++ b/docs/architecture/isa-manual/src/generated/mnemonic_index.adoc
@@ -3,7 +3,7 @@
 [[mnemonic-index]]
 === Mnemonic index
 
-This table lists unique mnemonics in the v0.57.0 catalog. Each mnemonic may have multiple encodable forms (different lengths, operand layouts, or suffix variants).
+This table lists unique mnemonics in the v0.57.1 catalog. Each mnemonic may have multiple encodable forms (different lengths, operand layouts, or suffix variants).
 
 [cols="2,3,1,1",options="header"]
 |===
@@ -20,7 +20,6 @@ This table lists unique mnemonics in the v0.57.0 catalog. Each mnemonic may have
 |`ANDIW` |Arithmetic Operation 32bit |32 |1
 |`ANDW` |Arithmetic Operation 32bit |32 |1
 |`ASSERT` |Execution Control |32 |1
-|`B.ARG` |Block Argument |32 |6
 |`B.CATR` |Block Control Attribute |32 |1
 |`B.DATR` |Block Data Attribute |32 |1
 |`B.DIM` |Block Argument |32 |3
@@ -45,8 +44,6 @@ This table lists unique mnemonics in the v0.57.0 catalog. Each mnemonic may have
 |`BSTART` |Block Split |32 |2
 |`BSTART CALL` |BSTART |32 |1
 |`BSTART.ACCCVT` |Block Split |32 |1
-|`BSTART.CUBE` |Block Split |32 |1
-|`BSTART.FIXP` |Block Split |32 |1
 |`BSTART.FP` |Block Split |32 |7
 |`BSTART.MGATHER` |Block Split |32 |1
 |`BSTART.MGATHER.CAS` |Block Split |32 |1
diff --git a/docs/architecture/isa-manual/src/generated/system_registers_ssr.adoc b/docs/architecture/isa-manual/src/generated/system_registers_ssr.adoc
index 6acb3d8c..05d4231b 100644
--- a/docs/architecture/isa-manual/src/generated/system_registers_ssr.adoc
+++ b/docs/architecture/isa-manual/src/generated/system_registers_ssr.adoc
@@ -54,8 +54,8 @@ Use `HL.SSRGET/HL.SSRSET` when the full `SSR_ID` does not fit in 12 bits.
 |`0xnf05` |`ETEMP_ACRn` |RW |Exception temporary register.
 |`0xnf06` |`ETEMP0_ACRn` |RW |Exception temporary register 0 (v0.2 bring-up).
 |`0xnf07` |`ECONFIG_ACRn` |RW |Exception/interrupt configuration.
-|`0xnf08` |`IPENDING_ACRn` |RW |Interrupt pending bitmap.
-|`0xnf09` |`TOPEI_ACRn` |RW |Top pending interrupt ID.
+|`0xnf08` |`IPENDING_ACRn` |RO |Interrupt pending bitmap.
+|`0xnf09` |`TOPEI_ACRn` |RO |Top pending interrupt ID.
 |`0xnf0A` |`EOIEI_ACRn` |WO |End-of-interrupt.
 |`0xnf10` |`TTBR0_ACR1` |RW |CPU MMU table base register 0 (ACR1).
 |`0xnf11` |`TTBR1_ACR1` |RW |CPU MMU table base register 1 (ACR1).
diff --git a/docs/architecture/pto-isa-v0.57.1-upgrade-plan.md b/docs/architecture/pto-isa-v0.57.1-upgrade-plan.md
new file mode 100644
index 00000000..5514e6d2
--- /dev/null
+++ b/docs/architecture/pto-isa-v0.57.1-upgrade-plan.md
@@ -0,0 +1,239 @@
+# PTO ISA 0.57.1 upgrade plan
+
+Status: accepted implementation plan
+
+Decision date: 2026-07-30
+
+## Authority and release identity
+
+[`PTO-ISA/pto-spec`](https://github.com/PTO-ISA/pto-spec) is the sole
+normative source for PTO ISA 0.57.1. LinxISA and DavinciOO are projections and
+implementations of the locked pto-spec release manifest; neither repository may
+override an encoding, operation signature, fault rule, or conformance vector.
+
+The upgrade starts from these fetched upstream commits:
+
+| Repository | Baseline |
+| --- | --- |
+| `PTO-ISA/pto-spec` | `8054a21fc7f98318f936b1dff9d2132b2aa990be` |
+| `LinxISA/linx-isa` | `98c08198a83ca03a832514b2b5cca27d4c30fa6d` |
+| `hengliao1972/DavinciOO` | `da1c1f7bf276b223fc49acf7027a46409620e017` |
+
+PTO ISA 0.57.1 is an encoding-ABI break despite the patch release number. An
+object or executable must carry the architecture release and canonical
+encoding-manifest identity. Producers, linkers, loaders, and bare-metal launch
+manifests reject missing, old, mixed, or mismatched identities. There is no
+untagged dual decoder; legacy source is reassembled or recompiled.
+
+ELF identity uses `.note.pto.isa` with owner bytes `PTO\0`, owner-local note
+type `1` (`PTO_NT_ISA_IDENTITY`), and four-byte alignment. Its descriptor is
+the canonical compact JSON identity object without a trailing NUL byte. These
+wire details come from the locked pto-spec release manifest and are shared by
+LLVM, LLD, the kernel, and dynamic loaders.
+
+## Frozen architecture delta
+
+### Direct operations
+
+The base inventory is exactly 120 operations: 98 TEPL, 9 TMA, and 13 CUBE,
+with zero optional direct operations.
+
+- Delete and reserve `TFMA`, `TFMOD`, `TFMODS`, `TADDC`, `TSUBC`, `TADDSC`,
+  `TSUBSC`, `TLRELU`, and `TRANDOM`.
+- Use canonical `TTRANS` and `TSORT`; `TTRANSPOSE` and `TSORT32` are
+  source-migration aliases only.
+- Add `TPARTARGMAX`, `TPARTARGMIN`, `TRESHAPE`, `TDEINTERLEAVE`,
+  `TINTERLEAVE`, `TPUSH`, `TPOP`, `TALLOC`, and `TFREE` at Mode 3 Functions
+  21 through 29.
+- TMA Functions 0 through 8 are `TLOAD`, `TSTORE`, `TMOV`, `TPREFETCH`,
+  `MGATHER`, `MSCATTER`, `MGATHER.MASK`, `MSCATTER.MASK`, and `MGATHER.CAS`.
+- All 13 CUBE functions are base identities. ACC access is selected by the
+  CUBE function, not by a B.IOT operand.
+
+### Raw command formats
+
+| Form | 0.57.1 contract |
+| --- | --- |
+| `BSTART.TEPL` | `DataType[31:27]`, `Mode[26:25]`, `Function[24:20]`, fixed low pattern `0x00019181`; mask `0x000fffff` |
+| `B.IOT` | `Src1[31:26]`, `Src0[25:20]`, `L[19]`, `imm4[18:15]`, `S1R[11]`, `S0R[10]`, `Dst[9:7]` |
+| `B.DATR` | `CMode[31:29]`, `PadValueOrByteId[28:27]`, `Sat[26]`, `Canonicalize[25]`, `DataType[24:20]`, `RMode[17:15]`, `Layout[11:7]` |
+| `B.CATR` | `DR[26]`, `trap[19]`, `far[18]`, `atom[17]`, `aq[16]`, `rl[15]`; all other dynamic high fields zero |
+
+The TEPL logical selector is `(Mode << 5) | Function`. All 128 selector
+positions are classified as one of 98 accepted or 30 reserved positions.
+DataType code 31 is illegal. Complete `DataType × Mode × Function` evidence
+must classify all 4096 header values without collision or fallback.
+
+The retired legacy Tile descriptor header, generic public `BSTART.TLSU`,
+generic unallocated `BSTART.CUBE`, and
+`BSTART.FIXP` are not executable 0.57.1 forms. Typed
+`BSTART.<TMA-operation> DataType` is canonical. TMA descriptors are owned by
+the operation schema plus B.IOR, B.DATR, and applicable B.DIM fields, not by
+the six legacy TMA-oriented B.ARG forms.
+
+### State and completion
+
+- CELL is 128 bytes; each PE exposes exactly 2048 CELL, or 256 KiB, of Tile
+  capacity. B.IOT size codes 3 through 9 mean 128 B through 8 KiB. Resource
+  exhaustion is a precise allocation fault; no silent eviction or spill is
+  architectural.
+- `reuse=0` releases a source only after successful consumer commit;
+  `reuse=1` retains it. Fault, retry, and squash preserve source lifetime.
+- ACC is implicit architectural state. B.IOT destination codes 4 through 6
+  remain reserved and 7 is illegal. Ordinary/BIAS CUBE functions initialize
+  ACC, `.ACC` functions read/write it, and ACCCVT publishes a Tile and releases
+  ACC only after successful commit. Trap context includes ACC.
+- NORM layout is mandatory. ND/DN/ZN/NZ conversion codes are capability
+  gated; an unsupported accepted layout faults precisely before effects.
+- A false mask lane performs no access or fault check. Masked gather writes
+  B.DATR PadValue to inactive destination lanes. Multi-access operations
+  preflight all active accesses and commit no partial state on failure.
+- Non-atomic duplicate-address scatter has an unspecified winning active lane
+  after complete successful preflight. PTO-TSO and B.CATR define ordering;
+  dependency metadata is not a fence.
+- The hardware conformance profile is IEEE-754 with canonical quiet NaN and
+  IEEE signed zero. The deterministic raw-carrier model remains a separately
+  identified reference-test profile.
+- TSORT is stable over 32-element groups and produces values plus U32 original
+  indices. NaNs follow numeric values while retaining input order.
+
+### Numeric and matrix conformance
+
+The hardware numeric identity is
+`pto-hardware-numeric-0.57.1-ieee-v1`. The release lock freezes both the
+hardware profile and its executable vectors; sharing only the encoding hash is
+not a conformance claim.
+
+- The assigned low-precision formats are the exact OCP `E4M3`, `E5M2`,
+  `E3M2`, `E2M3`, `E2M1`, and `E8M0` encodings. `HiF8` uses the Ascend
+  dynamic Dot/Exponent/Mantissa encoding. `HiF4X2` uses the public E1M2 value
+  table but remains a distinct DataType identity from `E1M2X2`.
+- Packed DataTypes use logical lanes: lane `2*i` is the low nibble and lane
+  `2*i+1` is the high nibble. Shape, matrix, and scale dimensions count these
+  logical lanes, not carrier bytes.
+- Ordinary matrix operations accept the 24 assigned non-`E8M0` DataTypes with
+  identical left, right, header, and logical bias types. Physical ACC is FP64
+  for FP64, FP32 for other floating formats, S64 for signed integer formats,
+  and U64 for unsigned integer formats.
+- MX accepts all four ordered pairs over `E4M3`/`E5M2` and all four ordered
+  pairs over `E2M1X2`/`HiF4X2`. Header, ACC, and bias are FP32; both scale
+  inputs are E8M0. One scale covers 32 logical K elements, with ScaleA shape
+  `M x ceil(K/32)` and ScaleB shape `ceil(K/32) x N`, and scaling occurs before
+  each fused multiply-add.
+- BIAS is added after the complete dot product in the logical result type;
+  MX BIAS is FP32. `.ACC` starts from the old ACC and adds the newly scaled
+  product. ACCCVT publishes the complete rounded Tile before releasing ACC.
+- Invalid float-to-signed conversion produces the destination minimum; invalid
+  float-to-unsigned conversion produces the destination maximum. Packed lanes
+  convert independently. RHB means nearest with exact ties toward positive
+  infinity.
+
+## Baseline differences that must close
+
+### pto-spec
+
+The baseline already has the right 98/9/13 names, but 80 of 98 TEPL selectors
+use the old 10-bit layout. B.IOT, B.DATR, and B.CATR are also old. Raw BSTART
+decode is not connected to direct Tile execution; reuse fields have no commit
+effect; capacity is 512 KiB; ACC and layout capabilities are absent; masked
+gather preserves stale destination data; and binary closure omits Tile/catalog
+and semantic content. The release PR must close those behaviors in ASL, not
+only update catalog rows.
+
+### LinxISA
+
+The baseline golden release is 0.57.0. `pto_ops.json` still derives 111 rows
+from the old workbook, while `engine_ops.json` has 120 names but 55 pending
+semantic records and the old raw ABI. Sail reports zero PTO operations as
+architecturally complete. LLVM, PTOAS, QEMU, LinxCore, the C++ models, kernel,
+glibc, and musl have independent copies of encodings or ABI assumptions.
+
+### DavinciOO
+
+The latest `isa/intrinsic` tree has no delta between its local intrinsic commit
+and fetched `origin/main`, but its workbook contains only 87 TEPL, 5 TMA, and
+8 CUBE rows. It includes deleted operations, misses retained PTO operations,
+contains a duplicate/wrong TSEL assignment, and describes a retired Tile
+descriptor header,
+TPREFETCH, ACC, layout, and descriptor rules. Nearly all authored and generated
+intrinsic content contains Linx branding, and generation has neither a locked
+pto-spec input nor an exact-file-set check.
+
+## PR dependency graph
+
+```mermaid
+flowchart TD
+  PTO["pto-spec: normative 0.57.1 + manifest"] --> GOLDEN["LinxISA golden + validators + Sail"]
+  PTO --> DAV["DavinciOO neutral intrinsic projection"]
+  GOLDEN --> PROD["LLVM + PTOAS producers and ABI tags"]
+  GOLDEN --> EXEC["QEMU + RTL + model consumers"]
+  PROD --> LOAD["LLD + kernel + glibc + musl identity rejection"]
+  EXEC --> AVS["AVS differential and semantic gates"]
+  LOAD --> AVS
+  AVS --> PIN["Superproject leaf SHA repin and release promotion"]
+```
+
+The normative pto-spec PR merges first. Every downstream PR locks its exact
+commit and manifest hash. The LinxISA superproject repins only leaf commits
+whose local gates passed; it never points at unmerged or unverified semantic
+work.
+
+## Repository ownership and gates
+
+| Lane | Required output | Blocking evidence |
+| --- | --- | --- |
+| pto-spec | ADR, catalogs, executable ASL, requirements, release manifest, vectors | repository checks, strict ASL typecheck/tests, 4096 totality, zero pending, stable regeneration |
+| Linx golden/Sail | locked pto manifest, 0.57.1 golden, decode and architectural semantics | golden validator, 120 raw positives, retired negatives, Sail typecheck/tests |
+| LLVM/PTOAS | canonical assembly/IR lowering, release/hash ELF attribute | MC roundtrip, CodeGen, mixed/missing ABI link rejection |
+| QEMU | exact decode, preflight/commit, ACC/lifetime/mask behavior | AVS QEMU Tile suites and pto-spec vector parity |
+| LinxCore/models | generated identifiers and commit/fault interfaces | unit tests plus QEMU/model differential vectors |
+| kernel/libc loaders | release/hash enforcement | matching acceptance and missing/old/mixed/hash-mismatch rejection |
+| DavinciOO | neutral locked projection, 120 pages/rows, deterministic site/workbook | exact owned set, zero Linx token including XLSX, selector/vector parity |
+| superproject | verified submodule SHAs and run manifest | layout check, pin/external lanes, full benchmark/QEMU/Linux flow |
+
+## Submodule synchronization matrix
+
+The following leaf repositories contain an ISA producer, consumer, loader, or
+conformance surface and require a reviewed commit before final repin:
+
+| Submodule | Upgrade responsibility |
+| --- | --- |
+| `compiler/llvm` | assembler, disassembler, MC/CodeGen, ELF attribute, LLD checks, MLIR PTO dialect |
+| `compiler/ptoas` | PTO IR/bytecode identities, typed TMA lowering, manifest gate |
+| `emulator/qemu` | decode and executable Tile semantics |
+| `rtl/LinxCore` | generated decode/catalog and precise commit/fault interface |
+| `tools/model` | generated tables and architectural reference state |
+| `tools/LinxCoreModel` | remove D operations and ACC-as-B.IOT assumptions |
+| `kernel/linux` | ELF loader identity rejection and trap/context ABI |
+| `lib/glibc` | dynamic-loader identity check |
+| `lib/musl` | dynamic-loader identity check |
+| `workloads/pto_kernels` | recompile and semantic parity vectors |
+
+`tools/pyCircuit`, `workloads/SuperNPUBench`, and other workload/RTL-facing
+submodules are repinned only if their generated artifacts or rebuild evidence
+changes. Existing user-owned submodule worktrees are never overwritten by the
+upgrade branch.
+
+## Completion criteria
+
+The release is complete only when all of the following hold:
+
+1. All three top-level repositories report the same pto-spec commit, release,
+   encoding ABI ID, and canonical content hash.
+2. The 120 base operations have machine-readable operands, legality, effects,
+   faults, restart, state-access, semantic handler, and executable evidence;
+   pending and optional counts are zero.
+3. Accepted, reserved, illegal, deleted, old-ABI, and six semantic-collision
+   raw words are covered by positive or negative evidence without heuristic
+   decode.
+4. Fault/retry/squash preserve Tile lifetime and ACC, and multi-access faults
+   produce no partial effects.
+5. Compiler, assembler, linker, loader, QEMU, RTL/model, Sail, and DavinciOO
+   projections agree byte-for-byte or effect-for-effect with pto-spec vectors.
+6. Generated source, documentation, workbook, and site checks are stable on a
+   second run and reject extra stale files.
+7. DavinciOO public intrinsic content contains no Linx ISA branding, including
+   compressed XLSX strings.
+8. Every required leaf PR is merged or pinned to an explicitly reviewed commit,
+   the superproject layout gate passes, and the benchmark/QEMU/Linux bring-up
+   manifest records the final SHA set.
diff --git a/docs/architecture/v0.57-encoding-decisions.md b/docs/architecture/v0.57-encoding-decisions.md
index dfe379cf..1e8391c4 100644
--- a/docs/architecture/v0.57-encoding-decisions.md
+++ b/docs/architecture/v0.57-encoding-decisions.md
@@ -1,7 +1,8 @@
-# LinxISA v0.57 Encoding Decisions
+# LinxISA v0.57.1 Encoding Decisions
 
-This page records the normative v0.57 encoding assignments. Encodings not
-named here remain defined by the canonical v0.57 opcode catalog.
+This page records the Linx projection of the normative PTO ISA 0.57.1
+assignments. Encodings not named here remain defined by the canonical v0.57
+opcode catalog and the locked PTO truth source.
 
 ## Stability Rule
 
@@ -48,17 +49,19 @@ Architecturally, `TPREFETCH` is `TLOAD` without destinations. It uses the same
 address-generation and memory contract as `TLOAD`, but it must not allocate or
 write a tile destination.
 
-## PTO Selector Manifest Rule
+## PTO selector manifest rule
 
-The exact 111-operation PTO map is authoritative in:
+The exact 120-operation PTO map (98 TEPL, 9 TMA, and 13 CUBE) is the
+reviewed projection in:
 
 `isa/v0.57/state/pto_encoding_map.json`
 
-The source workbook is normalized into `pto_ops.json` and is never read by the
-normal build. Workbook row order does not allocate encodings. Existing
-Established TEPL selectors are preserved; new selectors use only
-`0x02B..0x048`, `0x080..0x08B`, `0x0C0..0x0C8`, and `0x0E0..0x0E3`.
-All other 10-bit values remain reserved.
+Its normative input is the commit and hashes frozen by
+`isa/v0.57/pto-spec.lock.json`; no workbook allocates an encoding. TEPL uses
+the raw two-bit `Mode` plus five-bit `Function` fields, so the logical selector
+is `(Mode << 5) | Function`. Exactly 98 of the 128 selector positions are
+accepted and the other 30 are reserved. The generator rejects any attempt to
+recover the retired 10-bit selector ABI.
 
 ## CUBE Function Map
 
@@ -70,17 +73,20 @@ The PTO matrix rows use the inherited CUBE family plus named aliases:
 | 1 | `BSTART.TMATMUL.BIAS` | `TMATMUL_BIAS` |
 | 2 | `BSTART.TMATMUL.ACC` | `TMATMUL_ACC` |
 | 4 | `BSTART.TMATMULMX` | `TMATMUL_MX` |
+| 5 | `BSTART.TMATMULMX.BIAS` | `TMATMUL_MX_BIAS` |
+| 6 | `BSTART.TMATMULMX.ACC` | `TMATMUL_MX_ACC` |
+| 8 | `BSTART.ACCCVT` | `ACCCVT` |
 | 16 | `BSTART.TGEMV` | `TGEMV` |
 | 17 | `BSTART.TGEMV.BIAS` | `TGEMV_BIAS` |
 | 18 | `BSTART.TGEMV.ACC` | `TGEMV_ACC` |
 | 20 | `BSTART.TGEMVMX` | `TGEMV_MX` |
+| 21 | `BSTART.TGEMVMX.BIAS` | `TGEMV_MX_BIAS` |
+| 22 | `BSTART.TGEMVMX.ACC` | `TGEMV_MX_ACC` |
 
-Documented named aliases also exist at functions 5, 6, 21, and 22 for the
-micro-scaled bias and accumulate variants. The generic
-`BSTART.CUBE Function, DataType` form remains legal; function
-values without a named alias therefore retain only that generic decode. The
-generic form excludes the 13 named functions above, so each raw word has one
-canonical decode and the encoding-space overlap gate remains clean.
+Only these 13 assigned named CUBE functions are legal. Every unassigned
+function is an illegal instruction; there is no generic executable
+`BSTART.CUBE Function, DataType` form. ACC is implicit architectural state and
+is never named by a B.IOT source or destination field.
 
 ## Scalar Encoding Evidence
 
@@ -105,5 +111,10 @@ Assemblers, decoders, and tests must reject:
 
 - generic mixed TMA source forms,
 - unassigned TMA functions,
+- all 30 reserved TEPL Mode/Function selectors,
+- generic `BSTART.CUBE` and `BSTART.FIXP`,
+- the retired B.ARG Tile descriptor carrier,
+- `TFMA`, `TFMOD`, `TFMODS`, `TADDC`, `TSUBC`, `TADDSC`, `TSUBSC`,
+  `TLRELU`, and `TRANDOM`,
 - retired compatibility spellings from pre-v0.57 sources,
-- PTO selector numbers not present in the frozen v0.57 manifest.
+- PTO operations not present in the frozen 0.57.1 manifest.
diff --git a/docs/architecture/v0.57-hardening-policy.md b/docs/architecture/v0.57-hardening-policy.md
index 1813ca00..4a002386 100644
--- a/docs/architecture/v0.57-hardening-policy.md
+++ b/docs/architecture/v0.57-hardening-policy.md
@@ -26,8 +26,8 @@ Any hardening work under `v0.57` MUST preserve these already-frozen rules:
   execution across workload classes,
 - `MPAR` VEC kernels remain the required functional fallback for rendering PTOs,
 - TAU execution remains tile-to-tile only,
-- small or rarely changing state remains descriptor-driven through `B.ARG` and
-  `B.IOR`,
+- small or rarely changing state remains descriptor-driven through `B.DATR`,
+  `B.DIM`, and `B.IOR`,
 - larger or hot state remains explicit through referenced records or StateTiles,
 - hidden execution state outside the architectural block stream and referenced
   state records is not part of the canonical model.
@@ -95,8 +95,8 @@ tile-state records:
 
 - intermediate rendering state crossing between blocks or engines is carried in
   tiles,
-- small parameters and descriptor-like state are carried through `B.ARG` and
-  `B.IOR`,
+- small parameters and descriptor-like state are carried through `B.DATR`,
+  `B.DIM`, and `B.IOR`,
 - larger or hotter rendering state remains in explicit StateTiles,
 - TAU-facing work MUST consume and produce tile-visible state so the fallback
   boundary remains explicit and observable.
diff --git a/docs/architecture/v0.57-rendering-command-contract.md b/docs/architecture/v0.57-rendering-command-contract.md
index 30fbcad1..be3093dc 100644
--- a/docs/architecture/v0.57-rendering-command-contract.md
+++ b/docs/architecture/v0.57-rendering-command-contract.md
@@ -90,7 +90,7 @@ Pipeline and render-state bundles are canonicalized as referenced records, not
 as opaque command-processor private state.
 
 - Small or rarely changing values SHOULD be emitted directly through descriptor
-  operands such as `B.ARG` and `B.IOR`.
+  operands such as `B.DATR`, `B.DIM`, and `B.IOR`.
 - Larger or hot state MAY be materialized into referenced records or StateTiles
   and then named explicitly from the lowered block stream.
 - Pipeline-state objects, descriptor tables, and similar reused state MUST be
diff --git a/docs/architecture/v0.57-rendering-pto-contract.md b/docs/architecture/v0.57-rendering-pto-contract.md
index 9a0495b0..3fe504d4 100644
--- a/docs/architecture/v0.57-rendering-pto-contract.md
+++ b/docs/architecture/v0.57-rendering-pto-contract.md
@@ -12,8 +12,7 @@ names remain planning-only until a later catalog revision assigns them.
 - rendering-oriented use of PTO-style tile operations,
 - canonical mapping from rendering PTOs to current `v0.57` block carriers,
 - rules for TEPL selector use,
-- explicit non-assignment of rendering PTO semantics to `BSTART.FIXP` in the
-  current canonical profile.
+- explicit retirement of `BSTART.FIXP` from the current canonical profile.
 
 This page is normative for rendering PTO naming and carrier selection in live
 `v0.57` docs, examples, tests, and bring-up artifacts.
@@ -26,7 +25,7 @@ Canonical `v0.57` rendering PTOs use these carriers:
   `TileOpcode` values,
 - canonical `BSTART.TLOAD`, `BSTART.TSTORE`, and `BSTART.TMOV` forms for tile movement
   and tile-memory plumbing,
-- `BSTART.CUBE` aliases such as `TMATMUL`, `TMATMUL.ACC`, and `ACCCVT` for the
+- named CUBE-family forms such as `TMATMUL`, `TMATMUL.ACC`, and `ACCCVT` for the
   current matrix/accumulator engine path,
 - `BSTART.MPAR` VEC kernels as the required functional fallback when no
   canonical TEPL or other hardened mapping exists.
@@ -53,23 +52,21 @@ canonical `v0.57`.
 
 ## `BSTART.FIXP` Rule
 
-`BSTART.FIXP` exists in the opcode catalog as a block-split form, but canonical
-`v0.57` does not currently assign it a rendering PTO selector catalog, a
-machine-readable semantic profile, or a rendering-specific descriptor contract.
+`BSTART.FIXP` is retired and has no legal opcode in PTO ISA 0.57.1. It has no
+rendering selector catalog, machine-readable semantic profile, or
+rendering-specific descriptor contract.
 
 Therefore:
 
 - rendering PTOs MUST NOT be assigned to `BSTART.FIXP` in canonical `v0.57`
   docs, AVS, examples, or normalized output,
-- new rendering operations MUST NOT be routed to `BSTART.FIXP` unless a later
-  canonical revision adds:
+- a later revision may reintroduce a distinct form only by adding:
   - machine-readable selector assignments,
   - manual semantics,
   - descriptor requirements,
   - and validation coverage.
 
-In the current profile, `BSTART.FIXP` is not the canonical carrier for
-rendering PTO work.
+In the current profile, `BSTART.FIXP` must decode as an illegal instruction.
 
 ## Canonical Rendering-Relevant PTO Set Today
 
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/linx-qemu-tests.elf
new file mode 100755
index 00000000..257d8db9
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/linx-qemu-tests.o
new file mode 100644
index 00000000..9f1c3b06
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic.o
new file mode 100644
index 00000000..4bb0fed3
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic_lr_srczero.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic_lr_srczero.o
new file mode 100644
index 00000000..d9c8a663
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic_lr_srczero.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic_lr_srczero.s b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic_lr_srczero.s
new file mode 100644
index 00000000..6585bc57
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic_lr_srczero.s
@@ -0,0 +1,32 @@
+	.text
+	.align 2
+
+	.globl atomic_lr_w_nonzero_srczero
+	.type atomic_lr_w_nonzero_srczero,@function
+atomic_lr_w_nonzero_srczero:
+	C.BSTART.STD RET
+	# LR.W RegDst=a0, SrcL=a0, SrcZero=31.
+	.4byte 0x21f1010b
+	c.setc.tgt ra
+	C.BSTOP
+	.size atomic_lr_w_nonzero_srczero, .-atomic_lr_w_nonzero_srczero
+
+	.globl atomic_lr_w_signext
+	.type atomic_lr_w_signext,@function
+atomic_lr_w_signext:
+	C.BSTART.STD RET
+	# LR.W RegDst=a0, SrcL=a0, SrcZero=31.
+	.4byte 0x21f1010b
+	c.setc.tgt ra
+	C.BSTOP
+	.size atomic_lr_w_signext, .-atomic_lr_w_signext
+
+	.globl atomic_lr_d_nonzero_srczero
+	.type atomic_lr_d_nonzero_srczero,@function
+atomic_lr_d_nonzero_srczero:
+	C.BSTART.STD RET
+	# LR.D RegDst=a0, SrcL=a0, SrcZero=17.
+	.4byte 0x3111010b
+	c.setc.tgt ra
+	C.BSTOP
+	.size atomic_lr_d_nonzero_srczero, .-atomic_lr_d_nonzero_srczero
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/main.o
new file mode 100644
index 00000000..dcf89668
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/mem.o
new file mode 100644
index 00000000..5b1de528
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.json
new file mode 100644
index 00000000..e0885ea3
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.json
@@ -0,0 +1,421 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/linx-qemu-tests.elf",
+      "sha256": "feb61810002d50f35d41e09c4ba04466f8529b216d8df4f10db95bd57533ec8d"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/linx-qemu-tests.o",
+      "sha256": "4471fef5e01383615be031f001c6a4b08826007a96752a8f40a4e5fcb67dda12"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/main.o",
+        "sha256": "f172b095ab6dc35fb3a045dc38eb7854de6b86c27d251a99c38b480a97e3c2d9"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/mem.o",
+        "sha256": "092fc93cc4ebb1e2a2922e5318f3cefa1b504c23d36a76808b269806f3caac25"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic.o",
+        "sha256": "b736376c57a7352eadc6d1eb63844304727483eb02842a2f086b727a425248e4"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/obj/07_atomic_lr_srczero.o",
+        "sha256": "5b41b861ca3886025beabad50665a020c228d4599333c90c56932de721484029"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log",
+      "sha256": "c1bd2c917b6a8d7f93456192b4e5af07cc3137aca76edc8e65ecd476ae3c7049"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.uart.log",
+      "sha256": "a36603dc0295fd5df79737d20d74ac0b7b10840e69033ecda021be9238121edd"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x000000000001151a",
+      "0x000000000001152e"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 19539,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001151a"
+    },
+    {
+      "count": 20286,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001152e"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "002b4d206321f5ecaa40ef5064ba9756148bbcdc90ec349033f5897729654176",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-pto0571-evidence/qemu-system-linx64",
+    "sha": "583cad3f6ce68d05a559a354a3e7059844f47a5d",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1071-g583cad3f6c)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x1151a,0x1152e",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00007001",
+    "0x00007010",
+    "0x00007020",
+    "0x00007030",
+    "0x00007040",
+    "0x00007050",
+    "0x00007060",
+    "0x00007070",
+    "0x00007080",
+    "0x00007090",
+    "0x000070a0",
+    "0x000070b0",
+    "0x000070c0",
+    "0x000070d0",
+    "0x000070e0",
+    "0x000070e1",
+    "0x000070e2",
+    "0x000070f0",
+    "0x00007100",
+    "0x00007110",
+    "0x00007111",
+    "0x00007120",
+    "0x00007130",
+    "0x00007140",
+    "0x00007150",
+    "0x00007160",
+    "0x00007162",
+    "0x00007163",
+    "0x00007164"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x00007160"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "a36603dc0295fd5df79737d20d74ac0b7b10840e69033ecda021be9238121edd",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "atomic"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00007001"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00007001"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00007010"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00007010"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00007020"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00007020"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00007030"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00007030"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00007040"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00007040"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00007050"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00007050"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00007060"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00007060"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00007070"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00007070"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00007080"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00007080"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x00007090"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x00007090"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x000070a0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x000070a0"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x000070b0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x000070b0"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x000070c0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x000070c0"
+    },
+    {
+      "kind": "START",
+      "seq": 26,
+      "test_id": "0x000070d0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 27,
+      "test_id": "0x000070d0"
+    },
+    {
+      "kind": "START",
+      "seq": 28,
+      "test_id": "0x000070e0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 29,
+      "test_id": "0x000070e0"
+    },
+    {
+      "kind": "START",
+      "seq": 30,
+      "test_id": "0x000070e1"
+    },
+    {
+      "kind": "PASS",
+      "seq": 31,
+      "test_id": "0x000070e1"
+    },
+    {
+      "kind": "START",
+      "seq": 32,
+      "test_id": "0x000070e2"
+    },
+    {
+      "kind": "PASS",
+      "seq": 33,
+      "test_id": "0x000070e2"
+    },
+    {
+      "kind": "START",
+      "seq": 34,
+      "test_id": "0x000070f0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 35,
+      "test_id": "0x000070f0"
+    },
+    {
+      "kind": "START",
+      "seq": 36,
+      "test_id": "0x00007100"
+    },
+    {
+      "kind": "PASS",
+      "seq": 37,
+      "test_id": "0x00007100"
+    },
+    {
+      "kind": "START",
+      "seq": 38,
+      "test_id": "0x00007110"
+    },
+    {
+      "kind": "PASS",
+      "seq": 39,
+      "test_id": "0x00007110"
+    },
+    {
+      "kind": "START",
+      "seq": 40,
+      "test_id": "0x00007111"
+    },
+    {
+      "kind": "PASS",
+      "seq": 41,
+      "test_id": "0x00007111"
+    },
+    {
+      "kind": "START",
+      "seq": 42,
+      "test_id": "0x00007120"
+    },
+    {
+      "kind": "PASS",
+      "seq": 43,
+      "test_id": "0x00007120"
+    },
+    {
+      "kind": "START",
+      "seq": 44,
+      "test_id": "0x00007130"
+    },
+    {
+      "kind": "PASS",
+      "seq": 45,
+      "test_id": "0x00007130"
+    },
+    {
+      "kind": "START",
+      "seq": 46,
+      "test_id": "0x00007140"
+    },
+    {
+      "kind": "PASS",
+      "seq": 47,
+      "test_id": "0x00007140"
+    },
+    {
+      "kind": "START",
+      "seq": 48,
+      "test_id": "0x00007150"
+    },
+    {
+      "kind": "PASS",
+      "seq": 49,
+      "test_id": "0x00007150"
+    },
+    {
+      "kind": "START",
+      "seq": 50,
+      "test_id": "0x00007162"
+    },
+    {
+      "kind": "PASS",
+      "seq": 51,
+      "test_id": "0x00007162"
+    },
+    {
+      "kind": "START",
+      "seq": 52,
+      "test_id": "0x00007163"
+    },
+    {
+      "kind": "PASS",
+      "seq": 53,
+      "test_id": "0x00007163"
+    },
+    {
+      "kind": "START",
+      "seq": 54,
+      "test_id": "0x00007164"
+    },
+    {
+      "kind": "PASS",
+      "seq": 55,
+      "test_id": "0x00007164"
+    },
+    {
+      "kind": "START",
+      "seq": 56,
+      "test_id": "0x00007160"
+    },
+    {
+      "kind": "PASS",
+      "seq": 57,
+      "test_id": "0x00007160"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
new file mode 100644
index 00000000..7a0698c4
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
@@ -0,0 +1,2 @@
+linx_pc_watch: pc=0x1151a hit=1 printed=1 count=19539 sp=0x7feff50 a0=0x12000 a1=0x0 a2=0x1 ra=0x10bc4 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=7 tgt=0x0 bpc=0x11518 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1152e hit=1 printed=1 count=20286 sp=0x7feff50 a0=0x12008 a1=0x89abcdef a2=0x1234abcd ra=0x10c32 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=7 tgt=0x0 bpc=0x1152c tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.uart.log
new file mode 100644
index 00000000..38115a50
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v057-583cad3f-20260731-r1/run-evidence.uart.log
@@ -0,0 +1,40 @@
+Linx QEMU tests
+  Test 0x00007001: PASS
+  Test 0x00007010: PASS
+  Test 0x00007020: PASS
+  Test 0x00007030: PASS
+  Test 0x00007040: PASS
+  Test 0x00007050: PASS
+  Test 0x00007060: PASS
+  Test 0x00007070: PASS
+  Test 0x00007080: PASS
+  Test 0x00007090: PASS
+  Test 0x000070A0: PASS
+  Test 0x000070B0: PASS
+  Test 0x000070C0: PASS
+  Test 0x000070D0: PASS
+  Test 0x000070E0: PASS
+  Test 0x000070E1: PASS
+  Test 0x000070E2: PASS
+  Test 0x000070F0: PASS
+  Test 0x00007100: PASS
+  Test 0x00007110: PASS
+  Test 0x00007111: PASS
+  Test 0x00007120: PASS
+  Test 0x00007130: PASS
+  Test 0x00007140: PASS
+  Test 0x00007150: PASS
+  Test 0x00007162: PASS
+  Test 0x00007163: PASS
+  Test 0x00007164: PASS
+  Test 0x00007160: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf
new file mode 100755
index 00000000..75dfe117
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o
new file mode 100644
index 00000000..18493bae
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic.o
new file mode 100644
index 00000000..f892bca0
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.o
new file mode 100644
index 00000000..2cd47984
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.s b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.s
new file mode 100644
index 00000000..6585bc57
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.s
@@ -0,0 +1,32 @@
+	.text
+	.align 2
+
+	.globl atomic_lr_w_nonzero_srczero
+	.type atomic_lr_w_nonzero_srczero,@function
+atomic_lr_w_nonzero_srczero:
+	C.BSTART.STD RET
+	# LR.W RegDst=a0, SrcL=a0, SrcZero=31.
+	.4byte 0x21f1010b
+	c.setc.tgt ra
+	C.BSTOP
+	.size atomic_lr_w_nonzero_srczero, .-atomic_lr_w_nonzero_srczero
+
+	.globl atomic_lr_w_signext
+	.type atomic_lr_w_signext,@function
+atomic_lr_w_signext:
+	C.BSTART.STD RET
+	# LR.W RegDst=a0, SrcL=a0, SrcZero=31.
+	.4byte 0x21f1010b
+	c.setc.tgt ra
+	C.BSTOP
+	.size atomic_lr_w_signext, .-atomic_lr_w_signext
+
+	.globl atomic_lr_d_nonzero_srczero
+	.type atomic_lr_d_nonzero_srczero,@function
+atomic_lr_d_nonzero_srczero:
+	C.BSTART.STD RET
+	# LR.D RegDst=a0, SrcL=a0, SrcZero=17.
+	.4byte 0x3111010b
+	c.setc.tgt ra
+	C.BSTOP
+	.size atomic_lr_d_nonzero_srczero, .-atomic_lr_d_nonzero_srczero
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/main.o
new file mode 100644
index 00000000..ad962700
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/mem.o
new file mode 100644
index 00000000..dd408f9e
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json
new file mode 100644
index 00000000..9aa2a041
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json
@@ -0,0 +1,421 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "sha256": "9f4c8b9ad623eb34b71a7ae53d73096266e127ab85fd27fadf3cd4d18fce41a2"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o",
+      "sha256": "694bee10e1c83a36bf7271e91f4137350d4267963c78798861a31563460ee699"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/main.o",
+        "sha256": "3091b9ee9b7f5819cf688a61f7ead554a12f0e426b6976ba2fe27d7766a11655"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/mem.o",
+        "sha256": "31048812dd2be1454c0ba009c2f8381c1ca3417ebd1413a058fc89184dadecec"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic.o",
+        "sha256": "0826d5f52181083891c0479467532f403fc3eb4dade4878f303d9c1f95201b2b"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.o",
+        "sha256": "ae567cb616f141cfcbe80841346b3e887bc12e60804d0a8da71fca021f7a16cf"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log",
+      "sha256": "c1bd2c917b6a8d7f93456192b4e5af07cc3137aca76edc8e65ecd476ae3c7049"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.uart.log",
+      "sha256": "a36603dc0295fd5df79737d20d74ac0b7b10840e69033ecda021be9238121edd"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x000000000001151a",
+      "0x000000000001152e"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 19539,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001151a"
+    },
+    {
+      "count": 20286,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001152e"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "c6176cc23eef482e5a64ee4f728a22fd44f35aac214a9d0c389fc8aa03ef0290",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-v0571-clean/qemu-system-linx64",
+    "sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1067-gcfc253e844)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x1151a,0x1152e",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00007001",
+    "0x00007010",
+    "0x00007020",
+    "0x00007030",
+    "0x00007040",
+    "0x00007050",
+    "0x00007060",
+    "0x00007070",
+    "0x00007080",
+    "0x00007090",
+    "0x000070a0",
+    "0x000070b0",
+    "0x000070c0",
+    "0x000070d0",
+    "0x000070e0",
+    "0x000070e1",
+    "0x000070e2",
+    "0x000070f0",
+    "0x00007100",
+    "0x00007110",
+    "0x00007111",
+    "0x00007120",
+    "0x00007130",
+    "0x00007140",
+    "0x00007150",
+    "0x00007160",
+    "0x00007162",
+    "0x00007163",
+    "0x00007164"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x00007160"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "a36603dc0295fd5df79737d20d74ac0b7b10840e69033ecda021be9238121edd",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "atomic"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00007001"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00007001"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00007010"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00007010"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00007020"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00007020"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00007030"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00007030"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00007040"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00007040"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00007050"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00007050"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00007060"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00007060"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00007070"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00007070"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00007080"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00007080"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x00007090"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x00007090"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x000070a0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x000070a0"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x000070b0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x000070b0"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x000070c0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x000070c0"
+    },
+    {
+      "kind": "START",
+      "seq": 26,
+      "test_id": "0x000070d0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 27,
+      "test_id": "0x000070d0"
+    },
+    {
+      "kind": "START",
+      "seq": 28,
+      "test_id": "0x000070e0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 29,
+      "test_id": "0x000070e0"
+    },
+    {
+      "kind": "START",
+      "seq": 30,
+      "test_id": "0x000070e1"
+    },
+    {
+      "kind": "PASS",
+      "seq": 31,
+      "test_id": "0x000070e1"
+    },
+    {
+      "kind": "START",
+      "seq": 32,
+      "test_id": "0x000070e2"
+    },
+    {
+      "kind": "PASS",
+      "seq": 33,
+      "test_id": "0x000070e2"
+    },
+    {
+      "kind": "START",
+      "seq": 34,
+      "test_id": "0x000070f0"
+    },
+    {
+      "kind": "PASS",
+      "seq": 35,
+      "test_id": "0x000070f0"
+    },
+    {
+      "kind": "START",
+      "seq": 36,
+      "test_id": "0x00007100"
+    },
+    {
+      "kind": "PASS",
+      "seq": 37,
+      "test_id": "0x00007100"
+    },
+    {
+      "kind": "START",
+      "seq": 38,
+      "test_id": "0x00007110"
+    },
+    {
+      "kind": "PASS",
+      "seq": 39,
+      "test_id": "0x00007110"
+    },
+    {
+      "kind": "START",
+      "seq": 40,
+      "test_id": "0x00007111"
+    },
+    {
+      "kind": "PASS",
+      "seq": 41,
+      "test_id": "0x00007111"
+    },
+    {
+      "kind": "START",
+      "seq": 42,
+      "test_id": "0x00007120"
+    },
+    {
+      "kind": "PASS",
+      "seq": 43,
+      "test_id": "0x00007120"
+    },
+    {
+      "kind": "START",
+      "seq": 44,
+      "test_id": "0x00007130"
+    },
+    {
+      "kind": "PASS",
+      "seq": 45,
+      "test_id": "0x00007130"
+    },
+    {
+      "kind": "START",
+      "seq": 46,
+      "test_id": "0x00007140"
+    },
+    {
+      "kind": "PASS",
+      "seq": 47,
+      "test_id": "0x00007140"
+    },
+    {
+      "kind": "START",
+      "seq": 48,
+      "test_id": "0x00007150"
+    },
+    {
+      "kind": "PASS",
+      "seq": 49,
+      "test_id": "0x00007150"
+    },
+    {
+      "kind": "START",
+      "seq": 50,
+      "test_id": "0x00007162"
+    },
+    {
+      "kind": "PASS",
+      "seq": 51,
+      "test_id": "0x00007162"
+    },
+    {
+      "kind": "START",
+      "seq": 52,
+      "test_id": "0x00007163"
+    },
+    {
+      "kind": "PASS",
+      "seq": 53,
+      "test_id": "0x00007163"
+    },
+    {
+      "kind": "START",
+      "seq": 54,
+      "test_id": "0x00007164"
+    },
+    {
+      "kind": "PASS",
+      "seq": 55,
+      "test_id": "0x00007164"
+    },
+    {
+      "kind": "START",
+      "seq": 56,
+      "test_id": "0x00007160"
+    },
+    {
+      "kind": "PASS",
+      "seq": 57,
+      "test_id": "0x00007160"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
new file mode 100644
index 00000000..7a0698c4
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
@@ -0,0 +1,2 @@
+linx_pc_watch: pc=0x1151a hit=1 printed=1 count=19539 sp=0x7feff50 a0=0x12000 a1=0x0 a2=0x1 ra=0x10bc4 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=7 tgt=0x0 bpc=0x11518 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1152e hit=1 printed=1 count=20286 sp=0x7feff50 a0=0x12008 a1=0x89abcdef a2=0x1234abcd ra=0x10c32 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=7 tgt=0x0 bpc=0x1152c tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
new file mode 100644
index 00000000..38115a50
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
@@ -0,0 +1,40 @@
+Linx QEMU tests
+  Test 0x00007001: PASS
+  Test 0x00007010: PASS
+  Test 0x00007020: PASS
+  Test 0x00007030: PASS
+  Test 0x00007040: PASS
+  Test 0x00007050: PASS
+  Test 0x00007060: PASS
+  Test 0x00007070: PASS
+  Test 0x00007080: PASS
+  Test 0x00007090: PASS
+  Test 0x000070A0: PASS
+  Test 0x000070B0: PASS
+  Test 0x000070C0: PASS
+  Test 0x000070D0: PASS
+  Test 0x000070E0: PASS
+  Test 0x000070E1: PASS
+  Test 0x000070E2: PASS
+  Test 0x000070F0: PASS
+  Test 0x00007100: PASS
+  Test 0x00007110: PASS
+  Test 0x00007111: PASS
+  Test 0x00007120: PASS
+  Test 0x00007130: PASS
+  Test 0x00007140: PASS
+  Test 0x00007150: PASS
+  Test 0x00007162: PASS
+  Test 0x00007163: PASS
+  Test 0x00007164: PASS
+  Test 0x00007160: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/linx-qemu-tests.elf
new file mode 100755
index 00000000..b1918da9
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/linx-qemu-tests.o
new file mode 100644
index 00000000..06cb9b29
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diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/14_callret.o b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/14_callret.o
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diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/14_callret_templates.o b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/14_callret_templates.o
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index 00000000..4fd49aeb
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diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/14_callret_templates.s b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/14_callret_templates.s
new file mode 100644
index 00000000..b4fdcbb9
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/14_callret_templates.s
@@ -0,0 +1,153 @@
+	.text
+
+	.globl callret_tpl_fret_stk_slot_redirect
+	.type callret_tpl_fret_stk_slot_redirect,@function
+callret_tpl_fret_stk_slot_redirect:
+	# FENTRY [ra ~ ra], sp!, 16
+	.4byte 0x04a50041
+	c.movr ra, ->a1
+	addtpc %tpcrel_hi(.Lcallret_tpl_fret_stk_redirect), ->a2
+	addi a2, %tpcrel_lo(.Lcallret_tpl_fret_stk_redirect), ->a2
+	sdi a2, [sp, 8]
+	addi zero, 17, ->a0
+	# FRET.STK [ra ~ ra], sp!, 16
+	.4byte 0x04a53041
+.Lcallret_tpl_fret_stk_redirect:
+	C.BSTART.STD RET
+	addi zero, 34, ->a0
+	c.setc.tgt a1
+	C.BSTOP
+	.size callret_tpl_fret_stk_slot_redirect, .-callret_tpl_fret_stk_slot_redirect
+
+	.globl callret_tpl_fret_ra_slot_redirect
+	.type callret_tpl_fret_ra_slot_redirect,@function
+callret_tpl_fret_ra_slot_redirect:
+	# FENTRY [ra ~ ra], sp!, 16
+	.4byte 0x04a50041
+	c.movr ra, ->a1
+	addtpc %tpcrel_hi(.Lcallret_tpl_fret_ra_redirect), ->a2
+	addi a2, %tpcrel_lo(.Lcallret_tpl_fret_ra_redirect), ->a2
+	sdi a2, [sp, 8]
+	addi zero, 51, ->a0
+	# FRET.RA [ra ~ ra], sp!, 16
+	.4byte 0x04a52041
+.Lcallret_tpl_fret_ra_redirect:
+	C.BSTART.STD RET
+	addi zero, 68, ->a0
+	c.setc.tgt a1
+	C.BSTOP
+	.size callret_tpl_fret_ra_slot_redirect, .-callret_tpl_fret_ra_slot_redirect
+
+	.globl callret_tpl_ret_error_trailer_success
+	.type callret_tpl_ret_error_trailer_success,@function
+callret_tpl_ret_error_trailer_success:
+	C.BSTART.STD RET
+	C.BSTOP
+.Lcallret_tpl_ret_error_trailer_bad:
+	C.BSTART.STD RET
+	addi zero, 85, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_ret_error_trailer_success, .-callret_tpl_ret_error_trailer_success
+
+	.globl callret_tpl_cond_ret_error_trailer_taken
+	.type callret_tpl_cond_ret_error_trailer_taken,@function
+callret_tpl_cond_ret_error_trailer_taken:
+	C.BSTART COND, .Lcallret_tpl_cond_ret_error_jump
+	setc.eq zero, zero
+	C.BSTART.STD RET
+.Lcallret_tpl_cond_ret_error_jump:
+	j .Lcallret_tpl_cond_ret_error_handler
+	C.BSTOP
+.Lcallret_tpl_cond_ret_error_handler:
+	C.BSTART.STD RET
+	addi zero, 102, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_cond_ret_error_trailer_taken, .-callret_tpl_cond_ret_error_trailer_taken
+
+	.globl callret_tpl_c_bstart_cond_taken
+	.type callret_tpl_c_bstart_cond_taken,@function
+callret_tpl_c_bstart_cond_taken:
+	C.BSTART COND, .Lcallret_tpl_c_bstart_cond_taken_target
+	setc.eq zero, zero
+	C.BSTART.STD RET
+	addi zero, 225, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+.Lcallret_tpl_c_bstart_cond_taken_target:
+	C.BSTART.STD RET
+	addi zero, 102, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_c_bstart_cond_taken, .-callret_tpl_c_bstart_cond_taken
+
+	.globl callret_tpl_c_bstart_cond_not_taken
+	.type callret_tpl_c_bstart_cond_not_taken,@function
+callret_tpl_c_bstart_cond_not_taken:
+	C.BSTART COND, .Lcallret_tpl_c_bstart_cond_not_taken_target
+	setc.ne zero, zero
+	C.BSTART.STD RET
+	addi zero, 85, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+.Lcallret_tpl_c_bstart_cond_not_taken_target:
+	C.BSTART.STD RET
+	addi zero, 226, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_c_bstart_cond_not_taken, .-callret_tpl_c_bstart_cond_not_taken
+
+	.globl callret_tpl_j_skip_poison
+	.type callret_tpl_j_skip_poison,@function
+callret_tpl_j_skip_poison:
+	# FENTRY makes J the first instruction of the next translation block.
+	# Each observable path reaches its own frame-balanced FRET.STK return.
+	.4byte 0x04a50041
+	j .Lcallret_tpl_j_handler
+	addi zero, 85, ->a0
+	.4byte 0x04a53041
+.Lcallret_tpl_j_handler:
+	C.BSTART DIRECT, .Lcallret_tpl_j_handler_return
+	addi zero, 119, ->a0
+.Lcallret_tpl_j_handler_return:
+	.4byte 0x04a53041
+	.size callret_tpl_j_skip_poison, .-callret_tpl_j_skip_poison
+
+	.globl callret_tpl_l_bstart_direct_positive
+	.type callret_tpl_l_bstart_direct_positive,@function
+callret_tpl_l_bstart_direct_positive:
+	# Keep the target close: the canonical decoder treats this displacement as
+	# low25 halfwords, while the reversed decoder interprets it as high bits.
+	L.BSTART.STD DIRECT, .Lcallret_tpl_l_bstart_direct_positive_target
+	addi zero, 68, ->a0
+	C.BSTOP
+.Lcallret_tpl_l_bstart_direct_positive_fallthrough:
+	C.BSTART.STD RET
+	addi zero, 85, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+.Lcallret_tpl_l_bstart_direct_positive_target:
+	C.BSTART.STD RET
+	addi zero, 119, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_l_bstart_direct_positive, .-callret_tpl_l_bstart_direct_positive
+
+.Lcallret_tpl_l_bstart_direct_negative_target:
+	C.BSTART.STD RET
+	addi zero, 136, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+
+	.globl callret_tpl_l_bstart_direct_negative
+	.type callret_tpl_l_bstart_direct_negative,@function
+callret_tpl_l_bstart_direct_negative:
+	L.BSTART.STD DIRECT, .Lcallret_tpl_l_bstart_direct_negative_target
+	addi zero, 102, ->a0
+	C.BSTOP
+	C.BSTART.STD RET
+	addi zero, 153, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_l_bstart_direct_negative, .-callret_tpl_l_bstart_direct_negative
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/main.o
new file mode 100644
index 00000000..df984891
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diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/mem.o
new file mode 100644
index 00000000..5b1de528
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.json
new file mode 100644
index 00000000..4a926580
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.json
@@ -0,0 +1,335 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/linx-qemu-tests.elf",
+      "sha256": "593bcfe4fc758de208a1809aaafc111031e749d4d22cf068a4d221aa461483fb"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/linx-qemu-tests.o",
+      "sha256": "bbf8b0832965757c42a1ebbe5ad05d42ed9cbbe2f3f70cf45ac97212cd5e8667"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/main.o",
+        "sha256": "2cf79472fde78462f6ee15053dec319859bac80adaf3c0b15c8a23e85921788f"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/mem.o",
+        "sha256": "092fc93cc4ebb1e2a2922e5318f3cefa1b504c23d36a76808b269806f3caac25"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/14_callret.o",
+        "sha256": "03977adb96234a1cf30d7ba0fc32292fcc0e1cfae9943fd46f8a812bf90e0098"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/obj/14_callret_templates.o",
+        "sha256": "252edfe59e89b58502fd6bbfc93efe343a9b676edbe12af5c01ee0656babbb11"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log",
+      "sha256": "b50d01c9abe5e8bfd2f85e682830c65a0d9f6006889c115fa44f645d45ba630c"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.uart.log",
+      "sha256": "b4ae1246054b5101796a161644ee399e5329e44a83c74bbbd8ca7406a2d7ac99"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010fb4",
+      "0x0000000000010fca",
+      "0x0000000000010fee",
+      "0x0000000000010ffc",
+      "0x0000000000011022",
+      "0x000000000001105a",
+      "0x0000000000011070"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 8986,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010fb4"
+    },
+    {
+      "count": 8992,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010fca"
+    },
+    {
+      "count": 9740,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010fee"
+    },
+    {
+      "count": 10479,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010ffc"
+    },
+    {
+      "count": 11961,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000011022"
+    },
+    {
+      "count": 12717,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001105a"
+    },
+    {
+      "count": 13458,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000011070"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "002b4d206321f5ecaa40ef5064ba9756148bbcdc90ec349033f5897729654176",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-pto0571-evidence/qemu-system-linx64",
+    "sha": "583cad3f6ce68d05a559a354a3e7059844f47a5d",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1071-g583cad3f6c)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10fb4,0x10fca,0x10fee,0x10ffc,0x11022,0x1105a,0x11070",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00001401",
+    "0x00001402",
+    "0x00001403",
+    "0x00001404",
+    "0x00001405",
+    "0x00001406",
+    "0x00001407",
+    "0x00001408",
+    "0x00001409",
+    "0x0000140a",
+    "0x0000140b",
+    "0x0000140c",
+    "0x0000140d",
+    "0x0000140e",
+    "0x0000140f",
+    "0x00001410",
+    "0x00001411",
+    "0x00001412"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x00001412"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "b4ae1246054b5101796a161644ee399e5329e44a83c74bbbd8ca7406a2d7ac99",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "callret"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00001401"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00001401"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00001402"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00001402"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00001403"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00001403"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00001404"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00001404"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00001405"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00001405"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00001406"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00001406"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00001407"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00001407"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00001408"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00001408"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00001409"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00001409"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x0000140a"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x0000140a"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x0000140b"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x0000140b"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x0000140c"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x0000140c"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x0000140d"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x0000140d"
+    },
+    {
+      "kind": "START",
+      "seq": 26,
+      "test_id": "0x0000140e"
+    },
+    {
+      "kind": "PASS",
+      "seq": 27,
+      "test_id": "0x0000140e"
+    },
+    {
+      "kind": "START",
+      "seq": 28,
+      "test_id": "0x0000140f"
+    },
+    {
+      "kind": "PASS",
+      "seq": 29,
+      "test_id": "0x0000140f"
+    },
+    {
+      "kind": "START",
+      "seq": 30,
+      "test_id": "0x00001410"
+    },
+    {
+      "kind": "PASS",
+      "seq": 31,
+      "test_id": "0x00001410"
+    },
+    {
+      "kind": "START",
+      "seq": 32,
+      "test_id": "0x00001411"
+    },
+    {
+      "kind": "PASS",
+      "seq": 33,
+      "test_id": "0x00001411"
+    },
+    {
+      "kind": "START",
+      "seq": 34,
+      "test_id": "0x00001412"
+    },
+    {
+      "kind": "PASS",
+      "seq": 35,
+      "test_id": "0x00001412"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
new file mode 100644
index 00000000..79815649
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
@@ -0,0 +1,7 @@
+linx_pc_watch: pc=0x10fb4 hit=1 printed=1 count=8986 sp=0x7feff90 a0=0x0 a1=0x0 a2=0x49 ra=0x105a6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=4 tgt=0x10fb4 bpc=0x1059c tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=1 call_setret_pending=0
+linx_pc_watch: pc=0x10fca hit=1 printed=1 count=8992 sp=0x7feff80 a0=0x11 a1=0x105a6 a2=0x10fce ra=0x105a6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10fb4 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10fee hit=1 printed=1 count=9740 sp=0x7feff80 a0=0x33 a1=0x105f0 a2=0x10ff2 ra=0x105f0 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10fd8 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10ffc hit=1 printed=1 count=10479 sp=0x7feff90 a0=0x1234 a1=0x0 a2=0x33 ra=0x10640 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=4 tgt=0x10ffc bpc=0x10630 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=1 call_setret_pending=0
+linx_pc_watch: pc=0x11022 hit=1 printed=1 count=11961 sp=0x7feff90 a0=0x55 a1=0x0 a2=0x66 ra=0x106d4 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=4 tgt=0x11022 bpc=0x106c6 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=1 call_setret_pending=0
+linx_pc_watch: pc=0x1105a hit=1 printed=1 count=12717 sp=0x7feff80 a0=0x11 a1=0x0 a2=0x6655 ra=0x10730 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x11056 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x11070 hit=1 printed=1 count=13458 sp=0x7feff90 a0=0x11 a1=0x0 a2=0x77 ra=0x1077c tp=0x0 cstate=0x0 cond=0 carg=0 brtype=4 tgt=0x11070 bpc=0x10770 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=1 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.uart.log
new file mode 100644
index 00000000..a54d5fe8
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/callret-v057-583cad3f-20260731-r1/run-evidence.uart.log
@@ -0,0 +1,29 @@
+Linx QEMU tests
+  Test 0x00001401: PASS
+  Test 0x00001402: PASS
+  Test 0x00001403: PASS
+  Test 0x00001404: PASS
+  Test 0x00001405: PASS
+  Test 0x00001406: PASS
+  Test 0x00001407: PASS
+  Test 0x00001408: PASS
+  Test 0x00001409: PASS
+  Test 0x0000140A: PASS
+  Test 0x0000140B: PASS
+  Test 0x0000140C: PASS
+  Test 0x0000140D: PASS
+  Test 0x0000140E: PASS
+  Test 0x0000140F: PASS
+  Test 0x00001410: PASS
+  Test 0x00001411: PASS
+  Test 0x00001412: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf
new file mode 100755
index 00000000..b9443489
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o
new file mode 100644
index 00000000..1badf93e
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret.o b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret.o
new file mode 100644
index 00000000..a9d22eaa
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o
new file mode 100644
index 00000000..4d82a3c3
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.s b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.s
new file mode 100644
index 00000000..b4fdcbb9
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.s
@@ -0,0 +1,153 @@
+	.text
+
+	.globl callret_tpl_fret_stk_slot_redirect
+	.type callret_tpl_fret_stk_slot_redirect,@function
+callret_tpl_fret_stk_slot_redirect:
+	# FENTRY [ra ~ ra], sp!, 16
+	.4byte 0x04a50041
+	c.movr ra, ->a1
+	addtpc %tpcrel_hi(.Lcallret_tpl_fret_stk_redirect), ->a2
+	addi a2, %tpcrel_lo(.Lcallret_tpl_fret_stk_redirect), ->a2
+	sdi a2, [sp, 8]
+	addi zero, 17, ->a0
+	# FRET.STK [ra ~ ra], sp!, 16
+	.4byte 0x04a53041
+.Lcallret_tpl_fret_stk_redirect:
+	C.BSTART.STD RET
+	addi zero, 34, ->a0
+	c.setc.tgt a1
+	C.BSTOP
+	.size callret_tpl_fret_stk_slot_redirect, .-callret_tpl_fret_stk_slot_redirect
+
+	.globl callret_tpl_fret_ra_slot_redirect
+	.type callret_tpl_fret_ra_slot_redirect,@function
+callret_tpl_fret_ra_slot_redirect:
+	# FENTRY [ra ~ ra], sp!, 16
+	.4byte 0x04a50041
+	c.movr ra, ->a1
+	addtpc %tpcrel_hi(.Lcallret_tpl_fret_ra_redirect), ->a2
+	addi a2, %tpcrel_lo(.Lcallret_tpl_fret_ra_redirect), ->a2
+	sdi a2, [sp, 8]
+	addi zero, 51, ->a0
+	# FRET.RA [ra ~ ra], sp!, 16
+	.4byte 0x04a52041
+.Lcallret_tpl_fret_ra_redirect:
+	C.BSTART.STD RET
+	addi zero, 68, ->a0
+	c.setc.tgt a1
+	C.BSTOP
+	.size callret_tpl_fret_ra_slot_redirect, .-callret_tpl_fret_ra_slot_redirect
+
+	.globl callret_tpl_ret_error_trailer_success
+	.type callret_tpl_ret_error_trailer_success,@function
+callret_tpl_ret_error_trailer_success:
+	C.BSTART.STD RET
+	C.BSTOP
+.Lcallret_tpl_ret_error_trailer_bad:
+	C.BSTART.STD RET
+	addi zero, 85, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_ret_error_trailer_success, .-callret_tpl_ret_error_trailer_success
+
+	.globl callret_tpl_cond_ret_error_trailer_taken
+	.type callret_tpl_cond_ret_error_trailer_taken,@function
+callret_tpl_cond_ret_error_trailer_taken:
+	C.BSTART COND, .Lcallret_tpl_cond_ret_error_jump
+	setc.eq zero, zero
+	C.BSTART.STD RET
+.Lcallret_tpl_cond_ret_error_jump:
+	j .Lcallret_tpl_cond_ret_error_handler
+	C.BSTOP
+.Lcallret_tpl_cond_ret_error_handler:
+	C.BSTART.STD RET
+	addi zero, 102, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_cond_ret_error_trailer_taken, .-callret_tpl_cond_ret_error_trailer_taken
+
+	.globl callret_tpl_c_bstart_cond_taken
+	.type callret_tpl_c_bstart_cond_taken,@function
+callret_tpl_c_bstart_cond_taken:
+	C.BSTART COND, .Lcallret_tpl_c_bstart_cond_taken_target
+	setc.eq zero, zero
+	C.BSTART.STD RET
+	addi zero, 225, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+.Lcallret_tpl_c_bstart_cond_taken_target:
+	C.BSTART.STD RET
+	addi zero, 102, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_c_bstart_cond_taken, .-callret_tpl_c_bstart_cond_taken
+
+	.globl callret_tpl_c_bstart_cond_not_taken
+	.type callret_tpl_c_bstart_cond_not_taken,@function
+callret_tpl_c_bstart_cond_not_taken:
+	C.BSTART COND, .Lcallret_tpl_c_bstart_cond_not_taken_target
+	setc.ne zero, zero
+	C.BSTART.STD RET
+	addi zero, 85, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+.Lcallret_tpl_c_bstart_cond_not_taken_target:
+	C.BSTART.STD RET
+	addi zero, 226, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_c_bstart_cond_not_taken, .-callret_tpl_c_bstart_cond_not_taken
+
+	.globl callret_tpl_j_skip_poison
+	.type callret_tpl_j_skip_poison,@function
+callret_tpl_j_skip_poison:
+	# FENTRY makes J the first instruction of the next translation block.
+	# Each observable path reaches its own frame-balanced FRET.STK return.
+	.4byte 0x04a50041
+	j .Lcallret_tpl_j_handler
+	addi zero, 85, ->a0
+	.4byte 0x04a53041
+.Lcallret_tpl_j_handler:
+	C.BSTART DIRECT, .Lcallret_tpl_j_handler_return
+	addi zero, 119, ->a0
+.Lcallret_tpl_j_handler_return:
+	.4byte 0x04a53041
+	.size callret_tpl_j_skip_poison, .-callret_tpl_j_skip_poison
+
+	.globl callret_tpl_l_bstart_direct_positive
+	.type callret_tpl_l_bstart_direct_positive,@function
+callret_tpl_l_bstart_direct_positive:
+	# Keep the target close: the canonical decoder treats this displacement as
+	# low25 halfwords, while the reversed decoder interprets it as high bits.
+	L.BSTART.STD DIRECT, .Lcallret_tpl_l_bstart_direct_positive_target
+	addi zero, 68, ->a0
+	C.BSTOP
+.Lcallret_tpl_l_bstart_direct_positive_fallthrough:
+	C.BSTART.STD RET
+	addi zero, 85, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+.Lcallret_tpl_l_bstart_direct_positive_target:
+	C.BSTART.STD RET
+	addi zero, 119, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_l_bstart_direct_positive, .-callret_tpl_l_bstart_direct_positive
+
+.Lcallret_tpl_l_bstart_direct_negative_target:
+	C.BSTART.STD RET
+	addi zero, 136, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+
+	.globl callret_tpl_l_bstart_direct_negative
+	.type callret_tpl_l_bstart_direct_negative,@function
+callret_tpl_l_bstart_direct_negative:
+	L.BSTART.STD DIRECT, .Lcallret_tpl_l_bstart_direct_negative_target
+	addi zero, 102, ->a0
+	C.BSTOP
+	C.BSTART.STD RET
+	addi zero, 153, ->a0
+	c.setc.tgt ra
+	C.BSTOP
+	.size callret_tpl_l_bstart_direct_negative, .-callret_tpl_l_bstart_direct_negative
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/main.o
new file mode 100644
index 00000000..6b8c2844
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/mem.o
new file mode 100644
index 00000000..dd408f9e
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json
new file mode 100644
index 00000000..839f34ba
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json
@@ -0,0 +1,335 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "sha256": "dc6d2e11c1c1326557935540f2d866be97e552ebd657561d85c0ddd63d2b1483"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o",
+      "sha256": "19b33e96ad9520f9094f95b531681bb84de33fbf9353a782db0b81d3321acbca"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/main.o",
+        "sha256": "0c7fad60fda8205985bf05e5632d30db24d40b0d992bd9acd723c271887f274f"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/mem.o",
+        "sha256": "31048812dd2be1454c0ba009c2f8381c1ca3417ebd1413a058fc89184dadecec"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret.o",
+        "sha256": "01a77c4f1c102b7dd79759cb64b6f461a2486a06d16452cc5afc129d65285058"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
+        "sha256": "a152bf833aaafa70ffc7dccecd6c2d15574c103278bb14c142d58b26b4824a18"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log",
+      "sha256": "b50d01c9abe5e8bfd2f85e682830c65a0d9f6006889c115fa44f645d45ba630c"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.uart.log",
+      "sha256": "b4ae1246054b5101796a161644ee399e5329e44a83c74bbbd8ca7406a2d7ac99"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010fb4",
+      "0x0000000000010fca",
+      "0x0000000000010fee",
+      "0x0000000000010ffc",
+      "0x0000000000011022",
+      "0x000000000001105a",
+      "0x0000000000011070"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 8986,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010fb4"
+    },
+    {
+      "count": 8992,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010fca"
+    },
+    {
+      "count": 9740,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010fee"
+    },
+    {
+      "count": 10479,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010ffc"
+    },
+    {
+      "count": 11961,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000011022"
+    },
+    {
+      "count": 12717,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001105a"
+    },
+    {
+      "count": 13458,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000011070"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "c6176cc23eef482e5a64ee4f728a22fd44f35aac214a9d0c389fc8aa03ef0290",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-v0571-clean/qemu-system-linx64",
+    "sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1067-gcfc253e844)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10fb4,0x10fca,0x10fee,0x10ffc,0x11022,0x1105a,0x11070",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00001401",
+    "0x00001402",
+    "0x00001403",
+    "0x00001404",
+    "0x00001405",
+    "0x00001406",
+    "0x00001407",
+    "0x00001408",
+    "0x00001409",
+    "0x0000140a",
+    "0x0000140b",
+    "0x0000140c",
+    "0x0000140d",
+    "0x0000140e",
+    "0x0000140f",
+    "0x00001410",
+    "0x00001411",
+    "0x00001412"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x00001412"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "b4ae1246054b5101796a161644ee399e5329e44a83c74bbbd8ca7406a2d7ac99",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "callret"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00001401"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00001401"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00001402"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00001402"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00001403"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00001403"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00001404"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00001404"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00001405"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00001405"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00001406"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00001406"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00001407"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00001407"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00001408"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00001408"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00001409"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00001409"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x0000140a"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x0000140a"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x0000140b"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x0000140b"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x0000140c"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x0000140c"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x0000140d"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x0000140d"
+    },
+    {
+      "kind": "START",
+      "seq": 26,
+      "test_id": "0x0000140e"
+    },
+    {
+      "kind": "PASS",
+      "seq": 27,
+      "test_id": "0x0000140e"
+    },
+    {
+      "kind": "START",
+      "seq": 28,
+      "test_id": "0x0000140f"
+    },
+    {
+      "kind": "PASS",
+      "seq": 29,
+      "test_id": "0x0000140f"
+    },
+    {
+      "kind": "START",
+      "seq": 30,
+      "test_id": "0x00001410"
+    },
+    {
+      "kind": "PASS",
+      "seq": 31,
+      "test_id": "0x00001410"
+    },
+    {
+      "kind": "START",
+      "seq": 32,
+      "test_id": "0x00001411"
+    },
+    {
+      "kind": "PASS",
+      "seq": 33,
+      "test_id": "0x00001411"
+    },
+    {
+      "kind": "START",
+      "seq": 34,
+      "test_id": "0x00001412"
+    },
+    {
+      "kind": "PASS",
+      "seq": 35,
+      "test_id": "0x00001412"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
new file mode 100644
index 00000000..79815649
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
@@ -0,0 +1,7 @@
+linx_pc_watch: pc=0x10fb4 hit=1 printed=1 count=8986 sp=0x7feff90 a0=0x0 a1=0x0 a2=0x49 ra=0x105a6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=4 tgt=0x10fb4 bpc=0x1059c tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=1 call_setret_pending=0
+linx_pc_watch: pc=0x10fca hit=1 printed=1 count=8992 sp=0x7feff80 a0=0x11 a1=0x105a6 a2=0x10fce ra=0x105a6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10fb4 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10fee hit=1 printed=1 count=9740 sp=0x7feff80 a0=0x33 a1=0x105f0 a2=0x10ff2 ra=0x105f0 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10fd8 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10ffc hit=1 printed=1 count=10479 sp=0x7feff90 a0=0x1234 a1=0x0 a2=0x33 ra=0x10640 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=4 tgt=0x10ffc bpc=0x10630 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=1 call_setret_pending=0
+linx_pc_watch: pc=0x11022 hit=1 printed=1 count=11961 sp=0x7feff90 a0=0x55 a1=0x0 a2=0x66 ra=0x106d4 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=4 tgt=0x11022 bpc=0x106c6 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=1 call_setret_pending=0
+linx_pc_watch: pc=0x1105a hit=1 printed=1 count=12717 sp=0x7feff80 a0=0x11 a1=0x0 a2=0x6655 ra=0x10730 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x11056 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x11070 hit=1 printed=1 count=13458 sp=0x7feff90 a0=0x11 a1=0x0 a2=0x77 ra=0x1077c tp=0x0 cstate=0x0 cond=0 carg=0 brtype=4 tgt=0x11070 bpc=0x10770 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=1 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
new file mode 100644
index 00000000..a54d5fe8
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
@@ -0,0 +1,29 @@
+Linx QEMU tests
+  Test 0x00001401: PASS
+  Test 0x00001402: PASS
+  Test 0x00001403: PASS
+  Test 0x00001404: PASS
+  Test 0x00001405: PASS
+  Test 0x00001406: PASS
+  Test 0x00001407: PASS
+  Test 0x00001408: PASS
+  Test 0x00001409: PASS
+  Test 0x0000140A: PASS
+  Test 0x0000140B: PASS
+  Test 0x0000140C: PASS
+  Test 0x0000140D: PASS
+  Test 0x0000140E: PASS
+  Test 0x0000140F: PASS
+  Test 0x00001410: PASS
+  Test 0x00001411: PASS
+  Test 0x00001412: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/linx-qemu-tests.elf
new file mode 100755
index 00000000..b26ac940
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/linx-qemu-tests.o
new file mode 100644
index 00000000..74a392dd
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/24_executable_integer.o b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/24_executable_integer.o
new file mode 100644
index 00000000..a9b2613c
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/24_executable_integer.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/main.o
new file mode 100644
index 00000000..9b0af5ca
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/mem.o
new file mode 100644
index 00000000..5b1de528
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.json
new file mode 100644
index 00000000..a77a8c8b
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.json
@@ -0,0 +1,354 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/linx-qemu-tests.elf",
+      "sha256": "40a5574ee7471ca61282c18df23232959217ee2da055cd0893f5669f377bd67f"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/linx-qemu-tests.o",
+      "sha256": "e25946fe6a8a807fab1eff4cd8f330582579cee40749c8c68a0dc3ff16bf73c0"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/main.o",
+        "sha256": "87bdb227c8193a18a23bb1dcde346d657882dc337ac610ae482c8161a8f5090d"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/mem.o",
+        "sha256": "092fc93cc4ebb1e2a2922e5318f3cefa1b504c23d36a76808b269806f3caac25"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/obj/24_executable_integer.o",
+        "sha256": "e9e007e18c81cff3d77cd32f9604f0008597bc1dc1fbe4fa374975a0185b42a3"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log",
+      "sha256": "28c81e55ca08a4459eb2b6e5960d6a3523ba7325bb6ef5724c6e22f4050e8d03"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.uart.log",
+      "sha256": "187b6f5cc1b31d5604e460ae59e56ef7e9f4164f3385713c1eccb3741d1bb354"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010284",
+      "0x000000000001029c",
+      "0x00000000000102b4",
+      "0x00000000000102c6",
+      "0x00000000000102da",
+      "0x00000000000102ee",
+      "0x0000000000010302",
+      "0x0000000000010316",
+      "0x000000000001033e",
+      "0x000000000001037e",
+      "0x0000000000010390",
+      "0x00000000000103a2",
+      "0x00000000000103b4",
+      "0x00000000000103c6",
+      "0x000000000001040a"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 1095,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010284"
+    },
+    {
+      "count": 1854,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001029c"
+    },
+    {
+      "count": 2617,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102b4"
+    },
+    {
+      "count": 3374,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102c6"
+    },
+    {
+      "count": 4132,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102da"
+    },
+    {
+      "count": 4897,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102ee"
+    },
+    {
+      "count": 5654,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010302"
+    },
+    {
+      "count": 6412,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010316"
+    },
+    {
+      "count": 7174,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001033e"
+    },
+    {
+      "count": 7941,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001037e"
+    },
+    {
+      "count": 8699,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010390"
+    },
+    {
+      "count": 9457,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103a2"
+    },
+    {
+      "count": 10215,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103b4"
+    },
+    {
+      "count": 10973,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103c6"
+    },
+    {
+      "count": 11749,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001040a"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "002b4d206321f5ecaa40ef5064ba9756148bbcdc90ec349033f5897729654176",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-pto0571-evidence/qemu-system-linx64",
+    "sha": "583cad3f6ce68d05a559a354a3e7059844f47a5d",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1071-g583cad3f6c)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10284,0x1029c,0x102b4,0x102c6,0x102da,0x102ee,0x10302,0x10316,0x1033e,0x1037e,0x10390,0x103a2,0x103b4,0x103c6,0x1040a",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00002601",
+    "0x00002602",
+    "0x00002603",
+    "0x00002604",
+    "0x00002605",
+    "0x00002606",
+    "0x00002607",
+    "0x00002608",
+    "0x00002609",
+    "0x0000260a",
+    "0x0000260b",
+    "0x0000260c",
+    "0x0000260d",
+    "0x0000260e",
+    "0x0000260f"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x0000260f"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "187b6f5cc1b31d5604e460ae59e56ef7e9f4164f3385713c1eccb3741d1bb354",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "executable_integer"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00002601"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00002601"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00002602"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00002602"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00002603"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00002603"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00002604"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00002604"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00002605"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00002605"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00002606"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00002606"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00002607"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00002607"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00002608"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00002608"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00002609"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00002609"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x0000260a"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x0000260a"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x0000260b"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x0000260b"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x0000260c"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x0000260c"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x0000260d"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x0000260d"
+    },
+    {
+      "kind": "START",
+      "seq": 26,
+      "test_id": "0x0000260e"
+    },
+    {
+      "kind": "PASS",
+      "seq": 27,
+      "test_id": "0x0000260e"
+    },
+    {
+      "kind": "START",
+      "seq": 28,
+      "test_id": "0x0000260f"
+    },
+    {
+      "kind": "PASS",
+      "seq": 29,
+      "test_id": "0x0000260f"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
new file mode 100644
index 00000000..11fe9c97
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
@@ -0,0 +1,15 @@
+linx_pc_watch: pc=0x10284 hit=1 printed=1 count=1095 sp=0x7feffa8 a0=0x0 a1=0x10f18 a2=0x1 ra=0x106e2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10278 tq0=0x10000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1029c hit=1 printed=1 count=1854 sp=0x7feffa8 a0=0x0 a1=0x10f18 a2=0x2 ra=0x1074a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10290 tq0=0x10000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102b4 hit=1 printed=1 count=2617 sp=0x7feff98 a0=0x89abcdef00000000 a1=0x10f18 a2=0x4 ra=0x10790 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102a8 tq0=0x10000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102c6 hit=1 printed=1 count=3374 sp=0x7feffa8 a0=0x0 a1=0xfffffffffffffff9 a2=0xd ra=0x107c6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102c0 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102da hit=1 printed=1 count=4132 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffff9c a2=0x7 ra=0x107f6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102d2 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102ee hit=1 printed=1 count=4897 sp=0x7feff98 a0=0xfffffff00000000 a1=0xfffffffffffffff0 a2=0x10 ra=0x10842 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102e6 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10302 hit=1 printed=1 count=5654 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffff9c a2=0x7 ra=0x10886 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102fa tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10316 hit=1 printed=1 count=6412 sp=0x7feffa8 a0=0x0 a1=0x64 a2=0x7 ra=0x108b2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1030e tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1033e hit=1 printed=1 count=7174 sp=0x7feffa8 a0=0x0 a1=0x123456789abcdef0 a2=0x2 ra=0x108de tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10322 tq0=0x9abcdef0 tq1=0xffffffff9abcdef0 uq0=0x1234567800000000 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1037e hit=1 printed=1 count=7941 sp=0x7feffa8 a0=0x0 a1=0x123456789abcdef1 a2=0x1 ra=0x1090a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1034a tq0=0x9abcdef0 tq1=0x9abcdef000000000 uq0=0x1234567800000000 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10390 hit=1 printed=1 count=8699 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffffff a2=0x1 ra=0x10936 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1038a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103a2 hit=1 printed=1 count=9457 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffffff a2=0x1 ra=0x10962 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1039c tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103b4 hit=1 printed=1 count=10215 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffffff a2=0x1 ra=0x1098e tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103ae tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103c6 hit=1 printed=1 count=10973 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffffff a2=0x1 ra=0x109ba tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103c0 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1040a hit=1 printed=1 count=11749 sp=0x7feff88 a0=0x1 a1=0xccccdddd a2=0x1111222233334444 ra=0x10a08 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103d2 tq0=0xccccdddd tq1=0xffffffffccccdddd uq0=0xaaaabbbb00000000 uq1=0x1111222200000000 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.uart.log
new file mode 100644
index 00000000..a3dd86dd
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v057-583cad3f-20260731-r1/run-evidence.uart.log
@@ -0,0 +1,26 @@
+Linx QEMU tests
+  Test 0x00002601: PASS
+  Test 0x00002602: PASS
+  Test 0x00002603: PASS
+  Test 0x00002604: PASS
+  Test 0x00002605: PASS
+  Test 0x00002606: PASS
+  Test 0x00002607: PASS
+  Test 0x00002608: PASS
+  Test 0x00002609: PASS
+  Test 0x0000260A: PASS
+  Test 0x0000260B: PASS
+  Test 0x0000260C: PASS
+  Test 0x0000260D: PASS
+  Test 0x0000260E: PASS
+  Test 0x0000260F: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf
new file mode 100755
index 00000000..e350c202
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o
new file mode 100644
index 00000000..6779b638
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o
new file mode 100644
index 00000000..c9d3d3d1
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/main.o
new file mode 100644
index 00000000..e106dc06
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/mem.o
new file mode 100644
index 00000000..dd408f9e
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json
new file mode 100644
index 00000000..ae762888
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json
@@ -0,0 +1,354 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o",
+      "sha256": "2b4f295bd758f9028ecaef4664f9353f061230b2d87d680d29b68509a6ac119c"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/main.o",
+        "sha256": "052f6824808a1631579bf6eccbf8ef11519c842654bc896d66d4c2ccb2b30837"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/mem.o",
+        "sha256": "31048812dd2be1454c0ba009c2f8381c1ca3417ebd1413a058fc89184dadecec"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+        "sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log",
+      "sha256": "28c81e55ca08a4459eb2b6e5960d6a3523ba7325bb6ef5724c6e22f4050e8d03"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.uart.log",
+      "sha256": "187b6f5cc1b31d5604e460ae59e56ef7e9f4164f3385713c1eccb3741d1bb354"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010284",
+      "0x000000000001029c",
+      "0x00000000000102b4",
+      "0x00000000000102c6",
+      "0x00000000000102da",
+      "0x00000000000102ee",
+      "0x0000000000010302",
+      "0x0000000000010316",
+      "0x000000000001033e",
+      "0x000000000001037e",
+      "0x0000000000010390",
+      "0x00000000000103a2",
+      "0x00000000000103b4",
+      "0x00000000000103c6",
+      "0x000000000001040a"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 1095,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010284"
+    },
+    {
+      "count": 1854,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001029c"
+    },
+    {
+      "count": 2617,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102b4"
+    },
+    {
+      "count": 3374,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102c6"
+    },
+    {
+      "count": 4132,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102da"
+    },
+    {
+      "count": 4897,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102ee"
+    },
+    {
+      "count": 5654,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010302"
+    },
+    {
+      "count": 6412,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010316"
+    },
+    {
+      "count": 7174,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001033e"
+    },
+    {
+      "count": 7941,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001037e"
+    },
+    {
+      "count": 8699,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010390"
+    },
+    {
+      "count": 9457,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103a2"
+    },
+    {
+      "count": 10215,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103b4"
+    },
+    {
+      "count": 10973,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103c6"
+    },
+    {
+      "count": 11749,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001040a"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "c6176cc23eef482e5a64ee4f728a22fd44f35aac214a9d0c389fc8aa03ef0290",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-v0571-clean/qemu-system-linx64",
+    "sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1067-gcfc253e844)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10284,0x1029c,0x102b4,0x102c6,0x102da,0x102ee,0x10302,0x10316,0x1033e,0x1037e,0x10390,0x103a2,0x103b4,0x103c6,0x1040a",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00002601",
+    "0x00002602",
+    "0x00002603",
+    "0x00002604",
+    "0x00002605",
+    "0x00002606",
+    "0x00002607",
+    "0x00002608",
+    "0x00002609",
+    "0x0000260a",
+    "0x0000260b",
+    "0x0000260c",
+    "0x0000260d",
+    "0x0000260e",
+    "0x0000260f"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x0000260f"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "187b6f5cc1b31d5604e460ae59e56ef7e9f4164f3385713c1eccb3741d1bb354",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "executable_integer"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00002601"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00002601"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00002602"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00002602"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00002603"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00002603"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00002604"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00002604"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00002605"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00002605"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00002606"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00002606"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00002607"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00002607"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00002608"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00002608"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00002609"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00002609"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x0000260a"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x0000260a"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x0000260b"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x0000260b"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x0000260c"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x0000260c"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x0000260d"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x0000260d"
+    },
+    {
+      "kind": "START",
+      "seq": 26,
+      "test_id": "0x0000260e"
+    },
+    {
+      "kind": "PASS",
+      "seq": 27,
+      "test_id": "0x0000260e"
+    },
+    {
+      "kind": "START",
+      "seq": 28,
+      "test_id": "0x0000260f"
+    },
+    {
+      "kind": "PASS",
+      "seq": 29,
+      "test_id": "0x0000260f"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
new file mode 100644
index 00000000..11fe9c97
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
@@ -0,0 +1,15 @@
+linx_pc_watch: pc=0x10284 hit=1 printed=1 count=1095 sp=0x7feffa8 a0=0x0 a1=0x10f18 a2=0x1 ra=0x106e2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10278 tq0=0x10000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1029c hit=1 printed=1 count=1854 sp=0x7feffa8 a0=0x0 a1=0x10f18 a2=0x2 ra=0x1074a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10290 tq0=0x10000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102b4 hit=1 printed=1 count=2617 sp=0x7feff98 a0=0x89abcdef00000000 a1=0x10f18 a2=0x4 ra=0x10790 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102a8 tq0=0x10000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102c6 hit=1 printed=1 count=3374 sp=0x7feffa8 a0=0x0 a1=0xfffffffffffffff9 a2=0xd ra=0x107c6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102c0 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102da hit=1 printed=1 count=4132 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffff9c a2=0x7 ra=0x107f6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102d2 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102ee hit=1 printed=1 count=4897 sp=0x7feff98 a0=0xfffffff00000000 a1=0xfffffffffffffff0 a2=0x10 ra=0x10842 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102e6 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10302 hit=1 printed=1 count=5654 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffff9c a2=0x7 ra=0x10886 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102fa tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10316 hit=1 printed=1 count=6412 sp=0x7feffa8 a0=0x0 a1=0x64 a2=0x7 ra=0x108b2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1030e tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1033e hit=1 printed=1 count=7174 sp=0x7feffa8 a0=0x0 a1=0x123456789abcdef0 a2=0x2 ra=0x108de tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10322 tq0=0x9abcdef0 tq1=0xffffffff9abcdef0 uq0=0x1234567800000000 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1037e hit=1 printed=1 count=7941 sp=0x7feffa8 a0=0x0 a1=0x123456789abcdef1 a2=0x1 ra=0x1090a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1034a tq0=0x9abcdef0 tq1=0x9abcdef000000000 uq0=0x1234567800000000 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10390 hit=1 printed=1 count=8699 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffffff a2=0x1 ra=0x10936 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1038a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103a2 hit=1 printed=1 count=9457 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffffff a2=0x1 ra=0x10962 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1039c tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103b4 hit=1 printed=1 count=10215 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffffff a2=0x1 ra=0x1098e tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103ae tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103c6 hit=1 printed=1 count=10973 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffffff a2=0x1 ra=0x109ba tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103c0 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1040a hit=1 printed=1 count=11749 sp=0x7feff88 a0=0x1 a1=0xccccdddd a2=0x1111222233334444 ra=0x10a08 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103d2 tq0=0xccccdddd tq1=0xffffffffccccdddd uq0=0xaaaabbbb00000000 uq1=0x1111222200000000 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
new file mode 100644
index 00000000..a3dd86dd
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
@@ -0,0 +1,26 @@
+Linx QEMU tests
+  Test 0x00002601: PASS
+  Test 0x00002602: PASS
+  Test 0x00002603: PASS
+  Test 0x00002604: PASS
+  Test 0x00002605: PASS
+  Test 0x00002606: PASS
+  Test 0x00002607: PASS
+  Test 0x00002608: PASS
+  Test 0x00002609: PASS
+  Test 0x0000260A: PASS
+  Test 0x0000260B: PASS
+  Test 0x0000260C: PASS
+  Test 0x0000260D: PASS
+  Test 0x0000260E: PASS
+  Test 0x0000260F: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/linx-qemu-tests.elf
new file mode 100755
index 00000000..747b0aec
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/linx-qemu-tests.o
new file mode 100644
index 00000000..9cdb948f
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/22_executable_memory.o b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/22_executable_memory.o
new file mode 100644
index 00000000..8d6b7e2b
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/22_executable_memory.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/main.o
new file mode 100644
index 00000000..55c9a717
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/mem.o
new file mode 100644
index 00000000..5b1de528
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.json
new file mode 100644
index 00000000..fe5335ee
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.json
@@ -0,0 +1,318 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/linx-qemu-tests.elf",
+      "sha256": "0412c838be0720142078356d755e53afaef536c591805a7e8a253a33fc66277b"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/linx-qemu-tests.o",
+      "sha256": "d84261d70c784407027001991de41f9e7e573d1dfb0a9a1ec06cf08fd2202013"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/main.o",
+        "sha256": "4e4f0697c2e0f5500f67b633ba6e145b0124d02fbe10c728271ed509bb0b5888"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/mem.o",
+        "sha256": "092fc93cc4ebb1e2a2922e5318f3cefa1b504c23d36a76808b269806f3caac25"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/obj/22_executable_memory.o",
+        "sha256": "46af90f8487c8d97b7d671b6532c7c4bf244bc754ca20fc8661c8ab6f22c32e4"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log",
+      "sha256": "3390b90d2548d864452cfc7ceb5f1c247a24445df9a73d5c3709919655cb31ae"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.uart.log",
+      "sha256": "1c0462ed4c01ba6eec649b898acf5bff2430a4b8507828e9857987692462ea21"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010282",
+      "0x00000000000102bc",
+      "0x0000000000010302",
+      "0x000000000001033c",
+      "0x00000000000103a2",
+      "0x00000000000103f2",
+      "0x0000000000010442",
+      "0x000000000001049e",
+      "0x00000000000104ec",
+      "0x0000000000010544",
+      "0x00000000000105a6",
+      "0x0000000000010600",
+      "0x000000000001068a"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 1083,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010282"
+    },
+    {
+      "count": 1836,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102bc"
+    },
+    {
+      "count": 2589,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010302"
+    },
+    {
+      "count": 3339,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001033c"
+    },
+    {
+      "count": 4099,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103a2"
+    },
+    {
+      "count": 4854,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103f2"
+    },
+    {
+      "count": 5609,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010442"
+    },
+    {
+      "count": 6367,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001049e"
+    },
+    {
+      "count": 7122,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000104ec"
+    },
+    {
+      "count": 7878,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010544"
+    },
+    {
+      "count": 8637,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000105a6"
+    },
+    {
+      "count": 9395,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010600"
+    },
+    {
+      "count": 10163,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001068a"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "002b4d206321f5ecaa40ef5064ba9756148bbcdc90ec349033f5897729654176",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-pto0571-evidence/qemu-system-linx64",
+    "sha": "583cad3f6ce68d05a559a354a3e7059844f47a5d",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1071-g583cad3f6c)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10282,0x102bc,0x10302,0x1033c,0x103a2,0x103f2,0x10442,0x1049e,0x104ec,0x10544,0x105a6,0x10600,0x1068a",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00002201",
+    "0x00002202",
+    "0x00002203",
+    "0x00002204",
+    "0x00002205",
+    "0x00002206",
+    "0x00002207",
+    "0x00002208",
+    "0x00002209",
+    "0x0000220a",
+    "0x0000220b",
+    "0x0000220c",
+    "0x0000220d"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x0000220d"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "1c0462ed4c01ba6eec649b898acf5bff2430a4b8507828e9857987692462ea21",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "executable_memory"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00002201"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00002201"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00002202"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00002202"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00002203"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00002203"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00002204"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00002204"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00002205"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00002205"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00002206"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00002206"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00002207"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00002207"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00002208"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00002208"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00002209"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00002209"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x0000220a"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x0000220a"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x0000220b"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x0000220b"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x0000220c"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x0000220c"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x0000220d"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x0000220d"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
new file mode 100644
index 00000000..1300350b
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
@@ -0,0 +1,13 @@
+linx_pc_watch: pc=0x10282 hit=1 printed=1 count=1083 sp=0x7feff98 a0=0x110c0 a1=0x0 a2=0x0 ra=0x106ca tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10278 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102bc hit=1 printed=1 count=1836 sp=0x7feff98 a0=0x110c0 a1=0x0 a2=0x0 ra=0x10716 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102b2 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10302 hit=1 printed=1 count=2589 sp=0x7feff98 a0=0x110c0 a1=0x0 a2=0x0 ra=0x1075a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102f8 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1033c hit=1 printed=1 count=3339 sp=0x7feff98 a0=0x110c0 a1=0x0 a2=0x0 ra=0x1079e tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10332 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103a2 hit=1 printed=1 count=4099 sp=0x7feff98 a0=0xaabbccdd a1=0x0 a2=0x12000 ra=0x107e2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10378 tq0=0x12000 tq1=0xaabbccdd00000000 uq0=0xffffffffaabbccdd uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103f2 hit=1 printed=1 count=4854 sp=0x7feff98 a0=0x12000 a1=0x11223344 a2=0x12000 ra=0x10826 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103d4 tq0=0x12000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10442 hit=1 printed=1 count=5609 sp=0x7feff98 a0=0x12000 a1=0x55667788 a2=0x12004 ra=0x1086a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10424 tq0=0x12000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1049e hit=1 printed=1 count=6367 sp=0x7feff98 a0=0x99aabbcc a1=0x0 a2=0x12000 ra=0x108ae tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10474 tq0=0x12000 tq1=0x99aabbcc00000000 uq0=0xffffffff99aabbcc uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x104ec hit=1 printed=1 count=7122 sp=0x7feff98 a0=0x0 a1=0x110c0 a2=0x12000 ra=0x108f2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x104d0 tq0=0x11000 tq1=0x9abcdef000000000 uq0=0x9abcdef0 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10544 hit=1 printed=1 count=7878 sp=0x7feff98 a0=0xa0b0c0d0 a1=0x0 a2=0x12000 ra=0x10936 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10514 tq0=0x12000 tq1=0xa0b0c0d000000000 uq0=0xffffffffa0b0c0d0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x105a6 hit=1 printed=1 count=8637 sp=0x7feff98 a0=0xeeff0011 a1=0x0 a2=0x12000 ra=0x1097a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10576 tq0=0x12000 tq1=0xeeff001100000000 uq0=0xffffffffeeff0011 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10600 hit=1 printed=1 count=9395 sp=0x7feff98 a0=0x20 a1=0x0 a2=0x110c8 ra=0x109be tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x105d8 tq0=0x11000 tq1=0xdeadbeefcafebabe uq0=0xdeadbeef00000000 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1068a hit=1 printed=1 count=10163 sp=0x7feff98 a0=0x1122334455667788 a1=0x8877665544332211 a2=0x0 ra=0x10a02 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1063c tq0=0x12000 tq1=0x55667788 uq0=0x1122334400000000 uq1=0x44332211 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.uart.log
new file mode 100644
index 00000000..9f552233
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v057-583cad3f-20260731-r1/run-evidence.uart.log
@@ -0,0 +1,24 @@
+Linx QEMU tests
+  Test 0x00002201: PASS
+  Test 0x00002202: PASS
+  Test 0x00002203: PASS
+  Test 0x00002204: PASS
+  Test 0x00002205: PASS
+  Test 0x00002206: PASS
+  Test 0x00002207: PASS
+  Test 0x00002208: PASS
+  Test 0x00002209: PASS
+  Test 0x0000220A: PASS
+  Test 0x0000220B: PASS
+  Test 0x0000220C: PASS
+  Test 0x0000220D: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf
new file mode 100755
index 00000000..ef61d569
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o
new file mode 100644
index 00000000..4f7fd881
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o
new file mode 100644
index 00000000..907da6ec
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/main.o
new file mode 100644
index 00000000..666f329e
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/mem.o
new file mode 100644
index 00000000..dd408f9e
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json
new file mode 100644
index 00000000..53cb3899
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json
@@ -0,0 +1,318 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o",
+      "sha256": "df6444f9fb527554f52c3c03b35f033051a17ade83ce571f10d600a853c6d940"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/main.o",
+        "sha256": "fbfdd5d2a51bbdb23288ddc73fb8b6b4445d79964b748dfe30c65600b1ffddde"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/mem.o",
+        "sha256": "31048812dd2be1454c0ba009c2f8381c1ca3417ebd1413a058fc89184dadecec"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+        "sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log",
+      "sha256": "3390b90d2548d864452cfc7ceb5f1c247a24445df9a73d5c3709919655cb31ae"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.uart.log",
+      "sha256": "1c0462ed4c01ba6eec649b898acf5bff2430a4b8507828e9857987692462ea21"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010282",
+      "0x00000000000102bc",
+      "0x0000000000010302",
+      "0x000000000001033c",
+      "0x00000000000103a2",
+      "0x00000000000103f2",
+      "0x0000000000010442",
+      "0x000000000001049e",
+      "0x00000000000104ec",
+      "0x0000000000010544",
+      "0x00000000000105a6",
+      "0x0000000000010600",
+      "0x000000000001068a"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 1083,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010282"
+    },
+    {
+      "count": 1836,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102bc"
+    },
+    {
+      "count": 2589,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010302"
+    },
+    {
+      "count": 3339,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001033c"
+    },
+    {
+      "count": 4099,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103a2"
+    },
+    {
+      "count": 4854,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103f2"
+    },
+    {
+      "count": 5609,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010442"
+    },
+    {
+      "count": 6367,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001049e"
+    },
+    {
+      "count": 7122,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000104ec"
+    },
+    {
+      "count": 7878,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010544"
+    },
+    {
+      "count": 8637,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000105a6"
+    },
+    {
+      "count": 9395,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010600"
+    },
+    {
+      "count": 10163,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001068a"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "c6176cc23eef482e5a64ee4f728a22fd44f35aac214a9d0c389fc8aa03ef0290",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-v0571-clean/qemu-system-linx64",
+    "sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1067-gcfc253e844)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10282,0x102bc,0x10302,0x1033c,0x103a2,0x103f2,0x10442,0x1049e,0x104ec,0x10544,0x105a6,0x10600,0x1068a",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00002201",
+    "0x00002202",
+    "0x00002203",
+    "0x00002204",
+    "0x00002205",
+    "0x00002206",
+    "0x00002207",
+    "0x00002208",
+    "0x00002209",
+    "0x0000220a",
+    "0x0000220b",
+    "0x0000220c",
+    "0x0000220d"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x0000220d"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "1c0462ed4c01ba6eec649b898acf5bff2430a4b8507828e9857987692462ea21",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "executable_memory"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00002201"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00002201"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00002202"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00002202"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00002203"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00002203"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00002204"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00002204"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00002205"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00002205"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00002206"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00002206"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00002207"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00002207"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00002208"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00002208"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00002209"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00002209"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x0000220a"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x0000220a"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x0000220b"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x0000220b"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x0000220c"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x0000220c"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x0000220d"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x0000220d"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
new file mode 100644
index 00000000..1300350b
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
@@ -0,0 +1,13 @@
+linx_pc_watch: pc=0x10282 hit=1 printed=1 count=1083 sp=0x7feff98 a0=0x110c0 a1=0x0 a2=0x0 ra=0x106ca tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10278 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102bc hit=1 printed=1 count=1836 sp=0x7feff98 a0=0x110c0 a1=0x0 a2=0x0 ra=0x10716 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102b2 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10302 hit=1 printed=1 count=2589 sp=0x7feff98 a0=0x110c0 a1=0x0 a2=0x0 ra=0x1075a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102f8 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1033c hit=1 printed=1 count=3339 sp=0x7feff98 a0=0x110c0 a1=0x0 a2=0x0 ra=0x1079e tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10332 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103a2 hit=1 printed=1 count=4099 sp=0x7feff98 a0=0xaabbccdd a1=0x0 a2=0x12000 ra=0x107e2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10378 tq0=0x12000 tq1=0xaabbccdd00000000 uq0=0xffffffffaabbccdd uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103f2 hit=1 printed=1 count=4854 sp=0x7feff98 a0=0x12000 a1=0x11223344 a2=0x12000 ra=0x10826 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103d4 tq0=0x12000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10442 hit=1 printed=1 count=5609 sp=0x7feff98 a0=0x12000 a1=0x55667788 a2=0x12004 ra=0x1086a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10424 tq0=0x12000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1049e hit=1 printed=1 count=6367 sp=0x7feff98 a0=0x99aabbcc a1=0x0 a2=0x12000 ra=0x108ae tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10474 tq0=0x12000 tq1=0x99aabbcc00000000 uq0=0xffffffff99aabbcc uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x104ec hit=1 printed=1 count=7122 sp=0x7feff98 a0=0x0 a1=0x110c0 a2=0x12000 ra=0x108f2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x104d0 tq0=0x11000 tq1=0x9abcdef000000000 uq0=0x9abcdef0 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10544 hit=1 printed=1 count=7878 sp=0x7feff98 a0=0xa0b0c0d0 a1=0x0 a2=0x12000 ra=0x10936 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10514 tq0=0x12000 tq1=0xa0b0c0d000000000 uq0=0xffffffffa0b0c0d0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x105a6 hit=1 printed=1 count=8637 sp=0x7feff98 a0=0xeeff0011 a1=0x0 a2=0x12000 ra=0x1097a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10576 tq0=0x12000 tq1=0xeeff001100000000 uq0=0xffffffffeeff0011 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10600 hit=1 printed=1 count=9395 sp=0x7feff98 a0=0x20 a1=0x0 a2=0x110c8 ra=0x109be tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x105d8 tq0=0x11000 tq1=0xdeadbeefcafebabe uq0=0xdeadbeef00000000 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1068a hit=1 printed=1 count=10163 sp=0x7feff98 a0=0x1122334455667788 a1=0x8877665544332211 a2=0x0 ra=0x10a02 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1063c tq0=0x12000 tq1=0x55667788 uq0=0x1122334400000000 uq1=0x44332211 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
new file mode 100644
index 00000000..9f552233
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
@@ -0,0 +1,24 @@
+Linx QEMU tests
+  Test 0x00002201: PASS
+  Test 0x00002202: PASS
+  Test 0x00002203: PASS
+  Test 0x00002204: PASS
+  Test 0x00002205: PASS
+  Test 0x00002206: PASS
+  Test 0x00002207: PASS
+  Test 0x00002208: PASS
+  Test 0x00002209: PASS
+  Test 0x0000220A: PASS
+  Test 0x0000220B: PASS
+  Test 0x0000220C: PASS
+  Test 0x0000220D: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/linx-qemu-tests.elf
new file mode 100755
index 00000000..9eea8a55
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/linx-qemu-tests.o
new file mode 100644
index 00000000..883679f9
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/23_executable_scalar.o b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/23_executable_scalar.o
new file mode 100644
index 00000000..6e0fe001
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/23_executable_scalar.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/main.o
new file mode 100644
index 00000000..63df70a2
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/mem.o
new file mode 100644
index 00000000..5b1de528
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.json
new file mode 100644
index 00000000..53ee7e74
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.json
@@ -0,0 +1,372 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/linx-qemu-tests.elf",
+      "sha256": "f013d036456a4acc8f1665348fc1cccf42e13aa0663c7f326becbdc144483eb6"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/linx-qemu-tests.o",
+      "sha256": "d0405384214cebde34ebca3e98423151955b0b10cfc1b87136d2285a5a1f93f8"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/main.o",
+        "sha256": "36fb8b955c32f6f52fd559eb7d2ded95c3f23a78b9b34e766d72fdc616a0e30d"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/mem.o",
+        "sha256": "092fc93cc4ebb1e2a2922e5318f3cefa1b504c23d36a76808b269806f3caac25"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/obj/23_executable_scalar.o",
+        "sha256": "ad67a32962cc8881e651e1e36f82d9c45b972b116259340809a8bcb21220f10c"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log",
+      "sha256": "f11a4c7a59ee2d26191c6823ba0998a0b86d00ef763964c7383624ae42d32c95"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.uart.log",
+      "sha256": "82956cbbe2780222691b0024a8a9672a9ab5e8aead35d99a346f2531ab47790b"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010286",
+      "0x00000000000102a0",
+      "0x00000000000102b8",
+      "0x00000000000102d0",
+      "0x00000000000102e8",
+      "0x00000000000102fe",
+      "0x0000000000010330",
+      "0x0000000000010346",
+      "0x000000000001035e",
+      "0x0000000000010376",
+      "0x000000000001038e",
+      "0x00000000000103a6",
+      "0x00000000000103de",
+      "0x0000000000010456",
+      "0x00000000000104e8",
+      "0x0000000000010574"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 1094,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010286"
+    },
+    {
+      "count": 1852,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102a0"
+    },
+    {
+      "count": 2610,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102b8"
+    },
+    {
+      "count": 3368,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102d0"
+    },
+    {
+      "count": 4126,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102e8"
+    },
+    {
+      "count": 4884,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102fe"
+    },
+    {
+      "count": 5655,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010330"
+    },
+    {
+      "count": 6412,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010346"
+    },
+    {
+      "count": 7171,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001035e"
+    },
+    {
+      "count": 7930,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010376"
+    },
+    {
+      "count": 8689,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001038e"
+    },
+    {
+      "count": 9455,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103a6"
+    },
+    {
+      "count": 10220,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103de"
+    },
+    {
+      "count": 11003,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010456"
+    },
+    {
+      "count": 11794,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000104e8"
+    },
+    {
+      "count": 12582,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010574"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "002b4d206321f5ecaa40ef5064ba9756148bbcdc90ec349033f5897729654176",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-pto0571-evidence/qemu-system-linx64",
+    "sha": "583cad3f6ce68d05a559a354a3e7059844f47a5d",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1071-g583cad3f6c)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10286,0x102a0,0x102b8,0x102d0,0x102e8,0x102fe,0x10330,0x10346,0x1035e,0x10376,0x1038e,0x103a6,0x103de,0x10456,0x104e8,0x10574",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00002501",
+    "0x00002502",
+    "0x00002503",
+    "0x00002504",
+    "0x00002505",
+    "0x00002506",
+    "0x00002507",
+    "0x00002508",
+    "0x00002509",
+    "0x0000250a",
+    "0x0000250b",
+    "0x0000250c",
+    "0x0000250d",
+    "0x0000250e",
+    "0x0000250f",
+    "0x00002510"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x00002510"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "82956cbbe2780222691b0024a8a9672a9ab5e8aead35d99a346f2531ab47790b",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "executable_scalar"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00002501"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00002501"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00002502"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00002502"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00002503"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00002503"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00002504"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00002504"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00002505"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00002505"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00002506"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00002506"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00002507"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00002507"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00002508"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00002508"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00002509"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00002509"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x0000250a"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x0000250a"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x0000250b"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x0000250b"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x0000250c"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x0000250c"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x0000250d"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x0000250d"
+    },
+    {
+      "kind": "START",
+      "seq": 26,
+      "test_id": "0x0000250e"
+    },
+    {
+      "kind": "PASS",
+      "seq": 27,
+      "test_id": "0x0000250e"
+    },
+    {
+      "kind": "START",
+      "seq": 28,
+      "test_id": "0x0000250f"
+    },
+    {
+      "kind": "PASS",
+      "seq": 29,
+      "test_id": "0x0000250f"
+    },
+    {
+      "kind": "START",
+      "seq": 30,
+      "test_id": "0x00002510"
+    },
+    {
+      "kind": "PASS",
+      "seq": 31,
+      "test_id": "0x00002510"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
new file mode 100644
index 00000000..63b38cdd
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
@@ -0,0 +1,16 @@
+linx_pc_watch: pc=0x10286 hit=1 printed=1 count=1094 sp=0x7feffa8 a0=0x0 a1=0x1234 a2=0x5678 ra=0x1089a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10278 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102a0 hit=1 printed=1 count=1852 sp=0x7feffa8 a0=0x0 a1=0x9876 a2=0x1234 ra=0x10906 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10292 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102b8 hit=1 printed=1 count=2610 sp=0x7feffa8 a0=0x0 a1=0xf0f0 a2=0xff0 ra=0x1093a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102ac tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102d0 hit=1 printed=1 count=3368 sp=0x7feffa8 a0=0x0 a1=0xf0f0 a2=0xff0 ra=0x1096a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102c4 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102e8 hit=1 printed=1 count=4126 sp=0x7feffa8 a0=0x0 a1=0xaaaa a2=0xf0f ra=0x1099e tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102dc tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102fe hit=1 printed=1 count=4884 sp=0x7feffa8 a0=0x0 a1=0x123 a2=0x44 ra=0x109d2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102f4 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10330 hit=1 printed=1 count=5655 sp=0x7feff98 a0=0x800000000000000 a1=0x8000000000000000 a2=0x44 ra=0x10a26 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1030a tq0=0x0 tq1=0x0 uq0=0x8000000000000000 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10346 hit=1 printed=1 count=6412 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffff00 a2=0x44 ra=0x10a6a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033c tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1035e hit=1 printed=1 count=7171 sp=0x7feffa8 a0=0x0 a1=0x110e8 a2=0x1 ra=0x10a96 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10352 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10376 hit=1 printed=1 count=7930 sp=0x7feffa8 a0=0x0 a1=0x110e8 a2=0x2 ra=0x10ac2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1036a tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1038e hit=1 printed=1 count=8689 sp=0x7feffa8 a0=0x0 a1=0x110e8 a2=0x4 ra=0x10af2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10382 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103a6 hit=1 printed=1 count=9455 sp=0x7feff98 a0=0x123456700000000 a1=0x110e8 a2=0x8 ra=0x10b46 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1039a tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103de hit=1 printed=1 count=10220 sp=0x7feffa8 a0=0x12000 a1=0xa5 a2=0x1 ra=0x10b8a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103b2 tq0=0x12000 tq1=0x22 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10456 hit=1 printed=1 count=11003 sp=0x7feffa8 a0=0x12000 a1=0xb6c7 a2=0x1 ra=0x10bb6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10422 tq0=0x12000 tq1=0x22 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x104e8 hit=1 printed=1 count=11794 sp=0x7feffa8 a0=0xdeadbeef a1=0xffffffffdeadbeef a2=0x12000 ra=0x10be2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x104ae tq0=0x12000 tq1=0xdeadbeef00000000 uq0=0x20 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10574 hit=1 printed=1 count=12582 sp=0x7feffa8 a0=0x0 a1=0x123456789abcdef a2=0x12000 ra=0x10c0e tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1052c tq0=0x12000 tq1=0x89abcdef uq0=0x123456700000000 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.uart.log
new file mode 100644
index 00000000..87d94283
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v057-583cad3f-20260731-r1/run-evidence.uart.log
@@ -0,0 +1,27 @@
+Linx QEMU tests
+  Test 0x00002501: PASS
+  Test 0x00002502: PASS
+  Test 0x00002503: PASS
+  Test 0x00002504: PASS
+  Test 0x00002505: PASS
+  Test 0x00002506: PASS
+  Test 0x00002507: PASS
+  Test 0x00002508: PASS
+  Test 0x00002509: PASS
+  Test 0x0000250A: PASS
+  Test 0x0000250B: PASS
+  Test 0x0000250C: PASS
+  Test 0x0000250D: PASS
+  Test 0x0000250E: PASS
+  Test 0x0000250F: PASS
+  Test 0x00002510: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf
new file mode 100755
index 00000000..1b0acbf6
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o
new file mode 100644
index 00000000..306883d4
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o
new file mode 100644
index 00000000..6f04125f
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/main.o
new file mode 100644
index 00000000..579ae1df
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/mem.o
new file mode 100644
index 00000000..dd408f9e
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json
new file mode 100644
index 00000000..71e127d4
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json
@@ -0,0 +1,372 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o",
+      "sha256": "6d28bcb13e1db09ca031b22518cafa1f0045a294adca9870c290385a0bd7b25b"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/main.o",
+        "sha256": "b62073c462b60f11ecd32ec9945f6fb6c851ac8ad7f43a098cee5695add1c59f"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/mem.o",
+        "sha256": "31048812dd2be1454c0ba009c2f8381c1ca3417ebd1413a058fc89184dadecec"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+        "sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log",
+      "sha256": "f11a4c7a59ee2d26191c6823ba0998a0b86d00ef763964c7383624ae42d32c95"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.uart.log",
+      "sha256": "82956cbbe2780222691b0024a8a9672a9ab5e8aead35d99a346f2531ab47790b"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010286",
+      "0x00000000000102a0",
+      "0x00000000000102b8",
+      "0x00000000000102d0",
+      "0x00000000000102e8",
+      "0x00000000000102fe",
+      "0x0000000000010330",
+      "0x0000000000010346",
+      "0x000000000001035e",
+      "0x0000000000010376",
+      "0x000000000001038e",
+      "0x00000000000103a6",
+      "0x00000000000103de",
+      "0x0000000000010456",
+      "0x00000000000104e8",
+      "0x0000000000010574"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 1094,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010286"
+    },
+    {
+      "count": 1852,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102a0"
+    },
+    {
+      "count": 2610,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102b8"
+    },
+    {
+      "count": 3368,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102d0"
+    },
+    {
+      "count": 4126,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102e8"
+    },
+    {
+      "count": 4884,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102fe"
+    },
+    {
+      "count": 5655,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010330"
+    },
+    {
+      "count": 6412,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010346"
+    },
+    {
+      "count": 7171,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001035e"
+    },
+    {
+      "count": 7930,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010376"
+    },
+    {
+      "count": 8689,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x000000000001038e"
+    },
+    {
+      "count": 9455,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103a6"
+    },
+    {
+      "count": 10220,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000103de"
+    },
+    {
+      "count": 11003,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010456"
+    },
+    {
+      "count": 11794,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000104e8"
+    },
+    {
+      "count": 12582,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010574"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "c6176cc23eef482e5a64ee4f728a22fd44f35aac214a9d0c389fc8aa03ef0290",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-v0571-clean/qemu-system-linx64",
+    "sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1067-gcfc253e844)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10286,0x102a0,0x102b8,0x102d0,0x102e8,0x102fe,0x10330,0x10346,0x1035e,0x10376,0x1038e,0x103a6,0x103de,0x10456,0x104e8,0x10574",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00002501",
+    "0x00002502",
+    "0x00002503",
+    "0x00002504",
+    "0x00002505",
+    "0x00002506",
+    "0x00002507",
+    "0x00002508",
+    "0x00002509",
+    "0x0000250a",
+    "0x0000250b",
+    "0x0000250c",
+    "0x0000250d",
+    "0x0000250e",
+    "0x0000250f",
+    "0x00002510"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x00002510"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "82956cbbe2780222691b0024a8a9672a9ab5e8aead35d99a346f2531ab47790b",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "executable_scalar"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00002501"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00002501"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00002502"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00002502"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00002503"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00002503"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00002504"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00002504"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00002505"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00002505"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00002506"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00002506"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00002507"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00002507"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00002508"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00002508"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00002509"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00002509"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x0000250a"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x0000250a"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x0000250b"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x0000250b"
+    },
+    {
+      "kind": "START",
+      "seq": 22,
+      "test_id": "0x0000250c"
+    },
+    {
+      "kind": "PASS",
+      "seq": 23,
+      "test_id": "0x0000250c"
+    },
+    {
+      "kind": "START",
+      "seq": 24,
+      "test_id": "0x0000250d"
+    },
+    {
+      "kind": "PASS",
+      "seq": 25,
+      "test_id": "0x0000250d"
+    },
+    {
+      "kind": "START",
+      "seq": 26,
+      "test_id": "0x0000250e"
+    },
+    {
+      "kind": "PASS",
+      "seq": 27,
+      "test_id": "0x0000250e"
+    },
+    {
+      "kind": "START",
+      "seq": 28,
+      "test_id": "0x0000250f"
+    },
+    {
+      "kind": "PASS",
+      "seq": 29,
+      "test_id": "0x0000250f"
+    },
+    {
+      "kind": "START",
+      "seq": 30,
+      "test_id": "0x00002510"
+    },
+    {
+      "kind": "PASS",
+      "seq": 31,
+      "test_id": "0x00002510"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
new file mode 100644
index 00000000..63b38cdd
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
@@ -0,0 +1,16 @@
+linx_pc_watch: pc=0x10286 hit=1 printed=1 count=1094 sp=0x7feffa8 a0=0x0 a1=0x1234 a2=0x5678 ra=0x1089a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10278 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102a0 hit=1 printed=1 count=1852 sp=0x7feffa8 a0=0x0 a1=0x9876 a2=0x1234 ra=0x10906 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10292 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102b8 hit=1 printed=1 count=2610 sp=0x7feffa8 a0=0x0 a1=0xf0f0 a2=0xff0 ra=0x1093a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102ac tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102d0 hit=1 printed=1 count=3368 sp=0x7feffa8 a0=0x0 a1=0xf0f0 a2=0xff0 ra=0x1096a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102c4 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102e8 hit=1 printed=1 count=4126 sp=0x7feffa8 a0=0x0 a1=0xaaaa a2=0xf0f ra=0x1099e tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102dc tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102fe hit=1 printed=1 count=4884 sp=0x7feffa8 a0=0x0 a1=0x123 a2=0x44 ra=0x109d2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x102f4 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10330 hit=1 printed=1 count=5655 sp=0x7feff98 a0=0x800000000000000 a1=0x8000000000000000 a2=0x44 ra=0x10a26 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1030a tq0=0x0 tq1=0x0 uq0=0x8000000000000000 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10346 hit=1 printed=1 count=6412 sp=0x7feffa8 a0=0x0 a1=0xffffffffffffff00 a2=0x44 ra=0x10a6a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033c tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1035e hit=1 printed=1 count=7171 sp=0x7feffa8 a0=0x0 a1=0x110e8 a2=0x1 ra=0x10a96 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10352 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10376 hit=1 printed=1 count=7930 sp=0x7feffa8 a0=0x0 a1=0x110e8 a2=0x2 ra=0x10ac2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1036a tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x1038e hit=1 printed=1 count=8689 sp=0x7feffa8 a0=0x0 a1=0x110e8 a2=0x4 ra=0x10af2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10382 tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103a6 hit=1 printed=1 count=9455 sp=0x7feff98 a0=0x123456700000000 a1=0x110e8 a2=0x8 ra=0x10b46 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1039a tq0=0x11000 tq1=0x0 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x103de hit=1 printed=1 count=10220 sp=0x7feffa8 a0=0x12000 a1=0xa5 a2=0x1 ra=0x10b8a tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103b2 tq0=0x12000 tq1=0x22 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10456 hit=1 printed=1 count=11003 sp=0x7feffa8 a0=0x12000 a1=0xb6c7 a2=0x1 ra=0x10bb6 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10422 tq0=0x12000 tq1=0x22 uq0=0x0 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x104e8 hit=1 printed=1 count=11794 sp=0x7feffa8 a0=0xdeadbeef a1=0xffffffffdeadbeef a2=0x12000 ra=0x10be2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x104ae tq0=0x12000 tq1=0xdeadbeef00000000 uq0=0x20 uq1=0x0 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10574 hit=1 printed=1 count=12582 sp=0x7feffa8 a0=0x0 a1=0x123456789abcdef a2=0x12000 ra=0x10c0e tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1052c tq0=0x12000 tq1=0x89abcdef uq0=0x123456700000000 uq1=0x20 in_body=0 blocktype=0 body_tpc=0x0 return_pc=0x0 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
new file mode 100644
index 00000000..87d94283
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
@@ -0,0 +1,27 @@
+Linx QEMU tests
+  Test 0x00002501: PASS
+  Test 0x00002502: PASS
+  Test 0x00002503: PASS
+  Test 0x00002504: PASS
+  Test 0x00002505: PASS
+  Test 0x00002506: PASS
+  Test 0x00002507: PASS
+  Test 0x00002508: PASS
+  Test 0x00002509: PASS
+  Test 0x0000250A: PASS
+  Test 0x0000250B: PASS
+  Test 0x0000250C: PASS
+  Test 0x0000250D: PASS
+  Test 0x0000250E: PASS
+  Test 0x0000250F: PASS
+  Test 0x00002510: PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/refresh-v057-583cad3f-20260731-r1.json b/docs/bringup/gates/evidence/qemu-executable/refresh-v057-583cad3f-20260731-r1.json
new file mode 100644
index 00000000..098a3fa0
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/refresh-v057-583cad3f-20260731-r1.json
@@ -0,0 +1,7 @@
+{
+  "qemu_sha": "583cad3f6ce68d05a559a354a3e7059844f47a5d",
+  "llvm_sha": "487db9698c9c748de9afe33aa160c6a52be961ab",
+  "form_count": 60,
+  "unchanged_pc_count": 60,
+  "pc_changes": []
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/refresh-v0571-cfc253e8-20260802-r2.json b/docs/bringup/gates/evidence/qemu-executable/refresh-v0571-cfc253e8-20260802-r2.json
new file mode 100644
index 00000000..74519bb4
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/refresh-v0571-cfc253e8-20260802-r2.json
@@ -0,0 +1,7 @@
+{
+  "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+  "llvm_sha": "3feb50e4e1896105746a1831d3545d690518d3b3",
+  "form_count": 60,
+  "unchanged_pc_count": 60,
+  "pc_changes": []
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/linx-qemu-tests.elf
new file mode 100755
index 00000000..2ee5c2d1
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/linx-qemu-tests.o
new file mode 100644
index 00000000..81494076
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/13_v057_vector_ops_matrix.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/13_v057_vector_ops_matrix.o
new file mode 100644
index 00000000..75e72f99
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/13_v057_vector_ops_matrix.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/main.o
new file mode 100644
index 00000000..d2f76ed2
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/math.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/math.o
new file mode 100644
index 00000000..c86a0a96
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/math.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/mem.o
new file mode 100644
index 00000000..5b1de528
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/softfp.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/softfp.o
new file mode 100644
index 00000000..9c5eb86d
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/softfp.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.json
new file mode 100644
index 00000000..382d2c11
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.json
@@ -0,0 +1,262 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/linx-qemu-tests.elf",
+      "sha256": "ef79fdf2700634e8e575a1b584e09c9ed8419a8feba21ec3add047f0668581ef"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/linx-qemu-tests.o",
+      "sha256": "59ada63b8c7f5c50a1f452570f5834393515f3bd8c5f6038b1074d82e3fd563c"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/main.o",
+        "sha256": "ab34d56b45713cfdfbbf430b11ce73153a90c89e06da0cc0f3161dc497c47635"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/mem.o",
+        "sha256": "092fc93cc4ebb1e2a2922e5318f3cefa1b504c23d36a76808b269806f3caac25"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/13_v057_vector_ops_matrix.o",
+        "sha256": "f125193800aaea72927cbbc4a6b393031d0df3ec91b152d5c863192212767eac"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/softfp.o",
+        "sha256": "3f7590c6869e1441fa3f781a01740e5a31cb5a6882fe42192f321bd3afa2b009"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/obj/math.o",
+        "sha256": "94affc364c74116c0210fc83846cbc0dc6f9c1dfc3c4c7ef8ef620f5517335e8"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log",
+      "sha256": "8aa514d5eec652e4f357f701e9792421b7b605eb6b0056c8bc37209eec658645"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.uart.log",
+      "sha256": "00e7d09a06d0682b78f819d486b9c5f3024c45c01742ab8048e888964e91f658"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010278",
+      "0x0000000000010288",
+      "0x0000000000010290",
+      "0x0000000000010298",
+      "0x00000000000102b8",
+      "0x00000000000102c0",
+      "0x0000000000010324"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 2761,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010278"
+    },
+    {
+      "count": 2763,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010288"
+    },
+    {
+      "count": 2764,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010290"
+    },
+    {
+      "count": 2765,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010298"
+    },
+    {
+      "count": 15012,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102b8"
+    },
+    {
+      "count": 15013,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102c0"
+    },
+    {
+      "count": 52831,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010324"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "002b4d206321f5ecaa40ef5064ba9756148bbcdc90ec349033f5897729654176",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-pto0571-evidence/qemu-system-linx64",
+    "sha": "583cad3f6ce68d05a559a354a3e7059844f47a5d",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1071-g583cad3f6c)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10278,0x10288,0x10290,0x10298,0x102b8,0x102c0,0x10324",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00001300",
+    "0x00001310",
+    "0x00001320",
+    "0x00001370",
+    "0x00001371",
+    "0x00001372",
+    "0x00001373",
+    "0x00001374",
+    "0x00001375",
+    "0x00001376",
+    "0x00001377"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x00001320"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "00e7d09a06d0682b78f819d486b9c5f3024c45c01742ab8048e888964e91f658",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "v057_vector_ops"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00001300"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00001300"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00001310"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00001310"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00001370"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00001370"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00001371"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00001371"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00001372"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00001372"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00001373"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00001373"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00001374"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00001374"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00001375"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00001375"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00001376"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00001376"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x00001377"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x00001377"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x00001320"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x00001320"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
new file mode 100644
index 00000000..432eb465
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.pc-watch.log
@@ -0,0 +1,7 @@
+linx_pc_watch: pc=0x10278 hit=1 printed=1 count=2761 sp=0x7feff80 a0=0x15000 a1=0x15080 a2=0x15100 ra=0x104c2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10278 return_pc=0x1034c call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10288 hit=1 printed=1 count=2763 sp=0x7feff80 a0=0x15000 a1=0x15080 a2=0x15100 ra=0x104c2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10278 return_pc=0x1034c call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10290 hit=1 printed=1 count=2764 sp=0x7feff80 a0=0x15000 a1=0x15080 a2=0x15100 ra=0x104c2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10278 return_pc=0x1034c call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10298 hit=1 printed=1 count=2765 sp=0x7feff80 a0=0x15000 a1=0x15080 a2=0x15100 ra=0x104c2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10278 return_pc=0x1034c call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102b8 hit=1 printed=1 count=15012 sp=0x7feff80 a0=0x15210 a1=0x15290 a2=0x3f800000 ra=0x10620 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10362 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x102b0 return_pc=0x10374 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102c0 hit=1 printed=1 count=15013 sp=0x7feff80 a0=0x15210 a1=0x15290 a2=0x3f800000 ra=0x10620 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10362 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x102b0 return_pc=0x10374 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10324 hit=1 printed=1 count=52831 sp=0x7feff80 a0=0x15598 a1=0xc a2=0x1067514 ra=0x10c24 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103d6 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10320 return_pc=0x103e4 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.uart.log
new file mode 100644
index 00000000..58376b43
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v057-583cad3f-20260731-r1/run-evidence.uart.log
@@ -0,0 +1,22 @@
+Linx QEMU tests
+  Test 0x00001300: v0.57 vector add/sub matrix ... PASS
+  Test 0x00001310: v0.57 vector float matrix ... PASS
+  Test 0x00001370: v0.57 V.ADD evidence ... PASS
+  Test 0x00001371: v0.57 V.SUB evidence ... PASS
+  Test 0x00001372: v0.57 V.LW.BRG evidence ... PASS
+  Test 0x00001373: v0.57 V.SW.BRG evidence ... PASS
+  Test 0x00001374: v0.57 V.FADD evidence ... PASS
+  Test 0x00001375: v0.57 V.FMUL evidence ... PASS
+  Test 0x00001376: v0.57 V.FABS evidence ... PASS
+  Test 0x00001377: v0.57 V.MUL evidence ... PASS
+  Test 0x00001320: v0.57 mixed scalar/vector predicate ... PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf
new file mode 100755
index 00000000..3f3aa999
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o
new file mode 100644
index 00000000..18f6bfb5
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o
new file mode 100644
index 00000000..18c36177
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/main.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/main.o
new file mode 100644
index 00000000..1e3b023f
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/main.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/math.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/math.o
new file mode 100644
index 00000000..93c34889
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/math.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/mem.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/mem.o
new file mode 100644
index 00000000..dd408f9e
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/mem.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/softfp.o b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/softfp.o
new file mode 100644
index 00000000..e1f98fba
Binary files /dev/null and b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/softfp.o differ
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json
new file mode 100644
index 00000000..be5968ba
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json
@@ -0,0 +1,262 @@
+{
+  "artifacts": {
+    "elf": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "sha256": "1c28a1d7351c31376e11c3d34c153a3fa33be9e122e70c65912839eb05580b02"
+    },
+    "object": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.o",
+      "sha256": "da3fe09d56250babd4bad447d1ad1c3e6e238cf23d4a90f999e66f320e07ed1a"
+    },
+    "objects": [
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/main.o",
+        "sha256": "ee865a4f4d3d4734ea2dc70f593d5579630f36ccd8c4e47c571de059d0d8b2b1"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/mem.o",
+        "sha256": "31048812dd2be1454c0ba009c2f8381c1ca3417ebd1413a058fc89184dadecec"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
+        "sha256": "c9cd9482f6db396aef8f0527132d3c981914a975fe6a6e65ce04369ba455c871"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/softfp.o",
+        "sha256": "104c84cde46ed68199dfd2550369ec9620703bc54275dc520596a16c4b534f93"
+      },
+      {
+        "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/math.o",
+        "sha256": "7d2db7b15e4a2eb1ff9d580a71f9af664bd08aa9ffce54ec614b184031f6ff3f"
+      }
+    ],
+    "pc_watch": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log",
+      "sha256": "8aa514d5eec652e4f357f701e9792421b7b605eb6b0056c8bc37209eec658645"
+    },
+    "uart": {
+      "path": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.uart.log",
+      "sha256": "00e7d09a06d0682b78f819d486b9c5f3024c45c01742ab8048e888964e91f658"
+    }
+  },
+  "failure": null,
+  "oracle_verdict": "PASS",
+  "pc_evidence": {
+    "kind": "qemu_target_pc_watch_v1",
+    "packet_prefix": "linx_pc_watch:",
+    "requested_pcs": [
+      "0x0000000000010278",
+      "0x0000000000010288",
+      "0x0000000000010290",
+      "0x0000000000010298",
+      "0x00000000000102b8",
+      "0x00000000000102c0",
+      "0x0000000000010324"
+    ]
+  },
+  "pc_hits": [
+    {
+      "count": 2761,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010278"
+    },
+    {
+      "count": 2763,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010288"
+    },
+    {
+      "count": 2764,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010290"
+    },
+    {
+      "count": 2765,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010298"
+    },
+    {
+      "count": 15012,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102b8"
+    },
+    {
+      "count": 15013,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x00000000000102c0"
+    },
+    {
+      "count": 52831,
+      "evidence_kind": "qemu_target_pc_watch_v1",
+      "hit": 1,
+      "pc": "0x0000000000010324"
+    }
+  ],
+  "qemu": {
+    "binary_sha256": "c6176cc23eef482e5a64ee4f728a22fd44f35aac214a9d0c389fc8aa03ef0290",
+    "patch_sha256": null,
+    "path": "emulator/qemu/build-v0571-clean/qemu-system-linx64",
+    "sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+    "source_dirty": false,
+    "version": "QEMU emulator version 10.2.50 (v10.2.0-1067-gcfc253e844)"
+  },
+  "qemu_debug_env": {
+    "LINX_DEBUG_PC_WATCH": "0x10278,0x10288,0x10290,0x10298,0x102b8,0x102c0,0x10324",
+    "LINX_DEBUG_PC_WATCH_HIT_LIMIT": "1",
+    "LINX_DEBUG_PC_WATCH_PRINT": "1"
+  },
+  "required_test_ids_observed": [
+    "0x00001300",
+    "0x00001310",
+    "0x00001320",
+    "0x00001370",
+    "0x00001371",
+    "0x00001372",
+    "0x00001373",
+    "0x00001374",
+    "0x00001375",
+    "0x00001376",
+    "0x00001377"
+  ],
+  "run": {
+    "declared_suite_completion_test_ids": [
+      "0x00001320"
+    ],
+    "declared_terminal_test_ids": [],
+    "exit_code": 0,
+    "missing_required_test_ids": [],
+    "missing_suite_completion_test_ids": [],
+    "pass_marker": {
+      "kind": "uart_success_marker",
+      "value": "TEST SUITE COMPLETE"
+    },
+    "stalled": false,
+    "stdout_sha256": "00e7d09a06d0682b78f819d486b9c5f3024c45c01742ab8048e888964e91f658",
+    "timed_out": false,
+    "timeout_after_fail": false,
+    "verdict_reason": "clean_terminal_oracle"
+  },
+  "schema_version": 1,
+  "status": "PASS",
+  "suites": [
+    "v057_vector_ops"
+  ],
+  "test_events": [
+    {
+      "kind": "START",
+      "seq": 0,
+      "test_id": "0x00001300"
+    },
+    {
+      "kind": "PASS",
+      "seq": 1,
+      "test_id": "0x00001300"
+    },
+    {
+      "kind": "START",
+      "seq": 2,
+      "test_id": "0x00001310"
+    },
+    {
+      "kind": "PASS",
+      "seq": 3,
+      "test_id": "0x00001310"
+    },
+    {
+      "kind": "START",
+      "seq": 4,
+      "test_id": "0x00001370"
+    },
+    {
+      "kind": "PASS",
+      "seq": 5,
+      "test_id": "0x00001370"
+    },
+    {
+      "kind": "START",
+      "seq": 6,
+      "test_id": "0x00001371"
+    },
+    {
+      "kind": "PASS",
+      "seq": 7,
+      "test_id": "0x00001371"
+    },
+    {
+      "kind": "START",
+      "seq": 8,
+      "test_id": "0x00001372"
+    },
+    {
+      "kind": "PASS",
+      "seq": 9,
+      "test_id": "0x00001372"
+    },
+    {
+      "kind": "START",
+      "seq": 10,
+      "test_id": "0x00001373"
+    },
+    {
+      "kind": "PASS",
+      "seq": 11,
+      "test_id": "0x00001373"
+    },
+    {
+      "kind": "START",
+      "seq": 12,
+      "test_id": "0x00001374"
+    },
+    {
+      "kind": "PASS",
+      "seq": 13,
+      "test_id": "0x00001374"
+    },
+    {
+      "kind": "START",
+      "seq": 14,
+      "test_id": "0x00001375"
+    },
+    {
+      "kind": "PASS",
+      "seq": 15,
+      "test_id": "0x00001375"
+    },
+    {
+      "kind": "START",
+      "seq": 16,
+      "test_id": "0x00001376"
+    },
+    {
+      "kind": "PASS",
+      "seq": 17,
+      "test_id": "0x00001376"
+    },
+    {
+      "kind": "START",
+      "seq": 18,
+      "test_id": "0x00001377"
+    },
+    {
+      "kind": "PASS",
+      "seq": 19,
+      "test_id": "0x00001377"
+    },
+    {
+      "kind": "START",
+      "seq": 20,
+      "test_id": "0x00001320"
+    },
+    {
+      "kind": "PASS",
+      "seq": 21,
+      "test_id": "0x00001320"
+    }
+  ]
+}
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
new file mode 100644
index 00000000..432eb465
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.pc-watch.log
@@ -0,0 +1,7 @@
+linx_pc_watch: pc=0x10278 hit=1 printed=1 count=2761 sp=0x7feff80 a0=0x15000 a1=0x15080 a2=0x15100 ra=0x104c2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10278 return_pc=0x1034c call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10288 hit=1 printed=1 count=2763 sp=0x7feff80 a0=0x15000 a1=0x15080 a2=0x15100 ra=0x104c2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10278 return_pc=0x1034c call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10290 hit=1 printed=1 count=2764 sp=0x7feff80 a0=0x15000 a1=0x15080 a2=0x15100 ra=0x104c2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10278 return_pc=0x1034c call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10298 hit=1 printed=1 count=2765 sp=0x7feff80 a0=0x15000 a1=0x15080 a2=0x15100 ra=0x104c2 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x1033a tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10278 return_pc=0x1034c call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102b8 hit=1 printed=1 count=15012 sp=0x7feff80 a0=0x15210 a1=0x15290 a2=0x3f800000 ra=0x10620 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10362 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x102b0 return_pc=0x10374 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x102c0 hit=1 printed=1 count=15013 sp=0x7feff80 a0=0x15210 a1=0x15290 a2=0x3f800000 ra=0x10620 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x10362 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x102b0 return_pc=0x10374 call_ra_set=0 call_setret_pending=0
+linx_pc_watch: pc=0x10324 hit=1 printed=1 count=52831 sp=0x7feff80 a0=0x15598 a1=0xc a2=0x1067514 ra=0x10c24 tp=0x0 cstate=0x0 cond=0 carg=0 brtype=1 tgt=0x0 bpc=0x103d6 tq0=0x0 tq1=0x0 uq0=0x0 uq1=0x0 in_body=1 blocktype=1 body_tpc=0x10320 return_pc=0x103e4 call_ra_set=0 call_setret_pending=0
diff --git a/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.uart.log b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
new file mode 100644
index 00000000..58376b43
--- /dev/null
+++ b/docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.uart.log
@@ -0,0 +1,22 @@
+Linx QEMU tests
+  Test 0x00001300: v0.57 vector add/sub matrix ... PASS
+  Test 0x00001310: v0.57 vector float matrix ... PASS
+  Test 0x00001370: v0.57 V.ADD evidence ... PASS
+  Test 0x00001371: v0.57 V.SUB evidence ... PASS
+  Test 0x00001372: v0.57 V.LW.BRG evidence ... PASS
+  Test 0x00001373: v0.57 V.SW.BRG evidence ... PASS
+  Test 0x00001374: v0.57 V.FADD evidence ... PASS
+  Test 0x00001375: v0.57 V.FMUL evidence ... PASS
+  Test 0x00001376: v0.57 V.FABS evidence ... PASS
+  Test 0x00001377: v0.57 V.MUL evidence ... PASS
+  Test 0x00001320: v0.57 mixed scalar/vector predicate ... PASS
+
+=================================================
+              TEST SUITE COMPLETE                
+=================================================
+
+All tests completed successfully!
+
+Note: Check UART output for individual test results.
+      Each test suite prints PASS for each test.
+
diff --git a/docs/bringup/gates/isa_llvm_qemu_coverage_latest.json b/docs/bringup/gates/isa_llvm_qemu_coverage_latest.json
index 5f8f1ce7..e4f95538 100644
--- a/docs/bringup/gates/isa_llvm_qemu_coverage_latest.json
+++ b/docs/bringup/gates/isa_llvm_qemu_coverage_latest.json
@@ -1,205 +1,15 @@
 {
   "claim": "l1_mapping_coherence",
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-  "compiler_out_dir": "/Users/zhoubot/linx-isa/avs/compiler/linx-llvm/tests/out",
-  "generated_at_utc": "2026-07-18 02:41:48Z",
+  "compiler_analyzer": "/private/tmp/linx-isa-v0571/avs/compiler/linx-llvm/tests/analyze_coverage.py",
+  "compiler_out_dir": "/private/tmp/linx-isa-v0571/avs/compiler/linx-llvm/tests/out",
+  "generated_at_utc": "2026-08-02 12:51:47Z",
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-      "V.SHFLI.UP",
-      "V.SHI",
-      "V.SHI.BRG",
-      "V.SHI.U",
-      "V.SHI.U.BRG",
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-      "V.SW.AND",
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-      "V.SW.MIN",
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-      "V.SW.U",
-      "V.SW.U.BRG",
-      "V.SW.XOR",
-      "V.SWI",
-      "V.SWI.BRG",
-      "V.SWI.U",
-      "V.SWI.U.BRG",
-      "XB"
-    ],
-    "compiler_only_vs_qemu_l1_mapping_by_prefix": [
-      [
-        "V",
-        84
-      ],
-      [
-        "XB",
-        1
-      ]
-    ],
-    "compiler_only_vs_qemu_l1_mapping_count": 85,
+    "compiler_only_vs_qemu_impl": [],
+    "compiler_only_vs_qemu_impl_by_prefix": [],
+    "compiler_only_vs_qemu_impl_count": 0,
+    "compiler_only_vs_qemu_l1_mapping": [],
+    "compiler_only_vs_qemu_l1_mapping_by_prefix": [],
+    "compiler_only_vs_qemu_l1_mapping_count": 0,
     "compiler_only_vs_translation": [],
     "compiler_only_vs_translation_by_prefix": [],
     "compiler_only_vs_translation_count": 0,
@@ -211,186 +21,14 @@
     "qemu_l1_mapping_only_vs_translation_count": 0,
     "translation_non_spec_count": 0,
     "translation_non_spec_mnemonics": [],
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-      "V.SD.OR",
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-      "V.SHI",
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-      "V.SW.MIN",
-      "V.SW.OR",
-      "V.SW.U",
-      "V.SW.U.BRG",
-      "V.SW.XOR",
-      "V.SWI",
-      "V.SWI.BRG",
-      "V.SWI.U",
-      "V.SWI.U.BRG",
-      "XB"
-    ],
-    "translation_without_qemu_l1_mapping_count": 85
+    "translation_without_qemu_impl": [],
+    "translation_without_qemu_impl_count": 0,
+    "translation_without_qemu_l1_mapping": [],
+    "translation_without_qemu_l1_mapping_count": 0
   },
   "llvm": {
     "claim": "observed_disassembly_mnemonic_breadth",
-    "coverage_count": 731,
+    "coverage_count": 728,
     "coverage_ratio_percent": 100.0,
     "metric_scope": "unique ISA mnemonics observed in *.objdump instruction lines",
     "missing_count": 0,
@@ -404,59 +42,59 @@
     "L1": {
       "availability": "available",
       "claim": "decoder_source_mapping",
-      "form_count": 678,
-      "mnemonic_count": 646
+      "form_count": 761,
+      "mnemonic_count": 728
     },
     "L2": {
       "availability": "available",
       "claim": "runtime_execution",
       "form_count": 60,
       "mnemonic_count": 60,
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "source": "/Users/zhoubot/linx-isa/docs/bringup/gates/qemu_executable_coverage_latest.json"
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "source": "/private/tmp/linx-isa-v0571/docs/bringup/gates/qemu_executable_coverage_latest.json"
     },
     "L3": {
       "availability": "available",
       "claim": "semantic_oracle",
       "form_count": 60,
       "mnemonic_count": 60,
-      "qemu_sha": "d0e88a99f575f87436137d91341b410e6f2f445b",
-      "source": "/Users/zhoubot/linx-isa/docs/bringup/gates/qemu_executable_coverage_latest.json"
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "source": "/private/tmp/linx-isa-v0571/docs/bringup/gates/qemu_executable_coverage_latest.json"
     }
   },
   "qemu_impl": {
     "claim": "decoder_source_mapping",
-    "coverage_count": 646,
-    "coverage_ratio_percent": 88.37,
+    "coverage_count": 728,
+    "coverage_ratio_percent": 100.0,
     "deprecated_alias_for": "qemu_l1_mapping",
     "evidence_level": "L1",
-    "missing_count": 85
+    "missing_count": 0
   },
-  "qemu_isa_report": "/Users/zhoubot/linx-isa/docs/bringup/gates/qemu_isa_coverage_latest.json",
+  "qemu_isa_report": "/private/tmp/linx-isa-v0571/docs/bringup/gates/qemu_isa_coverage_latest.json",
   "qemu_l1_mapping": {
     "claim": "decoder_source_mapping",
-    "coverage_count": 646,
-    "coverage_ratio_percent": 88.37,
+    "coverage_count": 728,
+    "coverage_ratio_percent": 100.0,
     "evidence_level": "L1",
-    "missing_count": 85
+    "missing_count": 0
   },
   "qemu_translation": {
-    "coverage_count": 731,
+    "coverage_count": 728,
     "coverage_ratio_percent": 100.0,
-    "inventory_count": 731,
+    "inventory_count": 728,
     "missing_count": 0,
     "missing_spec_mnemonics": [],
     "non_spec_count": 0,
     "non_spec_mnemonics": []
   },
-  "qemu_translation_report": "/Users/zhoubot/linx-isa/docs/bringup/gates/qemu_translation_coverage_latest.json",
+  "qemu_translation_report": "/private/tmp/linx-isa-v0571/docs/bringup/gates/qemu_translation_coverage_latest.json",
   "result": {
-    "classification": "isa_llvm_qemu_l1_mapping_inconsistent",
+    "classification": "isa_llvm_qemu_l1_mapping_coherent",
     "ok": true,
     "runtime_execution_complete": null,
     "semantic_oracle_complete": null
   },
   "schema_version": "isa-llvm-qemu-l1-coherence-v3",
-  "spec_path": "/Users/zhoubot/linx-isa/isa/v0.57/linxisa-v0.57.json",
-  "spec_unique_mnemonics": 731
+  "spec_path": "/private/tmp/linx-isa-v0571/isa/v0.57/linxisa-v0.57.json",
+  "spec_unique_mnemonics": 728
 }
diff --git a/docs/bringup/gates/isa_llvm_qemu_coverage_latest.md b/docs/bringup/gates/isa_llvm_qemu_coverage_latest.md
index 504fdce8..0b79b2b6 100644
--- a/docs/bringup/gates/isa_llvm_qemu_coverage_latest.md
+++ b/docs/bringup/gates/isa_llvm_qemu_coverage_latest.md
@@ -1,7 +1,7 @@
 # ISA-LLVM-QEMU L1 Mapping Coherence
 
-- Generated (UTC): `2026-07-18 02:41:48Z`
-- Spec unique mnemonics: `731`
+- Generated (UTC): `2026-08-02 12:51:47Z`
+- Spec unique mnemonics: `728`
 - QEMU evidence: `L1 decoder_source_mapping`
 - L2 runtime execution: `available`
 - L3 semantic oracle: `available`
@@ -10,23 +10,21 @@
 
 | Surface | Covered | Ratio |
 | --- | --- | --- |
-| LLVM observed disassembly mnemonic breadth | `731/731` | `100.0%` |
-| QEMU L1 decoder/source mapping | `646/731` | `88.37%` |
-| QEMU AVS translation inventory | `731/731` | `100.0%` |
+| LLVM observed disassembly mnemonic breadth | `728/728` | `100.0%` |
+| QEMU L1 decoder/source mapping | `728/728` | `100.0%` |
+| QEMU AVS translation inventory | `728/728` | `100.0%` |
 
 - Non-spec translation inventory tokens: `0`
 
 ## Inconsistency Summary
 
-- Compiler-covered but missing from QEMU L1 mapping: `85`
+- Compiler-covered but missing from QEMU L1 mapping: `0`
 - QEMU L1-mapped but missing from AVS translation inventory: `0`
-- AVS translation-listed but absent from QEMU L1 mapping: `85`
+- AVS translation-listed but absent from QEMU L1 mapping: `0`
 - Compiler-covered but missing from AVS translation coverage: `0`
 
 ### Compiler vs QEMU L1 mapping
 
-- `V`: `84`
-- `XB`: `1`
 
 ### QEMU L1 mapping vs AVS translation
 
@@ -36,90 +34,5 @@
 
 ## Missing From QEMU L1 Mapping (First 200)
 
-- `V.LBI`
-- `V.LBI.BRG`
-- `V.LBUI`
-- `V.LBUI.BRG`
-- `V.LD`
-- `V.LD.ADD`
-- `V.LD.AND`
-- `V.LD.BRG`
-- `V.LD.MAX`
-- `V.LD.MIN`
-- `V.LD.OR`
-- `V.LD.XOR`
-- `V.LDI`
-- `V.LDI.BRG`
-- `V.LDI.U`
-- `V.LDI.U.BRG`
-- `V.LHI`
-- `V.LHI.BRG`
-- `V.LHI.U`
-- `V.LHI.U.BRG`
-- `V.LHUI`
-- `V.LHUI.BRG`
-- `V.LHUI.U`
-- `V.LHUI.U.BRG`
-- `V.LW.ADD`
-- `V.LW.AND`
-- `V.LW.MAX`
-- `V.LW.MIN`
-- `V.LW.OR`
-- `V.LW.XOR`
-- `V.LWI`
-- `V.LWI.BRG`
-- `V.LWI.U`
-- `V.LWI.U.BRG`
-- `V.LWU`
-- `V.LWU.BRG`
-- `V.LWUI`
-- `V.LWUI.BRG`
-- `V.LWUI.U`
-- `V.LWUI.U.BRG`
-- `V.QPOP`
-- `V.QPUSH`
-- `V.SBI`
-- `V.SBI.BRG`
-- `V.SD`
-- `V.SD.ADD`
-- `V.SD.AND`
-- `V.SD.BRG`
-- `V.SD.MAX`
-- `V.SD.MIN`
-- `V.SD.OR`
-- `V.SD.U`
-- `V.SD.U.BRG`
-- `V.SD.XOR`
-- `V.SDI`
-- `V.SDI.BRG`
-- `V.SDI.U`
-- `V.SDI.U.BRG`
-- `V.SH.U`
-- `V.SH.U.BRG`
-- `V.SHFL.BFLY`
-- `V.SHFL.DOWN`
-- `V.SHFL.IDX`
-- `V.SHFL.UP`
-- `V.SHFLI.BFLY`
-- `V.SHFLI.DOWN`
-- `V.SHFLI.IDX`
-- `V.SHFLI.UP`
-- `V.SHI`
-- `V.SHI.BRG`
-- `V.SHI.U`
-- `V.SHI.U.BRG`
-- `V.SW.ADD`
-- `V.SW.AND`
-- `V.SW.MAX`
-- `V.SW.MIN`
-- `V.SW.OR`
-- `V.SW.U`
-- `V.SW.U.BRG`
-- `V.SW.XOR`
-- `V.SWI`
-- `V.SWI.BRG`
-- `V.SWI.U`
-- `V.SWI.U.BRG`
-- `XB`
 
 ## Missing From AVS Translation Coverage (First 200)
diff --git a/docs/bringup/gates/llvm_c_codegen_coverage_latest.json b/docs/bringup/gates/llvm_c_codegen_coverage_latest.json
index f635eab0..26eed033 100644
--- a/docs/bringup/gates/llvm_c_codegen_coverage_latest.json
+++ b/docs/bringup/gates/llvm_c_codegen_coverage_latest.json
@@ -1,6 +1,6 @@
 {
   "schema_version": "linx-llvm-c-codegen-coverage-v1",
-  "generated_at_utc": "2026-07-18 02:41:42Z",
+  "generated_at_utc": "2026-08-02 12:51:42Z",
   "claim": "c_cpp_source_oriented_observed_disassembly_mnemonic_breadth",
   "status": "MEASURED",
   "threshold": null,
@@ -14,30 +14,30 @@
   "provenance_rule": "require a complete canonical run.sh build manifest with the exact current source set, exact flags, artifact and tool hashes; recompile every source with the manifest flags and regenerate objdump before accepting source-to-object-to-disassembly provenance",
   "inputs": {
     "spec": "isa/v0.57/linxisa-v0.57.json",
-    "spec_sha256": "9fded3bec2a2bb85adf088f20a95e089bc84e09eefc0cf60db0c40dce05ebecf",
+    "spec_sha256": "55099a57fda98b37fa067af9a284d5ec7dae156b9f9f2f3a51ed6efcdfb3edab",
     "compiler_analyzer": "avs/compiler/linx-llvm/tests/analyze_coverage.py",
-    "compiler_analyzer_sha256": "e84e461cc901f4dd8b9813682612afb1d49eead67c736f21916dfb6427269791",
+    "compiler_analyzer_sha256": "a6e79f229813ef078c095ca5e7fb6c6e76eb27aec3689f1e95fdd808e8b992da",
     "c_source_dir": "avs/compiler/linx-llvm/tests/c",
     "compiler_out_dir": "avs/compiler/linx-llvm/tests/out",
-    "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)",
-    "llvm_source_head": "c39f7d86ce08489b8beb0f0da9f614445a4aa8e5",
+    "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)",
+    "llvm_source_head": "3feb50e4e1896105746a1831d3545d690518d3b3",
     "llvm_source_clean": true,
-    "clang": "compiler/llvm/build-linxisa-clang/bin/clang-23",
-    "clang_sha256": "bba3a10f0eaf43f23f5dae9d06bd0312548f3c82129398c8baa6dc580d695391",
-    "llvm_objdump": "compiler/llvm/build-linxisa-clang/bin/llvm-objdump",
-    "llvm_objdump_sha256": "5caa9cae0011a7e91706e95f4fa08f7a2ff429c0246951c17eae65da57e02004",
+    "clang": "/private/tmp/llvm-v0571-verify-build/bin/clang-23",
+    "clang_sha256": "7557be4293747d4db2b20b285d153a64a705f1c5f944cbc2aac676c41cfa95c2",
+    "llvm_objdump": "/private/tmp/llvm-v0571-verify-build/bin/llvm-objdump",
+    "llvm_objdump_sha256": "2cb99299b9dd1723bd3ab5104048af29c37056387fa5b797acbdf00b01112ce9",
     "build_manifest": "avs/compiler/linx-llvm/tests/out/c-codegen-build-manifest.json",
-    "build_manifest_sha256": "30e841dfbe5e536db33566ecca3ef322348c36f9f100bf69948705829ad7025f",
+    "build_manifest_sha256": "4043fe1f9ead0d39f404fc5c6bd0909cfee8dd5104453c3d216ced6288fe56c8",
     "manifest_status": "complete",
     "target": "linx64-linx-none-elf",
     "replay_verified_source_count": 44,
     "plain_c_reachable_contract": "avs/compiler/linx-llvm/tests/plain_c_reachable_contract.json"
   },
-  "spec_unique_mnemonics": 731,
+  "spec_unique_mnemonics": 728,
   "direct": {
     "coverage_count": 146,
-    "coverage_denominator": 731,
-    "coverage_ratio_percent": 19.973,
+    "coverage_denominator": 728,
+    "coverage_ratio_percent": 20.055,
     "covered_mnemonics": [
       "ADD",
       "ADDI",
@@ -48,7 +48,7 @@
       "ANDI",
       "ANDIW",
       "ANDW",
-      "B.ARG",
+      "B.DATR",
       "BSTART.STD",
       "BXU",
       "C.ADD",
@@ -186,13 +186,12 @@
       "XORIW",
       "XORW"
     ],
-    "missing_count": 585,
+    "missing_count": 582,
     "missing_mnemonics": [
       "ACRC",
       "ACRE",
       "ASSERT",
       "B.CATR",
-      "B.DATR",
       "B.DIM",
       "B.EQ",
       "B.GE",
@@ -215,8 +214,6 @@
       "BSTART",
       "BSTART.ACCCVT",
       "BSTART.CALL",
-      "BSTART.CUBE",
-      "BSTART.FIXP",
       "BSTART.FP",
       "BSTART.MGATHER",
       "BSTART.MGATHER.CAS",
@@ -777,8 +774,8 @@
   },
   "alias_closure": {
     "coverage_count": 147,
-    "coverage_denominator": 731,
-    "coverage_ratio_percent": 20.109,
+    "coverage_denominator": 728,
+    "coverage_ratio_percent": 20.192,
     "covered_mnemonics": [
       "ADD",
       "ADDI",
@@ -789,7 +786,7 @@
       "ANDI",
       "ANDIW",
       "ANDW",
-      "B.ARG",
+      "B.DATR",
       "BSTART",
       "BSTART.STD",
       "BXU",
@@ -928,13 +925,12 @@
       "XORIW",
       "XORW"
     ],
-    "missing_count": 584,
+    "missing_count": 581,
     "missing_mnemonics": [
       "ACRC",
       "ACRE",
       "ASSERT",
       "B.CATR",
-      "B.DATR",
       "B.DIM",
       "B.EQ",
       "B.GE",
@@ -956,8 +952,6 @@
       "BSE",
       "BSTART.ACCCVT",
       "BSTART.CALL",
-      "BSTART.CUBE",
-      "BSTART.FIXP",
       "BSTART.FP",
       "BSTART.MGATHER",
       "BSTART.MGATHER.CAS",
@@ -1553,7 +1547,7 @@
     ],
     "direct_coverage_count": 145,
     "alias_closure_coverage_count": 146,
-    "coverage_denominator": 731,
+    "coverage_denominator": 728,
     "direct_covered_mnemonics": [
       "ADD",
       "ADDI",
@@ -1853,7 +1847,6 @@
       "ACRC",
       "ACRE",
       "ASSERT",
-      "B.ARG",
       "B.CATR",
       "B.DATR",
       "B.DIM",
@@ -1877,8 +1870,6 @@
       "BSE",
       "BSTART.ACCCVT",
       "BSTART.CALL",
-      "BSTART.CUBE",
-      "BSTART.FIXP",
       "BSTART.FP",
       "BSTART.MGATHER",
       "BSTART.MGATHER.CAS",
@@ -2559,9 +2550,9 @@
       "object": "avs/compiler/linx-llvm/tests/out/01_arith/01_arith.o",
       "objdump": "avs/compiler/linx-llvm/tests/out/01_arith/01_arith.objdump",
       "source_sha256": "6c4087ae77fd6016deb4bb055c2fc2f92288cbbe74fb9fcfbc72d2260217bb26",
-      "object_sha256": "8d65e77dcdb95fb764a1f99a32b6cac0fad3a660ebbcf909dc7e3de21bfc7fde",
+      "object_sha256": "924ee6757fd9cca4d3c5cb03ad2c918931d625e24e1d04692f3797610165637d",
       "objdump_sha256": "e846b490612e0d1c38f5e67f46dd6d46d7946d5bb8f2569d3ce52578dcda9267",
-      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)",
+      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)",
       "provenance_class": "pure_c_cpp",
       "source_directives": []
     },
@@ -2571,9 +2562,9 @@
       "object": "avs/compiler/linx-llvm/tests/out/02_control_flow/02_control_flow.o",
       "objdump": "avs/compiler/linx-llvm/tests/out/02_control_flow/02_control_flow.objdump",
       "source_sha256": "472eb0084b4a58fd73fc4a79664cb920c4fb9b0783cc68dc41749a3080ad28cc",
-      "object_sha256": "0327321b07f9772ddcb15ca9c956f4beaa108a01b2e4d75c4fba12922d597dae",
+      "object_sha256": "f9e7bfcead8837642b57707f9dfd7e575537cd1e89559e162364d65bd8575ea6",
       "objdump_sha256": "8f3aec57e7aa8d5d47d894ad6531b9ed4ec9ce6057e4318e0be11d3876be35ea",
-      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)",
+      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)",
       "provenance_class": "pure_c_cpp",
       "source_directives": []
     },
@@ -2583,9 +2574,9 @@
       "object": "avs/compiler/linx-llvm/tests/out/03_arrays/03_arrays.o",
       "objdump": "avs/compiler/linx-llvm/tests/out/03_arrays/03_arrays.objdump",
       "source_sha256": "7189784fbc1012c80702eee7edf0bc3a7b397da7d26f31d5f23e501dfd2a8ec8",
-      "object_sha256": "06237aa59ec8e8dedebf913e68ef263aa224c93ba42aa2f858cb90a92956bd34",
+      "object_sha256": "8c33cdadc0feb0bd8a81eb7ef1049d340f5a22beb8972467b969e24e4377ddd1",
       "objdump_sha256": "64aa476922d88d7fc97cfd1eb16d2c6c6ca30e1c300f56c5d8c90fb50642f4da",
-      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)",
+      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)",
       "provenance_class": "pure_c_cpp",
       "source_directives": []
     },
@@ -2595,9 +2586,9 @@
       "object": "avs/compiler/linx-llvm/tests/out/04_structs/04_structs.o",
       "objdump": "avs/compiler/linx-llvm/tests/out/04_structs/04_structs.objdump",
       "source_sha256": "1c59c538f98954d4dcd1569b63850a724a2929578b2b778d498cd0fbc363f3e9",
-      "object_sha256": "86f28b6bec9f61b5c3b3593ac726fbe3799789e36e47d7df02f197053568ce7f",
+      "object_sha256": "fdc317f60675f742e199cd5d386db7c7e8dbb08a5241442dc5c1fbb116aac1d5",
       "objdump_sha256": "5710f1e29f26aa561c18617bd056eb7f86a4e2a40c5c0a0edb2cd435a784e776",
-      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)",
+      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)",
       "provenance_class": "pure_c_cpp",
       "source_directives": []
     },
@@ -2607,9 +2598,9 @@
       "object": "avs/compiler/linx-llvm/tests/out/05_switch/05_switch.o",
       "objdump": "avs/compiler/linx-llvm/tests/out/05_switch/05_switch.objdump",
       "source_sha256": "a13399a606721d6a1ac72189ffb5268368cd35b9bf1881a6bd337f4cede8d9f2",
-      "object_sha256": "98bb3fd41eb908b5b2de8151535d386c13b248fedc7abc2e1b3cb6b61f057930",
+      "object_sha256": "ffa8e6a24cbf03f040ae16deed32c39bd1a02f59e4114b1470632fcb8035663e",
       "objdump_sha256": "1a272dd95fbc384e7bd17e82c330c8209ff0570b93fe1701ad07a2362450a6f9",
-      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)",
+      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)",
       "provenance_class": "pure_c_cpp",
       "source_directives": []
     },
@@ -2619,9 +2610,9 @@
       "object": "avs/compiler/linx-llvm/tests/out/06_recursion/06_recursion.o",
       "objdump": "avs/compiler/linx-llvm/tests/out/06_recursion/06_recursion.objdump",
       "source_sha256": "92591d5edbca981ff8b25136ac5200a23097f7cc69fa663f11926c89addc7fc3",
-      "object_sha256": "8bdec85584b20605a1ab0bb1b0871b0371c257c7b73bdf3f86f66820cb730b5e",
+      "object_sha256": "c3d36cc8f446d8a9bd2f17588245f2f185a863ca85f36e52f38f91a7b2ae1cac",
       "objdump_sha256": "4e82cc01e5dd58db4416108fc537020fc41086d5caaf8b389256e21261ef79ad",
-      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)",
+      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)",
       "provenance_class": "pure_c_cpp",
       "source_directives": []
     },
@@ -2631,9 +2622,9 @@
       "object": "avs/compiler/linx-llvm/tests/out/07_constants/07_constants.o",
       "objdump": "avs/compiler/linx-llvm/tests/out/07_constants/07_constants.objdump",
       "source_sha256": "8af76cfa6013ed9a8350ee9d04a883375837226f828e0e0adfade4c610fcc013",
-      "object_sha256": "ee9b67dd4b16fb839229896638a2ffd9f2d83ffd5824da1ca446c821e3aeeebf",
+      "object_sha256": "204f88ff4278877cbbc12167dce1fef41f124248e6395e8a864d324bfdb4db2e",
       "objdump_sha256": "839b3d49abe403ea674f0f361c7400c9f43fa7a70ac321ae58780b36c70552d0",
-      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)",
+      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)",
       "provenance_class": "pure_c_cpp",
       "source_directives": []
     },
@@ -2643,9 +2634,9 @@
       "object": "avs/compiler/linx-llvm/tests/out/08_loadstore/08_loadstore.o",
       "objdump": "avs/compiler/linx-llvm/tests/out/08_loadstore/08_loadstore.objdump",
       "source_sha256": "99720444922bd291e86ce69a898ee851e8ff7e8cfe1a2c5c837ddf1d1a67cde2",
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@@ -2871,9 +2862,9 @@
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       "objdump": "avs/compiler/linx-llvm/tests/out/27_three_source/27_three_source.objdump",
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@@ -2883,9 +2874,9 @@
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       "objdump": "avs/compiler/linx-llvm/tests/out/28_prefetch/28_prefetch.objdump",
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@@ -2897,9 +2888,9 @@
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@@ -2909,9 +2900,9 @@
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@@ -2921,9 +2912,9 @@
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@@ -2932,10 +2923,10 @@
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       "object": "avs/compiler/linx-llvm/tests/out/32_descriptor_marker/32_descriptor_marker.o",
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@@ -2947,9 +2938,9 @@
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@@ -2959,9 +2950,9 @@
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@@ -2971,9 +2962,9 @@
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@@ -2983,9 +2974,9 @@
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@@ -2995,9 +2986,9 @@
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@@ -3007,9 +2998,9 @@
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@@ -3019,9 +3010,9 @@
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       "objdump": "avs/compiler/linx-llvm/tests/out/39_callret_noreturn/39_callret_noreturn.objdump",
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@@ -3033,9 +3024,9 @@
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@@ -3047,9 +3038,9 @@
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@@ -3059,9 +3050,9 @@
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@@ -3071,9 +3062,9 @@
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@@ -3083,19 +3074,15 @@
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       "objdump": "avs/compiler/linx-llvm/tests/out/44_plain_c_sub_immediate/44_plain_c_sub_immediate.objdump",
       "source_sha256": "56bd6b4f33826797d44062d88429fe0c9499ed280a048efb7edec161c3cbacc0",
-      "object_sha256": "c230b4f17bf0ec782d592362ae9d4ecc01bd55eec4a18219963192c4ea7329c3",
+      "object_sha256": "14fdf160f652cb923a6bbec6fb118cfaf1116d5f712e8a5d883e050d5fce6808",
       "objdump_sha256": "15ddb2f868ff5ef48eefd13eb5fc7fefa4f7f34c2432a5af87063b73d86f79b1",
-      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)",
+      "compiler_identity": "clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)",
       "provenance_class": "pure_c_cpp",
       "source_directives": []
     }
   ],
-  "excluded_artifact_count": 7,
+  "excluded_artifact_count": 3,
   "excluded_artifacts": [
-    {
-      "artifact": "avs/compiler/linx-llvm/tests/out/41_v056_isa_forms/41_v056_isa_forms.objdump",
-      "reason": "no current C/C++ source with the same stem"
-    },
     {
       "artifact": "avs/compiler/linx-llvm/tests/out/41_v057_isa_forms/41_v057_isa_forms.objdump",
       "reason": "hand-authored assembly source; not C/C++ CodeGen"
@@ -3107,18 +3094,6 @@
     {
       "artifact": "avs/compiler/linx-llvm/tests/out/99_spec_decode/99_spec_decode.roundtrip.objdump",
       "reason": "roundtrip-only artifact; not C/C++ CodeGen"
-    },
-    {
-      "artifact": "avs/compiler/linx-llvm/tests/out/99_spec_decode/99_spec_decode.roundtrip.strict.objdump",
-      "reason": "roundtrip-only artifact; not C/C++ CodeGen"
-    },
-    {
-      "artifact": "avs/compiler/linx-llvm/tests/out/_neg/legacy_alias_l_bstop.objdump",
-      "reason": "no current C/C++ source with the same stem"
-    },
-    {
-      "artifact": "avs/compiler/linx-llvm/tests/out/grace-l-bstart-smoke/forms.objdump",
-      "reason": "no current C/C++ source with the same stem"
     }
   ],
   "observed_by_source": {
@@ -3685,7 +3660,7 @@
       "SRL"
     ],
     "avs/compiler/linx-llvm/tests/c/32_descriptor_marker.c": [
-      "B.ARG",
+      "B.DATR",
       "C.BSTART.STD",
       "FENTRY",
       "FRET.STK"
diff --git a/docs/bringup/gates/llvm_c_codegen_coverage_latest.md b/docs/bringup/gates/llvm_c_codegen_coverage_latest.md
index a9f1f4dd..4edba6af 100644
--- a/docs/bringup/gates/llvm_c_codegen_coverage_latest.md
+++ b/docs/bringup/gates/llvm_c_codegen_coverage_latest.md
@@ -1,15 +1,15 @@
 # LLVM C/C++ CodeGen ISA Mnemonic Breadth
 
-- Generated (UTC): `2026-07-18 02:41:42Z`
+- Generated (UTC): `2026-08-02 12:51:42Z`
 - Status: `MEASURED` (no target threshold is asserted)
-- Pure CodeGen direct coverage: `145/731`
-- Pure CodeGen after alias closure: `146/731`
-- C/C++ source-oriented direct coverage: `146/731` (`19.973%`)
-- C/C++ source-oriented after explicit alias closure: `147/731` (`20.109%`)
+- Pure CodeGen direct coverage: `145/728`
+- Pure CodeGen after alias closure: `146/728`
+- C/C++ source-oriented direct coverage: `146/728` (`20.055%`)
+- C/C++ source-oriented after explicit alias closure: `147/728` (`20.192%`)
 - Frozen plain-C reachable contract: `146/146` (`PASS`)
 - Included C/C++ artifacts: `44`
-- Excluded disassembly artifacts: `7`
-- Compiler identity: `clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git c39f7d86ce08489b8beb0f0da9f614445a4aa8e5)`
+- Excluded disassembly artifacts: `3`
+- Compiler identity: `clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 3feb50e4e1896105746a1831d3545d690518d3b3)`
 
 Pure CodeGen excludes C/C++ sources containing inline asm or compiler builtins. The broader source-oriented boundary includes those tests but does not relabel their source-directed instructions as compiler-selected CodeGen. Neither metric reuses generated `99_spec_decode` or hand-authored assembly-lane artifacts.
 
@@ -89,13 +89,9 @@ Pure CodeGen excludes C/C++ sources containing inline asm or compiler builtins.
 
 ## Excluded Artifacts
 
-- `avs/compiler/linx-llvm/tests/out/41_v056_isa_forms/41_v056_isa_forms.objdump`: no current C/C++ source with the same stem
 - `avs/compiler/linx-llvm/tests/out/41_v057_isa_forms/41_v057_isa_forms.objdump`: hand-authored assembly source; not C/C++ CodeGen
 - `avs/compiler/linx-llvm/tests/out/99_spec_decode/99_spec_decode.objdump`: generated ISA disassembly vector; not C/C++ CodeGen
 - `avs/compiler/linx-llvm/tests/out/99_spec_decode/99_spec_decode.roundtrip.objdump`: roundtrip-only artifact; not C/C++ CodeGen
-- `avs/compiler/linx-llvm/tests/out/99_spec_decode/99_spec_decode.roundtrip.strict.objdump`: roundtrip-only artifact; not C/C++ CodeGen
-- `avs/compiler/linx-llvm/tests/out/_neg/legacy_alias_l_bstop.objdump`: no current C/C++ source with the same stem
-- `avs/compiler/linx-llvm/tests/out/grace-l-bstart-smoke/forms.objdump`: no current C/C++ source with the same stem
 
 ## Missing Mnemonics After Alias Closure
 
@@ -103,7 +99,6 @@ Pure CodeGen excludes C/C++ sources containing inline asm or compiler builtins.
 - `ACRE`
 - `ASSERT`
 - `B.CATR`
-- `B.DATR`
 - `B.DIM`
 - `B.EQ`
 - `B.GE`
@@ -125,8 +120,6 @@ Pure CodeGen excludes C/C++ sources containing inline asm or compiler builtins.
 - `BSE`
 - `BSTART.ACCCVT`
 - `BSTART.CALL`
-- `BSTART.CUBE`
-- `BSTART.FIXP`
 - `BSTART.FP`
 - `BSTART.MGATHER`
 - `BSTART.MGATHER.CAS`
diff --git a/docs/bringup/gates/qemu_executable_coverage_latest.json b/docs/bringup/gates/qemu_executable_coverage_latest.json
index e32a1d55..4eda7150 100644
--- a/docs/bringup/gates/qemu_executable_coverage_latest.json
+++ b/docs/bringup/gates/qemu_executable_coverage_latest.json
@@ -1,428 +1,2572 @@
 {
   "admitted": [
     {
-      "disassembly": "hl.bfi a1, a2, 12, 19, ->a0",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/linx-qemu-tests.elf",
-      "elf_sha256": "6e4d51d08c2a346792ea004b7eba669bff3e02454010d7264c8d473c0b7084c7",
-      "form_id": "hl_bfi_48_8adfd476aacc",
+      "disassembly": "add a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "add_32_d04202886d0a",
       "form_key": {
-        "length_bits": 48,
-        "mask": "0xfe00707f000f",
-        "match": "0x204d000e"
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x5"
       },
       "max_level": "L3",
-      "mnemonic": "HL.BFI",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/obj/27_executable_maddw_bfi_mi.o",
-      "object_sha256": "231ea0e0955bacacd8269393cc5c14fc69038764eb685e1b23a4eaf91b92a185",
+      "mnemonic": "ADD",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
       "oracle": {
-        "expected": "0xffff0000000f0000",
+        "expected": "0x68ac",
         "kind": "exact_value",
-        "locator": "test_hl_bfi",
-        "source": "avs/qemu/tests/27_executable_maddw_bfi_mi.c"
+        "locator": "test_add",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
       },
-      "pc": "0x102e0",
+      "pc": "0x10286",
       "qemu_binary_verification": "local_binary_sha256",
-      "qemu_sha": "b4df5c31d06eaee04b602b4b6fd8b6f2c2592b4c",
-      "raw_bytes_le": "ce4c4da14100",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/run-evidence.json",
-      "suite": "executable_maddw_bfi_mi",
-      "symbol": "executable_hl_bfi",
-      "test_id": "0x00002902"
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "05814106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_add",
+      "test_id": "0x00002501"
     },
     {
-      "disassembly": "hl.miadd a1, a2, 344865, ->a0",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/linx-qemu-tests.elf",
-      "elf_sha256": "6e4d51d08c2a346792ea004b7eba669bff3e02454010d7264c8d473c0b7084c7",
-      "form_id": "hl_miadd_48_ec5127b6dfd6",
+      "disassembly": "and a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "and_32_b6a903a3ec94",
       "form_key": {
-        "length_bits": 48,
-        "mask": "0x707f000f",
-        "match": "0x4d000e"
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x2005"
       },
       "max_level": "L3",
-      "mnemonic": "HL.MIADD",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/obj/27_executable_maddw_bfi_mi.o",
-      "object_sha256": "231ea0e0955bacacd8269393cc5c14fc69038764eb685e1b23a4eaf91b92a185",
+      "mnemonic": "AND",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
       "oracle": {
-        "expected": "0x0128888889bb9752",
+        "expected": "0x00f0",
         "kind": "exact_value",
-        "locator": "test_hl_miadd",
-        "source": "avs/qemu/tests/27_executable_maddw_bfi_mi.c"
+        "locator": "test_and",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
       },
-      "pc": "0x10326",
+      "pc": "0x102b8",
       "qemu_binary_verification": "local_binary_sha256",
-      "qemu_sha": "b4df5c31d06eaee04b602b4b6fd8b6f2c2592b4c",
-      "raw_bytes_le": "6ea84d814142",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/run-evidence.json",
-      "suite": "executable_maddw_bfi_mi",
-      "symbol": "executable_hl_miadd",
-      "test_id": "0x00002903"
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "05a14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_and",
+      "test_id": "0x00002503"
     },
     {
-      "disassembly": "hl.misub a1, a2, 344865, ->a0",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/linx-qemu-tests.elf",
-      "elf_sha256": "6e4d51d08c2a346792ea004b7eba669bff3e02454010d7264c8d473c0b7084c7",
-      "form_id": "hl_misub_48_e9e4c7b23479",
+      "disassembly": "C.BSTART COND, 0x11032",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "dc6d2e11c1c1326557935540f2d866be97e552ebd657561d85c0ddd63d2b1483",
+      "form_id": "c_bstart_16_c4e238a9227a",
       "form_key": {
-        "length_bits": 48,
-        "mask": "0x707f000f",
-        "match": "0x104d000e"
+        "length_bits": 16,
+        "mask": "0xf",
+        "match": "0x4"
+      },
+      "max_level": "L3",
+      "mnemonic": "C.BSTART",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
+      "object_sha256": "a152bf833aaafa70ffc7dccecd6c2d15574c103278bb14c142d58b26b4824a18",
+      "oracle": {
+        "expected": "0x6655",
+        "kind": "exact_value",
+        "locator": "test_c_bstart_cond_paths",
+        "source": "avs/qemu/tests/14_callret.c"
+      },
+      "pc": "0x11022",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "8400",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "callret",
+      "symbol": "callret_tpl_c_bstart_cond_taken",
+      "test_id": "0x0000140f"
+    },
+    {
+      "disassembly": "C.BSTART.STD RET",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "dc6d2e11c1c1326557935540f2d866be97e552ebd657561d85c0ddd63d2b1483",
+      "form_id": "c_bstart_std_16_8b40f078c14a",
+      "form_key": {
+        "length_bits": 16,
+        "mask": "0xc7ff",
+        "match": "0x0"
+      },
+      "max_level": "L3",
+      "mnemonic": "C.BSTART.STD",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
+      "object_sha256": "a152bf833aaafa70ffc7dccecd6c2d15574c103278bb14c142d58b26b4824a18",
+      "oracle": {
+        "expected": "0x1234",
+        "kind": "exact_value",
+        "locator": "test_ret_error_trailer_returns_via_ra",
+        "source": "avs/qemu/tests/14_callret.c"
+      },
+      "pc": "0x10ffc",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "0038",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "callret",
+      "symbol": "callret_tpl_ret_error_trailer_success",
+      "test_id": "0x0000140d"
+    },
+    {
+      "disassembly": "cmp.eq a1, a1, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "cmp_eq_32_6af7c8f41300",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xf800707f",
+        "match": "0x45"
+      },
+      "max_level": "L3",
+      "mnemonic": "CMP.EQ",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x1",
+        "kind": "exact_value",
+        "locator": "test_cmp_eq",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x1033e",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "45813106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_cmp_eq",
+      "test_id": "0x00002609"
+    },
+    {
+      "disassembly": "cmp.ge a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "cmp_ge_32_d88e3a1cfff4",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xf800707f",
+        "match": "0x5045"
+      },
+      "max_level": "L3",
+      "mnemonic": "CMP.GE",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x0",
+        "kind": "exact_value",
+        "locator": "test_cmp_ge",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x103b4",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "45d14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_cmp_ge",
+      "test_id": "0x0000260d"
+    },
+    {
+      "disassembly": "cmp.geu a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "cmp_geu_32_0c002dc415ef",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xf800707f",
+        "match": "0x7045"
+      },
+      "max_level": "L3",
+      "mnemonic": "CMP.GEU",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x1",
+        "kind": "exact_value",
+        "locator": "test_cmp_geu",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x103c6",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "45f14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_cmp_geu",
+      "test_id": "0x0000260e"
+    },
+    {
+      "disassembly": "cmp.lt a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "cmp_lt_32_c0b8cc320f12",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xf800707f",
+        "match": "0x4045"
+      },
+      "max_level": "L3",
+      "mnemonic": "CMP.LT",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x1",
+        "kind": "exact_value",
+        "locator": "test_cmp_lt",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x10390",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "45c14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_cmp_lt",
+      "test_id": "0x0000260b"
+    },
+    {
+      "disassembly": "cmp.ltu a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "cmp_ltu_32_4377481baebc",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xf800707f",
+        "match": "0x6045"
+      },
+      "max_level": "L3",
+      "mnemonic": "CMP.LTU",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x0",
+        "kind": "exact_value",
+        "locator": "test_cmp_ltu",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x103a2",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "45e14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_cmp_ltu",
+      "test_id": "0x0000260c"
+    },
+    {
+      "disassembly": "cmp.ne a3, a1, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "cmp_ne_32_fc47fbb1a0de",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xf800707f",
+        "match": "0x1045"
+      },
+      "max_level": "L3",
+      "mnemonic": "CMP.NE",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x1",
+        "kind": "exact_value",
+        "locator": "test_cmp_ne",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x1037e",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "45913206",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_cmp_ne",
+      "test_id": "0x0000260a"
+    },
+    {
+      "disassembly": "csel a0, a2, a3, ->a1",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "csel_32_ba77cbad3c99",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x77"
+      },
+      "max_level": "L3",
+      "mnemonic": "CSEL",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "exact_value",
+        "locator": "test_csel",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x1040a",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "f7015216",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_csel",
+      "test_id": "0x0000260f"
+    },
+    {
+      "disassembly": "div a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "div_32_a6efe85f8662",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xfe00707f",
+        "match": "0x57"
+      },
+      "max_level": "L3",
+      "mnemonic": "DIV",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0xfffffffffffffff2",
+        "kind": "exact_value",
+        "locator": "test_div",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x102da",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "57814100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_div",
+      "test_id": "0x00002605"
+    },
+    {
+      "disassembly": "divu a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "divu_32_cfbc0d1760e4",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xfe00707f",
+        "match": "0x1057"
+      },
+      "max_level": "L3",
+      "mnemonic": "DIVU",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x0fffffffffffffff",
+        "kind": "exact_value",
+        "locator": "test_divu",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x102ee",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "57914100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_divu",
+      "test_id": "0x00002606"
+    },
+    {
+      "disassembly": "FENTRY [ra ~ ra], sp!, 16",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "dc6d2e11c1c1326557935540f2d866be97e552ebd657561d85c0ddd63d2b1483",
+      "form_id": "fentry_32_a47584ec13b6",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x41"
+      },
+      "max_level": "L3",
+      "mnemonic": "FENTRY",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
+      "object_sha256": "a152bf833aaafa70ffc7dccecd6c2d15574c103278bb14c142d58b26b4824a18",
+      "oracle": {
+        "expected": "0x22",
+        "kind": "exact_value",
+        "locator": "test_fret_stk_uses_stack_ra",
+        "source": "avs/qemu/tests/14_callret.c"
+      },
+      "pc": "0x10fb4",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "4100a504",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "callret",
+      "symbol": "callret_tpl_fret_stk_slot_redirect",
+      "test_id": "0x0000140b"
+    },
+    {
+      "disassembly": "FRET.RA [ra ~ ra], sp!, 16",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "dc6d2e11c1c1326557935540f2d866be97e552ebd657561d85c0ddd63d2b1483",
+      "form_id": "fret_ra_32_659c886221c1",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x2041"
+      },
+      "max_level": "L3",
+      "mnemonic": "FRET.RA",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
+      "object_sha256": "a152bf833aaafa70ffc7dccecd6c2d15574c103278bb14c142d58b26b4824a18",
+      "oracle": {
+        "expected": "0x33",
+        "kind": "exact_value",
+        "locator": "test_fret_ra_uses_snapshot_ra",
+        "source": "avs/qemu/tests/14_callret.c"
+      },
+      "pc": "0x10fee",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "4120a504",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "callret",
+      "symbol": "callret_tpl_fret_ra_slot_redirect",
+      "test_id": "0x0000140c"
+    },
+    {
+      "disassembly": "FRET.STK [ra ~ ra], sp!, 16",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "dc6d2e11c1c1326557935540f2d866be97e552ebd657561d85c0ddd63d2b1483",
+      "form_id": "fret_stk_32_4fe246bd8241",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x3041"
       },
       "max_level": "L3",
-      "mnemonic": "HL.MISUB",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/obj/27_executable_maddw_bfi_mi.o",
-      "object_sha256": "231ea0e0955bacacd8269393cc5c14fc69038764eb685e1b23a4eaf91b92a185",
+      "mnemonic": "FRET.STK",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
+      "object_sha256": "a152bf833aaafa70ffc7dccecd6c2d15574c103278bb14c142d58b26b4824a18",
       "oracle": {
-        "expected": "0x011e0246899c048c",
+        "expected": "0x22",
         "kind": "exact_value",
-        "locator": "test_hl_misub",
-        "source": "avs/qemu/tests/27_executable_maddw_bfi_mi.c"
+        "locator": "test_fret_stk_uses_stack_ra",
+        "source": "avs/qemu/tests/14_callret.c"
+      },
+      "pc": "0x10fca",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "4130a504",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "callret",
+      "symbol": "callret_tpl_fret_stk_slot_redirect",
+      "test_id": "0x0000140b"
+    },
+    {
+      "disassembly": "hl.ldip [a2, 0], ->a2, a3",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_ldip_48_60afa6423d39",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x3019001e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.LDIP",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_ldip",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x10600",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "1e2819320200",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_ldip",
+      "test_id": "0x0000220c"
+    },
+    {
+      "disassembly": "hl.lwui.po [a0, 4], ->a0, a1",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_lwui_po_48_09a75b628dc4",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x6019003e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.LWUI.PO",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_lwui_po",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x10282",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "3e1819611100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_lwui_po",
+      "test_id": "0x00002201"
+    },
+    {
+      "disassembly": "hl.lwui.pr [a0, 4], ->a0, a1",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_lwui_pr_48_32de19a508f0",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x6019002e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.LWUI.PR",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_lwui_pr",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x102bc",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "2e1819611100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_lwui_pr",
+      "test_id": "0x00002202"
+    },
+    {
+      "disassembly": "hl.lwui.upo [a0, 4], ->a0, a1",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_lwui_upo_48_33260eb06a2c",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x6029003e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.LWUI.UPO",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_lwui_upo",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x10302",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "3e1829614100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_lwui_upo",
+      "test_id": "0x00002203"
+    },
+    {
+      "disassembly": "hl.lwui.upr [a0, 4], ->a0, a1",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_lwui_upr_48_998a98c46469",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x6029002e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.LWUI.UPR",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_lwui_upr",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x1033c",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "2e1829614100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_lwui_upr",
+      "test_id": "0x00002204"
+    },
+    {
+      "disassembly": "hl.lwuip [a1, 0], ->a1, a2",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_lwuip_48_2a5d6d8f3b70",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x6019001e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.LWUIP",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_lwuip",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x104ec",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "1e2099e10100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_lwuip",
+      "test_id": "0x00002209"
+    },
+    {
+      "disassembly": "hl.sdip a0, a1, [a3, 0]",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_sdip_48_6d622cf167ca",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x3059001e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.SDIP",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_sdip",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x1068a",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "de0059305100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_sdip",
+      "test_id": "0x0000220d"
+    },
+    {
+      "disassembly": "hl.swi.po a0, [a2, 4], ->a3",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_swi_po_48_66a80d0fa7f5",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x2059003e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.SWI.PO",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_swi_po",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x103a2",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "3e2859204102",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_swi_po",
+      "test_id": "0x00002205"
+    },
+    {
+      "disassembly": "hl.swi.pr a1, [a0, 4], ->a2",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_swi_pr_48_68b9003e0421",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x2059002e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.SWI.PR",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_swi_pr",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x103f2",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "2e2059a02102",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_swi_pr",
+      "test_id": "0x00002206"
+    },
+    {
+      "disassembly": "hl.swi.upo a1, [a0, 4], ->a2",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_swi_upo_48_243d3c38cd1a",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x6059003e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.SWI.UPO",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_swi_upo",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x10442",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "3e2059e02108",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_swi_upo",
+      "test_id": "0x00002207"
+    },
+    {
+      "disassembly": "hl.swi.upr a0, [a2, 4], ->a3",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_swi_upr_48_15c2fb96aab0",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x6059002e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.SWI.UPR",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_swi_upr",
+        "source": "avs/qemu/tests/22_executable_memory.c"
       },
-      "pc": "0x1036c",
+      "pc": "0x1049e",
       "qemu_binary_verification": "local_binary_sha256",
-      "qemu_sha": "b4df5c31d06eaee04b602b4b6fd8b6f2c2592b4c",
-      "raw_bytes_le": "6ea84d914142",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/run-evidence.json",
-      "suite": "executable_maddw_bfi_mi",
-      "symbol": "executable_hl_misub",
-      "test_id": "0x00002904"
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "2e2859604108",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_swi_upr",
+      "test_id": "0x00002208"
+    },
+    {
+      "disassembly": "hl.swip a3, a0, [a2, 0]",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_swip_48_e2fca8cde001",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x2059001e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.SWIP",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_swip",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x10544",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "9e0059a04200",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_swip",
+      "test_id": "0x0000220a"
+    },
+    {
+      "disassembly": "hl.swip.u a3, a0, [a2, 8]",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "723f0049638abc190434c384c5ce49acc274fe96b87f16159d8ef2a3f26f1a28",
+      "form_id": "hl_swip_u_48_e2dc917c8505",
+      "form_key": {
+        "length_bits": 48,
+        "mask": "0x707f003f",
+        "match": "0x6059001e"
+      },
+      "max_level": "L3",
+      "mnemonic": "HL.SWIP.U",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/obj/22_executable_memory.o",
+      "object_sha256": "b9fe8055733047165dacce80640dd5165d5ba3e845d601c0d392713422434c4a",
+      "oracle": {
+        "expected": "0x3",
+        "kind": "architectural_state",
+        "locator": "test_hl_swip_u",
+        "source": "avs/qemu/tests/22_executable_memory.c"
+      },
+      "pc": "0x105a6",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "9e0059e04210",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-memory-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_memory",
+      "symbol": "executable_memory_hl_swip_u",
+      "test_id": "0x0000220b"
+    },
+    {
+      "disassembly": "j 6",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "dc6d2e11c1c1326557935540f2d866be97e552ebd657561d85c0ddd63d2b1483",
+      "form_id": "j_32_a303cf05af42",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x37"
+      },
+      "max_level": "L3",
+      "mnemonic": "J",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
+      "object_sha256": "a152bf833aaafa70ffc7dccecd6c2d15574c103278bb14c142d58b26b4824a18",
+      "oracle": {
+        "expected": "0x77",
+        "kind": "exact_value",
+        "locator": "test_j_isolated",
+        "source": "avs/qemu/tests/14_callret.c"
+      },
+      "pc": "0x1105a",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "37000300",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "callret",
+      "symbol": "callret_tpl_j_skip_poison",
+      "test_id": "0x00001410"
+    },
+    {
+      "disassembly": "L.BSTART.STD DIRECT, 24",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "dc6d2e11c1c1326557935540f2d866be97e552ebd657561d85c0ddd63d2b1483",
+      "form_id": "l_bstart_std_64_37e84068ce61",
+      "form_key": {
+        "length_bits": 64,
+        "mask": "0x7fff0000007f",
+        "match": "0x20010000000f"
+      },
+      "max_level": "L3",
+      "mnemonic": "L.BSTART.STD",
+      "object": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/obj/14_callret_templates.o",
+      "object_sha256": "a152bf833aaafa70ffc7dccecd6c2d15574c103278bb14c142d58b26b4824a18",
+      "oracle": {
+        "expected": "0x77",
+        "kind": "exact_value",
+        "locator": "test_l_bstart_direct_positive",
+        "source": "avs/qemu/tests/14_callret.c"
+      },
+      "pc": "0x11070",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "0f06000001200000",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/callret-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "callret",
+      "symbol": "callret_tpl_l_bstart_direct_positive",
+      "test_id": "0x00001411"
+    },
+    {
+      "disassembly": "lb [a1, a2], ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "lb_32_b718aa88e28f",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x9"
+      },
+      "max_level": "L3",
+      "mnemonic": "LB",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0xfffffffffffffffe",
+        "kind": "exact_value",
+        "locator": "test_lb",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x1035e",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "09814106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_lb",
+      "test_id": "0x00002509"
+    },
+    {
+      "disassembly": "lbu [a1, a2], ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "lbu_32_a9a58ab4ea22",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x4009"
+      },
+      "max_level": "L3",
+      "mnemonic": "LBU",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0xfe",
+        "kind": "exact_value",
+        "locator": "test_lbu",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x10284",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "09c14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_lbu",
+      "test_id": "0x00002601"
+    },
+    {
+      "disassembly": "ld [a1, a2], ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "ld_32_7c48838bc4e6",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x3009"
+      },
+      "max_level": "L3",
+      "mnemonic": "LD",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0x0123456789abcdef",
+        "kind": "exact_value",
+        "locator": "test_ld",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x103a6",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "09b14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_ld",
+      "test_id": "0x0000250c"
+    },
+    {
+      "disassembly": "lh [a1, a2], ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "lh_32_d0f04d7d7696",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x1009"
+      },
+      "max_level": "L3",
+      "mnemonic": "LH",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0xfffffffffffff234",
+        "kind": "exact_value",
+        "locator": "test_lh",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x10376",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "09914106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_lh",
+      "test_id": "0x0000250a"
+    },
+    {
+      "disassembly": "lhu [a1, a2], ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "lhu_32_730caf67ecd1",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x5009"
+      },
+      "max_level": "L3",
+      "mnemonic": "LHU",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0xabcd",
+        "kind": "exact_value",
+        "locator": "test_lhu",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x1029c",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "09d14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_lhu",
+      "test_id": "0x00002602"
+    },
+    {
+      "disassembly": "lr.d [a0, 0], ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "9f4c8b9ad623eb34b71a7ae53d73096266e127ab85fd27fadf3cd4d18fce41a2",
+      "form_id": "lr_d_32_84d21a553dc1",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xf000707f",
+        "match": "0x3000000b"
+      },
+      "max_level": "L3",
+      "mnemonic": "LR.D",
+      "object": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.o",
+      "object_sha256": "ae567cb616f141cfcbe80841346b3e887bc12e60804d0a8da71fca021f7a16cf",
+      "oracle": {
+        "expected": "0x0123456789abcdef",
+        "kind": "exact_value",
+        "locator": "test_lr_d_nonzero_srczero",
+        "source": "avs/qemu/tests/07_atomic.c"
+      },
+      "pc": "0x1152e",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "0b011131",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "atomic",
+      "symbol": "atomic_lr_d_nonzero_srczero",
+      "test_id": "0x00007163"
+    },
+    {
+      "disassembly": "lr.w [a0, 0], ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "9f4c8b9ad623eb34b71a7ae53d73096266e127ab85fd27fadf3cd4d18fce41a2",
+      "form_id": "lr_w_32_efecc735bb75",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xf000707f",
+        "match": "0x2000000b"
+      },
+      "max_level": "L3",
+      "mnemonic": "LR.W",
+      "object": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/obj/07_atomic_lr_srczero.o",
+      "object_sha256": "ae567cb616f141cfcbe80841346b3e887bc12e60804d0a8da71fca021f7a16cf",
+      "oracle": {
+        "expected": "0x1234abcd",
+        "kind": "exact_value",
+        "locator": "test_lr_w_nonzero_srczero",
+        "source": "avs/qemu/tests/07_atomic.c"
+      },
+      "pc": "0x1151a",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "0b01f121",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "atomic",
+      "symbol": "atomic_lr_w_nonzero_srczero",
+      "test_id": "0x00007162"
+    },
+    {
+      "disassembly": "lw [a1, a2], ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "lw_32_3a77ffafcb34",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x2009"
+      },
+      "max_level": "L3",
+      "mnemonic": "LW",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0xfffffffff23480fe",
+        "kind": "exact_value",
+        "locator": "test_lw",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x1038e",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "09a14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_lw",
+      "test_id": "0x0000250b"
+    },
+    {
+      "disassembly": "lwu [a1, a2], ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "lwu_32_678935925636",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x6009"
+      },
+      "max_level": "L3",
+      "mnemonic": "LWU",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x89abcdef",
+        "kind": "exact_value",
+        "locator": "test_lwu",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x102b4",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "09e14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_lwu",
+      "test_id": "0x00002603"
+    },
+    {
+      "disassembly": "mul a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "mul_32_9f2affd8efb8",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xfe00707f",
+        "match": "0x47"
+      },
+      "max_level": "L3",
+      "mnemonic": "MUL",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0xffffffffffffffa5",
+        "kind": "exact_value",
+        "locator": "test_mul",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x102c6",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "47814100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_mul",
+      "test_id": "0x00002604"
+    },
+    {
+      "disassembly": "or a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "or_32_a7fb80e78831",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x3005"
+      },
+      "max_level": "L3",
+      "mnemonic": "OR",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0xfff0",
+        "kind": "exact_value",
+        "locator": "test_or",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x102d0",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "05b14106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_or",
+      "test_id": "0x00002504"
+    },
+    {
+      "disassembly": "rem a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "rem_32_0abbd6a3b865",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xfe00707f",
+        "match": "0x4057"
+      },
+      "max_level": "L3",
+      "mnemonic": "REM",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0xfffffffffffffffe",
+        "kind": "exact_value",
+        "locator": "test_rem",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x10302",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "57c14100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_rem",
+      "test_id": "0x00002607"
+    },
+    {
+      "disassembly": "remu a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "591cbaf6c49374f26088b968364f136ab781f4c526b36d41fc0c5d4a61fa0990",
+      "form_id": "remu_32_d7a5d1ebbbf5",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xfe00707f",
+        "match": "0x5057"
+      },
+      "max_level": "L3",
+      "mnemonic": "REMU",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/obj/24_executable_integer.o",
+      "object_sha256": "834d3b03ea77c493b5cad17cdedc48ddb2b01ebe364f19f96587e4c0146f089f",
+      "oracle": {
+        "expected": "0x2",
+        "kind": "exact_value",
+        "locator": "test_remu",
+        "source": "avs/qemu/tests/24_executable_integer.c"
+      },
+      "pc": "0x10316",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "57d14100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_integer",
+      "symbol": "executable_integer_remu",
+      "test_id": "0x00002608"
+    },
+    {
+      "disassembly": "sb a1, [a0, a2]",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "sb_32_43c106ae3749",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x7fff",
+        "match": "0x49"
+      },
+      "max_level": "L3",
+      "mnemonic": "SB",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0x7",
+        "kind": "architectural_state",
+        "locator": "test_sb",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x103de",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "4900411e",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_sb",
+      "test_id": "0x0000250d"
+    },
+    {
+      "disassembly": "sd a1, [a2, a3<<3]",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "sd_32_9dbc40328653",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x7fff",
+        "match": "0x3049"
+      },
+      "max_level": "L3",
+      "mnemonic": "SD",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0x7",
+        "kind": "architectural_state",
+        "locator": "test_sd",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x10574",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "4930521e",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_sd",
+      "test_id": "0x00002510"
+    },
+    {
+      "disassembly": "sh a1, [a0, a2<<1]",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "sh_32_bc7d4a7dea28",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x7fff",
+        "match": "0x1049"
+      },
+      "max_level": "L3",
+      "mnemonic": "SH",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0xf",
+        "kind": "architectural_state",
+        "locator": "test_sh",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x10456",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "4910411e",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_sh",
+      "test_id": "0x0000250e"
+    },
+    {
+      "disassembly": "sll a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "sll_32_a100b8961e21",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xfe00707f",
+        "match": "0x7005"
+      },
+      "max_level": "L3",
+      "mnemonic": "SLL",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0x1230",
+        "kind": "exact_value",
+        "locator": "test_sll",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x102fe",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "05f14100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_sll",
+      "test_id": "0x00002506"
+    },
+    {
+      "disassembly": "sra a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "sra_32_ba03eea6386b",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xfe00707f",
+        "match": "0x6005"
+      },
+      "max_level": "L3",
+      "mnemonic": "SRA",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0xfffffffffffffff0",
+        "kind": "exact_value",
+        "locator": "test_sra",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x10346",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "05e14100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_sra",
+      "test_id": "0x00002508"
+    },
+    {
+      "disassembly": "srl a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "srl_32_5cfca42c59f3",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0xfe00707f",
+        "match": "0x5005"
+      },
+      "max_level": "L3",
+      "mnemonic": "SRL",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0x0800000000000000",
+        "kind": "exact_value",
+        "locator": "test_srl",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x10330",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "05d14100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_srl",
+      "test_id": "0x00002507"
+    },
+    {
+      "disassembly": "sub a1, a2, ->a0",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "sub_32_af383d4a2b42",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x707f",
+        "match": "0x1005"
+      },
+      "max_level": "L3",
+      "mnemonic": "SUB",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0x8642",
+        "kind": "exact_value",
+        "locator": "test_sub",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x102a0",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "05914106",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_sub",
+      "test_id": "0x00002502"
+    },
+    {
+      "disassembly": "sw a0, [a2, a3<<2]",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "ed2a6f4065fcd07c1d6e8c107a2dcd023135de7f883495ac70518b831dd5b539",
+      "form_id": "sw_32_28ad317b1b41",
+      "form_key": {
+        "length_bits": 32,
+        "mask": "0x7fff",
+        "match": "0x2049"
+      },
+      "max_level": "L3",
+      "mnemonic": "SW",
+      "object": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/obj/23_executable_scalar.o",
+      "object_sha256": "2ab67b969209d3f18016722c825eccda965e95a26e0e84bd8d9dd46bce5d78a4",
+      "oracle": {
+        "expected": "0x7",
+        "kind": "architectural_state",
+        "locator": "test_sw",
+        "source": "avs/qemu/tests/23_executable_scalar.c"
+      },
+      "pc": "0x104e8",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "49205216",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-scalar-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "executable_scalar",
+      "symbol": "executable_scalar_sw",
+      "test_id": "0x0000250f"
+    },
+    {
+      "disassembly": "v.add vt#1, vu#1.sw, ->vt",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "1c28a1d7351c31376e11c3d34c153a3fa33be9e122e70c65912839eb05580b02",
+      "form_id": "v_add_64_394294cc5946",
+      "form_key": {
+        "length_bits": 64,
+        "mask": "0x707ffe00707f",
+        "match": "0x50000007f"
+      },
+      "max_level": "L3",
+      "mnemonic": "V.ADD",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
+      "object_sha256": "c9cd9482f6db396aef8f0527132d3c981914a975fe6a6e65ce04369ba455c871",
+      "oracle": {
+        "expected": "0x75",
+        "kind": "exact_value",
+        "locator": "test_v_add_evidence",
+        "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c"
+      },
+      "pc": "0x10288",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "7f02520005801000",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "v057_vector_ops",
+      "symbol": "__linx_v057_ops_add_sub_body",
+      "test_id": "0x00001370"
+    },
+    {
+      "disassembly": "v.cmp.lt lc0, ri1, ->vt",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "1c28a1d7351c31376e11c3d34c153a3fa33be9e122e70c65912839eb05580b02",
+      "form_id": "v_cmp_lt_64_3ef2162a77ba",
+      "form_key": {
+        "length_bits": 64,
+        "mask": "0xfe00707ffe00707f",
+        "match": "0x40450000007f"
+      },
+      "max_level": "L3",
+      "mnemonic": "V.CMP.LT",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
+      "object_sha256": "c9cd9482f6db396aef8f0527132d3c981914a975fe6a6e65ce04369ba455c871",
+      "oracle": {
+        "expected": "0x1",
+        "kind": "exact_value",
+        "locator": "test_v_mixed_scalar_vector_predicate",
+        "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c"
+      },
+      "pc": "0x10324",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "7f82110045401000",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "v057_vector_ops",
+      "symbol": "__linx_v057_ops_mixed_pred_body",
+      "test_id": "0x00001320"
+    },
+    {
+      "disassembly": "v.fadd vt#1, ri2, ->vt",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "1c28a1d7351c31376e11c3d34c153a3fa33be9e122e70c65912839eb05580b02",
+      "form_id": "v_fadd_64_c5c08b2ac830",
+      "form_key": {
+        "length_bits": 64,
+        "mask": "0xfe00707ffe00707f",
+        "match": "0x4b0000007f"
+      },
+      "max_level": "L3",
+      "mnemonic": "V.FADD",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
+      "object_sha256": "c9cd9482f6db396aef8f0527132d3c981914a975fe6a6e65ce04369ba455c871",
+      "oracle": {
+        "expected": "0x40000000",
+        "kind": "exact_value",
+        "locator": "test_v_fadd_evidence",
+        "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c"
+      },
+      "pc": "0x102b8",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "7f0212004b802000",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "v057_vector_ops",
+      "symbol": "__linx_v057_ops_float_body",
+      "test_id": "0x00001374"
+    },
+    {
+      "disassembly": "v.fmul vt#1, ri3, ->vt",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "1c28a1d7351c31376e11c3d34c153a3fa33be9e122e70c65912839eb05580b02",
+      "form_id": "v_fmul_64_3e2b1576cbfe",
+      "form_key": {
+        "length_bits": 64,
+        "mask": "0xfe00707ffe00707f",
+        "match": "0x204b0000007f"
+      },
+      "max_level": "L3",
+      "mnemonic": "V.FMUL",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
+      "object_sha256": "c9cd9482f6db396aef8f0527132d3c981914a975fe6a6e65ce04369ba455c871",
+      "oracle": {
+        "expected": "0x40200000",
+        "kind": "exact_value",
+        "locator": "test_v_fmul_evidence",
+        "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c"
+      },
+      "pc": "0x102c0",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "7f0212004ba03000",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "v057_vector_ops",
+      "symbol": "__linx_v057_ops_float_body",
+      "test_id": "0x00001375"
+    },
+    {
+      "disassembly": "v.lw.brg [ri0, lc0<<2, zero], ->vt",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "1c28a1d7351c31376e11c3d34c153a3fa33be9e122e70c65912839eb05580b02",
+      "form_id": "v_lw_brg_64_6163b7a621fc",
+      "form_key": {
+        "length_bits": 64,
+        "mask": "0x600707ffe00207f",
+        "match": "0x20090000207f"
+      },
+      "max_level": "L3",
+      "mnemonic": "V.LW.BRG",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
+      "object_sha256": "c9cd9482f6db396aef8f0527132d3c981914a975fe6a6e65ce04369ba455c871",
+      "oracle": {
+        "expected": "0x79",
+        "kind": "exact_value",
+        "locator": "test_v_lw_brg_evidence",
+        "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c"
+      },
+      "pc": "0x10278",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "7fa2000009200000",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "v057_vector_ops",
+      "symbol": "__linx_v057_ops_add_sub_body",
+      "test_id": "0x00001372"
+    },
+    {
+      "disassembly": "v.sub vt#2, vu#1.sw, ->vt",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "1c28a1d7351c31376e11c3d34c153a3fa33be9e122e70c65912839eb05580b02",
+      "form_id": "v_sub_64_3c88cf0158f8",
+      "form_key": {
+        "length_bits": 64,
+        "mask": "0x707ffe00707f",
+        "match": "0x10050000007f"
+      },
+      "max_level": "L3",
+      "mnemonic": "V.SUB",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
+      "object_sha256": "c9cd9482f6db396aef8f0527132d3c981914a975fe6a6e65ce04369ba455c871",
+      "oracle": {
+        "expected": "0x53",
+        "kind": "exact_value",
+        "locator": "test_v_sub_evidence",
+        "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c"
+      },
+      "pc": "0x10298",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "7f02520005101100",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "suite": "v057_vector_ops",
+      "symbol": "__linx_v057_ops_add_sub_body",
+      "test_id": "0x00001371"
+    },
+    {
+      "disassembly": "v.sw.brg vt#1, [ri2, lc0<<2, zero<<2]",
+      "elf": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/linx-qemu-tests.elf",
+      "elf_sha256": "1c28a1d7351c31376e11c3d34c153a3fa33be9e122e70c65912839eb05580b02",
+      "form_id": "v_sw_brg_64_d78368c708bd",
+      "form_key": {
+        "length_bits": 64,
+        "mask": "0x6007fff0600207f",
+        "match": "0x20490000207f"
+      },
+      "max_level": "L3",
+      "mnemonic": "V.SW.BRG",
+      "object": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/obj/13_v057_vector_ops_matrix.o",
+      "object_sha256": "c9cd9482f6db396aef8f0527132d3c981914a975fe6a6e65ce04369ba455c871",
+      "oracle": {
+        "expected": "0x55",
+        "kind": "exact_value",
+        "locator": "test_v_sw_brg_evidence",
+        "source": "avs/qemu/tests/13_v057_vector_ops_matrix.c"
+      },
+      "pc": "0x10290",
+      "qemu_binary_verification": "local_binary_sha256",
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "raw_bytes_le": "7fa0002049200108",
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+      "test_id": "0x00001373"
+    },
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+      "oracle_verdict": "PASS",
+      "pass_marker": {
+        "kind": "uart_success_marker",
+        "value": "TEST SUITE COMPLETE"
       },
-      "pc": "0x1029c",
-      "qemu_binary_verification": "local_binary_sha256",
-      "qemu_sha": "b4df5c31d06eaee04b602b4b6fd8b6f2c2592b4c",
-      "raw_bytes_le": "47f15120",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/run-evidence.json",
-      "suite": "executable_maddw_bfi_mi",
-      "symbol": "executable_maddw",
-      "test_id": "0x00002901"
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "stalled": false,
+      "status": "PASS",
+      "suite": "executable_integer",
+      "test_contract": "valid",
+      "test_id": "0x00002607",
+      "timed_out": false,
+      "timeout_after_fail": false
     },
     {
-      "disassembly": "setc.andi a0, 4096",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/linx-qemu-tests.elf",
-      "elf_sha256": "f8395d4e9ccc0d75ef7d0518a58611a312ca6bb1e80412aa54ac5e3cd2e83b95",
-      "form_id": "setc_andi_32_32fe61c0559b",
-      "form_key": {
-        "length_bits": 32,
-        "mask": "0x707f",
-        "match": "0x2075"
-      },
-      "max_level": "L3",
-      "mnemonic": "SETC.ANDI",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/obj/26_executable_setc_imm.o",
-      "object_sha256": "a6585eccc45227b99115388765042ad4bcf018c2483beec48d26e4afecb04534",
-      "oracle": {
-        "expected": "0x3",
-        "kind": "exact_value",
-        "locator": "test_setc_andi",
-        "source": "avs/qemu/tests/26_executable_setc_imm.c"
+      "exit_code": 0,
+      "failure": null,
+      "failure_attribution": "none",
+      "oracle_verdict": "PASS",
+      "pass_marker": {
+        "kind": "uart_success_marker",
+        "value": "TEST SUITE COMPLETE"
       },
-      "pc": "0x1028c",
-      "qemu_binary_verification": "local_binary_sha256",
-      "qemu_sha": "b4df5c31d06eaee04b602b4b6fd8b6f2c2592b4c",
-      "raw_bytes_le": "75261100",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
-      "suite": "executable_setc_imm",
-      "symbol": "executable_setc_imm_setc_andi",
-      "test_id": "0x00002801"
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "stalled": false,
+      "status": "PASS",
+      "suite": "executable_integer",
+      "test_contract": "valid",
+      "test_id": "0x00002608",
+      "timed_out": false,
+      "timeout_after_fail": false
     },
     {
-      "disassembly": "setc.ori a0, 4096",
-      "elf": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/linx-qemu-tests.elf",
-      "elf_sha256": "f8395d4e9ccc0d75ef7d0518a58611a312ca6bb1e80412aa54ac5e3cd2e83b95",
-      "form_id": "setc_ori_32_183dc15fad54",
-      "form_key": {
-        "length_bits": 32,
-        "mask": "0x707f",
-        "match": "0x3075"
+      "exit_code": 0,
+      "failure": null,
+      "failure_attribution": "none",
+      "oracle_verdict": "PASS",
+      "pass_marker": {
+        "kind": "uart_success_marker",
+        "value": "TEST SUITE COMPLETE"
       },
-      "max_level": "L3",
-      "mnemonic": "SETC.ORI",
-      "object": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/obj/26_executable_setc_imm.o",
-      "object_sha256": "a6585eccc45227b99115388765042ad4bcf018c2483beec48d26e4afecb04534",
-      "oracle": {
-        "expected": "0x3",
-        "kind": "exact_value",
-        "locator": "test_setc_ori",
-        "source": "avs/qemu/tests/26_executable_setc_imm.c"
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "stalled": false,
+      "status": "PASS",
+      "suite": "executable_integer",
+      "test_contract": "valid",
+      "test_id": "0x00002609",
+      "timed_out": false,
+      "timeout_after_fail": false
+    },
+    {
+      "exit_code": 0,
+      "failure": null,
+      "failure_attribution": "none",
+      "oracle_verdict": "PASS",
+      "pass_marker": {
+        "kind": "uart_success_marker",
+        "value": "TEST SUITE COMPLETE"
       },
-      "pc": "0x10300",
-      "qemu_binary_verification": "local_binary_sha256",
-      "qemu_sha": "b4df5c31d06eaee04b602b4b6fd8b6f2c2592b4c",
-      "raw_bytes_le": "75361100",
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
-      "suite": "executable_setc_imm",
-      "symbol": "executable_setc_imm_setc_ori",
-      "test_id": "0x00002802"
-    }
-  ],
-  "claim": "per_form_qemu_executable_coverage",
-  "evidence": {
-    "L2": {
-      "availability": "available",
-      "claim": "runtime_execution",
-      "form_count": 14,
-      "mnemonic_count": 14
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
+      "stalled": false,
+      "status": "PASS",
+      "suite": "executable_integer",
+      "test_contract": "valid",
+      "test_id": "0x0000260a",
+      "timed_out": false,
+      "timeout_after_fail": false
     },
-    "L3": {
-      "availability": "available",
-      "claim": "semantic_oracle",
-      "form_count": 14,
-      "mnemonic_count": 14
-    }
-  },
-  "execution_observations": [
     {
       "exit_code": 0,
       "failure": null,
@@ -432,12 +2576,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "executable_integer",
       "test_contract": "valid",
-      "test_id": "0x00002801",
+      "test_id": "0x0000260b",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -450,12 +2594,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "executable_integer",
       "test_contract": "valid",
-      "test_id": "0x00002802",
+      "test_id": "0x0000260c",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -468,12 +2612,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "executable_integer",
       "test_contract": "valid",
-      "test_id": "0x00002803",
+      "test_id": "0x0000260d",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -486,12 +2630,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "executable_integer",
       "test_contract": "valid",
-      "test_id": "0x00002804",
+      "test_id": "0x0000260e",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -504,12 +2648,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-integer-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "executable_integer",
       "test_contract": "valid",
-      "test_id": "0x00002805",
+      "test_id": "0x0000260f",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -522,12 +2666,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "v057_vector_ops",
       "test_contract": "valid",
-      "test_id": "0x00002806",
+      "test_id": "0x00001372",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -540,12 +2684,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "v057_vector_ops",
       "test_contract": "valid",
-      "test_id": "0x00002807",
+      "test_id": "0x00001370",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -558,12 +2702,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "v057_vector_ops",
       "test_contract": "valid",
-      "test_id": "0x00002808",
+      "test_id": "0x00001373",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -576,12 +2720,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "v057_vector_ops",
       "test_contract": "valid",
-      "test_id": "0x00002809",
+      "test_id": "0x00001371",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -594,12 +2738,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-setc-imm-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_setc_imm",
+      "suite": "v057_vector_ops",
       "test_contract": "valid",
-      "test_id": "0x0000280a",
+      "test_id": "0x00001374",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -612,12 +2756,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_maddw_bfi_mi",
+      "suite": "v057_vector_ops",
       "test_contract": "valid",
-      "test_id": "0x00002901",
+      "test_id": "0x00001375",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -630,12 +2774,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/v057-vector-ops-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_maddw_bfi_mi",
+      "suite": "v057_vector_ops",
       "test_contract": "valid",
-      "test_id": "0x00002902",
+      "test_id": "0x00001320",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -648,12 +2792,12 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_maddw_bfi_mi",
+      "suite": "atomic",
       "test_contract": "valid",
-      "test_id": "0x00002903",
+      "test_id": "0x00007162",
       "timed_out": false,
       "timeout_after_fail": false
     },
@@ -666,20 +2810,37 @@
         "kind": "uart_success_marker",
         "value": "TEST SUITE COMPLETE"
       },
-      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/executable-maddw-bfi-mi-b4df5c31-clean-20260725-r2/run-evidence.json",
+      "run_evidence": "docs/bringup/gates/evidence/qemu-executable/atomic-lr-srczero-v0571-cfc253e8-20260802-r2/run-evidence.json",
       "stalled": false,
       "status": "PASS",
-      "suite": "executable_maddw_bfi_mi",
+      "suite": "atomic",
       "test_contract": "valid",
-      "test_id": "0x00002904",
+      "test_id": "0x00007163",
       "timed_out": false,
       "timeout_after_fail": false
+    },
+    {
+      "failure": {
+        "actual": "0x0000000000000011",
+        "expected": "0x0000000000000053",
+        "test_id": "0x00001321"
+      },
+      "failure_attribution": "test_contract",
+      "oracle_verdict": "FAIL",
+      "qemu_attribution": false,
+      "review_note": "Historical first-red evidence. The AVS source used invalid VT/VU lifetime and relative-index semantics; the corrected source and authored B.IOR binding now pass 0x1300, 0x1310, and 0x1320.",
+      "status": "FAIL",
+      "suite": "v057_vector_ops",
+      "test_contract": "invalid",
+      "test_id": "0x00001321",
+      "timed_out": true,
+      "timeout_after_fail": true
     }
   ],
-  "generated_at_utc": "2026-07-25T08:30:24Z",
+  "generated_at_utc": "2026-08-02T12:51:46Z",
   "inputs": {
-    "manifest": "avs/qemu/qemu_executable_b4df5c31_clean_manifest.json.refresh-candidate",
-    "qemu_sha": "b4df5c31d06eaee04b602b4b6fd8b6f2c2592b4c",
+    "manifest": "avs/qemu/qemu_executable_coverage_manifest.json",
+    "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
     "spec": "isa/v0.57/linxisa-v0.57.json"
   },
   "policy": {
diff --git a/docs/bringup/gates/qemu_executable_coverage_latest.md b/docs/bringup/gates/qemu_executable_coverage_latest.md
index 4fb8cc51..c0e4b4a7 100644
--- a/docs/bringup/gates/qemu_executable_coverage_latest.md
+++ b/docs/bringup/gates/qemu_executable_coverage_latest.md
@@ -1,6 +1,6 @@
 # QEMU Executable Coverage Ledger
 
-Generated: `2026-07-25T08:30:24Z`
+Generated: `2026-08-02T12:51:46Z`
 
 This ledger counts only per-form evidence bound to golden identity, bytes, test ID,
 artifacts, QEMU SHA, a test-specific terminal PASS, and an oracle. Suite exit 0 and stdout alone do not count.
@@ -9,27 +9,73 @@ artifacts, QEMU SHA, a test-specific terminal PASS, and an oracle. Suite exit 0
 
 | Level | Availability | Forms | Mnemonics |
 | --- | --- | ---: | ---: |
-| L2 | `available` | 14 | 14 |
-| L3 | `available` | 14 | 14 |
+| L2 | `available` | 60 | 60 |
+| L3 | `available` | 60 | 60 |
 
 ## Admitted Forms
 
 | Form | Suite / Test | Level | Oracle | Bytes |
 | --- | --- | --- | --- | --- |
-| `hl_bfi_48_8adfd476aacc` | `executable_maddw_bfi_mi / 0x00002902` | `L3` | `exact_value` | `ce4c4da14100` |
-| `hl_miadd_48_ec5127b6dfd6` | `executable_maddw_bfi_mi / 0x00002903` | `L3` | `exact_value` | `6ea84d814142` |
-| `hl_misub_48_e9e4c7b23479` | `executable_maddw_bfi_mi / 0x00002904` | `L3` | `exact_value` | `6ea84d914142` |
-| `hl_setc_andi_48_f27796612fb3` | `executable_setc_imm / 0x00002803` | `L3` | `exact_value` | `2e01f5225134` |
-| `hl_setc_eqi_48_0fe891fb0890` | `executable_setc_imm / 0x00002804` | `L3` | `exact_value` | `2e01f5025134` |
-| `hl_setc_gei_48_9563d6395d06` | `executable_setc_imm / 0x00002805` | `L3` | `exact_value` | `defef552b1cb` |
-| `hl_setc_geui_48_2390319baf54` | `executable_setc_imm / 0x00002806` | `L3` | `exact_value` | `2e01f5725134` |
-| `hl_setc_lti_48_ad4ffebe877c` | `executable_setc_imm / 0x00002807` | `L3` | `exact_value` | `defef542b1cb` |
-| `hl_setc_ltui_48_cb7a12ba6ead` | `executable_setc_imm / 0x00002808` | `L3` | `exact_value` | `2e01f5625134` |
-| `hl_setc_nei_48_f0bcf6586274` | `executable_setc_imm / 0x00002809` | `L3` | `exact_value` | `defef512b1cb` |
-| `hl_setc_ori_48_137bce8aeb04` | `executable_setc_imm / 0x0000280a` | `L3` | `exact_value` | `2e01f5325134` |
-| `maddw_32_9f922b15e674` | `executable_maddw_bfi_mi / 0x00002901` | `L3` | `exact_value` | `47f15120` |
-| `setc_andi_32_32fe61c0559b` | `executable_setc_imm / 0x00002801` | `L3` | `exact_value` | `75261100` |
-| `setc_ori_32_183dc15fad54` | `executable_setc_imm / 0x00002802` | `L3` | `exact_value` | `75361100` |
+| `add_32_d04202886d0a` | `executable_scalar / 0x00002501` | `L3` | `exact_value` | `05814106` |
+| `and_32_b6a903a3ec94` | `executable_scalar / 0x00002503` | `L3` | `exact_value` | `05a14106` |
+| `c_bstart_16_c4e238a9227a` | `callret / 0x0000140f` | `L3` | `exact_value` | `8400` |
+| `c_bstart_std_16_8b40f078c14a` | `callret / 0x0000140d` | `L3` | `exact_value` | `0038` |
+| `cmp_eq_32_6af7c8f41300` | `executable_integer / 0x00002609` | `L3` | `exact_value` | `45813106` |
+| `cmp_ge_32_d88e3a1cfff4` | `executable_integer / 0x0000260d` | `L3` | `exact_value` | `45d14106` |
+| `cmp_geu_32_0c002dc415ef` | `executable_integer / 0x0000260e` | `L3` | `exact_value` | `45f14106` |
+| `cmp_lt_32_c0b8cc320f12` | `executable_integer / 0x0000260b` | `L3` | `exact_value` | `45c14106` |
+| `cmp_ltu_32_4377481baebc` | `executable_integer / 0x0000260c` | `L3` | `exact_value` | `45e14106` |
+| `cmp_ne_32_fc47fbb1a0de` | `executable_integer / 0x0000260a` | `L3` | `exact_value` | `45913206` |
+| `csel_32_ba77cbad3c99` | `executable_integer / 0x0000260f` | `L3` | `exact_value` | `f7015216` |
+| `div_32_a6efe85f8662` | `executable_integer / 0x00002605` | `L3` | `exact_value` | `57814100` |
+| `divu_32_cfbc0d1760e4` | `executable_integer / 0x00002606` | `L3` | `exact_value` | `57914100` |
+| `fentry_32_a47584ec13b6` | `callret / 0x0000140b` | `L3` | `exact_value` | `4100a504` |
+| `fret_ra_32_659c886221c1` | `callret / 0x0000140c` | `L3` | `exact_value` | `4120a504` |
+| `fret_stk_32_4fe246bd8241` | `callret / 0x0000140b` | `L3` | `exact_value` | `4130a504` |
+| `hl_ldip_48_60afa6423d39` | `executable_memory / 0x0000220c` | `L3` | `architectural_state` | `1e2819320200` |
+| `hl_lwui_po_48_09a75b628dc4` | `executable_memory / 0x00002201` | `L3` | `architectural_state` | `3e1819611100` |
+| `hl_lwui_pr_48_32de19a508f0` | `executable_memory / 0x00002202` | `L3` | `architectural_state` | `2e1819611100` |
+| `hl_lwui_upo_48_33260eb06a2c` | `executable_memory / 0x00002203` | `L3` | `architectural_state` | `3e1829614100` |
+| `hl_lwui_upr_48_998a98c46469` | `executable_memory / 0x00002204` | `L3` | `architectural_state` | `2e1829614100` |
+| `hl_lwuip_48_2a5d6d8f3b70` | `executable_memory / 0x00002209` | `L3` | `architectural_state` | `1e2099e10100` |
+| `hl_sdip_48_6d622cf167ca` | `executable_memory / 0x0000220d` | `L3` | `architectural_state` | `de0059305100` |
+| `hl_swi_po_48_66a80d0fa7f5` | `executable_memory / 0x00002205` | `L3` | `architectural_state` | `3e2859204102` |
+| `hl_swi_pr_48_68b9003e0421` | `executable_memory / 0x00002206` | `L3` | `architectural_state` | `2e2059a02102` |
+| `hl_swi_upo_48_243d3c38cd1a` | `executable_memory / 0x00002207` | `L3` | `architectural_state` | `3e2059e02108` |
+| `hl_swi_upr_48_15c2fb96aab0` | `executable_memory / 0x00002208` | `L3` | `architectural_state` | `2e2859604108` |
+| `hl_swip_48_e2fca8cde001` | `executable_memory / 0x0000220a` | `L3` | `architectural_state` | `9e0059a04200` |
+| `hl_swip_u_48_e2dc917c8505` | `executable_memory / 0x0000220b` | `L3` | `architectural_state` | `9e0059e04210` |
+| `j_32_a303cf05af42` | `callret / 0x00001410` | `L3` | `exact_value` | `37000300` |
+| `l_bstart_std_64_37e84068ce61` | `callret / 0x00001411` | `L3` | `exact_value` | `0f06000001200000` |
+| `lb_32_b718aa88e28f` | `executable_scalar / 0x00002509` | `L3` | `exact_value` | `09814106` |
+| `lbu_32_a9a58ab4ea22` | `executable_integer / 0x00002601` | `L3` | `exact_value` | `09c14106` |
+| `ld_32_7c48838bc4e6` | `executable_scalar / 0x0000250c` | `L3` | `exact_value` | `09b14106` |
+| `lh_32_d0f04d7d7696` | `executable_scalar / 0x0000250a` | `L3` | `exact_value` | `09914106` |
+| `lhu_32_730caf67ecd1` | `executable_integer / 0x00002602` | `L3` | `exact_value` | `09d14106` |
+| `lr_d_32_84d21a553dc1` | `atomic / 0x00007163` | `L3` | `exact_value` | `0b011131` |
+| `lr_w_32_efecc735bb75` | `atomic / 0x00007162` | `L3` | `exact_value` | `0b01f121` |
+| `lw_32_3a77ffafcb34` | `executable_scalar / 0x0000250b` | `L3` | `exact_value` | `09a14106` |
+| `lwu_32_678935925636` | `executable_integer / 0x00002603` | `L3` | `exact_value` | `09e14106` |
+| `mul_32_9f2affd8efb8` | `executable_integer / 0x00002604` | `L3` | `exact_value` | `47814100` |
+| `or_32_a7fb80e78831` | `executable_scalar / 0x00002504` | `L3` | `exact_value` | `05b14106` |
+| `rem_32_0abbd6a3b865` | `executable_integer / 0x00002607` | `L3` | `exact_value` | `57c14100` |
+| `remu_32_d7a5d1ebbbf5` | `executable_integer / 0x00002608` | `L3` | `exact_value` | `57d14100` |
+| `sb_32_43c106ae3749` | `executable_scalar / 0x0000250d` | `L3` | `architectural_state` | `4900411e` |
+| `sd_32_9dbc40328653` | `executable_scalar / 0x00002510` | `L3` | `architectural_state` | `4930521e` |
+| `sh_32_bc7d4a7dea28` | `executable_scalar / 0x0000250e` | `L3` | `architectural_state` | `4910411e` |
+| `sll_32_a100b8961e21` | `executable_scalar / 0x00002506` | `L3` | `exact_value` | `05f14100` |
+| `sra_32_ba03eea6386b` | `executable_scalar / 0x00002508` | `L3` | `exact_value` | `05e14100` |
+| `srl_32_5cfca42c59f3` | `executable_scalar / 0x00002507` | `L3` | `exact_value` | `05d14100` |
+| `sub_32_af383d4a2b42` | `executable_scalar / 0x00002502` | `L3` | `exact_value` | `05914106` |
+| `sw_32_28ad317b1b41` | `executable_scalar / 0x0000250f` | `L3` | `architectural_state` | `49205216` |
+| `v_add_64_394294cc5946` | `v057_vector_ops / 0x00001370` | `L3` | `exact_value` | `7f02520005801000` |
+| `v_cmp_lt_64_3ef2162a77ba` | `v057_vector_ops / 0x00001320` | `L3` | `exact_value` | `7f82110045401000` |
+| `v_fadd_64_c5c08b2ac830` | `v057_vector_ops / 0x00001374` | `L3` | `exact_value` | `7f0212004b802000` |
+| `v_fmul_64_3e2b1576cbfe` | `v057_vector_ops / 0x00001375` | `L3` | `exact_value` | `7f0212004ba03000` |
+| `v_lw_brg_64_6163b7a621fc` | `v057_vector_ops / 0x00001372` | `L3` | `exact_value` | `7fa2000009200000` |
+| `v_sub_64_3c88cf0158f8` | `v057_vector_ops / 0x00001371` | `L3` | `exact_value` | `7f02520005101100` |
+| `v_sw_brg_64_d78368c708bd` | `v057_vector_ops / 0x00001373` | `L3` | `exact_value` | `7fa0002049200108` |
+| `xor_32_33510860c585` | `executable_scalar / 0x00002505` | `L3` | `exact_value` | `05c14106` |
 
 ## Failed / Rejected Evidence
 
@@ -37,17 +83,63 @@ None.
 
 ## Execution Observations
 
-- `executable_setc_imm / 0x00002801`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_setc_imm / 0x00002802`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_setc_imm / 0x00002803`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_setc_imm / 0x00002804`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_setc_imm / 0x00002805`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_setc_imm / 0x00002806`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_setc_imm / 0x00002807`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_setc_imm / 0x00002808`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_setc_imm / 0x00002809`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_setc_imm / 0x0000280a`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_maddw_bfi_mi / 0x00002901`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_maddw_bfi_mi / 0x00002902`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_maddw_bfi_mi / 0x00002903`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
-- `executable_maddw_bfi_mi / 0x00002904`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `callret / 0x0000140b`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `callret / 0x0000140c`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `callret / 0x0000140d`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `callret / 0x0000140f`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `callret / 0x00001410`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `callret / 0x00001411`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x00002201`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x00002202`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002501`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002502`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002503`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002504`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002505`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002506`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002507`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002508`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002509`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x0000250a`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x0000250b`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x0000250c`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x0000250d`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x0000250e`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x0000250f`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_scalar / 0x00002510`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x00002203`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x00002204`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x00002205`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x00002206`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x00002207`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x00002208`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x00002209`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x0000220a`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x0000220b`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x0000220c`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_memory / 0x0000220d`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x00002601`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x00002602`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x00002603`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x00002604`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x00002605`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x00002606`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x00002607`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x00002608`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x00002609`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x0000260a`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x0000260b`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x0000260c`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x0000260d`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x0000260e`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `executable_integer / 0x0000260f`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `v057_vector_ops / 0x00001372`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `v057_vector_ops / 0x00001370`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `v057_vector_ops / 0x00001373`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `v057_vector_ops / 0x00001371`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `v057_vector_ops / 0x00001374`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `v057_vector_ops / 0x00001375`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `v057_vector_ops / 0x00001320`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `atomic / 0x00007162`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `atomic / 0x00007163`: status `PASS`, oracle `PASS`, timeout-after-fail `False`, test-contract `valid`, attribution `none`
+- `v057_vector_ops / 0x00001321`: status `FAIL`, oracle `FAIL`, timeout-after-fail `True`, failure `0x00001321` expected `0x0000000000000053` actual `0x0000000000000011`, test-contract `invalid`, attribution `test_contract`, note: Historical first-red evidence. The AVS source used invalid VT/VU lifetime and relative-index semantics; the corrected source and authored B.IOR binding now pass 0x1300, 0x1310, and 0x1320.
diff --git a/docs/bringup/gates/qemu_isa_coverage_latest.json b/docs/bringup/gates/qemu_isa_coverage_latest.json
index 62c2698b..ae6272e2 100644
--- a/docs/bringup/gates/qemu_isa_coverage_latest.json
+++ b/docs/bringup/gates/qemu_isa_coverage_latest.json
@@ -1,7 +1,5 @@
 {
-  "canonical_specialization_forms": [
-    "BSTART.ACCCVT [len=32 mask=0x7ffffff match=0x831181]"
-  ],
+  "canonical_specialization_forms": [],
   "capabilities": [
     "decoder_source_to_isa_mnemonic_mapping",
     "decoder_mask_to_isa_form_matching",
@@ -10,41 +8,42 @@
   ],
   "claim": "decoder_source_mapping",
   "constraint_union_forms": [
+    "C.BSTART.FP [len=16 mask=0xc7ff match=0x80]",
     "C.BSTART.STD [len=16 mask=0xc7ff match=0x0]"
   ],
-  "coverage_count": 646,
-  "coverage_ratio_percent": 88.37,
+  "coverage_count": 728,
+  "coverage_ratio_percent": 100.0,
   "evidence": {
     "L1": {
       "availability": "available",
       "claim": "decoder_source_mapping",
-      "form_count": 678,
-      "mnemonic_count": 646
+      "form_count": 761,
+      "mnemonic_count": 728
     },
     "L2": {
       "availability": "available",
       "claim": "runtime_execution",
-      "form_count": 10,
-      "mnemonic_count": 10,
-      "qemu_sha": "b4df5c31d06eaee04b602b4b6fd8b6f2c2592b4c",
-      "source": "/Users/zhoubot/linx-isa/docs/bringup/gates/qemu_executable_coverage_latest.json"
+      "form_count": 60,
+      "mnemonic_count": 60,
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "source": "/private/tmp/linx-isa-v0571/docs/bringup/gates/qemu_executable_coverage_latest.json"
     },
     "L3": {
       "availability": "available",
       "claim": "semantic_oracle",
-      "form_count": 10,
-      "mnemonic_count": 10,
-      "qemu_sha": "b4df5c31d06eaee04b602b4b6fd8b6f2c2592b4c",
-      "source": "/Users/zhoubot/linx-isa/docs/bringup/gates/qemu_executable_coverage_latest.json"
+      "form_count": 60,
+      "mnemonic_count": 60,
+      "qemu_sha": "cfc253e844f4b0d017b2190a025c4375771f899a",
+      "source": "/private/tmp/linx-isa-v0571/docs/bringup/gates/qemu_executable_coverage_latest.json"
     }
   },
   "evidence_level": "L1",
-  "form_coverage_count": 678,
-  "form_coverage_ratio_percent": 88.17,
-  "form_missing_count": 91,
-  "generated_at_utc": "2026-07-25 07:32:23Z",
-  "legal_form_count": 769,
-  "legal_mnemonic_count": 731,
+  "form_coverage_count": 761,
+  "form_coverage_ratio_percent": 100.0,
+  "form_missing_count": 0,
+  "generated_at_utc": "2026-08-02 12:51:46Z",
+  "legal_form_count": 761,
+  "legal_mnemonic_count": 728,
   "limitations": [
     "runtime_execution_evidence_is_partial",
     "semantic_oracle_evidence_is_partial",
@@ -63,13 +62,13 @@
     "ANDIW": 1,
     "ANDW": 1,
     "ASSERT": 1,
-    "B": 16,
+    "B": 15,
     "BC": 2,
     "BCNT": 1,
     "BIC": 1,
     "BIS": 1,
     "BSE": 1,
-    "BSTART": 34,
+    "BSTART": 32,
     "BSTOP": 1,
     "BWE": 1,
     "BWI": 1,
@@ -208,7 +207,8 @@
     "SWI": 2,
     "TLB": 4,
     "UCVTF": 1,
-    "V": 100,
+    "V": 184,
+    "XB": 1,
     "XOR": 1,
     "XORI": 1,
     "XORIW": 1,
@@ -227,13 +227,13 @@
     "ANDIW": 1,
     "ANDW": 1,
     "ASSERT": 1,
-    "B": 26,
+    "B": 22,
     "BC": 2,
     "BCNT": 1,
     "BIC": 1,
     "BIS": 1,
     "BSE": 1,
-    "BSTART": 43,
+    "BSTART": 45,
     "BSTOP": 1,
     "BWE": 1,
     "BWI": 1,
@@ -372,7 +372,8 @@
     "SWI": 2,
     "TLB": 4,
     "UCVTF": 1,
-    "V": 100,
+    "V": 184,
+    "XB": 1,
     "XOR": 1,
     "XORI": 1,
     "XORIW": 1,
@@ -418,24 +419,6 @@
     "assert": [
       "ASSERT"
     ],
-    "b_arg": [
-      "B.ARG"
-    ],
-    "b_arg_dn2nz": [
-      "B.ARG"
-    ],
-    "b_arg_dn2zn": [
-      "B.ARG"
-    ],
-    "b_arg_nd2zn": [
-      "B.ARG"
-    ],
-    "b_arg_norm": [
-      "B.ARG"
-    ],
-    "b_arg_nz2dn": [
-      "B.ARG"
-    ],
     "b_catr": [
       "B.CATR"
     ],
@@ -508,6 +491,9 @@
     "bse": [
       "BSE"
     ],
+    "bstart_acccvt": [
+      "BSTART.ACCCVT"
+    ],
     "bstart_call": [
       "BSTART CALL",
       "BSTART.STD"
@@ -516,10 +502,6 @@
       "BSTART",
       "BSTART.STD"
     ],
-    "bstart_cube": [
-      "BSTART.CUBE",
-      "BSTART.ACCCVT"
-    ],
     "bstart_direct": [
       "BSTART",
       "BSTART.STD"
@@ -527,9 +509,6 @@
     "bstart_fall": [
       "BSTART.STD"
     ],
-    "bstart_fixp": [
-      "BSTART.FIXP"
-    ],
     "bstart_fp_call": [
       "BSTART.FP"
     ],
@@ -772,6 +751,9 @@
     "c_setc_tgt": [
       "C.SETC.TGT"
     ],
+    "c_setret": [
+      "C.SETRET"
+    ],
     "c_sext_b": [
       "C.SEXT.B"
     ],
@@ -2315,30 +2297,150 @@
     "v_lb_brg": [
       "V.LB.BRG"
     ],
+    "v_lbi": [
+      "V.LBI"
+    ],
+    "v_lbi_brg": [
+      "V.LBI.BRG"
+    ],
     "v_lbu": [
       "V.LBU"
     ],
     "v_lbu_brg": [
       "V.LBU.BRG"
     ],
+    "v_lbui": [
+      "V.LBUI"
+    ],
+    "v_lbui_brg": [
+      "V.LBUI.BRG"
+    ],
+    "v_ld": [
+      "V.LD"
+    ],
+    "v_ld_add": [
+      "V.LD.ADD"
+    ],
+    "v_ld_and": [
+      "V.LD.AND"
+    ],
+    "v_ld_brg": [
+      "V.LD.BRG"
+    ],
+    "v_ld_max": [
+      "V.LD.MAX"
+    ],
+    "v_ld_min": [
+      "V.LD.MIN"
+    ],
+    "v_ld_or": [
+      "V.LD.OR"
+    ],
+    "v_ld_xor": [
+      "V.LD.XOR"
+    ],
+    "v_ldi": [
+      "V.LDI"
+    ],
+    "v_ldi_brg": [
+      "V.LDI.BRG"
+    ],
+    "v_ldi_u": [
+      "V.LDI.U"
+    ],
+    "v_ldi_u_brg": [
+      "V.LDI.U.BRG"
+    ],
     "v_lh": [
       "V.LH"
     ],
     "v_lh_brg": [
       "V.LH.BRG"
     ],
+    "v_lhi": [
+      "V.LHI"
+    ],
+    "v_lhi_brg": [
+      "V.LHI.BRG"
+    ],
+    "v_lhi_u": [
+      "V.LHI.U"
+    ],
+    "v_lhi_u_brg": [
+      "V.LHI.U.BRG"
+    ],
     "v_lhu": [
       "V.LHU"
     ],
     "v_lhu_brg": [
       "V.LHU.BRG"
     ],
+    "v_lhui": [
+      "V.LHUI"
+    ],
+    "v_lhui_brg": [
+      "V.LHUI.BRG"
+    ],
+    "v_lhui_u": [
+      "V.LHUI.U"
+    ],
+    "v_lhui_u_brg": [
+      "V.LHUI.U.BRG"
+    ],
     "v_lw": [
       "V.LW"
     ],
+    "v_lw_add": [
+      "V.LW.ADD"
+    ],
+    "v_lw_and": [
+      "V.LW.AND"
+    ],
     "v_lw_brg": [
       "V.LW.BRG"
     ],
+    "v_lw_max": [
+      "V.LW.MAX"
+    ],
+    "v_lw_min": [
+      "V.LW.MIN"
+    ],
+    "v_lw_or": [
+      "V.LW.OR"
+    ],
+    "v_lw_xor": [
+      "V.LW.XOR"
+    ],
+    "v_lwi": [
+      "V.LWI"
+    ],
+    "v_lwi_brg": [
+      "V.LWI.BRG"
+    ],
+    "v_lwi_u": [
+      "V.LWI.U"
+    ],
+    "v_lwi_u_brg": [
+      "V.LWI.U.BRG"
+    ],
+    "v_lwu": [
+      "V.LWU"
+    ],
+    "v_lwu_brg": [
+      "V.LWU.BRG"
+    ],
+    "v_lwui": [
+      "V.LWUI"
+    ],
+    "v_lwui_brg": [
+      "V.LWUI.BRG"
+    ],
+    "v_lwui_u": [
+      "V.LWUI.U"
+    ],
+    "v_lwui_u_brg": [
+      "V.LWUI.U.BRG"
+    ],
     "v_madd": [
       "V.MADD"
     ],
@@ -2360,6 +2462,12 @@
     "v_psel": [
       "V.PSEL"
     ],
+    "v_qpop": [
+      "V.QPOP"
+    ],
+    "v_qpush": [
+      "V.QPUSH"
+    ],
     "v_rdadd": [
       "V.RDADD"
     ],
@@ -2399,12 +2507,102 @@
     "v_sb_brg": [
       "V.SB.BRG"
     ],
+    "v_sbi": [
+      "V.SBI"
+    ],
+    "v_sbi_brg": [
+      "V.SBI.BRG"
+    ],
+    "v_sd": [
+      "V.SD"
+    ],
+    "v_sd_add": [
+      "V.SD.ADD"
+    ],
+    "v_sd_and": [
+      "V.SD.AND"
+    ],
+    "v_sd_brg": [
+      "V.SD.BRG"
+    ],
+    "v_sd_max": [
+      "V.SD.MAX"
+    ],
+    "v_sd_min": [
+      "V.SD.MIN"
+    ],
+    "v_sd_or": [
+      "V.SD.OR"
+    ],
+    "v_sd_u": [
+      "V.SD.U"
+    ],
+    "v_sd_u_brg": [
+      "V.SD.U.BRG"
+    ],
+    "v_sd_xor": [
+      "V.SD.XOR"
+    ],
+    "v_sdi": [
+      "V.SDI"
+    ],
+    "v_sdi_brg": [
+      "V.SDI.BRG"
+    ],
+    "v_sdi_u": [
+      "V.SDI.U"
+    ],
+    "v_sdi_u_brg": [
+      "V.SDI.U.BRG"
+    ],
     "v_sh": [
       "V.SH"
     ],
     "v_sh_brg": [
       "V.SH.BRG"
     ],
+    "v_sh_u": [
+      "V.SH.U"
+    ],
+    "v_sh_u_brg": [
+      "V.SH.U.BRG"
+    ],
+    "v_shfl_bfly": [
+      "V.SHFL.BFLY"
+    ],
+    "v_shfl_down": [
+      "V.SHFL.DOWN"
+    ],
+    "v_shfl_idx": [
+      "V.SHFL.IDX"
+    ],
+    "v_shfl_up": [
+      "V.SHFL.UP"
+    ],
+    "v_shfli_bfly": [
+      "V.SHFLI.BFLY"
+    ],
+    "v_shfli_down": [
+      "V.SHFLI.DOWN"
+    ],
+    "v_shfli_idx": [
+      "V.SHFLI.IDX"
+    ],
+    "v_shfli_up": [
+      "V.SHFLI.UP"
+    ],
+    "v_shi": [
+      "V.SHI"
+    ],
+    "v_shi_brg": [
+      "V.SHI.BRG"
+    ],
+    "v_shi_u": [
+      "V.SHI.U"
+    ],
+    "v_shi_u_brg": [
+      "V.SHI.U.BRG"
+    ],
     "v_sll": [
       "V.SLL"
     ],
@@ -2432,15 +2630,54 @@
     "v_sw": [
       "V.SW"
     ],
+    "v_sw_add": [
+      "V.SW.ADD"
+    ],
+    "v_sw_and": [
+      "V.SW.AND"
+    ],
     "v_sw_brg": [
       "V.SW.BRG"
     ],
+    "v_sw_max": [
+      "V.SW.MAX"
+    ],
+    "v_sw_min": [
+      "V.SW.MIN"
+    ],
+    "v_sw_or": [
+      "V.SW.OR"
+    ],
+    "v_sw_u": [
+      "V.SW.U"
+    ],
+    "v_sw_u_brg": [
+      "V.SW.U.BRG"
+    ],
+    "v_sw_xor": [
+      "V.SW.XOR"
+    ],
+    "v_swi": [
+      "V.SWI"
+    ],
+    "v_swi_brg": [
+      "V.SWI.BRG"
+    ],
+    "v_swi_u": [
+      "V.SWI.U"
+    ],
+    "v_swi_u_brg": [
+      "V.SWI.U.BRG"
+    ],
     "v_xor": [
       "V.XOR"
     ],
     "v_xori": [
       "V.XORI"
     ],
+    "xb": [
+      "XB"
+    ],
     "xor": [
       "XOR"
     ],
@@ -2454,208 +2691,22 @@
       "XORW"
     ]
   },
-  "missing_by_prefix": {
-    "V": 84,
-    "XB": 1
-  },
-  "missing_count": 85,
-  "missing_forms_by_prefix": {
-    "B": 2,
-    "BSTART": 4,
-    "V": 84,
-    "XB": 1
-  },
-  "missing_spec_forms": [
-    "B.IOT [len=32 mask=0x1fc0707f match=0x1c04013]",
-    "B.IOT [len=32 mask=0x9fff707f match=0x1c05013]",
-    "BSTART.MPAR [len=32 mask=0xf9ffffff match=0x1181]",
-    "BSTART.MSEQ [len=32 mask=0xf9ffffff match=0x9181]",
-    "BSTART.VPAR [len=32 mask=0xf9ffffff match=0x21181]",
-    "BSTART.VSEQ [len=32 mask=0xf9ffffff match=0x29181]",
-    "V.LBI [len=64 mask=0x707f0000207f match=0x190000007f]",
-    "V.LBI.BRG [len=64 mask=0x707f0000207f match=0x190000207f]",
-    "V.LBUI [len=64 mask=0x707f0000207f match=0x40190000007f]",
-    "V.LBUI.BRG [len=64 mask=0x707f0000207f match=0x40190000207f]",
-    "V.LD [len=64 mask=0x600707ffe00207f match=0x30090000007f]",
-    "V.LD.ADD [len=64 mask=0xf800707ffc00707f match=0xb0000207f]",
-    "V.LD.AND [len=64 mask=0xf800707ffc00707f match=0x100b0000207f]",
-    "V.LD.BRG [len=64 mask=0x600707ffe00207f match=0x30090000207f]",
-    "V.LD.MAX [len=64 mask=0xf800707ffc00707f match=0x400b0000207f]",
-    "V.LD.MIN [len=64 mask=0xf800707ffc00707f match=0x500b0000207f]",
-    "V.LD.OR [len=64 mask=0xf800707ffc00707f match=0x200b0000207f]",
-    "V.LD.XOR [len=64 mask=0xf800707ffc00707f match=0x300b0000207f]",
-    "V.LDI [len=64 mask=0x707f0000207f match=0x30190000007f]",
-    "V.LDI.BRG [len=64 mask=0x707f0000207f match=0x30190000207f]",
-    "V.LDI.U [len=64 mask=0x707f0000207f match=0x30290000007f]",
-    "V.LDI.U.BRG [len=64 mask=0x707f0000207f match=0x30290000207f]",
-    "V.LHI [len=64 mask=0x707f0000207f match=0x10190000007f]",
-    "V.LHI.BRG [len=64 mask=0x707f0000207f match=0x10190000207f]",
-    "V.LHI.U [len=64 mask=0x707f0000207f match=0x10290000007f]",
-    "V.LHI.U.BRG [len=64 mask=0x707f0000207f match=0x10290000207f]",
-    "V.LHUI [len=64 mask=0x707f0000207f match=0x50190000007f]",
-    "V.LHUI.BRG [len=64 mask=0x707f0000207f match=0x50190000207f]",
-    "V.LHUI.U [len=64 mask=0x707f0000207f match=0x50290000007f]",
-    "V.LHUI.U.BRG [len=64 mask=0x707f0000207f match=0x50290000207f]",
-    "V.LW.ADD [len=64 mask=0xf800707ffc00707f match=0xb0000007f]",
-    "V.LW.AND [len=64 mask=0xf800707ffc00707f match=0x100b0000007f]",
-    "V.LW.MAX [len=64 mask=0xf800707ffc00707f match=0x400b0000007f]",
-    "V.LW.MIN [len=64 mask=0xf800707ffc00707f match=0x500b0000007f]",
-    "V.LW.OR [len=64 mask=0xf800707ffc00707f match=0x200b0000007f]",
-    "V.LW.XOR [len=64 mask=0xf800707ffc00707f match=0x300b0000007f]",
-    "V.LWI [len=64 mask=0x707f0000207f match=0x20190000007f]",
-    "V.LWI.BRG [len=64 mask=0x707f0000207f match=0x20190000207f]",
-    "V.LWI.U [len=64 mask=0x707f0000207f match=0x20290000007f]",
-    "V.LWI.U.BRG [len=64 mask=0x707f0000207f match=0x20290000207f]",
-    "V.LWU [len=64 mask=0x600707ffe00207f match=0x60090000007f]",
-    "V.LWU.BRG [len=64 mask=0x600707ffe00207f match=0x60090000207f]",
-    "V.LWUI [len=64 mask=0x707f0000207f match=0x60190000007f]",
-    "V.LWUI.BRG [len=64 mask=0x707f0000207f match=0x60190000207f]",
-    "V.LWUI.U [len=64 mask=0x707f0000207f match=0x60290000007f]",
-    "V.LWUI.U.BRG [len=64 mask=0x707f0000207f match=0x60290000207f]",
-    "V.QPOP [len=64 mask=0xfff0707ffff0707f match=0x207d0000007f]",
-    "V.QPUSH [len=64 mask=0xfe00707ffe00707f match=0x107d0000007f]",
-    "V.SBI [len=64 mask=0x707f0000207f match=0x590000007f]",
-    "V.SBI.BRG [len=64 mask=0x707f0000207f match=0x590000207f]",
-    "V.SD [len=64 mask=0x6007fff0600207f match=0x30490000007f]",
-    "V.SD.ADD [len=64 mask=0xfc007ffff8007fff match=0xb0000307f]",
-    "V.SD.AND [len=64 mask=0xfc007ffff8007fff match=0x100b0000307f]",
-    "V.SD.BRG [len=64 mask=0x6007fff0600207f match=0x30490000207f]",
-    "V.SD.MAX [len=64 mask=0xfc007ffff8007fff match=0x400b0000307f]",
-    "V.SD.MIN [len=64 mask=0xfc007ffff8007fff match=0x500b0000307f]",
-    "V.SD.OR [len=64 mask=0xfc007ffff8007fff match=0x200b0000307f]",
-    "V.SD.U [len=64 mask=0x6007fff0600207f match=0x70490000007f]",
-    "V.SD.U.BRG [len=64 mask=0x6007fff0600207f match=0x70490000207f]",
-    "V.SD.XOR [len=64 mask=0xfc007ffff8007fff match=0x300b0000307f]",
-    "V.SDI [len=64 mask=0x707f0000207f match=0x30590000007f]",
-    "V.SDI.BRG [len=64 mask=0x707f0000207f match=0x30590000207f]",
-    "V.SDI.U [len=64 mask=0x707f0000207f match=0x70590000007f]",
-    "V.SDI.U.BRG [len=64 mask=0x707f0000207f match=0x70590000207f]",
-    "V.SH.U [len=64 mask=0x6007fff0600207f match=0x50490000007f]",
-    "V.SH.U.BRG [len=64 mask=0x6007fff0600207f match=0x50490000207f]",
-    "V.SHFL.BFLY [len=64 mask=0x7f0707f07f0707f match=0x201d0000007f]",
-    "V.SHFL.DOWN [len=64 mask=0x600707f0600707f match=0x101d0000007f]",
-    "V.SHFL.IDX [len=64 mask=0x600707f0600707f match=0x301d0000007f]",
-    "V.SHFL.UP [len=64 mask=0x600707f0600707f match=0x1d0000007f]",
-    "V.SHFLI.BFLY [len=64 mask=0x1f0707f01f0707f match=0x602d0000007f]",
-    "V.SHFLI.DOWN [len=64 mask=0x707f0000707f match=0x502d0000007f]",
-    "V.SHFLI.IDX [len=64 mask=0x707f0000707f match=0x702d0000007f]",
-    "V.SHFLI.UP [len=64 mask=0x707f0000707f match=0x402d0000007f]",
-    "V.SHI [len=64 mask=0x707f0000207f match=0x10590000007f]",
-    "V.SHI.BRG [len=64 mask=0x707f0000207f match=0x10590000207f]",
-    "V.SHI.U [len=64 mask=0x707f0000207f match=0x50590000007f]",
-    "V.SHI.U.BRG [len=64 mask=0x707f0000207f match=0x50590000207f]",
-    "V.SW.ADD [len=64 mask=0xfc007ffff8007fff match=0xb0000107f]",
-    "V.SW.AND [len=64 mask=0xfc007ffff8007fff match=0x100b0000107f]",
-    "V.SW.MAX [len=64 mask=0xfc007ffff8007fff match=0x400b0000107f]",
-    "V.SW.MIN [len=64 mask=0xfc007ffff8007fff match=0x500b0000107f]",
-    "V.SW.OR [len=64 mask=0xfc007ffff8007fff match=0x200b0000107f]",
-    "V.SW.U [len=64 mask=0x6007fff0600207f match=0x60490000007f]",
-    "V.SW.U.BRG [len=64 mask=0x6007fff0600207f match=0x60490000207f]",
-    "V.SW.XOR [len=64 mask=0xfc007ffff8007fff match=0x300b0000107f]",
-    "V.SWI [len=64 mask=0x707f0000207f match=0x20590000007f]",
-    "V.SWI.BRG [len=64 mask=0x707f0000207f match=0x20590000207f]",
-    "V.SWI.U [len=64 mask=0x707f0000207f match=0x60590000007f]",
-    "V.SWI.U.BRG [len=64 mask=0x707f0000207f match=0x60590000207f]",
-    "XB [len=32 mask=0x7fff match=0x6f81]"
-  ],
-  "missing_spec_mnemonics": [
-    "V.LBI",
-    "V.LBI.BRG",
-    "V.LBUI",
-    "V.LBUI.BRG",
-    "V.LD",
-    "V.LD.ADD",
-    "V.LD.AND",
-    "V.LD.BRG",
-    "V.LD.MAX",
-    "V.LD.MIN",
-    "V.LD.OR",
-    "V.LD.XOR",
-    "V.LDI",
-    "V.LDI.BRG",
-    "V.LDI.U",
-    "V.LDI.U.BRG",
-    "V.LHI",
-    "V.LHI.BRG",
-    "V.LHI.U",
-    "V.LHI.U.BRG",
-    "V.LHUI",
-    "V.LHUI.BRG",
-    "V.LHUI.U",
-    "V.LHUI.U.BRG",
-    "V.LW.ADD",
-    "V.LW.AND",
-    "V.LW.MAX",
-    "V.LW.MIN",
-    "V.LW.OR",
-    "V.LW.XOR",
-    "V.LWI",
-    "V.LWI.BRG",
-    "V.LWI.U",
-    "V.LWI.U.BRG",
-    "V.LWU",
-    "V.LWU.BRG",
-    "V.LWUI",
-    "V.LWUI.BRG",
-    "V.LWUI.U",
-    "V.LWUI.U.BRG",
-    "V.QPOP",
-    "V.QPUSH",
-    "V.SBI",
-    "V.SBI.BRG",
-    "V.SD",
-    "V.SD.ADD",
-    "V.SD.AND",
-    "V.SD.BRG",
-    "V.SD.MAX",
-    "V.SD.MIN",
-    "V.SD.OR",
-    "V.SD.U",
-    "V.SD.U.BRG",
-    "V.SD.XOR",
-    "V.SDI",
-    "V.SDI.BRG",
-    "V.SDI.U",
-    "V.SDI.U.BRG",
-    "V.SH.U",
-    "V.SH.U.BRG",
-    "V.SHFL.BFLY",
-    "V.SHFL.DOWN",
-    "V.SHFL.IDX",
-    "V.SHFL.UP",
-    "V.SHFLI.BFLY",
-    "V.SHFLI.DOWN",
-    "V.SHFLI.IDX",
-    "V.SHFLI.UP",
-    "V.SHI",
-    "V.SHI.BRG",
-    "V.SHI.U",
-    "V.SHI.U.BRG",
-    "V.SW.ADD",
-    "V.SW.AND",
-    "V.SW.MAX",
-    "V.SW.MIN",
-    "V.SW.OR",
-    "V.SW.U",
-    "V.SW.U.BRG",
-    "V.SW.XOR",
-    "V.SWI",
-    "V.SWI.BRG",
-    "V.SWI.U",
-    "V.SWI.U.BRG",
-    "XB"
-  ],
+  "missing_by_prefix": {},
+  "missing_count": 0,
+  "missing_forms_by_prefix": {},
+  "missing_spec_forms": [],
+  "missing_spec_mnemonics": [],
   "qemu_manual_translate_mnemonics": [
     "C.SETRET"
   ],
-  "qemu_mapped_spec_forms": 678,
-  "qemu_mapped_spec_mnemonics": 646,
-  "qemu_meta_mnemonics": 678,
-  "qemu_meta_path": "/Users/zhoubot/linx-isa/emulator/qemu-clean-b4df5c31/target/linx/linx_opcode_meta_gen.h",
-  "qemu_root": "/Users/zhoubot/linx-isa/emulator/qemu-clean-b4df5c31",
+  "qemu_mapped_spec_forms": 761,
+  "qemu_mapped_spec_mnemonics": 728,
+  "qemu_meta_mnemonics": 855,
+  "qemu_meta_path": "/private/tmp/linx-isa-v0571/emulator/qemu/target/linx/linx_opcode_meta_gen.h",
+  "qemu_root": "/private/tmp/linx-isa-v0571/emulator/qemu",
   "qemu_source_kind": "decode",
-  "qemu_unique_forms": 687,
-  "qemu_unique_mnemonics": 679,
+  "qemu_unique_forms": 872,
+  "qemu_unique_mnemonics": 856,
   "reserved_encoding_families": [
     {
       "behavior": "illegal_instruction",
@@ -2675,8 +2726,107 @@
     "ok": true
   },
   "schema_version": "qemu-isa-coverage-v3",
-  "spec_path": "/Users/zhoubot/linx-isa/isa/v0.57/linxisa-v0.57.json",
-  "spec_total_forms": 769,
-  "spec_unique_mnemonics": 731,
-  "unmapped_qemu_mnemonics": []
+  "spec_path": "/private/tmp/linx-isa-v0571/isa/v0.57/linxisa-v0.57.json",
+  "spec_total_forms": 761,
+  "spec_unique_mnemonics": 728,
+  "unmapped_qemu_mnemonics": [
+    "bstart_tabs",
+    "bstart_tadd",
+    "bstart_tadds",
+    "bstart_talloc",
+    "bstart_tand",
+    "bstart_tands",
+    "bstart_taxpy",
+    "bstart_tci",
+    "bstart_tcmp",
+    "bstart_tcmps",
+    "bstart_tcolargmax",
+    "bstart_tcolargmin",
+    "bstart_tcolexpand",
+    "bstart_tcolexpandadd",
+    "bstart_tcolexpanddiv",
+    "bstart_tcolexpandexpdif",
+    "bstart_tcolexpandmax",
+    "bstart_tcolexpandmin",
+    "bstart_tcolexpandmul",
+    "bstart_tcolexpandsub",
+    "bstart_tcolmax",
+    "bstart_tcolmin",
+    "bstart_tcolprod",
+    "bstart_tcolsum",
+    "bstart_tconcat",
+    "bstart_tcvt",
+    "bstart_tdeinterleave",
+    "bstart_tdequant",
+    "bstart_tdiv",
+    "bstart_tdivs",
+    "bstart_texp",
+    "bstart_texpands",
+    "bstart_textract",
+    "bstart_tfillpad",
+    "bstart_tfree",
+    "bstart_tgather",
+    "bstart_tgatherb",
+    "bstart_thistogram",
+    "bstart_timg2col",
+    "bstart_tinsert",
+    "bstart_tinterleave",
+    "bstart_tlog",
+    "bstart_tmax",
+    "bstart_tmaxs",
+    "bstart_tmin",
+    "bstart_tmins",
+    "bstart_tmrgsort",
+    "bstart_tmul",
+    "bstart_tmuls",
+    "bstart_tneg",
+    "bstart_tnot",
+    "bstart_tor",
+    "bstart_tors",
+    "bstart_tpartadd",
+    "bstart_tpartargmax",
+    "bstart_tpartargmin",
+    "bstart_tpartmax",
+    "bstart_tpartmin",
+    "bstart_tpartmul",
+    "bstart_tpop",
+    "bstart_tprelu",
+    "bstart_tpush",
+    "bstart_tquant",
+    "bstart_trecip",
+    "bstart_trelu",
+    "bstart_trem",
+    "bstart_trems",
+    "bstart_treshape",
+    "bstart_trowargmax",
+    "bstart_trowargmin",
+    "bstart_trowexpand",
+    "bstart_trowexpandadd",
+    "bstart_trowexpanddiv",
+    "bstart_trowexpandexpdif",
+    "bstart_trowexpandmax",
+    "bstart_trowexpandmin",
+    "bstart_trowexpandmul",
+    "bstart_trowexpandsub",
+    "bstart_trowmax",
+    "bstart_trowmin",
+    "bstart_trowprod",
+    "bstart_trowsum",
+    "bstart_trsqrt",
+    "bstart_tscatter",
+    "bstart_tsel",
+    "bstart_tsels",
+    "bstart_tshl",
+    "bstart_tshls",
+    "bstart_tshr",
+    "bstart_tshrs",
+    "bstart_tsort",
+    "bstart_tsqrt",
+    "bstart_tsub",
+    "bstart_tsubs",
+    "bstart_ttrans",
+    "bstart_ttri",
+    "bstart_txor",
+    "bstart_txors"
+  ]
 }
diff --git a/docs/bringup/gates/qemu_isa_coverage_latest.md b/docs/bringup/gates/qemu_isa_coverage_latest.md
index ffdaa9fd..8026e369 100644
--- a/docs/bringup/gates/qemu_isa_coverage_latest.md
+++ b/docs/bringup/gates/qemu_isa_coverage_latest.md
@@ -1,22 +1,22 @@
 # ISA vs QEMU Decoder/Source Mapping Snapshot
 
-- Generated (UTC): `2026-07-25 07:32:23Z`
+- Generated (UTC): `2026-08-02 12:51:46Z`
 - Evidence level: `L1`
 - Claim: `decoder_source_mapping`
-- L2 runtime execution: `available`; `10` forms / `10` mnemonics
-- L3 semantic oracle: `available`; `10` forms / `10` mnemonics
+- L2 runtime execution: `available`; `60` forms / `60` mnemonics
+- L3 semantic oracle: `available`; `60` forms / `60` mnemonics
 - Limitation: L1 mapping does not imply execution; L2/L3 counts are independently audited per-form evidence and remain partial.
-- Spec unique mnemonics: `731`
-- QEMU unique decode mnemonics (non-internal): `679`
-- QEMU mapped spec mnemonics: `646`
-- L1 mnemonic mapping: `646/731` (`88.37%`)
-- Spec legal forms: `769`
-- QEMU mapped spec forms: `678`
-- L1 form mapping: `678/769` (`88.17%`)
-- Missing spec mnemonics: `85`
-- Missing spec forms: `91`
+- Spec unique mnemonics: `728`
+- QEMU unique decode mnemonics (non-internal): `856`
+- QEMU mapped spec mnemonics: `728`
+- L1 mnemonic mapping: `728/728` (`100.0%`)
+- Spec legal forms: `761`
+- QEMU mapped spec forms: `761`
+- L1 form mapping: `761/761` (`100.0%`)
+- Missing spec mnemonics: `0`
+- Missing spec forms: `0`
 - Reserved spec forms: `1`
-- Unmapped QEMU mnemonics: `0`
+- Unmapped QEMU mnemonics: `98`
 
 ## L1 Mnemonic Mapping By Prefix
 
@@ -32,13 +32,13 @@
 - `ANDIW`: `1`
 - `ANDW`: `1`
 - `ASSERT`: `1`
-- `B`: `16`
+- `B`: `15`
 - `BC`: `2`
 - `BCNT`: `1`
 - `BIC`: `1`
 - `BIS`: `1`
 - `BSE`: `1`
-- `BSTART`: `34`
+- `BSTART`: `32`
 - `BSTOP`: `1`
 - `BWE`: `1`
 - `BWI`: `1`
@@ -177,7 +177,8 @@
 - `SWI`: `2`
 - `TLB`: `4`
 - `UCVTF`: `1`
-- `V`: `100`
+- `V`: `184`
+- `XB`: `1`
 - `XOR`: `1`
 - `XORI`: `1`
 - `XORIW`: `1`
@@ -185,8 +186,6 @@
 
 ## Missing Mnemonics By Prefix
 
-- `V`: `84`
-- `XB`: `1`
 
 ## L1 Form Mapping By Prefix
 
@@ -202,13 +201,13 @@
 - `ANDIW`: `1`
 - `ANDW`: `1`
 - `ASSERT`: `1`
-- `B`: `26`
+- `B`: `22`
 - `BC`: `2`
 - `BCNT`: `1`
 - `BIC`: `1`
 - `BIS`: `1`
 - `BSE`: `1`
-- `BSTART`: `43`
+- `BSTART`: `45`
 - `BSTOP`: `1`
 - `BWE`: `1`
 - `BWI`: `1`
@@ -347,7 +346,8 @@
 - `SWI`: `2`
 - `TLB`: `4`
 - `UCVTF`: `1`
-- `V`: `100`
+- `V`: `184`
+- `XB`: `1`
 - `XOR`: `1`
 - `XORI`: `1`
 - `XORIW`: `1`
@@ -355,193 +355,109 @@
 
 ## Missing Forms By Prefix
 
-- `B`: `2`
-- `BSTART`: `4`
-- `V`: `84`
-- `XB`: `1`
 
 ## Unmapped QEMU Mnemonics
 
-- none
+- `bstart_tabs`
+- `bstart_tadd`
+- `bstart_tadds`
+- `bstart_talloc`
+- `bstart_tand`
+- `bstart_tands`
+- `bstart_taxpy`
+- `bstart_tci`
+- `bstart_tcmp`
+- `bstart_tcmps`
+- `bstart_tcolargmax`
+- `bstart_tcolargmin`
+- `bstart_tcolexpand`
+- `bstart_tcolexpandadd`
+- `bstart_tcolexpanddiv`
+- `bstart_tcolexpandexpdif`
+- `bstart_tcolexpandmax`
+- `bstart_tcolexpandmin`
+- `bstart_tcolexpandmul`
+- `bstart_tcolexpandsub`
+- `bstart_tcolmax`
+- `bstart_tcolmin`
+- `bstart_tcolprod`
+- `bstart_tcolsum`
+- `bstart_tconcat`
+- `bstart_tcvt`
+- `bstart_tdeinterleave`
+- `bstart_tdequant`
+- `bstart_tdiv`
+- `bstart_tdivs`
+- `bstart_texp`
+- `bstart_texpands`
+- `bstart_textract`
+- `bstart_tfillpad`
+- `bstart_tfree`
+- `bstart_tgather`
+- `bstart_tgatherb`
+- `bstart_thistogram`
+- `bstart_timg2col`
+- `bstart_tinsert`
+- `bstart_tinterleave`
+- `bstart_tlog`
+- `bstart_tmax`
+- `bstart_tmaxs`
+- `bstart_tmin`
+- `bstart_tmins`
+- `bstart_tmrgsort`
+- `bstart_tmul`
+- `bstart_tmuls`
+- `bstart_tneg`
+- `bstart_tnot`
+- `bstart_tor`
+- `bstart_tors`
+- `bstart_tpartadd`
+- `bstart_tpartargmax`
+- `bstart_tpartargmin`
+- `bstart_tpartmax`
+- `bstart_tpartmin`
+- `bstart_tpartmul`
+- `bstart_tpop`
+- `bstart_tprelu`
+- `bstart_tpush`
+- `bstart_tquant`
+- `bstart_trecip`
+- `bstart_trelu`
+- `bstart_trem`
+- `bstart_trems`
+- `bstart_treshape`
+- `bstart_trowargmax`
+- `bstart_trowargmin`
+- `bstart_trowexpand`
+- `bstart_trowexpandadd`
+- `bstart_trowexpanddiv`
+- `bstart_trowexpandexpdif`
+- `bstart_trowexpandmax`
+- `bstart_trowexpandmin`
+- `bstart_trowexpandmul`
+- `bstart_trowexpandsub`
+- `bstart_trowmax`
+- `bstart_trowmin`
+- `bstart_trowprod`
+- `bstart_trowsum`
+- `bstart_trsqrt`
+- `bstart_tscatter`
+- `bstart_tsel`
+- `bstart_tsels`
+- `bstart_tshl`
+- `bstart_tshls`
+- `bstart_tshr`
+- `bstart_tshrs`
+- `bstart_tsort`
+- `bstart_tsqrt`
+- `bstart_tsub`
+- `bstart_tsubs`
+- `bstart_ttrans`
+- `bstart_ttri`
+- `bstart_txor`
+- `bstart_txors`
 
 ## Missing Spec Mnemonics (First 200)
 
-- `V.LBI`
-- `V.LBI.BRG`
-- `V.LBUI`
-- `V.LBUI.BRG`
-- `V.LD`
-- `V.LD.ADD`
-- `V.LD.AND`
-- `V.LD.BRG`
-- `V.LD.MAX`
-- `V.LD.MIN`
-- `V.LD.OR`
-- `V.LD.XOR`
-- `V.LDI`
-- `V.LDI.BRG`
-- `V.LDI.U`
-- `V.LDI.U.BRG`
-- `V.LHI`
-- `V.LHI.BRG`
-- `V.LHI.U`
-- `V.LHI.U.BRG`
-- `V.LHUI`
-- `V.LHUI.BRG`
-- `V.LHUI.U`
-- `V.LHUI.U.BRG`
-- `V.LW.ADD`
-- `V.LW.AND`
-- `V.LW.MAX`
-- `V.LW.MIN`
-- `V.LW.OR`
-- `V.LW.XOR`
-- `V.LWI`
-- `V.LWI.BRG`
-- `V.LWI.U`
-- `V.LWI.U.BRG`
-- `V.LWU`
-- `V.LWU.BRG`
-- `V.LWUI`
-- `V.LWUI.BRG`
-- `V.LWUI.U`
-- `V.LWUI.U.BRG`
-- `V.QPOP`
-- `V.QPUSH`
-- `V.SBI`
-- `V.SBI.BRG`
-- `V.SD`
-- `V.SD.ADD`
-- `V.SD.AND`
-- `V.SD.BRG`
-- `V.SD.MAX`
-- `V.SD.MIN`
-- `V.SD.OR`
-- `V.SD.U`
-- `V.SD.U.BRG`
-- `V.SD.XOR`
-- `V.SDI`
-- `V.SDI.BRG`
-- `V.SDI.U`
-- `V.SDI.U.BRG`
-- `V.SH.U`
-- `V.SH.U.BRG`
-- `V.SHFL.BFLY`
-- `V.SHFL.DOWN`
-- `V.SHFL.IDX`
-- `V.SHFL.UP`
-- `V.SHFLI.BFLY`
-- `V.SHFLI.DOWN`
-- `V.SHFLI.IDX`
-- `V.SHFLI.UP`
-- `V.SHI`
-- `V.SHI.BRG`
-- `V.SHI.U`
-- `V.SHI.U.BRG`
-- `V.SW.ADD`
-- `V.SW.AND`
-- `V.SW.MAX`
-- `V.SW.MIN`
-- `V.SW.OR`
-- `V.SW.U`
-- `V.SW.U.BRG`
-- `V.SW.XOR`
-- `V.SWI`
-- `V.SWI.BRG`
-- `V.SWI.U`
-- `V.SWI.U.BRG`
-- `XB`
 
 ## Missing Spec Forms (First 200)
-
-- `B.IOT [len=32 mask=0x1fc0707f match=0x1c04013]`
-- `B.IOT [len=32 mask=0x9fff707f match=0x1c05013]`
-- `BSTART.MPAR [len=32 mask=0xf9ffffff match=0x1181]`
-- `BSTART.MSEQ [len=32 mask=0xf9ffffff match=0x9181]`
-- `BSTART.VPAR [len=32 mask=0xf9ffffff match=0x21181]`
-- `BSTART.VSEQ [len=32 mask=0xf9ffffff match=0x29181]`
-- `V.LBI [len=64 mask=0x707f0000207f match=0x190000007f]`
-- `V.LBI.BRG [len=64 mask=0x707f0000207f match=0x190000207f]`
-- `V.LBUI [len=64 mask=0x707f0000207f match=0x40190000007f]`
-- `V.LBUI.BRG [len=64 mask=0x707f0000207f match=0x40190000207f]`
-- `V.LD [len=64 mask=0x600707ffe00207f match=0x30090000007f]`
-- `V.LD.ADD [len=64 mask=0xf800707ffc00707f match=0xb0000207f]`
-- `V.LD.AND [len=64 mask=0xf800707ffc00707f match=0x100b0000207f]`
-- `V.LD.BRG [len=64 mask=0x600707ffe00207f match=0x30090000207f]`
-- `V.LD.MAX [len=64 mask=0xf800707ffc00707f match=0x400b0000207f]`
-- `V.LD.MIN [len=64 mask=0xf800707ffc00707f match=0x500b0000207f]`
-- `V.LD.OR [len=64 mask=0xf800707ffc00707f match=0x200b0000207f]`
-- `V.LD.XOR [len=64 mask=0xf800707ffc00707f match=0x300b0000207f]`
-- `V.LDI [len=64 mask=0x707f0000207f match=0x30190000007f]`
-- `V.LDI.BRG [len=64 mask=0x707f0000207f match=0x30190000207f]`
-- `V.LDI.U [len=64 mask=0x707f0000207f match=0x30290000007f]`
-- `V.LDI.U.BRG [len=64 mask=0x707f0000207f match=0x30290000207f]`
-- `V.LHI [len=64 mask=0x707f0000207f match=0x10190000007f]`
-- `V.LHI.BRG [len=64 mask=0x707f0000207f match=0x10190000207f]`
-- `V.LHI.U [len=64 mask=0x707f0000207f match=0x10290000007f]`
-- `V.LHI.U.BRG [len=64 mask=0x707f0000207f match=0x10290000207f]`
-- `V.LHUI [len=64 mask=0x707f0000207f match=0x50190000007f]`
-- `V.LHUI.BRG [len=64 mask=0x707f0000207f match=0x50190000207f]`
-- `V.LHUI.U [len=64 mask=0x707f0000207f match=0x50290000007f]`
-- `V.LHUI.U.BRG [len=64 mask=0x707f0000207f match=0x50290000207f]`
-- `V.LW.ADD [len=64 mask=0xf800707ffc00707f match=0xb0000007f]`
-- `V.LW.AND [len=64 mask=0xf800707ffc00707f match=0x100b0000007f]`
-- `V.LW.MAX [len=64 mask=0xf800707ffc00707f match=0x400b0000007f]`
-- `V.LW.MIN [len=64 mask=0xf800707ffc00707f match=0x500b0000007f]`
-- `V.LW.OR [len=64 mask=0xf800707ffc00707f match=0x200b0000007f]`
-- `V.LW.XOR [len=64 mask=0xf800707ffc00707f match=0x300b0000007f]`
-- `V.LWI [len=64 mask=0x707f0000207f match=0x20190000007f]`
-- `V.LWI.BRG [len=64 mask=0x707f0000207f match=0x20190000207f]`
-- `V.LWI.U [len=64 mask=0x707f0000207f match=0x20290000007f]`
-- `V.LWI.U.BRG [len=64 mask=0x707f0000207f match=0x20290000207f]`
-- `V.LWU [len=64 mask=0x600707ffe00207f match=0x60090000007f]`
-- `V.LWU.BRG [len=64 mask=0x600707ffe00207f match=0x60090000207f]`
-- `V.LWUI [len=64 mask=0x707f0000207f match=0x60190000007f]`
-- `V.LWUI.BRG [len=64 mask=0x707f0000207f match=0x60190000207f]`
-- `V.LWUI.U [len=64 mask=0x707f0000207f match=0x60290000007f]`
-- `V.LWUI.U.BRG [len=64 mask=0x707f0000207f match=0x60290000207f]`
-- `V.QPOP [len=64 mask=0xfff0707ffff0707f match=0x207d0000007f]`
-- `V.QPUSH [len=64 mask=0xfe00707ffe00707f match=0x107d0000007f]`
-- `V.SBI [len=64 mask=0x707f0000207f match=0x590000007f]`
-- `V.SBI.BRG [len=64 mask=0x707f0000207f match=0x590000207f]`
-- `V.SD [len=64 mask=0x6007fff0600207f match=0x30490000007f]`
-- `V.SD.ADD [len=64 mask=0xfc007ffff8007fff match=0xb0000307f]`
-- `V.SD.AND [len=64 mask=0xfc007ffff8007fff match=0x100b0000307f]`
-- `V.SD.BRG [len=64 mask=0x6007fff0600207f match=0x30490000207f]`
-- `V.SD.MAX [len=64 mask=0xfc007ffff8007fff match=0x400b0000307f]`
-- `V.SD.MIN [len=64 mask=0xfc007ffff8007fff match=0x500b0000307f]`
-- `V.SD.OR [len=64 mask=0xfc007ffff8007fff match=0x200b0000307f]`
-- `V.SD.U [len=64 mask=0x6007fff0600207f match=0x70490000007f]`
-- `V.SD.U.BRG [len=64 mask=0x6007fff0600207f match=0x70490000207f]`
-- `V.SD.XOR [len=64 mask=0xfc007ffff8007fff match=0x300b0000307f]`
-- `V.SDI [len=64 mask=0x707f0000207f match=0x30590000007f]`
-- `V.SDI.BRG [len=64 mask=0x707f0000207f match=0x30590000207f]`
-- `V.SDI.U [len=64 mask=0x707f0000207f match=0x70590000007f]`
-- `V.SDI.U.BRG [len=64 mask=0x707f0000207f match=0x70590000207f]`
-- `V.SH.U [len=64 mask=0x6007fff0600207f match=0x50490000007f]`
-- `V.SH.U.BRG [len=64 mask=0x6007fff0600207f match=0x50490000207f]`
-- `V.SHFL.BFLY [len=64 mask=0x7f0707f07f0707f match=0x201d0000007f]`
-- `V.SHFL.DOWN [len=64 mask=0x600707f0600707f match=0x101d0000007f]`
-- `V.SHFL.IDX [len=64 mask=0x600707f0600707f match=0x301d0000007f]`
-- `V.SHFL.UP [len=64 mask=0x600707f0600707f match=0x1d0000007f]`
-- `V.SHFLI.BFLY [len=64 mask=0x1f0707f01f0707f match=0x602d0000007f]`
-- `V.SHFLI.DOWN [len=64 mask=0x707f0000707f match=0x502d0000007f]`
-- `V.SHFLI.IDX [len=64 mask=0x707f0000707f match=0x702d0000007f]`
-- `V.SHFLI.UP [len=64 mask=0x707f0000707f match=0x402d0000007f]`
-- `V.SHI [len=64 mask=0x707f0000207f match=0x10590000007f]`
-- `V.SHI.BRG [len=64 mask=0x707f0000207f match=0x10590000207f]`
-- `V.SHI.U [len=64 mask=0x707f0000207f match=0x50590000007f]`
-- `V.SHI.U.BRG [len=64 mask=0x707f0000207f match=0x50590000207f]`
-- `V.SW.ADD [len=64 mask=0xfc007ffff8007fff match=0xb0000107f]`
-- `V.SW.AND [len=64 mask=0xfc007ffff8007fff match=0x100b0000107f]`
-- `V.SW.MAX [len=64 mask=0xfc007ffff8007fff match=0x400b0000107f]`
-- `V.SW.MIN [len=64 mask=0xfc007ffff8007fff match=0x500b0000107f]`
-- `V.SW.OR [len=64 mask=0xfc007ffff8007fff match=0x200b0000107f]`
-- `V.SW.U [len=64 mask=0x6007fff0600207f match=0x60490000007f]`
-- `V.SW.U.BRG [len=64 mask=0x6007fff0600207f match=0x60490000207f]`
-- `V.SW.XOR [len=64 mask=0xfc007ffff8007fff match=0x300b0000107f]`
-- `V.SWI [len=64 mask=0x707f0000207f match=0x20590000007f]`
-- `V.SWI.BRG [len=64 mask=0x707f0000207f match=0x20590000207f]`
-- `V.SWI.U [len=64 mask=0x707f0000207f match=0x60590000007f]`
-- `V.SWI.U.BRG [len=64 mask=0x707f0000207f match=0x60590000207f]`
-- `XB [len=32 mask=0x7fff match=0x6f81]`
diff --git a/docs/bringup/gates/qemu_opcode_sync_latest.json b/docs/bringup/gates/qemu_opcode_sync_latest.json
index b8463a0f..a2d7a24f 100644
--- a/docs/bringup/gates/qemu_opcode_sync_latest.json
+++ b/docs/bringup/gates/qemu_opcode_sync_latest.json
@@ -1,10 +1,10 @@
 {
-  "allowlist": "/home/jialewang/workspace/superscalarNPU/linx-isa/docs/bringup/qemu_opcode_sync_allowlist.json",
+  "allowlist": "/private/tmp/linx-isa-v0571/docs/bringup/qemu_opcode_sync_allowlist.json",
   "decode_only": [],
   "decode_only_unexpected": [],
   "decode_only_unexpected_count": 0,
-  "decode_unique_patterns": 678,
-  "generated_at_utc": "2026-07-25 03:02:19Z",
+  "decode_unique_patterns": 855,
+  "generated_at_utc": "2026-08-02 12:51:45Z",
   "have_opcode_meta": true,
   "id_mismatch": [],
   "id_mismatch_count": 0,
@@ -16,9 +16,9 @@
   "meta_only": [],
   "meta_only_unexpected": [],
   "meta_only_unexpected_count": 0,
-  "meta_unique_decode_patterns": 678,
-  "meta_unique_non_internal": 678,
-  "qemu_root": "/home/jialewang/workspace/superscalarNPU/linx-isa/emulator/qemu",
+  "meta_unique_decode_patterns": 855,
+  "meta_unique_non_internal": 855,
+  "qemu_root": "/private/tmp/linx-isa-v0571/emulator/qemu",
   "result": {
     "classification": "qemu_opcode_meta_sync_ok",
     "ok": true
diff --git a/docs/bringup/gates/qemu_opcode_sync_latest.md b/docs/bringup/gates/qemu_opcode_sync_latest.md
index 2073b738..2d1e2eff 100644
--- a/docs/bringup/gates/qemu_opcode_sync_latest.md
+++ b/docs/bringup/gates/qemu_opcode_sync_latest.md
@@ -1,10 +1,10 @@
 # QEMU Opcode Sync Audit
 
-- Generated (UTC): `2026-07-25 03:02:19Z`
+- Generated (UTC): `2026-08-02 12:51:45Z`
 - Result: `qemu_opcode_meta_sync_ok`
 - OK: `true`
-- Decode forms (unique): `678`
-- Meta mnemonics (unique, non-internal): `678`
+- Decode forms (unique): `855`
+- Meta mnemonics (unique, non-internal): `855`
 
 ## Drift Summary
 
diff --git a/docs/bringup/gates/qemu_translation_coverage_latest.json b/docs/bringup/gates/qemu_translation_coverage_latest.json
index 7aaa13c7..cb47c43c 100644
--- a/docs/bringup/gates/qemu_translation_coverage_latest.json
+++ b/docs/bringup/gates/qemu_translation_coverage_latest.json
@@ -1,5 +1,5 @@
 {
-  "coverage_count": 731,
+  "coverage_count": 728,
   "coverage_ratio_percent": 100.0,
   "covered_by_object": {
     "01_arithmetic.o": [
@@ -301,6 +301,7 @@
       "HL.SW.PCR",
       "LB",
       "LBUI",
+      "LDI",
       "LUI",
       "OR",
       "ORIW",
@@ -474,81 +475,6 @@
       "SSRSWAP",
       "SWI"
     ],
-    "12_v03_vector_tile.o": [
-      "ADDI",
-      "ADDIW",
-      "ADDTPC",
-      "ADDW",
-      "AND",
-      "ANDI",
-      "ANDIW",
-      "B.IOR",
-      "B.NE",
-      "B.NZ",
-      "B.TEXT",
-      "B.Z",
-      "BSTART",
-      "BSTART.CALL",
-      "BSTART.MPAR",
-      "BSTART.MSEQ",
-      "BSTART.STD",
-      "BSTART.TEPL",
-      "BSTART.VPAR",
-      "BSTART.VSEQ",
-      "BSTOP",
-      "C.ADD",
-      "C.ADDI",
-      "C.B.DIMI",
-      "C.BSTART",
-      "C.BSTART.MPAR",
-      "C.BSTART.MSEQ",
-      "C.BSTART.STD",
-      "C.BSTOP",
-      "C.LWI",
-      "C.MOVI",
-      "C.MOVR",
-      "C.SETC.EQ",
-      "C.SETC.NE",
-      "C.SETC.TGT",
-      "C.SEXT.W",
-      "C.SWI",
-      "C.ZEXT.W",
-      "FENTRY",
-      "FRET.STK",
-      "HL.BSTART.CALL",
-      "HL.BSTART.STD",
-      "HL.LUI",
-      "HL.LW.PCR",
-      "HL.SUBIW",
-      "HL.SW.PCR",
-      "J",
-      "LB",
-      "LBUI",
-      "LDI",
-      "LUI",
-      "LW",
-      "LWUI",
-      "OR",
-      "SDI",
-      "SETC.NEI",
-      "SLL",
-      "SRA",
-      "SRL",
-      "SRLI",
-      "SRLIW",
-      "SWI",
-      "UCVTF",
-      "V.ADD",
-      "V.CMP.EQ",
-      "V.CMP.LTU",
-      "V.CMP.LTUI",
-      "V.FADD",
-      "V.FMUL",
-      "V.LW.BRG",
-      "V.RDOR",
-      "V.SW",
-      "V.SW.BRG"
-    ],
     "12_v057_vector_tile.o": [
       "ADDI",
       "ADDIW",
@@ -624,77 +550,6 @@
       "V.SW",
       "V.SW.BRG"
     ],
-    "13_v03_vector_ops_matrix.o": [
-      "ADDI",
-      "ADDIW",
-      "ADDTPC",
-      "ADDW",
-      "AND",
-      "ANDI",
-      "ANDIW",
-      "ANDW",
-      "B.IOR",
-      "B.TEXT",
-      "BSTART",
-      "BSTART.CALL",
-      "BSTART.MSEQ",
-      "BSTART.STD",
-      "BSTART.TEPL",
-      "BSTOP",
-      "C.ADD",
-      "C.ADDI",
-      "C.B.DIMI",
-      "C.BSTART",
-      "C.BSTART.MSEQ",
-      "C.BSTART.STD",
-      "C.BSTOP",
-      "C.LWI",
-      "C.MOVI",
-      "C.MOVR",
-      "C.SETC.EQ",
-      "C.SETC.NE",
-      "C.SETC.TGT",
-      "C.SEXT.W",
-      "C.SWI",
-      "C.ZEXT.W",
-      "CMP.LTUI",
-      "FENTRY",
-      "FRET.STK",
-      "HL.BSTART.CALL",
-      "HL.BSTART.STD",
-      "HL.LUI",
-      "HL.LW.PCR",
-      "HL.SW.PCR",
-      "LB",
-      "LBUI",
-      "LUI",
-      "LW",
-      "LWI",
-      "MULW",
-      "OR",
-      "ORW",
-      "SDI",
-      "SETC.NEI",
-      "SLL",
-      "SLLI",
-      "SRA",
-      "SRL",
-      "SRLI",
-      "SRLIW",
-      "SUBIW",
-      "SUBW",
-      "SWI",
-      "UCVTF",
-      "V.ADD",
-      "V.CMP.LT",
-      "V.FABS",
-      "V.FADD",
-      "V.FMUL",
-      "V.LW.BRG",
-      "V.MUL",
-      "V.SUB",
-      "V.SW.BRG"
-    ],
     "13_v057_vector_ops_matrix.o": [
       "ADDI",
       "ADDIW",
@@ -873,7 +728,6 @@
       "FRET.STK",
       "HL.BSTART.CALL",
       "HL.BSTART.STD",
-      "HL.LDIP",
       "HL.LUI",
       "HL.LWU.PCR",
       "HL.SDIP",
@@ -916,17 +770,20 @@
       "XORI",
       "XORW"
     ],
-    "21_freestanding_runtime.o": [
+    "17_deepseek_tilekernels.o": [
       "ADDI",
       "ADDIW",
       "ADDTPC",
       "ADDW",
+      "AND",
       "ANDI",
       "ANDIW",
+      "ANDW",
       "BSTART",
       "BSTART.CALL",
       "BSTART.STD",
       "BSTOP",
+      "C.ADD",
       "C.ADDI",
       "C.BSTART",
       "C.BSTART.STD",
@@ -935,73 +792,115 @@
       "C.LWI",
       "C.MOVI",
       "C.MOVR",
+      "C.SDI",
       "C.SETC.EQ",
       "C.SETC.NE",
       "C.SEXT.W",
       "C.SWI",
       "C.ZEXT.W",
+      "CMP.LTUI",
+      "CSEL",
       "FENTRY",
+      "FEQ",
+      "FGE",
+      "FLT",
       "FRET.STK",
       "HL.BSTART.CALL",
       "HL.BSTART.STD",
+      "HL.LB.PCR",
+      "HL.LBU.PCR",
+      "HL.LDIP",
       "HL.LUI",
+      "HL.LWU.PCR",
+      "HL.SDI.PO",
+      "HL.SDI.PR",
+      "HL.SDIP",
+      "HL.SWI.PO",
       "LB",
+      "LBI",
       "LBUI",
       "LDI",
       "LUI",
+      "LW",
+      "LWI",
+      "LWU",
+      "LWUI",
       "MUL",
+      "MULW",
       "OR",
+      "ORW",
+      "SB",
+      "SCVTF",
       "SDI",
       "SETC.GEU",
-      "SETC.LTU",
+      "SETC.LT",
+      "SETC.NEI",
+      "SHI",
       "SLL",
+      "SLLI",
       "SRA",
       "SRL",
       "SRLI",
-      "SWI"
+      "SRLIW",
+      "SUB",
+      "SUBI",
+      "SUBIW",
+      "SUBW",
+      "SWI",
+      "UCVTF",
+      "XOR",
+      "XORI",
+      "XORW"
     ],
-    "41_v056_isa_forms.o": [
-      "B.ARG",
-      "B.DIM",
-      "B.IOR",
-      "BSTART.ACCCVT",
-      "BSTART.CUBE",
-      "BSTART.FIXP",
-      "BSTART.MPAR",
-      "BSTART.MSEQ",
-      "BSTART.TEPL",
-      "BSTART.TLOAD",
-      "BSTART.TMATMUL",
-      "BSTART.TMATMUL.ACC",
-      "BSTART.TMOV",
-      "BSTART.TSTORE",
-      "BSTART.VPAR",
-      "BSTART.VSEQ",
+    "21_freestanding_runtime.o": [
+      "ADDI",
+      "ADDIW",
+      "ADDTPC",
+      "ADDW",
+      "ANDI",
+      "ANDIW",
+      "BSTART",
+      "BSTART.CALL",
+      "BSTART.STD",
       "BSTOP",
-      "C.BSTART.MPAR",
-      "C.BSTART.MSEQ",
-      "C.BSTART.SYS",
-      "C.BSTART.VPAR",
-      "C.BSTART.VSEQ",
+      "C.ADDI",
+      "C.BSTART",
+      "C.BSTART.STD",
       "C.BSTOP",
-      "C.SSRGET",
-      "ERCOV",
-      "ESAVE",
+      "C.LDI",
+      "C.LWI",
+      "C.MOVI",
+      "C.MOVR",
+      "C.SETC.EQ",
+      "C.SETC.NE",
+      "C.SEXT.W",
+      "C.SWI",
+      "C.ZEXT.W",
       "FENTRY",
       "FRET.STK",
-      "HL.CASD",
-      "HL.CASW",
-      "L.BSTART.FP",
-      "L.BSTART.STD",
-      "L.BSTART.SYS"
+      "HL.BSTART.CALL",
+      "HL.BSTART.STD",
+      "HL.LUI",
+      "LB",
+      "LBUI",
+      "LDI",
+      "LUI",
+      "MUL",
+      "OR",
+      "SDI",
+      "SETC.GEU",
+      "SETC.LTU",
+      "SLL",
+      "SRA",
+      "SRL",
+      "SRLI",
+      "SWI"
     ],
     "41_v057_isa_forms.o": [
-      "B.ARG",
+      "B.DATR",
       "B.DIM",
       "B.IOR",
       "BSTART.ACCCVT",
-      "BSTART.CUBE",
-      "BSTART.FIXP",
       "BSTART.MPAR",
       "BSTART.MSEQ",
       "BSTART.TEPL",
@@ -1043,7 +942,6 @@
       "ANDIW",
       "ANDW",
       "ASSERT",
-      "B.ARG",
       "B.CATR",
       "B.DATR",
       "B.DIM",
@@ -1068,8 +966,6 @@
       "BSTART",
       "BSTART.ACCCVT",
       "BSTART.CALL",
-      "BSTART.CUBE",
-      "BSTART.FIXP",
       "BSTART.FP",
       "BSTART.MGATHER",
       "BSTART.MGATHER.CAS",
@@ -1825,6 +1721,28 @@
       "SRL",
       "SUBI"
     ],
+    "engram.o": [
+      "ADDI",
+      "AND",
+      "B.DIM",
+      "B.IOR",
+      "B.IOT",
+      "BSTART",
+      "BSTART.STD",
+      "BSTART.TLOAD",
+      "BSTART.TSTORE",
+      "C.BSTART",
+      "C.BSTART.STD",
+      "C.MOVI",
+      "FENTRY",
+      "FRET.STK",
+      "HL.LUI",
+      "LUI",
+      "LWUI",
+      "SLL",
+      "SRL",
+      "SUBIW"
+    ],
     "fa_performance.o": [
       "ADDI",
       "ADDW",
@@ -2303,19 +2221,6 @@
       "SRA",
       "SWI"
     ],
-    "mamulb.o": [
-      "ADDI",
-      "C.BSTART",
-      "C.BSTART.STD",
-      "C.MOVR",
-      "C.SETC.NE",
-      "FENTRY",
-      "FRET.STK",
-      "LW",
-      "MADDW",
-      "SLLI",
-      "SW"
-    ],
     "math.o": [
       "ADDI",
       "ADDIW",
@@ -2359,70 +2264,166 @@
       "SETC.EQI",
       "SETC.GEI",
       "SETC.LT",
-      "SETC.LTI",
-      "SETC.LTU",
+      "SETC.LTI",
+      "SETC.LTU",
+      "SLL",
+      "SRL",
+      "SUBIW",
+      "UCVTF",
+      "XOR",
+      "XORI",
+      "XORIW"
+    ],
+    "mem.o": [
+      "ADDI",
+      "ADDW",
+      "ANDI",
+      "C.ADD",
+      "C.BSTART",
+      "C.BSTART.STD",
+      "C.BSTOP",
+      "C.LWI",
+      "C.MOVI",
+      "C.MOVR",
+      "C.SETC.EQ",
+      "C.SETC.NE",
+      "C.SEXT.W",
+      "C.SUB",
+      "C.SWI",
+      "FENTRY",
+      "FRET.STK",
+      "LB",
+      "LBI",
+      "LBUI",
+      "SB",
+      "SBI",
+      "SETC.GEU",
+      "SETC.LTU",
+      "SETC.LTUI",
+      "SUBI",
+      "SUBW"
+    ],
+    "mhc.o": [
+      "ADDI",
+      "ADDIW",
+      "ADDW",
+      "AND",
+      "B.DIM",
+      "B.IOR",
+      "B.IOT",
+      "BSTART",
+      "BSTART.STD",
+      "BSTART.TLOAD",
+      "BSTART.TSTORE",
+      "C.BSTART",
+      "C.BSTART.STD",
+      "C.MOVI",
+      "C.MOVR",
+      "C.SEXT.W",
+      "CMP.LTI",
+      "CSEL",
+      "FENTRY",
+      "FRET.STK",
+      "HL.LUI",
+      "LUI",
+      "SCVTF",
+      "SETC.GE",
+      "SETC.LT",
       "SLL",
+      "SLLI",
       "SRL",
       "SUBIW",
-      "UCVTF",
-      "XOR",
-      "XORI",
-      "XORIW"
+      "SUBW"
     ],
-    "mem.o": [
+    "mla_attention_demo.o": [
       "ADDI",
-      "ADDW",
-      "ANDI",
       "C.ADD",
       "C.BSTART",
       "C.BSTART.STD",
-      "C.BSTOP",
-      "C.LWI",
+      "C.LDI",
       "C.MOVI",
       "C.MOVR",
-      "C.SETC.EQ",
+      "C.SDI",
       "C.SETC.NE",
-      "C.SEXT.W",
-      "C.SUB",
-      "C.SWI",
       "FENTRY",
       "FRET.STK",
-      "LB",
-      "LBI",
-      "LBUI",
-      "SB",
-      "SBI",
-      "SETC.GEU",
-      "SETC.LTU",
-      "SETC.LTUI",
-      "SUBI",
-      "SUBW"
+      "HL.BSTART.CALL",
+      "HL.BSTART.STD",
+      "HL.LDIP",
+      "HL.LWU.PCR",
+      "LDI",
+      "LUI",
+      "LW",
+      "SDI",
+      "SLL",
+      "SLLI",
+      "SRL",
+      "SW",
+      "SWI"
     ],
-    "mla_attention_demo.o": [
+    "moe.o": [
       "ADDI",
+      "ADDIW",
+      "ADDW",
+      "ANDIW",
+      "B.DIM",
+      "B.IOR",
+      "B.IOT",
+      "BSTART",
+      "BSTART.STD",
+      "BSTART.TLOAD",
+      "BSTART.TSTORE",
       "C.ADD",
       "C.BSTART",
       "C.BSTART.STD",
+      "C.BSTOP",
       "C.LDI",
+      "C.LWI",
       "C.MOVI",
       "C.MOVR",
       "C.SDI",
+      "C.SETC.EQ",
       "C.SETC.NE",
+      "C.SEXT.W",
+      "C.SWI",
+      "CMP.LT",
+      "CMP.LTI",
+      "CSEL",
       "FENTRY",
+      "FLT",
       "FRET.STK",
       "HL.BSTART.CALL",
       "HL.BSTART.STD",
       "HL.LDIP",
-      "HL.LWU.PCR",
+      "HL.SWI.PO",
       "LDI",
       "LUI",
       "LW",
+      "LWI",
+      "LWU",
+      "LWUI",
+      "MULW",
       "SDI",
+      "SETC.EQI",
+      "SETC.GE",
+      "SETC.GEI",
+      "SETC.GEU",
+      "SETC.LT",
+      "SETC.LTI",
       "SLL",
       "SLLI",
+      "SLLIW",
+      "SRAI",
+      "SRAIW",
       "SRL",
+      "SRLIW",
+      "SUBI",
+      "SUBIW",
+      "SUBW",
       "SW",
-      "SWI"
+      "SWI",
+      "UCVTF",
+      "XORI"
     ],
     "permute_nhwc_nchw_fp32.o": [
       "ADDI",
@@ -2446,6 +2447,42 @@
       "SRL",
       "SUBI"
     ],
+    "quant.o": [
+      "ADDI",
+      "ADDIW",
+      "ADDW",
+      "B.DIM",
+      "B.IOR",
+      "B.IOT",
+      "BSTART",
+      "BSTART.STD",
+      "BSTART.TLOAD",
+      "BSTART.TSTORE",
+      "C.BSTART",
+      "C.BSTART.STD",
+      "C.LDI",
+      "C.MOVI",
+      "C.MOVR",
+      "C.SDI",
+      "C.SETC.EQ",
+      "C.SEXT.W",
+      "CMP.LTI",
+      "CSEL",
+      "FENTRY",
+      "FRET.STK",
+      "HL.LUI",
+      "HL.SDIP",
+      "LDI",
+      "LUI",
+      "SDI",
+      "SETC.GE",
+      "SETC.LT",
+      "SLL",
+      "SLLI",
+      "SRL",
+      "SUBIW",
+      "SUBW"
+    ],
     "relu_fp32.o": [
       "ADDI",
       "C.BSTART",
@@ -3009,6 +3046,43 @@
       "SLLI",
       "SW"
     ],
+    "transpose.o": [
+      "ADDI",
+      "ADDIW",
+      "ADDW",
+      "B.DIM",
+      "B.IOR",
+      "B.IOT",
+      "BSTART",
+      "BSTART.STD",
+      "BSTART.TLOAD",
+      "BSTART.TSTORE",
+      "C.ADD",
+      "C.BSTART",
+      "C.BSTART.STD",
+      "C.LDI",
+      "C.MOVI",
+      "C.MOVR",
+      "C.SDI",
+      "C.SETC.EQ",
+      "C.SEXT.W",
+      "CMP.LTI",
+      "CSEL",
+      "FENTRY",
+      "FRET.STK",
+      "HL.LDIP",
+      "LDI",
+      "MULW",
+      "SDI",
+      "SETC.GE",
+      "SETC.LT",
+      "SLL",
+      "SLLI",
+      "SLLIW",
+      "SRL",
+      "SUBIW",
+      "SUBW"
+    ],
     "transpose_large_fp32.o": [
       "ADDI",
       "C.BSTART",
@@ -3128,13 +3202,13 @@
     "ANDIW": 1,
     "ANDW": 1,
     "ASSERT": 1,
-    "B": 16,
+    "B": 15,
     "BC": 2,
     "BCNT": 1,
     "BIC": 1,
     "BIS": 1,
     "BSE": 1,
-    "BSTART": 34,
+    "BSTART": 32,
     "BSTOP": 1,
     "BWE": 1,
     "BWI": 1,
@@ -3305,18 +3379,18 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
       "argmax_fp32.o",
       "concat_fp32.o",
+      "engram.o",
       "fa_performance.o",
       "flash_attention.o",
       "flash_attention_cube_fp16.o",
@@ -3333,11 +3407,13 @@
       "gemm_performance.o",
       "gqa_fp16.o",
       "main.o",
-      "mamulb.o",
       "math.o",
       "mem.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -3356,6 +3432,7 @@
       "tanh_fp32.o",
       "tload_store.o",
       "tmatmul_acc.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -3373,23 +3450,26 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
       "math.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "softfp.o",
       "softmax_fp32.o",
       "sparse_attention_local_fp16.o",
-      "syscall.o"
+      "syscall.o",
+      "transpose.o"
     ],
     "ADDTPC": [
       "01_arithmetic.o",
@@ -3402,13 +3482,12 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
@@ -3426,11 +3505,10 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
@@ -3443,6 +3521,9 @@
       "gqa_fp16.o",
       "math.o",
       "mem.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
@@ -3451,6 +3532,7 @@
       "sparse_attention_local_fp16.o",
       "stdlib.o",
       "tanh_fp32.o",
+      "transpose.o",
       "unique_i32.o"
     ],
     "AND": [
@@ -3460,13 +3542,14 @@
       "06_floating_point.o",
       "07_atomic.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
+      "engram.o",
       "math.o",
+      "mhc.o",
       "softfp.o",
       "stdlib.o"
     ],
@@ -3481,12 +3564,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "gemm_basic.o",
@@ -3508,26 +3590,26 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
       "main.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "softfp.o",
       "sparse_attention_local_fp16.o"
     ],
     "ANDW": [
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
@@ -3539,22 +3621,22 @@
     "ASSERT": [
       "99_spec_decode_qemu.o"
     ],
-    "B.ARG": [
-      "41_v056_isa_forms.o",
-      "41_v057_isa_forms.o",
-      "99_spec_decode_qemu.o"
-    ],
     "B.CATR": [
       "04_branch.o",
       "99_spec_decode_qemu.o"
     ],
     "B.DATR": [
+      "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
     "B.DIM": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
-      "99_spec_decode_qemu.o"
+      "99_spec_decode_qemu.o",
+      "engram.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
+      "transpose.o"
     ],
     "B.EQ": [
       "99_spec_decode_qemu.o"
@@ -3570,16 +3652,23 @@
     ],
     "B.IOR": [
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
-      "99_spec_decode_qemu.o"
+      "99_spec_decode_qemu.o",
+      "engram.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
+      "transpose.o"
     ],
     "B.IOT": [
-      "99_spec_decode_qemu.o"
+      "99_spec_decode_qemu.o",
+      "engram.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
+      "transpose.o"
     ],
     "B.LT": [
       "99_spec_decode_qemu.o"
@@ -3588,25 +3677,20 @@
       "99_spec_decode_qemu.o"
     ],
     "B.NE": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "99_spec_decode_qemu.o"
     ],
     "B.NZ": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "99_spec_decode_qemu.o"
     ],
     "B.TEXT": [
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
     "B.Z": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "99_spec_decode_qemu.o"
     ],
@@ -3640,19 +3724,22 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
+      "engram.o",
       "main.o",
-      "softfp.o"
+      "mhc.o",
+      "moe.o",
+      "quant.o",
+      "softfp.o",
+      "transpose.o"
     ],
     "BSTART.ACCCVT": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -3667,27 +3754,16 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "main.o",
       "softfp.o"
     ],
-    "BSTART.CUBE": [
-      "41_v056_isa_forms.o",
-      "41_v057_isa_forms.o",
-      "99_spec_decode_qemu.o"
-    ],
-    "BSTART.FIXP": [
-      "41_v056_isa_forms.o",
-      "41_v057_isa_forms.o",
-      "99_spec_decode_qemu.o"
-    ],
     "BSTART.FP": [
       "99_spec_decode_qemu.o"
     ],
@@ -3701,9 +3777,7 @@
       "99_spec_decode_qemu.o"
     ],
     "BSTART.MPAR": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -3715,11 +3789,8 @@
     ],
     "BSTART.MSEQ": [
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -3734,16 +3805,20 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
+      "engram.o",
       "main.o",
-      "softfp.o"
+      "mhc.o",
+      "moe.o",
+      "quant.o",
+      "softfp.o",
+      "transpose.o"
     ],
     "BSTART.SYS": [
       "04_branch.o",
@@ -3751,11 +3826,8 @@
     ],
     "BSTART.TEPL": [
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -3778,17 +3850,19 @@
       "99_spec_decode_qemu.o"
     ],
     "BSTART.TLOAD": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
-      "99_spec_decode_qemu.o"
+      "99_spec_decode_qemu.o",
+      "engram.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
+      "transpose.o"
     ],
     "BSTART.TMATMUL": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
     "BSTART.TMATMUL.ACC": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -3805,7 +3879,6 @@
       "99_spec_decode_qemu.o"
     ],
     "BSTART.TMOV": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -3813,21 +3886,21 @@
       "99_spec_decode_qemu.o"
     ],
     "BSTART.TSTORE": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
-      "99_spec_decode_qemu.o"
+      "99_spec_decode_qemu.o",
+      "engram.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
+      "transpose.o"
     ],
     "BSTART.VPAR": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
     "BSTART.VSEQ": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -3840,13 +3913,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o",
       "main.o"
@@ -3870,12 +3941,11 @@
     ],
     "C.ADD": [
       "07_atomic.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
       "fa_performance.o",
@@ -3890,6 +3960,7 @@
       "gqa_fp16.o",
       "mem.o",
       "mla_attention_demo.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "softmax_fp32.o",
       "sparse_attention_local_fp16.o",
@@ -3897,6 +3968,7 @@
       "stdlib.o",
       "syscall.o",
       "tload_store.o",
+      "transpose.o",
       "where_fp32.o"
     ],
     "C.ADDI": [
@@ -3908,12 +3980,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "flash_attention_masked.o",
@@ -3934,9 +4005,7 @@
     ],
     "C.B.DIMI": [
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
@@ -3952,18 +4021,18 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
       "argmax_fp32.o",
       "concat_fp32.o",
+      "engram.o",
       "fa_performance.o",
       "flash_attention.o",
       "flash_attention_cube_fp16.o",
@@ -3980,11 +4049,13 @@
       "gemm_performance.o",
       "gqa_fp16.o",
       "main.o",
-      "mamulb.o",
       "math.o",
       "mem.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -4003,6 +4074,7 @@
       "tanh_fp32.o",
       "tload_store.o",
       "tmatmul_acc.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -4013,19 +4085,14 @@
       "99_spec_decode_qemu.o"
     ],
     "C.BSTART.MPAR": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
     "C.BSTART.MSEQ": [
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -4041,18 +4108,18 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
       "argmax_fp32.o",
       "concat_fp32.o",
+      "engram.o",
       "fa_performance.o",
       "flash_attention.o",
       "flash_attention_cube_fp16.o",
@@ -4069,11 +4136,13 @@
       "gemm_performance.o",
       "gqa_fp16.o",
       "main.o",
-      "mamulb.o",
       "math.o",
       "mem.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -4092,6 +4161,7 @@
       "tanh_fp32.o",
       "tload_store.o",
       "tmatmul_acc.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -4099,17 +4169,14 @@
       "where_fp32.o"
     ],
     "C.BSTART.SYS": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
     "C.BSTART.VPAR": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
     "C.BSTART.VSEQ": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -4123,18 +4190,17 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o",
       "main.o",
       "mem.o",
+      "moe.o",
       "stdlib.o",
       "syscall.o"
     ],
@@ -4165,6 +4231,7 @@
       "07_atomic.o",
       "09_varargs.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "fa_performance.o",
@@ -4177,10 +4244,13 @@
       "gqa_fp16.o",
       "math.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "softfp.o",
-      "sparse_attention_local_fp16.o"
+      "sparse_attention_local_fp16.o",
+      "transpose.o"
     ],
     "C.LWI": [
       "01_arithmetic.o",
@@ -4193,16 +4263,16 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "main.o",
       "mem.o",
+      "moe.o",
       "softfp.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o"
@@ -4218,16 +4288,16 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
       "concat_fp32.o",
+      "engram.o",
       "fa_performance.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_masked.o",
@@ -4240,8 +4310,11 @@
       "gqa_fp16.o",
       "math.o",
       "mem.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -4258,6 +4331,7 @@
       "stdlib.o",
       "syscall.o",
       "tanh_fp32.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -4275,13 +4349,12 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
@@ -4303,11 +4376,13 @@
       "gemm_performance.o",
       "gqa_fp16.o",
       "main.o",
-      "mamulb.o",
       "math.o",
       "mem.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -4326,6 +4401,7 @@
       "tanh_fp32.o",
       "tload_store.o",
       "tmatmul_acc.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -4350,6 +4426,7 @@
       "07_atomic.o",
       "09_varargs.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "fa_performance.o",
       "flash_attention_cube_fp16.o",
@@ -4361,11 +4438,14 @@
       "gqa_fp16.o",
       "math.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "softfp.o",
       "sparse_attention_local_fp16.o",
-      "syscall.o"
+      "syscall.o",
+      "transpose.o"
     ],
     "C.SETC.EQ": [
       "03_loadstore.o",
@@ -4376,12 +4456,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
@@ -4393,6 +4472,8 @@
       "main.o",
       "math.o",
       "mem.o",
+      "moe.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
@@ -4402,6 +4483,7 @@
       "stdlib.o",
       "syscall.o",
       "tanh_fp32.o",
+      "transpose.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o"
     ],
@@ -4416,12 +4498,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
@@ -4442,10 +4523,10 @@
       "gemm_performance.o",
       "gqa_fp16.o",
       "main.o",
-      "mamulb.o",
       "math.o",
       "mem.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
       "relu_fp32.o",
       "reshape_fp32.o",
@@ -4472,9 +4553,7 @@
     ],
     "C.SETC.TGT": [
       "07_atomic_lr_srczero.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
@@ -4503,12 +4582,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
@@ -4525,7 +4603,10 @@
       "main.o",
       "math.o",
       "mem.o",
+      "mhc.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -4542,6 +4623,7 @@
       "stdlib.o",
       "syscall.o",
       "tanh_fp32.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -4555,7 +4637,6 @@
       "99_spec_decode_qemu.o"
     ],
     "C.SSRGET": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -4577,12 +4658,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "concat_fp32.o",
@@ -4593,6 +4673,7 @@
       "gemm_performance.o",
       "main.o",
       "mem.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
       "relu_fp32.o",
       "reshape_fp32.o",
@@ -4620,11 +4701,10 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "math.o"
@@ -4705,11 +4785,16 @@
     ],
     "CMP.LT": [
       "99_spec_decode_qemu.o",
+      "moe.o",
       "softfp.o"
     ],
     "CMP.LTI": [
       "99_spec_decode_qemu.o",
-      "softmax_fp32.o"
+      "mhc.o",
+      "moe.o",
+      "quant.o",
+      "softmax_fp32.o",
+      "transpose.o"
     ],
     "CMP.LTU": [
       "14_callret.o",
@@ -4720,8 +4805,8 @@
       "syscall.o"
     ],
     "CMP.LTUI": [
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o"
     ],
     "CMP.NE": [
@@ -4741,6 +4826,7 @@
       "05_move.o",
       "06_floating_point.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
       "concat_fp32.o",
@@ -4756,7 +4842,10 @@
       "gemm_performance.o",
       "gqa_fp16.o",
       "math.o",
+      "mhc.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -4773,6 +4862,7 @@
       "stdlib.o",
       "syscall.o",
       "tanh_fp32.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -4827,12 +4917,10 @@
       "99_spec_decode_qemu.o"
     ],
     "ERCOV": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
     "ESAVE": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -4882,20 +4970,19 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
       "argmax_fp32.o",
       "concat_fp32.o",
+      "engram.o",
       "fa_performance.o",
       "flash_attention.o",
       "flash_attention_cube_fp16.o",
@@ -4912,11 +4999,13 @@
       "gemm_performance.o",
       "gqa_fp16.o",
       "main.o",
-      "mamulb.o",
       "math.o",
       "mem.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -4935,6 +5024,7 @@
       "tanh_fp32.o",
       "tload_store.o",
       "tmatmul_acc.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -4943,6 +5033,7 @@
     ],
     "FEQ": [
       "06_floating_point.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
@@ -4965,6 +5056,7 @@
     "FGE": [
       "06_floating_point.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "math.o",
       "rmsnorm_fp16.o"
@@ -4975,6 +5067,7 @@
     "FLT": [
       "06_floating_point.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
       "flash_attention_cube_fp16.o",
@@ -4983,6 +5076,7 @@
       "gelu_fp32.o",
       "gqa_fp16.o",
       "math.o",
+      "moe.o",
       "relu_fp32.o",
       "rmsnorm_fp16.o",
       "sigmoid_fp32.o",
@@ -5040,20 +5134,19 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
       "argmax_fp32.o",
       "concat_fp32.o",
+      "engram.o",
       "fa_performance.o",
       "flash_attention.o",
       "flash_attention_cube_fp16.o",
@@ -5070,11 +5163,13 @@
       "gemm_performance.o",
       "gqa_fp16.o",
       "main.o",
-      "mamulb.o",
       "math.o",
       "mem.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -5093,6 +5188,7 @@
       "tanh_fp32.o",
       "tload_store.o",
       "tmatmul_acc.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -5126,12 +5222,11 @@
     "HL.BSTART.CALL": [
       "06_floating_point.o",
       "07_atomic.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
@@ -5146,6 +5241,7 @@
       "main.o",
       "math.o",
       "mla_attention_demo.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
@@ -5162,12 +5258,11 @@
     "HL.BSTART.STD": [
       "06_floating_point.o",
       "07_atomic.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
@@ -5182,6 +5277,7 @@
       "main.o",
       "math.o",
       "mla_attention_demo.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
@@ -5199,7 +5295,6 @@
       "99_spec_decode_qemu.o"
     ],
     "HL.CASD": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -5207,7 +5302,6 @@
       "99_spec_decode_qemu.o"
     ],
     "HL.CASW": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -5255,6 +5349,7 @@
       "99_spec_decode_qemu.o"
     ],
     "HL.LB.PCR": [
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o"
     ],
     "HL.LB.PO": [
@@ -5280,6 +5375,7 @@
     ],
     "HL.LBU.PCR": [
       "07_atomic.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o"
     ],
     "HL.LBU.PO": [
@@ -5340,12 +5436,14 @@
     ],
     "HL.LDIP": [
       "03_loadstore.o",
-      "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "fa_performance.o",
       "flash_attention_demo.o",
       "flash_attention_masked.o",
-      "mla_attention_demo.o"
+      "mla_attention_demo.o",
+      "moe.o",
+      "transpose.o"
     ],
     "HL.LDIP.U": [
       "99_spec_decode_qemu.o"
@@ -5442,15 +5540,15 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
+      "engram.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gelu_fp32.o",
@@ -5458,6 +5556,8 @@
       "gqa_fp16.o",
       "main.o",
       "math.o",
+      "mhc.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "softfp.o",
       "sparse_attention_local_fp16.o",
@@ -5468,9 +5568,7 @@
     "HL.LW.PCR": [
       "03_loadstore.o",
       "07_atomic.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o",
       "stdlib.o"
@@ -5512,6 +5610,7 @@
     "HL.LWU.PCR": [
       "07_atomic.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "fa_performance.o",
       "flash_attention_cube_fp16.o",
@@ -5676,9 +5775,11 @@
       "99_spec_decode_qemu.o"
     ],
     "HL.SDI.PO": [
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o"
     ],
     "HL.SDI.PR": [
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o"
     ],
     "HL.SDI.U": [
@@ -5693,9 +5794,11 @@
     "HL.SDIP": [
       "03_loadstore.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_demo.o",
       "math.o",
+      "quant.o",
       "rmsnorm_fp16.o"
     ],
     "HL.SDIP.U": [
@@ -5791,7 +5894,6 @@
       "99_spec_decode_qemu.o"
     ],
     "HL.SUBIW": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "16_pto_kernel_parity.o",
       "99_spec_decode_qemu.o"
@@ -5799,9 +5901,7 @@
     "HL.SW.PCR": [
       "03_loadstore.o",
       "07_atomic.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
       "99_spec_decode_qemu.o",
@@ -5827,10 +5927,12 @@
       "03_loadstore.o",
       "11_system.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "slice_fp32.o",
       "softmax_fp32.o",
@@ -5880,7 +5982,6 @@
       "99_spec_decode_qemu.o"
     ],
     "J": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "14_callret_templates.o",
       "99_spec_decode_qemu.o"
@@ -5889,18 +5990,15 @@
       "99_spec_decode_qemu.o"
     ],
     "L.BSTART.FP": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
     "L.BSTART.STD": [
       "14_callret_templates.o",
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
     "L.BSTART.SYS": [
-      "41_v056_isa_forms.o",
       "41_v057_isa_forms.o",
       "99_spec_decode_qemu.o"
     ],
@@ -5915,12 +6013,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "mem.o",
@@ -5930,6 +6027,7 @@
       "99_spec_decode_qemu.o"
     ],
     "LBI": [
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "mem.o"
     ],
@@ -5949,12 +6047,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "main.o",
@@ -5999,10 +6096,11 @@
       "03_loadstore.o",
       "04_branch.o",
       "06_floating_point.o",
-      "12_v03_vector_tile.o",
+      "07_atomic.o",
       "12_v057_vector_tile.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "fa_performance.o",
@@ -6015,6 +6113,8 @@
       "gqa_fp16.o",
       "math.o",
       "mla_attention_demo.o",
+      "moe.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
@@ -6022,7 +6122,8 @@
       "softmax_fp32.o",
       "sparse_attention_local_fp16.o",
       "stdlib.o",
-      "tanh_fp32.o"
+      "tanh_fp32.o",
+      "transpose.o"
     ],
     "LDI.U": [
       "99_spec_decode_qemu.o"
@@ -6085,14 +6186,14 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
+      "engram.o",
       "fa_performance.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_demo.o",
@@ -6102,7 +6203,10 @@
       "gelu_fp32.o",
       "gqa_fp16.o",
       "main.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
@@ -6116,11 +6220,10 @@
     ],
     "LW": [
       "08_jumptable.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
       "fa_performance.o",
@@ -6132,8 +6235,8 @@
       "flash_attention_vec_fp32.o",
       "gemm.o",
       "gqa_fp16.o",
-      "mamulb.o",
       "mla_attention_demo.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "softmax_fp32.o",
       "sparse_attention_local_fp16.o",
@@ -6171,15 +6274,16 @@
     ],
     "LWI": [
       "01_arithmetic.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "flash_attention_vec_fp32.o",
       "gather_fp32.o",
       "gqa_fp16.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "scatter_fp32.o",
       "softfp.o",
@@ -6192,11 +6296,13 @@
     ],
     "LWU": [
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
       "flash_attention_vec_fp32.o",
       "gather_fp32.o",
       "gelu_fp32.o",
+      "moe.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
       "softmax_fp32.o",
@@ -6208,12 +6314,13 @@
       "99_spec_decode_qemu.o"
     ],
     "LWUI": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
       "concat_fp32.o",
+      "engram.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "flash_attention_vec_fp32.o",
@@ -6222,6 +6329,7 @@
       "gemm_demo.o",
       "gemm_performance.o",
       "gqa_fp16.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
       "relu_fp32.o",
       "reshape_fp32.o",
@@ -6246,7 +6354,6 @@
       "99_spec_decode_qemu.o",
       "flash_attention.o",
       "gemm.o",
-      "mamulb.o",
       "tmatmul_acc.o"
     ],
     "MAX": [
@@ -6270,6 +6377,7 @@
     "MUL": [
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
@@ -6285,14 +6393,16 @@
       "99_spec_decode_qemu.o"
     ],
     "MULW": [
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
-      "sparse_attention_local_fp16.o"
+      "moe.o",
+      "sparse_attention_local_fp16.o",
+      "transpose.o"
     ],
     "OR": [
       "03_loadstore.o",
@@ -6303,12 +6413,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "gemm_performance.o",
@@ -6329,9 +6438,9 @@
       "softfp.o"
     ],
     "ORW": [
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
@@ -6366,6 +6475,7 @@
       "99_spec_decode_qemu.o"
     ],
     "SB": [
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "mem.o"
     ],
@@ -6391,11 +6501,13 @@
     ],
     "SCVTF": [
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
       "math.o",
+      "mhc.o",
       "sparse_attention_local_fp16.o"
     ],
     "SD": [
@@ -6440,13 +6552,12 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "14_callret_templates.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "fa_performance.o",
@@ -6459,6 +6570,8 @@
       "gqa_fp16.o",
       "math.o",
       "mla_attention_demo.o",
+      "moe.o",
+      "quant.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
       "softfp.o",
@@ -6466,7 +6579,8 @@
       "sparse_attention_local_fp16.o",
       "stdlib.o",
       "syscall.o",
-      "tanh_fp32.o"
+      "tanh_fp32.o",
+      "transpose.o"
     ],
     "SDI.U": [
       "99_spec_decode_qemu.o"
@@ -6487,28 +6601,36 @@
       "14_callret.o",
       "99_spec_decode_qemu.o",
       "math.o",
+      "moe.o",
       "softfp.o",
       "syscall.o"
     ],
     "SETC.GE": [
       "11_system.o",
       "99_spec_decode_qemu.o",
-      "softfp.o"
+      "mhc.o",
+      "moe.o",
+      "quant.o",
+      "softfp.o",
+      "transpose.o"
     ],
     "SETC.GEI": [
       "11_system.o",
       "99_spec_decode_qemu.o",
-      "math.o"
+      "math.o",
+      "moe.o"
     ],
     "SETC.GEU": [
       "11_system.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
       "mem.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "sparse_attention_local_fp16.o",
       "stdlib.o",
@@ -6528,6 +6650,7 @@
       "stdlib.o"
     ],
     "SETC.LT": [
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
       "concat_fp32.o",
@@ -6535,10 +6658,14 @@
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
       "math.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
       "softfp.o",
       "sparse_attention_local_fp16.o",
       "split_fp32.o",
       "stdlib.o",
+      "transpose.o",
       "unique_i32.o"
     ],
     "SETC.LTI": [
@@ -6547,6 +6674,7 @@
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
       "math.o",
+      "moe.o",
       "softfp.o",
       "softmax_fp32.o",
       "sparse_attention_local_fp16.o",
@@ -6583,10 +6711,9 @@
       "04_branch.o",
       "07_atomic.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
@@ -6619,6 +6746,7 @@
     ],
     "SHI": [
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
@@ -6640,17 +6768,17 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
       "argmax_fp32.o",
       "concat_fp32.o",
+      "engram.o",
       "fa_performance.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_demo.o",
@@ -6664,8 +6792,11 @@
       "gqa_fp16.o",
       "main.o",
       "math.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -6682,6 +6813,7 @@
       "stdlib.o",
       "syscall.o",
       "tanh_fp32.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -6690,10 +6822,10 @@
     ],
     "SLLI": [
       "08_jumptable.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
       "concat_fp32.o",
@@ -6707,9 +6839,11 @@
       "gemm.o",
       "gemm_performance.o",
       "gqa_fp16.o",
-      "mamulb.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "slice_fp32.o",
       "softfp.o",
       "softmax_fp32.o",
@@ -6718,6 +6852,7 @@
       "stack_fp32.o",
       "stdlib.o",
       "tmatmul_acc.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "where_fp32.o"
     ],
@@ -6727,10 +6862,12 @@
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "softfp.o",
       "sparse_attention_local_fp16.o",
-      "syscall.o"
+      "syscall.o",
+      "transpose.o"
     ],
     "SLLW": [
       "99_spec_decode_qemu.o",
@@ -6752,21 +6889,22 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "main.o"
     ],
     "SRAI": [
-      "99_spec_decode_qemu.o"
+      "99_spec_decode_qemu.o",
+      "moe.o"
     ],
     "SRAIW": [
-      "99_spec_decode_qemu.o"
+      "99_spec_decode_qemu.o",
+      "moe.o"
     ],
     "SRAW": [
       "99_spec_decode_qemu.o"
@@ -6782,17 +6920,17 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
       "argmax_fp32.o",
       "concat_fp32.o",
+      "engram.o",
       "fa_performance.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_demo.o",
@@ -6805,8 +6943,11 @@
       "gemm_performance.o",
       "gqa_fp16.o",
       "math.o",
+      "mhc.o",
       "mla_attention_demo.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
+      "quant.o",
       "relu_fp32.o",
       "reshape_fp32.o",
       "rmsnorm_fp16.o",
@@ -6823,6 +6964,7 @@
       "stdlib.o",
       "syscall.o",
       "tanh_fp32.o",
+      "transpose.o",
       "transpose_large_fp32.o",
       "unique_i32.o",
       "unsorted_segment_sum_fp32.o",
@@ -6840,12 +6982,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "softfp.o",
@@ -6860,16 +7001,16 @@
       "06_floating_point.o",
       "07_atomic.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "softfp.o",
       "sparse_attention_local_fp16.o"
@@ -6899,6 +7040,7 @@
     ],
     "SUB": [
       "14_callret.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "stdlib.o"
     ],
@@ -6906,6 +7048,7 @@
       "09_varargs.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "argmax_fp32.o",
       "concat_fp32.o",
@@ -6915,6 +7058,7 @@
       "gather_fp32.o",
       "gqa_fp16.o",
       "mem.o",
+      "moe.o",
       "permute_nhwc_nchw_fp32.o",
       "relu_fp32.o",
       "reshape_fp32.o",
@@ -6933,33 +7077,42 @@
       "06_floating_point.o",
       "07_atomic.o",
       "09_varargs.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
+      "engram.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "flash_attention_vec_fp32.o",
       "gqa_fp16.o",
       "math.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "softfp.o",
       "sparse_attention_local_fp16.o",
       "stdlib.o",
-      "syscall.o"
+      "syscall.o",
+      "transpose.o"
     ],
     "SUBW": [
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
       "gqa_fp16.o",
       "mem.o",
+      "mhc.o",
+      "moe.o",
+      "quant.o",
       "rmsnorm_fp16.o",
       "softfp.o",
-      "sparse_attention_local_fp16.o"
+      "sparse_attention_local_fp16.o",
+      "transpose.o"
     ],
     "SW": [
       "99_spec_decode_qemu.o",
@@ -6973,8 +7126,8 @@
       "flash_attention_vec_fp32.o",
       "gelu_fp32.o",
       "gqa_fp16.o",
-      "mamulb.o",
       "mla_attention_demo.o",
+      "moe.o",
       "scatter_fp32.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
@@ -7037,12 +7190,11 @@
       "08_jumptable.o",
       "09_varargs.o",
       "11_system.o",
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "14_callret.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "21_freestanding_runtime.o",
       "99_spec_decode_qemu.o",
       "add_custom.o",
@@ -7053,6 +7205,7 @@
       "gqa_fp16.o",
       "main.o",
       "mla_attention_demo.o",
+      "moe.o",
       "rmsnorm_fp16.o",
       "softfp.o",
       "softmax_fp32.o",
@@ -7079,11 +7232,10 @@
       "99_spec_decode_qemu.o"
     ],
     "UCVTF": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "flash_attention_cube_fp16.o",
       "flash_attention_vec_fp16.o",
@@ -7091,6 +7243,7 @@
       "gelu_fp32.o",
       "gqa_fp16.o",
       "math.o",
+      "moe.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
       "softmax_fp32.o",
@@ -7098,9 +7251,7 @@
       "tanh_fp32.o"
     ],
     "V.ADD": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7138,7 +7289,6 @@
       "99_spec_decode_qemu.o"
     ],
     "V.CMP.EQ": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7158,7 +7308,6 @@
       "99_spec_decode_qemu.o"
     ],
     "V.CMP.LT": [
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7166,12 +7315,10 @@
       "99_spec_decode_qemu.o"
     ],
     "V.CMP.LTU": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "99_spec_decode_qemu.o"
     ],
     "V.CMP.LTUI": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7197,14 +7344,11 @@
       "99_spec_decode_qemu.o"
     ],
     "V.FABS": [
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
     "V.FADD": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7254,9 +7398,7 @@
       "99_spec_decode_qemu.o"
     ],
     "V.FMUL": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7393,9 +7535,7 @@
       "99_spec_decode_qemu.o"
     ],
     "V.LW.BRG": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7451,7 +7591,6 @@
       "99_spec_decode_qemu.o"
     ],
     "V.MUL": [
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7492,7 +7631,6 @@
       "99_spec_decode_qemu.o"
     ],
     "V.RDOR": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7626,7 +7764,6 @@
       "99_spec_decode_qemu.o"
     ],
     "V.SUB": [
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7634,7 +7771,6 @@
       "99_spec_decode_qemu.o"
     ],
     "V.SW": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7645,9 +7781,7 @@
       "99_spec_decode_qemu.o"
     ],
     "V.SW.BRG": [
-      "12_v03_vector_tile.o",
       "12_v057_vector_tile.o",
-      "13_v03_vector_ops_matrix.o",
       "13_v057_vector_ops_matrix.o",
       "99_spec_decode_qemu.o"
     ],
@@ -7692,6 +7826,7 @@
     ],
     "XOR": [
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "math.o",
       "softfp.o"
@@ -7699,8 +7834,10 @@
     "XORI": [
       "06_floating_point.o",
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
-      "math.o"
+      "math.o",
+      "moe.o"
     ],
     "XORIW": [
       "07_atomic.o",
@@ -7714,38 +7851,39 @@
     ],
     "XORW": [
       "16_pto_kernel_parity.o",
+      "17_deepseek_tilekernels.o",
       "99_spec_decode_qemu.o",
       "sigmoid_fp32.o",
       "silu_fp32.o",
       "softfp.o"
     ]
   },
-  "generated_at_utc": "2026-07-18 02:41:47Z",
-  "llvm_objdump": "/Users/zhoubot/linx-isa/compiler/llvm/build-linxisa-clang/bin/llvm-objdump",
+  "generated_at_utc": "2026-08-02 12:51:47Z",
+  "llvm_objdump": "/private/tmp/llvm-v0571-verify-build/bin/llvm-objdump",
   "missing_by_prefix": {},
   "missing_count": 0,
   "missing_spec_mnemonics": [],
-  "obj_dir": "/Users/zhoubot/linx-isa/avs/qemu/out/obj",
-  "object_files_scanned": 69,
+  "obj_dir": "/private/tmp/linx-isa-v0571/avs/qemu/out/obj",
+  "object_files_scanned": 71,
   "result": {
     "classification": "qemu_avs_translation_coverage_complete",
     "ok": true
   },
   "schema_version": "qemu-avs-translation-coverage-v1",
-  "spec_path": "/Users/zhoubot/linx-isa/isa/v0.57/linxisa-v0.57.json",
-  "spec_unique_mnemonics": 731,
+  "spec_path": "/private/tmp/linx-isa-v0571/isa/v0.57/linxisa-v0.57.json",
+  "spec_unique_mnemonics": 728,
   "top_covering_objects": [
     [
       "99_spec_decode_qemu.o",
-      731
+      728
     ],
     [
-      "16_pto_kernel_parity.o",
-      75
+      "17_deepseek_tilekernels.o",
+      80
     ],
     [
-      "12_v03_vector_tile.o",
-      73
+      "16_pto_kernel_parity.o",
+      74
     ],
     [
       "12_v057_vector_tile.o",
@@ -7755,10 +7893,6 @@
       "softfp.o",
       72
     ],
-    [
-      "13_v03_vector_ops_matrix.o",
-      69
-    ],
     [
       "13_v057_vector_ops_matrix.o",
       69
@@ -7767,6 +7901,10 @@
       "11_system.o",
       64
     ],
+    [
+      "moe.o",
+      62
+    ],
     [
       "sparse_attention_local_fp16.o",
       62
@@ -7789,7 +7927,7 @@
     ],
     [
       "07_atomic.o",
-      56
+      57
     ],
     [
       "14_callret.o",
@@ -7853,21 +7991,12 @@
       "U#4"
     ],
     "11_system.o": [],
-    "12_v03_vector_tile.o": [
-      "A0",
-      "A1",
-      "A5",
-      "S6"
-    ],
     "12_v057_vector_tile.o": [
       "A0",
       "A1",
       "A5",
       "S6"
     ],
-    "13_v03_vector_ops_matrix.o": [
-      "A7"
-    ],
     "13_v057_vector_ops_matrix.o": [
       "A7"
     ],
@@ -7884,13 +8013,18 @@
       "S2",
       "S7"
     ],
+    "17_deepseek_tilekernels.o": [
+      "A0",
+      "S0",
+      "T#1"
+    ],
     "21_freestanding_runtime.o": [
       "T#1",
       "U#1"
     ],
-    "41_v056_isa_forms.o": [],
     "41_v057_isa_forms.o": [],
     "99_spec_decode_qemu.o": [
+      "<UNKNOWN>",
       "A1"
     ],
     "add_custom.o": [],
@@ -7900,6 +8034,7 @@
     "concat_fp32.o": [
       "A0"
     ],
+    "engram.o": [],
     "fa_performance.o": [
       "T#1"
     ],
@@ -7947,14 +8082,26 @@
       "S7"
     ],
     "main.o": [],
-    "mamulb.o": [
-      "A2"
-    ],
     "math.o": [],
     "mem.o": [
       "A0"
     ],
+    "mhc.o": [
+      "A0",
+      "A1"
+    ],
     "mla_attention_demo.o": [],
+    "moe.o": [
+      "A0",
+      "A2",
+      "A3",
+      "A5",
+      "A6",
+      "A7",
+      "S0",
+      "S1",
+      "S3"
+    ],
     "permute_nhwc_nchw_fp32.o": [
       "A0",
       "A1",
@@ -7963,6 +8110,14 @@
       "S5",
       "X3"
     ],
+    "quant.o": [
+      "A0",
+      "A2",
+      "A4",
+      "S2",
+      "S4",
+      "T#1"
+    ],
     "relu_fp32.o": [],
     "reshape_fp32.o": [],
     "rmsnorm_fp16.o": [],
@@ -8001,6 +8156,11 @@
     "tmatmul_acc.o": [
       "A2"
     ],
+    "transpose.o": [
+      "A2",
+      "S8",
+      "T#1"
+    ],
     "transpose_large_fp32.o": [
       "A1",
       "X1"
diff --git a/docs/bringup/gates/qemu_translation_coverage_latest.md b/docs/bringup/gates/qemu_translation_coverage_latest.md
index 0b0ab7c2..dbc77c2b 100644
--- a/docs/bringup/gates/qemu_translation_coverage_latest.md
+++ b/docs/bringup/gates/qemu_translation_coverage_latest.md
@@ -1,9 +1,9 @@
 # AVS QEMU Translation Coverage
 
-- Generated (UTC): `2026-07-18 02:41:47Z`
-- Spec unique mnemonics: `731`
-- AVS object files scanned: `69`
-- Covered spec mnemonics: `731/731` (`100.0%`)
+- Generated (UTC): `2026-08-02 12:51:47Z`
+- Spec unique mnemonics: `728`
+- AVS object files scanned: `71`
+- Covered spec mnemonics: `728/728` (`100.0%`)
 - Missing spec mnemonics: `0`
 
 ## Coverage By Prefix
@@ -20,13 +20,13 @@
 - `ANDIW`: `1`
 - `ANDW`: `1`
 - `ASSERT`: `1`
-- `B`: `16`
+- `B`: `15`
 - `BC`: `2`
 - `BCNT`: `1`
 - `BIC`: `1`
 - `BIS`: `1`
 - `BSE`: `1`
-- `BSTART`: `34`
+- `BSTART`: `32`
 - `BSTOP`: `1`
 - `BWE`: `1`
 - `BWI`: `1`
@@ -179,20 +179,20 @@
 
 ## Top Covering Objects
 
-- `99_spec_decode_qemu.o`: `731`
-- `16_pto_kernel_parity.o`: `75`
-- `12_v03_vector_tile.o`: `73`
+- `99_spec_decode_qemu.o`: `728`
+- `17_deepseek_tilekernels.o`: `80`
+- `16_pto_kernel_parity.o`: `74`
 - `12_v057_vector_tile.o`: `73`
 - `softfp.o`: `72`
-- `13_v03_vector_ops_matrix.o`: `69`
 - `13_v057_vector_ops_matrix.o`: `69`
 - `11_system.o`: `64`
+- `moe.o`: `62`
 - `sparse_attention_local_fp16.o`: `62`
 - `flash_attention_cube_fp16.o`: `59`
 - `flash_attention_vec_fp16.o`: `59`
 - `gqa_fp16.o`: `59`
 - `03_loadstore.o`: `58`
-- `07_atomic.o`: `56`
+- `07_atomic.o`: `57`
 - `14_callret.o`: `54`
 - `math.o`: `51`
 - `06_floating_point.o`: `49`
diff --git a/docs/isa/arch/prgorder.md b/docs/isa/arch/prgorder.md
index d7e5dbbe..cbe51dd4 100644
--- a/docs/isa/arch/prgorder.md
+++ b/docs/isa/arch/prgorder.md
@@ -40,12 +40,16 @@ The following is a "header → Expand → PO" comparison of three common blocks,
 **header (the order of appearance is L1-IPO):**
 
 ```asm
-BSTART.TEPL TMATMUL, FP16      ; 配置：做 FP16 的 A×B
+BSTART.TMATMUL FP16           ; 配置：做 FP16 的 A×B
 B.DIM     rM, 128, ->M        ; M=128
 B.DIM     rN, 128, ->N        ; N=128
 B.DIM     rK, 256, ->K        ; K=256
-B.IOT     [TA, TB], group=0, ->ACC<64KB>   ; 绑定 A/B 到 ACC
-B.ARG     CD2RD                ; 结果默认行主序，无额外变换
+B.DATR    normal, FP16, ZERO, cmode0, rmode0
+B.IOT     TA, TB, last        ; ACC 由 CUBE opcode 隐式选择
+
+BSTART.ACCCVT FP16            ; 将隐式 ACC 发布到普通 Tile
+B.DATR    normal, FP16, ZERO, cmode0, rmode0
+B.IOT     last, ->t<32KB>
 ```
 
 **Expanded block body steps (sequential replacement):**
@@ -57,7 +61,7 @@ B.ARG     CD2RD                ; 结果默认行主序，无额外变换
 **Final PO (Semantic Order):**
 
 ```
-BSTART.TEPL → B.DIM → B.DIM → B.DIM → B.IOT → B.ARG →
+BSTART.TMATMUL → B.DIM → B.DIM → B.DIM → B.DATR → B.IOT →
 加载分片 → 乘累加到 ACC → ACC 写回 Tile
 ```
 
@@ -68,12 +72,16 @@ BSTART.TEPL → B.DIM → B.DIM → B.DIM → B.IOT → B.ARG →
 **header：**
 
 ```asm
-BSTART.TEPL TMATMUL, FP16
+BSTART.TMATMUL FP16
 B.DIM     zero, 64,  ->M
 B.DIM     zero, 64,  ->N
 B.DIM     zero, 256, ->K
-B.IOT     [TA, TB], group=0, ->ACC<64KB>
-B.ARG     ZZ2RD                  ; 指定 TCVT 的布局变换（例）
+B.DATR    normal, FP16, ZERO, cmode0, rmode0
+B.IOT     TA, TB, last
+
+BSTART.ACCCVT FP16
+B.DATR    zn, FP16, ZERO, cmode0, rmode0  ; 指定转换布局（例）
+B.IOT     last, ->t<16KB>
 ```
 
 **Expanded block body (sequential replacement):**
@@ -98,14 +106,17 @@ ZXTERMZH39QXZ顺序 → 读取/预取 → 乘累加到 ACC → TCVT 边搬边转
 **header：**
 
 ```asm
-BSTART.TEPL TMATMULMX, INT8
+BSTART.TMATMULMX INT8
 B.DIM     zero, 128, ->M
 B.DIM     zero, 128, ->N
 B.DIM     zero, 256, ->K
-B.IOT     [TA, TSA], group=0, ->ACC<64KB>  ; A 与 ScaleA
-B.IOT     [TB, TSB], group=1               ; B 与 ScaleB
-; 可选：B.IOT [TC], group=2               ; 若做 +C
-B.ARG     CD2RD
+B.DATR    normal, INT8, ZERO, cmode0, rmode0
+B.IOT     TA, TSA                           ; A 与 ScaleA
+B.IOT     TB, TSB, last                     ; B 与 ScaleB；ACC 隐式选择
+
+BSTART.ACCCVT INT8
+B.DATR    normal, INT8, ZERO, cmode0, rmode0
+B.IOT     last, ->t<32KB>
 ```
 
 **Block body (sequential replacement):**1. Load A, ScaleA and B, ScaleB;
diff --git a/docs/isa/blockIntro/cube_block/header.md b/docs/isa/blockIntro/cube_block/header.md
index 2fc18b88..a08d20f0 100644
--- a/docs/isa/blockIntro/cube_block/header.md
+++ b/docs/isa/blockIntro/cube_block/header.md
@@ -51,9 +51,9 @@ by its descriptor records. For example:
 -...
 - [B.IOT](../../header/B.IOT.md) SrcTile6<.reuse>, SrcTile7<.reuse>, last, ->DstTile3<TileSize3>
 
-All named CUBE headers share the CUBE encoding family shown below. The generic
-`BSTART.CUBE Function, DataType` syntax is reserved for unnamed function
-values; named function values must use their canonical mnemonics.
+All named CUBE headers share the CUBE encoding family shown below. Only the 13
+assigned named functions are legal; unassigned function values are illegal and
+there is no generic executable `BSTART.CUBE Function, DataType` spelling.
 
 ![CUBE encoding family](../../../figs/bitfield/svg/BlockHeader_32bit/BSTART.CUBE.svg)
 
diff --git a/docs/isa/blockIntro/cube_block/intro.md b/docs/isa/blockIntro/cube_block/intro.md
index cea609d6..05605a7d 100644
--- a/docs/isa/blockIntro/cube_block/intro.md
+++ b/docs/isa/blockIntro/cube_block/intro.md
@@ -34,12 +34,25 @@ The matrix data block belongs to the instruction type that only has header but n
 
 Example:
 ```asm
-    TMATMUL <M:64, N:32, K:64, FP32> T#4, T#3, ->ACC<16KB>
-    TMATMUL.ACC <M:64, N:32, K:64, FP32> T#1, T#2, ACC, ->ACC<8KB>
-    ACCCVT NORM <Row:64, Col:64, FP32> ACC, ->T<16KB>
+    BSTART.TMATMUL FP32
+    C.B.DIMI 64, ->lb0
+    C.B.DIMI 32, ->lb1
+    C.B.DIMI 64, ->lb2
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
+    B.IOT t#4, t#3, last
+
+    BSTART.TMATMUL.ACC FP32
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
+    B.IOT t#1, t#2, last
+
+    BSTART.ACCCVT FP32
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
+    B.IOT last, ->t<16KB>
 ```
 
-In the above example, the `TMATMUL` instruction is written to the ACC register, which is then read by the subsequent `TMATMUL.ACC` instruction and used for the multiply-accumulate operation. Finally, the result is moved to the T-type Tile register through the `ACCCVT` instruction.
+In the above example, the CUBE opcode selects implicit ACC state; ACC is never
+encoded in `B.IOT`. `TMATMUL` initializes ACC, `TMATMUL.ACC` reads and updates
+it, and `ACCCVT` publishes the result to an ordinary T-type Tile.
 
 ## Input requirements
 
@@ -87,4 +100,4 @@ The output requirements for matrix operations are summarized as follows:
 |------|-----------|
 | Destination register | Only output to ACC register allowed |
 | Output layout | Big N small z format |
-| Fractal size | 1024Byte |
\ No newline at end of file
+| Fractal size | 1024Byte |
diff --git a/docs/isa/blockIntro/tepl_block/header.md b/docs/isa/blockIntro/tepl_block/header.md
index eb3889b9..0a3e19d6 100644
--- a/docs/isa/blockIntro/tepl_block/header.md
+++ b/docs/isa/blockIntro/tepl_block/header.md
@@ -54,7 +54,7 @@ Among them, the mode and function fields are used to encode specific TileOp info
 | 0 | 2 | [TMUL](../../header/tileblock/TMUL.md) | Element-wise multiplication of two Tiles |
 | 0 | 3 | [TDIV](../../header/tileblock/TDIV.md) | Element-wise division of two Tiles |
 | 0 | 4 | [TREM](../../header/tileblock/TREM.md) | Element-wise remainder of two Tiles, the remainder sign is the same as the divisor |
-| 0 | 5 | [TFMOD](../../header/tileblock/TFMOD.md) | Element-wise remainder of two Tiles, the remainder sign is the same as the dividend |
+| 0 | 5 | - | Reserved/illegal |
 | 0 | 6 | [TAND](../../header/tileblock/TAND.md) | Element-wise bitwise AND of two Tiles |
 | 0 | 7 | [TOR](../../header/tileblock/TOR.md) | Element-wise bitwise OR of two Tiles |
 | 0 | 8 | [TXOR](../../header/tileblock/TXOR.md) | Element-wise bitwise XOR of two Tiles |
@@ -72,8 +72,8 @@ Among them, the mode and function fields are used to encode specific TileOp info
 | 0 | 20 | [TRECIP](../../header/tileblock/TRECIP.md) | Element-wise reciprocal of Tile |
 | 0 | 21 | [TSQRT](../../header/tileblock/TSQRT.md) | Element-wise square root |
 | 0 | 22 | [TRSQRT](../../header/tileblock/TRSQRT.md) | Element-wise reciprocal square root |
-| 0 | 23 | [TRELU](../../header/tileblock/TRELU.md) | Element-wise ReLU of Tile || 0 | 24 | [TADDC](../../header/tileblock/TADDC.md) | Ternary element-wise addition: dst = src0 + src1 + src2 |
-| 0 | 25 | [TSUBC](../../header/tileblock/TSUBC.md) | Ternary element-wise subtraction: dst = src0 - src1 + src2 |
+| 0 | 23 | [TRELU](../../header/tileblock/TRELU.md) | Element-wise ReLU of Tile |
+| 0 | 24-25 | - | Reserved/illegal |
 | 0 | 26 | [TSEL](../../header/tileblock/TSEL.md) | Select between two Tiles using a masked Tile (element-wise selection) |
 | 0 | 27 | [TCVT](../../header/tileblock/TCVT.md) | Element-by-element data format conversion of Tile. |
 | 0 | 28-31 | - | Reserved |
@@ -85,7 +85,7 @@ Among them, the mode and function fields are used to encode specific TileOp info
 | 1 | 2 | [TMULS](../../header/tileblock/TMULS.md) | Element-wise multiplication of Tile and scalar |
 | 1 | 3 | [TDIVS](../../header/tileblock/TDIVS.md) | Element-wise division with scalar (Tile/scalar or scalar/Tile) |
 | 1 | 4 | [TREMS](../../header/tileblock/TREMS.md) | Element-wise remainder with scalar: remainder(src, scalar) |
-| 1 | 5 | [TFMODS](../../header/tileblock/TFMODS.md) | Element-wise remainder with scalar: fmod(src, scalar) |
+| 1 | 5 | - | Reserved/illegal |
 | 1 | 6 | [TANDS](../../header/tileblock/TANDS.md) | Element-wise bitwise AND of Tile and scalar |
 | 1 | 7 | [TORS](../../header/tileblock/TORS.md) | Element-wise bitwise OR of Tile and scalar |
 | 1 | 8 | [TXORS](../../header/tileblock/TXORS.md) | Element-wise bitwise XOR of Tile and scalar |
@@ -94,10 +94,9 @@ Among them, the mode and function fields are used to encode specific TileOp info
 | 1 | 11 | [TMAXS](../../header/tileblock/TMAXS.md) | Element-wise maximum value of Tile and scalar: max(src, scalar) |
 | 1 | 12 | [TMINS](../../header/tileblock/TMINS.md) | Element-wise minimum value of Tile and scalar |
 | 1 | 13 | [TCMPS](../../header/tileblock/TCMPS.md) | Compare Tile with scalar element by element |
-| 1 | 14 | [TLRELU](../../header/tileblock/TLRELU.md) | LeakyReLU with scalar slope |
+| 1 | 14 | - | Reserved/illegal |
 | 1 | 15-23 | - | Reserved code |
-| 1 | 24 | [TADDSC](../../header/tileblock/TADDSC.md) | With scalar fusion element-wise addition operation: dst = src0 + scalar + src1 |
-| 1 | 25 | [TSUBSC](../../header/tileblock/TSUBSC.md) | With scalar fused element-wise subtraction operation: dst = src0 - scalar + src1 |
+| 1 | 24-25 | - | Reserved/illegal |
 | 1 | 26 | [SELS](../../header/tileblock/TSELS.md) | Use mask Tile to select between source Tile and scalar (source Tile element-wise selection) || 1 | 27 | [TEXPANDS](../../header/tileblock/TEXPANDS.md) | Broadcast scalar to the target Tile |
 | 1 | 28-31 | - | Reserved code |
 
diff --git a/docs/isa/encoding.md b/docs/isa/encoding.md
index ee0d5f18..fd82f186 100644
--- a/docs/isa/encoding.md
+++ b/docs/isa/encoding.md
@@ -1,8 +1,8 @@
 # Instruction Encoding Formats
 
-> **ISA Version:** v0.57.0 &nbsp;|&nbsp; **Chapter 03** of the ISA Manual
+> **ISA Version:** v0.57.1 &nbsp;|&nbsp; **Chapter 03** of the ISA Manual
 
-LinxISA v0.57.0 supports four instruction lengths in a little-endian
+LinxISA v0.57.1 supports four instruction lengths in a little-endian
 halfword-oriented model. Bit positions are shown as `[msb:0]`
 (MSB leftmost, LSB rightmost), matching ARM and RISC-V conventions.
 
diff --git a/docs/isa/gen_isa_pages.py b/docs/isa/gen_isa_pages.py
index 90327167..742312a6 100644
--- a/docs/isa/gen_isa_pages.py
+++ b/docs/isa/gen_isa_pages.py
@@ -470,7 +470,7 @@ def _build_index_page(
 : Bit numbering, instruction lengths, decode tags, field colour key
 
 [![](assets/ch04.svg){: style="width:120px;height:80px"} **Ch 04 — Block ISA**{.chapter-card style="--ch04-color:#8b5cf6"}
-: BSTART, BSTOP, B.ARG, B.DIM, tile/SIMT control flow
+: BSTART, BSTOP, B.DATR, B.DIM, B.IOT, tile/SIMT control flow
 
 [![](assets/ch11.svg){: style="width:120px;height:80px"} **Ch 11 — AGU**{.chapter-card style="--ch11-color:#059669"}
 : Loads, stores, prefetch, all addressing modes
@@ -1346,6 +1346,21 @@ def main() -> int:
         )
         return 0
 
+    expected_managed = {
+        "index.md",
+        "encoding.md",
+        "groups/index.md",
+        "instructions/index.md",
+        *(f"groups/{_slug(group)}.md" for group in groups),
+        *(f"instructions/{_slug(mnemonic)}.md" for mnemonic in mnem_map),
+    }
+    for sub in ("groups", "instructions"):
+        managed_dir = os.path.join(out_dir, sub)
+        for name in os.listdir(managed_dir):
+            rel = os.path.join(sub, name)
+            if name.endswith(".md") and rel not in expected_managed:
+                os.unlink(os.path.join(out_dir, rel))
+
     print(f"\n[gen_isa_pages] Done — {len(mnem_map)} instruction pages, {len(groups)} group pages.")
     return 0
 
diff --git a/docs/isa/groups/block_argument.md b/docs/isa/groups/block_argument.md
index f74876ff..234b35e7 100644
--- a/docs/isa/groups/block_argument.md
+++ b/docs/isa/groups/block_argument.md
@@ -5,8 +5,8 @@
 <span class="ch-tag ch-tag-04">Ch 04</span>
 &nbsp; <strong>Block ISA — Block-structured Control Flow</strong> &nbsp;|&nbsp;
 **Group:** Block Argument &nbsp;|&nbsp;
-**Forms:** 9 &nbsp;|&nbsp;
-**Unique mnemonics:** 2
+**Forms:** 3 &nbsp;|&nbsp;
+**Unique mnemonics:** 1
 
 </div>
 
@@ -16,7 +16,6 @@ Instructions that declare block argument bindings (input registers).
 
 | Mnemonic | Assembly | Length | Decode | Description |
 |----------|----------|--------|--------|-------------|
-| [B.ARG](../instructions/b_arg.md) | `B.ARG NORM.normal` | 32 | — | Instruction from the Block Argument group. |
 | [B.DIM](../instructions/b_dim.md) | `B.DIM RegSrc, uimm, ->LB2` | 32 | — | Instruction from the Block Argument group. |
 
 ## See Also
diff --git a/docs/isa/groups/block_data_attribute.md b/docs/isa/groups/block_data_attribute.md
index f3d2feba..bea5a9d3 100644
--- a/docs/isa/groups/block_data_attribute.md
+++ b/docs/isa/groups/block_data_attribute.md
@@ -16,7 +16,7 @@ Block data annotation instructions.
 
 | Mnemonic | Assembly | Length | Decode | Description |
 |----------|----------|--------|--------|-------------|
-| [B.DATR](../instructions/b_datr.md) | `B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat}` | 32 | — | Instruction from the Block Data Attribute group. |
+| [B.DATR](../instructions/b_datr.md) | `B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}` | 32 | — | Instruction from the Block Data Attribute group. |
 
 ## See Also
 
diff --git a/docs/isa/groups/block_split.md b/docs/isa/groups/block_split.md
index 18d0d151..47c32679 100644
--- a/docs/isa/groups/block_split.md
+++ b/docs/isa/groups/block_split.md
@@ -5,8 +5,8 @@
 <span class="ch-tag ch-tag-04">Ch 04</span>
 &nbsp; <strong>Block ISA — Block-structured Control Flow</strong> &nbsp;|&nbsp;
 **Group:** Block Split &nbsp;|&nbsp;
-**Forms:** 59 &nbsp;|&nbsp;
-**Unique mnemonics:** 45
+**Forms:** 57 &nbsp;|&nbsp;
+**Unique mnemonics:** 43
 
 </div>
 
@@ -18,8 +18,6 @@ Block structural instructions (BSTART, BSTOP, FENTRY, etc.).
 |----------|----------|--------|--------|-------------|
 | [BSTART](../instructions/bstart.md) | `BSTART {DIRECT, CALL}, <label>` | 32 | — | Block split marker. Terminates the current basic block and begins the next. Encodes block type and transition kind. |
 | [BSTART.ACCCVT](../instructions/bstart_acccvt.md) | `BSTART.ACCCVT DataType` | 32 | — | Terminates the current block and begins the next. |
-| [BSTART.CUBE](../instructions/bstart_cube.md) | `BSTART.CUBE Function, DataType` | 32 | — | Terminates the current block and begins the next. |
-| [BSTART.FIXP](../instructions/bstart_fixp.md) | `BSTART.FIXP TileOp, DataType` | 32 | — | Terminates the current block and begins the next. |
 | [BSTART.FP](../instructions/bstart_fp.md) | `BSTART.FP RET` | 32 | — | Terminates the current block and begins the next. |
 | [BSTART.MGATHER](../instructions/bstart_mgather.md) | `BSTART.MGATHER DataType` | 32 | — | Terminates the current block and begins the next. |
 | [BSTART.MGATHER.CAS](../instructions/bstart_mgather_cas.md) | `BSTART.MGATHER.CAS DataType` | 32 | — | Terminates the current block and begins the next. |
@@ -30,7 +28,7 @@ Block structural instructions (BSTART, BSTOP, FENTRY, etc.).
 | [BSTART.MSEQ](../instructions/bstart_mseq.md) | `BSTART.MSEQ <VS8, VS16>` | 32 | — | Terminates the current block and begins the next. |
 | [BSTART.STD](../instructions/bstart_std.md) | `BSTART.STD COND, <label>` | 32 | — | Terminates the current block and begins the next. |
 | [BSTART.SYS](../instructions/bstart_sys.md) | `BSTART.SYS FALL<, fixup_label>` | 32 | — | Terminates the current block and begins the next. |
-| [BSTART.TEPL](../instructions/bstart_tepl.md) | `BSTART.TEPL TileOpcode, DataType` | 32 | — | Terminates the current block and begins the next. |
+| [BSTART.TEPL](../instructions/bstart_tepl.md) | `BSTART.TEPL Mode, Function, DataType` | 32 | — | Terminates the current block and begins the next. |
 | [BSTART.TGEMV](../instructions/bstart_tgemv.md) | `BSTART.TGEMV DataType` | 32 | — | Terminates the current block and begins the next. |
 | [BSTART.TGEMV.ACC](../instructions/bstart_tgemv_acc.md) | `BSTART.TGEMV.ACC DataType` | 32 | — | Terminates the current block and begins the next. |
 | [BSTART.TGEMV.BIAS](../instructions/bstart_tgemv_bias.md) | `BSTART.TGEMV.BIAS DataType` | 32 | — | Terminates the current block and begins the next. |
diff --git a/docs/isa/groups/dma_operation.md b/docs/isa/groups/dma_operation.md
index c4308641..2a903c8b 100644
--- a/docs/isa/groups/dma_operation.md
+++ b/docs/isa/groups/dma_operation.md
@@ -10,7 +10,7 @@
 
 </div>
 
-Instructions in the **DMA Operation** group of the LinxISA v0.57.0 catalog.
+Instructions in the **DMA Operation** group of the LinxISA v0.57.1 catalog.
 
 ## Instructions
 
diff --git a/docs/isa/groups/floating_point_arithmetic.md b/docs/isa/groups/floating_point_arithmetic.md
index f3fae43c..5c8582d8 100644
--- a/docs/isa/groups/floating_point_arithmetic.md
+++ b/docs/isa/groups/floating_point_arithmetic.md
@@ -10,7 +10,7 @@
 
 </div>
 
-Instructions in the **Floating Point Arithmetic** group of the LinxISA v0.57.0 catalog.
+Instructions in the **Floating Point Arithmetic** group of the LinxISA v0.57.1 catalog.
 
 ## Instructions
 
diff --git a/docs/isa/groups/index.md b/docs/isa/groups/index.md
index beaeb0ef..e342015c 100644
--- a/docs/isa/groups/index.md
+++ b/docs/isa/groups/index.md
@@ -1,6 +1,6 @@
 # Instruction Groups
 
-Alphabetical list of all 67 instruction groups in the LinxISA v0.57.0 catalog.
+Alphabetical list of all 67 instruction groups in the LinxISA v0.57.1 catalog.
 See the [chapter index](index.md) for the manual organization.
 
 | Group | Forms | Chapter | Sample mnemonics |
@@ -9,16 +9,16 @@ See the [chapter index](index.md) for the manual organization.
 | [Arithmetic Operation 64bit](arithmetic_operation_64bit.md) | 21 | **Ch 12** — [source](index.md) | `ADD`, `ADDI`, `AND`, `ANDI`, `HL.ADDI`, `HL.ANDI`, `HL.ORI`, `HL.SUBI` +13 |
 | [Arithmetic Operation 32bit](arithmetic_operation_32bit.md) | 21 | **Ch 12** — [source](index.md) | `ADDIW`, `ADDW`, `ANDIW`, `ANDW`, `HL.ADDIW`, `HL.ANDIW`, `HL.ORIW`, `HL.SUBIW` +13 |
 | [PC-Relative](pc_relative.md) | 4 | **Ch 16** — [source](index.md) | `ADDTPC`, `HL.ADDTPC`, `HL.SETRET`, `SETRET` |
-| [Block Argument](block_argument.md) | 9 | **Ch 4** — [source](index.md) | `B.ARG`, `B.DIM` |
 | [Block Control Attribute](block_control_attribute.md) | 1 | **Ch 17** — [source](index.md) | `B.CATR` |
 | [Block Data Attribute](block_data_attribute.md) | 1 | **Ch 17** — [source](index.md) | `B.DATR` |
+| [Block Argument](block_argument.md) | 3 | **Ch 4** — [source](index.md) | `B.DIM` |
 | [Branch](branch.md) | 10 | **Ch 16** — [source](index.md) | `B.EQ`, `B.GE`, `B.GEU`, `B.LT`, `B.LTU`, `B.NE`, `B.NZ`, `B.Z` +2 |
 | [Block Hint](block_hint.md) | 2 | **Ch 17** — [source](index.md) | `B.HINT` |
 | [Block Input & Output](block_input_output.md) | 6 | **Ch 4** — [source](index.md) | `B.IOR`, `B.IOT` |
 | [Block Offset](block_offset.md) | 1 | **Ch 4** — [source](index.md) | `B.TEXT` |
 | [Cache Maintain](cache_maintain.md) | 16 | **Ch 19** — [source](index.md) | `BC.IALL`, `BC.IVA`, `DC.CISW`, `DC.CIVA`, `DC.CSW`, `DC.CVA`, `DC.IALL`, `DC.ISW` +8 |
 | [Bit Operation](bit_operation.md) | 8 | **Ch 12** — [source](index.md) | `BCNT`, `BIC`, `BIS`, `BXS`, `BXU`, `CLZ`, `CTZ`, `REV` |
-| [Block Split](block_split.md) | 59 | **Ch 4** — [source](index.md) | `BSTART`, `BSTART.ACCCVT`, `BSTART.CUBE`, `BSTART.FIXP`, `BSTART.FP`, `BSTART.MGATHER`, `BSTART.MGATHER.CAS`, `BSTART.MGATHER.MASK` +37 |
+| [Block Split](block_split.md) | 57 | **Ch 4** — [source](index.md) | `BSTART`, `BSTART.ACCCVT`, `BSTART.FP`, `BSTART.MGATHER`, `BSTART.MGATHER.CAS`, `BSTART.MGATHER.MASK`, `BSTART.MPAR`, `BSTART.MSCATTER` +35 |
 | [BSTART](bstart.md) | 20 | **Ch 4** — [source](index.md) | `BSTART CALL`, `HL.BSTART CALL`, `HL.BSTART.FP`, `HL.BSTART.STD`, `HL.BSTART.SYS`, `L.BSTART.FP`, `L.BSTART.STD`, `L.BSTART.SYS` |
 | [Arithmetic Operation](arithmetic_operation.md) | 20 | **Ch 12** — [source](index.md) | `C.ADD`, `C.AND`, `C.OR`, `C.SUB`, `V.ADD`, `V.ADDI`, `V.AND`, `V.ANDI` +12 |
 | [Arithmetic](arithmetic.md) | 1 | **Ch 12** — [source](index.md) | `C.ADDI` |
diff --git a/docs/isa/header/tileblock/TADDC.md b/docs/isa/header/tileblock/TADDC.md
deleted file mode 100644
index 8cc6fe65..00000000
--- a/docs/isa/header/tileblock/TADDC.md
+++ /dev/null
@@ -1,3 +0,0 @@
-# TADDC
-
-This page is part of the standalone LinxISA reference hierarchy. Use the appendix reference pages when you need exact mnemonic-by-mnemonic detail.
diff --git a/docs/isa/header/tileblock/TADDSC.md b/docs/isa/header/tileblock/TADDSC.md
deleted file mode 100644
index 8c3b8432..00000000
--- a/docs/isa/header/tileblock/TADDSC.md
+++ /dev/null
@@ -1,3 +0,0 @@
-# TADDSC
-
-This page is part of the standalone LinxISA reference hierarchy. Use the appendix reference pages when you need exact mnemonic-by-mnemonic detail.
diff --git a/docs/isa/header/tileblock/TFMOD.md b/docs/isa/header/tileblock/TFMOD.md
deleted file mode 100644
index ed3be319..00000000
--- a/docs/isa/header/tileblock/TFMOD.md
+++ /dev/null
@@ -1,3 +0,0 @@
-# TFMOD
-
-This page is part of the standalone LinxISA reference hierarchy. Use the appendix reference pages when you need exact mnemonic-by-mnemonic detail.
diff --git a/docs/isa/header/tileblock/TFMODS.md b/docs/isa/header/tileblock/TFMODS.md
deleted file mode 100644
index 15655e49..00000000
--- a/docs/isa/header/tileblock/TFMODS.md
+++ /dev/null
@@ -1,3 +0,0 @@
-# TFMODS
-
-This page is part of the standalone LinxISA reference hierarchy. Use the appendix reference pages when you need exact mnemonic-by-mnemonic detail.
diff --git a/docs/isa/header/tileblock/TLRELU.md b/docs/isa/header/tileblock/TLRELU.md
deleted file mode 100644
index e4cbb45c..00000000
--- a/docs/isa/header/tileblock/TLRELU.md
+++ /dev/null
@@ -1,3 +0,0 @@
-# TLRELU
-
-This page is part of the standalone LinxISA reference hierarchy. Use the appendix reference pages when you need exact mnemonic-by-mnemonic detail.
diff --git a/docs/isa/header/tileblock/TSUBC.md b/docs/isa/header/tileblock/TSUBC.md
deleted file mode 100644
index 14e7ce6e..00000000
--- a/docs/isa/header/tileblock/TSUBC.md
+++ /dev/null
@@ -1,3 +0,0 @@
-# TSUBC
-
-This page is part of the standalone LinxISA reference hierarchy. Use the appendix reference pages when you need exact mnemonic-by-mnemonic detail.
diff --git a/docs/isa/header/tileblock/TSUBSC.md b/docs/isa/header/tileblock/TSUBSC.md
deleted file mode 100644
index bcfc68b1..00000000
--- a/docs/isa/header/tileblock/TSUBSC.md
+++ /dev/null
@@ -1,3 +0,0 @@
-# TSUBSC
-
-This page is part of the standalone LinxISA reference hierarchy. Use the appendix reference pages when you need exact mnemonic-by-mnemonic detail.
diff --git a/docs/isa/index.md b/docs/isa/index.md
index cc036598..52b4a966 100644
--- a/docs/isa/index.md
+++ b/docs/isa/index.md
@@ -3,7 +3,7 @@
 <!-- Hero Banner -->
 <div class="isa-hero">
 
-**ISA Version:** v0.57.0 &nbsp;·&nbsp; **769 instruction forms** &nbsp;·&nbsp; **67 groups** &nbsp;·&nbsp; **4 encoding formats**
+**ISA Version:** v0.57.1 &nbsp;·&nbsp; **761 instruction forms** &nbsp;·&nbsp; **67 groups** &nbsp;·&nbsp; **4 encoding formats**
 
 ---
 
@@ -25,7 +25,7 @@ The LinxISA manual is organized into 12 chapters covering distinct functional un
 : Bit numbering, instruction lengths, decode tags, field colour key
 
 [![](assets/ch04.svg){: style="width:120px;height:80px"} **Ch 04 — Block ISA**{.chapter-card style="--ch04-color:#8b5cf6"}
-: BSTART, BSTOP, B.ARG, B.DIM, tile/SIMT control flow
+: BSTART, BSTOP, B.DATR, B.DIM, B.IOT, tile/SIMT control flow
 
 [![](assets/ch11.svg){: style="width:120px;height:80px"} **Ch 11 — AGU**{.chapter-card style="--ch11-color:#059669"}
 : Loads, stores, prefetch, all addressing modes
@@ -66,9 +66,9 @@ The LinxISA manual is organized into 12 chapters covering distinct functional un
 <div class="group-card-grid">
 [Arithmetic (1)](groups/arithmetic.md){.group-card} [Arithmetic Operation (20)](groups/arithmetic_operation.md){.group-card} [Arithmetic Operation 32bit (21)](groups/arithmetic_operation_32bit.md){.group-card} [Arithmetic Operation 64bit (21)](groups/arithmetic_operation_64bit.md){.group-card}
 [Atomic (4)](groups/atomic.md){.group-card} [Atomic Operation (72)](groups/atomic_operation.md){.group-card} [BSTART (20)](groups/bstart.md){.group-card} [Bit Manipulation (8)](groups/bit_manipulation.md){.group-card}
-[Bit Operation (8)](groups/bit_operation.md){.group-card} [Block Argument (9)](groups/block_argument.md){.group-card} [Block Control Attribute (1)](groups/block_control_attribute.md){.group-card} [Block Data Attribute (1)](groups/block_data_attribute.md){.group-card}
+[Bit Operation (8)](groups/bit_operation.md){.group-card} [Block Argument (3)](groups/block_argument.md){.group-card} [Block Control Attribute (1)](groups/block_control_attribute.md){.group-card} [Block Data Attribute (1)](groups/block_data_attribute.md){.group-card}
 [Block Dimension (2)](groups/block_dimension.md){.group-card} [Block Hint (2)](groups/block_hint.md){.group-card} [Block Input & Output (6)](groups/block_input_output.md){.group-card} [Block Offset (1)](groups/block_offset.md){.group-card}
-[Block Split (59)](groups/block_split.md){.group-card} [Branch (10)](groups/branch.md){.group-card} [C.BSTART (7)](groups/c_bstart.md){.group-card} [C.TINST (6)](groups/c_tinst.md){.group-card}
+[Block Split (57)](groups/block_split.md){.group-card} [Branch (10)](groups/branch.md){.group-card} [C.BSTART (7)](groups/c_bstart.md){.group-card} [C.TINST (6)](groups/c_tinst.md){.group-card}
 [C.UNARY (7)](groups/c_unary.md){.group-card} [Cache Maintain (16)](groups/cache_maintain.md){.group-card} [Compare Instruction (40)](groups/compare_instruction.md){.group-card} [Compound Operation (1)](groups/compound_operation.md){.group-card}
 [Concat (2)](groups/concat.md){.group-card} [DMA Operation (1)](groups/dma_operation.md){.group-card} [Division (2)](groups/division.md){.group-card} [Execution Control (10)](groups/execution_control.md){.group-card}
 [Floating Point Arithmetic (5)](groups/floating_point_arithmetic.md){.group-card} [Floating-point Arithmetic (12)](groups/floating_point_arithmetic.md){.group-card} [Floating-point Compare (8)](groups/floating_point_compare.md){.group-card} [Format Convert (12)](groups/format_convert.md){.group-card}
@@ -114,10 +114,9 @@ Use **Ctrl+F** / **Cmd+F** to search, or browse the [full alphabetical list](ins
 | [HL.ADDTPC](instructions/hl_addtpc.md) | pc_relative | 48 | [48-bit HL.] Instruction from the PC-Relative group. |
 | [HL.SETRET](instructions/hl_setret.md) | pc_relative | 48 | [48-bit HL.] Instruction from the PC-Relative group. |
 | [SETRET](instructions/setret.md) | pc_relative | 32 | Materializes a return address (ra) using a PC-relative offset. Used in call headers. |
-| [B.ARG](instructions/b_arg.md) | block_argument | 32 | Instruction from the Block Argument group. |
-| [B.DIM](instructions/b_dim.md) | block_argument | 32 | Instruction from the Block Argument group. |
 | [B.CATR](instructions/b_catr.md) | block_control_attribute | 32 | Instruction from the Block Control Attribute group. |
 | [B.DATR](instructions/b_datr.md) | block_data_attribute | 32 | Instruction from the Block Data Attribute group. |
+| [B.DIM](instructions/b_dim.md) | block_argument | 32 | Instruction from the Block Argument group. |
 | [B.EQ](instructions/b_eq.md) | branch | 32 | Conditional branch taken when SrcL equals SrcR. |
 | [B.GE](instructions/b_ge.md) | branch | 32 | Conditional branch taken when SrcL is greater than or equal to SrcR (signed). |
 | [B.GEU](instructions/b_geu.md) | branch | 32 | Conditional branch taken when SrcL is greater than or equal to SrcR (unsigned). |
@@ -139,9 +138,9 @@ Use **Ctrl+F** / **Cmd+F** to search, or browse the [full alphabetical list](ins
 | [BXU](instructions/bxu.md) | bit_operation | 32 | Bit-field extract unsigned. |
 | [BSTART](instructions/bstart.md) | block_split | 32 | Block split marker. Terminates the current basic block and begins the next. Encodes block type and transition kind. |
 | [BSTART.ACCCVT](instructions/bstart_acccvt.md) | block_split | 32 | Terminates the current block and begins the next. |
-| [BSTART.CUBE](instructions/bstart_cube.md) | block_split | 32 | Terminates the current block and begins the next. |
-| [BSTART.FIXP](instructions/bstart_fixp.md) | block_split | 32 | Terminates the current block and begins the next. |
 | [BSTART.FP](instructions/bstart_fp.md) | block_split | 32 | Terminates the current block and begins the next. |
+| [BSTART.MGATHER](instructions/bstart_mgather.md) | block_split | 32 | Terminates the current block and begins the next. |
+| [BSTART.MGATHER.CAS](instructions/bstart_mgather_cas.md) | block_split | 32 | Terminates the current block and begins the next. |
 | [BSTART CALL](instructions/bstart_call.md) | bstart | 32 | Atomic fused call with independent call-target and return-target fields; transfers to the call block and writes `ra`. This exact aggregate is distinct from the generic bare-call form, which preserves `ra` and requires an adjacent `SETRET` or `C.SETRET`. |
 | [HL.BSTART CALL](instructions/hl_bstart_call.md) | bstart | 48 | [48-bit HL.] Atomic fused call with independent call-target and return-target fields; transfers to the call block and writes `ra`. This exact aggregate is distinct from the generic bare-call form, which preserves `ra` and requires an adjacent `SETRET` or `C.SETRET`. |
 | [HL.BSTART.FP](instructions/hl_bstart_fp.md) | bstart | 48 | [48-bit HL.] Terminates the current block and begins the next. |
@@ -365,4 +364,4 @@ Use **Ctrl+F** / **Cmd+F** to search, or browse the [full alphabetical list](ins
 | [V.SHFL.UP](instructions/v_shfl_up.md) | shuffle | 64 | [64-bit V.] Instruction from the Shuffle group. |
 | [V.SHFLI.BFLY](instructions/v_shfli_bfly.md) | shuffle | 64 | [64-bit V.] Instruction from the Shuffle group. |
 
-[View all 769 instruction forms →](instructions/index.md)
+[View all 761 instruction forms →](instructions/index.md)
diff --git a/docs/isa/instructions/b_arg.md b/docs/isa/instructions/b_arg.md
deleted file mode 100644
index 485324f8..00000000
--- a/docs/isa/instructions/b_arg.md
+++ /dev/null
@@ -1,86 +0,0 @@
-# B.ARG
-
-<div class="insn-header">
-
-<span class="badge-32">32-bit Base</span> **Group:** <a href="../groups/block_argument.md">Block Argument</a> &nbsp;|&nbsp;
-<span class="ch-tag ch-tag-04">Ch 04</span>
-&nbsp; <strong>Block ISA — Block-structured Control Flow</strong> &nbsp;|&nbsp;
-**Length:** <code>32</code> &nbsp;|&nbsp; **Decode:** <code>—</code>
-
-</div>
-
-## Assembly Syntax
-
-- `B.ARG NORM.normal`
-- `B.ARG format`
-- `B.ARG NZ2DN.canon`
-- `B.ARG ND2ZN.normal, FP16, Null`
-- `B.ARG DN2ZN.normal, FP16, Null`
-- `B.ARG DN2NZ.normal, FP32, Null`
-
-## Encoding
-
-<div class="enc-diagram">
-
-<figure id="encoding-b_arg_32_374ec956affe">
-<img src="../wavedrom/enc_b_arg_32_374ec956affe.svg" alt="B.ARG encoding form b_arg_32_374ec956affe" width="100%" />
-<figcaption><code>b_arg_32_374ec956affe</code> — <code>B.ARG NORM.normal</code>. MSB is on the left, LSB is on the right.</figcaption>
-</figure>
-
-<figure id="encoding-b_arg_32_47e8ac50ac96">
-<img src="../wavedrom/enc_b_arg_32_47e8ac50ac96.svg" alt="B.ARG encoding form b_arg_32_47e8ac50ac96" width="100%" />
-<figcaption><code>b_arg_32_47e8ac50ac96</code> — <code>B.ARG format</code>. MSB is on the left, LSB is on the right.</figcaption>
-</figure>
-
-<figure id="encoding-b_arg_32_5c8bfa662370">
-<img src="../wavedrom/enc_b_arg_32_5c8bfa662370.svg" alt="B.ARG encoding form b_arg_32_5c8bfa662370" width="100%" />
-<figcaption><code>b_arg_32_5c8bfa662370</code> — <code>B.ARG NZ2DN.canon</code>. MSB is on the left, LSB is on the right.</figcaption>
-</figure>
-
-<figure id="encoding-b_arg_32_95152c29a268">
-<img src="../wavedrom/enc_b_arg_32_95152c29a268.svg" alt="B.ARG encoding form b_arg_32_95152c29a268" width="100%" />
-<figcaption><code>b_arg_32_95152c29a268</code> — <code>B.ARG ND2ZN.normal, FP16, Null</code>. MSB is on the left, LSB is on the right.</figcaption>
-</figure>
-
-<figure id="encoding-b_arg_32_c6d5c49a4ad7">
-<img src="../wavedrom/enc_b_arg_32_c6d5c49a4ad7.svg" alt="B.ARG encoding form b_arg_32_c6d5c49a4ad7" width="100%" />
-<figcaption><code>b_arg_32_c6d5c49a4ad7</code> — <code>B.ARG DN2ZN.normal, FP16, Null</code>. MSB is on the left, LSB is on the right.</figcaption>
-</figure>
-
-<figure id="encoding-b_arg_32_f19d18f2126b">
-<img src="../wavedrom/enc_b_arg_32_f19d18f2126b.svg" alt="B.ARG encoding form b_arg_32_f19d18f2126b" width="100%" />
-<figcaption><code>b_arg_32_f19d18f2126b</code> — <code>B.ARG DN2NZ.normal, FP32, Null</code>. MSB is on the left, LSB is on the right.</figcaption>
-</figure>
-
-</div>
-
-## Description
-
-Instruction from the Block Argument group.
-
-## Pseudocode (informative)
-
-```c
-// Execute B.ARG as defined by the Block Argument semantics.
-```
-
-## Encoding Notes
-
-_No additional encoding notes._
-
-## Full Catalog Forms
-
-| Form ID | Assembly | Length | Decode | Encoding |
-|---------|----------|--------|--------|----------|
-| `b_arg_32_374ec956affe` | `B.ARG NORM.normal` | 32 | — | [SVG](../wavedrom/enc_b_arg_32_374ec956affe.svg) |
-| `b_arg_32_47e8ac50ac96` | `B.ARG format` | 32 | — | [SVG](../wavedrom/enc_b_arg_32_47e8ac50ac96.svg) |
-| `b_arg_32_5c8bfa662370` | `B.ARG NZ2DN.canon` | 32 | — | [SVG](../wavedrom/enc_b_arg_32_5c8bfa662370.svg) |
-| `b_arg_32_95152c29a268` | `B.ARG ND2ZN.normal, FP16, Null` | 32 | — | [SVG](../wavedrom/enc_b_arg_32_95152c29a268.svg) |
-| `b_arg_32_c6d5c49a4ad7` | `B.ARG DN2ZN.normal, FP16, Null` | 32 | — | [SVG](../wavedrom/enc_b_arg_32_c6d5c49a4ad7.svg) |
-| `b_arg_32_f19d18f2126b` | `B.ARG DN2NZ.normal, FP32, Null` | 32 | — | [SVG](../wavedrom/enc_b_arg_32_f19d18f2126b.svg) |
-
-<div class="insn-nav">
-
-← [Block Argument](../groups/block_argument.md) &nbsp;&nbsp; [Index](../index.md) &nbsp;&nbsp; [All instructions](index.md) →
-
-</div>
diff --git a/docs/isa/instructions/b_catr.md b/docs/isa/instructions/b_catr.md
index 25bbfc47..beecd852 100644
--- a/docs/isa/instructions/b_catr.md
+++ b/docs/isa/instructions/b_catr.md
@@ -36,7 +36,7 @@ Instruction from the Block Control Attribute group.
 
 ## Encoding Notes
 
-- `canonical split of legacy B.CATR/B.DATR control fields. Bits 25:15 are reserved zero.`
+- `PTO ISA 0.57.1 control attributes. Only DR[26], trap[19], far[18], atom[17], aq[16], and rl[15] are variable.`
 
 ## Full Catalog Forms
 
diff --git a/docs/isa/instructions/b_datr.md b/docs/isa/instructions/b_datr.md
index 493cfca5..5f3fc8c3 100644
--- a/docs/isa/instructions/b_datr.md
+++ b/docs/isa/instructions/b_datr.md
@@ -11,7 +11,7 @@
 
 ## Assembly Syntax
 
-- `B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat}`
+- `B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}`
 
 ## Encoding
 
@@ -36,13 +36,13 @@ Instruction from the Block Data Attribute group.
 
 ## Encoding Notes
 
-- `canonical split of legacy B.CATR/B.DATR data fields. CMode is 3 bits; RMode is 3 bits; Sat is bit 31.`
+- `PTO ISA 0.57.1 data attributes. PadValueOrByteId is an opcode-defined two-bit union; bits 19:18 are reserved zero.`
 
 ## Full Catalog Forms
 
 | Assembly | Length | Decode |
 |----------|--------|--------|
-| `B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat}` | 32 | — |
+| `B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}` | 32 | — |
 
 <div class="insn-nav">
 
diff --git a/docs/isa/instructions/b_iot.md b/docs/isa/instructions/b_iot.md
index 53e8ae5f..6fc978a1 100644
--- a/docs/isa/instructions/b_iot.md
+++ b/docs/isa/instructions/b_iot.md
@@ -12,38 +12,38 @@
 ## Assembly Syntax
 
 - `B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>`
-- `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>`
 - `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>`
 - `B.IOT SrcTile0<.reuse>, <last>`
 - `B.IOT <last>, ->DstTile<Size>`
+- `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>`
 
 ## Encoding
 
 <div class="enc-diagram">
 
-<figure id="encoding-b_iot_32_10db6db84f5d">
-<img src="../wavedrom/enc_b_iot_32_10db6db84f5d.svg" alt="B.IOT encoding form b_iot_32_10db6db84f5d" width="100%" />
-<figcaption><code>b_iot_32_10db6db84f5d</code> — <code>B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size></code>. MSB is on the left, LSB is on the right.</figcaption>
+<figure id="encoding-b_iot_32_0f23e46d6176">
+<img src="../wavedrom/enc_b_iot_32_0f23e46d6176.svg" alt="B.IOT encoding form b_iot_32_0f23e46d6176" width="100%" />
+<figcaption><code>b_iot_32_0f23e46d6176</code> — <code>B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size></code>. MSB is on the left, LSB is on the right.</figcaption>
 </figure>
 
-<figure id="encoding-b_iot_32_2c07e7177fad">
-<img src="../wavedrom/enc_b_iot_32_2c07e7177fad.svg" alt="B.IOT encoding form b_iot_32_2c07e7177fad" width="100%" />
-<figcaption><code>b_iot_32_2c07e7177fad</code> — <code>B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last></code>. MSB is on the left, LSB is on the right.</figcaption>
+<figure id="encoding-b_iot_32_3a6945dec034">
+<img src="../wavedrom/enc_b_iot_32_3a6945dec034.svg" alt="B.IOT encoding form b_iot_32_3a6945dec034" width="100%" />
+<figcaption><code>b_iot_32_3a6945dec034</code> — <code>B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size></code>. MSB is on the left, LSB is on the right.</figcaption>
 </figure>
 
-<figure id="encoding-b_iot_32_8b8bce6bffe8">
-<img src="../wavedrom/enc_b_iot_32_8b8bce6bffe8.svg" alt="B.IOT encoding form b_iot_32_8b8bce6bffe8" width="100%" />
-<figcaption><code>b_iot_32_8b8bce6bffe8</code> — <code>B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size></code>. MSB is on the left, LSB is on the right.</figcaption>
+<figure id="encoding-b_iot_32_778f84340400">
+<img src="../wavedrom/enc_b_iot_32_778f84340400.svg" alt="B.IOT encoding form b_iot_32_778f84340400" width="100%" />
+<figcaption><code>b_iot_32_778f84340400</code> — <code>B.IOT SrcTile0<.reuse>, <last></code>. MSB is on the left, LSB is on the right.</figcaption>
 </figure>
 
-<figure id="encoding-b_iot_32_c11eb189dd83">
-<img src="../wavedrom/enc_b_iot_32_c11eb189dd83.svg" alt="B.IOT encoding form b_iot_32_c11eb189dd83" width="100%" />
-<figcaption><code>b_iot_32_c11eb189dd83</code> — <code>B.IOT SrcTile0<.reuse>, <last></code>. MSB is on the left, LSB is on the right.</figcaption>
+<figure id="encoding-b_iot_32_a06b9b6c1965">
+<img src="../wavedrom/enc_b_iot_32_a06b9b6c1965.svg" alt="B.IOT encoding form b_iot_32_a06b9b6c1965" width="100%" />
+<figcaption><code>b_iot_32_a06b9b6c1965</code> — <code>B.IOT <last>, ->DstTile<Size></code>. MSB is on the left, LSB is on the right.</figcaption>
 </figure>
 
-<figure id="encoding-b_iot_32_efa0fe3fe49a">
-<img src="../wavedrom/enc_b_iot_32_efa0fe3fe49a.svg" alt="B.IOT encoding form b_iot_32_efa0fe3fe49a" width="100%" />
-<figcaption><code>b_iot_32_efa0fe3fe49a</code> — <code>B.IOT <last>, ->DstTile<Size></code>. MSB is on the left, LSB is on the right.</figcaption>
+<figure id="encoding-b_iot_32_f1ca66bbcce1">
+<img src="../wavedrom/enc_b_iot_32_f1ca66bbcce1.svg" alt="B.IOT encoding form b_iot_32_f1ca66bbcce1" width="100%" />
+<figcaption><code>b_iot_32_f1ca66bbcce1</code> — <code>B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last></code>. MSB is on the left, LSB is on the right.</figcaption>
 </figure>
 
 </div>
@@ -60,21 +60,21 @@ Instruction from the Block Input & Output group.
 
 ## Encoding Notes
 
-- `canonical one-input immediate-size tile descriptor; function=101 means only SrcTile0 is valid. v0.57 excludes DstTile=111 from this destination-producing form.`
-- `v0.57 two-input source-only tile descriptor required by multi-descriptor PTO expansions. DstTile=111 denotes no output and the unused size field is canonically zero.`
-- `canonical two-input immediate-size tile descriptor. SrcTile0/1 are independent 6-bit fields; imm4 encodes 0B..512KB. v0.57 excludes DstTile=111 from this destination-producing form.`
-- `v0.57 one-input source-only tile descriptor required by multi-descriptor PTO expansions. DstTile=111 denotes no output and the unused size field is canonically zero.`
-- `canonical no-input immediate-size tile descriptor; function=110 means only the destination allocation is valid.`
+- `PTO ISA 0.57.1 one-source descriptor. Inactive source and reuse fields encode zero.`
+- `PTO ISA 0.57.1 two-source descriptor. imm4 3..9 selects 128B..8KiB; ACC is never encoded as DstTile.`
+- `PTO ISA 0.57.1 one-source destination-free descriptor. All inapplicable fields encode zero.`
+- `PTO ISA 0.57.1 zero-source destination descriptor. Inactive source and reuse fields encode zero.`
+- `PTO ISA 0.57.1 two-source destination-free descriptor. DstTile and imm4 encode zero; zero does not name an output.`
 
 ## Full Catalog Forms
 
 | Form ID | Assembly | Length | Decode | Encoding |
 |---------|----------|--------|--------|----------|
-| `b_iot_32_10db6db84f5d` | `B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_10db6db84f5d.svg) |
-| `b_iot_32_2c07e7177fad` | `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_2c07e7177fad.svg) |
-| `b_iot_32_8b8bce6bffe8` | `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_8b8bce6bffe8.svg) |
-| `b_iot_32_c11eb189dd83` | `B.IOT SrcTile0<.reuse>, <last>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_c11eb189dd83.svg) |
-| `b_iot_32_efa0fe3fe49a` | `B.IOT <last>, ->DstTile<Size>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_efa0fe3fe49a.svg) |
+| `b_iot_32_0f23e46d6176` | `B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_0f23e46d6176.svg) |
+| `b_iot_32_3a6945dec034` | `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_3a6945dec034.svg) |
+| `b_iot_32_778f84340400` | `B.IOT SrcTile0<.reuse>, <last>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_778f84340400.svg) |
+| `b_iot_32_a06b9b6c1965` | `B.IOT <last>, ->DstTile<Size>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_a06b9b6c1965.svg) |
+| `b_iot_32_f1ca66bbcce1` | `B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>` | 32 | — | [SVG](../wavedrom/enc_b_iot_32_f1ca66bbcce1.svg) |
 
 <div class="insn-nav">
 
diff --git a/docs/isa/instructions/bstart_acccvt.md b/docs/isa/instructions/bstart_acccvt.md
index 76858d75..7f71a82d 100644
--- a/docs/isa/instructions/bstart_acccvt.md
+++ b/docs/isa/instructions/bstart_acccvt.md
@@ -36,7 +36,7 @@ EndBlock(); BeginNextBlock(/* kind */);
 
 ## Encoding Notes
 
-- `Alias of BSTART.CUBE Function=8. ACCCVT requires quantization args via B.ARG+B.IOR (scale/zero-point required in strict profile).`
+- `Named CUBE-family Function=8. ACCCVT reads implicit ACC and uses B.DATR conversion controls before publishing an ordinary Tile.`
 
 ## Full Catalog Forms
 
diff --git a/docs/isa/instructions/bstart_cube.md b/docs/isa/instructions/bstart_cube.md
deleted file mode 100644
index 057045e1..00000000
--- a/docs/isa/instructions/bstart_cube.md
+++ /dev/null
@@ -1,51 +0,0 @@
-# BSTART.CUBE
-
-<div class="insn-header">
-
-<span class="badge-32">32-bit Base</span> **Group:** <a href="../groups/block_split.md">Block Split</a> &nbsp;|&nbsp;
-<span class="ch-tag ch-tag-04">Ch 04</span>
-&nbsp; <strong>Block ISA — Block-structured Control Flow</strong> &nbsp;|&nbsp;
-**Length:** <code>32</code> &nbsp;|&nbsp; **Decode:** <code>—</code>
-
-</div>
-
-## Assembly Syntax
-
-- `BSTART.CUBE Function, DataType`
-
-## Encoding
-
-<div class="enc-diagram">
-
-<figure>
-<img src="../wavedrom/enc_bstart_cube.svg" alt="BSTART.CUBE encoding" width="100%" />
-<figcaption>Bitfield encoding diagram. MSB is on the left, LSB on the right.</figcaption>
-</figure>
-
-</div>
-
-## Description
-
-Terminates the current block and begins the next.
-
-## Pseudocode (informative)
-
-```c
-EndBlock(); BeginNextBlock(/* kind */);
-```
-
-## Encoding Notes
-
-- `Generic CUBE selector form for unnamed functions. Functions 0/1/2/4/5/6/8/16/17/18/20/21/22 decode through their canonical named forms.`
-
-## Full Catalog Forms
-
-| Assembly | Length | Decode |
-|----------|--------|--------|
-| `BSTART.CUBE Function, DataType` | 32 | — |
-
-<div class="insn-nav">
-
-← [Block Split](../groups/block_split.md) &nbsp;&nbsp; [Index](../index.md) &nbsp;&nbsp; [All instructions](index.md) →
-
-</div>
diff --git a/docs/isa/instructions/bstart_fixp.md b/docs/isa/instructions/bstart_fixp.md
deleted file mode 100644
index 492ab423..00000000
--- a/docs/isa/instructions/bstart_fixp.md
+++ /dev/null
@@ -1,51 +0,0 @@
-# BSTART.FIXP
-
-<div class="insn-header">
-
-<span class="badge-32">32-bit Base</span> **Group:** <a href="../groups/block_split.md">Block Split</a> &nbsp;|&nbsp;
-<span class="ch-tag ch-tag-04">Ch 04</span>
-&nbsp; <strong>Block ISA — Block-structured Control Flow</strong> &nbsp;|&nbsp;
-**Length:** <code>32</code> &nbsp;|&nbsp; **Decode:** <code>—</code>
-
-</div>
-
-## Assembly Syntax
-
-- `BSTART.FIXP TileOp, DataType`
-
-## Encoding
-
-<div class="enc-diagram">
-
-<figure>
-<img src="../wavedrom/enc_bstart_fixp.svg" alt="BSTART.FIXP encoding" width="100%" />
-<figcaption>Bitfield encoding diagram. MSB is on the left, LSB on the right.</figcaption>
-</figure>
-
-</div>
-
-## Description
-
-Terminates the current block and begins the next.
-
-## Pseudocode (informative)
-
-```c
-EndBlock(); BeginNextBlock(/* kind */);
-```
-
-## Encoding Notes
-
-_No additional encoding notes._
-
-## Full Catalog Forms
-
-| Assembly | Length | Decode |
-|----------|--------|--------|
-| `BSTART.FIXP TileOp, DataType` | 32 | — |
-
-<div class="insn-nav">
-
-← [Block Split](../groups/block_split.md) &nbsp;&nbsp; [Index](../index.md) &nbsp;&nbsp; [All instructions](index.md) →
-
-</div>
diff --git a/docs/isa/instructions/bstart_mgather.md b/docs/isa/instructions/bstart_mgather.md
index 4bc90e2c..aee4ad35 100644
--- a/docs/isa/instructions/bstart_mgather.md
+++ b/docs/isa/instructions/bstart_mgather.md
@@ -36,7 +36,7 @@ EndBlock(); BeginNextBlock(/* kind */);
 
 ## Encoding Notes
 
-- `Named TMA-family Function=4. Memory gather uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57.`
+- `TMA Function=4. Memory gather uses B.DATR/B.IOR/B.IOT descriptor state.`
 
 ## Full Catalog Forms
 
diff --git a/docs/isa/instructions/bstart_mscatter.md b/docs/isa/instructions/bstart_mscatter.md
index 03d50f9d..8d31d048 100644
--- a/docs/isa/instructions/bstart_mscatter.md
+++ b/docs/isa/instructions/bstart_mscatter.md
@@ -36,7 +36,7 @@ EndBlock(); BeginNextBlock(/* kind */);
 
 ## Encoding Notes
 
-- `Named TMA-family Function=5. Memory scatter uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57.`
+- `TMA Function=5. Memory scatter uses B.DATR/B.IOR/B.IOT descriptor state.`
 
 ## Full Catalog Forms
 
diff --git a/docs/isa/instructions/bstart_tepl.md b/docs/isa/instructions/bstart_tepl.md
index f2e3d8ec..861b4eba 100644
--- a/docs/isa/instructions/bstart_tepl.md
+++ b/docs/isa/instructions/bstart_tepl.md
@@ -11,7 +11,7 @@
 
 ## Assembly Syntax
 
-- `BSTART.TEPL TileOpcode, DataType`
+- `BSTART.TEPL Mode, Function, DataType`
 
 ## Encoding
 
@@ -36,13 +36,13 @@ EndBlock(); BeginNextBlock(/* kind */);
 
 ## Encoding Notes
 
-- `Tile opcode selects PTO template ops. Canonical established assignments require TileOpcode[9:6]=0 and pack TileOpcode[5]=Mode with TileOpcode[4:0]=Function; unassigned values remain reserved for future template extension.`
+- `PTO ISA 0.57.1 TEPL selector: logical_selector=(Mode<<5)|Function. There is no legacy 10-bit TileOpcode decode.`
 
 ## Full Catalog Forms
 
 | Assembly | Length | Decode |
 |----------|--------|--------|
-| `BSTART.TEPL TileOpcode, DataType` | 32 | — |
+| `BSTART.TEPL Mode, Function, DataType` | 32 | — |
 
 <div class="insn-nav">
 
diff --git a/docs/isa/instructions/bstart_tload.md b/docs/isa/instructions/bstart_tload.md
index 15307e3f..0415d005 100644
--- a/docs/isa/instructions/bstart_tload.md
+++ b/docs/isa/instructions/bstart_tload.md
@@ -36,7 +36,7 @@ EndBlock(); BeginNextBlock(/* kind */);
 
 ## Encoding Notes
 
-- `Alias of BSTART.TMA Function=0. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding.`
+- `TMA Function=0. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding.`
 
 ## Full Catalog Forms
 
diff --git a/docs/isa/instructions/bstart_tmatmul.md b/docs/isa/instructions/bstart_tmatmul.md
index 8a6d20f3..0395b718 100644
--- a/docs/isa/instructions/bstart_tmatmul.md
+++ b/docs/isa/instructions/bstart_tmatmul.md
@@ -36,7 +36,7 @@ EndBlock(); BeginNextBlock(/* kind */);
 
 ## Encoding Notes
 
-- `Alias of BSTART.CUBE Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.`
+- `Named CUBE-family Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.`
 
 ## Full Catalog Forms
 
diff --git a/docs/isa/instructions/bstart_tmatmul_acc.md b/docs/isa/instructions/bstart_tmatmul_acc.md
index fa101b5c..902707f4 100644
--- a/docs/isa/instructions/bstart_tmatmul_acc.md
+++ b/docs/isa/instructions/bstart_tmatmul_acc.md
@@ -36,7 +36,7 @@ EndBlock(); BeginNextBlock(/* kind */);
 
 ## Encoding Notes
 
-- `Alias of BSTART.CUBE Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.`
+- `Named CUBE-family Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT.`
 
 ## Full Catalog Forms
 
diff --git a/docs/isa/instructions/bstart_tstore.md b/docs/isa/instructions/bstart_tstore.md
index eb557464..7454fd52 100644
--- a/docs/isa/instructions/bstart_tstore.md
+++ b/docs/isa/instructions/bstart_tstore.md
@@ -36,7 +36,7 @@ EndBlock(); BeginNextBlock(/* kind */);
 
 ## Encoding Notes
 
-- `Alias of BSTART.TMA Function=1. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding.`
+- `TMA Function=1. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding.`
 
 ## Full Catalog Forms
 
diff --git a/docs/isa/instructions/index.md b/docs/isa/instructions/index.md
index 24b91c57..3eeca07d 100644
--- a/docs/isa/instructions/index.md
+++ b/docs/isa/instructions/index.md
@@ -1,6 +1,6 @@
 # All Instructions
 
-Complete alphabetical index of all **769** instruction forms in the LinxISA v0.57.0 catalog.
+Complete alphabetical index of all **761** instruction forms in the LinxISA v0.57.1 catalog.
 
 Use **Ctrl+F** / **Cmd+F** to search, or click a letter below to jump to it.
 
@@ -27,12 +27,6 @@ Use **Ctrl+F** / **Cmd+F** to search, or click a letter below to jump to it.
 
 | Mnemonic | Group | Bits | Description |
 |----------|-------|------|-------------|
-| [B.ARG](b_arg.md) | [Block Argument](../groups/block_argument.md) | 32 | Instruction from the Block Argument group. |
-| [B.ARG](b_arg.md) | [Block Argument](../groups/block_argument.md) | 32 | Instruction from the Block Argument group. |
-| [B.ARG](b_arg.md) | [Block Argument](../groups/block_argument.md) | 32 | Instruction from the Block Argument group. |
-| [B.ARG](b_arg.md) | [Block Argument](../groups/block_argument.md) | 32 | Instruction from the Block Argument group. |
-| [B.ARG](b_arg.md) | [Block Argument](../groups/block_argument.md) | 32 | Instruction from the Block Argument group. |
-| [B.ARG](b_arg.md) | [Block Argument](../groups/block_argument.md) | 32 | Instruction from the Block Argument group. |
 | [B.CATR](b_catr.md) | [Block Control Attribute](../groups/block_control_attribute.md) | 32 | Instruction from the Block Control Attribute group. |
 | [B.DATR](b_datr.md) | [Block Data Attribute](../groups/block_data_attribute.md) | 32 | Instruction from the Block Data Attribute group. |
 | [B.DIM](b_dim.md) | [Block Argument](../groups/block_argument.md) | 32 | Instruction from the Block Argument group. |
@@ -65,8 +59,6 @@ Use **Ctrl+F** / **Cmd+F** to search, or click a letter below to jump to it.
 | [BSTART](bstart.md) | [Block Split](../groups/block_split.md) | 32 | Block split marker. Terminates the current basic block and begins the next. Encodes block type and transition kind. |
 | [BSTART CALL](bstart_call.md) | [BSTART](../groups/bstart.md) | 32 | Atomic fused call with independent call-target and return-target fields; transfers to the call block and writes `ra`. This exact aggregate is distinct from the generic bare-call form, which preserves `ra` and requires an adjacent `SETRET` or `C.SETRET`. |
 | [BSTART.ACCCVT](bstart_acccvt.md) | [Block Split](../groups/block_split.md) | 32 | Terminates the current block and begins the next. |
-| [BSTART.CUBE](bstart_cube.md) | [Block Split](../groups/block_split.md) | 32 | Terminates the current block and begins the next. |
-| [BSTART.FIXP](bstart_fixp.md) | [Block Split](../groups/block_split.md) | 32 | Terminates the current block and begins the next. |
 | [BSTART.FP](bstart_fp.md) | [Block Split](../groups/block_split.md) | 32 | Terminates the current block and begins the next. |
 | [BSTART.FP](bstart_fp.md) | [Block Split](../groups/block_split.md) | 32 | Terminates the current block and begins the next. |
 | [BSTART.FP](bstart_fp.md) | [Block Split](../groups/block_split.md) | 32 | Terminates the current block and begins the next. |
diff --git a/docs/isa/wavedrom/enc_b_arg_32_374ec956affe.svg b/docs/isa/wavedrom/enc_b_arg_32_374ec956affe.svg
deleted file mode 100644
index ac89ba0d..00000000
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deleted file mode 100644
index 5eb73b40..00000000
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deleted file mode 100644
index e8b6fb9a..00000000
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index 4f2fbe36..00000000
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-  <text x="463.9" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Src…</text>
+  <rect x="6.000" y="25" width="166.500" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="89.2" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">SrcTile1</text>
+  <rect x="172.500" y="25" width="166.500" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="255.8" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">SrcTile0</text>
+  <rect x="339.000" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="352.9" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">L</text>
+  <rect x="366.750" y="25" width="111.000" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
   <rect x="477.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">101</text>
-  <rect x="561.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="630.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">SrcTile0</text>
+  <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">100</text>
+  <rect x="561.000" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="574.9" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">S1R</text>
+  <rect x="588.750" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="602.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">S0R</text>
+  <rect x="616.500" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
   <rect x="699.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
   <text x="741.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
   <rect x="783.000" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
diff --git a/docs/isa/wavedrom/enc_bstart_cube.svg b/docs/isa/wavedrom/enc_bstart_cube.svg
deleted file mode 100644
index 839d499a..00000000
--- a/docs/isa/wavedrom/enc_bstart_cube.svg
+++ /dev/null
@@ -1,34 +0,0 @@
-<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 900 68" width="900" height="68">
-  <defs>
-    <style>
-      text { font-family: 'Courier New', monospace; }
-    </style>
-  </defs>
-  <text x="6" y="15" font-family="Helvetica Neue,Arial,sans-serif" font-weight="bold" font-size="14" fill="#1a1a1a">BSTART.CUBE</text>
-  <text x="19.88" y="8" text-anchor="middle" font-size="8" fill="#999999">31</text>
-  <text x="103.12" y="8" text-anchor="middle" font-size="8" fill="#999999">28</text>
-  <text x="214.12" y="8" text-anchor="middle" font-size="8" fill="#999999">24</text>
-  <text x="325.12" y="8" text-anchor="middle" font-size="8" fill="#999999">20</text>
-  <text x="436.12" y="8" text-anchor="middle" font-size="8" fill="#999999">16</text>
-  <text x="547.12" y="8" text-anchor="middle" font-size="8" fill="#999999">12</text>
-  <text x="658.12" y="8" text-anchor="middle" font-size="8" fill="#999999">8</text>
-  <text x="769.12" y="8" text-anchor="middle" font-size="8" fill="#999999">4</text>
-  <text x="880.12" y="8" text-anchor="middle" font-size="8" fill="#999999">0</text>
-  <rect x="6" y="24" width="888.00" height="28" fill="none" stroke="#999999" stroke-width="0.8"/>
-  <rect x="6.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="75.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">DataType</text>
-  <rect x="144.750" y="25" width="55.500" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="200.250" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="269.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Function</text>
-  <rect x="339.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="408.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x06</text>
-  <rect x="477.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
-  <rect x="561.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="630.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x03</text>
-  <rect x="699.750" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="783.000" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="866.250" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="880.1" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">1</text>
-  <text x="6" y="64" font-size="9" fill="#aaaaaa" font-family="Helvetica Neue,Arial,sans-serif">32-bit encoding</text>
-</svg>
\ No newline at end of file
diff --git a/docs/isa/wavedrom/enc_bstart_fixp.svg b/docs/isa/wavedrom/enc_bstart_fixp.svg
deleted file mode 100644
index 865a48e9..00000000
--- a/docs/isa/wavedrom/enc_bstart_fixp.svg
+++ /dev/null
@@ -1,34 +0,0 @@
-<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 900 68" width="900" height="68">
-  <defs>
-    <style>
-      text { font-family: 'Courier New', monospace; }
-    </style>
-  </defs>
-  <text x="6" y="15" font-family="Helvetica Neue,Arial,sans-serif" font-weight="bold" font-size="14" fill="#1a1a1a">BSTART.FIXP</text>
-  <text x="19.88" y="8" text-anchor="middle" font-size="8" fill="#999999">31</text>
-  <text x="103.12" y="8" text-anchor="middle" font-size="8" fill="#999999">28</text>
-  <text x="214.12" y="8" text-anchor="middle" font-size="8" fill="#999999">24</text>
-  <text x="325.12" y="8" text-anchor="middle" font-size="8" fill="#999999">20</text>
-  <text x="436.12" y="8" text-anchor="middle" font-size="8" fill="#999999">16</text>
-  <text x="547.12" y="8" text-anchor="middle" font-size="8" fill="#999999">12</text>
-  <text x="658.12" y="8" text-anchor="middle" font-size="8" fill="#999999">8</text>
-  <text x="769.12" y="8" text-anchor="middle" font-size="8" fill="#999999">4</text>
-  <text x="880.12" y="8" text-anchor="middle" font-size="8" fill="#999999">0</text>
-  <rect x="6" y="24" width="888.00" height="28" fill="none" stroke="#999999" stroke-width="0.8"/>
-  <rect x="6.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="75.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">DataType</text>
-  <rect x="144.750" y="25" width="55.500" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="200.250" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="269.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Function</text>
-  <rect x="339.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="408.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x07</text>
-  <rect x="477.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
-  <rect x="561.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="630.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x03</text>
-  <rect x="699.750" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="783.000" y="25" width="83.250" height="26" fill="#90A4AE" stroke="white" stroke-width="0.5"/>
-  <rect x="866.250" y="25" width="27.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="880.1" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">1</text>
-  <text x="6" y="64" font-size="9" fill="#aaaaaa" font-family="Helvetica Neue,Arial,sans-serif">32-bit encoding</text>
-</svg>
\ No newline at end of file
diff --git a/docs/isa/wavedrom/enc_bstart_tepl.svg b/docs/isa/wavedrom/enc_bstart_tepl.svg
index c04f1ab1..7b89db94 100644
--- a/docs/isa/wavedrom/enc_bstart_tepl.svg
+++ b/docs/isa/wavedrom/enc_bstart_tepl.svg
@@ -18,9 +18,11 @@
   <rect x="6.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
   <text x="75.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">DataType</text>
   <rect x="144.750" y="25" width="55.500" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
-  <text x="172.5" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">01</text>
-  <rect x="200.250" y="25" width="277.500" height="26" fill="#6A1B9A" stroke="white" stroke-width="0.5"/>
-  <text x="339.0" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">TileOpco</text>
+  <text x="172.5" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Mode</text>
+  <rect x="200.250" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="269.6" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">Function</text>
+  <rect x="339.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
+  <text x="408.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">0x03</text>
   <rect x="477.750" y="25" width="83.250" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
   <text x="519.4" y="41.5" text-anchor="middle" dominant-baseline="middle" font-size="8.5" fill="white" pointer-events="none">001</text>
   <rect x="561.000" y="25" width="138.750" height="26" fill="#607D8B" stroke="white" stroke-width="0.5"/>
diff --git a/docs/reference/examples/v0.57/README.md b/docs/reference/examples/v0.57/README.md
index e6be4a09..39af85f7 100644
--- a/docs/reference/examples/v0.57/README.md
+++ b/docs/reference/examples/v0.57/README.md
@@ -1,25 +1,26 @@
-# LinxISA Assembly Sample Pack (v0.57)
+# LinxISA Assembly Sample Pack (v0.57.1)
 
-Canonical public assembly examples for LinxISA v0.57.
+Canonical public assembly examples generated from the locked PTO ISA 0.57.1
+kernel surface.
 
 ## Layout
 
-- `curated/`: reviewed hand-curated examples.
-- `scratch-legacy/`: selected migrated scratch assembly (public allowlist).
-- `generated/`: deterministic outputs generated from PTO examples.
-- `legacy-reference/`: moved historical reference examples.
-- `index.yaml`: manifest with provenance and generation commands.
+- `curated/`: reviewed hand-curated scalar/disassembly examples.
+- `generated/`: deterministic compiler outputs from
+  `workloads/pto_kernels/tools/examples/`.
+- `index.yaml`: exact source and toolchain provenance.
 
-## Canonical Example
+## Canonical tile example
 
 ```asm
-BSTART.TLOAD FP16
-B.ARG        ND2ZN.normal, FP16, Null
-B.IOT       [], last ->t<4KB>
-B.IOR        [x2,a6],[]
-C.B.DIMI     64, ->lb0
-C.B.DIMI     64, ->lb1
-C.B.DIMI     64, ->lb2
+BSTART.TLOAD INT32
+B.DIM        a3, 0, ->lb0
+B.DIM        a3, 0, ->lb1
+B.DIM        a3, 0, ->lb2
+B.IOR        [a6,a7],[]
+B.IOT        last, ->t<4KB>
 ```
 
-Source: `docs/reference/examples/v0.57/curated/linxisa-v0.57-normalized.asm`
+The 0.57.1 examples contain no `B.ARG`, generic `BSTART.TMA` or
+`BSTART.CUBE`, `MAMULB`, or deleted D-class operation. Regenerate them with the
+LLVM and PTO-Kernel commits recorded in `index.yaml`.
diff --git a/docs/reference/examples/v0.57/generated/pto_flash_attention_auto.s b/docs/reference/examples/v0.57/generated/pto_flash_attention_auto.s
index 3d361f76..eb4a057c 100644
--- a/docs/reference/examples/v0.57/generated/pto_flash_attention_auto.s
+++ b/docs/reference/examples/v0.57/generated/pto_flash_attention_auto.s
@@ -1,400 +1,390 @@
-	.file	"pto_flash_attention_auto.cpp" # LinxISA v0.57
+	.file	"pto_flash_attention_auto.cpp"
 	.text
 	.globl	pto_flash_attention_auto_i32    #  -- Begin function pto_flash_attention_auto_i32
 	.p2align	1
 	.type	pto_flash_attention_auto_i32,@function
 pto_flash_attention_auto_i32:           #  @pto_flash_attention_auto_i32
 #  %bb.0:
-FENTRY	[ra ~ ra], sp!, 16
-#  %bb.2:
-BSTART	CALL, _ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi, ra=.LBB0_1
-.LBB0_1:                                #  Label of block must be emitted
-FRET.STK	[ra ~ ra], sp!, 16
-.Lfunc_end0:
-	.size	pto_flash_attention_auto_i32, .Lfunc_end0-pto_flash_attention_auto_i32
-                                        #  -- End function
-	.section	.text._ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi,"axG",@progbits,_ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi,comdat
-	.weak	_ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi #  -- Begin function _ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi
-	.p2align	1
-	.type	_ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi,@function
-_ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi: #  @_ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi
-#  %bb.0:
 FENTRY	[ra ~ ra], sp!, 8
 #  %bb.1:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a0],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.3:
 C.BSTART.STD
-hl.addi	a0, 4096,	->a4
+c.movr	zero,	->a4
+c.movi	8,	->a5
+#  %bb.3:
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	last, ->t<4KB>
 #  %bb.4:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a4],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.5:
 C.BSTART.STD
-hl.addi	a0, 8192,	->a4
+hl.addi	a0, 4096,	->a6
+#  %bb.5:
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a6,a4],[]
+B.IOT	last, ->t<4KB>
 #  %bb.6:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a4],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.7:
 C.BSTART.STD
-hl.addi	a0, 12288,	->a4
+hl.addi	a0, 8192,	->a6
+#  %bb.7:
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a6,a4],[]
+B.IOT	last, ->t<4KB>
 #  %bb.8:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a4],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.9:
 C.BSTART.STD
-hl.addi	a0, 16384,	->a4
+hl.addi	a0, 12288,	->a6
+#  %bb.9:
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a6,a4],[]
+B.IOT	last, ->t<4KB>
 #  %bb.10:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a4],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.11:
 C.BSTART.STD
-hl.addi	a1, 16384,	->a4
-hl.addi	a1, 12288,	->a5
-hl.addi	a1, 8192,	->a6
-hl.addi	a1, 4096,	->a7
+hl.addi	a0, 16384,	->a0
+#  %bb.11:
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	last, ->t<4KB>
 #  %bb.12:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a1],[]
-B.IOT	[], last	->t<4KB>
+C.BSTART.STD
+hl.addi	a1, 16384,	->a0
+hl.addi	a1, 12288,	->a6
+hl.addi	a1, 8192,	->a7
+hl.addi	a1, 4096,	->x0
 #  %bb.13:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a7],[]
-B.IOT	[], last	->t<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a1,a4],[]
+B.IOT	last, ->t<4KB>
 #  %bb.14:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a6],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[x0,a4],[]
+B.IOT	last, ->t<4KB>
 #  %bb.15:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a5],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a7,a4],[]
+B.IOT	last, ->t<4KB>
 #  %bb.16:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a4],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a6,a4],[]
+B.IOT	last, ->u<4KB>
 #  %bb.17:
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	last, ->u<4KB>
+#  %bb.18:
 C.BSTART.STD
-hl.addi	a2, 12288,	->a4
-hl.addi	a2, 8192,	->a5
+hl.addi	a2, 12288,	->a0
+hl.addi	a2, 8192,	->a1
 hl.addi	a2, 4096,	->a6
-#  %bb.18:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[], last	->t<4KB>
 #  %bb.19:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a6],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a2,a4],[]
+B.IOT	last, ->u<4KB>
 #  %bb.20:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a5],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a6,a4],[]
+B.IOT	last, ->u<4KB>
 #  %bb.21:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a4],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a1,a4],[]
+B.IOT	last, ->u<4KB>
 #  %bb.22:
-BSTART.CUBE	MAMULB, INT32
-C.B.DIMI	8, 	->lb0
-C.B.DIMI	8, 	->lb1
-C.B.DIMI	8, 	->lb2
-B.IOT	[t#2, t#7], last	->acc<4KB>
-#  %bb.57:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	last, ->u<4KB>
 #  %bb.23:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#3, t#8], last	->acc<4KB>
+B.IOT	t#8.reuse, t#3, last
 #  %bb.58:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.24:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#4, u#1], last	->acc<4KB>
+B.IOT	t#6.reuse, t#2.reuse, last
 #  %bb.59:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.25:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#5, u#2], last	->acc<4KB>
+B.IOT	t#5.reuse, t#1.reuse, last
 #  %bb.60:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.26:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#6, u#3], last	->acc<4KB>
+B.IOT	t#4.reuse, u#6.reuse, last
 #  %bb.61:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.27:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#2, t#8], last	->acc<4KB>
+B.IOT	t#3, u#5.reuse, last
 #  %bb.62:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.28:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#3, u#1], last	->acc<4KB>
+B.IOT	t#6, t#2, last
 #  %bb.63:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.29:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#4, u#2], last	->acc<4KB>
+B.IOT	t#4, t#1, last
 #  %bb.64:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.30:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#5, u#3], last	->acc<4KB>
+B.IOT	t#2, u#6, last
 #  %bb.65:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->n<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.31:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[m#1, t#1], last	->acc<4KB>
+B.IOT	t#1, u#5, last
 #  %bb.66:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->n<4KB>
 #  %bb.32:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[m#1], last	->t<4KB>
-#  %bb.33:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[m#2, u#4], last	->acc<4KB>
+B.IOT	m#8, u#4.reuse, last
 #  %bb.67:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
+#  %bb.33:
+BSTART.TMATMUL	INT32
+C.B.DIMI	8, 	->lb0
+C.B.DIMI	8, 	->lb1
+C.B.DIMI	8, 	->lb2
+B.IOT	m#8, u#3.reuse, last
+#  %bb.68:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.34:
-C.BSTART.STD
-hl.addi	a3, 4096,	->a2
+BSTART.TMATMUL	INT32
+C.B.DIMI	8, 	->lb0
+C.B.DIMI	8, 	->lb1
+C.B.DIMI	8, 	->lb2
+B.IOT	m#8, u#2.reuse, last
+#  %bb.69:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.35:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
+BSTART.TMATMUL	INT32
+C.B.DIMI	8, 	->lb0
+C.B.DIMI	8, 	->lb1
+C.B.DIMI	8, 	->lb2
+B.IOT	m#8, u#1.reuse, last
+#  %bb.70:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.36:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[m#3, u#5], last	->acc<4KB>
-#  %bb.68:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+B.IOT	m#8, u#4.reuse, last
+#  %bb.71:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.37:
-C.BSTART.STD
-hl.addi	a3, 8192,	->a2
+BSTART.TMATMUL	INT32
+C.B.DIMI	8, 	->lb0
+C.B.DIMI	8, 	->lb1
+C.B.DIMI	8, 	->lb2
+B.IOT	m#8, u#3, last
+#  %bb.72:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.38:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
+BSTART.TMATMUL	INT32
+C.B.DIMI	8, 	->lb0
+C.B.DIMI	8, 	->lb1
+C.B.DIMI	8, 	->lb2
+B.IOT	m#8, u#2, last
+#  %bb.73:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.39:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[m#4, u#6], last	->acc<4KB>
-#  %bb.69:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+B.IOT	m#8, u#1, last
+#  %bb.74:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.40:
-C.BSTART.STD
-hl.addi	a3, 12288,	->a2
-#  %bb.41:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
-#  %bb.42:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[m#5, t#1], last	->acc<4KB>
-#  %bb.70:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
-#  %bb.43:
+B.IOT	n#1, u#1, last
+#  %bb.75:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->n<4KB>
+#  %bb.41:
+BSTART.TSTORE	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a3,a4],[]
+B.IOT	m#8, last
+#  %bb.42:
 C.BSTART.STD
-hl.addi	a3, 16384,	->a2
+hl.addi	a3, 4096,	->a0
+#  %bb.43:
+BSTART.TSTORE	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	m#7, last
 #  %bb.44:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
+C.BSTART.STD
+hl.addi	a3, 8192,	->a0
 #  %bb.45:
-BSTART.CUBE	MAMULB, INT32
-C.B.DIMI	8, 	->lb0
-C.B.DIMI	8, 	->lb1
-C.B.DIMI	8, 	->lb2
-B.IOT	[m#6, u#4], last	->acc<4KB>
-#  %bb.71:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.TSTORE	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	m#6, last
 #  %bb.46:
 C.BSTART.STD
-hl.addi	a3, 20480,	->a2
+hl.addi	a3, 12288,	->a0
 #  %bb.47:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
+BSTART.TSTORE	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	m#5, last
 #  %bb.48:
-BSTART.CUBE	MAMULB, INT32
-C.B.DIMI	8, 	->lb0
-C.B.DIMI	8, 	->lb1
-C.B.DIMI	8, 	->lb2
-B.IOT	[m#7, u#5], last	->acc<4KB>
-#  %bb.72:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
-#  %bb.49:
 C.BSTART.STD
-hl.addi	a3, 24576,	->a2
+hl.addi	a3, 16384,	->a0
+#  %bb.49:
+BSTART.TSTORE	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	m#4, last
 #  %bb.50:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
+C.BSTART.STD
+hl.addi	a3, 20480,	->a0
 #  %bb.51:
-BSTART.CUBE	MAMULB, INT32
-C.B.DIMI	8, 	->lb0
-C.B.DIMI	8, 	->lb1
-C.B.DIMI	8, 	->lb2
-B.IOT	[m#8, u#6], last	->acc<4KB>
-#  %bb.73:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.TSTORE	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	m#3, last
 #  %bb.52:
 C.BSTART.STD
-hl.addi	a3, 28672,	->a2
+hl.addi	a3, 24576,	->a0
 #  %bb.53:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
+BSTART.TSTORE	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	m#2, last
 #  %bb.54:
-BSTART.CUBE	MAMULB, INT32
-C.B.DIMI	8, 	->lb0
-C.B.DIMI	8, 	->lb1
-C.B.DIMI	8, 	->lb2
-B.IOT	[n#1, t#1], last	->acc<4KB>
-#  %bb.74:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
-#  %bb.55:
 C.BSTART.STD
-hl.addi	a3, 32768,	->a2
+hl.addi	a3, 28672,	->a0
+#  %bb.55:
+BSTART.TSTORE	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	m#1, last
 #  %bb.56:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
+C.BSTART.STD
+hl.addi	a3, 32768,	->a0
+#  %bb.57:
+BSTART.TSTORE	INT32
+B.DIM	a5, 0, ->lb0
+B.DIM	a5, 0, ->lb1
+B.DIM	a5, 0, ->lb2
+B.IOR	[a0,a4],[]
+B.IOT	n#1, last
 #  %bb.2:
 FRET.STK	[ra ~ ra], sp!, 8
-.Lfunc_end1:
-	.size	_ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi, .Lfunc_end1-_ZN3pto4linx9auto_mode26flash_attention_kernel_i32EPKiS3_S3_Pi
+.Lfunc_end0:
+	.size	pto_flash_attention_auto_i32, .Lfunc_end0-pto_flash_attention_auto_i32
                                         #  -- End function
-	.ident	"clang version 23.0.0git (git@github.com:zhoubot/llvm-project.git cfc6dd5711dcb22eac664da55e1a011c1a49b548)"
+	.ident	"clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 487db9698c9c748de9afe33aa160c6a52be961ab)"
 	.section	".note.GNU-stack","",@progbits
 	.addrsig
diff --git a/docs/reference/examples/v0.57/generated/pto_gemm_auto.s b/docs/reference/examples/v0.57/generated/pto_gemm_auto.s
index 1d42290b..6d3ab37a 100644
--- a/docs/reference/examples/v0.57/generated/pto_gemm_auto.s
+++ b/docs/reference/examples/v0.57/generated/pto_gemm_auto.s
@@ -1,422 +1,408 @@
-	.file	"pto_gemm_auto.cpp" # LinxISA v0.57
+	.file	"pto_gemm_auto.cpp"
 	.text
 	.globl	pto_gemm_auto_i32               #  -- Begin function pto_gemm_auto_i32
 	.p2align	1
 	.type	pto_gemm_auto_i32,@function
 pto_gemm_auto_i32:                      #  @pto_gemm_auto_i32
 #  %bb.0:
-FENTRY	[ra ~ ra], sp!, 16
-#  %bb.2:
-BSTART	CALL, _ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi, ra=.LBB0_1
-.LBB0_1:                                #  Label of block must be emitted
-FRET.STK	[ra ~ ra], sp!, 16
-.Lfunc_end0:
-	.size	pto_gemm_auto_i32, .Lfunc_end0-pto_gemm_auto_i32
-                                        #  -- End function
-	.section	.text._ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi,"axG",@progbits,_ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi,comdat
-	.weak	_ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi #  -- Begin function _ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi
-	.p2align	1
-	.type	_ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi,@function
-_ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi: #  @_ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi
-#  %bb.0:
 FENTRY	[ra ~ ra], sp!, 16384
 #  %bb.1:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a0],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.3:
 C.BSTART.STD
-hl.addi	a0, 4096,	->a3
+c.movr	zero,	->a3
+c.movi	8,	->a4
+#  %bb.3:
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.4:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.5:
 C.BSTART.STD
-hl.addi	a0, 8192,	->a3
+hl.addi	a0, 4096,	->a5
+#  %bb.5:
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a5,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.6:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.7:
 C.BSTART.STD
-hl.addi	sp, 8192,	->a3
+hl.addi	a0, 8192,	->a5
+#  %bb.7:
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a5,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.8:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[t#1], last	->t<4KB>
-#  %bb.9:
 C.BSTART.STD
-hl.addi	a0, 12288,	->a3
-#  %bb.10:
-BSTART.TLOAD INT32
+hl.addi	sp, 8192,	->a5
+#  %bb.9:
+BSTART.TSTORE	INT32
 C.B.DIMI	0, 	->lb0
 C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.11:
+B.IOR	[a5],[]
+B.IOT	t#1, last
+#  %bb.10:
 C.BSTART.STD
-hl.addi	sp, 4096,	->a3
+hl.addi	a0, 12288,	->a5
+#  %bb.11:
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a5,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.12:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[t#1], last	->t<4KB>
-#  %bb.13:
 C.BSTART.STD
-hl.addi	a0, 16384,	->a3
-#  %bb.14:
-BSTART.TLOAD INT32
+hl.addi	sp, 4096,	->a5
+#  %bb.13:
+BSTART.TSTORE	INT32
 C.B.DIMI	0, 	->lb0
 C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.15:
+B.IOR	[a5],[]
+B.IOT	t#1, last
+#  %bb.14:
 C.BSTART.STD
-hl.addi	a0, 32768,	->a3
-hl.addi	a0, 28672,	->a4
-hl.addi	a0, 24576,	->a5
-hl.addi	a0, 20480,	->a6
+hl.addi	a0, 16384,	->a5
+#  %bb.15:
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a5,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.16:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a6],[]
-B.IOT	[], last	->t<4KB>
+C.BSTART.STD
+hl.addi	a0, 32768,	->a5
+hl.addi	a0, 28672,	->a6
+hl.addi	a0, 24576,	->a7
+hl.addi	a0, 20480,	->a0
 #  %bb.17:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a5],[]
-B.IOT	[], last	->t<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.18:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a4],[]
-B.IOT	[], last	->t<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a7,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.19:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a6,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.20:
-C.BSTART.STD
-hl.addi	a1, 28672,	->a3
-hl.addi	a1, 24576,	->a4
-hl.addi	a1, 20480,	->a5
-hl.addi	a1, 16384,	->a6
-hl.addi	a1, 12288,	->a7
-hl.addi	a1, 8192,	->x0
-hl.addi	a1, 4096,	->x1
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a5,a3],[]
+B.IOT	last, ->u<4KB>
 #  %bb.21:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a1],[]
-B.IOT	[], last	->u<4KB>
+C.BSTART.STD
+hl.addi	a1, 28672,	->a0
+hl.addi	a1, 24576,	->a5
+hl.addi	a1, 20480,	->a6
+hl.addi	a1, 16384,	->a7
+hl.addi	a1, 12288,	->x0
+hl.addi	a1, 8192,	->x1
+hl.addi	a1, 4096,	->x2
 #  %bb.22:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[x1],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a1,a3],[]
+B.IOT	last, ->u<4KB>
 #  %bb.23:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[x0],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[x2,a3],[]
+B.IOT	last, ->u<4KB>
 #  %bb.24:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a7],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[x1,a3],[]
+B.IOT	last, ->u<4KB>
 #  %bb.25:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a6],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[x0,a3],[]
+B.IOT	last, ->u<4KB>
 #  %bb.26:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a5],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a7,a3],[]
+B.IOT	last, ->u<4KB>
 #  %bb.27:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a4],[]
-B.IOT	[], last	->u<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a6,a3],[]
+B.IOT	last, ->u<4KB>
 #  %bb.28:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[], last	->t<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a5,a3],[]
+B.IOT	last, ->u<4KB>
 #  %bb.29:
-BSTART.CUBE	MAMULB, INT32
-C.B.DIMI	8, 	->lb0
-C.B.DIMI	8, 	->lb1
-C.B.DIMI	8, 	->lb2
-B.IOT	[t#3, u#2], last	->acc<4KB>
-#  %bb.65:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.30:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#2, u#3], last	->acc<4KB>
+B.IOT	t#7.reuse, u#7.reuse, last
 #  %bb.66:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.31:
-C.BSTART.STD
-hl.addi	sp, 8192,	->a3
-#  %bb.32:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.33:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#4, u#4], last	->acc<4KB>
+B.IOT	t#6.reuse, u#6.reuse, last
 #  %bb.67:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
-#  %bb.34:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
+#  %bb.32:
 C.BSTART.STD
-hl.addi	sp, 4096,	->a3
-#  %bb.35:
-BSTART.TLOAD INT32
+hl.addi	sp, 8192,	->a0
+#  %bb.33:
+BSTART.TLOAD	INT32
 C.B.DIMI	0, 	->lb0
 C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[], last	->t<4KB>
-#  %bb.36:
-BSTART.CUBE	MAMULB, INT32
+B.IOR	[a0],[]
+B.IOT	last, ->t<4KB>
+#  %bb.34:
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#4, u#5], last	->acc<4KB>
+B.IOT	t#1, u#5.reuse, last
 #  %bb.68:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
+#  %bb.35:
+C.BSTART.STD
+hl.addi	sp, 4096,	->a0
+#  %bb.36:
+BSTART.TLOAD	INT32
+C.B.DIMI	0, 	->lb0
+C.B.DIMI	0, 	->lb1
+B.IOR	[a0],[]
+B.IOT	last, ->t<4KB>
 #  %bb.37:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#5, u#6], last	->acc<4KB>
+B.IOT	t#1, u#4, last
 #  %bb.69:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.38:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#6, u#7], last	->acc<4KB>
+B.IOT	t#5, u#3, last
 #  %bb.70:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.39:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#7, u#8], last	->acc<4KB>
+B.IOT	t#4, u#2, last
 #  %bb.71:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.40:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#8, u#2], last	->acc<4KB>
+B.IOT	t#3, u#1, last
 #  %bb.72:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.41:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[u#1, u#3], last	->acc<4KB>
+B.IOT	t#2, u#3, last
 #  %bb.73:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->n<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.42:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#3, u#4], last	->acc<4KB>
+B.IOT	u#3, u#2, last
 #  %bb.74:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->n<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->n<4KB>
 #  %bb.43:
-BSTART.CUBE	MAMULB, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#2, t#1], last	->acc<4KB>
+B.IOT	t#3, u#1, last
 #  %bb.75:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->n<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->n<4KB>
 #  %bb.44:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
+BSTART.TMATMUL	INT32
+C.B.DIMI	8, 	->lb0
+C.B.DIMI	8, 	->lb1
+C.B.DIMI	8, 	->lb2
+B.IOT	t#2, t#1, last
+#  %bb.76:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->n<4KB>
 #  %bb.45:
-C.BSTART.STD
-hl.addi	a2, 4096,	->a3
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a2,a3],[]
+B.IOT	m#8, last
 #  %bb.46:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[m#2], last	->t<4KB>
-#  %bb.47:
 C.BSTART.STD
-hl.addi	a2, 8192,	->a3
+hl.addi	a2, 4096,	->a0
+#  %bb.47:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	m#7, last
 #  %bb.48:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[m#3], last	->t<4KB>
-#  %bb.49:
 C.BSTART.STD
-hl.addi	a2, 12288,	->a3
+hl.addi	a2, 8192,	->a0
+#  %bb.49:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	m#6, last
 #  %bb.50:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[m#4], last	->t<4KB>
-#  %bb.51:
 C.BSTART.STD
-hl.addi	a2, 16384,	->a3
+hl.addi	a2, 12288,	->a0
+#  %bb.51:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	m#5, last
 #  %bb.52:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[m#5], last	->t<4KB>
-#  %bb.53:
 C.BSTART.STD
-hl.addi	a2, 20480,	->a3
+hl.addi	a2, 16384,	->a0
+#  %bb.53:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	m#4, last
 #  %bb.54:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[m#6], last	->t<4KB>
-#  %bb.55:
 C.BSTART.STD
-hl.addi	a2, 24576,	->a3
+hl.addi	a2, 20480,	->a0
+#  %bb.55:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	m#3, last
 #  %bb.56:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[m#7], last	->t<4KB>
-#  %bb.57:
 C.BSTART.STD
-hl.addi	a2, 28672,	->a3
+hl.addi	a2, 24576,	->a0
+#  %bb.57:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	m#2, last
 #  %bb.58:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[m#8], last	->t<4KB>
-#  %bb.59:
 C.BSTART.STD
-hl.addi	a2, 32768,	->a3
+hl.addi	a2, 28672,	->a0
+#  %bb.59:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	m#1, last
 #  %bb.60:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[n#1], last	->t<4KB>
-#  %bb.61:
 C.BSTART.STD
-hl.addi	a2, 36864,	->a3
+hl.addi	a2, 32768,	->a0
+#  %bb.61:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	n#3, last
 #  %bb.62:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a3],[]
-B.IOT	[n#2], last	->t<4KB>
-#  %bb.63:
 C.BSTART.STD
-hl.addi	a2, 40960,	->a2
+hl.addi	a2, 36864,	->a0
+#  %bb.63:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	n#2, last
 #  %bb.64:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[n#3], last	->t<4KB>
+C.BSTART.STD
+hl.addi	a2, 40960,	->a0
+#  %bb.65:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	n#1, last
 #  %bb.2:
 FRET.STK	[ra ~ ra], sp!, 16384
-.Lfunc_end1:
-	.size	_ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi, .Lfunc_end1-_ZN3pto4linx9auto_mode15gemm_kernel_i32EPKiS3_Pi
+.Lfunc_end0:
+	.size	pto_gemm_auto_i32, .Lfunc_end0-pto_gemm_auto_i32
                                         #  -- End function
-	.ident	"clang version 23.0.0git (git@github.com:zhoubot/llvm-project.git cfc6dd5711dcb22eac664da55e1a011c1a49b548)"
+	.ident	"clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 487db9698c9c748de9afe33aa160c6a52be961ab)"
 	.section	".note.GNU-stack","",@progbits
 	.addrsig
diff --git a/docs/reference/examples/v0.57/generated/pto_tload_store.s b/docs/reference/examples/v0.57/generated/pto_tload_store.s
index 0974e1bd..5561b268 100644
--- a/docs/reference/examples/v0.57/generated/pto_tload_store.s
+++ b/docs/reference/examples/v0.57/generated/pto_tload_store.s
@@ -1,4 +1,4 @@
-	.file	"pto_tload_store.cpp" # LinxISA v0.57
+	.file	"pto_tload_store.cpp"
 	.text
 	.globl	pto_tload_store_i32             #  -- Begin function pto_tload_store_i32
 	.p2align	1
@@ -7,24 +7,28 @@ pto_tload_store_i32:                    #  @pto_tload_store_i32
 #  %bb.0:
 FENTRY	[ra ~ ra], sp!, 8
 #  %bb.1:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a0],[]
-B.IOT	[], last	->t<4KB>
+C.BSTART.STD
+c.movr	zero,	->a2
+addi	zero, 32,	->a3
 #  %bb.3:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a1],[]
-B.IOT	[t#1], last	->t<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a3, 0, ->lb0
+B.DIM	a3, 0, ->lb1
+B.DIM	a3, 0, ->lb2
+B.IOR	[a0,a2],[]
+B.IOT	last, ->t<4KB>
+#  %bb.4:
+BSTART.TSTORE	INT32
+B.DIM	a3, 0, ->lb0
+B.DIM	a3, 0, ->lb1
+B.DIM	a3, 0, ->lb2
+B.IOR	[a1,a2],[]
+B.IOT	t#1, last
 #  %bb.2:
 FRET.STK	[ra ~ ra], sp!, 8
 .Lfunc_end0:
 	.size	pto_tload_store_i32, .Lfunc_end0-pto_tload_store_i32
                                         #  -- End function
-	.ident	"clang version 23.0.0git (git@github.com:zhoubot/llvm-project.git cfc6dd5711dcb22eac664da55e1a011c1a49b548)"
+	.ident	"clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 487db9698c9c748de9afe33aa160c6a52be961ab)"
 	.section	".note.GNU-stack","",@progbits
 	.addrsig
diff --git a/docs/reference/examples/v0.57/generated/pto_tmatmul_acc.s b/docs/reference/examples/v0.57/generated/pto_tmatmul_acc.s
index 2bb1cc92..44c5c8ec 100644
--- a/docs/reference/examples/v0.57/generated/pto_tmatmul_acc.s
+++ b/docs/reference/examples/v0.57/generated/pto_tmatmul_acc.s
@@ -1,4 +1,4 @@
-	.file	"pto_tmatmul_acc.cpp" # LinxISA v0.57
+	.file	"pto_tmatmul_acc.cpp"
 	.text
 	.globl	pto_tmatmul_acc_i32_8x8         #  -- Begin function pto_tmatmul_acc_i32_8x8
 	.p2align	1
@@ -7,49 +7,53 @@ pto_tmatmul_acc_i32_8x8:                #  @pto_tmatmul_acc_i32_8x8
 #  %bb.0:
 FENTRY	[ra ~ ra], sp!, 8
 #  %bb.1:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a0],[]
-B.IOT	[], last	->t<4KB>
+C.BSTART.STD
+c.movr	zero,	->a3
+c.movi	8,	->a4
 #  %bb.3:
-BSTART.TLOAD INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a1],[]
-B.IOT	[], last	->t<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a0,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.4:
-BSTART.CUBE	MAMULB, INT32
-C.B.DIMI	8, 	->lb0
-C.B.DIMI	8, 	->lb1
-C.B.DIMI	8, 	->lb2
-B.IOT	[t#1, t#2], last	->acc<4KB>
-#  %bb.7:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.TLOAD	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a1,a3],[]
+B.IOT	last, ->t<4KB>
 #  %bb.5:
-BSTART.CUBE	MAMULB.ACC, INT32
+BSTART.TMATMUL	INT32
 C.B.DIMI	8, 	->lb0
 C.B.DIMI	8, 	->lb1
 C.B.DIMI	8, 	->lb2
-B.IOT	[t#1, t#2], last	->acc<4KB>
+B.IOT	t#2.reuse, t#1.reuse, last
 #  %bb.8:
-BSTART.CUBE	ACCCVT, INT32
-B.IOT	[], last	->m<4KB>
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
 #  %bb.6:
-BSTART.TSTORE INT32
-C.B.DIMI	0, 	->lb0
-C.B.DIMI	0, 	->lb1
-B.ARG	NORM.normal
-B.IOR	[a2],[]
-B.IOT	[m#1], last	->t<4KB>
+BSTART.TMATMUL.ACC	INT32
+C.B.DIMI	8, 	->lb0
+C.B.DIMI	8, 	->lb1
+C.B.DIMI	8, 	->lb2
+B.IOT	t#2, t#1, last
+#  %bb.9:
+BSTART.ACCCVT	INT32
+B.IOT	last, ->m<4KB>
+#  %bb.7:
+BSTART.TSTORE	INT32
+B.DIM	a4, 0, ->lb0
+B.DIM	a4, 0, ->lb1
+B.DIM	a4, 0, ->lb2
+B.IOR	[a2,a3],[]
+B.IOT	m#1, last
 #  %bb.2:
 FRET.STK	[ra ~ ra], sp!, 8
 .Lfunc_end0:
 	.size	pto_tmatmul_acc_i32_8x8, .Lfunc_end0-pto_tmatmul_acc_i32_8x8
                                         #  -- End function
-	.ident	"clang version 23.0.0git (git@github.com:zhoubot/llvm-project.git cfc6dd5711dcb22eac664da55e1a011c1a49b548)"
+	.ident	"clang version 23.0.0git (https://github.com/LinxISA/llvm-project.git 487db9698c9c748de9afe33aa160c6a52be961ab)"
 	.section	".note.GNU-stack","",@progbits
 	.addrsig
diff --git a/docs/reference/examples/v0.57/index.yaml b/docs/reference/examples/v0.57/index.yaml
index 59e20179..6c272d82 100644
--- a/docs/reference/examples/v0.57/index.yaml
+++ b/docs/reference/examples/v0.57/index.yaml
@@ -1,55 +1,27 @@
-profile: v0.57
-commit: 36c45461f934ddb693a21d31fa84a4f7429edefd
-generated_at: 2026-02-14T05:53:06Z
+schema_version: 2
+profile: v0.57.1
+generated_at: 2026-07-31
+toolchain:
+  llvm_commit: 487db9698c9c748de9afe33aa160c6a52be961ab
+  pto_kernel_commit: 7b379eaa855dcba6c5bff5cd0f6136c1767ad440
+  compiler: compiler/llvm/build-linxisa-clang/bin/clang++
+  flags: >-
+    -target linx64-linx-none-elf -O2 -S -ffreestanding -fno-builtin
+    -fno-stack-protector -fno-exceptions -fno-rtti -nostdlib
+    -Iworkloads/pto_kernels/include
 entries:
   - path: docs/reference/examples/v0.57/curated/disasm_example.s
-    source: docs/reference/examples/v0.57/legacy-reference/disasm_example.s
+    source: historical reviewed disassembly fixture
     generation: manual-curation
-  - path: docs/reference/examples/v0.57/curated/linxisa-v0.57-normalized.asm
-    source: docs/reference/examples/v0.57/curated/linxisa-v0.57-normalized.asm
-    generation: manual-curation
-  - path: docs/reference/examples/v0.57/scratch-legacy/simple.s
-    source: avs/scratch/simple.s
-    generation: migrated-allowlist
-  - path: docs/reference/examples/v0.57/scratch-legacy/test_asm_call.S
-    source: avs/scratch/test_asm_call.S
-    generation: migrated-allowlist
-  - path: docs/reference/examples/v0.57/scratch-legacy/test_branch.s
-    source: avs/scratch/test_branch.s
-    generation: migrated-allowlist
-  - path: docs/reference/examples/v0.57/scratch-legacy/test_branch2.s
-    source: avs/scratch/test_branch2.s
-    generation: migrated-allowlist
-  - path: docs/reference/examples/v0.57/scratch-legacy/test_csel.s
-    source: avs/scratch/test_csel.s
-    generation: migrated-allowlist
-  - path: docs/reference/examples/v0.57/scratch-legacy/test_or.s
-    source: avs/scratch/test_or.s
-    generation: migrated-allowlist
-  - path: docs/reference/examples/v0.57/scratch-legacy/test_regs.s
-    source: avs/scratch/test_regs.s
-    generation: migrated-allowlist
-  - path: docs/reference/examples/v0.57/scratch-legacy/test_simple.s
-    source: avs/scratch/test_simple.s
-    generation: migrated-allowlist
-  - path: docs/reference/examples/v0.57/scratch-legacy/test_simple_fixed.s
-    source: avs/scratch/test_simple_fixed.s
-    generation: migrated-allowlist
-  - path: docs/reference/examples/v0.57/generated/flash_attention.s
-    source: workloads/pto_kernels/kernels/attention/flash_attention.cpp
-    generation: RUN_QEMU_TILE=0 bash workloads/pto_kernels/tools/run_pto_to_linx.sh
-  - path: docs/reference/examples/v0.57/generated/flash_attention_masked.s
-    source: workloads/pto_kernels/kernels/attention/flash_attention_masked.cpp
-    generation: RUN_QEMU_TILE=0 bash workloads/pto_kernels/tools/run_pto_to_linx.sh
-  - path: docs/reference/examples/v0.57/generated/gemm.s
-    source: workloads/pto_kernels/kernels/matmul/gemm.cpp
-    generation: RUN_QEMU_TILE=0 bash workloads/pto_kernels/tools/run_pto_to_linx.sh
-  - path: docs/reference/examples/v0.57/generated/mamulb.s
-    source: workloads/pto_kernels/kernels/matmul/mamulb.cpp
-    generation: RUN_QEMU_TILE=0 bash workloads/pto_kernels/tools/run_pto_to_linx.sh
-  - path: docs/reference/examples/v0.57/generated/tload_store.s
-    source: workloads/pto_kernels/kernels/memory/tload_store.cpp
-    generation: RUN_QEMU_TILE=0 bash workloads/pto_kernels/tools/run_pto_to_linx.sh
-  - path: docs/reference/examples/v0.57/generated/tmatmul_acc.s
-    source: workloads/pto_kernels/kernels/matmul/tmatmul_acc.cpp
-    generation: RUN_QEMU_TILE=0 bash workloads/pto_kernels/tools/run_pto_to_linx.sh
+  - path: docs/reference/examples/v0.57/generated/pto_flash_attention_auto.s
+    source: workloads/pto_kernels/tools/examples/pto_flash_attention_auto.cpp
+    generation: compile-with-recorded-toolchain
+  - path: docs/reference/examples/v0.57/generated/pto_gemm_auto.s
+    source: workloads/pto_kernels/tools/examples/pto_gemm_auto.cpp
+    generation: compile-with-recorded-toolchain
+  - path: docs/reference/examples/v0.57/generated/pto_tload_store.s
+    source: workloads/pto_kernels/tools/examples/pto_tload_store.cpp
+    generation: compile-with-recorded-toolchain
+  - path: docs/reference/examples/v0.57/generated/pto_tmatmul_acc.s
+    source: workloads/pto_kernels/tools/examples/pto_tmatmul_acc.cpp
+    generation: compile-with-recorded-toolchain
diff --git a/docs/zh/assets/lang-map.json b/docs/zh/assets/lang-map.json
index 4588fbe2..d3290aa4 100644
--- a/docs/zh/assets/lang-map.json
+++ b/docs/zh/assets/lang-map.json
@@ -382,9 +382,7 @@
   "/isa/header/tileblock/MSCATTER/": "/zh/isa/header/tileblock/MSCATTER/",
   "/isa/header/tileblock/TABS/": "/zh/isa/header/tileblock/TABS/",
   "/isa/header/tileblock/TADD/": "/zh/isa/header/tileblock/TADD/",
-  "/isa/header/tileblock/TADDC/": "/zh/isa/header/tileblock/TADDC/",
   "/isa/header/tileblock/TADDS/": "/zh/isa/header/tileblock/TADDS/",
-  "/isa/header/tileblock/TADDSC/": "/zh/isa/header/tileblock/TADDSC/",
   "/isa/header/tileblock/TAND/": "/zh/isa/header/tileblock/TAND/",
   "/isa/header/tileblock/TANDS/": "/zh/isa/header/tileblock/TANDS/",
   "/isa/header/tileblock/TCMP/": "/zh/isa/header/tileblock/TCMP/",
@@ -406,8 +404,6 @@
   "/isa/header/tileblock/TDIVS/": "/zh/isa/header/tileblock/TDIVS/",
   "/isa/header/tileblock/TEXP/": "/zh/isa/header/tileblock/TEXP/",
   "/isa/header/tileblock/TEXPANDS/": "/zh/isa/header/tileblock/TEXPANDS/",
-  "/isa/header/tileblock/TFMOD/": "/zh/isa/header/tileblock/TFMOD/",
-  "/isa/header/tileblock/TFMODS/": "/zh/isa/header/tileblock/TFMODS/",
   "/isa/header/tileblock/TGATHER/": "/zh/isa/header/tileblock/TGATHER/",
   "/isa/header/tileblock/TGEMV.ACC/": "/zh/isa/header/tileblock/TGEMV.ACC/",
   "/isa/header/tileblock/TGEMV.BIAS/": "/zh/isa/header/tileblock/TGEMV.BIAS/",
@@ -418,7 +414,6 @@
   "/isa/header/tileblock/THISTOGRAM/": "/zh/isa/header/tileblock/THISTOGRAM/",
   "/isa/header/tileblock/TLOAD/": "/zh/isa/header/tileblock/TLOAD/",
   "/isa/header/tileblock/TLOG/": "/zh/isa/header/tileblock/TLOG/",
-  "/isa/header/tileblock/TLRELU/": "/zh/isa/header/tileblock/TLRELU/",
   "/isa/header/tileblock/TMATMUL.ACC/": "/zh/isa/header/tileblock/TMATMUL.ACC/",
   "/isa/header/tileblock/TMATMUL.BIAS/": "/zh/isa/header/tileblock/TMATMUL.BIAS/",
   "/isa/header/tileblock/TMATMUL/": "/zh/isa/header/tileblock/TMATMUL/",
@@ -464,9 +459,7 @@
   "/isa/header/tileblock/TSQRT/": "/zh/isa/header/tileblock/TSQRT/",
   "/isa/header/tileblock/TSTORE/": "/zh/isa/header/tileblock/TSTORE/",
   "/isa/header/tileblock/TSUB/": "/zh/isa/header/tileblock/TSUB/",
-  "/isa/header/tileblock/TSUBC/": "/zh/isa/header/tileblock/TSUBC/",
   "/isa/header/tileblock/TSUBS/": "/zh/isa/header/tileblock/TSUBS/",
-  "/isa/header/tileblock/TSUBSC/": "/zh/isa/header/tileblock/TSUBSC/",
   "/isa/header/tileblock/TTRANS/": "/zh/isa/header/tileblock/TTRANS/",
   "/isa/header/tileblock/TXOR/": "/zh/isa/header/tileblock/TXOR/",
   "/isa/header/tileblock/TXORS/": "/zh/isa/header/tileblock/TXORS/",
@@ -2486,9 +2479,7 @@
   "/zh/isa/header/tileblock/MSCATTER/": "/isa/header/tileblock/MSCATTER/",
   "/zh/isa/header/tileblock/TABS/": "/isa/header/tileblock/TABS/",
   "/zh/isa/header/tileblock/TADD/": "/isa/header/tileblock/TADD/",
-  "/zh/isa/header/tileblock/TADDC/": "/isa/header/tileblock/TADDC/",
   "/zh/isa/header/tileblock/TADDS/": "/isa/header/tileblock/TADDS/",
-  "/zh/isa/header/tileblock/TADDSC/": "/isa/header/tileblock/TADDSC/",
   "/zh/isa/header/tileblock/TAND/": "/isa/header/tileblock/TAND/",
   "/zh/isa/header/tileblock/TANDS/": "/isa/header/tileblock/TANDS/",
   "/zh/isa/header/tileblock/TCMP/": "/isa/header/tileblock/TCMP/",
@@ -2510,8 +2501,6 @@
   "/zh/isa/header/tileblock/TDIVS/": "/isa/header/tileblock/TDIVS/",
   "/zh/isa/header/tileblock/TEXP/": "/isa/header/tileblock/TEXP/",
   "/zh/isa/header/tileblock/TEXPANDS/": "/isa/header/tileblock/TEXPANDS/",
-  "/zh/isa/header/tileblock/TFMOD/": "/isa/header/tileblock/TFMOD/",
-  "/zh/isa/header/tileblock/TFMODS/": "/isa/header/tileblock/TFMODS/",
   "/zh/isa/header/tileblock/TGATHER/": "/isa/header/tileblock/TGATHER/",
   "/zh/isa/header/tileblock/TGEMV.ACC/": "/isa/header/tileblock/TGEMV.ACC/",
   "/zh/isa/header/tileblock/TGEMV.BIAS/": "/isa/header/tileblock/TGEMV.BIAS/",
@@ -2522,7 +2511,6 @@
   "/zh/isa/header/tileblock/THISTOGRAM/": "/isa/header/tileblock/THISTOGRAM/",
   "/zh/isa/header/tileblock/TLOAD/": "/isa/header/tileblock/TLOAD/",
   "/zh/isa/header/tileblock/TLOG/": "/isa/header/tileblock/TLOG/",
-  "/zh/isa/header/tileblock/TLRELU/": "/isa/header/tileblock/TLRELU/",
   "/zh/isa/header/tileblock/TMATMUL.ACC/": "/isa/header/tileblock/TMATMUL.ACC/",
   "/zh/isa/header/tileblock/TMATMUL.BIAS/": "/isa/header/tileblock/TMATMUL.BIAS/",
   "/zh/isa/header/tileblock/TMATMUL/": "/isa/header/tileblock/TMATMUL/",
@@ -2568,9 +2556,7 @@
   "/zh/isa/header/tileblock/TSQRT/": "/isa/header/tileblock/TSQRT/",
   "/zh/isa/header/tileblock/TSTORE/": "/isa/header/tileblock/TSTORE/",
   "/zh/isa/header/tileblock/TSUB/": "/isa/header/tileblock/TSUB/",
-  "/zh/isa/header/tileblock/TSUBC/": "/isa/header/tileblock/TSUBC/",
   "/zh/isa/header/tileblock/TSUBS/": "/isa/header/tileblock/TSUBS/",
-  "/zh/isa/header/tileblock/TSUBSC/": "/isa/header/tileblock/TSUBSC/",
   "/zh/isa/header/tileblock/TTRANS/": "/isa/header/tileblock/TTRANS/",
   "/zh/isa/header/tileblock/TXOR/": "/isa/header/tileblock/TXOR/",
   "/zh/isa/header/tileblock/TXORS/": "/isa/header/tileblock/TXORS/",
diff --git a/docs/zh/isa/arch/prgorder.md b/docs/zh/isa/arch/prgorder.md
index e04796a4..d24430e9 100644
--- a/docs/zh/isa/arch/prgorder.md
+++ b/docs/zh/isa/arch/prgorder.md
@@ -40,12 +40,16 @@
 **块头（出现顺序，就是 L1-IPO）：**
 
 ```asm
-BSTART.TEPL TMATMUL, FP16      ; 配置：做 FP16 的 A×B
+BSTART.TMATMUL FP16           ; 配置：做 FP16 的 A×B
 B.DIM     rM, 128, ->M        ; M=128
 B.DIM     rN, 128, ->N        ; N=128
 B.DIM     rK, 256, ->K        ; K=256
-B.IOT     [TA, TB], group=0, ->ACC<64KB>   ; 绑定 A/B 到 ACC
-B.ARG     CD2RD                ; 结果默认行主序，无额外变换
+B.DATR    normal, FP16, ZERO, cmode0, rmode0
+B.IOT     TA, TB, last        ; ACC 由 CUBE opcode 隐式选择
+
+BSTART.ACCCVT FP16            ; 将隐式 ACC 发布到普通 Tile
+B.DATR    normal, FP16, ZERO, cmode0, rmode0
+B.IOT     last, ->t<32KB>
 ```
 
 **展开后的块身步骤（顺序替换）：**
@@ -57,7 +61,7 @@ B.ARG     CD2RD                ; 结果默认行主序，无额外变换
 **最终 PO（语义顺序）：**
 
 ```
-BSTART.TEPL → B.DIM → B.DIM → B.DIM → B.IOT → B.ARG →
+BSTART.TMATMUL → B.DIM → B.DIM → B.DIM → B.DATR → B.IOT →
 加载分片 → 乘累加到 ACC → ACC 写回 Tile
 ```
 
@@ -68,12 +72,16 @@ BSTART.TEPL → B.DIM → B.DIM → B.DIM → B.IOT → B.ARG →
 **块头：**
 
 ```asm
-BSTART.TEPL TMATMUL, FP16
+BSTART.TMATMUL FP16
 B.DIM     zero, 64,  ->M
 B.DIM     zero, 64,  ->N
 B.DIM     zero, 256, ->K
-B.IOT     [TA, TB], group=0, ->ACC<64KB>
-B.ARG     ZZ2RD                  ; 指定 TCVT 的布局变换（例）
+B.DATR    normal, FP16, ZERO, cmode0, rmode0
+B.IOT     TA, TB, last
+
+BSTART.ACCCVT FP16
+B.DATR    zn, FP16, ZERO, cmode0, rmode0  ; 指定转换布局（例）
+B.IOT     last, ->t<16KB>
 ```
 
 **展开后的块身（顺序替换）：**
@@ -98,14 +106,17 @@ B.ARG     ZZ2RD                  ; 指定 TCVT 的布局变换（例）
 **块头：**
 
 ```asm
-BSTART.TEPL TMATMULMX, INT8
+BSTART.TMATMULMX INT8
 B.DIM     zero, 128, ->M
 B.DIM     zero, 128, ->N
 B.DIM     zero, 256, ->K
-B.IOT     [TA, TSA], group=0, ->ACC<64KB>  ; A 与 ScaleA
-B.IOT     [TB, TSB], group=1               ; B 与 ScaleB
-; 可选：B.IOT [TC], group=2               ; 若做 +C
-B.ARG     CD2RD
+B.DATR    normal, INT8, ZERO, cmode0, rmode0
+B.IOT     TA, TSA                           ; A 与 ScaleA
+B.IOT     TB, TSB, last                     ; B 与 ScaleB；ACC 隐式选择
+
+BSTART.ACCCVT INT8
+B.DATR    normal, INT8, ZERO, cmode0, rmode0
+B.IOT     last, ->t<32KB>
 ```
 
 **块身（顺序替换）：**
diff --git a/docs/zh/isa/blockIntro/cube_block/header.md b/docs/zh/isa/blockIntro/cube_block/header.md
index 37f922ac..42bb6773 100644
--- a/docs/zh/isa/blockIntro/cube_block/header.md
+++ b/docs/zh/isa/blockIntro/cube_block/header.md
@@ -43,8 +43,9 @@ TileOp <LB0:arg0, LB1:arg1, LB2:arg2, DataType>, SrcTile0<.reuse>, ..., SrcTile7
 - ...
 - [B.IOT](../../header/B.IOT.md) SrcTile6<.reuse>, SrcTile7<.reuse>, last, ->DstTile3< TileSize3>
 
-其中，CUBE 命名块头共享 BSTART.CUBE 编码族。活动汇编对下表中的命名函数使用
-命名块头；泛化 `BSTART.CUBE` 只保留给未命名函数编码，不能覆盖已命名函数。
+其中，CUBE 命名块头共享 BSTART.CUBE 编码族。只有表中的 13 个命名函数
+合法；未分配的 Function 均为非法指令，不存在可执行的泛化 `BSTART.CUBE`
+汇编形式。
 
 其中，BSTART.CUBE 编码族格式如下：
 
diff --git a/docs/zh/isa/blockIntro/cube_block/intro.md b/docs/zh/isa/blockIntro/cube_block/intro.md
index c87c0910..37ee2aa6 100644
--- a/docs/zh/isa/blockIntro/cube_block/intro.md
+++ b/docs/zh/isa/blockIntro/cube_block/intro.md
@@ -36,12 +36,25 @@
 
 示例：
 ```asm
-    TMATMUL <M:64, N:32, K:64, FP32> T#4, T#3, ->ACC<16KB>
-    TMATMUL.ACC <M:64, N:32, K:64, FP32> T#1, T#2, ACC, ->ACC<8KB>
-    ACCCVT NORM <Row:64, Col:64, FP32> ACC, ->T<16KB>
+    BSTART.TMATMUL FP32
+    C.B.DIMI 64, ->lb0
+    C.B.DIMI 32, ->lb1
+    C.B.DIMI 64, ->lb2
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
+    B.IOT t#4, t#3, last
+
+    BSTART.TMATMUL.ACC FP32
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
+    B.IOT t#1, t#2, last
+
+    BSTART.ACCCVT FP32
+    B.DATR normal, FP32, ZERO, cmode0, rmode0
+    B.IOT last, ->t<16KB>
 ```
 
-上述示例中，`TMATMUL`指令写到ACC寄存器，然后被后序的`TMATMUL.ACC`指令读取并用于乘累加运算，最后通过`ACCCVT`指令将结果搬运至T类型Tile寄存器。
+上述示例中，CUBE opcode 隐式选择 ACC，`B.IOT` 永不编码 ACC。
+`TMATMUL` 初始化 ACC，`TMATMUL.ACC` 读取并更新 ACC，最后由 `ACCCVT`
+把结果发布到普通 T 类型 Tile。
 
 ## 输入要求
 
diff --git a/docs/zh/isa/blockIntro/tepl_block/header.md b/docs/zh/isa/blockIntro/tepl_block/header.md
index e7d37f02..8a196abe 100644
--- a/docs/zh/isa/blockIntro/tepl_block/header.md
+++ b/docs/zh/isa/blockIntro/tepl_block/header.md
@@ -56,7 +56,7 @@ TileOp <LB0:arg0, LB1:arg1, LB2:arg2, DataType>, SrcTile0<.reuse>, ..., SrcTile7
 | 0    | 2        | [TMUL](../../header/tileblock/TMUL.md)   | 两个Tile的逐元素乘法 |
 | 0    | 3        | [TDIV](../../header/tileblock/TDIV.md)   | 两个Tile的逐元素除法 |
 | 0    | 4        | [TREM](../../header/tileblock/TREM.md)   | 两个Tile的逐元素余数，余数符号与除数相同 |
-| 0    | 5        | [TFMOD](../../header/tileblock/TFMOD.md)  | 两个Tile的逐元素余数，余数符号与被除数相同 |
+| 0    | 5        | - | 保留/非法 |
 | 0    | 6        | [TAND](../../header/tileblock/TAND.md)   | 两个Tile的逐元素按位与 |
 | 0    | 7        | [TOR](../../header/tileblock/TOR.md)     | 两个Tile的逐元素按位或 |
 | 0    | 8        | [TXOR](../../header/tileblock/TXOR.md)   | 两个Tile的逐元素按位异或 |
@@ -75,8 +75,7 @@ TileOp <LB0:arg0, LB1:arg1, LB2:arg2, DataType>, SrcTile0<.reuse>, ..., SrcTile7
 | 0    | 21       | [TSQRT](../../header/tileblock/TSQRT.md)  | 逐元素平方根 |
 | 0    | 22       | [TRSQRT](../../header/tileblock/TRSQRT.md) | 逐元素倒数平方根 |
 | 0    | 23       | [TRELU](../../header/tileblock/TRELU.md)  | Tile的逐元素ReLU |
-| 0    | 24       | [TADDC](../../header/tileblock/TADDC.md)  | 三元逐元素加法：dst = src0 + src1 + src2 |
-| 0    | 25       | [TSUBC](../../header/tileblock/TSUBC.md)  | 三元逐元素减法：dst = src0 - src1 + src2 |
+| 0    | 24-25    | - | 保留/非法 |
 | 0    | 26       | [TSEL](../../header/tileblock/TSEL.md)   | 使用掩码Tile在两个Tile之间进行选择（逐元素选择） |
 | 0    | 27       | [TCVT](../../header/tileblock/TCVT.md)   | Tile的逐元素数据格式转换。 |
 | 0    | 28-31    | -      | 保留 |
@@ -90,7 +89,7 @@ TileOp <LB0:arg0, LB1:arg1, LB2:arg2, DataType>, SrcTile0<.reuse>, ..., SrcTile7
 | 1    | 2        | [TMULS](../../header/tileblock/TMULS.md)  | Tile与标量的逐元素乘法 |
 | 1    | 3        | [TDIVS](../../header/tileblock/TDIVS.md)  | 与标量的逐元素除法（Tile/标量或标量/Tile） |
 | 1    | 4        | [TREMS](../../header/tileblock/TREMS.md)  | 与标量的逐元素余数：remainder(src, scalar) |
-| 1    | 5        | [TFMODS](../../header/tileblock/TFMODS.md) | 与标量的逐元素余数：fmod(src, scalar) |
+| 1    | 5        | - | 保留/非法 |
 | 1    | 6        | [TANDS](../../header/tileblock/TANDS.md)  | Tile与标量的逐元素按位与 |
 | 1    | 7        | [TORS](../../header/tileblock/TORS.md)    | Tile与标量的逐元素按位或 |
 | 1    | 8        | [TXORS](../../header/tileblock/TXORS.md)  | Tile与标量的逐元素按位异或 |
@@ -99,10 +98,9 @@ TileOp <LB0:arg0, LB1:arg1, LB2:arg2, DataType>, SrcTile0<.reuse>, ..., SrcTile7
 | 1    | 11       | [TMAXS](../../header/tileblock/TMAXS.md)  | Tile与标量的逐元素最大值：max(src, scalar) |
 | 1    | 12       | [TMINS](../../header/tileblock/TMINS.md)  | Tile与标量的逐元素最小值 |
 | 1    | 13       | [TCMPS](../../header/tileblock/TCMPS.md)  | 将Tile与标量逐元素比较 |
-| 1    | 14       | [TLRELU](../../header/tileblock/TLRELU.md) | 带标量斜率的LeakyReLU |
+| 1    | 14       | - | 保留/非法 |
 | 1    | 15-23    | -      | 预留编码 |
-| 1    | 24       | [TADDSC](../../header/tileblock/TADDSC.md) | 带标量融合逐元素加法运算：dst = src0 + scalar + src1 |
-| 1    | 25       | [TSUBSC](../../header/tileblock/TSUBSC.md) | 带标量融合逐元素减法运算：dst = src0 - scalar + src1 |
+| 1    | 24-25    | - | 保留/非法 |
 | 1    | 26       | [SELS](../../header/tileblock/TSELS.md)  | 使用掩码Tile在源Tile和标量之间进行选择（源Tile逐元素选择） |
 | 1    | 27       | [TEXPANDS](../../header/tileblock/TEXPANDS.md) | 将标量广播到目标Tile中 |
 | 1    | 28-31    | -      | 预留编码 |
diff --git a/docs/zh/isa/header/tileblock/ACCCVT.md b/docs/zh/isa/header/tileblock/ACCCVT.md
index 5ec22fe1..0942ebdf 100644
--- a/docs/zh/isa/header/tileblock/ACCCVT.md
+++ b/docs/zh/isa/header/tileblock/ACCCVT.md
@@ -15,7 +15,7 @@
 ## 汇编语法
 
 ```asm
-ACCCVT Layout.{canon, normal}, <LB0:Row, LB1:Col, SrcType, DstType>, ACC, [RegSrc], DepSrc0, DepSrc1, DepSrc2,
+ACCCVT Layout.{canon, normal}, <LB0:Row, LB1:Col, SrcType, DstType>, [RegSrc], DepSrc0, DepSrc1, DepSrc2,
                                ->DstTile0<TileSize0>, DstTile1<TileSize1>, DepDst
 ```
 
@@ -28,14 +28,14 @@ ACCCVT Layout.{canon, normal}, <LB0:Row, LB1:Col, SrcType, DstType>, ACC, [RegSr
 - **Row、Col**：表示输入矩阵的尺寸，可分别通过`全局寄存器`、`立即数`或`全局寄存器加立即数`的形式设置。
     - **Row**：表示输入矩阵的行数。
     - **Col**：表示输入矩阵的列数。
-- **ACC**：指示输入ACC类型[Tile 寄存器](../../register/common/tilereg.md)。
+- **ACC**：由 `BSTART.ACCCVT` opcode 隐式选择，不在 `B.IOT` 中编码。
 - **RegSrc**：指示输入的[全局寄存器](../../register/common/ggpr.md)，用于存储scale值。该参数数据类型必须与ACC Tile的数据类型保持一致，否则指令不保证计算结果的正确性。如果不执行scale操作则可缺省。
 - **DstTile0**：指示第一个输出的[Tile 寄存器](../../register/common/tilereg.md)类型，可选T, U, M, N。用于存储随路运算主结果。
 - **DstTile1**：指示第二个输出的[Tile 寄存器](../../register/common/tilereg.md)类型，可选T, U, M, N。用于存储RowMax结果，如果不执行RowMax则缺省。
 - **TileSize0**：指示第一个输出[Tile 寄存器](../../register/common/tilereg.md)的空间大小，可以通过立即数或者全局寄存器传参。
 - **TileSize1**：指示第二个输出[Tile 寄存器](../../register/common/tilereg.md)的空间大小，可以通过立即数或者全局寄存器传参。跟随DstTile1缺省。
 - **DepSrc0 / DepSrc1 / DepSrc2**：表示本块指令最多显式记录 3 个前序 `D` 依赖槽位。
-- **DepDst**：表示本块指令对后序引用该标识的块指令的屏障。
+- **DepDst**：仅表示调度依赖元数据，不构成内存屏障或 fence。
 
 输入ACC寄存器中元素的数据格式（SrcType）可以是以下几种：
 
@@ -69,7 +69,7 @@ ACCCVT Layout.{canon, normal}, <LB0:Row, LB1:Col, SrcType, DstType>, ACC, [RegSr
 - [B.DATR](../../header/B.DATR.md) Layout.{canon, normal}, DstType
 - [B.DIM](../../header/B.DIM.md) reg, imm, ->LB0
 - [B.DIM](../../header/B.DIM.md) reg, imm, ->LB1
-- [B.IOT](../../header/B.IOT.md) , ->DstTile0< TileSize0>
+- [B.IOT](../../header/B.IOT.md) last, ->DstTile0< TileSize0>
 - [B.IOT](../../header/B.IOT.md) last, ->DstTile1< TileSize1>
 - [B.IOR](../../header/B.IOR.md) RegSrc
 
diff --git a/docs/zh/isa/header/tileblock/TADDC.md b/docs/zh/isa/header/tileblock/TADDC.md
deleted file mode 100644
index 81b9a60e..00000000
--- a/docs/zh/isa/header/tileblock/TADDC.md
+++ /dev/null
@@ -1,111 +0,0 @@
-# TADDC
-
-## 说明
-
-**数据块带进位加法(Tile Add with Carry)**
-
-`TADDC` 将三个输入 Tile 逐元素相加，结果写入输出 Tile 中。 
-
-实现伪代码示意如下：
-```pseudocode
-// 逐元素加法操作
-for r in 0..(Rv-1):           // 遍历所有行
-  for c in 0..(Cv-1):       // 遍历所有列
-    dst[r, c] = src0[r, c] + src1[r, c] + src2[r, c]  // 对应位置元素相加
-```
-
-实现示意图如下：
-
-![TADDC](../../../figs/isa/tileop/TADDC.png){ width="900" }
-
----
-
-## 汇编语法
-
-```asm
-    TADDC <LB0:ValidCol, LB1:ValidRow, LB2:Col, DataType, PadValue>, SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, ->DstTile<Size>
-```
-
-## 汇编符号
-
-- **ValidCol**：输入Tile中有效元素的列数。该参数可以通过以下3种形式配置到LB0寄存器中：
-    - **reg**：通过全局寄存器[GGPR](../../register/common/ggpr.md)设置。
-    - **imm**: 使用立即数设置。
-    - **reg+imm**：通过全局寄存器加立即数的形式设置。
-- **ValidRow**：输入Tile中有效元素的行数（可缺省，默认值：`1`）。该参数配置到LB1寄存器中，配置方式同上。
-- **Col**：输入Tile的总列数（可缺省，默认值：等于`ValidCol`）。该参数配置到LB2寄存器中，配置方式同上。
-- **Row**：输入Tile的总行数，通过公式计算：`Row = SrcTileSize / (Col × sizeof(DataType))`。
-- **DataType**：输入Tile元素的数据格式，支持类型见下表。
-- **PadValue**：输出Tile无效区域的填充值，可选：`Null`、`Zero`、`Max`、`Min`（可缺省，默认值：`Null`）。
-- **SrcTile0/1/2**：输入Tile寄存器，支持`T`/`U`/`M`/`N`队列输入（参见：[Tile寄存器](../../register/common/tilereg.md)）。
-- **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
-- **DstTile**：输出Tile寄存器，支持`T`/`U`/`M`/`N`队列输出。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
-
-本指令支持数据类型（DataType）如下表所示：
-
-| 数据位宽 | 类型列表 |
-|----------|------------|
-| b64 | S64, U64, FP64 |
-| b32 | S32, U32, FP32, TF32, HF32 |
-| b16 | S16, U16, FP16, BF16 |
-| b8  | S8,  U8,  FP8(E4M3, E5M2) |
-
----
-
-## 编码格式
-
-该TileOp模版块编码为以下指令：
-
-- [BSTART.TEPL](../../blockIntro/tepl_block/header.md) `TADDC, DataType`
-- [B.DATR](../../header/B.DATR.md) `PadValue`
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`    （注：*ValidCol*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*ValidRow*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*Col*）
-- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`
-- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, last, ->DstTile<Size>`
-
-## 约束条件
-
-- 多个输入Tile的以下参数必须一致，否则硬件不保证结果正确性：
-    - `src0::Row == src1::Row == src2::Row`
-    - `src0::Col == src1::Col == src2::Col`
-    - `src0::ValidRow == src1::ValidRow == src2::ValidRow`
-    - `src0::ValidCol == src1::ValidCol == src2::ValidCol`
-    - `src0::DataType == src1::DataType == src2::DataType`
-- **尺寸范围**：
-    - 输入Tile的行列/有效行列等参数大小均必须小于等于16bit。
-    - 有效边界：`ValidRow <= Row`, `ValidCol <= Col`
-- **数据布局**：必须是行主序（RowMajor）。
-
----
-
-## 汇编示例
-
-```asm
-    TADDC <LB0:40, LB1:32, LB2:48, s16>, T#1, T#2.reuse, U#4, ->T<4KB>
-```
-
-1. **操作内容**  
-    - 输入：`T#1` 、`T#2` 和 `U#4` Tile寄存器
-    - 输出：结果存入新的 `T` 队列Tile寄存器
-2. **数据处理范围**  
-    - 只处理前 `40列`（由 `LB0:40` 指定）  
-    - 有效行数为 `32`（`LB1:32`）  
-    - 总列数为：`48`（`LB2:48`）
-3. **数据格式**  
-    - 使用 `16位整数`（`s16`）格式处理数据  
-    - 每个元素占2字节（影响内存布局计算）
-4. **寄存器管理**  
-    - 输入寄存器 `T#2` 添加了 `.reuse` 标记，表示**执行后保留该寄存器**  
-    - 输入寄存器 `T#1` 和 `U#4` **执行后自动释放**（无reuse标记）  
-    - 输出寄存器分配 `4KB` 空间（足够存储计算结果）
-5. **特殊处理**  
-    - 区域中**超出有效范围的部分**不初始化（`PadValue` 缺省）  
-    - 输出寄存器由硬件自动分配（`->T` 未指定具体寄存器号）
-
----
-
-## 备注
-
-此指令是TileOp模版块，软件只定义块头。
diff --git a/docs/zh/isa/header/tileblock/TADDSC.md b/docs/zh/isa/header/tileblock/TADDSC.md
deleted file mode 100644
index 1a6e1e43..00000000
--- a/docs/zh/isa/header/tileblock/TADDSC.md
+++ /dev/null
@@ -1,115 +0,0 @@
-# TADDSC
-
-## 说明
-
-**数据块与标量带进位加法(Tile Add Scalar with Carry)**
-
-`TADDSC` 将两个输入 Tile 逐元素与标量相加，结果写入输出 Tile 中。 
-
-实现伪代码示意如下：
-```pseudocode
-// 逐元素带进位加法操作
-for r in 0..(Rv-1):           // 遍历所有行
-  for c in 0..(Cv-1):       // 遍历所有列
-    dst[r, c] = src0[r, c] + scalar + src1[r, c]  // 对应位置元素与标量相加
-```
-
-实现示意图如下：
-
-![TADDSC](../../../figs/isa/tileop/TADDSC.png){ width="900" }
-
----
-
-## 汇编语法
-
-```asm
-    TADDSC <LB0:ValidCol, LB1:ValidRow, LB2:Col, DataType, PadValue>, SrcTile0<.reuse>, [RegSrc], SrcTile1<.reuse>, ->DstTile<Size>
-```
-
-## 汇编符号
-
-- **ValidCol**：输入Tile中有效元素的列数。该参数可以通过以下3种形式配置到LB0寄存器中：
-    - **reg**：通过全局寄存器[GGPR](../../register/common/ggpr.md)设置。
-    - **imm**: 使用立即数设置。
-    - **reg+imm**：通过全局寄存器加立即数的形式设置。
-- **ValidRow**：输入Tile中有效元素的行数（可缺省，默认值：`1`）。该参数配置到LB1寄存器中，配置方式同上。
-- **Col**：输入Tile的总列数（可缺省，默认值：等于`ValidCol`）。该参数配置到LB2寄存器中，配置方式同上。
-- **Row**：输入Tile的总行数，通过公式计算：`Row = SrcTileSize / (Col × sizeof(DataType))`。
-- **DataType**：输入Tile元素的数据格式，支持类型见下表。
-- **PadValue**：输出Tile无效区域的填充值，可选：`Null`、`Zero`、`Max`、`Min`（可缺省，默认值：`Null`）。
-- **SrcTile0/1**：输入Tile寄存器，支持`T`/`U`/`M`/`N`队列输入（参见：[Tile寄存器](../../register/common/tilereg.md)）。
-- **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
-- **RegSrc**：输入全局寄存器，用于存储标量值。（参见：[全局寄存器](../../register/common/ggpr.md)）
-- **DstTile**：输出Tile寄存器，支持`T`/`U`/`M`/`N`队列输出。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
-
-本指令支持数据类型（DataType）如下表所示：
-
-| 数据位宽 | 类型列表 |
-|----------|------------|
-| b64 | S64, U64, FP64 |
-| b32 | S32, U32, FP32, TF32, HF32 |
-| b16 | S16, U16, FP16, BF16 |
-
----
-
-## 编码格式
-
-该TileOp模版块编码为以下指令：
-
-- [BSTART.TEPL](../../blockIntro/tepl_block/header.md) `TADDSC, DataType`
-- [B.DATR](../../header/B.DATR.md) `PadValue`
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`    （注：*ValidCol*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*ValidRow*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*Col*）
-- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last, ->DstTile<Size>`
-- [B.IOR](../../header/B.IOR.md) `RegSrc`
-
-## 约束条件
-
-- **静态参数**：
-    - `SrcTile0::Row == SrcTile1::Row == DstTile::Row`
-    - `SrcTile0::Col == SrcTile1::Col == DstTile::Col`
-- **动态参数**：
-    - `SrcTile0::ValidRow == SrcTile1::ValidRow == DstTile::ValidRow`
-    - `SrcTile0::ValidCol == SrcTile1::ValidCol == DstTile::ValidCol`
-- **有效边界**：
-    - `ValidRow <= Row`, `ValidCol <= Col`
-- **数据类型**：
-    - `SrcTile0::DataType == SrcTile1::DataType == DstTile::DataType`
-- **存储布局**：
-    - 必须是**行主序（RowMajor）**。
-- **尺寸范围**：
-    - Tile的行列/有效行列等参数大小均必须小于等于16bit。
-
----
-
-## 汇编示例
-
-```asm
-    TADDSC <LB0:20, LB1:32, LB2:24, s16>, T#1, [a0], T#2.reuse, ->T<2KB>
-```
-
-1. **操作内容**  
-    - 输入：`T#1` 、`T#2` Tile寄存器；`a0` 全局寄存器
-    - 输出：结果存入新的 `T` 队列Tile寄存器
-2. **数据处理范围**  
-    - 只处理前 `20列`（由 `LB0:20` 指定）  
-    - 有效行数为 `32`（`LB1:32`）  
-    - 总列数为：`24`（`LB2:24`）
-3. **数据格式**  
-    - 使用 `16位整数`（`s16`）格式处理数据  
-    - 每个元素占2字节（影响内存布局计算）
-4. **寄存器管理**  
-    - 输入寄存器 `T#2` 添加了 `.reuse` 标记，表示**执行后保留该寄存器**  
-    - 输入寄存器 `T#1` **执行后自动释放**（无reuse标记）  
-    - 输出寄存器分配 `2KB` 空间（足够存储计算结果）
-5. **特殊处理**  
-    - 区域中**超出有效范围的部分**不初始化（`PadValue` 缺省）  
-    - 输出寄存器由硬件自动分配（`->T` 未指定具体寄存器号）
-
----
-
-## 备注
-
-此指令是TileOp模版块，软件只定义块头。
diff --git a/docs/zh/isa/header/tileblock/TFMOD.md b/docs/zh/isa/header/tileblock/TFMOD.md
deleted file mode 100644
index fdb28d52..00000000
--- a/docs/zh/isa/header/tileblock/TFMOD.md
+++ /dev/null
@@ -1,109 +0,0 @@
-# TFMOD
-
-## 说明
-
-**数据块余数(Tile Fmod)**
-
-`TFMOD` 对两个输入 Tile 逐元素求余数，结果写入输出 Tile 中。余数符号与被除数相同。
-
-实现伪代码示意如下：
-```pseudocode
-// 逐元素求余操作
-for r in 0..(Rv-1):         // 遍历所有行
-  for c in 0..(Cv-1):       // 遍历所有列
-    dst[r, c] = fmod(src0[r, c], src1[r, c])  // 对应位置元素求余数
-```
-
-实现示意图如下：
-
-![TFMOD](../../../figs/isa/tileop/TFMOD.png){ width="800" }
-
----
-
-## 汇编语法
-
-```asm
-    TFMOD <LB0:ValidCol, LB1:ValidRow, LB2:Col, DataType, PadValue>, SrcTile0<.reuse>, SrcTile1<.reuse>, ->DstTile<Size>
-```
-
-## 汇编符号
-
-- **ValidCol**：输入Tile中有效元素的列数。该参数可以通过以下3种形式配置到LB0寄存器中：
-    - **reg**：通过全局寄存器[GGPR](../../register/common/ggpr.md)设置。
-    - **imm**: 使用立即数设置。
-    - **reg+imm**：通过全局寄存器加立即数的形式设置。
-- **ValidRow**：输入Tile中有效元素的行数（可缺省，默认值：`1`）。该参数配置到LB1寄存器中，配置方式同上。
-- **Col**：输入Tile的总列数（可缺省，默认值：等于`ValidCol`）。该参数配置到LB2寄存器中，配置方式同上。
-- **Row**：输入Tile的总行数，通过公式计算：`Row = SrcTileSize / (Col × sizeof(DataType))`。
-- **DataType**：输入Tile元素的数据格式，支持类型见下表。
-- **PadValue**：输出Tile无效区域的填充值，可选：`Null`、`Zero`、`Max`、`Min`（可缺省，默认值：`Null`）。
-- **SrcTile0/SrcTile1**：输入Tile寄存器，支持`T`/`U`/`M`/`N`队列输入（参见：[Tile寄存器](../../register/common/tilereg.md)）。
-- **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
-- **DstTile**：输出Tile寄存器，支持`T`/`U`/`M`/`N`队列输出。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
-
-本指令支持数据类型（DataType）如下表所示：
-
-| 数据位宽 | 类型列表 |
-|----------|------------|
-| b64 | S64, U64, FP64 |
-| b32 | S32, U32, FP32, TF32, HF32 |
-| b16 | S16, U16, FP16, BF16 |
-| b8  | S8,  U8,  FP8(E4M3, E5M2) |
-
----
-
-## 编码格式
-
-该TileOp模版块编码为以下指令：
-
-- [BSTART.TEPL](../../blockIntro/tepl_block/header.md) `TFMOD, DataType`
-- [B.DATR](../../header/B.DATR.md) `PadValue`
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`    （注：*ValidCol*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*ValidRow*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*Col*）
-- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last, ->DstTile<Size>`
-
-## 约束条件
-
-- 两个输入Tile的以下参数必须一致，否则硬件不保证结果正确性：
-    - `SrcTile0::Row == SrcTile1::Row`, `SrcTile0::Col == SrcTile1::Col`
-    - `SrcTile0::ValidRow == SrcTile1::ValidRow`, `SrcTile0::ValidCol == SrcTile1::ValidCol`
-    - `SrcTile0::DataType == SrcTile1::DataType`
-- **尺寸范围**：
-    - 输入Tile的行列/有效行列等参数大小均必须小于等于16bit。
-    - 有效边界：`ValidRow <= Row`, `ValidCol <= Col`
-- **数据布局**：必须是行主序（RowMajor）。
-- **除零**：行为由实现定义。
-
----
-
-## 汇编示例
-
-```asm
-    TFMOD <LB0:32, LB1:a0, LB2:a1+10, fp16>, T#1, U#2.reuse, ->U<1KB>
-```
-
-1. **操作内容**  
-    - 输入：`T#1` 和 `U#2` Tile寄存器
-    - 输出：结果存入新的 `U` 队列Tile寄存器
-2. **数据处理范围**  
-    - 只处理前 `32列`（由 `LB0:32` 指定）  
-    - 有效行数由寄存器 `a0` 的值动态决定（`LB1:a0`）  
-    - 总列数动态计算为：`a1寄存器的值 + 10`（`LB2:a1+10`）
-3. **数据格式**  
-    - 使用 `16位浮点数`（`fp16`）格式处理数据  
-    - 每个元素占2字节（影响内存布局计算）
-4. **寄存器管理**  
-    - 输入寄存器 `U#2 添加了 `.reuse` 标记，表示**执行后保留该寄存器**  
-    - 输入寄存器 `T#1` **执行后自动释放**（无reuse标记）  
-    - 输出寄存器分配 `1KB` 空间（足够存储计算结果）
-5. **特殊处理**  
-    - 区域中**超出有效范围的部分**不初始化（`PadValue` 缺省）  
-    - 输出寄存器由硬件自动分配（`->U` 未指定具体寄存器号）
-
----
-
-## 备注
-
-此指令是TileOp模版块，软件只定义块头。
diff --git a/docs/zh/isa/header/tileblock/TFMODS.md b/docs/zh/isa/header/tileblock/TFMODS.md
deleted file mode 100644
index 47b7f427..00000000
--- a/docs/zh/isa/header/tileblock/TFMODS.md
+++ /dev/null
@@ -1,115 +0,0 @@
-# TFMODS
-
-## 说明
-
-**数据块余数(Tile Fmod with Scalar)**
-
-`TFMODS` 将输入 Tile 逐元素与 一个标量 相加，结果写入输出 Tile 中。余数符号与被除数相同。
-
-实现伪代码示意如下：
-```pseudocode
-// 逐元素求余操作
-for r in 0..(Rv-1):           // 遍历所有行
-  for c in 0..(Cv-1):       // 遍历所有列
-    dst[r, c] = fmod(src[r, c], scalar)  // 逐元素与标量求余数
-```
-
-实现示意图如下：
-
-![TFMODS](../../../figs/isa/tileop/TFMODS.png){ width="800" }
-
----
-
-## 汇编语法
-
-```asm
-    TFMODS <LB0:ValidCol, LB1:ValidRow, LB2:Col, DataType, PadValue>, SrcTile<.reuse>, [RegSrc], ->DstTile<Size>
-```
-
-## 汇编符号
-
-- **ValidCol**：输入Tile中有效元素的列数。该参数可以通过以下3种形式配置到LB0寄存器中：
-    - **reg**：通过全局寄存器[GGPR](../../register/common/ggpr.md)设置。
-    - **imm**: 使用立即数设置。
-    - **reg+imm**：通过全局寄存器加立即数的形式设置。
-- **ValidRow**：输入Tile中有效元素的行数（可缺省，默认值：`1`）。该参数配置到LB1寄存器中，配置方式同上。
-- **Col**：输入Tile的总列数（可缺省，默认值：等于`ValidCol`）。该参数配置到LB2寄存器中，配置方式同上。
-- **Row**：输入Tile的总行数，通过公式计算：`Row = SrcTileSize / (Col × sizeof(DataType))`。
-- **DataType**：输入Tile元素与标量的数据格式，支持类型见下表。
-- **PadValue**：输出Tile无效区域的填充值，可选：`Null`、`Zero`、`Max`、`Min`（可缺省，默认值：`Null`）。
-- **SrcTile**：输入Tile寄存器，支持`T`/`U`/`M`/`N`队列输入（参见：[Tile寄存器](../../register/common/tilereg.md)）。
-- **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
-- **RegSrc**：输入全局寄存器，用于存储标量值。（参见：[全局寄存器](../../register/common/ggpr.md)）
-- **DstTile**：输出Tile寄存器，支持`T`/`U`/`M`/`N`队列输出。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
-
-本指令支持数据类型（DataType）如下表所示：
-
-| 数据位宽 | 类型列表 |
-|----------|------------|
-| b64 | S64, U64, FP64 |
-| b32 | S32, U32, FP32, TF32, HF32 |
-| b16 | S16, U16, FP16, BF16 |
-| b8  | S8,  U8,  FP8(E4M3, E5M2) |
-
----
-
-## 编码格式
-
-该TileOp模版块编码为以下指令：
-
-- [BSTART.TEPL](../../blockIntro/tepl_block/header.md) `TFMODS, DataType`
-- [B.DATR](../../header/B.DATR.md) `PadValue`
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`   （注：*ValidCol*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`   （注：*ValidRow*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`   （注：*Col*）
-- [B.IOT](../../header/B.IOT.md) `SrcTile<.reuse>, last, ->DstTile<Size>`
-- [B.IOR](../../header/B.IOR.md) `RegSrc`
-
-## 约束条件
-
-- **静态参数**：
-    - `SrcTile::Row == DstTile::Row`
-    - `SrcTile::Col == DstTile::Col`
-- **动态参数**：
-    - `SrcTile::ValidRow == DstTile::ValidRow`
-    - `SrcTile::ValidCol == DstTile::ValidCol`
-- **有效边界**：
-    - `ValidRow <= Row`, `ValidCol <= Col`
-- **数据类型**：
-    - `SrcTile::DataType == DstTile::DataType`
-- **存储布局**：
-    - 必须是**行主序（RowMajor）**。
-- **尺寸范围**：
-    - Tile的行列/有效行列等参数大小均必须小于等于16bit。
-
----
-
-## 汇编示例
-
-```asm
-    TFMODS <LB0:16, LB1:32, fp16>, T#4.reuse, [a1], ->T<1KB>
-```
-
-1. **操作内容**  
-    - 输入：`T#4` Tile寄存器；`a1` 全局寄存器
-    - 输出：结果存入新的 `T` 队列Tile寄存器
-2. **数据处理范围**  
-    - 有效列数 `16`（由 `LB0:16` 指定）  
-    - 有效行数 `32`（由 `LB1:32` 指定）  
-    - 总列数缺省，默认等于 `16`
-3. **数据格式**  
-    - 使用 `8位浮点数`（`fp8`）格式处理数据  
-    - 每个元素占1字节（影响内存布局计算）
-4. **寄存器管理**  
-    - 输入寄存器 `T#3` 添加了 `.reuse` 标记，表示**执行后保留该寄存器**  
-    - 输出寄存器分配 `1KB` 空间（足够存储计算结果）
-5. **特殊处理**  
-    - 区域中**超出有效范围的部分**不初始化（`PadValue` 缺省）  
-    - 输出寄存器由硬件自动分配（`->T` 未指定具体寄存器号）
-
----
-
-## 备注
-
-此指令是TileOp模版块，软件只定义块头。
diff --git a/docs/zh/isa/header/tileblock/TGEMV.ACC.md b/docs/zh/isa/header/tileblock/TGEMV.ACC.md
index dad018d5..48fb8ecf 100644
--- a/docs/zh/isa/header/tileblock/TGEMV.ACC.md
+++ b/docs/zh/isa/header/tileblock/TGEMV.ACC.md
@@ -23,7 +23,7 @@ for n in 0..(N-1):         // 遍历N维度
 ## 汇编语法
 
 ```asm
-TGEMV.ACC <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, ACC, ->ACC<Size>
+TGEMV.ACC <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>
 ```
 
 ## 汇编符号
@@ -37,7 +37,7 @@ TGEMV.ACC <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, AC
 - **SrcTile1**：存储B矩阵的[Tile 寄存器](../../register/common/tilereg.md)，支持`T`/`U`/`M`/`N`队列输入。
 - **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的[Tile 寄存器](../../register/common/tilereg.md)（同时也做为输入）。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 本指令支持数据类型（DataType）如下表所示：
 
@@ -58,21 +58,21 @@ TGEMV.ACC <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, AC
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`    （注：*M*）
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*N*）
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*K*）
-- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last, ->ACC<Size>`
+- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last`
 
 ---
 
 ## 汇编示例
 
 ```asm
-TGEMV.ACC <LB0:1, LB1:16, LB2:32, FP16>, T#1, U#1, ACC, ->ACC<256B>
+TGEMV.ACC <LB0:1, LB1:16, LB2:32, FP16>, T#1, U#1
 ```
 
 - **输入输出**：
     - `SrcTile0 = T#1`：存放 A 向量的 tile。
     - `SrcTile1 = U#1`：存放 B 矩阵的 tile。
     - 两者均未带 .reuse 后缀，表示本条指令提交后，硬件允许释放这些寄存器的占用。
-    - `DstTile = ACC`: 存放C矩阵的 tile，分配容量为 256B。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
 - **尺寸参数设定**:
     - A 的维度为 `1×K = 1 × 32`，K 通过 “立即数” 设定。
     - B 的维度为 `K×N = 32 x 16`，N 通过 “立即数” 设定。
diff --git a/docs/zh/isa/header/tileblock/TGEMV.BIAS.md b/docs/zh/isa/header/tileblock/TGEMV.BIAS.md
index 5481003d..fd3e601b 100644
--- a/docs/zh/isa/header/tileblock/TGEMV.BIAS.md
+++ b/docs/zh/isa/header/tileblock/TGEMV.BIAS.md
@@ -25,7 +25,7 @@ for n in 0..(N-1):         // 遍历N维度
 ## 汇编语法
 
 ```asm
-TGEMV.BIAS <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, ->ACC<Size>
+TGEMV.BIAS <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>
 ```
 
 ## 汇编符号
@@ -40,7 +40,7 @@ TGEMV.BIAS <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, S
 - **SrcTile2**：存储Bias矩阵的[Tile 寄存器](../../register/common/tilereg.md)，支持`T`/`U`/`M`/`N`队列输入。
 - **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的[Tile 寄存器](../../register/common/tilereg.md)类型。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 本指令支持数据类型（DataType）如下表所示：
 
@@ -64,14 +64,14 @@ TGEMV.BIAS <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, S
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*N*）
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*K*）
 - [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`
-- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, last, ->ACC<Size>`
+- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, last`
 
 ---
 
 ## 汇编示例
 
 ```asm
-TGEMV.BIAS <LB0:1, LB1:32, LB2:32, FP16>, T#1, U#1, M#1, ->ACC<256B>
+TGEMV.BIAS <LB0:1, LB1:32, LB2:32, FP16>, T#1, U#1, M#1
 ```
 
 - **输入输出**：
@@ -79,7 +79,7 @@ TGEMV.BIAS <LB0:1, LB1:32, LB2:32, FP16>, T#1, U#1, M#1, ->ACC<256B>
     - `SrcTile1 = U#1`：存放 B 矩阵的 tile。
     - `SrcTile2 = M#1`：存放 Bias 矩阵的 tile。
     - 输入 tile 均未带 .reuse 后缀，表示本条指令提交后，硬件允许释放这些寄存器的占用。
-    - `DstTile = ACC`: 存放C矩阵的 tile，分配容量为 256B。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
 - **尺寸参数设定**:
     - A 的维度为 `1×K = 1 × 32`，K 通过 “立即数” 设定。
     - B 的维度为 `K×N = 32 x 32`，N 通过 “立即数” 设定。
diff --git a/docs/zh/isa/header/tileblock/TGEMV.md b/docs/zh/isa/header/tileblock/TGEMV.md
index f0390daf..b01e575b 100644
--- a/docs/zh/isa/header/tileblock/TGEMV.md
+++ b/docs/zh/isa/header/tileblock/TGEMV.md
@@ -24,7 +24,7 @@ for n in 0..(N-1):         // 遍历N维度
 ## 汇编语法
 
 ```asm
-TGEMV <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, ->ACC<Size>
+TGEMV <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>
 ```
 
 ## 汇编符号
@@ -38,7 +38,7 @@ TGEMV <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, ->ACC<
 - **SrcTile1**：存储B矩阵的[Tile 寄存器](../../register/common/tilereg.md)，支持`T`/`U`/`M`/`N`队列输入。
 - **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的[Tile 寄存器](../../register/common/tilereg.md)类型。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 本指令支持数据类型（DataType）如下表所示：
 
@@ -59,21 +59,21 @@ TGEMV <LB0:M, LB1:N, LB2:K, DataType> SrcTile0<.reuse>, SrcTile1<.reuse>, ->ACC<
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`    （注：*M*）
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*N*）
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*K*）
-- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last, ->ACC<Size>`
+- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last`
 
 ---
 
 ## 汇编示例
 
 ```asm
-TGEMV <LB0:1, LB1:16, LB2:32, FP16>, T#1, U#1, ->ACC<256B>
+TGEMV <LB0:1, LB1:16, LB2:32, FP16>, T#1, U#1
 ```
 
 - **输入输出**：
     - `SrcTile0 = T#1`：存放 A 向量的 tile。
     - `SrcTile1 = U#1`：存放 B 矩阵的 tile。
     - 两者均未带 .reuse 后缀，表示本条指令提交后，硬件允许释放这些寄存器的占用。
-    - `DstTile = ACC`: 存放C矩阵的 tile，分配容量为 256B。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
 - **尺寸参数设定**:
     - A 的维度为 `1×K = 1 × 32`，K 通过 “立即数” 设定。
     - B 的维度为 `K×N = 32 x 16`，N 通过 “立即数” 设定。
diff --git a/docs/zh/isa/header/tileblock/TGEMVMX.ACC.md b/docs/zh/isa/header/tileblock/TGEMVMX.ACC.md
index de8dc426..a8389954 100644
--- a/docs/zh/isa/header/tileblock/TGEMVMX.ACC.md
+++ b/docs/zh/isa/header/tileblock/TGEMVMX.ACC.md
@@ -27,7 +27,7 @@ for n in 0..(N-1):         // 遍历N维度
 ## 汇编语法
 
 ```asm
-TGEMVMX.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>, ACC, ->ACC<Size>
+TGEMVMX.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>
 ```
 
 ## 汇编符号
@@ -46,7 +46,7 @@ TGEMVMX.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTil
 - **SrcTile3**：存储缩放B矩阵的[Tile 寄存器](../../register/common/tilereg.md)，支持`T`/`U`/`M`/`N`队列输入。
 - **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的[Tile 寄存器](../../register/common/tilereg.md)（同时也做为输入）。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 ---
 
@@ -110,7 +110,7 @@ TGEMVMX.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTil
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*N*）
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*K*）
 - [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`
-- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>, last, ->ACC<Size>`
+- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>, last`
 
 ---
 
@@ -119,7 +119,7 @@ TGEMVMX.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTil
 下面给出一个 **TGEMVMX.ACC** 汇编示例，示范如何同时传入向量 A、A 的缩放、矩阵 B 以及 B 的缩放，并累加结果矩阵 C：
 
 ```asm
-TGEMVMX.ACC <LB0:1, LB1:32, LB2:64, e3m4, e1m2X2>, T#1.reuse, U#1, M#2, N#2, ACC, ->ACC<512B>
+TGEMVMX.ACC <LB0:1, LB1:32, LB2:64, e3m4, e1m2X2>, T#1.reuse, U#1, M#2, N#2
 ```
 
 - **寄存器绑定**：
@@ -127,7 +127,7 @@ TGEMVMX.ACC <LB0:1, LB1:32, LB2:64, e3m4, e1m2X2>, T#1.reuse, U#1, M#2, N#2, ACC
     - `SrcTile1 = U#1`：存放 A 的缩放因子（`1 × K/32 = 1 × 2` 个 E8M0 值）。
     - `SrcTile2 = M#2`：存放 B 矩阵（`64 x 32`），采用 Zn 布局。
     - `SrcTile3 = N#2`：存放 B 的缩放因子（`(K/32) × N = 2 × 32`，分形为 `2 × 16`）。
-    - `DstTile = ACC<512B>`：存放累加 `1 × 32` 的 FP32 结果。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
 - **尺寸设定**：
     - `M = 1`：A 为单行向量。
     - `N = 32`：结果/输出宽度。
diff --git a/docs/zh/isa/header/tileblock/TGEMVMX.BIAS.md b/docs/zh/isa/header/tileblock/TGEMVMX.BIAS.md
index 296a1317..4e17a829 100644
--- a/docs/zh/isa/header/tileblock/TGEMVMX.BIAS.md
+++ b/docs/zh/isa/header/tileblock/TGEMVMX.BIAS.md
@@ -29,7 +29,7 @@ for n in 0..(N-1):         // 遍历N维度
 ## 汇编语法
 
 ```asm
-TGEMVMX.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>, SrcTile4<.reuse>, ->ACC<Size>
+TGEMVMX.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>, SrcTile4<.reuse>
 ```
 
 ## 汇编符号
@@ -49,7 +49,7 @@ TGEMVMX.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTi
 - **SrcTile4**：存储偏置Bias矩阵的[Tile 寄存器](../../register/common/tilereg.md)，支持`T`/`U`/`M`/`N`队列输入。
 - **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的[Tile 寄存器](../../register/common/tilereg.md)。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 ---
 
@@ -120,7 +120,7 @@ TGEMVMX.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTi
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*K*）
 - [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`
 - [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>`
-- [B.IOT](../../header/B.IOT.md) `SrcTile4<.reuse>, last, ->ACC<Size>`
+- [B.IOT](../../header/B.IOT.md) `SrcTile4<.reuse>, last`
 
 ---
 
@@ -129,7 +129,7 @@ TGEMVMX.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTi
 下面给出一个 **TGEMVMX.BIAS** 汇编示例，示范如何同时传入向量 A、A 的缩放、矩阵 B 以及 B 的缩放，并累加结果矩阵 C：
 
 ```asm
-TGEMVMX.BIAS <LB0:1, LB1:32, LB2:64, e3m4, e1m2X2>, T#1.reuse, U#1, M#2, N#2, T#2, ->ACC<512B>
+TGEMVMX.BIAS <LB0:1, LB1:32, LB2:64, e3m4, e1m2X2>, T#1.reuse, U#1, M#2, N#2, T#2
 ```
 
 - **寄存器绑定**：
@@ -138,7 +138,7 @@ TGEMVMX.BIAS <LB0:1, LB1:32, LB2:64, e3m4, e1m2X2>, T#1.reuse, U#1, M#2, N#2, T#
     - `SrcTile2 = M#2`：存放 B 矩阵（`64 x 32`），采用 Zn 布局。
     - `SrcTile3 = N#2`：存放 B 的缩放因子（`(K/32) × N = 2 × 32`，分形为 `2 × 16`）。
     - `SrcTile4 = T#2`：存放 Bias 矩阵（`(1 × N = 1 × 32`。
-    - `DstTile = ACC<512B>`：存放累加 `1 × 32` 的 FP32 结果。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
 - **尺寸设定**：
     - `M = 1`：A 为单行向量。
     - `N = 32`：结果/输出宽度。
diff --git a/docs/zh/isa/header/tileblock/TGEMVMX.md b/docs/zh/isa/header/tileblock/TGEMVMX.md
index ec28141d..28c0604c 100644
--- a/docs/zh/isa/header/tileblock/TGEMVMX.md
+++ b/docs/zh/isa/header/tileblock/TGEMVMX.md
@@ -26,7 +26,7 @@ for n in 0..(N-1):         // 遍历N维度
 ## 汇编语法
 
 ```asm
-TGEMVMX <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>, ->ACC<Size>
+TGEMVMX <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>
 ```
 
 ## 汇编符号
@@ -45,7 +45,7 @@ TGEMVMX <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.
 - **SrcTile3**：存储缩放B矩阵的[Tile 寄存器](../../register/common/tilereg.md)，支持`T`/`U`/`M`/`N`队列输入。
 - **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的[Tile 寄存器](../../register/common/tilereg.md)。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 ---
 
@@ -109,7 +109,7 @@ TGEMVMX <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*N*）
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*K*）
 - [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`
-- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>, last, ->ACC<Size>`
+- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>, last`
 
 ---
 
@@ -118,7 +118,7 @@ TGEMVMX <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.
 下面给出一个 **TGEMVMX** 汇编示例，示范如何同时传入向量 A、A 的缩放、矩阵 B 以及 B 的缩放，并生成结果矩阵 C：
 
 ```asm
-TGEMVMX <LB0:1, LB1:32, LB2:64, e3m4, e1m2X2>, T#1.reuse, U#1, M#2, N#2, ->ACC<512B>
+TGEMVMX <LB0:1, LB1:32, LB2:64, e3m4, e1m2X2>, T#1.reuse, U#1, M#2, N#2
 ```
 
 - **寄存器绑定**：
@@ -126,7 +126,7 @@ TGEMVMX <LB0:1, LB1:32, LB2:64, e3m4, e1m2X2>, T#1.reuse, U#1, M#2, N#2, ->ACC<5
     - `SrcTile1 = U#1`：存放 A 的缩放因子（`1 × K/32 = 1 × 2` 个 E8M0 值）。
     - `SrcTile2 = M#2`：存放 B 矩阵（`64 x 32`），采用 Zn 布局。
     - `SrcTile3 = N#2`：存放 B 的缩放因子（`(K/32) × N = 2 × 32`，分形为 `2 × 16`）。
-    - `DstTile = ACC<512B>`：存放输出 `1 × 32` 的 FP32 结果。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
 - **尺寸设定**：
     - `M = 1`：A 为单行向量。
     - `N = 32`：结果/输出宽度。
diff --git a/docs/zh/isa/header/tileblock/TLRELU.md b/docs/zh/isa/header/tileblock/TLRELU.md
deleted file mode 100644
index dd3947f0..00000000
--- a/docs/zh/isa/header/tileblock/TLRELU.md
+++ /dev/null
@@ -1,115 +0,0 @@
-# TLRELU
-
-## 说明
-
-**数据块标量ReLU(Tile ReLU with Scalar)**
-
-`TLRELU` 对输入 Tile 逐元素进行Leaky ReLU运算，结果写入输出 Tile 中。 
-
-实现伪代码示意如下：
-```pseudocode
-// 逐元素LReLU操作
-for r in 0..(Rv-1):           // 遍历所有行
-  for c in 0..(Cv-1):       // 遍历所有列
-    dst[r, c] = (src0[r, c] > 0) ? src0[r, c] : (scalar * src0[r, c])  // 逐元素LReLU
-```
-
-实现示意图如下：
-
-![TLRELU](../../../figs/isa/tileop/TLRELU.png){ width="800" }
-
----
-
-## 汇编语法
-
-```asm
-    TLRELU <LB0:ValidCol, LB1:ValidRow, LB2:Col, DataType, PadValue>, SrcTile<.reuse>, [RegSrc], ->DstTile<Size>
-```
-
-## 汇编符号
-
-- **ValidCol**：输入Tile中有效元素的列数。该参数可以通过以下3种形式配置到LB0寄存器中：
-    - **reg**：通过全局寄存器[GGPR](../../register/common/ggpr.md)设置。
-    - **imm**: 使用立即数设置。
-    - **reg+imm**：通过全局寄存器加立即数的形式设置。
-- **ValidRow**：输入Tile中有效元素的行数（可缺省，默认值：`1`）。该参数配置到LB1寄存器中，配置方式同上。
-- **Col**：输入Tile的总列数（可缺省，默认值：等于`ValidCol`）。该参数配置到LB2寄存器中，配置方式同上。
-- **Row**：输入Tile的总行数，通过公式计算：`Row = SrcTileSize / (Col × sizeof(DataType))`。
-- **DataType**：输入Tile元素与标量的数据格式，支持类型见下表。
-- **PadValue**：输出Tile无效区域的填充值，可选：`Null`、`Zero`、`Max`、`Min`（可缺省，默认值：`Null`）。
-- **SrcTile**：输入Tile寄存器，支持`T`/`U`/`M`/`N`队列输入（参见：[Tile寄存器](../../register/common/tilereg.md)）。
-- **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
-- **RegSrc**：输入全局寄存器，用于存储标量值。（参见：[全局寄存器](../../register/common/ggpr.md)）
-- **DstTile**：输出Tile寄存器，支持`T`/`U`/`M`/`N`队列输出。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
-
-本指令支持数据类型（DataType）如下表所示：
-
-| 数据位宽 | 类型列表 |
-|----------|------------|
-| b64 | S64, U64, FP64 |
-| b32 | S32, U32, FP32, TF32, HF32 |
-| b16 | S16, U16, FP16, BF16 |
-| b8  | S8,  U8,  FP8(E4M3, E5M2) |
-
----
-
-## 编码格式
-
-该TileOp模版块编码为以下指令：
-
-- [BSTART.TEPL](../../blockIntro/tepl_block/header.md) `TLRELU, DataType`
-- [B.DATR](../../header/B.DATR.md) `PadValue`
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`   （注：*ValidCol*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`   （注：*ValidRow*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`   （注：*Col*）
-- [B.IOT](../../header/B.IOT.md) `SrcTile<.reuse>, last, ->DstTile<Size>`
-- [B.IOR](../../header/B.IOR.md) `RegSrc`
-
-## 约束条件
-
-- **静态参数**：
-    - `SrcTile::Row == DstTile::Row`
-    - `SrcTile::Col == DstTile::Col`
-- **动态参数**：
-    - `SrcTile::ValidRow == DstTile::ValidRow`
-    - `SrcTile::ValidCol == DstTile::ValidCol`
-- **有效边界**：
-    - `ValidRow <= Row`, `ValidCol <= Col`
-- **数据类型**：
-    - `SrcTile::DataType == DstTile::DataType`
-- **存储布局**：
-    - 必须是**行主序（RowMajor）**。
-- **尺寸范围**：
-    - Tile的行列/有效行列等参数大小均必须小于等于16bit。
-
----
-
-## 汇编示例
-
-```asm
-    TLRELU <LB0:16, LB1:32, fp16>, T#3.reuse, [a1], ->T<1KB>
-```
-
-1. **操作内容**  
-    - 输入：`T#3` Tile寄存器；`a1` 全局寄存器
-    - 输出：结果存入新的 `T` 队列Tile寄存器
-2. **数据处理范围**  
-    - 有效列数 `16`（由 `LB0:16` 指定）  
-    - 有效行数 `32`（由 `LB1:32` 指定）  
-    - 总列数缺省，默认等于 `16`
-3. **数据格式**  
-    - 使用 `16位浮点数`（`fp16`）格式处理数据  
-    - 每个元素占1字节（影响内存布局计算）
-4. **寄存器管理**  
-    - 输入寄存器 `T#3` 添加了 `.reuse` 标记，表示**执行后保留该寄存器**  
-    - 输出寄存器分配 `1KB` 空间（足够存储计算结果）
-5. **特殊处理**  
-    - 区域中**超出有效范围的部分**不初始化（`PadValue` 缺省）  
-    - 输出寄存器由硬件自动分配（`->T` 未指定具体寄存器号）
-
----
-
-## 备注
-
-此指令是TileOp模版块，软件只定义块头。
diff --git a/docs/zh/isa/header/tileblock/TMATMUL.ACC.md b/docs/zh/isa/header/tileblock/TMATMUL.ACC.md
index 353202e0..f164d962 100644
--- a/docs/zh/isa/header/tileblock/TMATMUL.ACC.md
+++ b/docs/zh/isa/header/tileblock/TMATMUL.ACC.md
@@ -15,7 +15,7 @@ Matrix_C += Matrix_A * Matrix_B
 ## 汇编语法
 
 ```asm
-TMATMUL.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, ACC, ->ACC<Size>
+TMATMUL.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>
 ```
 
 ## 汇编符号
@@ -30,7 +30,7 @@ TMATMUL.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTil
 - **SrcTile1**：存储B矩阵的[Tile 寄存器](../../register/common/tilereg.md)。
 - **reuse**：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储C矩阵和结果矩阵的[Tile 寄存器](../../register/common/tilereg.md)。
-- **Size**：指示输出Tile寄存器空间大小的立即数。容量约束请见[Tile寄存器介绍](../../register/common/tilereg.md)。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 本指令 A/B矩阵支持的数据类型（DataTypeA/B）如下表所示：
 
@@ -53,7 +53,7 @@ TMATMUL.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTil
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`    *(注：M)*
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    *(注：N)*
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    *(注：K)*
-- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last, ->ACC<Size>`
+- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last`
 
 注意：ACC寄存器为隐含输入。
 
@@ -81,7 +81,7 @@ void TMATMUL_ACC(Tile __out__ C, Tile __in__ B, Tile __in__ A) {
 ## 汇编示例
 
 ```asm
-TMATMUL.ACC <LB0:100, LB1:a0, LB2:a1+10, FP32>, T#1, U#1, ACC, ->ACC<64KB>
+TMATMUL.ACC <LB0:100, LB1:a0, LB2:a1+10, FP32>, T#1, U#1
 ```
 
 - **输入输出**：
diff --git a/docs/zh/isa/header/tileblock/TMATMUL.BIAS.md b/docs/zh/isa/header/tileblock/TMATMUL.BIAS.md
index c32100a1..c7bb096f 100644
--- a/docs/zh/isa/header/tileblock/TMATMUL.BIAS.md
+++ b/docs/zh/isa/header/tileblock/TMATMUL.BIAS.md
@@ -19,7 +19,7 @@ C[i, j] = sum_k(A[i, k] × B[k, j]) + Bias[0, j]
 ## 汇编语法
 
 ```asm
-TMATMUL.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, ->ACC<Size>
+TMATMUL.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>
 ```
 
 ## 汇编符号
@@ -35,7 +35,7 @@ TMATMUL.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTi
 - **SrcTile2**：存储Bias矩阵的[Tile 寄存器](../../register/common/tilereg.md)。
 - **reuse**：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的[Tile 寄存器](../../register/common/tilereg.md)类型。
-- **Size**：指示输出Tile寄存器空间大小的立即数。容量约束请见[Tile寄存器介绍](../../register/common/tilereg.md)。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 本指令 A/B矩阵支持的数据类型（DataTypeA/B）如下表所示：
 
@@ -65,7 +65,7 @@ Bias 矩阵特点：
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    *(注：N)*
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    *(注：K)*
 - [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`
-- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, last, ->ACC<Size>`
+- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, last`
 
 ---
 
@@ -91,7 +91,7 @@ void TMATMUL.BIAS(Tile __out__ D, Tile __in__ A, Tile __in__ B, Tile __in__ Bias
 ## 汇编示例
 
 ```asm
-TMATMUL.BIAS <LB0:100, LB1:a0, LB2:a1+10, FP32>, T#1, U#1, N#1, ->ACC<64KB>
+TMATMUL.BIAS <LB0:100, LB1:a0, LB2:a1+10, FP32>, T#1, U#1, N#1
 ```
 
 - **输入/输出含义**:
@@ -99,7 +99,7 @@ TMATMUL.BIAS <LB0:100, LB1:a0, LB2:a1+10, FP32>, T#1, U#1, N#1, ->ACC<64KB>
     - SrcTile1 = U#1：存放 B 矩阵的 tile。
     - SrcTile2 = N#1：存放 Bias 矩阵的 tile（形状 1×N，按列广播到输出的每一行）。
     - 以上三个源寄存器均未带 `.reuse` 后缀，表示本条指令提交后，硬件可释放这些寄存器的占用。
-    - DstTile = ACC：存放结果矩阵 C 的 tile，容量配置为 64KB。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
 - **尺寸参数设定**:
     - M = LB0:100，表示 A 的行数为 100。
     - N = LB1:a0，表示 B 的列数为 a0（同时也是 Bias 的列数与 C 的列数）。
diff --git a/docs/zh/isa/header/tileblock/TMATMUL.md b/docs/zh/isa/header/tileblock/TMATMUL.md
index a58286f6..b99f10f6 100644
--- a/docs/zh/isa/header/tileblock/TMATMUL.md
+++ b/docs/zh/isa/header/tileblock/TMATMUL.md
@@ -19,7 +19,7 @@ C[i, j] = sum_k(A[i, k] × B[k, j])
 ## 汇编语法
 
 ```asm
-TMATMUL <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, ->ACC<Size>
+TMATMUL <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>
 ```
 
 ## 汇编符号
@@ -33,7 +33,7 @@ TMATMUL <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.
 - **SrcTile1**：存储B矩阵的[Tile 寄存器](../../register/common/tilereg.md)。
 - **reuse**：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的[Tile 寄存器](../../register/common/tilereg.md)类型。
-- **Size**：指示输出Tile寄存器空间大小的立即数。容量约束请见[Tile寄存器介绍](../../register/common/tilereg.md)。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 本指令 A/B矩阵支持的数据类型（DataTypeA/B）如下表所示：
 
@@ -56,7 +56,7 @@ TMATMUL <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`    *(注：M)*
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    *(注：N)*
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    *(注：K)*
-- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last, ->ACC<Size>`
+- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last`
 
 ---
 
@@ -93,7 +93,7 @@ void TMATMUL(Tile __out__ C, Tile __in__ B, Tile __in__ A) {
 
 示例1：fp16 x fp8(e5m2)
 ```asm
-TMATMUL <LB0:32, LB1:64, LB2:16, fp16, e5m2> T#1.reuse, M#1, ->ACC<8KB>
+TMATMUL <LB0:32, LB1:64, LB2:16, fp16, e5m2> T#1.reuse, M#1
 ```
 
 - 输入左矩阵：
@@ -105,14 +105,14 @@ TMATMUL <LB0:32, LB1:64, LB2:16, fp16, e5m2> T#1.reuse, M#1, ->ACC<8KB>
     - 形状尺寸（K x N）：16 x 64
     - 数据格式：e5m2
 - 输出结果矩阵：
-    - 寄存器：DstTile = ACC，申请空间 8KB。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
     - 形状尺寸（M x N）：32 x 64
     - 数据格式：fp32, 输入统一转换为fp32精度进行CUBE运算。
 
 
 示例2：TMATMUL的e1m2x2输入
 ```asm
-TMATMUL <LB0:32, LB1:32, LB2:64, e1m2x2>, T#1.reuse, U#1, ->ACC<4KB>
+TMATMUL <LB0:32, LB1:32, LB2:64, e1m2x2>, T#1.reuse, U#1
 ```
 
 - 输入左矩阵：
@@ -124,7 +124,7 @@ TMATMUL <LB0:32, LB1:32, LB2:64, e1m2x2>, T#1.reuse, U#1, ->ACC<4KB>
     - 形状尺寸（K x N）：64 x 32
     - 数据格式：e1m2x2
 - 输出结果矩阵：
-    - 寄存器：DstTile = ACC，申请空间 4KB。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
     - 形状尺寸（M x N）：32 x 32
     - 数据格式：fp32, 输入统一转换为fp32精度进行CUBE运算。
 
diff --git a/docs/zh/isa/header/tileblock/TMATMULMX.ACC.md b/docs/zh/isa/header/tileblock/TMATMULMX.ACC.md
index c10301d5..0aa707ab 100644
--- a/docs/zh/isa/header/tileblock/TMATMULMX.ACC.md
+++ b/docs/zh/isa/header/tileblock/TMATMULMX.ACC.md
@@ -13,7 +13,7 @@
 ## 汇编语法
 
 ```asm
-TMATMULMX.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>, ACC, ->ACC<Size>
+TMATMULMX.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>
 ```
 
 ## 汇编符号
@@ -31,7 +31,7 @@ TMATMULMX.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcT
 - **ACC**：**输入兼输出**。存储 **C 矩阵** (Matrix C) 及结果矩阵的 [Tile 寄存器](../../register/common/tilereg.md)。
     - 执行前：存放累加前的初始值。
     - 执行后：存放累加后的结果值。
-- **Size**：指示输出 Tile 寄存器空间大小的立即数，例如 `ACC<64KB>`。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 ---
 
@@ -51,7 +51,7 @@ TMATMULMX.ACC <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcT
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    *(注：N)*
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    *(注：K)*
 - [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`   *(A, ScaleA)*
-- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>, last, ACC, ->ACC<Size>`   *(B, ScaleB)*
+- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>, last`   *(B, ScaleB)*
 
 ## 执行模型
 
@@ -82,7 +82,7 @@ void TMATMULMX_ACC(Tile __inout__ C, Tile __in__ A, Tile __in__ ScaleA,
 ## 汇编示例
 
 ```asm
-TMATMULMX.ACC <LB0:100, LB1:a0, LB2:a1+10, e4m3, e5m2>, T#1, U#1, M#1, N#1, ACC, ->ACC<64KB>
+TMATMULMX.ACC <LB0:100, LB1:a0, LB2:a1+10, e4m3, e5m2>, T#1, U#1, M#1, N#1
 ```
 
 - **输入输出**：
diff --git a/docs/zh/isa/header/tileblock/TMATMULMX.BIAS.md b/docs/zh/isa/header/tileblock/TMATMULMX.BIAS.md
index 352ad9e0..d9216ba7 100644
--- a/docs/zh/isa/header/tileblock/TMATMULMX.BIAS.md
+++ b/docs/zh/isa/header/tileblock/TMATMULMX.BIAS.md
@@ -18,7 +18,7 @@ C[i, j] = Σ(k=0 to K-1) (A[i, k] * ScaleA[i, k]) × (B[k, j] * ScaleB[k, j]) +
 ## 汇编语法
 
 ```asm
-TMATMULMX.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>, SrcTile4<.reuse>, ->ACC<Size>
+TMATMULMX.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>, SrcTile4<.reuse>
 ```
 
 ## 汇编符号
@@ -36,7 +36,7 @@ TMATMULMX.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, Src
 - **SrcTile4**：存储 **偏置向量Bias** (Bias Vector) 的 [Tile 寄存器](../../register/common/tilereg.md)。
 - **reuse**：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的 [Tile 寄存器](../../register/common/tilereg.md) 类型。
-- **Size**：指示输出 Tile 寄存器空间大小的立即数，例如 `` `ACC<64KB>` ``。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 ---
 
@@ -71,7 +71,7 @@ TMATMULMX.BIAS <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, Src
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    *(注：K)*
 - [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`   *(A, ScaleA)*
 - [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>`   *(B, ScaleB)*
-- [B.IOT](../../header/B.IOT.md) `SrcTile4<.reuse>, last, ->ACC<Size>`  *(Bias, Out)*
+- [B.IOT](../../header/B.IOT.md) `SrcTile4<.reuse>, last`  *(Bias, Out)*
 
 ## 执行模型
 
@@ -102,7 +102,7 @@ void TMATMULMX_BIAS(Tile __out__ C, Tile __in__ A, Tile __in__ ScaleA,
 ## 汇编示例
 
 ```asm
-TMATMULMX.BIAS <LB0:100, LB1:a0, LB2:a1+10, e5m2, e1m2x2>, T#1, U#1, M#1, N#1, T#2, ->ACC<64KB>
+TMATMULMX.BIAS <LB0:100, LB1:a0, LB2:a1+10, e5m2, e1m2x2>, T#1, U#1, M#1, N#1, T#2
 ```
 
 - **输入输出**：
@@ -111,7 +111,7 @@ TMATMULMX.BIAS <LB0:100, LB1:a0, LB2:a1+10, e5m2, e1m2x2>, T#1, U#1, M#1, N#1, T
     - `SrcTile2 = M#1`：存放 B 矩阵。
     - `SrcTile3 = N#1`：存放 B 缩放矩阵。
     - `SrcTile4 = T#2`：存放 **Bias 偏置向量** (1xN)。
-    - `DstTile = ACC`：存放结果矩阵。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
 - **尺寸参数设定**:
     - A 的维度为 `M×K = 100 × (a1 + 10)`。
     - B 的维度为 `K×N = (a1 + 10) × a0`。
diff --git a/docs/zh/isa/header/tileblock/TMATMULMX.md b/docs/zh/isa/header/tileblock/TMATMULMX.md
index 59fe9127..13d83ef9 100644
--- a/docs/zh/isa/header/tileblock/TMATMULMX.md
+++ b/docs/zh/isa/header/tileblock/TMATMULMX.md
@@ -13,7 +13,7 @@
 ## 汇编语法
 
 ```asm
-TMATMULMX <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>, ->ACC<Size>
+TMATMULMX <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, SrcTile3<.reuse>
 ```
 
 ## 汇编符号
@@ -29,7 +29,7 @@ TMATMULMX <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1
 - **SrcTile3**：存储 **缩放矩阵B** (Scale Matrix B) 的 [Tile 寄存器](../../register/common/tilereg.md)。
 - **reuse**：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
 - **ACC**：存储结果矩阵的 [Tile 寄存器](../../register/common/tilereg.md) 类型。
-- **Size**：指示输出 Tile 寄存器空间大小的立即数，例如 `ACC<64KB>`。
+- **ACC**：由 CUBE opcode 隐式选择，不在 `B.IOT` 中编码，也没有目的 Tile size 字段。
 
 ---
 
@@ -43,7 +43,7 @@ TMATMULMX <LB0:M, LB1:N, LB2:K, DataTypeA, DataTypeB> SrcTile0<.reuse>, SrcTile1
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    *(注：N)*
 - [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    *(注：K)*
 - [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`   *(A, ScaleA)*
-- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>, last, ->ACC<Size>`   *(B, ScaleB)*
+- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, SrcTile3<.reuse>, last`   *(B, ScaleB)*
 
 ---
 
@@ -142,7 +142,7 @@ FP8 + HiF4输入的缩放矩阵乘 实现示意图如下：
 ## 汇编示例
 
 ```asm
-TMATMULMX <LB0:100, LB1:a0, LB2:a1+10, e4m3, e1m2x2>, T#1, U#1, M#1, N#1, ->ACC<64KB>
+TMATMULMX <LB0:100, LB1:a0, LB2:a1+10, e4m3, e1m2x2>, T#1, U#1, M#1, N#1
 ```
 
 - **输入输出**：
@@ -150,7 +150,7 @@ TMATMULMX <LB0:100, LB1:a0, LB2:a1+10, e4m3, e1m2x2>, T#1, U#1, M#1, N#1, ->ACC<
     - `SrcTile1 = U#1`：存放 A 缩放矩阵 (Scale Matrix A)。
     - `SrcTile2 = M#1`：存放 B 矩阵 (Matrix B)。
     - `SrcTile3 = N#1`：存放 B 缩放矩阵 (Scale Matrix B)。
-    - `DstTile = ACC`：存放结果矩阵，分配容量为 64KB。
+    - ACC 为隐式状态，不通过 `B.IOT` 编码。
 - **指令功能**：执行带缩放的矩阵乘法 `D = (ScaleA × A) × (ScaleB × B)`。
 - **尺寸参数设定**:
     - A 的维度为 `M×K = 100 × (a1 + 10)`。
diff --git a/docs/zh/isa/header/tileblock/TRELU.md b/docs/zh/isa/header/tileblock/TRELU.md
index 7db0361c..b738e4d2 100644
--- a/docs/zh/isa/header/tileblock/TRELU.md
+++ b/docs/zh/isa/header/tileblock/TRELU.md
@@ -111,7 +111,7 @@ ReLU（Rectified Linear Unit）是一种广泛使用的激活函数，尤其在
 
 为了解决 “神经元死亡” 问题，同时支持一些ReLU的变种：
 
-- Leaky ReLU：允许负区间有一个小的斜率（如0.01），即当 x < 0 时输出 0.01x。（参见[TLRELU](./TLRELU.md)）
+- Leaky ReLU 不属于 PTO ISA 0.57.1 的直接操作集合；`TLRELU` 已删除并保留其旧选择子。
 - Parametric ReLU：将负区间的斜率作为可学习的参数。（参见[TPRELU](./TPRELU.md)）
 
 ## 备注
diff --git a/docs/zh/isa/header/tileblock/TSUBC.md b/docs/zh/isa/header/tileblock/TSUBC.md
deleted file mode 100644
index 3c0c6f31..00000000
--- a/docs/zh/isa/header/tileblock/TSUBC.md
+++ /dev/null
@@ -1,111 +0,0 @@
-# TSUBC
-
-## 说明
-
-**数据块带进位减法(Tile Subtract with Carry)**
-
-`TSUBC` 将三个输入 Tile 逐元素相减，结果写入输出 Tile 中。 
-
-实现伪代码示意如下：
-```pseudocode
-// 逐元素减法操作
-for r in 0..(Rv-1):           // 遍历所有行
-  for c in 0..(Cv-1):       // 遍历所有列
-    dst[r, c] = src0[r, c] + src1[r, c] + src2[r, c]  // 对应位置元素相减
-```
-
-实现示意图如下：
-
-![TSUBC](../../../figs/isa/tileop/TSUBC.png){ width="900" }
-
----
-
-## 汇编语法
-
-```asm
-    TSUBC <LB0:ValidCol, LB1:ValidRow, LB2:Col, DataType, PadValue>, SrcTile0<.reuse>, SrcTile1<.reuse>, SrcTile2<.reuse>, ->DstTile<Size>
-```
-
-## 汇编符号
-
-- **ValidCol**：输入Tile中有效元素的列数。该参数可以通过以下3种形式配置到LB0寄存器中：
-    - **reg**：通过全局寄存器[GGPR](../../register/common/ggpr.md)设置。
-    - **imm**: 使用立即数设置。
-    - **reg+imm**：通过全局寄存器加立即数的形式设置。
-- **ValidRow**：输入Tile中有效元素的行数（可缺省，默认值：`1`）。该参数配置到LB1寄存器中，配置方式同上。
-- **Col**：输入Tile的总列数（可缺省，默认值：等于`ValidCol`）。该参数配置到LB2寄存器中，配置方式同上。
-- **Row**：输入Tile的总行数，通过公式计算：`Row = SrcTileSize / (Col × sizeof(DataType))`。
-- **DataType**：输入Tile元素的数据格式，支持类型见下表。
-- **PadValue**：输出Tile无效区域的填充值，可选：`Null`、`Zero`、`Max`、`Min`（可缺省，默认值：`Null`）。
-- **SrcTile0/1/2**：输入Tile寄存器，支持`T`/`U`/`M`/`N`队列输入（参见：[Tile寄存器](../../register/common/tilereg.md)）。
-- **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
-- **DstTile**：输出Tile寄存器，支持`T`/`U`/`M`/`N`队列输出。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
-
-本指令支持数据类型（DataType）如下表所示：
-
-| 数据位宽 | 类型列表 |
-|----------|------------|
-| b64 | S64, U64, FP64 |
-| b32 | S32, U32, FP32, TF32, HF32 |
-| b16 | S16, U16, FP16, BF16 |
-| b8  | S8,  U8,  FP8(E4M3, E5M2) |
-
----
-
-## 编码格式
-
-该TileOp模版块编码为以下指令：
-
-- [BSTART.TEPL](../../blockIntro/tepl_block/header.md) `TSUBC, DataType`
-- [B.DATR](../../header/B.DATR.md) `PadValue`
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`    （注：*ValidCol*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*ValidRow*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*Col*）
-- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>`
-- [B.IOT](../../header/B.IOT.md) `SrcTile2<.reuse>, last, ->DstTile<Size>`
-
-## 约束条件
-
-- 多个输入Tile的以下参数必须一致，否则硬件不保证结果正确性：
-    - `src0::Row == src1::Row == src2::Row`
-    - `src0::Col == src1::Col == src2::Col`
-    - `src0::ValidRow == src1::ValidRow == src2::ValidRow`
-    - `src0::ValidCol == src1::ValidCol == src2::ValidCol`
-    - `src0::DataType == src1::DataType == src2::DataType`
-- **尺寸范围**：
-    - 输入Tile的行列/有效行列等参数大小均必须小于等于16bit。
-    - 有效边界：`ValidRow <= Row`, `ValidCol <= Col`
-- **数据布局**：必须是行主序（RowMajor）。
-
----
-
-## 汇编示例
-
-```asm
-    TSUBC <LB0:40, LB1:32, LB2:48, s16>, T#1, T#2.reuse, U#4, ->T<4KB>
-```
-
-1. **操作内容**  
-    - 输入：`T#1` 、`T#2` 和 `U#4` Tile寄存器
-    - 输出：结果存入新的 `T` 队列Tile寄存器
-2. **数据处理范围**  
-    - 只处理前 `40列`（由 `LB0:40` 指定）  
-    - 有效行数为 `32`（`LB1:32`）  
-    - 总列数为：`48`（`LB2:48`）
-3. **数据格式**  
-    - 使用 `16位整数`（`s16`）格式处理数据  
-    - 每个元素占2字节（影响内存布局计算）
-4. **寄存器管理**  
-    - 输入寄存器 `T#2` 添加了 `.reuse` 标记，表示**执行后保留该寄存器**  
-    - 输入寄存器 `T#1` 和 `U#4` **执行后自动释放**（无reuse标记）  
-    - 输出寄存器分配 `4KB` 空间（足够存储计算结果）
-5. **特殊处理**  
-    - 区域中**超出有效范围的部分**不初始化（`PadValue` 缺省）  
-    - 输出寄存器由硬件自动分配（`->T` 未指定具体寄存器号）
-
----
-
-## 备注
-
-此指令是TileOp模版块，软件只定义块头。
diff --git a/docs/zh/isa/header/tileblock/TSUBSC.md b/docs/zh/isa/header/tileblock/TSUBSC.md
deleted file mode 100644
index caed423a..00000000
--- a/docs/zh/isa/header/tileblock/TSUBSC.md
+++ /dev/null
@@ -1,115 +0,0 @@
-# TSUBSC
-
-## 说明
-
-**数据块与标量带进位减法(Tile Subtract Scalar with Carry)**
-
-`TSUBSC` 将两个输入 Tile 逐元素与标量相减，结果写入输出 Tile 中。 
-
-实现伪代码示意如下：
-```pseudocode
-// 逐元素带进位减法操作
-for r in 0..(Rv-1):           // 遍历所有行
-  for c in 0..(Cv-1):       // 遍历所有列
-    dst[r, c] = src0[r, c] - scalar + src1[r, c]  // 对应位置元素与标量相减
-```
-
-实现示意图如下：
-
-![TSUBSC](../../../figs/isa/tileop/TSUBSC.png){ width="900" }
-
----
-
-## 汇编语法
-
-```asm
-    TSUBSC <LB0:ValidCol, LB1:ValidRow, LB2:Col, DataType, PadValue>, SrcTile0<.reuse>, [RegSrc], SrcTile1<.reuse>, ->DstTile<Size>
-```
-
-## 汇编符号
-
-- **ValidCol**：输入Tile中有效元素的列数。该参数可以通过以下3种形式配置到LB0寄存器中：
-    - **reg**：通过全局寄存器[GGPR](../../register/common/ggpr.md)设置。
-    - **imm**: 使用立即数设置。
-    - **reg+imm**：通过全局寄存器加立即数的形式设置。
-- **ValidRow**：输入Tile中有效元素的行数（可缺省，默认值：`1`）。该参数配置到LB1寄存器中，配置方式同上。
-- **Col**：输入Tile的总列数（可缺省，默认值：等于`ValidCol`）。该参数配置到LB2寄存器中，配置方式同上。
-- **Row**：输入Tile的总行数，通过公式计算：`Row = SrcTileSize / (Col × sizeof(DataType))`。
-- **DataType**：输入Tile元素的数据格式，支持类型见下表。
-- **PadValue**：输出Tile无效区域的填充值，可选：`Null`、`Zero`、`Max`、`Min`（可缺省，默认值：`Null`）。
-- **SrcTile0/1**：输入Tile寄存器，支持`T`/`U`/`M`/`N`队列输入（参见：[Tile寄存器](../../register/common/tilereg.md)）。
-- **reuse**（后缀）：指示当前指令提交后保留寄存器（若无此标识，允许硬件自动释放）。
-- **RegSrc**：输入全局寄存器，用于存储标量值。（参见：[全局寄存器](../../register/common/ggpr.md)）
-- **DstTile**：输出Tile寄存器，支持`T`/`U`/`M`/`N`队列输出。
-- **Size**：输出Tile寄存器的空间大小（有效范围参见：[Tile寄存器](../../register/common/tilereg.md)）。
-
-本指令支持数据类型（DataType）如下表所示：
-
-| 数据位宽 | 类型列表 |
-|----------|------------|
-| b64 | S64, U64, FP64 |
-| b32 | S32, U32, FP32, TF32, HF32 |
-| b16 | S16, U16, FP16, BF16 |
-
----
-
-## 编码格式
-
-该TileOp模版块编码为以下指令：
-
-- [BSTART.TEPL](../../blockIntro/tepl_block/header.md) `TSUBSC, DataType`
-- [B.DATR](../../header/B.DATR.md) `PadValue`
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB0`    （注：*ValidCol*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB1`    （注：*ValidRow*）
-- [B.DIM](../../header/B.DIM.md) `reg, imm, ->LB2`    （注：*Col*）
-- [B.IOT](../../header/B.IOT.md) `SrcTile0<.reuse>, SrcTile1<.reuse>, last, ->DstTile<Size>`
-- [B.IOR](../../header/B.IOR.md) `RegSrc`
-
-## 约束条件
-
-- **静态参数**：
-    - `SrcTile0::Row == SrcTile1::Row == DstTile::Row`
-    - `SrcTile0::Col == SrcTile1::Col == DstTile::Col`
-- **动态参数**：
-    - `SrcTile0::ValidRow == SrcTile1::ValidRow == DstTile::ValidRow`
-    - `SrcTile0::ValidCol == SrcTile1::ValidCol == DstTile::ValidCol`
-- **有效边界**：
-    - `ValidRow <= Row`, `ValidCol <= Col`
-- **数据类型**：
-    - `SrcTile0::DataType == SrcTile1::DataType == DstTile::DataType`
-- **存储布局**：
-    - 必须是**行主序（RowMajor）**。
-- **尺寸范围**：
-    - Tile的行列/有效行列等参数大小均必须小于等于16bit。
-
----
-
-## 汇编示例
-
-```asm
-    TSUBSC <LB0:20, LB1:32, LB2:24, s16>, T#1, [a0], T#2.reuse, ->T<2KB>
-```
-
-1. **操作内容**  
-    - 输入：`T#1` 、`T#2` Tile寄存器；`a0` 全局寄存器
-    - 输出：结果存入新的 `T` 队列Tile寄存器
-2. **数据处理范围**  
-    - 只处理前 `20列`（由 `LB0:20` 指定）  
-    - 有效行数为 `32`（`LB1:32`）  
-    - 总列数为：`24`（`LB2:24`）
-3. **数据格式**  
-    - 使用 `16位整数`（`s16`）格式处理数据  
-    - 每个元素占2字节（影响内存布局计算）
-4. **寄存器管理**  
-    - 输入寄存器 `T#2` 添加了 `.reuse` 标记，表示**执行后保留该寄存器**  
-    - 输入寄存器 `T#1` **执行后自动释放**（无reuse标记）  
-    - 输出寄存器分配 `2KB` 空间（足够存储计算结果）
-5. **特殊处理**  
-    - 区域中**超出有效范围的部分**不初始化（`PadValue` 缺省）  
-    - 输出寄存器由硬件自动分配（`->T` 未指定具体寄存器号）
-
----
-
-## 备注
-
-此指令是TileOp模版块，软件只定义块头。
diff --git a/docs/zh/isa/header/tileblock/intro.md b/docs/zh/isa/header/tileblock/intro.md
index 590b9156..ae70dc06 100644
--- a/docs/zh/isa/header/tileblock/intro.md
+++ b/docs/zh/isa/header/tileblock/intro.md
@@ -76,7 +76,7 @@ TEPL类指令主要用于对Tile数据块进行逐元素操作、标量操作以
 | 0    | 2        | [TMUL](./TMUL.md)   | 两个Tile的逐元素乘法 |
 | 0    | 3        | [TDIV](./TDIV.md)   | 两个Tile的逐元素除法 |
 | 0    | 4        | [TREM](./TREM.md)   | 两个Tile的逐元素余数，余数符号与除数相同 |
-| 0    | 5        | [TFMOD](./TFMOD.md)  | 两个Tile的逐元素余数，余数符号与被除数相同 |
+| 0    | 5        | - | 保留/非法 |
 | 0    | 6        | [TAND](./TAND.md)   | 两个Tile的逐元素按位与 |
 | 0    | 7        | [TOR](./TOR.md)     | 两个Tile的逐元素按位或 |
 | 0    | 8        | [TXOR](./TXOR.md)   | 两个Tile的逐元素按位异或 |
@@ -95,8 +95,7 @@ TEPL类指令主要用于对Tile数据块进行逐元素操作、标量操作以
 | 0    | 21       | [TSQRT](./TSQRT.md)  | 逐元素平方根 |
 | 0    | 22       | [TRSQRT](./TRSQRT.md) | 逐元素倒数平方根 |
 | 0    | 23       | [TRELU](./TRELU.md)  | Tile的逐元素ReLU |
-| 0    | 24       | [TADDC](./TADDC.md)  | 三元逐元素加法：dst = src0 + src1 + src2 |
-| 0    | 25       | [TSUBC](./TSUBC.md)  | 三元逐元素减法：dst = src0 - src1 + src2 |
+| 0    | 24-25    | - | 保留/非法 |
 | 0    | 26       | [TSEL](./TSEL.md)   | 使用掩码Tile在两个Tile之间进行选择（逐元素选择） |
 | 0    | 27       | [TCVT](./TCVT.md)   | Tile的逐元素数据格式转换。 |
 | 0    | 28-31    | -      | 保留 |
@@ -110,7 +109,7 @@ TEPL类指令主要用于对Tile数据块进行逐元素操作、标量操作以
 | 1    | 2        | [TMULS](./TMULS.md)  | Tile与标量的逐元素乘法 |
 | 1    | 3        | [TDIVS](./TDIVS.md)  | 与标量的逐元素除法（Tile/标量或标量/Tile） |
 | 1    | 4        | [TREMS](./TREMS.md)  | 与标量的逐元素余数：remainder(src, scalar) |
-| 1    | 5        | [TFMODS](./TFMODS.md) | 与标量的逐元素余数：fmod(src, scalar) |
+| 1    | 5        | - | 保留/非法 |
 | 1    | 6        | [TANDS](./TANDS.md)  | Tile与标量的逐元素按位与 |
 | 1    | 7        | [TORS](./TORS.md)    | Tile与标量的逐元素按位或 |
 | 1    | 8        | [TXORS](./TXORS.md)  | Tile与标量的逐元素按位异或 |
@@ -119,10 +118,9 @@ TEPL类指令主要用于对Tile数据块进行逐元素操作、标量操作以
 | 1    | 11       | [TMAXS](./TMAXS.md)  | Tile与标量的逐元素最大值：max(src, scalar) |
 | 1    | 12       | [TMINS](./TMINS.md)  | Tile与标量的逐元素最小值 |
 | 1    | 13       | [TCMPS](./TCMPS.md)  | 将Tile与标量逐元素比较 |
-| 1    | 14       | [TLRELU](./TLRELU.md) | 带标量斜率的LeakyReLU |
+| 1    | 14       | - | 保留/非法 |
 | 1    | 15-23    | -      | 预留编码 |
-| 1    | 24       | [TADDSC](./TADDSC.md) | 带标量融合逐元素加法运算：dst = src0 + scalar + src1 |
-| 1    | 25       | [TSUBSC](./TSUBSC.md) | 带标量融合逐元素减法运算：dst = src0 - scalar + src1 |
+| 1    | 24-25    | - | 保留/非法 |
 | 1    | 26       | [SELS](./TSELS.md)  | 使用掩码Tile在源Tile和标量之间进行选择（源Tile逐元素选择） |
 | 1    | 27       | [TEXPANDS](./TEXPANDS.md) | 将标量广播到目标Tile中 |
 | 1    | 28-31    | -      | 预留编码 |
diff --git a/docs/zh/reference/examples/v0.57/README.md b/docs/zh/reference/examples/v0.57/README.md
index 1f400e9c..015b9ac7 100644
--- a/docs/zh/reference/examples/v0.57/README.md
+++ b/docs/zh/reference/examples/v0.57/README.md
@@ -1,25 +1,26 @@
-# 灵犀指令集汇编示例包 (v0.57)
+# LinxISA 汇编示例包（v0.57.1）
 
-灵犀指令集 v0.57 的规范公共汇编示例。
+本目录包含由锁定的 PTO ISA 0.57.1 kernel surface 生成的规范公共汇编示例。
 
-## 布局
+## 目录布局
 
-- `curated/`：审查了手工策划的示例。
-- `scratch-legacy/`：选定的迁移的暂存程序集（公共允许列表）。
-- `generated/`：从 PTO 示例生成的确定性输出。
-- `legacy-reference/`：移动历史参考示例。
-- `index.yaml`：带有出处和生成命令的清单。
+- `curated/`：经过审阅的手写标量与反汇编示例。
+- `generated/`：由 `workloads/pto_kernels/tools/examples/` 确定性生成的编译器输出。
+- `index.yaml`：精确记录源文件和工具链来源。
 
-## 规范示例
+## 规范 Tile 示例
 
 ```asm
-BSTART.TMA   TLOAD, FP16
-B.ARG        ND2ZN.normal, FP16, Null
-B.IOT       [], last ->t<4KB>
-B.IOR        [x2,a6],[]
-C.B.DIMI     64, ->lb0
-C.B.DIMI     64, ->lb1
-C.B.DIMI     64, ->lb2
+BSTART.TLOAD INT32
+B.DIM        a3, 0, ->lb0
+B.DIM        a3, 0, ->lb1
+B.DIM        a3, 0, ->lb2
+B.IOR        [a6,a7],[]
+B.IOT        last, ->t<4KB>
 ```
 
+0.57.1 示例不包含 `B.ARG`、通用 `BSTART.TMA` / `BSTART.CUBE`、
+`MAMULB` 或已删除的 D 类操作。请使用 `index.yaml` 记录的 LLVM 与
+PTO-Kernel 提交重新生成示例。
+
 来源：`docs/reference/examples/v0.57/`
diff --git a/docs/zh/translation-manifest.json b/docs/zh/translation-manifest.json
index f17a58f8..5f6df765 100644
--- a/docs/zh/translation-manifest.json
+++ b/docs/zh/translation-manifest.json
@@ -6,7 +6,7 @@
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+      "translation_sha256": "d29697df72d4049ed3ca80c8c618251d7eef7f13e90871623e6b1c677cfad9ff"
     },
     "isa/header/tileblock/TGEMVMX.ACC.md": {
       "source_sha256": "f9ba3cc142e187007e7ee09b01584c2a8b7bdf4108796152791ad1f6308b040a",
-      "translation_sha256": "0c929a21c82e14236ec4d2c76a3b213e76ac0125c5ca22f48b910fa57d5b4c76"
+      "translation_sha256": "ecbb21980780bd84230ee40aa9d0e766a620bf903fde492a4becce60e36ebb6f"
     },
     "isa/header/tileblock/TGEMVMX.BIAS.md": {
       "source_sha256": "bfa4cdb0e8d534aadfc09fae8e9085916165836fd0fbe30fb4db29a25256c585",
-      "translation_sha256": "6fb5f30caf37164d68926cbf1fc69cd02e6d24b5bc1396448d305dddc7983475"
+      "translation_sha256": "71beb287d6d36bf6570dbf55ff53c8dd85aeeb41c2a05a35ce42bdb30f5a833a"
     },
     "isa/header/tileblock/TGEMVMX.md": {
       "source_sha256": "8f3d6cd1ff2adc7118b26277d00c7d7c51c27d247c9208ec93d743c9794719d8",
-      "translation_sha256": "3a12f445d1c402f3af84ac7f5537e9c1ef8f932df539b98dca3c3fbbccb42131"
+      "translation_sha256": "79ecd02de7f0bf98223cfba6806a6ba623850a7e9a2c86a0f6f73fbde38c51df"
     },
     "isa/header/tileblock/THISTOGRAM.md": {
       "source_sha256": "2244c7d7171202d5f8a784083a9189b27e72c085bb5145724e1f6c20a8a66ddf",
@@ -1621,33 +1605,29 @@
       "source_sha256": "ef1ce35a1f216873c0644b413eaedc00856ad935aa7763099075ffd4f9565549",
       "translation_sha256": "91549bfc6f6646a7a090f96f063f43e86bb32b544f7f4afae3a41f63be9c0d8c"
     },
-    "isa/header/tileblock/TLRELU.md": {
-      "source_sha256": "64561620ed5c9fe336e5501a50a68e7ccd878992399651f40035749ae158d08b",
-      "translation_sha256": "d60717434ab59a398e393041e122449af51493b07d7f531cbe9074bdafe8f6e9"
-    },
     "isa/header/tileblock/TMATMUL.ACC.md": {
       "source_sha256": "9e98a6db94acf001e14af3273702b94345bf3b69675fdb9937de40c26f5d0e3d",
-      "translation_sha256": "7ce2da76a83214b3011e4608614ac282ee4e67f0c7461b0586608594f557dce2"
+      "translation_sha256": "b0efc6ce232495e2d09de0fcb4f14a290aa50b8cca42cdc289e1985366a5082e"
     },
     "isa/header/tileblock/TMATMUL.BIAS.md": {
       "source_sha256": "3873092f9856893231c7cf319f197da32e97fc5b024ae8e81240962160e068b6",
-      "translation_sha256": "e5ee9a1b548bf76998e684f89d8fae2b7e4ecaee4d83089898a0cea1b9f89362"
+      "translation_sha256": "6e0e0e7895d0fb0ea272965074a44d3af197c07a3cfa7f048f5a13d830fad4f7"
     },
     "isa/header/tileblock/TMATMUL.md": {
       "source_sha256": "6ad0796bb7039ca7efac4052e964e6ed758e4737a6c5d0750691581fcecede08",
-      "translation_sha256": "880516798e6bf20a5bea8cb151656dd915d5d720acd5612703ad8dc7e12cd798"
+      "translation_sha256": "fc06ffde5b1840ab927cf253d8674000f7cac07765351bea2ec9c2b2de29f671"
     },
     "isa/header/tileblock/TMATMULMX.ACC.md": {
       "source_sha256": "d45083791845b3ec346c8134f3308333f65a10a08d6659efb806ffc4891ce7f6",
-      "translation_sha256": "ad41b978aaabd3e4e1259c4679f9b9e4df1c678dcf2b90117d8c36e5e5a55db2"
+      "translation_sha256": "8701f70b507cf3c564bda86943ef94b2f57eb96ad00b0b119791fe6586572984"
     },
     "isa/header/tileblock/TMATMULMX.BIAS.md": {
       "source_sha256": "78cd548d8f73e89edeaef3e8664838d077a90b91e9dcb9fc3e25024123a2e7c5",
-      "translation_sha256": "bb3bf7cc7622e7f302d6e9643c565c33c284a17bb78b7aade56115873d04992d"
+      "translation_sha256": "bea2dd570804bee3a053940a8ab78284c6539b5b8d5ee52a6324566048b7e858"
     },
     "isa/header/tileblock/TMATMULMX.md": {
       "source_sha256": "80159fc99bd96ab06c3c64de41b9ff2cfca064ce0ffaddd6462160a287a33fef",
-      "translation_sha256": "4b6c939c6b126e99a1f9cbf9b19e7839e0c1273b069addf1ab1d36b72a3b33ee"
+      "translation_sha256": "5248eb1a6dee7bab4c7b0bf240a9f3acfee7db9f4152f09d5dccd42bf2d9d305"
     },
     "isa/header/tileblock/TMAX.md": {
       "source_sha256": "b0b4e84601217bb42b2d1d40b8993b6568f0f69f5caa85c3fcb4830aff99253c",
@@ -1707,7 +1687,7 @@
     },
     "isa/header/tileblock/TRELU.md": {
       "source_sha256": "4325562d3491dd63d76eb6fce26cc6e3a8b5640358a4a9fd54eb3d3483539c3f",
-      "translation_sha256": "645d58a207c897a3f45fede91c41f7606f3c5c706eedc465b807eef217aaf855"
+      "translation_sha256": "e4cc3c52f1ed054317ef34285103ed926914c0619570aabc9ea2923698bdf229"
     },
     "isa/header/tileblock/TREM.md": {
       "source_sha256": "08469a00d0813312b5a052295c0250ec2dc6817f7b2e7857d3307a603ebfdb0c",
@@ -1809,18 +1789,10 @@
       "source_sha256": "48d624b5e105b077d10d5fa1a3367f68c9bb9c973ee5ef3ff725570a22e0b348",
       "translation_sha256": "52ceb9f3b8916f9e77254f3a61581de80182116bd3443f16b71bd0ecd4d6b0cc"
     },
-    "isa/header/tileblock/TSUBC.md": {
-      "source_sha256": "5c9fe9d49a0357d85b4fb0beb27c5cbd9674c7b7042a17c4b682aa80c6859fb4",
-      "translation_sha256": "4ce0ebb9e1443422a5451b124d983ef831609dbe29c6dfef38c3ce5845065064"
-    },
     "isa/header/tileblock/TSUBS.md": {
       "source_sha256": "d3134f4a3865aa070f57ee26cb0aaaaea49514eeae69d9de5c4c25a5cc09444a",
       "translation_sha256": "ee9bc426f8c83f2d81714415e9750abfdb24f4e9e107a271962b380041e3c921"
     },
-    "isa/header/tileblock/TSUBSC.md": {
-      "source_sha256": "cf2a8dee8ae75ada192e570dce62adea4d272eb9bc436a5c2f59906c83540096",
-      "translation_sha256": "d81bf6878c26dc9873c01301344a45e8888edb5eec1080fb9f1f68fb1cf114f2"
-    },
     "isa/header/tileblock/TTRANS.md": {
       "source_sha256": "c80266d066f538e41ad2fb863d2ef118098a0509e26374cf352c16a5a68be80a",
       "translation_sha256": "8742f5d61d0ae6b104d95cbddd417db1ffa34b9fb3b527f981ee5bf3b307cbad"
@@ -1835,10 +1807,10 @@
     },
     "isa/header/tileblock/intro.md": {
       "source_sha256": "5439acb26ce649cc1a26066cd9113cfdb08fbcd1874661d13baa3e3f6662a254",
-      "translation_sha256": "c023a28ba0d0e108b8de9b351e8fd0c84a15ef66fa23980d49e2cd0e6a07f7e2"
+      "translation_sha256": "fe53241a09c1e2b15c5e4f609a93b52b472be2345d79db121c743df17cb80d63"
     },
     "isa/index.md": {
-      "source_sha256": "514bbb4ff0a233c803e1c52cf9d60532db4f69c50a3d67f4856cb615f5be54ca",
+      "source_sha256": "df854d4ee71e5d720f6b31b1f8e8a0ea9df09e3dae5a9ed8be1df35bfb849de4",
       "translation_sha256": "eb9d601567d2df58900caaf140764880c1e9a9bfebb05396c3f037d20615a2a9"
     },
     "isa/inst/LibPseudoCode.md": {
@@ -5117,16 +5089,12 @@
       "source_sha256": "08d9315a60377ecfef9caa57ebcb77964c43621cf588abea6853a02372df0173",
       "translation_sha256": "353e44431d52b9bcd89d233c1d3ba03f1bf54eb0051903b4a855e70bfe685c65"
     },
-    "isa/instructions/b_arg.md": {
-      "source_sha256": "c77c87ee288bbc6ac619525c2a3241e232fee36145f9e445fb50fecd742a4ae3",
-      "translation_sha256": "b2a2d6b9ae1382ac0f6594f4e235a47c017a401a51771671bc7d221631b1a76b"
-    },
     "isa/instructions/b_catr.md": {
-      "source_sha256": "fee2205eba1dbaaf7abc284a78ccbf9c7a84cbb442ac6ac7d6a895c8aeb94bd2",
+      "source_sha256": "bd37d2136238f518435d038d596989c9e6c5d767a32a9753c0bf94bb55cc9cf0",
       "translation_sha256": "c17cd5d3665f0b53266777184a2cdbbbfa01f3325c6b782db62c7d3e33db7f27"
     },
     "isa/instructions/b_datr.md": {
-      "source_sha256": "622c0669d843aaeb73ec31211d89aef6dda7884c1582a6f280ae4b02c1a2cba1",
+      "source_sha256": "51f5933d34411a3677fbec8f839473839e1608482570f1a52071a179d1773fd2",
       "translation_sha256": "649eec574b494fb1fc7386ce3543457a00e91e2c052d929f54f47b8360a405f1"
     },
     "isa/instructions/b_dim.md": {
@@ -5154,7 +5122,7 @@
       "translation_sha256": "42cc954bac30d17e6e42a0537d20f53c326e3ebe89e2256b6686306c3fc0983d"
     },
     "isa/instructions/b_iot.md": {
-      "source_sha256": "6b66d30a459d4693c51a2e15e63a66aef77c86521dc9fa27d7c1cd05f8e68a6f",
+      "source_sha256": "3366a77bcc32d335e63fa8614e9a7b50d479d2689039c2d32f5dfa52e997860c",
       "translation_sha256": "e317e87b90352342d2abe5f1bce4915c7eaabadbbbc58bcf071dc4b6170efea5"
     },
     "isa/instructions/b_lt.md": {
@@ -5210,21 +5178,13 @@
       "translation_sha256": "50fee8454fbd5ed65824b3afbd94a351b2322fd9d69cbc8319fa69c08cad5c27"
     },
     "isa/instructions/bstart_acccvt.md": {
-      "source_sha256": "adebed2a1dbe92556e7e294e33f3bc95564181322662414fe5cfa8f794699828",
+      "source_sha256": "a3a6c8f0d3cc104650eb7233d27c1f9f98d73008b7bb5e96dcc6580667254c70",
       "translation_sha256": "acb6e6a34aa6dd3314a90cc09fa80b1602b5b5a6515b24a5dffd0d28bf61bf42"
     },
     "isa/instructions/bstart_call.md": {
       "source_sha256": "430e9c1f4438cf2520f14cd6f07f860484ce487bba170ea7fcb47ea5a87305d1",
       "translation_sha256": "89157ed6b56eaa31a770bfd927f905db9dff74f765228c46987b2753f7bb6947"
     },
-    "isa/instructions/bstart_cube.md": {
-      "source_sha256": "98e36f7bb235e17f6bab08039c16b2b0ed01a540f5bf592b12f3a5e5284d1971",
-      "translation_sha256": "632fde6c288b3d226104ab0f588c4dd85c92706acbc23e0ac63e3a2cb9361124"
-    },
-    "isa/instructions/bstart_fixp.md": {
-      "source_sha256": "c76853f9ac70b6221db70551874866152cf7a90157e6f24c98ef27c9c2d4558d",
-      "translation_sha256": "e9b0d827b4ce3b55a61f9932254254c7d34e52448fa5879d6844091aae8b536d"
-    },
     "isa/instructions/bstart_fp.md": {
       "source_sha256": "6bb7010d9ddcadc3e80b1c4fc61d990dd5aeb65b804e963b56b6dcc6cb532509",
       "translation_sha256": "393ede2f366048e2602eb1130d61245682718759b4bb1cc0634c835486eaf298"
@@ -5246,19 +5206,19 @@
       "translation_sha256": "2dba59326b48caa84279b7fd63c73464b3b2678bbf0527734d7b2d8bc296fc45"
     },
     "isa/instructions/bstart_tepl.md": {
-      "source_sha256": "404931f0ca8d21cc8714a8c4a8df16220515cf879ed323b4c5ed78cd8cda7217",
+      "source_sha256": "a0297d86c198938d586c04130b0c96de9d58063c5039852d64996fbb91faa180",
       "translation_sha256": "d665fca03cd11049f371737868c68c80e6504618e6fbf84a68e9c25b710fc14e"
     },
     "isa/instructions/bstart_tload.md": {
-      "source_sha256": "92c7c08a9673d27598495cb51c6dd4ba1521906c57a7a421080c5a3b412244f7",
+      "source_sha256": "e79747da0a8763d6c1eb38f1017026276d0133bd95f6ea1eef6197f469bc9248",
       "translation_sha256": "ffc84bcf31f7391963e516583e11f9dd5f476f5744a378a5bc9745c694fe28c4"
     },
     "isa/instructions/bstart_tmatmul.md": {
-      "source_sha256": "9a7c2c4151c382305a957da4787df21eb63c17997d4b2f87c42c56a9a1e2caed",
+      "source_sha256": "599aacd1c1346c2beb1f118064d39b139ce4c40923f3efbb475c791dc4873d4f",
       "translation_sha256": "717e1f7a91da06221ef89b4096b07c1532c69dc0e408f6eccbed1d83626fc2d5"
     },
     "isa/instructions/bstart_tmatmul_acc.md": {
-      "source_sha256": "46674d8307c1f6e6a99d6dd24d85d867cb6e2d9a54834240de7c21619abcd7ea",
+      "source_sha256": "4a1c242a210a9f334e51ef5e3026b2c89857784e085f3a992b84045916dbf16a",
       "translation_sha256": "946515dc3d4ef4cd323b5c4179c5ff2213d48a8916bc8a38f1df2618c72a42e2"
     },
     "isa/instructions/bstart_tmov.md": {
@@ -5266,7 +5226,7 @@
       "translation_sha256": "cb630e7053f1caab70b546661cce96dea283662e1cf512315759122840b5f34e"
     },
     "isa/instructions/bstart_tstore.md": {
-      "source_sha256": "83fb29903e7812d943450a414f84cc5bf4e76eef0ee21e8580259e7e8fb22d62",
+      "source_sha256": "fb39d5270057fa51a086c208c581186a0940ef5eb782d71725ff693df190f7e6",
       "translation_sha256": "bda865ecdedc122e6365d734c53820dd8b117512dcb13b1ef0f9206e4e2805fc"
     },
     "isa/instructions/bstart_vpar.md": {
@@ -6510,7 +6470,7 @@
       "translation_sha256": "77a2c05e2e1a76c24bf10a9e9973947d6f087fad502c009c39deceef1d8265d2"
     },
     "isa/instructions/index.md": {
-      "source_sha256": "e8cd5661f825d380106da6f2743b021ccc46a58d1a82bcb7d9cf09b8079e7c75",
+      "source_sha256": "3bfd52b2387da3fbe37ab544bca5c6b8387037eda6f3315dc70df144f1a13bba",
       "translation_sha256": "e431843538eea1226c59c05a0d6fd7582635b1f1e8355ceff6539611a7485ab4"
     },
     "isa/instructions/j.md": {
@@ -8290,15 +8250,15 @@
       "translation_sha256": "4a569eecd6cba6e6c07ceef24d01c99b6ed674fd47bf75b0403780eb9c6170ce"
     },
     "reference/examples/v0.57/README.md": {
-      "source_sha256": "6af9b29de494a86198ea7920c599e529ab75bacf3a55e0693efd6eff3be9064f",
-      "translation_sha256": "436887e9cbcc51bb31e279b091458ef03b7f4a658a836a8e01af86f1e193fefc"
+      "source_sha256": "a04d1ce8c95b2e58dbbd75711b4ba362e5f108a93a711cea4d90ebdcb0eecc78",
+      "translation_sha256": "2e2b179a7427714d03d3d6753ae47e50c25f9b3757937ba3d7a093ccdb319e63"
     },
     "reference/linxisa-assembly-agent-guide.md": {
       "source_sha256": "f3b54b7534aaadc115c309055c23852f890387e14ae60fd6d9be980eae84bb4d",
       "translation_sha256": "4fe65229d8c39b98fa17f905906bfdf0c712cc91fcebd3e2b50582acae7f600f"
     },
     "reference/linxisa-call-ret-contract.md": {
-      "source_sha256": "5d9506e49e92f952b1e3f78b7b39273a9d335127df8eea95c46c2fca66fcccb6",
+      "source_sha256": "07facc4e7e325fda578a37b20910c8bce09e7dbda52e72987c4dd1abbdc4a395",
       "translation_sha256": "807d7a0a5f8b1e66436a6344fbe03b1ea608a18551fda4963654919c755dfe44"
     },
     "releases/v0.3.0.md": {
@@ -8395,7 +8355,10 @@
     "isa/header/B.CACR.md",
     "isa/header/B.NEXT.md",
     "isa/header/tileblock/ERCOV.md",
-    "isa/header/tileblock/ESAVE.md"
+    "isa/header/tileblock/ESAVE.md",
+    "isa/instructions/b_arg.md",
+    "isa/instructions/bstart_cube.md",
+    "isa/instructions/bstart_fixp.md"
   ],
   "validation": {
     "forbidden_placeholder_pattern": "ZXTER[M]EN",
diff --git a/emulator/qemu b/emulator/qemu
index c9f9570a..cfc253e8 160000
--- a/emulator/qemu
+++ b/emulator/qemu
@@ -1 +1 @@
-Subproject commit c9f9570aa70da7e193ff8857bd9bde2cf052e546
+Subproject commit cfc253e844f4b0d017b2190a025c4375771f899a
diff --git a/isa/generated/codecs/linxisa32.decode b/isa/generated/codecs/linxisa32.decode
index 236aa721..d4b484d8 100644
--- a/isa/generated/codecs/linxisa32.decode
+++ b/isa/generated/codecs/linxisa32.decode
@@ -4,24 +4,25 @@
 # Fields
 %ACR_ID 15:10
 %B_E 15:1
-%CMode 25:3
+%CMode 29:3
 %CROSS_BID 25:7
+%Canonicalize 25:1
 %DR 26:1
-%DataLayout 7:5
 %DataType_20_5 20:5
 %DataType_27_5 27:5
 %DstBegin 15:5
 %DstEnd 20:5
-%DstTile 22:3
+%DstTile 7:3
 %DstType 27:5
 %Function 20:5
-%L 29:1
+%L 19:1
 %LSR_ID 20:12
 %L_UL 16:1
+%Layout 7:5
 %Mode 25:2
 %PRED_IMM 24:4
-%PadValue 15:5
-%RMode 28:3
+%PadValueOrByteId 27:2
+%RMode 15:3
 %RRA_Type 20:4
 %RST_Type 20:4
 %RegDst 7:5
@@ -29,11 +30,11 @@
 %RegSrc0 15:5
 %RegSrc1 20:5
 %RegSrc2 27:5
-%S0R 30:1
-%S1R 31:1
+%S0R 10:1
+%S1R 11:1
 %SSR_ID 20:12
 %SUCC_IMM 20:4
-%Sat 31:1
+%Sat 26:1
 %SrcA 27:5
 %SrcBegin 15:5
 %SrcD 27:5
@@ -42,26 +43,25 @@
 %SrcP 27:5
 %SrcR 20:5
 %SrcRType 25:2
-%SrcTile0 15:1 7:5
-%SrcTile1 16:6
+%SrcTile0 20:6
+%SrcTile1 26:6
 %SrcType 25:2
 %SrcZero 20:5
-%TileOpcode 15:10
 %V 15:1
+%aq_16_1 16:1
 %aq_26_1 26:1
-%aq_29_1 29:1
-%atom 30:1
-%far 27:1
-%format 7:5
+%atom 17:1
+%far_18_1 18:1
+%far_27_1 27:1
 %imm20 12:20
+%imm4_15_4 15:4
 %imm4_24_4 24:4
-%imm4_25_4 25:4
 %imml 20:6
 %immr 26:6
 %imms 26:6
 %prefetch_size 20:12
+%rl_15_1 15:1
 %rl_25_1 25:1
-%rl_28_1 28:1
 %shamt_20_5 20:5
 %shamt_20_6 20:6
 %shamt_27_5 27:5
@@ -74,7 +74,7 @@
 %simm22 7:s5 15:17
 %simm25 7:s25
 %temp 17:2
-%trap 31:1
+%trap 19:1
 %uimm 7:5 25:7
 %uimm12 20:12
 %uimm17 7:5 20:12
@@ -117,977 +117,953 @@ andw_32_6907ed7cec90 .... .... .... .... .010 .... .010 0101 %RegDst %SrcL %SrcR
 # ASSERT | assert SrcL | opcodes/lx_32.opc:22
 assert_32_f05d67874ae5 0000 0000 0000 .... .001 0000 0010 1011 %SrcL
 
-# B.ARG | B.ARG NORM.normal | opcodes/lx_32.opc:30
-b_arg_32_374ec956affe 0000 0000 0000 1111 1010 0000 0010 0011
-
-# B.ARG | B.ARG format | opcodes/lx_32.opc:25
-b_arg_32_47e8ac50ac96 0000 0000 0000 0000 0011 .... .100 0011 %format
-
-# B.ARG | B.ARG NZ2DN.canon | opcodes/lx_32.opc:29
-b_arg_32_5c8bfa662370 0000 0010 0000 1111 1010 1110 0010 0011
-
-# B.ARG | B.ARG ND2ZN.normal, FP16, Null | opcodes/lx_32.opc:26
-b_arg_32_95152c29a268 0001 1000 0000 0010 0010 0001 1010 0011
-
-# B.ARG | B.ARG DN2ZN.normal, FP16, Null | opcodes/lx_32.opc:28
-b_arg_32_c6d5c49a4ad7 0001 1000 0000 0010 0010 0100 0010 0011
-
-# B.ARG | B.ARG DN2NZ.normal, FP32, Null | opcodes/lx_32.opc:27
-b_arg_32_f19d18f2126b 0001 1000 0000 0000 1010 0100 1010 0011
-
 # B.CATR | B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr} | opcodes/lx_32.opc:23
-b_catr_32_e90bd52fa480 .... ..00 0000 0000 0000 0000 0010 0011 %DR aq=%aq_29_1 %atom %far rl=%rl_28_1 %trap
+b_catr_32_8f94bdb16d29 0000 0.00 0000 .... .000 0000 0010 0011 %DR aq=%aq_16_1 %atom far=%far_18_1 rl=%rl_15_1 %trap
 
-# B.DATR | B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat} | opcodes/lx_32.opc:24
-b_datr_32_c161a042ff38 .... .... .... .... .001 .... .010 0011 %CMode %DataLayout DataType=%DataType_20_5 %PadValue %RMode %Sat
+# B.DATR | B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize} | opcodes/lx_32.opc:24
+b_datr_32_840f4b8d579d .... .... .... 00.. .001 .... .010 0011 %CMode %Canonicalize DataType=%DataType_20_5 %Layout %PadValueOrByteId %RMode %Sat
 
-# B.DIM | B.DIM RegSrc, uimm, ->LB2 | opcodes/lx_32.opc:31
+# B.DIM | B.DIM RegSrc, uimm, ->LB2 | opcodes/lx_32.opc:25
 b_dim_32_1caa1aa2944a .... .... .... .... .010 .... .100 0011 %RegSrc %uimm17
 
-# B.DIM | B.DIM RegSrc, uimm, ->LB0 | opcodes/lx_32.opc:32
+# B.DIM | B.DIM RegSrc, uimm, ->LB0 | opcodes/lx_32.opc:26
 b_dim_32_27602ab68929 .... .... .... .... .000 .... .100 0011 %RegSrc %uimm17
 
-# B.DIM | B.DIM RegSrc, uimm, ->LB1 | opcodes/lx_32.opc:33
+# B.DIM | B.DIM RegSrc, uimm, ->LB1 | opcodes/lx_32.opc:27
 b_dim_32_4191099a5f4d .... .... .... .... .001 .... .100 0011 %RegSrc %uimm17
 
-# B.EQ | b.eq SrcL, SrcR, label | opcodes/lx_32.opc:34
+# B.EQ | b.eq SrcL, SrcR, label | opcodes/lx_32.opc:28
 b_eq_32_41f00e5abd89 .... .... .... .... .000 .... .010 0111 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# B.GE | b.ge SrcL, SrcR, label | opcodes/lx_32.opc:35
+# B.GE | b.ge SrcL, SrcR, label | opcodes/lx_32.opc:29
 b_ge_32_7bd9050705dc .... .... .... .... .011 .... .010 0111 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# B.GEU | b.geu SrcL, SrcR, label | opcodes/lx_32.opc:36
+# B.GEU | b.geu SrcL, SrcR, label | opcodes/lx_32.opc:30
 b_geu_32_43a6e57dce55 .... .... .... .... .101 .... .010 0111 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# B.HINT | B.HINT {BR.{likely, unlikely}, TEMP.{hot, warm, cool, none}, PRFSIZE} | opcodes/lx_32.opc:37
+# B.HINT | B.HINT {BR.{likely, unlikely}, TEMP.{hot, warm, cool, none}, PRFSIZE} | opcodes/lx_32.opc:31
 b_hint_32_69d942ff1583 .... .... .... 0... .000 0000 0011 0011 %L_UL %V %prefetch_size %temp
 
-# B.HINT | B.HINT TRACE.{begin, end} | opcodes/lx_32.opc:38
+# B.HINT | B.HINT TRACE.{begin, end} | opcodes/lx_32.opc:32
 b_hint_32_f7d01d734925 0000 0000 0000 0000 .001 0000 0011 0011 %B_E
 
-# B.IOR | B.IOR [RegSrc0, RegSrc1, RegSrc2],[RegDst] | opcodes/lx_32.opc:39
+# B.IOR | B.IOR [RegSrc0, RegSrc1, RegSrc2],[RegDst] | opcodes/lx_32.opc:33
 b_ior_32_c3ea71404eb3 .... .00. .... .... .000 .... .001 0011 %RegDst %RegSrc0 %RegSrc1 %RegSrc2
 
-# B.IOT | B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size> | opcodes/lx_32.opc:41
-b_iot_32_10db6db84f5d 0... .... ..00 0000 .101 .... .001 0011 %DstTile %L %S0R %SrcTile0 imm4=%imm4_25_4
+# B.IOT | B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size> | opcodes/lx_32.opc:35
+b_iot_32_0f23e46d6176 0000 00.. .... .... .101 0... .001 0011 %DstTile %L %S0R %SrcTile0 imm4=%imm4_15_4
 
-# B.IOT | B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last> | opcodes/lx_32.opc:43
-b_iot_32_2c07e7177fad ...0 0001 11.. .... .100 .... .001 0011 %L %S0R %S1R %SrcTile0 %SrcTile1
+# B.IOT | B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size> | opcodes/lx_32.opc:34
+b_iot_32_3a6945dec034 .... .... .... .... .100 .... .001 0011 %DstTile %L %S0R %S1R %SrcTile0 %SrcTile1 imm4=%imm4_15_4
 
-# B.IOT | B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size> | opcodes/lx_32.opc:40
-b_iot_32_8b8bce6bffe8 .... .... .... .... .100 .... .001 0011 %DstTile %L %S0R %S1R %SrcTile0 %SrcTile1 imm4=%imm4_25_4
+# B.IOT | B.IOT SrcTile0<.reuse>, <last> | opcodes/lx_32.opc:38
+b_iot_32_778f84340400 0000 00.. .... .000 0101 0.00 0001 0011 %L %S0R %SrcTile0
 
-# B.IOT | B.IOT SrcTile0<.reuse>, <last> | opcodes/lx_32.opc:44
-b_iot_32_c11eb189dd83 0..0 0001 1100 0000 .101 .... .001 0011 %L %S0R %SrcTile0
+# B.IOT | B.IOT <last>, ->DstTile<Size> | opcodes/lx_32.opc:36
+b_iot_32_a06b9b6c1965 0000 0000 0000 .... .110 00.. .001 0011 %DstTile %L imm4=%imm4_15_4
 
-# B.IOT | B.IOT <last>, ->DstTile<Size> | opcodes/lx_32.opc:42
-b_iot_32_efa0fe3fe49a 00.. .... ..00 0000 0110 0000 0001 0011 %DstTile %L imm4=%imm4_25_4
+# B.IOT | B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last> | opcodes/lx_32.opc:37
+b_iot_32_f1ca66bbcce1 .... .... .... .000 0100 ..00 0001 0011 %L %S0R %S1R %SrcTile0 %SrcTile1
 
-# B.LT | b.lt SrcL, SrcR, label | opcodes/lx_32.opc:45
+# B.LT | b.lt SrcL, SrcR, label | opcodes/lx_32.opc:39
 b_lt_32_2ca5ecd25cfb .... .... .... .... .010 .... .010 0111 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# B.LTU | b.ltu SrcL, SrcR, label | opcodes/lx_32.opc:46
+# B.LTU | b.ltu SrcL, SrcR, label | opcodes/lx_32.opc:40
 b_ltu_32_f1ea7ad44e37 .... .... .... .... .100 .... .010 0111 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# B.NE | b.ne SrcL, SrcR, label | opcodes/lx_32.opc:47
+# B.NE | b.ne SrcL, SrcR, label | opcodes/lx_32.opc:41
 b_ne_32_831af6a36ff4 .... .... .... .... .001 .... .010 0111 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# B.NZ | b.nz label | opcodes/lx_32.opc:48
+# B.NZ | b.nz label | opcodes/lx_32.opc:42
 b_nz_32_0f583cdd8d4d .... .... .... .... .010 .... .011 0111 %simm22
 
-# B.TEXT | B.TEXT <label> | opcodes/lx_32.opc:49
+# B.TEXT | B.TEXT <label> | opcodes/lx_32.opc:43
 b_text_32_1ce09f50e5dd .... .... .... .... .... .... .000 0011 %simm25
 
-# B.Z | b.z label | opcodes/lx_32.opc:50
+# B.Z | b.z label | opcodes/lx_32.opc:44
 b_z_32_753dd3b4fcb6 .... .... .... .... .001 .... .011 0111 %simm22
 
-# BC.IALL | bc.iall | opcodes/lx_32.opc:51
+# BC.IALL | bc.iall | opcodes/lx_32.opc:45
 bc_iall_32_fdceb48516a8 0000 0000 0001 0000 0100 0000 0010 1011
 
-# BC.IVA | bc.iva SrcL | opcodes/lx_32.opc:52
+# BC.IVA | bc.iva SrcL | opcodes/lx_32.opc:46
 bc_iva_32_c166de534c98 0000 0000 0000 .... .100 0000 0010 1011 %SrcL
 
-# BCNT | bcnt srcL,  M, N, ->{t, u, Rd} | opcodes/lx_32.opc:53
+# BCNT | bcnt srcL,  M, N, ->{t, u, Rd} | opcodes/lx_32.opc:47
 bcnt_32_e0b06e436a5b .... .... .... .... .110 .... .110 0111 %RegDst %SrcL %imml %imms
 
-# BIC | bic SrcL, M, N, ->{t, u, Rd} | opcodes/lx_32.opc:54
+# BIC | bic SrcL, M, N, ->{t, u, Rd} | opcodes/lx_32.opc:48
 bic_32_3a10830a3a93 .... .... .... .... .010 .... .110 0111 %RegDst %SrcL %imml %imms
 
-# BIS | bis SrcL, M, N, ->{t, u, Rd} | opcodes/lx_32.opc:55
+# BIS | bis SrcL, M, N, ->{t, u, Rd} | opcodes/lx_32.opc:49
 bis_32_bca5d1a80f32 .... .... .... .... .011 .... .110 0111 %RegDst %SrcL %imml %imms
 
-# BSE | bse SrcL | opcodes/lx_32.opc:56
+# BSE | bse SrcL | opcodes/lx_32.opc:50
 bse_32_883b5167edbc 0000 0000 0000 .... .000 0000 0010 1011 %SrcL
 
-# BSTART | BSTART {DIRECT, CALL}, <label> | opcodes/lx_32.opc:57
+# BSTART | BSTART {DIRECT, CALL}, <label> | opcodes/lx_32.opc:51
 bstart_32_7eb93b649748 .... .... .... .... .... .... .001 0001 %simm25
 
-# BSTART | BSTART COND, <label> | opcodes/lx_32.opc:58
+# BSTART | BSTART COND, <label> | opcodes/lx_32.opc:52
 bstart_32_e11e678a32ac .... .... .... .... .... .... .010 0001 %simm25
 
-# BSTART CALL | BSTART.CALL <br_label>, <rt_label>, ->ra | opcodes/lx_32.opc:59
+# BSTART CALL | BSTART.CALL <br_label>, <rt_label>, ->ra | opcodes/lx_32.opc:53
 bstart_call_32_9404418d1ae5 0101 0... ..01 0110 .... .... .... 0010 simm12=%simm12_4_s12 %uimm5
 
-# BSTART.ACCCVT | BSTART.ACCCVT DataType | opcodes/lx_32.opc:66
+# BSTART.ACCCVT | BSTART.ACCCVT DataType | opcodes/lx_32.opc:60
 bstart_acccvt_32_56c3ce3838c5 .... .000 1000 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.CUBE | BSTART.CUBE Function, DataType | opcodes/lx_32.opc:67
-bstart_cube_32_bd3f337acb9d .... .00. .... 0011 0001 0001 1000 0001 DataType=%DataType_27_5 %Function
-
-# BSTART.FIXP | BSTART.FIXP TileOp, DataType | opcodes/lx_32.opc:68
-bstart_fixp_32_3b0ae11126a6 .... .00. .... 0011 1001 0001 1000 0001 DataType=%DataType_27_5 %Function
-
-# BSTART.FP | BSTART.FP RET | opcodes/lx_32.opc:69
+# BSTART.FP | BSTART.FP RET | opcodes/lx_32.opc:61
 bstart_fp_32_0c671a644214 0000 0000 0000 0000 0111 0001 0000 0001
 
-# BSTART.FP | BSTART.FP ICALL | opcodes/lx_32.opc:73
+# BSTART.FP | BSTART.FP ICALL | opcodes/lx_32.opc:65
 bstart_fp_32_24db3966d6ba 0000 0000 0000 0000 0110 0001 0000 0001
 
-# BSTART.FP | BSTART.FP COND, <label> | opcodes/lx_32.opc:71
+# BSTART.FP | BSTART.FP COND, <label> | opcodes/lx_32.opc:63
 bstart_fp_32_58ad7954fb49 .... .... .... .... .011 0001 0000 0001 %simm17
 
-# BSTART.FP | BSTART.FP IND | opcodes/lx_32.opc:70
+# BSTART.FP | BSTART.FP IND | opcodes/lx_32.opc:62
 bstart_fp_32_7978795a29a1 0000 0000 0000 0000 0101 0001 0000 0001
 
-# BSTART.FP | BSTART.FP DIRECT, <label> | opcodes/lx_32.opc:72
+# BSTART.FP | BSTART.FP DIRECT, <label> | opcodes/lx_32.opc:64
 bstart_fp_32_d00a708a81f0 .... .... .... .... .010 0001 0000 0001 %simm17
 
-# BSTART.FP | BSTART.FP CALL, <label> | opcodes/lx_32.opc:74
+# BSTART.FP | BSTART.FP CALL, <label> | opcodes/lx_32.opc:66
 bstart_fp_32_dd7bc8dd694c .... .... .... .... .100 0001 0000 0001 %simm17
 
-# BSTART.FP | BSTART.FP FALL<, fixup_label> | opcodes/lx_32.opc:75
+# BSTART.FP | BSTART.FP FALL<, fixup_label> | opcodes/lx_32.opc:67
 bstart_fp_32_face4f238d84 .... .... .... .... .001 0001 0000 0001 %simm17
 
-# BSTART.MGATHER | BSTART.MGATHER DataType | opcodes/lx_32.opc:89
+# BSTART.MGATHER | BSTART.MGATHER DataType | opcodes/lx_32.opc:81
 bstart_mgather_32_c9defbf18276 .... .000 0100 0001 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.MGATHER.CAS | BSTART.MGATHER.CAS DataType | opcodes/lx_32.opc:90
+# BSTART.MGATHER.CAS | BSTART.MGATHER.CAS DataType | opcodes/lx_32.opc:82
 bstart_mgather_cas_32_fd8c8a3b720a .... .000 1000 0001 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.MGATHER.MASK | BSTART.MGATHER.MASK DataType | opcodes/lx_32.opc:91
+# BSTART.MGATHER.MASK | BSTART.MGATHER.MASK DataType | opcodes/lx_32.opc:83
 bstart_mgather_mask_32_5573241cd944 .... .000 0110 0001 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.MPAR | BSTART.MPAR <VS8, VS16> | opcodes/lx_32.opc:76
+# BSTART.MPAR | BSTART.MPAR <VS8, VS16> | opcodes/lx_32.opc:68
 bstart_mpar_32_2d163417c615 0000 0..0 0000 0000 0001 0001 1000 0001 %Mode
 
-# BSTART.MSCATTER | BSTART.MSCATTER DataType | opcodes/lx_32.opc:92
+# BSTART.MSCATTER | BSTART.MSCATTER DataType | opcodes/lx_32.opc:84
 bstart_mscatter_32_0f0ba08bd798 .... .000 0101 0001 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.MSCATTER.MASK | BSTART.MSCATTER.MASK DataType | opcodes/lx_32.opc:93
+# BSTART.MSCATTER.MASK | BSTART.MSCATTER.MASK DataType | opcodes/lx_32.opc:85
 bstart_mscatter_mask_32_2a33eed646f7 .... .000 0111 0001 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.MSEQ | BSTART.MSEQ <VS8, VS16> | opcodes/lx_32.opc:77
+# BSTART.MSEQ | BSTART.MSEQ <VS8, VS16> | opcodes/lx_32.opc:69
 bstart_mseq_32_39343a456ec5 0000 0..0 0000 0000 1001 0001 1000 0001 %Mode
 
-# BSTART.STD | BSTART.STD COND, <label> | opcodes/lx_32.opc:78
+# BSTART.STD | BSTART.STD COND, <label> | opcodes/lx_32.opc:70
 bstart_std_32_1ef99c4cedcb .... .... .... .... .011 0000 0000 0001 %simm17
 
-# BSTART.STD | BSTART.STD ICALL | opcodes/lx_32.opc:81
+# BSTART.STD | BSTART.STD ICALL | opcodes/lx_32.opc:73
 bstart_std_32_3f6980d013f7 0000 0000 0000 0000 0110 0000 0000 0001
 
-# BSTART.STD | BSTART.STD FALL<, fixup_label> | opcodes/lx_32.opc:80
+# BSTART.STD | BSTART.STD FALL<, fixup_label> | opcodes/lx_32.opc:72
 bstart_std_32_441ad677fffe .... .... .... .... .001 0000 0000 0001 %simm17
 
-# BSTART.STD | BSTART.STD RET | opcodes/lx_32.opc:79
+# BSTART.STD | BSTART.STD RET | opcodes/lx_32.opc:71
 bstart_std_32_816dfa76cc4a 0000 0000 0000 0000 0111 0000 0000 0001
 
-# BSTART.STD | BSTART.STD IND | opcodes/lx_32.opc:83
+# BSTART.STD | BSTART.STD IND | opcodes/lx_32.opc:75
 bstart_std_32_986b7ee2cf6a 0000 0000 0000 0000 0101 0000 0000 0001
 
-# BSTART.STD | BSTART.STD CALL, <label> | opcodes/lx_32.opc:82
+# BSTART.STD | BSTART.STD CALL, <label> | opcodes/lx_32.opc:74
 bstart_std_32_b05390d367cf .... .... .... .... .100 0000 0000 0001 %simm17
 
-# BSTART.STD | BSTART.STD DIRECT, <label> | opcodes/lx_32.opc:84
+# BSTART.STD | BSTART.STD DIRECT, <label> | opcodes/lx_32.opc:76
 bstart_std_32_c1de85e06878 .... .... .... .... .010 0000 0000 0001 %simm17
 
-# BSTART.SYS | BSTART.SYS FALL<, fixup_label> | opcodes/lx_32.opc:85
+# BSTART.SYS | BSTART.SYS FALL<, fixup_label> | opcodes/lx_32.opc:77
 bstart_sys_32_762d9d84a6d8 .... .... .... .... .001 0000 1000 0001 %simm17
 
-# BSTART.TEPL | BSTART.TEPL TileOpcode, DataType | opcodes/lx_32.opc:86
-bstart_tepl_32_d022db6dacb3 .... .01. .... .... .001 0001 1000 0001 DataType=%DataType_27_5 %TileOpcode
+# BSTART.TEPL | BSTART.TEPL Mode, Function, DataType | opcodes/lx_32.opc:78
+bstart_tepl_32_bff5143d4fe3 .... .... .... 0001 1001 0001 1000 0001 DataType=%DataType_27_5 %Function %Mode
 
-# BSTART.TGEMV | BSTART.TGEMV DataType | opcodes/lx_32.opc:100
+# BSTART.TGEMV | BSTART.TGEMV DataType | opcodes/lx_32.opc:92
 bstart_tgemv_32_ae19f5b678f5 .... .001 0000 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TGEMV.ACC | BSTART.TGEMV.ACC DataType | opcodes/lx_32.opc:102
+# BSTART.TGEMV.ACC | BSTART.TGEMV.ACC DataType | opcodes/lx_32.opc:94
 bstart_tgemv_acc_32_9a471b21913e .... .001 0010 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TGEMV.BIAS | BSTART.TGEMV.BIAS DataType | opcodes/lx_32.opc:101
+# BSTART.TGEMV.BIAS | BSTART.TGEMV.BIAS DataType | opcodes/lx_32.opc:93
 bstart_tgemv_bias_32_186ee96c0a8b .... .001 0001 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TGEMVMX | BSTART.TGEMVMX DataType | opcodes/lx_32.opc:103
+# BSTART.TGEMVMX | BSTART.TGEMVMX DataType | opcodes/lx_32.opc:95
 bstart_tgemvmx_32_ae5e005f6589 .... .001 0100 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TGEMVMX.ACC | BSTART.TGEMVMX.ACC DataType | opcodes/lx_32.opc:105
+# BSTART.TGEMVMX.ACC | BSTART.TGEMVMX.ACC DataType | opcodes/lx_32.opc:97
 bstart_tgemvmx_acc_32_368647b04bb0 .... .001 0110 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TGEMVMX.BIAS | BSTART.TGEMVMX.BIAS DataType | opcodes/lx_32.opc:104
+# BSTART.TGEMVMX.BIAS | BSTART.TGEMVMX.BIAS DataType | opcodes/lx_32.opc:96
 bstart_tgemvmx_bias_32_d23011f15171 .... .001 0101 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TLOAD | BSTART.TLOAD DataType | opcodes/lx_32.opc:87
+# BSTART.TLOAD | BSTART.TLOAD DataType | opcodes/lx_32.opc:79
 bstart_tload_32_d0c18bb0ab15 .... .000 0000 0001 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TMATMUL | BSTART.TMATMUL DataType | opcodes/lx_32.opc:94
+# BSTART.TMATMUL | BSTART.TMATMUL DataType | opcodes/lx_32.opc:86
 bstart_tmatmul_32_f9da70e4e0ad .... .000 0000 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TMATMUL.ACC | BSTART.TMATMUL.ACC DataType | opcodes/lx_32.opc:96
+# BSTART.TMATMUL.ACC | BSTART.TMATMUL.ACC DataType | opcodes/lx_32.opc:88
 bstart_tmatmul_acc_32_0c8c62e5f00a .... .000 0010 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TMATMUL.BIAS | BSTART.TMATMUL.BIAS DataType | opcodes/lx_32.opc:95
+# BSTART.TMATMUL.BIAS | BSTART.TMATMUL.BIAS DataType | opcodes/lx_32.opc:87
 bstart_tmatmul_bias_32_4d5a498d12f3 .... .000 0001 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TMATMULMX | BSTART.TMATMULMX DataType | opcodes/lx_32.opc:97
+# BSTART.TMATMULMX | BSTART.TMATMULMX DataType | opcodes/lx_32.opc:89
 bstart_tmatmulmx_32_e26cb3874648 .... .000 0100 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TMATMULMX.ACC | BSTART.TMATMULMX.ACC DataType | opcodes/lx_32.opc:99
+# BSTART.TMATMULMX.ACC | BSTART.TMATMULMX.ACC DataType | opcodes/lx_32.opc:91
 bstart_tmatmulmx_acc_32_70fa59b0ab4c .... .000 0110 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TMATMULMX.BIAS | BSTART.TMATMULMX.BIAS DataType | opcodes/lx_32.opc:98
+# BSTART.TMATMULMX.BIAS | BSTART.TMATMULMX.BIAS DataType | opcodes/lx_32.opc:90
 bstart_tmatmulmx_bias_32_098c7efa51b0 .... .000 0101 0011 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TMOV | BSTART.TMOV DataType | opcodes/lx_32.opc:106
+# BSTART.TMOV | BSTART.TMOV DataType | opcodes/lx_32.opc:98
 bstart_tmov_32_211446509efb .... .000 0010 0001 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TPREFETCH | BSTART.TPREFETCH DataType | opcodes/lx_32.opc:107
+# BSTART.TPREFETCH | BSTART.TPREFETCH DataType | opcodes/lx_32.opc:99
 bstart_tprefetch_32_d5f83e5aadf6 .... .000 0011 0001 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.TSTORE | BSTART.TSTORE DataType | opcodes/lx_32.opc:108
+# BSTART.TSTORE | BSTART.TSTORE DataType | opcodes/lx_32.opc:100
 bstart_tstore_32_4048b6e8b0f4 .... .000 0001 0001 0001 0001 1000 0001 DataType=%DataType_27_5
 
-# BSTART.VPAR | BSTART.VPAR <VS8, VS16> | opcodes/lx_32.opc:109
+# BSTART.VPAR | BSTART.VPAR <VS8, VS16> | opcodes/lx_32.opc:101
 bstart_vpar_32_8998d3fa51f8 0000 0..0 0000 0010 0001 0001 1000 0001 %Mode
 
-# BSTART.VSEQ | BSTART.VSEQ <VS8, VS16> | opcodes/lx_32.opc:110
+# BSTART.VSEQ | BSTART.VSEQ <VS8, VS16> | opcodes/lx_32.opc:102
 bstart_vseq_32_9324064902ae 0000 0..0 0000 0010 1001 0001 1000 0001 %Mode
 
-# BSTOP | BSTOP | opcodes/lx_32.opc:111
+# BSTOP | BSTOP | opcodes/lx_32.opc:103
 bstop_32_d25b09fdd59c 0000 0000 0000 0000 0000 0000 0000 0001
 
-# BWE | bwe SrcL | opcodes/lx_32.opc:112
+# BWE | bwe SrcL | opcodes/lx_32.opc:104
 bwe_32_e5a5240bdf9b 0000 0000 0001 .... .000 0000 0010 1011 %SrcL
 
-# BWI | bwi SrcL | opcodes/lx_32.opc:113
+# BWI | bwi SrcL | opcodes/lx_32.opc:105
 bwi_32_d9a0905cb31b 0000 0000 0010 .... .000 0000 0010 1011 %SrcL
 
-# BWT | bwt SrcL | opcodes/lx_32.opc:114
+# BWT | bwt SrcL | opcodes/lx_32.opc:106
 bwt_32_5a0fe4a8e61f 0000 0000 0011 .... .000 0000 0010 1011 %SrcL
 
-# BXS | bxs SrcL, M, N, ->{t, u, Rd} | opcodes/lx_32.opc:115
+# BXS | bxs SrcL, M, N, ->{t, u, Rd} | opcodes/lx_32.opc:107
 bxs_32_b1bb003c1703 .... .... .... .... .000 .... .110 0111 %RegDst %SrcL %imml %imms
 
-# BXU | bxu SrcL, M, N, ->{t, u, Rd} | opcodes/lx_32.opc:116
+# BXU | bxu SrcL, M, N, ->{t, u, Rd} | opcodes/lx_32.opc:108
 bxu_32_e9ea9715ba62 .... .... .... .... .001 .... .110 0111 %RegDst %SrcL %imml %imms
 
-# CASB | casb<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:117
+# CASB | casb<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:109
 casb_32_7e529b871832 .... .... .... .... .000 .... .001 1011 %RegDst %SrcD %SrcL %SrcR aq=%aq_26_1 rl=%rl_25_1
 
-# CASD | casd<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:118
+# CASD | casd<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:110
 casd_32_5852c57277a6 .... .... .... .... .011 .... .001 1011 %RegDst %SrcD %SrcL %SrcR aq=%aq_26_1 rl=%rl_25_1
 
-# CASH | cash<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:119
+# CASH | cash<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:111
 cash_32_cb1315ff6cb5 .... .... .... .... .001 .... .001 1011 %RegDst %SrcD %SrcL %SrcR aq=%aq_26_1 rl=%rl_25_1
 
-# CASW | casw<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:120
+# CASW | casw<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:112
 casw_32_cb29e4287223 .... .... .... .... .010 .... .001 1011 %RegDst %SrcD %SrcL %SrcR aq=%aq_26_1 rl=%rl_25_1
 
-# CLZ | clz SrcL,  M, N, ->{t, u, Rd} | opcodes/lx_32.opc:121
+# CLZ | clz SrcL,  M, N, ->{t, u, Rd} | opcodes/lx_32.opc:113
 clz_32_f890415c15b6 .... .... .... .... .101 .... .110 0111 %RegDst %SrcL %imml %imms
 
-# CMP.AND | cmp.and SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd} | opcodes/lx_32.opc:122
+# CMP.AND | cmp.and SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd} | opcodes/lx_32.opc:114
 cmp_and_32_036813a12ae8 0000 0... .... .... .010 .... .100 0101 %RegDst %SrcL %SrcR %SrcRType
 
-# CMP.ANDI | cmp.andi SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:123
+# CMP.ANDI | cmp.andi SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:115
 cmp_andi_32_da7a5391738d .... .... .... .... .010 .... .101 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# CMP.EQ | cmp.eq SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:124
+# CMP.EQ | cmp.eq SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:116
 cmp_eq_32_6af7c8f41300 0000 0... .... .... .000 .... .100 0101 %RegDst %SrcL %SrcR %SrcRType
 
-# CMP.EQI | cmp.eqi SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:125
+# CMP.EQI | cmp.eqi SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:117
 cmp_eqi_32_252943516dca .... .... .... .... .000 .... .101 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# CMP.GE | cmp.ge SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:126
+# CMP.GE | cmp.ge SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:118
 cmp_ge_32_d88e3a1cfff4 0000 0... .... .... .101 .... .100 0101 %RegDst %SrcL %SrcR %SrcRType
 
-# CMP.GEI | cmp.gei SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:127
+# CMP.GEI | cmp.gei SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:119
 cmp_gei_32_48bf7ea50737 .... .... .... .... .101 .... .101 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# CMP.GEU | cmp.geu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:128
+# CMP.GEU | cmp.geu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:120
 cmp_geu_32_0c002dc415ef 0000 0... .... .... .111 .... .100 0101 %RegDst %SrcL %SrcR %SrcRType
 
-# CMP.GEUI | cmp.geui SrcL, uimm, ->{t, u, Rd} | opcodes/lx_32.opc:129
+# CMP.GEUI | cmp.geui SrcL, uimm, ->{t, u, Rd} | opcodes/lx_32.opc:121
 cmp_geui_32_69ec7b908f5d .... .... .... .... .111 .... .101 0101 %RegDst %SrcL %uimm12
 
-# CMP.LT | cmp.lt SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:130
+# CMP.LT | cmp.lt SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:122
 cmp_lt_32_c0b8cc320f12 0000 0... .... .... .100 .... .100 0101 %RegDst %SrcL %SrcR %SrcRType
 
-# CMP.LTI | cmp.lti SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:131
+# CMP.LTI | cmp.lti SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:123
 cmp_lti_32_02d3081d120b .... .... .... .... .100 .... .101 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# CMP.LTU | cmp.ltu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:132
+# CMP.LTU | cmp.ltu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:124
 cmp_ltu_32_4377481baebc 0000 0... .... .... .110 .... .100 0101 %RegDst %SrcL %SrcR %SrcRType
 
-# CMP.LTUI | cmp.ltui SrcL, uimm, ->{t, u, Rd} | opcodes/lx_32.opc:133
+# CMP.LTUI | cmp.ltui SrcL, uimm, ->{t, u, Rd} | opcodes/lx_32.opc:125
 cmp_ltui_32_8676c7bfd797 .... .... .... .... .110 .... .101 0101 %RegDst %SrcL %uimm12
 
-# CMP.NE | cmp.ne SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:134
+# CMP.NE | cmp.ne SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | opcodes/lx_32.opc:126
 cmp_ne_32_fc47fbb1a0de 0000 0... .... .... .001 .... .100 0101 %RegDst %SrcL %SrcR %SrcRType
 
-# CMP.NEI | cmp.nei SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:135
+# CMP.NEI | cmp.nei SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:127
 cmp_nei_32_00abf831b572 .... .... .... .... .001 .... .101 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# CMP.OR | cmp.or SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd} | opcodes/lx_32.opc:136
+# CMP.OR | cmp.or SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd} | opcodes/lx_32.opc:128
 cmp_or_32_75e1fa54ba94 0000 0... .... .... .011 .... .100 0101 %RegDst %SrcL %SrcR %SrcRType
 
-# CMP.ORI | cmp.ori SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:137
+# CMP.ORI | cmp.ori SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:129
 cmp_ori_32_6d3efbc3d093 .... .... .... .... .011 .... .101 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# CSEL | csel SrcP, SrcL, SrcR<.neg>, ->{t, u, Rd} | opcodes/lx_32.opc:138
+# CSEL | csel SrcP, SrcL, SrcR<.neg>, ->{t, u, Rd} | opcodes/lx_32.opc:130
 csel_32_ba77cbad3c99 .... .... .... .... .000 .... .111 0111 %RegDst %SrcL %SrcP %SrcR %SrcRType
 
-# CTZ | ctz SrcL,  M, N, ->{t, u, Rd} | opcodes/lx_32.opc:139
+# CTZ | ctz SrcL,  M, N, ->{t, u, Rd} | opcodes/lx_32.opc:131
 ctz_32_1761cbcc2a89 .... .... .... .... .100 .... .110 0111 %RegDst %SrcL %imml %imms
 
-# DC.CISW | dc.cisw SrcL | opcodes/lx_32.opc:140
+# DC.CISW | dc.cisw SrcL | opcodes/lx_32.opc:132
 dc_cisw_32_166b7135e3c1 0000 0000 0110 .... .110 0000 0010 1011 %SrcL
 
-# DC.CIVA | dc.civa SrcL | opcodes/lx_32.opc:141
+# DC.CIVA | dc.civa SrcL | opcodes/lx_32.opc:133
 dc_civa_32_265d686549c8 0000 0000 0011 .... .110 0000 0010 1011 %SrcL
 
-# DC.CSW | dc.csw SrcL | opcodes/lx_32.opc:142
+# DC.CSW | dc.csw SrcL | opcodes/lx_32.opc:134
 dc_csw_32_2719115a9246 0000 0000 0101 .... .110 0000 0010 1011 %SrcL
 
-# DC.CVA | dc.cva SrcL | opcodes/lx_32.opc:143
+# DC.CVA | dc.cva SrcL | opcodes/lx_32.opc:135
 dc_cva_32_166d5a076f0e 0000 0000 0010 .... .110 0000 0010 1011 %SrcL
 
-# DC.IALL | dc.iall | opcodes/lx_32.opc:144
+# DC.IALL | dc.iall | opcodes/lx_32.opc:136
 dc_iall_32_3d61563dd077 0000 0000 0001 0000 0110 0000 0010 1011
 
-# DC.ISW | dc.isw SrcL | opcodes/lx_32.opc:145
+# DC.ISW | dc.isw SrcL | opcodes/lx_32.opc:137
 dc_isw_32_7940273560b2 0000 0000 0100 .... .110 0000 0010 1011 %SrcL
 
-# DC.IVA | dc.iva SrcL | opcodes/lx_32.opc:146
+# DC.IVA | dc.iva SrcL | opcodes/lx_32.opc:138
 dc_iva_32_0131d0cf364f 0000 0000 0000 .... .110 0000 0010 1011 %SrcL
 
-# DC.ZVA | dc.zva SrcL | opcodes/lx_32.opc:147
+# DC.ZVA | dc.zva SrcL | opcodes/lx_32.opc:139
 dc_zva_32_0859a1d7aa5b 0000 0000 0111 .... .110 0000 0010 1011 %SrcL
 
-# DIV | div SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:149
+# DIV | div SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:141
 div_32_a6efe85f8662 0000 000. .... .... .000 .... .101 0111 %RegDst %SrcL %SrcR
 
-# DIVU | divu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:150
+# DIVU | divu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:142
 divu_32_cfbc0d1760e4 0000 000. .... .... .001 .... .101 0111 %RegDst %SrcL %SrcR
 
-# DIVUW | divuw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:151
+# DIVUW | divuw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:143
 divuw_32_9c9470ef8982 0000 000. .... .... .011 .... .101 0111 %RegDst %SrcL %SrcR
 
-# DIVW | divw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:152
+# DIVW | divw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:144
 divw_32_b6366c50ac8c 0000 000. .... .... .010 .... .101 0111 %RegDst %SrcL %SrcR
 
-# DMA | dma [SrcL], SrcR | opcodes/lx_32.opc:148
+# DMA | dma [SrcL], SrcR | opcodes/lx_32.opc:140
 dma_32_a168aeca5fa5 0000 000. .... .... .111 0000 0000 1011 %SrcL %SrcR
 
-# EBREAK | ebreak imm | opcodes/lx_32.opc:153
+# EBREAK | ebreak imm | opcodes/lx_32.opc:145
 ebreak_32_4f122d1e6be3 0000 .... 0001 0000 0001 0000 0010 1011 imm4=%imm4_24_4
 
-# ERCOV | ERCOV [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind] | opcodes/lx_32.opc:249
+# ERCOV | ERCOV [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind] | opcodes/lx_32.opc:241
 ercov_32_dc0be14a2d8b .... .00. .... .... .011 0000 0011 0001 %RegSrc0 %RegSrc1 %RegSrc2
 
-# ESAVE | ESAVE [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind] | opcodes/lx_32.opc:248
+# ESAVE | ESAVE [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind] | opcodes/lx_32.opc:240
 esave_32_4c4f79fe3171 .... .00. .... .... .010 0000 0011 0001 %RegSrc0 %RegSrc1 %RegSrc2
 
-# FABS | fabs.{T} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:154
+# FABS | fabs.{T} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:146
 fabs_32_9515e008bf17 0000 0..0 0000 .... .000 .... .111 1011 %RegDst %SrcL %SrcType
 
-# FADD | fadd.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:155
+# FADD | fadd.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:147
 fadd_32_b78b658e6740 0000 0... .... .... .000 .... .100 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FCVT | fcvt.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:156
+# FCVT | fcvt.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:148
 fcvt_32_1102f5aeeda9 .... ...0 0000 .... .000 .... .110 1011 %DstType %RegDst %SrcL %SrcType
 
-# FCVTA | fcvta.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:157
+# FCVTA | fcvta.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:149
 fcvta_32_010837b9acbd .... ...0 0000 .... .001 .... .110 1011 %DstType %RegDst %SrcL %SrcType
 
-# FCVTM | fcvtm.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:158
+# FCVTM | fcvtm.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:150
 fcvtm_32_8801f1562870 .... ...0 0000 .... .010 .... .110 1011 %DstType %RegDst %SrcL %SrcType
 
-# FCVTN | fcvtn.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:159
+# FCVTN | fcvtn.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:151
 fcvtn_32_8714ba358d80 .... ...0 0000 .... .011 .... .110 1011 %DstType %RegDst %SrcL %SrcType
 
-# FCVTP | fcvtp.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:160
+# FCVTP | fcvtp.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:152
 fcvtp_32_84354a7aa6b1 .... ...0 0000 .... .100 .... .110 1011 %DstType %RegDst %SrcL %SrcType
 
-# FCVTZ | fcvtz.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:161
+# FCVTZ | fcvtz.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:153
 fcvtz_32_bee01d31217c .... ...0 0000 .... .101 .... .110 1011 %DstType %RegDst %SrcL %SrcType
 
-# FDIV | fdiv.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:162
+# FDIV | fdiv.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:154
 fdiv_32_04a5bb6ab56f 0000 0... .... .... .011 .... .100 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FENCE.D | fence.d pred_imm, succ_imm | opcodes/lx_32.opc:163
+# FENCE.D | fence.d pred_imm, succ_imm | opcodes/lx_32.opc:155
 fence_d_32_f4783f17d84d 0000 .... .... 0000 0010 0000 0010 1011 %PRED_IMM %SUCC_IMM
 
-# FENCE.I | fence.i | opcodes/lx_32.opc:164
+# FENCE.I | fence.i | opcodes/lx_32.opc:156
 fence_i_32_a321a2a186b1 0001 0000 0000 0000 0010 0000 0010 1011
 
-# FENTRY | FENTRY [RegSrc0 ~ RegSrcn], sp!, uimm | opcodes/lx_32.opc:165
+# FENTRY | FENTRY [RegSrc0 ~ RegSrcn], sp!, uimm | opcodes/lx_32.opc:157
 fentry_32_a47584ec13b6 .... .... .... .... .000 .... .100 0001 %SrcBegin %SrcEnd %uimm
 
-# FEQ | feq.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:166
+# FEQ | feq.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:158
 feq_32_9435d6959c3c 0000 0... .... .... .000 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FEQS | feqs.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:167
+# FEQS | feqs.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:159
 feqs_32_1d3011890fa8 0000 1... .... .... .000 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FEXIT | FEXIT [RegDst0 ~ RegDstn], sp!, uimm | opcodes/lx_32.opc:168
+# FEXIT | FEXIT [RegDst0 ~ RegDstn], sp!, uimm | opcodes/lx_32.opc:160
 fexit_32_37b663f2a34d .... .... .... .... .001 .... .100 0001 %DstBegin %DstEnd %uimm
 
-# FEXP | fexp.{T} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:169
+# FEXP | fexp.{T} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:161
 fexp_32_592ef5288c7d 0000 0..0 0000 .... .011 .... .111 1011 %RegDst %SrcL %SrcType
 
-# FGE | fge.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:170
+# FGE | fge.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:162
 fge_32_b3244b2ffa89 0000 0... .... .... .011 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FGES | fges.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:171
+# FGES | fges.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:163
 fges_32_e0301fcee743 0000 1... .... .... .011 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FLT | flt.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:172
+# FLT | flt.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:164
 flt_32_1c09549d8d3f 0000 0... .... .... .010 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FLTS | flts.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:173
+# FLTS | flts.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:165
 flts_32_c744c874e6a2 0000 1... .... .... .010 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FMADD | fmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | opcodes/lx_32.opc:174
+# FMADD | fmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | opcodes/lx_32.opc:166
 fmadd_32_c616a17bcb12 .... .... .... .... .100 .... .100 1011 %RegDst %SrcA %SrcL %SrcR %SrcType
 
-# FMAX | fmax.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:175
+# FMAX | fmax.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:167
 fmax_32_eaf3880d7739 0000 0... .... .... .110 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FMIN | fmin.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:176
+# FMIN | fmin.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:168
 fmin_32_b5c106e5cd7e 0000 0... .... .... .111 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FMSUB | fmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | opcodes/lx_32.opc:177
+# FMSUB | fmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | opcodes/lx_32.opc:169
 fmsub_32_b83012b83148 .... .... .... .... .101 .... .100 1011 %RegDst %SrcA %SrcL %SrcR %SrcType
 
-# FMUL | fmul.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:178
+# FMUL | fmul.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:170
 fmul_32_7d521d9d65e7 0000 0... .... .... .010 .... .100 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FNE | fne.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:179
+# FNE | fne.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:171
 fne_32_822c18caca3b 0000 0... .... .... .001 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FNES | fnes.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:180
+# FNES | fnes.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:172
 fnes_32_9b4b5a493783 0000 1... .... .... .001 .... .101 1011 %RegDst %SrcL %SrcR %SrcType
 
-# FNMADD | fnmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | opcodes/lx_32.opc:181
+# FNMADD | fnmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | opcodes/lx_32.opc:173
 fnmadd_32_7f45e606d299 .... .... .... .... .110 .... .100 1011 %RegDst %SrcA %SrcL %SrcR %SrcType
 
-# FNMSUB | fnmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | opcodes/lx_32.opc:182
+# FNMSUB | fnmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | opcodes/lx_32.opc:174
 fnmsub_32_6542d56665b3 .... .... .... .... .111 .... .100 1011 %RegDst %SrcA %SrcL %SrcR %SrcType
 
-# FRECIP | frecip.{T} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:183
+# FRECIP | frecip.{T} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:175
 frecip_32_3d51f4f727ea 0000 0..0 0000 .... .010 .... .111 1011 %RegDst %SrcL %SrcType
 
-# FRET.RA | FRET.RA [RegDst0 ~ RegDstn], sp!, uimm | opcodes/lx_32.opc:184
+# FRET.RA | FRET.RA [RegDst0 ~ RegDstn], sp!, uimm | opcodes/lx_32.opc:176
 fret_ra_32_659c886221c1 .... .... .... .... .010 .... .100 0001 %DstBegin %DstEnd %uimm
 
-# FRET.STK | FRET.STK [RegDst0 ~ RegDstn], sp!, uimm | opcodes/lx_32.opc:185
+# FRET.STK | FRET.STK [RegDst0 ~ RegDstn], sp!, uimm | opcodes/lx_32.opc:177
 fret_stk_32_4fe246bd8241 .... .... .... .... .011 .... .100 0001 %DstBegin %DstEnd %uimm
 
-# FSQRT | fsqrt.{T} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:186
+# FSQRT | fsqrt.{T} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:178
 fsqrt_32_84b3495cc6c7 0000 0..0 0000 .... .001 .... .111 1011 %RegDst %SrcL %SrcType
 
-# FSUB | fsub.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:187
+# FSUB | fsub.{T} SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:179
 fsub_32_a4479d0d4276 0000 0... .... .... .001 .... .100 1011 %RegDst %SrcL %SrcR %SrcType
 
-# IC.IALL | ic.iall | opcodes/lx_32.opc:188
+# IC.IALL | ic.iall | opcodes/lx_32.opc:180
 ic_iall_32_854f0d4d906a 0000 0000 0001 0000 0101 0000 0010 1011
 
-# IC.IVA | ic.iva SrcL | opcodes/lx_32.opc:189
+# IC.IVA | ic.iva SrcL | opcodes/lx_32.opc:181
 ic_iva_32_11b9a61dd8b5 0000 0000 0000 .... .101 0000 0010 1011 %SrcL
 
-# J | j label | opcodes/lx_32.opc:190
+# J | j label | opcodes/lx_32.opc:182
 j_32_a303cf05af42 .... .... .... .... .000 .... .011 0111 %simm22
 
-# JR | jr SrcL, label | opcodes/lx_32.opc:191
+# JR | jr SrcL, label | opcodes/lx_32.opc:183
 jr_32_c4128e843b05 .... .... .... .... .110 .... .010 0111 %SrcL %SrcZero simm12=%simm12_7_s5_25_7
 
-# LB | lb [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:192
+# LB | lb [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:184
 lb_32_b718aa88e28f .... .... .... .... .000 .... .000 1001 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# LB.PCR | lb.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:193
+# LB.PCR | lb.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:185
 lb_pcr_32_3fa2540b22d0 .... .... .... .... .000 .... .011 1001 %RegDst %simm17
 
-# LBI | lbi [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:194
+# LBI | lbi [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:186
 lbi_32_9af2cdbeb38f .... .... .... .... .000 .... .001 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LBU | lbu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:195
+# LBU | lbu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:187
 lbu_32_a9a58ab4ea22 .... .... .... .... .100 .... .000 1001 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# LBU.PCR | lbu.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:196
+# LBU.PCR | lbu.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:188
 lbu_pcr_32_5b571b0c8dc2 .... .... .... .... .100 .... .011 1001 %RegDst %simm17
 
-# LBUI | lbui [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:197
+# LBUI | lbui [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:189
 lbui_32_c39b9aa11f02 .... .... .... .... .100 .... .001 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LD | ld [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:198
+# LD | ld [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:190
 ld_32_7c48838bc4e6 .... .... .... .... .011 .... .000 1001 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# LD.ADD | ld.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:199
-ld_add_32_a4038a6c7e86 0000 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LD.ADD | ld.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:191
+ld_add_32_a4038a6c7e86 0000 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LD.AND | ld.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:200
-ld_and_32_2a46b3003480 0001 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LD.AND | ld.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:192
+ld_and_32_2a46b3003480 0001 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LD.OR | ld.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:201
-ld_or_32_456d270cfc7d 0010 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LD.OR | ld.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:193
+ld_or_32_456d270cfc7d 0010 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LD.PCR | ld.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:202
+# LD.PCR | ld.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:194
 ld_pcr_32_99bc3d2d487b .... .... .... .... .011 .... .011 1001 %RegDst %simm17
 
-# LD.SMAX | ld.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:203
-ld_smax_32_a3aad6120226 0100 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LD.SMAX | ld.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:195
+ld_smax_32_a3aad6120226 0100 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LD.SMIN | ld.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:204
-ld_smin_32_9461d345718f 0101 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LD.SMIN | ld.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:196
+ld_smin_32_9461d345718f 0101 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LD.UMAX | ld.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:205
-ld_umax_32_a84af75745d9 0110 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LD.UMAX | ld.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:197
+ld_umax_32_a84af75745d9 0110 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LD.UMIN | ld.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:206
-ld_umin_32_4bf2f357eff3 0111 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LD.UMIN | ld.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:198
+ld_umin_32_4bf2f357eff3 0111 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LD.XOR | ld.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:207
-ld_xor_32_33072c0fde61 0011 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LD.XOR | ld.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:199
+ld_xor_32_33072c0fde61 0011 .... .... .... .100 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LDI | ldi [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:208
+# LDI | ldi [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:200
 ldi_32_d82a643f7a2b .... .... .... .... .011 .... .001 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LDI.U | ldi.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:209
+# LDI.U | ldi.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:201
 ldi_u_32_111bb521a439 .... .... .... .... .011 .... .010 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LH | lh [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:210
+# LH | lh [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:202
 lh_32_d0f04d7d7696 .... .... .... .... .001 .... .000 1001 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# LH.PCR | lh.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:211
+# LH.PCR | lh.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:203
 lh_pcr_32_aabf46d21e49 .... .... .... .... .001 .... .011 1001 %RegDst %simm17
 
-# LHI | lhi [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:212
+# LHI | lhi [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:204
 lhi_32_46a45ec7074d .... .... .... .... .001 .... .001 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LHI.U | lhi.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:213
+# LHI.U | lhi.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:205
 lhi_u_32_bb0c81c6e61d .... .... .... .... .001 .... .010 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LHU | lhu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:214
+# LHU | lhu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:206
 lhu_32_730caf67ecd1 .... .... .... .... .101 .... .000 1001 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# LHU.PCR | lhu.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:215
+# LHU.PCR | lhu.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:207
 lhu_pcr_32_9f4a1c04f258 .... .... .... .... .101 .... .011 1001 %RegDst %simm17
 
-# LHUI | lhui [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:216
+# LHUI | lhui [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:208
 lhui_32_6da39bba900b .... .... .... .... .101 .... .001 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LHUI.U | lhui.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:217
+# LHUI.U | lhui.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:209
 lhui_u_32_748b15cd2ced .... .... .... .... .101 .... .010 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LR.B | lr.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | opcodes/lx_32.opc:218
-lr_b_32_cf80903a761a 0000 .... .... .... .000 .... .000 1011 %RegDst %SrcL %SrcZero aq=%aq_26_1 %far rl=%rl_25_1
+# LR.B | lr.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | opcodes/lx_32.opc:210
+lr_b_32_cf80903a761a 0000 .... .... .... .000 .... .000 1011 %RegDst %SrcL %SrcZero aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LR.D | lr.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | opcodes/lx_32.opc:219
-lr_d_32_84d21a553dc1 0011 .... .... .... .000 .... .000 1011 %RegDst %SrcL %SrcZero aq=%aq_26_1 %far rl=%rl_25_1
+# LR.D | lr.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | opcodes/lx_32.opc:211
+lr_d_32_84d21a553dc1 0011 .... .... .... .000 .... .000 1011 %RegDst %SrcL %SrcZero aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LR.H | lr.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | opcodes/lx_32.opc:220
-lr_h_32_f936df218d63 0001 .... .... .... .000 .... .000 1011 %RegDst %SrcL %SrcZero aq=%aq_26_1 %far rl=%rl_25_1
+# LR.H | lr.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | opcodes/lx_32.opc:212
+lr_h_32_f936df218d63 0001 .... .... .... .000 .... .000 1011 %RegDst %SrcL %SrcZero aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LR.W | lr.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | opcodes/lx_32.opc:221
-lr_w_32_efecc735bb75 0010 .... .... .... .000 .... .000 1011 %RegDst %SrcL %SrcZero aq=%aq_26_1 %far rl=%rl_25_1
+# LR.W | lr.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | opcodes/lx_32.opc:213
+lr_w_32_efecc735bb75 0010 .... .... .... .000 .... .000 1011 %RegDst %SrcL %SrcZero aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LSRGET | lsrget LSR_ID, ->{t, u, Rd} | opcodes/lx_32.opc:222
+# LSRGET | lsrget LSR_ID, ->{t, u, Rd} | opcodes/lx_32.opc:214
 lsrget_32_448b17d7c20a .... .... .... 0000 0011 .... .011 1011 %LSR_ID %RegDst
 
-# LUI | lui simm, ->{t, u, Rd} | opcodes/lx_32.opc:223
+# LUI | lui simm, ->{t, u, Rd} | opcodes/lx_32.opc:215
 lui_32_982113b541d6 .... .... .... .... .... .... .001 0111 %RegDst %imm20
 
-# LW | lw [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:224
+# LW | lw [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:216
 lw_32_3a77ffafcb34 .... .... .... .... .010 .... .000 1001 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# LW.ADD | lw.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:225
-lw_add_32_5be3ad1ad081 0000 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LW.ADD | lw.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:217
+lw_add_32_5be3ad1ad081 0000 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LW.AND | lw.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:226
-lw_and_32_f8dd9866b069 0001 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LW.AND | lw.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:218
+lw_and_32_f8dd9866b069 0001 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LW.OR | lw.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:227
-lw_or_32_d6d2f87706fd 0010 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LW.OR | lw.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:219
+lw_or_32_d6d2f87706fd 0010 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LW.PCR | lw.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:228
+# LW.PCR | lw.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:220
 lw_pcr_32_d135a1aa4ffb .... .... .... .... .010 .... .011 1001 %RegDst %simm17
 
-# LW.SMAX | lw.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:229
-lw_smax_32_838b8c673c91 0100 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LW.SMAX | lw.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:221
+lw_smax_32_838b8c673c91 0100 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LW.SMIN | lw.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:230
-lw_smin_32_44452ae44d02 0101 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LW.SMIN | lw.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:222
+lw_smin_32_44452ae44d02 0101 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LW.UMAX | lw.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:231
-lw_umax_32_3c6a5a534674 0110 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LW.UMAX | lw.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:223
+lw_umax_32_3c6a5a534674 0110 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LW.UMIN | lw.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:232
-lw_umin_32_fd9b7bb538a3 0111 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LW.UMIN | lw.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:224
+lw_umin_32_fd9b7bb538a3 0111 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LW.XOR | lw.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:233
-lw_xor_32_4d4aa82c676a 0011 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# LW.XOR | lw.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:225
+lw_xor_32_4d4aa82c676a 0011 .... .... .... .010 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# LWI | lwi [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:234
+# LWI | lwi [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:226
 lwi_32_7085c98058fa .... .... .... .... .010 .... .001 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LWI.U | lwi.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:235
+# LWI.U | lwi.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:227
 lwi_u_32_4a7426a70f10 .... .... .... .... .010 .... .010 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LWU | lwu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:236
+# LWU | lwu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | opcodes/lx_32.opc:228
 lwu_32_678935925636 .... .... .... .... .110 .... .000 1001 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# LWU.PCR | lwu.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:237
+# LWU.PCR | lwu.pcr [symbol], ->{t, u, Rd} | opcodes/lx_32.opc:229
 lwu_pcr_32_df27ea51c564 .... .... .... .... .110 .... .011 1001 %RegDst %simm17
 
-# LWUI | lwui [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:238
+# LWUI | lwui [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:230
 lwui_32_b435f946eb71 .... .... .... .... .110 .... .001 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# LWUI.U | lwui.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:239
+# LWUI.U | lwui.u [SrcL, simm], ->{t, u, Rd} | opcodes/lx_32.opc:231
 lwui_u_32_1fcbb98df571 .... .... .... .... .110 .... .010 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# MADD | madd SrcL, SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:240
+# MADD | madd SrcL, SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:232
 madd_32_6208e8e59303 .... .00. .... .... .110 .... .100 0111 %RegDst %SrcD %SrcL %SrcR
 
-# MADDW | maddw SrcL, SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:241
+# MADDW | maddw SrcL, SrcR, SrcD, ->{t, u, Rd} | opcodes/lx_32.opc:233
 maddw_32_9f922b15e674 .... .00. .... .... .111 .... .100 0111 %RegDst %SrcD %SrcL %SrcR
 
-# MAX | max SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:242
+# MAX | max SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:234
 max_32_9166468a1db7 0000 000. .... .... .100 .... .101 1011 %RegDst %SrcL %SrcR
 
-# MAXU | maxu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:243
+# MAXU | maxu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:235
 maxu_32_b8789571339d 0000 100. .... .... .100 .... .101 1011 %RegDst %SrcL %SrcR
 
-# MCOPY | MCOPY [RegSrc0, RegSrc1, RegSrc2] | opcodes/lx_32.opc:244
+# MCOPY | MCOPY [RegSrc0, RegSrc1, RegSrc2] | opcodes/lx_32.opc:236
 mcopy_32_4fc4a803e995 .... .00. .... .... .000 0000 0011 0001 %RegSrc0 %RegSrc1 %RegSrc2
 
-# MIN | min SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:245
+# MIN | min SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:237
 min_32_25692b799267 0000 000. .... .... .101 .... .101 1011 %RegDst %SrcL %SrcR
 
-# MINU | minu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:246
+# MINU | minu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:238
 minu_32_9bdb71ef7b19 0000 100. .... .... .101 .... .101 1011 %RegDst %SrcL %SrcR
 
-# MSET | MSET [RegSrc0, RegSrc1, RegSrc2] | opcodes/lx_32.opc:247
+# MSET | MSET [RegSrc0, RegSrc1, RegSrc2] | opcodes/lx_32.opc:239
 mset_32_0b932f291932 .... .00. .... .... .001 0000 0011 0001 %RegSrc0 %RegSrc1 %RegSrc2
 
-# MUL | mul SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:250
+# MUL | mul SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:242
 mul_32_9f2affd8efb8 0000 000. .... .... .000 .... .100 0111 %RegDst %SrcL %SrcR
 
-# MULU | mulu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:251
+# MULU | mulu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:243
 mulu_32_10b9d1936631 0000 000. .... .... .001 .... .100 0111 %RegDst %SrcL %SrcR
 
-# MULUW | muluw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:252
+# MULUW | muluw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:244
 muluw_32_8f52b3d45e53 0000 000. .... .... .011 .... .100 0111 %RegDst %SrcL %SrcR
 
-# MULW | mulw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:253
+# MULW | mulw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:245
 mulw_32_b90cb6a30a23 0000 000. .... .... .010 .... .100 0111 %RegDst %SrcL %SrcR
 
-# OR | or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:254
+# OR | or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:246
 or_32_a7fb80e78831 .... .... .... .... .011 .... .000 0101 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# ORI | ori SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:255
+# ORI | ori SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:247
 ori_32_413a6cc76e9a .... .... .... .... .011 .... .001 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# ORIW | oriw SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:256
+# ORIW | oriw SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:248
 oriw_32_91608caf1ba6 .... .... .... .... .011 .... .011 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# ORW | orw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:257
+# ORW | orw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:249
 orw_32_84f7ac2ed68f .... .... .... .... .011 .... .010 0101 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# PRF | prf [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>] | opcodes/lx_32.opc:258
+# PRF | prf [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>] | opcodes/lx_32.opc:250
 prf_32_30e6dfe4e3ce .... .... .... .... .111 .... .000 1001 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# PRFI.U | prfi.u [SrcL, simm] | opcodes/lx_32.opc:259
+# PRFI.U | prfi.u [SrcL, simm] | opcodes/lx_32.opc:251
 prfi_u_32_167b42882547 .... .... .... .... .111 .... .010 1001 %RegDst %SrcL simm12=%simm12_20_s12
 
-# REM | rem SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:260
+# REM | rem SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:252
 rem_32_0abbd6a3b865 0000 000. .... .... .100 .... .101 0111 %RegDst %SrcL %SrcR
 
-# REMU | remu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:261
+# REMU | remu SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:253
 remu_32_d7a5d1ebbbf5 0000 000. .... .... .101 .... .101 0111 %RegDst %SrcL %SrcR
 
-# REMUW | remuw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:262
+# REMUW | remuw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:254
 remuw_32_f10ade2f5ccb 0000 000. .... .... .111 .... .101 0111 %RegDst %SrcL %SrcR
 
-# REMW | remw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:263
+# REMW | remw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:255
 remw_32_22659af46ec0 0000 000. .... .... .110 .... .101 0111 %RegDst %SrcL %SrcR
 
-# REV | rev SrcL,  M, N, ->{t, u, Rd} | opcodes/lx_32.opc:264
+# REV | rev SrcL,  M, N, ->{t, u, Rd} | opcodes/lx_32.opc:256
 rev_32_58badc109d49 .... .... .... .... .111 .... .110 0111 %RegDst %SrcL %imml %immr
 
-# SB | sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | opcodes/lx_32.opc:265
+# SB | sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | opcodes/lx_32.opc:257
 sb_32_43c106ae3749 .... .... .... .... .000 0000 0100 1001 %SrcD %SrcL %SrcR %SrcRType
 
-# SB.PCR | sb.pcr SrcL, [symbol] | opcodes/lx_32.opc:266
+# SB.PCR | sb.pcr SrcL, [symbol] | opcodes/lx_32.opc:258
 sb_pcr_32_7625a9a24c59 .... .... .... .... .000 .... .110 1001 %SrcL %simm
 
-# SBI | sbi SrcL, [SrcR, simm] | opcodes/lx_32.opc:267
+# SBI | sbi SrcL, [SrcR, simm] | opcodes/lx_32.opc:259
 sbi_32_f3c6b796f0d9 .... .... .... .... .000 .... .101 1001 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# SC.B | sc.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | opcodes/lx_32.opc:268
-sc_b_32_baf609e1d5c3 0000 .... .... .... .001 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# SC.B | sc.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | opcodes/lx_32.opc:260
+sc_b_32_baf609e1d5c3 0000 .... .... .... .001 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# SC.D | sc.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | opcodes/lx_32.opc:269
-sc_d_32_2e714149031c 0011 .... .... .... .001 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# SC.D | sc.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | opcodes/lx_32.opc:261
+sc_d_32_2e714149031c 0011 .... .... .... .001 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# SC.H | sc.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | opcodes/lx_32.opc:270
-sc_h_32_108941eabac6 0001 .... .... .... .001 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# SC.H | sc.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | opcodes/lx_32.opc:262
+sc_h_32_108941eabac6 0001 .... .... .... .001 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# SC.W | sc.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | opcodes/lx_32.opc:271
-sc_w_32_14b238f02bfd 0010 .... .... .... .001 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# SC.W | sc.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | opcodes/lx_32.opc:263
+sc_w_32_14b238f02bfd 0010 .... .... .... .001 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# SCVTF | scvtf.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:272
+# SCVTF | scvtf.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:264
 scvtf_32_01861bbd5ef2 .... ...0 0000 .... .110 .... .110 1011 %DstType %RegDst %SrcL %SrcType
 
-# SD | sd SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3] | opcodes/lx_32.opc:273
+# SD | sd SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3] | opcodes/lx_32.opc:265
 sd_32_9dbc40328653 .... .... .... .... .011 0000 0100 1001 %SrcD %SrcL %SrcR %SrcRType
 
-# SD.ADD | sd.add<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:274
-sd_add_32_2a55ae1228bd 0000 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SD.ADD | sd.add<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:266
+sd_add_32_2a55ae1228bd 0000 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SD.AND | sd.and<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:275
-sd_and_32_71963e1769c2 0001 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SD.AND | sd.and<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:267
+sd_and_32_71963e1769c2 0001 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SD.OR | sd.or<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:276
-sd_or_32_2a65eedfae0f 0010 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SD.OR | sd.or<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:268
+sd_or_32_2a65eedfae0f 0010 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SD.PCR | sd.pcr SrcL, [symbol] | opcodes/lx_32.opc:277
+# SD.PCR | sd.pcr SrcL, [symbol] | opcodes/lx_32.opc:269
 sd_pcr_32_2340e0085413 .... .... .... .... .011 .... .110 1001 %SrcL %simm
 
-# SD.SMAX | sd.smax<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:278
-sd_smax_32_e59bf90b50c3 0100 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SD.SMAX | sd.smax<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:270
+sd_smax_32_e59bf90b50c3 0100 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SD.SMIN | sd.smin<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:279
-sd_smin_32_188d93125032 0101 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SD.SMIN | sd.smin<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:271
+sd_smin_32_188d93125032 0101 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SD.U | sd.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | opcodes/lx_32.opc:280
+# SD.U | sd.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | opcodes/lx_32.opc:272
 sd_u_32_1602c58c2031 .... .... .... .... .111 0000 0100 1001 %SrcD %SrcL %SrcR %SrcRType
 
-# SD.UMAX | sd.umax<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:281
-sd_umax_32_89c5ec42be68 0110 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SD.UMAX | sd.umax<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:273
+sd_umax_32_89c5ec42be68 0110 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SD.UMIN | sd.umin<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:282
-sd_umin_32_2388cbb378ac 0111 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SD.UMIN | sd.umin<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:274
+sd_umin_32_2388cbb378ac 0111 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SD.XOR | sd.xor<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:283
-sd_xor_32_7655ceaf9497 0011 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SD.XOR | sd.xor<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:275
+sd_xor_32_7655ceaf9497 0011 .0.. .... .... .101 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SDI | sdi SrcL, [SrcR, simm] | opcodes/lx_32.opc:284
+# SDI | sdi SrcL, [SrcR, simm] | opcodes/lx_32.opc:276
 sdi_32_fab563230a66 .... .... .... .... .011 .... .101 1001 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# SDI.U | sdi.u SrcL, [SrcR, simm] | opcodes/lx_32.opc:285
+# SDI.U | sdi.u SrcL, [SrcR, simm] | opcodes/lx_32.opc:277
 sdi_u_32_cba5a4a04e7b .... .... .... .... .111 .... .101 1001 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# SETC.AND | setc.and SrcL, SrcR<.sw, .uw, .not> | opcodes/lx_32.opc:286
+# SETC.AND | setc.and SrcL, SrcR<.sw, .uw, .not> | opcodes/lx_32.opc:278
 setc_and_32_90b4e93ef9d4 0000 0... .... .... .010 0000 0110 0101 %SrcL %SrcR %SrcRType
 
-# SETC.ANDI | setc.andi SrcL, simm | opcodes/lx_32.opc:287
+# SETC.ANDI | setc.andi SrcL, simm | opcodes/lx_32.opc:279
 setc_andi_32_32fe61c0559b .... .... .... .... .010 .... .111 0101 %SrcL shamt=%shamt_7_5 simm12=%simm12_20_s12
 
-# SETC.EQ | setc.eq SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:288
+# SETC.EQ | setc.eq SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:280
 setc_eq_32_fb06e1dddc5c 0000 0... .... .... .000 0000 0110 0101 %SrcL %SrcR %SrcRType
 
-# SETC.EQI | setc.eqi SrcL, simm | opcodes/lx_32.opc:289
+# SETC.EQI | setc.eqi SrcL, simm | opcodes/lx_32.opc:281
 setc_eqi_32_5b2366a4e55d .... .... .... .... .000 .... .111 0101 %SrcL shamt=%shamt_7_5 simm12=%simm12_20_s12
 
-# SETC.GE | setc.ge SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:290
+# SETC.GE | setc.ge SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:282
 setc_ge_32_56a2b539b072 0000 0... .... .... .101 0000 0110 0101 %SrcL %SrcR %SrcRType
 
-# SETC.GEI | setc.gei SrcL, simm | opcodes/lx_32.opc:291
+# SETC.GEI | setc.gei SrcL, simm | opcodes/lx_32.opc:283
 setc_gei_32_c3f4fdc4adcc .... .... .... .... .101 .... .111 0101 %SrcL shamt=%shamt_7_5 simm12=%simm12_20_s12
 
-# SETC.GEU | setc.geu SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:292
+# SETC.GEU | setc.geu SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:284
 setc_geu_32_494f1f79099e 0000 0... .... .... .111 0000 0110 0101 %SrcL %SrcR %SrcRType
 
-# SETC.GEUI | setc.geui SrcL, uimm | opcodes/lx_32.opc:293
+# SETC.GEUI | setc.geui SrcL, uimm | opcodes/lx_32.opc:285
 setc_geui_32_6c34bc4ad314 .... .... .... .... .111 .... .111 0101 %SrcL shamt=%shamt_7_5 %uimm12
 
-# SETC.LT | setc.lt SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:294
+# SETC.LT | setc.lt SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:286
 setc_lt_32_10de99f3ad6a 0000 0... .... .... .100 0000 0110 0101 %SrcL %SrcR %SrcRType
 
-# SETC.LTI | setc.lti SrcL, simm | opcodes/lx_32.opc:295
+# SETC.LTI | setc.lti SrcL, simm | opcodes/lx_32.opc:287
 setc_lti_32_89d74d948b74 .... .... .... .... .100 .... .111 0101 %SrcL shamt=%shamt_7_5 simm12=%simm12_20_s12
 
-# SETC.LTU | setc.ltu SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:296
+# SETC.LTU | setc.ltu SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:288
 setc_ltu_32_4a1ff65ecafb 0000 0... .... .... .110 0000 0110 0101 %SrcL %SrcR %SrcRType
 
-# SETC.LTUI | setc.ltui SrcL, uimm | opcodes/lx_32.opc:297
+# SETC.LTUI | setc.ltui SrcL, uimm | opcodes/lx_32.opc:289
 setc_ltui_32_7908d25901c6 .... .... .... .... .110 .... .111 0101 %SrcL shamt=%shamt_7_5 %uimm12
 
-# SETC.NE | setc.ne SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:298
+# SETC.NE | setc.ne SrcL, SrcR<{.sw, .uw}> | opcodes/lx_32.opc:290
 setc_ne_32_77576a5c690c 0000 0... .... .... .001 0000 0110 0101 %SrcL %SrcR %SrcRType
 
-# SETC.NEI | setc.nei SrcL, simm | opcodes/lx_32.opc:299
+# SETC.NEI | setc.nei SrcL, simm | opcodes/lx_32.opc:291
 setc_nei_32_fa01e973ab76 .... .... .... .... .001 .... .111 0101 %SrcL shamt=%shamt_7_5 simm12=%simm12_20_s12
 
-# SETC.OR | setc.or SrcL, SrcR<.sw, .uw, .not> | opcodes/lx_32.opc:300
+# SETC.OR | setc.or SrcL, SrcR<.sw, .uw, .not> | opcodes/lx_32.opc:292
 setc_or_32_740134c709d2 0000 0... .... .... .011 0000 0110 0101 %SrcL %SrcR %SrcRType
 
-# SETC.ORI | setc.ori SrcL, simm | opcodes/lx_32.opc:301
+# SETC.ORI | setc.ori SrcL, simm | opcodes/lx_32.opc:293
 setc_ori_32_183dc15fad54 .... .... .... .... .011 .... .111 0101 %SrcL shamt=%shamt_7_5 simm12=%simm12_20_s12
 
-# SETC.TGT | setc.tgt SrcL | opcodes/lx_32.opc:302
+# SETC.TGT | setc.tgt SrcL | opcodes/lx_32.opc:294
 setc_tgt_32_c02656d3a2b8 0000 0000 0000 .... .100 0000 0011 1011 %SrcL
 
-# SETRET | setret uimm, ->Ra | opcodes/lx_32.opc:303
+# SETRET | setret uimm, ->Ra | opcodes/lx_32.opc:295
 setret_32_72003dcf3b59 .... .... .... .... .... 0101 0000 0111 %imm20
 
-# SH | sh SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1] | opcodes/lx_32.opc:304
+# SH | sh SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1] | opcodes/lx_32.opc:296
 sh_32_bc7d4a7dea28 .... .... .... .... .001 0000 0100 1001 %SrcD %SrcL %SrcR %SrcRType
 
-# SH.PCR | sh.pcr SrcL, [symbol] | opcodes/lx_32.opc:305
+# SH.PCR | sh.pcr SrcL, [symbol] | opcodes/lx_32.opc:297
 sh_pcr_32_14ba505eb3c2 .... .... .... .... .001 .... .110 1001 %SrcL %simm
 
-# SH.U | sh.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | opcodes/lx_32.opc:306
+# SH.U | sh.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | opcodes/lx_32.opc:298
 sh_u_32_fa87afbf8f24 .... .... .... .... .101 0000 0100 1001 %SrcD %SrcL %SrcR %SrcRType
 
-# SHI | shi SrcL, [SrcR, simm] | opcodes/lx_32.opc:307
+# SHI | shi SrcL, [SrcR, simm] | opcodes/lx_32.opc:299
 shi_32_21351c202204 .... .... .... .... .001 .... .101 1001 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# SHI.U | shi.u SrcL, [SrcR, simm] | opcodes/lx_32.opc:308
+# SHI.U | shi.u SrcL, [SrcR, simm] | opcodes/lx_32.opc:300
 shi_u_32_caaf3ed72a8f .... .... .... .... .101 .... .101 1001 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# SLL | sll SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:309
+# SLL | sll SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:301
 sll_32_a100b8961e21 0000 000. .... .... .111 .... .000 0101 %RegDst %SrcL %SrcR
 
-# SLLI | slli SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:310
+# SLLI | slli SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:302
 slli_32_b43ca2454e3a 0000 00.. .... .... .111 .... .001 0101 %RegDst %SrcL shamt=%shamt_20_6
 
-# SLLIW | slliw SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:311
+# SLLIW | slliw SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:303
 slliw_32_c6bf463b97ae 0000 000. .... .... .111 .... .011 0101 %RegDst %SrcL shamt=%shamt_20_5
 
-# SLLW | sllw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:312
+# SLLW | sllw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:304
 sllw_32_a37b63c16b27 0000 000. .... .... .111 .... .010 0101 %RegDst %SrcL %SrcR
 
-# SRA | sra SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:313
+# SRA | sra SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:305
 sra_32_ba03eea6386b 0000 000. .... .... .110 .... .000 0101 %RegDst %SrcL %SrcR
 
-# SRAI | srai SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:314
+# SRAI | srai SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:306
 srai_32_e471ea84d4fd 0000 00.. .... .... .110 .... .001 0101 %RegDst %SrcL shamt=%shamt_20_6
 
-# SRAIW | sraiw SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:315
+# SRAIW | sraiw SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:307
 sraiw_32_db04a6299504 0000 000. .... .... .110 .... .011 0101 %RegDst %SrcL shamt=%shamt_20_5
 
-# SRAW | sraw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:316
+# SRAW | sraw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:308
 sraw_32_5baf37f34241 0000 000. .... .... .110 .... .010 0101 %RegDst %SrcL %SrcR
 
-# SRL | srl SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:317
+# SRL | srl SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:309
 srl_32_5cfca42c59f3 0000 000. .... .... .101 .... .000 0101 %RegDst %SrcL %SrcR
 
-# SRLI | srli SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:318
+# SRLI | srli SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:310
 srli_32_dd29ca058cfe 0000 00.. .... .... .101 .... .001 0101 %RegDst %SrcL shamt=%shamt_20_6
 
-# SRLIW | srliw SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:319
+# SRLIW | srliw SrcL, shamt, ->{t, u, Rd} | opcodes/lx_32.opc:311
 srliw_32_ef4aa650f46e 0000 000. .... .... .101 .... .011 0101 %RegDst %SrcL shamt=%shamt_20_5
 
-# SRLW | srlw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:320
+# SRLW | srlw SrcL, SrcR, ->{t, u, Rd} | opcodes/lx_32.opc:312
 srlw_32_2c6458b2aadb 0000 000. .... .... .101 .... .010 0101 %RegDst %SrcL %SrcR
 
-# SSRGET | ssrget SSR_ID, ->{t, u, Rd} | opcodes/lx_32.opc:321
+# SSRGET | ssrget SSR_ID, ->{t, u, Rd} | opcodes/lx_32.opc:313
 ssrget_32_959957ab6b75 .... .... .... 0000 0000 .... .011 1011 %RegDst %SSR_ID
 
-# SSRSET | ssrset SrcL, SSR_ID | opcodes/lx_32.opc:322
+# SSRSET | ssrset SrcL, SSR_ID | opcodes/lx_32.opc:314
 ssrset_32_4dd3b71802c6 .... .... .... .... .001 0000 0011 1011 %SSR_ID %SrcL
 
-# SSRSWAP | ssrswap SrcL, SSR_ID, ->{t, u, Rd} | opcodes/lx_32.opc:323
+# SSRSWAP | ssrswap SrcL, SSR_ID, ->{t, u, Rd} | opcodes/lx_32.opc:315
 ssrswap_32_a01c7e2c7c29 .... .... .... .... .010 .... .011 1011 %RegDst %SSR_ID %SrcL
 
-# SUB | sub SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:324
+# SUB | sub SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:316
 sub_32_af383d4a2b42 .... .... .... .... .001 .... .000 0101 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# SUBI | subi SrcL, uimm, ->{t, u, Rd} | opcodes/lx_32.opc:325
+# SUBI | subi SrcL, uimm, ->{t, u, Rd} | opcodes/lx_32.opc:317
 subi_32_a0c87f5e7ac4 .... .... .... .... .001 .... .001 0101 %RegDst %SrcL %uimm12
 
-# SUBIW | subiw SrcL, uimm, ->{t, u, Rd} | opcodes/lx_32.opc:326
+# SUBIW | subiw SrcL, uimm, ->{t, u, Rd} | opcodes/lx_32.opc:318
 subiw_32_51019ff77d0a .... .... .... .... .001 .... .011 0101 %RegDst %SrcL %uimm12
 
-# SUBW | subw SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:327
+# SUBW | subw SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:319
 subw_32_3a8d45653c98 .... .... .... .... .001 .... .010 0101 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# SW | sw SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2] | opcodes/lx_32.opc:328
+# SW | sw SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2] | opcodes/lx_32.opc:320
 sw_32_28ad317b1b41 .... .... .... .... .010 0000 0100 1001 %SrcD %SrcL %SrcR %SrcRType
 
-# SW.ADD | sw.add<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:329
-sw_add_32_3dca755552cb 0000 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SW.ADD | sw.add<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:321
+sw_add_32_3dca755552cb 0000 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SW.AND | sw.and<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:330
-sw_and_32_7ef0872d5502 0001 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SW.AND | sw.and<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:322
+sw_and_32_7ef0872d5502 0001 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SW.OR | sw.or<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:331
-sw_or_32_354579538c4e 0010 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SW.OR | sw.or<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:323
+sw_or_32_354579538c4e 0010 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SW.PCR | sw.pcr SrcL, [symbol] | opcodes/lx_32.opc:332
+# SW.PCR | sw.pcr SrcL, [symbol] | opcodes/lx_32.opc:324
 sw_pcr_32_436677679523 .... .... .... .... .010 .... .110 1001 %SrcL %simm
 
-# SW.SMAX | sw.smax<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:333
-sw_smax_32_8bab38a878d7 0100 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SW.SMAX | sw.smax<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:325
+sw_smax_32_8bab38a878d7 0100 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SW.SMIN | sw.smin<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:334
-sw_smin_32_773e7d83b011 0101 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SW.SMIN | sw.smin<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:326
+sw_smin_32_773e7d83b011 0101 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SW.U | sw.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | opcodes/lx_32.opc:335
+# SW.U | sw.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | opcodes/lx_32.opc:327
 sw_u_32_718a61f75d33 .... .... .... .... .110 0000 0100 1001 %SrcD %SrcL %SrcR %SrcRType
 
-# SW.UMAX | sw.umax<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:336
-sw_umax_32_5530dfa23323 0110 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SW.UMAX | sw.umax<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:328
+sw_umax_32_5530dfa23323 0110 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SW.UMIN | sw.umin<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:337
-sw_umin_32_3ce114819cfc 0111 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SW.UMIN | sw.umin<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:329
+sw_umin_32_3ce114819cfc 0111 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SW.XOR | sw.xor<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:338
-sw_xor_32_874c32572226 0011 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR %far rl=%rl_25_1
+# SW.XOR | sw.xor<.{rl, f, rlf}> [SrcL], SrcR | opcodes/lx_32.opc:330
+sw_xor_32_874c32572226 0011 .0.. .... .... .011 0000 0000 1011 %SrcL %SrcR far=%far_27_1 rl=%rl_25_1
 
-# SWAPB | swapb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:339
-swapb_32_80733f03b77f 0000 .... .... .... .110 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# SWAPB | swapb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:331
+swapb_32_80733f03b77f 0000 .... .... .... .110 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# SWAPD | swapd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:340
-swapd_32_cd31ccde2303 0011 .... .... .... .110 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# SWAPD | swapd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:332
+swapd_32_cd31ccde2303 0011 .... .... .... .110 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# SWAPH | swaph<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:341
-swaph_32_8c2d4a28bf25 0001 .... .... .... .110 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# SWAPH | swaph<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:333
+swaph_32_8c2d4a28bf25 0001 .... .... .... .110 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# SWAPW | swapw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:342
-swapw_32_ef15c3ebac33 0010 .... .... .... .110 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 %far rl=%rl_25_1
+# SWAPW | swapw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | opcodes/lx_32.opc:334
+swapw_32_ef15c3ebac33 0010 .... .... .... .110 .... .000 1011 %RegDst %SrcL %SrcR aq=%aq_26_1 far=%far_27_1 rl=%rl_25_1
 
-# SWI | swi SrcL, [SrcR, simm] | opcodes/lx_32.opc:343
+# SWI | swi SrcL, [SrcR, simm] | opcodes/lx_32.opc:335
 swi_32_147e55489c41 .... .... .... .... .010 .... .101 1001 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# SWI.U | swi.u SrcL, [SrcR, simm] | opcodes/lx_32.opc:344
+# SWI.U | swi.u SrcL, [SrcR, simm] | opcodes/lx_32.opc:336
 swi_u_32_1630e926da1a .... .... .... .... .110 .... .101 1001 %SrcL %SrcR simm12=%simm12_7_s5_25_7
 
-# TLB.IA | tlb.ia SrcL | opcodes/lx_32.opc:345
+# TLB.IA | tlb.ia SrcL | opcodes/lx_32.opc:337
 tlb_ia_32_e794d6bf347e 0000 0000 0000 .... .111 0000 0010 1011 %SrcL
 
-# TLB.IALL | tlb.iall | opcodes/lx_32.opc:346
+# TLB.IALL | tlb.iall | opcodes/lx_32.opc:338
 tlb_iall_32_0fb421b85c88 0000 0000 0011 0000 0111 0000 0010 1011
 
-# TLB.IAV | tlb.iav SrcL | opcodes/lx_32.opc:347
+# TLB.IAV | tlb.iav SrcL | opcodes/lx_32.opc:339
 tlb_iav_32_95f4937d2917 0000 0000 0010 .... .111 0000 0010 1011 %SrcL
 
-# TLB.IV | tlb.iv SrcL | opcodes/lx_32.opc:348
+# TLB.IV | tlb.iv SrcL | opcodes/lx_32.opc:340
 tlb_iv_32_bf0a5d1ea211 0000 0000 0001 .... .111 0000 0010 1011 %SrcL
 
-# UCVTF | ucvtf.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:349
+# UCVTF | ucvtf.{srcT2dstT} SrcL, ->{t, u, Rd} | opcodes/lx_32.opc:341
 ucvtf_32_987f4e019c32 .... ...0 0000 .... .111 .... .110 1011 %DstType %RegDst %SrcL %SrcType
 
-# XB | XB ACR-ID, C-ID | opcodes/lx_32.opc:350
+# XB | XB ACR-ID, C-ID | opcodes/lx_32.opc:342
 xb_32_40ad190a0a7f .... .... .... .... .110 1111 1000 0001 %ACR_ID %CROSS_BID
 
-# XOR | xor SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:351
+# XOR | xor SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:343
 xor_32_33510860c585 .... .... .... .... .100 .... .000 0101 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
 
-# XORI | xori SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:352
+# XORI | xori SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:344
 xori_32_5cf7e5be17e7 .... .... .... .... .100 .... .001 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# XORIW | xoriw SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:353
+# XORIW | xoriw SrcL, simm, ->{t, u, Rd} | opcodes/lx_32.opc:345
 xoriw_32_1f8c6f43e2bd .... .... .... .... .100 .... .011 0101 %RegDst %SrcL simm12=%simm12_20_s12
 
-# XORW | xorw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:354
+# XORW | xorw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | opcodes/lx_32.opc:346
 xorw_32_32282566e32d .... .... .... .... .100 .... .010 0101 %RegDst %SrcL %SrcR %SrcRType shamt=%shamt_27_5
diff --git a/isa/generated/codecs/linxisa_opcodes.c b/isa/generated/codecs/linxisa_opcodes.c
index 42894250..e66b3758 100644
--- a/isa/generated/codecs/linxisa_opcodes.c
+++ b/isa/generated/codecs/linxisa_opcodes.c
@@ -41,19 +41,19 @@ const linxisa_field_piece linxisa_field_pieces[] = {
   { .insn_lsb = 25, .width = 2, .value_lsb = 0 },
   { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 15, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 7, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 26, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 29, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 30, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 27, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 28, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 31, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 25, .width = 3, .value_lsb = 0 },
-  { .insn_lsb = 7, .width = 5, .value_lsb = 0 },
+  { .insn_lsb = 16, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 17, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 18, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 15, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 19, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 29, .width = 3, .value_lsb = 0 },
+  { .insn_lsb = 25, .width = 1, .value_lsb = 0 },
   { .insn_lsb = 20, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 15, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 28, .width = 3, .value_lsb = 0 },
-  { .insn_lsb = 31, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 7, .width = 5, .value_lsb = 0 },
+  { .insn_lsb = 27, .width = 2, .value_lsb = 0 },
+  { .insn_lsb = 15, .width = 3, .value_lsb = 0 },
+  { .insn_lsb = 26, .width = 1, .value_lsb = 0 },
   { .insn_lsb = 15, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 20, .width = 12, .value_lsb = 0 },
   { .insn_lsb = 7, .width = 5, .value_lsb = 12 },
@@ -84,33 +84,29 @@ const linxisa_field_piece linxisa_field_pieces[] = {
   { .insn_lsb = 15, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 20, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 22, .width = 3, .value_lsb = 0 },
-  { .insn_lsb = 29, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 30, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 7, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 15, .width = 1, .value_lsb = 5 },
-  { .insn_lsb = 25, .width = 4, .value_lsb = 0 },
-  { .insn_lsb = 29, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 30, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 31, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 7, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 15, .width = 1, .value_lsb = 5 },
-  { .insn_lsb = 16, .width = 6, .value_lsb = 0 },
-  { .insn_lsb = 22, .width = 3, .value_lsb = 0 },
-  { .insn_lsb = 29, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 30, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 31, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 7, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 15, .width = 1, .value_lsb = 5 },
-  { .insn_lsb = 16, .width = 6, .value_lsb = 0 },
-  { .insn_lsb = 25, .width = 4, .value_lsb = 0 },
-  { .insn_lsb = 29, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 30, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 7, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 15, .width = 1, .value_lsb = 5 },
-  { .insn_lsb = 22, .width = 3, .value_lsb = 0 },
-  { .insn_lsb = 29, .width = 1, .value_lsb = 0 },
-  { .insn_lsb = 25, .width = 4, .value_lsb = 0 },
+  { .insn_lsb = 7, .width = 3, .value_lsb = 0 },
+  { .insn_lsb = 19, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 10, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 20, .width = 6, .value_lsb = 0 },
+  { .insn_lsb = 15, .width = 4, .value_lsb = 0 },
+  { .insn_lsb = 7, .width = 3, .value_lsb = 0 },
+  { .insn_lsb = 19, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 10, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 11, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 20, .width = 6, .value_lsb = 0 },
+  { .insn_lsb = 26, .width = 6, .value_lsb = 0 },
+  { .insn_lsb = 15, .width = 4, .value_lsb = 0 },
+  { .insn_lsb = 19, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 10, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 20, .width = 6, .value_lsb = 0 },
+  { .insn_lsb = 7, .width = 3, .value_lsb = 0 },
+  { .insn_lsb = 19, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 15, .width = 4, .value_lsb = 0 },
+  { .insn_lsb = 19, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 10, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 11, .width = 1, .value_lsb = 0 },
+  { .insn_lsb = 20, .width = 6, .value_lsb = 0 },
+  { .insn_lsb = 26, .width = 6, .value_lsb = 0 },
   { .insn_lsb = 15, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 20, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 25, .width = 7, .value_lsb = 0 },
@@ -147,10 +143,6 @@ const linxisa_field_piece linxisa_field_pieces[] = {
   { .insn_lsb = 4, .width = 12, .value_lsb = 0 },
   { .insn_lsb = 22, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 20, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 20, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 15, .width = 17, .value_lsb = 0 },
   { .insn_lsb = 15, .width = 17, .value_lsb = 0 },
   { .insn_lsb = 15, .width = 17, .value_lsb = 0 },
@@ -168,7 +160,8 @@ const linxisa_field_piece linxisa_field_pieces[] = {
   { .insn_lsb = 15, .width = 17, .value_lsb = 0 },
   { .insn_lsb = 15, .width = 17, .value_lsb = 0 },
   { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
-  { .insn_lsb = 15, .width = 10, .value_lsb = 0 },
+  { .insn_lsb = 20, .width = 5, .value_lsb = 0 },
+  { .insn_lsb = 25, .width = 2, .value_lsb = 0 },
   { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
   { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
@@ -3403,7 +3396,7 @@ const linxisa_field_piece linxisa_field_pieces[] = {
   { .insn_lsb = 25, .width = 2, .value_lsb = 0 },
   { .insn_lsb = 27, .width = 5, .value_lsb = 0 },
 };
-const size_t linxisa_field_pieces_count = 3398;
+const size_t linxisa_field_pieces_count = 3391;
 
 const linxisa_field linxisa_fields[] = {
   { .name = "RST_Type", .signed_hint = -1, .bit_width = 4, .piece_start = 0, .piece_count = 1 },
@@ -3443,17 +3436,17 @@ const linxisa_field linxisa_fields[] = {
   { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 34, .piece_count = 1 },
   { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 35, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 36, .piece_count = 1 },
-  { .name = "format", .signed_hint = -1, .bit_width = 5, .piece_start = 37, .piece_count = 1 },
-  { .name = "DR", .signed_hint = -1, .bit_width = 1, .piece_start = 38, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 39, .piece_count = 1 },
-  { .name = "atom", .signed_hint = -1, .bit_width = 1, .piece_start = 40, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 41, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 42, .piece_count = 1 },
-  { .name = "trap", .signed_hint = -1, .bit_width = 1, .piece_start = 43, .piece_count = 1 },
-  { .name = "CMode", .signed_hint = -1, .bit_width = 3, .piece_start = 44, .piece_count = 1 },
-  { .name = "DataLayout", .signed_hint = -1, .bit_width = 5, .piece_start = 45, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 46, .piece_count = 1 },
-  { .name = "PadValue", .signed_hint = -1, .bit_width = 5, .piece_start = 47, .piece_count = 1 },
+  { .name = "DR", .signed_hint = -1, .bit_width = 1, .piece_start = 37, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 38, .piece_count = 1 },
+  { .name = "atom", .signed_hint = -1, .bit_width = 1, .piece_start = 39, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 40, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 41, .piece_count = 1 },
+  { .name = "trap", .signed_hint = -1, .bit_width = 1, .piece_start = 42, .piece_count = 1 },
+  { .name = "CMode", .signed_hint = -1, .bit_width = 3, .piece_start = 43, .piece_count = 1 },
+  { .name = "Canonicalize", .signed_hint = -1, .bit_width = 1, .piece_start = 44, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 45, .piece_count = 1 },
+  { .name = "Layout", .signed_hint = -1, .bit_width = 5, .piece_start = 46, .piece_count = 1 },
+  { .name = "PadValueOrByteId", .signed_hint = -1, .bit_width = 2, .piece_start = 47, .piece_count = 1 },
   { .name = "RMode", .signed_hint = -1, .bit_width = 3, .piece_start = 48, .piece_count = 1 },
   { .name = "Sat", .signed_hint = -1, .bit_width = 1, .piece_start = 49, .piece_count = 1 },
   { .name = "RegSrc", .signed_hint = -1, .bit_width = 5, .piece_start = 50, .piece_count = 1 },
@@ -3483,39 +3476,43 @@ const linxisa_field linxisa_fields[] = {
   { .name = "DstTile", .signed_hint = -1, .bit_width = 3, .piece_start = 80, .piece_count = 1 },
   { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 81, .piece_count = 1 },
   { .name = "S0R", .signed_hint = -1, .bit_width = 1, .piece_start = 82, .piece_count = 1 },
-  { .name = "SrcTile0", .signed_hint = -1, .bit_width = 6, .piece_start = 83, .piece_count = 2 },
-  { .name = "imm4", .signed_hint = -1, .bit_width = 4, .piece_start = 85, .piece_count = 1 },
+  { .name = "SrcTile0", .signed_hint = -1, .bit_width = 6, .piece_start = 83, .piece_count = 1 },
+  { .name = "imm4", .signed_hint = -1, .bit_width = 4, .piece_start = 84, .piece_count = 1 },
+  { .name = "DstTile", .signed_hint = -1, .bit_width = 3, .piece_start = 85, .piece_count = 1 },
   { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 86, .piece_count = 1 },
   { .name = "S0R", .signed_hint = -1, .bit_width = 1, .piece_start = 87, .piece_count = 1 },
   { .name = "S1R", .signed_hint = -1, .bit_width = 1, .piece_start = 88, .piece_count = 1 },
-  { .name = "SrcTile0", .signed_hint = -1, .bit_width = 6, .piece_start = 89, .piece_count = 2 },
-  { .name = "SrcTile1", .signed_hint = -1, .bit_width = 6, .piece_start = 91, .piece_count = 1 },
-  { .name = "DstTile", .signed_hint = -1, .bit_width = 3, .piece_start = 92, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 93, .piece_count = 1 },
-  { .name = "S0R", .signed_hint = -1, .bit_width = 1, .piece_start = 94, .piece_count = 1 },
-  { .name = "S1R", .signed_hint = -1, .bit_width = 1, .piece_start = 95, .piece_count = 1 },
-  { .name = "SrcTile0", .signed_hint = -1, .bit_width = 6, .piece_start = 96, .piece_count = 2 },
-  { .name = "SrcTile1", .signed_hint = -1, .bit_width = 6, .piece_start = 98, .piece_count = 1 },
-  { .name = "imm4", .signed_hint = -1, .bit_width = 4, .piece_start = 99, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 100, .piece_count = 1 },
-  { .name = "S0R", .signed_hint = -1, .bit_width = 1, .piece_start = 101, .piece_count = 1 },
-  { .name = "SrcTile0", .signed_hint = -1, .bit_width = 6, .piece_start = 102, .piece_count = 2 },
-  { .name = "DstTile", .signed_hint = -1, .bit_width = 3, .piece_start = 104, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 105, .piece_count = 1 },
-  { .name = "imm4", .signed_hint = -1, .bit_width = 4, .piece_start = 106, .piece_count = 1 },
+  { .name = "SrcTile0", .signed_hint = -1, .bit_width = 6, .piece_start = 89, .piece_count = 1 },
+  { .name = "SrcTile1", .signed_hint = -1, .bit_width = 6, .piece_start = 90, .piece_count = 1 },
+  { .name = "imm4", .signed_hint = -1, .bit_width = 4, .piece_start = 91, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 92, .piece_count = 1 },
+  { .name = "S0R", .signed_hint = -1, .bit_width = 1, .piece_start = 93, .piece_count = 1 },
+  { .name = "SrcTile0", .signed_hint = -1, .bit_width = 6, .piece_start = 94, .piece_count = 1 },
+  { .name = "DstTile", .signed_hint = -1, .bit_width = 3, .piece_start = 95, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 96, .piece_count = 1 },
+  { .name = "imm4", .signed_hint = -1, .bit_width = 4, .piece_start = 97, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 98, .piece_count = 1 },
+  { .name = "S0R", .signed_hint = -1, .bit_width = 1, .piece_start = 99, .piece_count = 1 },
+  { .name = "S1R", .signed_hint = -1, .bit_width = 1, .piece_start = 100, .piece_count = 1 },
+  { .name = "SrcTile0", .signed_hint = -1, .bit_width = 6, .piece_start = 101, .piece_count = 1 },
+  { .name = "SrcTile1", .signed_hint = -1, .bit_width = 6, .piece_start = 102, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 103, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 104, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 105, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 107, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 108, .piece_count = 1 },
   { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 109, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 111, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 112, .piece_count = 1 },
   { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 113, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 115, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 116, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 117, .piece_count = 2 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 119, .piece_count = 2 },
-  { .name = "simm25", .signed_hint = 1, .bit_width = 25, .piece_start = 121, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 122, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 124, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 115, .piece_count = 2 },
+  { .name = "simm25", .signed_hint = 1, .bit_width = 25, .piece_start = 117, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 118, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 120, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 121, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 122, .piece_count = 1 },
+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 123, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 124, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 125, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 126, .piece_count = 1 },
   { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 127, .piece_count = 1 },
@@ -3524,38 +3521,38 @@ const linxisa_field linxisa_fields[] = {
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 130, .piece_count = 1 },
   { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 131, .piece_count = 1 },
   { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 132, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 133, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 134, .piece_count = 1 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 135, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 136, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 137, .piece_count = 1 },
-  { .name = "simm25", .signed_hint = 1, .bit_width = 25, .piece_start = 138, .piece_count = 1 },
-  { .name = "simm25", .signed_hint = 1, .bit_width = 25, .piece_start = 139, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 140, .piece_count = 1 },
-  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 141, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 142, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 133, .piece_count = 1 },
+  { .name = "simm25", .signed_hint = 1, .bit_width = 25, .piece_start = 134, .piece_count = 1 },
+  { .name = "simm25", .signed_hint = 1, .bit_width = 25, .piece_start = 135, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 136, .piece_count = 1 },
+  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 137, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 138, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 139, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 140, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 141, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 142, .piece_count = 1 },
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 143, .piece_count = 1 },
-  { .name = "Function", .signed_hint = -1, .bit_width = 5, .piece_start = 144, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 144, .piece_count = 1 },
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 145, .piece_count = 1 },
-  { .name = "Function", .signed_hint = -1, .bit_width = 5, .piece_start = 146, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 147, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 148, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 149, .piece_count = 1 },
+  { .name = "Mode", .signed_hint = -1, .bit_width = 2, .piece_start = 146, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 147, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 148, .piece_count = 1 },
+  { .name = "Mode", .signed_hint = -1, .bit_width = 2, .piece_start = 149, .piece_count = 1 },
   { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 150, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 151, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 152, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 153, .piece_count = 1 },
-  { .name = "Mode", .signed_hint = -1, .bit_width = 2, .piece_start = 154, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 151, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 152, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 153, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 154, .piece_count = 1 },
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 155, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 156, .piece_count = 1 },
+  { .name = "Function", .signed_hint = -1, .bit_width = 5, .piece_start = 156, .piece_count = 1 },
   { .name = "Mode", .signed_hint = -1, .bit_width = 2, .piece_start = 157, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 158, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 159, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 160, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 161, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 162, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 158, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 159, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 160, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 161, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 162, .piece_count = 1 },
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 163, .piece_count = 1 },
-  { .name = "TileOpcode", .signed_hint = -1, .bit_width = 10, .piece_start = 164, .piece_count = 1 },
+  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 164, .piece_count = 1 },
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 165, .piece_count = 1 },
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 166, .piece_count = 1 },
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 167, .piece_count = 1 },
@@ -3565,102 +3562,102 @@ const linxisa_field linxisa_fields[] = {
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 171, .piece_count = 1 },
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 172, .piece_count = 1 },
   { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 173, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 174, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 175, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 176, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 177, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 178, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 179, .piece_count = 1 },
-  { .name = "DataType", .signed_hint = -1, .bit_width = 5, .piece_start = 180, .piece_count = 1 },
-  { .name = "Mode", .signed_hint = -1, .bit_width = 2, .piece_start = 181, .piece_count = 1 },
-  { .name = "Mode", .signed_hint = -1, .bit_width = 2, .piece_start = 182, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 183, .piece_count = 1 },
+  { .name = "Mode", .signed_hint = -1, .bit_width = 2, .piece_start = 174, .piece_count = 1 },
+  { .name = "Mode", .signed_hint = -1, .bit_width = 2, .piece_start = 175, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 176, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 177, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 178, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 179, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 180, .piece_count = 1 },
+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 181, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 182, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 183, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 184, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 185, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 186, .piece_count = 1 },
+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 185, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 186, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 187, .piece_count = 1 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 188, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 189, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 190, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 188, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 189, .piece_count = 1 },
+  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 190, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 191, .piece_count = 1 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 192, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 193, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 194, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 195, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 196, .piece_count = 1 },
-  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 197, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 198, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 199, .piece_count = 1 },
-  { .name = "LoopNest", .signed_hint = -1, .bit_width = 3, .piece_start = 200, .piece_count = 1 },
-  { .name = "RegSrc", .signed_hint = -1, .bit_width = 5, .piece_start = 201, .piece_count = 1 },
-  { .name = "LoopNest", .signed_hint = -1, .bit_width = 2, .piece_start = 202, .piece_count = 1 },
-  { .name = "imm8", .signed_hint = -1, .bit_width = 8, .piece_start = 203, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 204, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 205, .piece_count = 1 },
-  { .name = "BrType", .signed_hint = -1, .bit_width = 3, .piece_start = 206, .piece_count = 1 },
-  { .name = "BrType", .signed_hint = -1, .bit_width = 3, .piece_start = 207, .piece_count = 1 },
-  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 208, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 192, .piece_count = 1 },
+  { .name = "LoopNest", .signed_hint = -1, .bit_width = 3, .piece_start = 193, .piece_count = 1 },
+  { .name = "RegSrc", .signed_hint = -1, .bit_width = 5, .piece_start = 194, .piece_count = 1 },
+  { .name = "LoopNest", .signed_hint = -1, .bit_width = 2, .piece_start = 195, .piece_count = 1 },
+  { .name = "imm8", .signed_hint = -1, .bit_width = 8, .piece_start = 196, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 197, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 198, .piece_count = 1 },
+  { .name = "BrType", .signed_hint = -1, .bit_width = 3, .piece_start = 199, .piece_count = 1 },
+  { .name = "BrType", .signed_hint = -1, .bit_width = 3, .piece_start = 200, .piece_count = 1 },
+  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 201, .piece_count = 1 },
+  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 202, .piece_count = 1 },
+  { .name = "imm5", .signed_hint = -1, .bit_width = 5, .piece_start = 203, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 204, .piece_count = 1 },
+  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 205, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 206, .piece_count = 1 },
+  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 207, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 208, .piece_count = 1 },
   { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 209, .piece_count = 1 },
-  { .name = "imm5", .signed_hint = -1, .bit_width = 5, .piece_start = 210, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 210, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 211, .piece_count = 1 },
-  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 212, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 213, .piece_count = 1 },
-  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 214, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 215, .piece_count = 1 },
-  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 216, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 217, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 212, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 213, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 214, .piece_count = 1 },
+  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 215, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 216, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 217, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 218, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 219, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 220, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 221, .piece_count = 1 },
-  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 222, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 219, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 220, .piece_count = 1 },
+  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 221, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 222, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 223, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 224, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 225, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 226, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 227, .piece_count = 1 },
-  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 228, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 229, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 224, .piece_count = 1 },
+  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 225, .piece_count = 1 },
+  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 226, .piece_count = 1 },
+  { .name = "SSRID", .signed_hint = -1, .bit_width = 5, .piece_start = 227, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 228, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 229, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 230, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 231, .piece_count = 1 },
-  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 232, .piece_count = 1 },
-  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 233, .piece_count = 1 },
-  { .name = "SSRID", .signed_hint = -1, .bit_width = 5, .piece_start = 234, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 235, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 236, .piece_count = 1 },
+  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 231, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 232, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 233, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 234, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 235, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 236, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 237, .piece_count = 1 },
-  { .name = "simm5", .signed_hint = 1, .bit_width = 5, .piece_start = 238, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 239, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 240, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 241, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 242, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 243, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 244, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 245, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 246, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 247, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 248, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 249, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 250, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 251, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 252, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 253, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 254, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 255, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 256, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 257, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 258, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 259, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 260, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 261, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 262, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 263, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 264, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 265, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 266, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 267, .piece_count = 1 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 268, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 269, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 238, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 239, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 240, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 241, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 242, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 243, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 244, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 245, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 246, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 247, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 248, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 249, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 250, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 251, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 252, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 253, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 254, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 255, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 256, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 257, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 258, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 259, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 260, .piece_count = 1 },
+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 261, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 262, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 263, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 264, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 265, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 266, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 267, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 268, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 269, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 270, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 271, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 272, .piece_count = 1 },
@@ -3681,28 +3678,28 @@ const linxisa_field linxisa_fields[] = {
   { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 287, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 288, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 289, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 290, .piece_count = 1 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 290, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 291, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 292, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 293, .piece_count = 1 },
   { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 294, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 295, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 296, .piece_count = 1 },
-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 297, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 297, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 298, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 299, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 300, .piece_count = 1 },
   { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 301, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 302, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 303, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 304, .piece_count = 1 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 304, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 305, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 306, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 307, .piece_count = 1 },
   { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 308, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 309, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 310, .piece_count = 1 },
-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 311, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 311, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 312, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 313, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 314, .piece_count = 1 },
@@ -3712,204 +3709,204 @@ const linxisa_field linxisa_fields[] = {
   { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 318, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 319, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 320, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 321, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 322, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 323, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 324, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 325, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 326, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 327, .piece_count = 1 },
-  { .name = "SrcP", .signed_hint = -1, .bit_width = 5, .piece_start = 328, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 329, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 330, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 331, .piece_count = 1 },
+  { .name = "SrcP", .signed_hint = -1, .bit_width = 5, .piece_start = 321, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 322, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 323, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 324, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 325, .piece_count = 1 },
+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 326, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 327, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 328, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 329, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 330, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 331, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 332, .piece_count = 1 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 333, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 334, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 335, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 333, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 334, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 335, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 336, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 337, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 338, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 337, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 338, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 339, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 340, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 341, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 342, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 343, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 344, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 345, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 346, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 347, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 348, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 349, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 350, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 351, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 352, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 353, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 354, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 355, .piece_count = 1 },
-  { .name = "imm4", .signed_hint = -1, .bit_width = 4, .piece_start = 356, .piece_count = 1 },
-  { .name = "RegSrc0", .signed_hint = -1, .bit_width = 5, .piece_start = 357, .piece_count = 1 },
-  { .name = "RegSrc1", .signed_hint = -1, .bit_width = 5, .piece_start = 358, .piece_count = 1 },
-  { .name = "RegSrc2", .signed_hint = -1, .bit_width = 5, .piece_start = 359, .piece_count = 1 },
-  { .name = "RegSrc0", .signed_hint = -1, .bit_width = 5, .piece_start = 360, .piece_count = 1 },
-  { .name = "RegSrc1", .signed_hint = -1, .bit_width = 5, .piece_start = 361, .piece_count = 1 },
-  { .name = "RegSrc2", .signed_hint = -1, .bit_width = 5, .piece_start = 362, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 363, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 364, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 365, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 366, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 367, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 368, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 369, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 370, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 371, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 372, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 373, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 374, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 375, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 376, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 377, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 378, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 379, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 380, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 381, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 382, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 383, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 384, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 385, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 386, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 340, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 341, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 342, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 343, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 344, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 345, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 346, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 347, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 348, .piece_count = 1 },
+  { .name = "imm4", .signed_hint = -1, .bit_width = 4, .piece_start = 349, .piece_count = 1 },
+  { .name = "RegSrc0", .signed_hint = -1, .bit_width = 5, .piece_start = 350, .piece_count = 1 },
+  { .name = "RegSrc1", .signed_hint = -1, .bit_width = 5, .piece_start = 351, .piece_count = 1 },
+  { .name = "RegSrc2", .signed_hint = -1, .bit_width = 5, .piece_start = 352, .piece_count = 1 },
+  { .name = "RegSrc0", .signed_hint = -1, .bit_width = 5, .piece_start = 353, .piece_count = 1 },
+  { .name = "RegSrc1", .signed_hint = -1, .bit_width = 5, .piece_start = 354, .piece_count = 1 },
+  { .name = "RegSrc2", .signed_hint = -1, .bit_width = 5, .piece_start = 355, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 356, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 357, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 358, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 359, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 360, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 361, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 362, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 363, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 364, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 365, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 366, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 367, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 368, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 369, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 370, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 371, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 372, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 373, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 374, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 375, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 376, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 377, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 378, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 379, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 380, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 381, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 382, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 383, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 384, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 385, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 386, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 387, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 388, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 389, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 390, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 391, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 392, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 393, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 394, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 395, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 396, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 397, .piece_count = 1 },
-  { .name = "PRED_IMM", .signed_hint = -1, .bit_width = 4, .piece_start = 398, .piece_count = 1 },
-  { .name = "SUCC_IMM", .signed_hint = -1, .bit_width = 4, .piece_start = 399, .piece_count = 1 },
-  { .name = "SrcBegin", .signed_hint = -1, .bit_width = 5, .piece_start = 400, .piece_count = 1 },
-  { .name = "SrcEnd", .signed_hint = -1, .bit_width = 5, .piece_start = 401, .piece_count = 1 },
-  { .name = "uimm", .signed_hint = 0, .bit_width = 15, .piece_start = 402, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 404, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 405, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 406, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 407, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 408, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 409, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 410, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 389, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 390, .piece_count = 1 },
+  { .name = "PRED_IMM", .signed_hint = -1, .bit_width = 4, .piece_start = 391, .piece_count = 1 },
+  { .name = "SUCC_IMM", .signed_hint = -1, .bit_width = 4, .piece_start = 392, .piece_count = 1 },
+  { .name = "SrcBegin", .signed_hint = -1, .bit_width = 5, .piece_start = 393, .piece_count = 1 },
+  { .name = "SrcEnd", .signed_hint = -1, .bit_width = 5, .piece_start = 394, .piece_count = 1 },
+  { .name = "uimm", .signed_hint = 0, .bit_width = 15, .piece_start = 395, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 397, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 398, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 399, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 400, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 401, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 402, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 403, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 404, .piece_count = 1 },
+  { .name = "DstBegin", .signed_hint = -1, .bit_width = 5, .piece_start = 405, .piece_count = 1 },
+  { .name = "DstEnd", .signed_hint = -1, .bit_width = 5, .piece_start = 406, .piece_count = 1 },
+  { .name = "uimm", .signed_hint = 0, .bit_width = 15, .piece_start = 407, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 409, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 410, .piece_count = 1 },
   { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 411, .piece_count = 1 },
-  { .name = "DstBegin", .signed_hint = -1, .bit_width = 5, .piece_start = 412, .piece_count = 1 },
-  { .name = "DstEnd", .signed_hint = -1, .bit_width = 5, .piece_start = 413, .piece_count = 1 },
-  { .name = "uimm", .signed_hint = 0, .bit_width = 15, .piece_start = 414, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 412, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 413, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 414, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 415, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 416, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 417, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 418, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 419, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 420, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 421, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 422, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 423, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 424, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 425, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 426, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 427, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 428, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 429, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 430, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 431, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 432, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 433, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 434, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 435, .piece_count = 1 },
-  { .name = "SrcA", .signed_hint = -1, .bit_width = 5, .piece_start = 436, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 437, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 438, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 439, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 440, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 441, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 442, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 443, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 444, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 445, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 446, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 447, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 448, .piece_count = 1 },
-  { .name = "SrcA", .signed_hint = -1, .bit_width = 5, .piece_start = 449, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 450, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 451, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 452, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 453, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 454, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 455, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 456, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 457, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 458, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 459, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 460, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 461, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 462, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 463, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 464, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 465, .piece_count = 1 },
-  { .name = "SrcA", .signed_hint = -1, .bit_width = 5, .piece_start = 466, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 467, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 468, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 469, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 470, .piece_count = 1 },
-  { .name = "SrcA", .signed_hint = -1, .bit_width = 5, .piece_start = 471, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 472, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 473, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 474, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 475, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 476, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 477, .piece_count = 1 },
-  { .name = "DstBegin", .signed_hint = -1, .bit_width = 5, .piece_start = 478, .piece_count = 1 },
-  { .name = "DstEnd", .signed_hint = -1, .bit_width = 5, .piece_start = 479, .piece_count = 1 },
-  { .name = "uimm", .signed_hint = 0, .bit_width = 15, .piece_start = 480, .piece_count = 2 },
-  { .name = "DstBegin", .signed_hint = -1, .bit_width = 5, .piece_start = 482, .piece_count = 1 },
-  { .name = "DstEnd", .signed_hint = -1, .bit_width = 5, .piece_start = 483, .piece_count = 1 },
-  { .name = "uimm", .signed_hint = 0, .bit_width = 15, .piece_start = 484, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 418, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 419, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 420, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 421, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 422, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 423, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 424, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 425, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 426, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 427, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 428, .piece_count = 1 },
+  { .name = "SrcA", .signed_hint = -1, .bit_width = 5, .piece_start = 429, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 430, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 431, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 432, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 433, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 434, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 435, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 436, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 437, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 438, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 439, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 440, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 441, .piece_count = 1 },
+  { .name = "SrcA", .signed_hint = -1, .bit_width = 5, .piece_start = 442, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 443, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 444, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 445, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 446, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 447, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 448, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 449, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 450, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 451, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 452, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 453, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 454, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 455, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 456, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 457, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 458, .piece_count = 1 },
+  { .name = "SrcA", .signed_hint = -1, .bit_width = 5, .piece_start = 459, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 460, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 461, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 462, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 463, .piece_count = 1 },
+  { .name = "SrcA", .signed_hint = -1, .bit_width = 5, .piece_start = 464, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 465, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 466, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 467, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 468, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 469, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 470, .piece_count = 1 },
+  { .name = "DstBegin", .signed_hint = -1, .bit_width = 5, .piece_start = 471, .piece_count = 1 },
+  { .name = "DstEnd", .signed_hint = -1, .bit_width = 5, .piece_start = 472, .piece_count = 1 },
+  { .name = "uimm", .signed_hint = 0, .bit_width = 15, .piece_start = 473, .piece_count = 2 },
+  { .name = "DstBegin", .signed_hint = -1, .bit_width = 5, .piece_start = 475, .piece_count = 1 },
+  { .name = "DstEnd", .signed_hint = -1, .bit_width = 5, .piece_start = 476, .piece_count = 1 },
+  { .name = "uimm", .signed_hint = 0, .bit_width = 15, .piece_start = 477, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 479, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 480, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 481, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 482, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 483, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 484, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 485, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 486, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 487, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 488, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 489, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 490, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 491, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 492, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 493, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 494, .piece_count = 1 },
-  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 495, .piece_count = 2 },
+  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 488, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 490, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 491, .piece_count = 1 },
+  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 492, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 494, .piece_count = 1 },
+  { .name = "imm32", .signed_hint = -1, .bit_width = 32, .piece_start = 495, .piece_count = 2 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 497, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 498, .piece_count = 1 },
-  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 499, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 499, .piece_count = 2 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 501, .piece_count = 1 },
-  { .name = "imm32", .signed_hint = -1, .bit_width = 32, .piece_start = 502, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 504, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 505, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 506, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 508, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 509, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 510, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 512, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 513, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 514, .piece_count = 1 },
-  { .name = "immr", .signed_hint = -1, .bit_width = 6, .piece_start = 515, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 516, .piece_count = 1 },
-  { .name = "simm25", .signed_hint = 1, .bit_width = 25, .piece_start = 517, .piece_count = 1 },
-  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 518, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 519, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 521, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 523, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 525, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 527, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 529, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 531, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 533, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 535, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 502, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 503, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 505, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 506, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 507, .piece_count = 1 },
+  { .name = "immr", .signed_hint = -1, .bit_width = 6, .piece_start = 508, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 509, .piece_count = 1 },
+  { .name = "simm25", .signed_hint = 1, .bit_width = 25, .piece_start = 510, .piece_count = 1 },
+  { .name = "uimm5", .signed_hint = 0, .bit_width = 5, .piece_start = 511, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 512, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 514, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 516, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 518, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 520, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 522, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 524, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 526, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 30, .piece_start = 528, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 530, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 531, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 532, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 533, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 534, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 535, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 536, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 537, .piece_count = 1 },
   { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 538, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 539, .piece_count = 1 },
@@ -3931,1883 +3928,1881 @@ const linxisa_field linxisa_fields[] = {
   { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 555, .piece_count = 1 },
   { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 556, .piece_count = 1 },
   { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 557, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 558, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 559, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 558, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 559, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 560, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 561, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 562, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 563, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 564, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 565, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 566, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 567, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 568, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 7, .piece_start = 569, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 570, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 571, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 572, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 573, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 7, .piece_start = 574, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 575, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 576, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 577, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 579, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 580, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 581, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 583, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 584, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 585, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 587, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 588, .piece_count = 1 },
-  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 589, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 591, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 592, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 593, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 595, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 596, .piece_count = 1 },
-  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 597, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 599, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 600, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 601, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 603, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 604, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 605, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 607, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 608, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 609, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 610, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 611, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 612, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 613, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 614, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 615, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 616, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 617, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 618, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 7, .piece_start = 562, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 563, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 564, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 565, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 566, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 7, .piece_start = 567, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 568, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 569, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 570, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 572, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 573, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 574, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 576, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 577, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 578, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 580, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 581, .piece_count = 1 },
+  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 582, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 584, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 585, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 586, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 588, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 589, .piece_count = 1 },
+  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 590, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 592, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 593, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 594, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 596, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 597, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 598, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 600, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 601, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 602, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 603, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 604, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 605, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 606, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 607, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 608, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 609, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 610, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 611, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 612, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 613, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 614, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 615, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 616, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 617, .piece_count = 2 },
   { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 619, .piece_count = 1 },
   { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 620, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 621, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 622, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 623, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 624, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 626, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 627, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 628, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 629, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 630, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 631, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 632, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 633, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 634, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 635, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 636, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 637, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 638, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 639, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 640, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 642, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 643, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 644, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 645, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 647, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 648, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 649, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 650, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 652, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 653, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 654, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 655, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 657, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 658, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 659, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 660, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 661, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 662, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 663, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 664, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 666, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 667, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 668, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 669, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 670, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 671, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 672, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 673, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 674, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 675, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 676, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 677, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 678, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 679, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 680, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 682, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 683, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 684, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 685, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 687, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 688, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 689, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 690, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 692, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 693, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 694, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 695, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 697, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 698, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 699, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 700, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 701, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 702, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 703, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 704, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 706, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 707, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 708, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 709, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 710, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 711, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 712, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 713, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 714, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 715, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 716, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 717, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 718, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 719, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 720, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 722, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 723, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 724, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 725, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 727, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 728, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 729, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 730, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 732, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 733, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 734, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 736, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 737, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 738, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 739, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 741, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 742, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 743, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 744, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 746, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 747, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 748, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 749, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 751, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 752, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 753, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 754, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 756, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 757, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 758, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 759, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 760, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 761, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 762, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 763, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 765, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 766, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 767, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 768, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 769, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 770, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 771, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 772, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 773, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 774, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 775, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 776, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 777, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 778, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 779, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 781, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 782, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 783, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 784, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 786, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 787, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 788, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 789, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 791, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 792, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 793, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 795, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 796, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 797, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 798, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 800, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 801, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 802, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 803, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 805, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 806, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 807, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 808, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 810, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 811, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 812, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 813, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 815, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 816, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 817, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 818, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 819, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 820, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 821, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 822, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 824, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 825, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 826, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 827, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 828, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 829, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 830, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 831, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 832, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 833, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 834, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 835, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 836, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 837, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 838, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 840, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 841, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 842, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 843, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 845, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 846, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 847, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 848, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 850, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 851, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 852, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 854, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 855, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 856, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 857, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 859, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 860, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 861, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 862, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 864, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 865, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 866, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 867, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 869, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 870, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 871, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 872, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 874, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 875, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 876, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 877, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 878, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 879, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 880, .piece_count = 1 },
-  { .name = "simm32", .signed_hint = 1, .bit_width = 32, .piece_start = 881, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 883, .piece_count = 1 },
-  { .name = "uimm32", .signed_hint = 0, .bit_width = 32, .piece_start = 884, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 886, .piece_count = 1 },
-  { .name = "imm", .signed_hint = -1, .bit_width = 32, .piece_start = 887, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 889, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 890, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 892, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 893, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 894, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 895, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 896, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 897, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 898, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 899, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 900, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 901, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 902, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 903, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 904, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 905, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 906, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 908, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 909, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 910, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 911, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 913, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 914, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 915, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 916, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 918, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 919, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 920, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 922, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 923, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 924, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 925, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 927, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 928, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 929, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 930, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 932, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 933, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 934, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 935, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 937, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 938, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 939, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 940, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 942, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 943, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 944, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 945, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 946, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 947, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 948, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 949, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 951, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 952, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 953, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 954, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 955, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 956, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 957, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 958, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 959, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 960, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 961, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 962, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 963, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 964, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 965, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 967, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 968, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 969, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 970, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 972, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 973, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 974, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 975, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 977, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 978, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 979, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 981, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 982, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 983, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 984, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 986, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 987, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 988, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 989, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 991, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 992, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 993, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 994, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 996, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 997, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 998, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 999, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1001, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1002, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 623, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 624, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 625, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 626, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 627, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 628, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 629, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 630, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 631, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 632, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 633, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 635, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 636, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 637, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 638, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 640, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 641, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 642, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 643, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 645, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 646, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 647, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 648, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 650, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 651, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 652, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 653, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 654, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 655, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 656, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 657, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 659, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 660, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 661, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 662, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 663, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 664, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 665, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 666, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 667, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 668, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 669, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 670, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 671, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 672, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 673, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 675, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 676, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 677, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 678, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 680, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 681, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 682, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 683, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 685, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 686, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 687, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 688, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 690, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 691, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 692, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 693, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 694, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 695, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 696, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 697, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 699, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 700, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 701, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 702, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 703, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 704, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 705, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 706, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 707, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 708, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 709, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 710, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 711, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 712, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 713, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 715, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 716, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 717, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 718, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 720, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 721, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 722, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 723, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 725, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 726, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 727, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 729, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 730, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 731, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 732, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 734, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 735, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 736, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 737, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 739, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 740, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 741, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 742, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 744, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 745, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 746, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 747, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 749, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 750, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 751, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 752, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 753, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 754, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 755, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 756, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 758, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 759, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 760, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 761, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 762, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 763, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 764, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 765, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 766, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 767, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 768, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 769, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 770, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 771, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 772, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 774, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 775, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 776, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 777, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 779, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 780, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 781, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 782, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 784, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 785, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 786, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 788, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 789, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 790, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 791, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 793, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 794, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 795, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 796, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 798, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 799, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 800, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 801, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 803, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 804, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 805, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 806, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 808, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 809, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 810, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 811, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 812, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 813, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 814, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 815, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 817, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 818, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 819, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 820, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 821, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 822, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 823, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 824, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 825, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 826, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 827, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 828, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 829, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 830, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 831, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 833, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 834, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 835, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 836, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 838, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 839, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 840, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 841, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 843, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 844, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 845, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 847, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 848, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 849, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 850, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 852, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 853, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 854, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 855, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 857, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 858, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 859, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 860, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 862, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 863, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 864, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 865, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 867, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 868, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 869, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 870, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 871, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 872, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 873, .piece_count = 1 },
+  { .name = "simm32", .signed_hint = 1, .bit_width = 32, .piece_start = 874, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 876, .piece_count = 1 },
+  { .name = "uimm32", .signed_hint = 0, .bit_width = 32, .piece_start = 877, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 879, .piece_count = 1 },
+  { .name = "imm", .signed_hint = -1, .bit_width = 32, .piece_start = 880, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 882, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 883, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 885, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 886, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 887, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 888, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 889, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 890, .piece_count = 1 },
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+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 892, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 893, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 894, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 895, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 896, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 897, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 898, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 899, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 901, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 902, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 903, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 904, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 906, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 907, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 908, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 909, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 911, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 912, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 913, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 915, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 916, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 917, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 918, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 920, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 921, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 922, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 923, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 925, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 926, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 927, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 928, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 930, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 931, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 932, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 933, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 935, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 936, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 937, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 938, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 939, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 940, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 941, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 942, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 944, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 945, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 946, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 947, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 948, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 949, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 950, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 951, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 952, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 953, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 954, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 955, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 956, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 957, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 958, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 960, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 961, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 962, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 963, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 965, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 966, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 967, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 968, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 970, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 971, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 972, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 974, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 975, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 976, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 977, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 979, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 980, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 981, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 982, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 984, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 985, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 986, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 987, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 989, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 990, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 991, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 992, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 994, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 995, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 996, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 997, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 998, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 999, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1000, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1001, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1002, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1003, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1004, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1005, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1006, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1007, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1008, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1009, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1010, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1011, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1012, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1013, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1014, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1015, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1016, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1017, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1018, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1019, .piece_count = 1 },
-  { .name = "uimm19", .signed_hint = 0, .bit_width = 19, .piece_start = 1020, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1022, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1023, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1024, .piece_count = 1 },
-  { .name = "uimm19", .signed_hint = 0, .bit_width = 19, .piece_start = 1025, .piece_count = 2 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1027, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1028, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1005, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1006, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1007, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1008, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1009, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1010, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1011, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1012, .piece_count = 1 },
+  { .name = "uimm19", .signed_hint = 0, .bit_width = 19, .piece_start = 1013, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1015, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1016, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1017, .piece_count = 1 },
+  { .name = "uimm19", .signed_hint = 0, .bit_width = 19, .piece_start = 1018, .piece_count = 2 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1020, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1021, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1022, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1023, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1024, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1025, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1026, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1027, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1028, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1029, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1030, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1031, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1032, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1030, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1032, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1033, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1034, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1035, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1034, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1036, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1037, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1039, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1040, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1041, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1043, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1044, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1045, .piece_count = 1 },
-  { .name = "model", .signed_hint = -1, .bit_width = 5, .piece_start = 1046, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1047, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1048, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1049, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1050, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1051, .piece_count = 1 },
-  { .name = "model", .signed_hint = -1, .bit_width = 5, .piece_start = 1052, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1053, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1054, .piece_count = 1 },
-  { .name = "model", .signed_hint = -1, .bit_width = 5, .piece_start = 1055, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1056, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1058, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1059, .piece_count = 1 },
-  { .name = "model", .signed_hint = -1, .bit_width = 5, .piece_start = 1060, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1061, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1063, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1064, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1065, .piece_count = 1 },
-  { .name = "e", .signed_hint = -1, .bit_width = 1, .piece_start = 1066, .piece_count = 1 },
-  { .name = "i", .signed_hint = -1, .bit_width = 1, .piece_start = 1067, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1037, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1038, .piece_count = 1 },
+  { .name = "model", .signed_hint = -1, .bit_width = 5, .piece_start = 1039, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1040, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1041, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1042, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1043, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1044, .piece_count = 1 },
+  { .name = "model", .signed_hint = -1, .bit_width = 5, .piece_start = 1045, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1046, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1047, .piece_count = 1 },
+  { .name = "model", .signed_hint = -1, .bit_width = 5, .piece_start = 1048, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1049, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1051, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1052, .piece_count = 1 },
+  { .name = "model", .signed_hint = -1, .bit_width = 5, .piece_start = 1053, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1054, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1056, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1057, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1058, .piece_count = 1 },
+  { .name = "e", .signed_hint = -1, .bit_width = 1, .piece_start = 1059, .piece_count = 1 },
+  { .name = "i", .signed_hint = -1, .bit_width = 1, .piece_start = 1060, .piece_count = 1 },
+  { .name = "r", .signed_hint = -1, .bit_width = 1, .piece_start = 1061, .piece_count = 1 },
+  { .name = "s", .signed_hint = -1, .bit_width = 1, .piece_start = 1062, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1063, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1064, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1065, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1066, .piece_count = 1 },
+  { .name = "e", .signed_hint = -1, .bit_width = 1, .piece_start = 1067, .piece_count = 1 },
   { .name = "r", .signed_hint = -1, .bit_width = 1, .piece_start = 1068, .piece_count = 1 },
-  { .name = "s", .signed_hint = -1, .bit_width = 1, .piece_start = 1069, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1070, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1071, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1072, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1073, .piece_count = 1 },
-  { .name = "e", .signed_hint = -1, .bit_width = 1, .piece_start = 1074, .piece_count = 1 },
-  { .name = "r", .signed_hint = -1, .bit_width = 1, .piece_start = 1075, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1076, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1069, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1070, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1071, .piece_count = 1 },
+  { .name = "e", .signed_hint = -1, .bit_width = 1, .piece_start = 1072, .piece_count = 1 },
+  { .name = "h", .signed_hint = -1, .bit_width = 1, .piece_start = 1073, .piece_count = 1 },
+  { .name = "r", .signed_hint = -1, .bit_width = 1, .piece_start = 1074, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1075, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1076, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1077, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1078, .piece_count = 1 },
-  { .name = "e", .signed_hint = -1, .bit_width = 1, .piece_start = 1079, .piece_count = 1 },
-  { .name = "h", .signed_hint = -1, .bit_width = 1, .piece_start = 1080, .piece_count = 1 },
-  { .name = "r", .signed_hint = -1, .bit_width = 1, .piece_start = 1081, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1082, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1083, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1084, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1085, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1086, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1087, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1088, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1089, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1090, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1091, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1092, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1093, .piece_count = 1 },
-  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1094, .piece_count = 1 },
-  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1095, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1096, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1097, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1098, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 1099, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1102, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1103, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1104, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1105, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1106, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1107, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1108, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1109, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1110, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1111, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1112, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1113, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1114, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1117, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1118, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1119, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1120, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1123, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1124, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1125, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1126, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1129, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1130, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1079, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1080, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1081, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1082, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1083, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1084, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1085, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1086, .piece_count = 1 },
+  { .name = "RegDst0", .signed_hint = -1, .bit_width = 5, .piece_start = 1087, .piece_count = 1 },
+  { .name = "RegDst1", .signed_hint = -1, .bit_width = 5, .piece_start = 1088, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1089, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1090, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1091, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 1092, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1095, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1096, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1097, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1098, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1099, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1100, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1101, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1102, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1103, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1104, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1105, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1106, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1107, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1110, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1111, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1112, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1113, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1116, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1117, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1118, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1119, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1122, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1123, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1124, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1125, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1128, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1129, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1130, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1131, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1132, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1135, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1136, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1137, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1138, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1139, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1140, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 1141, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1144, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1145, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1146, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1147, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1148, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1149, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1150, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1151, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1152, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1153, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1154, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1155, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1156, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1157, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1158, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1159, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1160, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1161, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1162, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1163, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1164, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1165, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1166, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1169, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1170, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1171, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1172, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1175, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1176, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1177, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1178, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1181, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1182, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1183, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1186, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1187, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1188, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1189, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1192, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1193, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1194, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1195, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1198, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1199, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1200, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1201, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1204, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1205, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1132, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1133, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 1134, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1137, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1138, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1139, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1140, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1141, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1142, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1143, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1144, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1145, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1146, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1147, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1148, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1149, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1150, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1151, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1152, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1153, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1154, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1155, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1156, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1157, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1158, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1159, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1162, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1163, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1164, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1165, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1168, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1169, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1170, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1171, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1174, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1175, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1176, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1179, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1180, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1181, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1182, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1185, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1186, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1187, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1188, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1191, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1192, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1193, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1194, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1197, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1198, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1199, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1200, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1203, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1204, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1205, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1206, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1207, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1210, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1211, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1212, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1213, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1214, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1215, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1216, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1207, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1208, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1209, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1210, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1211, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1212, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1213, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1214, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1215, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1217, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1218, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1219, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1220, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1221, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1222, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1224, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1225, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1226, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1228, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1229, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1230, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1232, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1233, .piece_count = 1 },
-  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 1234, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1236, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1237, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1238, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1240, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1241, .piece_count = 1 },
-  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 1242, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1244, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1245, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1246, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1248, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1249, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1250, .piece_count = 2 },
-  { .name = "imm32", .signed_hint = -1, .bit_width = 32, .piece_start = 1252, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1254, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 1255, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1258, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1259, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1260, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1261, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1262, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1263, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1264, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1265, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1266, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1267, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1268, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1269, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1270, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1271, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1272, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1273, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1274, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1275, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1276, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1277, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1278, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1279, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1280, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1283, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1284, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1285, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1286, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1289, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1290, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1291, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1292, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1295, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1296, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1297, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1300, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1301, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1302, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1303, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1306, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1307, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1308, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1309, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1312, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1313, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1314, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1315, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1318, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1319, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1218, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1219, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1221, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1222, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1223, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1225, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1226, .piece_count = 1 },
+  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 1227, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1229, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1230, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1231, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1233, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1234, .piece_count = 1 },
+  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 1235, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1237, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1238, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1239, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1241, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1242, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1243, .piece_count = 2 },
+  { .name = "imm32", .signed_hint = -1, .bit_width = 32, .piece_start = 1245, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1247, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 1248, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1251, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1252, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1253, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1254, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1255, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1256, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1257, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1258, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1259, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1260, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1261, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1262, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1263, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1264, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1265, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1266, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1267, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1268, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1269, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1270, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1271, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1272, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1273, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1276, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1277, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1278, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1279, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1282, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1283, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1284, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1285, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1288, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1289, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1290, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1293, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1294, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1295, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1296, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1299, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1300, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1301, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1302, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1305, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1306, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1307, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1308, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1311, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1312, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1313, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1314, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1317, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1318, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1319, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1320, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1321, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1324, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1325, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1326, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1327, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1328, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1329, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1330, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1331, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1332, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1333, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1334, .piece_count = 1 },
-  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 24, .piece_start = 1335, .piece_count = 2 },
-  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 24, .piece_start = 1337, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1339, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1340, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1321, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1322, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1323, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1324, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1325, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1326, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1327, .piece_count = 1 },
+  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 24, .piece_start = 1328, .piece_count = 2 },
+  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 24, .piece_start = 1330, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1332, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1333, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1334, .piece_count = 1 },
+  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 1335, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1337, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1338, .piece_count = 1 },
+  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 1339, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1341, .piece_count = 1 },
-  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 1342, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1344, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1345, .piece_count = 1 },
-  { .name = "uimm24", .signed_hint = 0, .bit_width = 24, .piece_start = 1346, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1348, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 1349, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1352, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1353, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1354, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1355, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1356, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1357, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1358, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1359, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1360, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1361, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1362, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1363, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1364, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1365, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1366, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1367, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1368, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1369, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1370, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1371, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1372, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1373, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1374, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1377, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1378, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1379, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1380, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1383, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1384, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1385, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1386, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1389, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1390, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1391, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1394, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1395, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1396, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1397, .piece_count = 3 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1400, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1401, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1402, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1403, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1406, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1407, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1408, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1409, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1412, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1413, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 29, .piece_start = 1342, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1345, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1346, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1347, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1348, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1349, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1350, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1351, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1352, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1353, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1354, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1355, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1356, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1357, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1358, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1359, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1360, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1361, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1362, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1363, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1364, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1365, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1366, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1367, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1370, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1371, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1372, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1373, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1376, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1377, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1378, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1379, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1382, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1383, .piece_count = 1 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1384, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1387, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1388, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1389, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1390, .piece_count = 3 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1393, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1394, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1395, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1396, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1399, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1400, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1401, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1402, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1405, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1406, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1407, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1408, .piece_count = 3 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1411, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1412, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1413, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1414, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1415, .piece_count = 3 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1418, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1419, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1420, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1421, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1422, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1423, .piece_count = 1 },
-  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1424, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1425, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1426, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1427, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1428, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1415, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1416, .piece_count = 1 },
+  { .name = "SrcD1", .signed_hint = -1, .bit_width = 5, .piece_start = 1417, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1418, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1419, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1420, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1421, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1422, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1423, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1425, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1426, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1427, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1429, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1430, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1432, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1433, .piece_count = 1 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 1434, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1436, .piece_count = 1 },
-  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1437, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1439, .piece_count = 1 },
-  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1440, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1441, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1443, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1445, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1447, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1449, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1451, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1453, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1455, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1457, .piece_count = 2 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1459, .piece_count = 2 },
+  { .name = "simm22", .signed_hint = 1, .bit_width = 22, .piece_start = 1430, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1432, .piece_count = 1 },
+  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1433, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1434, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1436, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1438, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1440, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1442, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1444, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1446, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1448, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1450, .piece_count = 2 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 42, .piece_start = 1452, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1454, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1455, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1456, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1457, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1458, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1459, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1460, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1461, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1462, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1463, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1464, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1465, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1466, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1467, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1468, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1469, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1470, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1463, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1464, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1465, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1466, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1467, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1468, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1469, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1470, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1471, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1472, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1473, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1474, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1475, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1476, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1477, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1478, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1479, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1480, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1481, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1482, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1483, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1484, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1485, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1486, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1487, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1488, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1489, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1490, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1491, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1492, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1493, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1494, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1495, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1496, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1497, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1498, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1499, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1500, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1501, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1502, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1503, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1504, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1505, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1506, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1507, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1508, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1509, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1510, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1511, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1512, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1513, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1514, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1515, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1516, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1517, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1518, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1519, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1520, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1521, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1522, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1523, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1524, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1525, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1526, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1527, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1528, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1529, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1530, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1531, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1532, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1533, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1534, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1535, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1536, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1537, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1538, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1539, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1540, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1541, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1473, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1474, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1475, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1476, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1477, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1478, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1479, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1480, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1481, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1482, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1483, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1484, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1485, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1486, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1487, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1488, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1489, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1490, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1491, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1492, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1493, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1494, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1495, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1496, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1497, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1498, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1499, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1500, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1501, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1502, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1503, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1504, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1505, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1506, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1507, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1508, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1509, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1510, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1511, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1512, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1513, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1514, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1515, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1516, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1517, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1518, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1519, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1520, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1521, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1522, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1523, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1524, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1525, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1526, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1527, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1528, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1529, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1530, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1531, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1532, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1533, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1534, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1535, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1536, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1537, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1538, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1539, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1540, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1541, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1542, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1543, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1544, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1545, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1546, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1547, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1548, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1549, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1550, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1551, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1552, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1553, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1554, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1544, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1545, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1546, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1547, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1548, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1549, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1550, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1551, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1552, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1553, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1554, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1555, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1556, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1557, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1558, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1559, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1560, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1561, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1562, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1563, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1564, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1565, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1566, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1567, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1568, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1569, .piece_count = 1 },
-  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1570, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1571, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1572, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1573, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1574, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1575, .piece_count = 1 },
-  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1576, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1577, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1578, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1579, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1580, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1581, .piece_count = 1 },
-  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1582, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1583, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1584, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1585, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1557, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1558, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1559, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1560, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1561, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1562, .piece_count = 1 },
+  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1563, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1564, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1565, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1566, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1567, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1568, .piece_count = 1 },
+  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1569, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1570, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1571, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1572, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1573, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1574, .piece_count = 1 },
+  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1575, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1576, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1577, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1578, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1579, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1580, .piece_count = 1 },
+  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1581, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1582, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1583, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1584, .piece_count = 1 },
+  { .name = "LSR_ID", .signed_hint = -1, .bit_width = 12, .piece_start = 1585, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1586, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1587, .piece_count = 1 },
-  { .name = "SrcZero", .signed_hint = -1, .bit_width = 5, .piece_start = 1588, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1589, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1590, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1591, .piece_count = 1 },
-  { .name = "LSR_ID", .signed_hint = -1, .bit_width = 12, .piece_start = 1592, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1593, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1587, .piece_count = 1 },
+  { .name = "imm20", .signed_hint = -1, .bit_width = 20, .piece_start = 1588, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1589, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1590, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1591, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1592, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1593, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1594, .piece_count = 1 },
-  { .name = "imm20", .signed_hint = -1, .bit_width = 20, .piece_start = 1595, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1596, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1597, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1598, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1599, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1600, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1601, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1602, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1603, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1604, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1605, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1606, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1607, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1608, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1609, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1610, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1611, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1612, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1613, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1614, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1615, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1616, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1617, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1618, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1619, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1620, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1621, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1622, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1623, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1624, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1625, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1626, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1627, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1628, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1629, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1630, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1631, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1632, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1633, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1634, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1635, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1636, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1637, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1638, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1639, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1640, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1641, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1642, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1643, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1644, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1645, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1646, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1647, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1648, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1649, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1650, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1651, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1652, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1653, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1654, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1655, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1656, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1595, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1596, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1597, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1598, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1599, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1600, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1601, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1602, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1603, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1604, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1605, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1606, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1607, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1608, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1609, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1610, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1611, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1612, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1613, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1614, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1615, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1616, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1617, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1618, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1619, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1620, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1621, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1622, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1623, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1624, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1625, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1626, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1627, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1628, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1629, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1630, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1631, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1632, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1633, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1634, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1635, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1636, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1637, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1638, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1639, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1640, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1641, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1642, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1643, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1644, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1645, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1646, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1647, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1648, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1649, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1650, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1651, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1652, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1653, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1654, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1655, .piece_count = 1 },
+  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1656, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1657, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1658, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1659, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1660, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1661, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1662, .piece_count = 1 },
-  { .name = "simm17", .signed_hint = 1, .bit_width = 17, .piece_start = 1663, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1664, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1659, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1660, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1661, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1662, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1663, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1664, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1665, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1666, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1666, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1667, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1668, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1669, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1670, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1671, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1668, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1669, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1670, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1671, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1672, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1673, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1674, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1675, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1676, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1677, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1678, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1679, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1680, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1681, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1682, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1683, .piece_count = 1 },
-  { .name = "RegSrc0", .signed_hint = -1, .bit_width = 5, .piece_start = 1684, .piece_count = 1 },
-  { .name = "RegSrc1", .signed_hint = -1, .bit_width = 5, .piece_start = 1685, .piece_count = 1 },
-  { .name = "RegSrc2", .signed_hint = -1, .bit_width = 5, .piece_start = 1686, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1687, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1688, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1689, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1690, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1691, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1692, .piece_count = 1 },
-  { .name = "RegSrc0", .signed_hint = -1, .bit_width = 5, .piece_start = 1693, .piece_count = 1 },
-  { .name = "RegSrc1", .signed_hint = -1, .bit_width = 5, .piece_start = 1694, .piece_count = 1 },
-  { .name = "RegSrc2", .signed_hint = -1, .bit_width = 5, .piece_start = 1695, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1696, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1697, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1698, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1699, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1700, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1701, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1702, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1703, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1704, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1705, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1706, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1707, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1708, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1709, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1710, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1711, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1712, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1713, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1714, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1715, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1716, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1717, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1718, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1719, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1720, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1721, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1722, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1723, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1724, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1725, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1726, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1727, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1728, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1729, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1730, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1731, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1732, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1733, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1734, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1735, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1736, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1737, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1738, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1739, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1740, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1741, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1675, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1676, .piece_count = 1 },
+  { .name = "RegSrc0", .signed_hint = -1, .bit_width = 5, .piece_start = 1677, .piece_count = 1 },
+  { .name = "RegSrc1", .signed_hint = -1, .bit_width = 5, .piece_start = 1678, .piece_count = 1 },
+  { .name = "RegSrc2", .signed_hint = -1, .bit_width = 5, .piece_start = 1679, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1680, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1681, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1682, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1683, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1684, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1685, .piece_count = 1 },
+  { .name = "RegSrc0", .signed_hint = -1, .bit_width = 5, .piece_start = 1686, .piece_count = 1 },
+  { .name = "RegSrc1", .signed_hint = -1, .bit_width = 5, .piece_start = 1687, .piece_count = 1 },
+  { .name = "RegSrc2", .signed_hint = -1, .bit_width = 5, .piece_start = 1688, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1689, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1690, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1691, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1692, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1693, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1694, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1695, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1696, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1697, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1698, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1699, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1700, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1701, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1702, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1703, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1704, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1705, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1706, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1707, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1708, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1709, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1710, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1711, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1712, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1713, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1714, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1715, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1716, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1717, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1718, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1719, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1720, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1721, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1722, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1723, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1724, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1725, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1726, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1727, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1728, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1729, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1730, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1731, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1732, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1733, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1734, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1735, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1736, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1737, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1738, .piece_count = 1 },
+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 1739, .piece_count = 1 },
+  { .name = "immr", .signed_hint = -1, .bit_width = 6, .piece_start = 1740, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1741, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1742, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1743, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1744, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1744, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1745, .piece_count = 1 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 1746, .piece_count = 1 },
-  { .name = "immr", .signed_hint = -1, .bit_width = 6, .piece_start = 1747, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1748, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1749, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1750, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1751, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1752, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 17, .piece_start = 1753, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1755, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1756, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1757, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1759, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1760, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1761, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1762, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1763, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1764, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1765, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1766, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1767, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1768, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1769, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1770, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1771, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1772, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1773, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1774, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1775, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1776, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 17, .piece_start = 1746, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1748, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1749, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1750, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1752, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1753, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1754, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1755, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1756, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1757, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1758, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1759, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1760, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1761, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1762, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1763, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1764, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1765, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1766, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1767, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1768, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1769, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1770, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1771, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1772, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1773, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1774, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1775, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 1776, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1777, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1778, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1779, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 1780, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1781, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1782, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 1783, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1784, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1785, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 1786, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1787, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 1779, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1780, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1781, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1782, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1783, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1784, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1785, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1786, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1787, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1788, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1789, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1790, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1791, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1792, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1793, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1794, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1795, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1796, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1797, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1798, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1790, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1791, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1792, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1793, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1794, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1795, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1796, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 17, .piece_start = 1797, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1799, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1800, .piece_count = 1 },
   { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1801, .piece_count = 1 },
   { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1802, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1803, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 17, .piece_start = 1804, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1806, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1807, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1808, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1809, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1810, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1811, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1812, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1813, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1814, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1804, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1805, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1806, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1807, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1808, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1809, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1810, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1811, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1812, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1813, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1814, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1815, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1816, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1817, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1818, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1819, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1820, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1821, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1822, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1823, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1824, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1825, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1826, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1827, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1828, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1829, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1830, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1831, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1832, .piece_count = 2 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1817, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1818, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1819, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1820, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1821, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1822, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1823, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1824, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1825, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1827, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1828, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1829, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1831, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1832, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1833, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1834, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1835, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1836, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1838, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1839, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1840, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1841, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1842, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1843, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1844, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1845, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1846, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1847, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1848, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1849, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1850, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1851, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1852, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1853, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1854, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1855, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1856, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1857, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1858, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1859, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1860, .piece_count = 1 },
-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 1861, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1862, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1863, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1864, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1865, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1866, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1867, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1868, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1869, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1870, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1871, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1872, .piece_count = 1 },
-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 1873, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1874, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1875, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1876, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1877, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1878, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1879, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1880, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1881, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1882, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1883, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1884, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1885, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1886, .piece_count = 1 },
-  { .name = "imm20", .signed_hint = -1, .bit_width = 20, .piece_start = 1887, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1835, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1836, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1837, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1838, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1839, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1840, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1841, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1842, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1843, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1844, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1845, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1846, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1847, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1848, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1849, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1850, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1851, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1852, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1853, .piece_count = 1 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 1854, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1855, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1856, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1857, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1858, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1859, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1860, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1861, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1862, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1863, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1864, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1865, .piece_count = 1 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 1866, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1867, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1868, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1869, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1870, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1871, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1872, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1873, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1874, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1875, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1876, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1877, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1878, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1879, .piece_count = 1 },
+  { .name = "imm20", .signed_hint = -1, .bit_width = 20, .piece_start = 1880, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1881, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1882, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1883, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1884, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1885, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 17, .piece_start = 1886, .piece_count = 2 },
   { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1888, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1889, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1890, .piece_count = 1 },
   { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1891, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1892, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 17, .piece_start = 1893, .piece_count = 2 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1895, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1893, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1894, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1896, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1897, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1898, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1899, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1900, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1901, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1903, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1904, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1905, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1907, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1908, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1909, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1910, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1911, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 1912, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1913, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1914, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1915, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1916, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1917, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1918, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1919, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1920, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1921, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1922, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1923, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 1924, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1925, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1926, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1927, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1928, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1929, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1930, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1931, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1932, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1933, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1934, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1935, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 1936, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1937, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1938, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1939, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 1898, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1900, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1901, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1902, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1903, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1904, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 1905, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1906, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1907, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1908, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1909, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1910, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1911, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1912, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1913, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1914, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1915, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1916, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 1917, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1918, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1919, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1920, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1921, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1922, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1923, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1924, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1925, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1926, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1927, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1928, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 1929, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1930, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1931, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1932, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1933, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1934, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1935, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1936, .piece_count = 1 },
+  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 12, .piece_start = 1937, .piece_count = 1 },
+  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 12, .piece_start = 1938, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1939, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1940, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1941, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1942, .piece_count = 1 },
+  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 12, .piece_start = 1941, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1942, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1943, .piece_count = 1 },
-  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 12, .piece_start = 1944, .piece_count = 1 },
-  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 12, .piece_start = 1945, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1946, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1947, .piece_count = 1 },
-  { .name = "SSR_ID", .signed_hint = -1, .bit_width = 12, .piece_start = 1948, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1944, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1945, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1946, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1947, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1948, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1949, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1950, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1951, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1952, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1953, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1954, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1955, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1956, .piece_count = 1 },
-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 1957, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1958, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1959, .piece_count = 1 },
-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 1960, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1961, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1962, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1963, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1964, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1965, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1966, .piece_count = 1 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 1950, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1951, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1952, .piece_count = 1 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 1953, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 1954, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1955, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1956, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1957, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 1958, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1959, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1960, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1961, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1962, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1963, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1964, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1965, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1966, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1967, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1968, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1969, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1970, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1971, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1972, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1973, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1974, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1975, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1976, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1977, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1969, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1970, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1971, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1972, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1973, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1974, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1975, .piece_count = 1 },
+  { .name = "simm", .signed_hint = 1, .bit_width = 17, .piece_start = 1976, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1978, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1979, .piece_count = 1 },
   { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1980, .piece_count = 1 },
   { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1981, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1982, .piece_count = 1 },
-  { .name = "simm", .signed_hint = 1, .bit_width = 17, .piece_start = 1983, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1985, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1986, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1987, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1988, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1989, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1990, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1991, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1992, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1993, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1983, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1984, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1985, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 5, .piece_start = 1986, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1987, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1988, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1989, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1990, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1991, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1992, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1993, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1994, .piece_count = 1 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1995, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 1996, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1997, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1998, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 1999, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2000, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2001, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2002, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2003, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2004, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2005, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2006, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2007, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2008, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2009, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2010, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2011, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2012, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2013, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2014, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2015, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2016, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2017, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2018, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2019, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2020, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2021, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2022, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2023, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2024, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2025, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2026, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2027, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2028, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2029, .piece_count = 1 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2030, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2031, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2032, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2033, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2034, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2035, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2037, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2038, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2039, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2041, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2042, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2043, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2044, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2045, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2046, .piece_count = 1 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 2047, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2048, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2050, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2052, .piece_count = 2 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2054, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2055, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2056, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2058, .piece_count = 2 },
-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 2060, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2061, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2063, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2065, .piece_count = 2 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2067, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2068, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2069, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2071, .piece_count = 2 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2073, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2074, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2076, .piece_count = 2 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2078, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2079, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2080, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2082, .piece_count = 2 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2084, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2085, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2086, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2088, .piece_count = 2 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2090, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2091, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2092, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2094, .piece_count = 2 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2096, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2097, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2098, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2100, .piece_count = 2 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2102, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2103, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2104, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2106, .piece_count = 2 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2108, .piece_count = 1 },
-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2109, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2110, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2112, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2114, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2116, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2118, .piece_count = 2 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2120, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2121, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2123, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2125, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2127, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2129, .piece_count = 2 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2131, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2132, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2134, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2136, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2138, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2140, .piece_count = 2 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2142, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2143, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2145, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2147, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2149, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2151, .piece_count = 2 },
-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 2153, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2154, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2156, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2158, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2160, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2162, .piece_count = 2 },
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-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2165, .piece_count = 2 },
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-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 2175, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2176, .piece_count = 2 },
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-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2182, .piece_count = 2 },
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-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2193, .piece_count = 2 },
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-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2197, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2198, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2200, .piece_count = 2 },
-  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 2202, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2204, .piece_count = 2 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2206, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2207, .piece_count = 2 },
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-  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2212, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2213, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2215, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2217, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2219, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2221, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2223, .piece_count = 2 },
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-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2227, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2229, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2231, .piece_count = 2 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2233, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2234, .piece_count = 2 },
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-  { .name = "SrcType", .signed_hint = -1, .bit_width = 5, .piece_start = 2238, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2239, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2240, .piece_count = 2 },
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-  { .name = "SrcType", .signed_hint = -1, .bit_width = 5, .piece_start = 2244, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2245, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2247, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2249, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2251, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2253, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2255, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2257, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2259, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2261, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2263, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2265, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2267, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2269, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2271, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2273, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2275, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2277, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2279, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2281, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2283, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2285, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2287, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2289, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2291, .piece_count = 2 },
-  { .name = "SrcA", .signed_hint = -1, .bit_width = 10, .piece_start = 2293, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2295, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2297, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2299, .piece_count = 2 },
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-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2303, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2305, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2307, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2309, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2311, .piece_count = 2 },
-  { .name = "SrcA", .signed_hint = -1, .bit_width = 10, .piece_start = 2313, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2315, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2317, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2319, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2321, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2323, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2325, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2327, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2329, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2331, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2333, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2335, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2337, .piece_count = 2 },
-  { .name = "SrcA", .signed_hint = -1, .bit_width = 10, .piece_start = 2339, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2341, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2343, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2345, .piece_count = 2 },
-  { .name = "SrcA", .signed_hint = -1, .bit_width = 10, .piece_start = 2347, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2349, .piece_count = 2 },
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-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2353, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2355, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2357, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2359, .piece_count = 2 },
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+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 1997, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 1998, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 1999, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2000, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2001, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2002, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2003, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2004, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2005, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2006, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2007, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2008, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2009, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2010, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2011, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2012, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2013, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2014, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2015, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2016, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2017, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2018, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2019, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2020, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2021, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2022, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2023, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2024, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2025, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2026, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2027, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2028, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2030, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 2031, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2032, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2034, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2035, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2036, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2037, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 2038, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 2039, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 2, .piece_start = 2040, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2041, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2043, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2045, .piece_count = 2 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2047, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2048, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2049, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2051, .piece_count = 2 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 2053, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2054, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2056, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2058, .piece_count = 2 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2060, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2061, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2062, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2064, .piece_count = 2 },
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+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2067, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2069, .piece_count = 2 },
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+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2072, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2073, .piece_count = 2 },
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+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2077, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2078, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2079, .piece_count = 2 },
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+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2083, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2084, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2085, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2087, .piece_count = 2 },
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+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2090, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2091, .piece_count = 2 },
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+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2095, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2096, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2097, .piece_count = 2 },
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+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2102, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2103, .piece_count = 2 },
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+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2109, .piece_count = 2 },
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+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2114, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2116, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2118, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2120, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2122, .piece_count = 2 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2124, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2125, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2127, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2129, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2131, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2133, .piece_count = 2 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2135, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2136, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2138, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2140, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2142, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2144, .piece_count = 2 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 2146, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2147, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2149, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2151, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2153, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2155, .piece_count = 2 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2157, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2158, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2160, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2162, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2164, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2166, .piece_count = 2 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 2168, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2169, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2171, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2173, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2175, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2177, .piece_count = 2 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2179, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2180, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2182, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2184, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2186, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2188, .piece_count = 2 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2190, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2191, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2193, .piece_count = 2 },
+  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 2195, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2197, .piece_count = 2 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2199, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2200, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2202, .piece_count = 2 },
+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2204, .piece_count = 1 },
+  { .name = "imms", .signed_hint = -1, .bit_width = 6, .piece_start = 2205, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2206, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2208, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2210, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2212, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2214, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2216, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2218, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2220, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2222, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2224, .piece_count = 2 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2226, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2227, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2229, .piece_count = 2 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 5, .piece_start = 2231, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2232, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2233, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2235, .piece_count = 2 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 5, .piece_start = 2237, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2238, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2240, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2242, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2244, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2246, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2248, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2250, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2252, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2254, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2256, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2258, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2260, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2262, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2264, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2266, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2268, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2270, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2272, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2274, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2276, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2278, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2280, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2282, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2284, .piece_count = 2 },
+  { .name = "SrcA", .signed_hint = -1, .bit_width = 10, .piece_start = 2286, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2288, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2290, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2292, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2294, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2296, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2298, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2300, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2302, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2304, .piece_count = 2 },
+  { .name = "SrcA", .signed_hint = -1, .bit_width = 10, .piece_start = 2306, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2308, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2310, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2312, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2314, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2316, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2318, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2320, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2322, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2324, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2326, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2328, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2330, .piece_count = 2 },
+  { .name = "SrcA", .signed_hint = -1, .bit_width = 10, .piece_start = 2332, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2334, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2336, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2338, .piece_count = 2 },
+  { .name = "SrcA", .signed_hint = -1, .bit_width = 10, .piece_start = 2340, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2342, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2344, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2346, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2348, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2350, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2352, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2354, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2356, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2358, .piece_count = 2 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2360, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2361, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2363, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2365, .piece_count = 2 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2367, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2368, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2370, .piece_count = 2 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 5, .piece_start = 2372, .piece_count = 1 },
-  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2373, .piece_count = 1 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 5, .piece_start = 2365, .piece_count = 1 },
+  { .name = "DstType", .signed_hint = -1, .bit_width = 5, .piece_start = 2366, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2367, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2369, .piece_count = 2 },
+  { .name = "SrcType", .signed_hint = -1, .bit_width = 5, .piece_start = 2371, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2372, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2373, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2374, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2376, .piece_count = 2 },
-  { .name = "SrcType", .signed_hint = -1, .bit_width = 5, .piece_start = 2378, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2379, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2380, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2381, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2383, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2385, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2387, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2388, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2389, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2390, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2392, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2394, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2396, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2397, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2398, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2399, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2401, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2403, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2405, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2406, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2407, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2409, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2411, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2413, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2414, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2415, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2417, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2419, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2421, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2422, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2423, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2424, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2426, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2428, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2430, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2431, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2432, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2433, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2435, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2437, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2439, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2440, .piece_count = 1 },
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-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2443, .piece_count = 2 },
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-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2448, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2378, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2380, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2381, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2382, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2383, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2385, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2387, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2389, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2390, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2391, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2392, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2394, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2396, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2398, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2399, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2400, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2402, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2404, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2406, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2407, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2408, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2410, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2412, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2414, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2415, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2416, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2417, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2419, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2421, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2423, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2424, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2425, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2426, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2428, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2430, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2432, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2433, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2434, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2436, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2438, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2440, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2441, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2442, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2444, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2446, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2448, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2449, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2451, .piece_count = 2 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2453, .piece_count = 2 },
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-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2456, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2458, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2460, .piece_count = 2 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2462, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2463, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2464, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2465, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2467, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2469, .piece_count = 2 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2471, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2472, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2473, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2474, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2475, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2455, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2456, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2457, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2458, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2460, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2462, .piece_count = 2 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2464, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2465, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2466, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2467, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2468, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2469, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2471, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2473, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2475, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2476, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2478, .piece_count = 2 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2480, .piece_count = 2 },
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-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2483, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2485, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2487, .piece_count = 2 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2489, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2490, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2491, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2492, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2494, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2496, .piece_count = 2 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2498, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2499, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2500, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2501, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2503, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2505, .piece_count = 2 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2507, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2508, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2509, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2510, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2512, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2514, .piece_count = 2 },
-  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2516, .piece_count = 1 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2517, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2518, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2519, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2520, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2521, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2523, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2525, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2527, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2528, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2529, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2531, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2533, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2535, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2536, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2537, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2539, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2541, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2543, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2544, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2545, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2547, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2549, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2551, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2552, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2553, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2555, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2557, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2559, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2560, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2561, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2562, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2564, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2566, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2568, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2569, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2570, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2571, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2573, .piece_count = 2 },
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-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2577, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2578, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2579, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2581, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2583, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2585, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2586, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2587, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2589, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2591, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2593, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2594, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2595, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2597, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2599, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2601, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2602, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2603, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2605, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2607, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2609, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2610, .piece_count = 1 },
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-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2612, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2614, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2616, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2618, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2619, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2620, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2621, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2623, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2625, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2627, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2628, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2629, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2631, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2633, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2635, .piece_count = 1 },
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-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2637, .piece_count = 2 },
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-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2641, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2643, .piece_count = 1 },
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+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2485, .piece_count = 2 },
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+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2492, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2493, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2494, .piece_count = 2 },
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+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2502, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2503, .piece_count = 2 },
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+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2507, .piece_count = 2 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2509, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2510, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2511, .piece_count = 1 },
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+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2514, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2516, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2518, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2520, .piece_count = 1 },
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+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2522, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2524, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2526, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2528, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2529, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2530, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2532, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2534, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2536, .piece_count = 1 },
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+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2538, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2540, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2542, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2544, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2545, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2546, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2548, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2550, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2552, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2553, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2554, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2555, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2557, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2559, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2561, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2562, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2563, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2564, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2566, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2568, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2570, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2571, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2572, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2574, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2576, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2578, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2579, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2580, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2582, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2584, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2586, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2587, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2588, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2590, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2592, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2594, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2595, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2596, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2598, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2600, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2602, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2603, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2604, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2605, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2607, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2609, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2611, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2612, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2613, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2614, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2616, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2618, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2620, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2621, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2622, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2624, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2626, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2628, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2629, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2630, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2632, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2634, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2636, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2637, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2638, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2640, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2642, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2644, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2645, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2646, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2648, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2650, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2652, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2653, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2655, .piece_count = 2 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2657, .piece_count = 2 },
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-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2679, .piece_count = 1 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2659, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2660, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2661, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2662, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2664, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2666, .piece_count = 2 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2668, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2669, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2670, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2671, .piece_count = 1 },
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+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2673, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2675, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2677, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2679, .piece_count = 1 },
   { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2680, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2682, .piece_count = 2 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2684, .piece_count = 2 },
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-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2731, .piece_count = 1 },
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-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2733, .piece_count = 2 },
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-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2737, .piece_count = 2 },
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-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2753, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2755, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2756, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2757, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2759, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2761, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2763, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2764, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2765, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2766, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2768, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2770, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2772, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2773, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2774, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2775, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2777, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2779, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2781, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2782, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2783, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2785, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2787, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2789, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2790, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2791, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2793, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2795, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2797, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2798, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2799, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2801, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2803, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2805, .piece_count = 2 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2807, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2809, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2811, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2813, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2815, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2817, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2819, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2821, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2823, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2825, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2827, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2829, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2831, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2833, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2835, .piece_count = 2 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2837, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2838, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2839, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2841, .piece_count = 2 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2843, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2844, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2846, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2848, .piece_count = 2 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2850, .piece_count = 1 },
-  { .name = "SrcZero", .signed_hint = -1, .bit_width = 10, .piece_start = 2851, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2853, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2855, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2857, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2859, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2861, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2863, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2865, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2867, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2869, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2871, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2873, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2875, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2877, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2879, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2881, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2883, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2885, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2887, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2889, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2891, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2893, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2895, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2897, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2899, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2901, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2903, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2905, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2907, .piece_count = 2 },
-  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2909, .piece_count = 1 },
-  { .name = "immr", .signed_hint = -1, .bit_width = 6, .piece_start = 2910, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2911, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2912, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2913, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2915, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2917, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2919, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2920, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2921, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2922, .piece_count = 2 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2686, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2687, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2688, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2689, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2691, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2693, .piece_count = 2 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2695, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2696, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2697, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2698, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2700, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2702, .piece_count = 2 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2704, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2705, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2706, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2707, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2709, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2711, .piece_count = 2 },
+  { .name = "aq", .signed_hint = -1, .bit_width = 1, .piece_start = 2713, .piece_count = 1 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2714, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2715, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2716, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2717, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2718, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2720, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2722, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2724, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2725, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2726, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2728, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2730, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2732, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2733, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2734, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2736, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2738, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2740, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2741, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2742, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2744, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2746, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2748, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2749, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2750, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2752, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2754, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2756, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2757, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2758, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2759, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2761, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2763, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2765, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2766, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2767, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2768, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2770, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2772, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2774, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2775, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2776, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2778, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2780, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2782, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2783, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2784, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2786, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2788, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2790, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2791, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2792, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2794, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2796, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2798, .piece_count = 2 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2800, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2802, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2804, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2806, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2808, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2810, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2812, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2814, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2816, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2818, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2820, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2822, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2824, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2826, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2828, .piece_count = 2 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2830, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2831, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2832, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2834, .piece_count = 2 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 2836, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2837, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2839, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2841, .piece_count = 2 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 2843, .piece_count = 1 },
+  { .name = "SrcZero", .signed_hint = -1, .bit_width = 10, .piece_start = 2844, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2846, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2848, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2850, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2852, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2854, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2856, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2858, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2860, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2862, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2864, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2866, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2868, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2870, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2872, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2874, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2876, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2878, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2880, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2882, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2884, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2886, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2888, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2890, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2892, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2894, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2896, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 2898, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2900, .piece_count = 2 },
+  { .name = "imml", .signed_hint = -1, .bit_width = 6, .piece_start = 2902, .piece_count = 1 },
+  { .name = "immr", .signed_hint = -1, .bit_width = 6, .piece_start = 2903, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2904, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2905, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2906, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2908, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2910, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2912, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2913, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2914, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2915, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2917, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2919, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2921, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2922, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2923, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2924, .piece_count = 2 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2926, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2928, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2929, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2930, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2931, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2933, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2935, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2939, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2940, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2941, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2943, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2945, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2949, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2950, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2951, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2953, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2955, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2957, .piece_count = 1 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2928, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2932, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2933, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2934, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2936, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 2938, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2942, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2943, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2944, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2946, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2948, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2950, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2951, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2953, .piece_count = 2 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2955, .piece_count = 1 },
+  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 2956, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2957, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2958, .piece_count = 2 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2960, .piece_count = 2 },
   { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2962, .piece_count = 1 },
   { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 2963, .piece_count = 1 },
   { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2964, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2965, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2967, .piece_count = 2 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2969, .piece_count = 1 },
-  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 2970, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2971, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2972, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2973, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2974, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2976, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2978, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2980, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2965, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2966, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2967, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2969, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2971, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 2973, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2974, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2976, .piece_count = 2 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2978, .piece_count = 1 },
+  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 2979, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2980, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2981, .piece_count = 2 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2983, .piece_count = 2 },
   { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2985, .piece_count = 1 },
@@ -5818,170 +5813,170 @@ const linxisa_field linxisa_fields[] = {
   { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2992, .piece_count = 1 },
   { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 2993, .piece_count = 1 },
   { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 2994, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2995, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 2997, .piece_count = 2 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 2999, .piece_count = 1 },
-  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3000, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3001, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3002, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3003, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3004, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3006, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3008, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3010, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3011, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3012, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3013, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3015, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3017, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3019, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3020, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3022, .piece_count = 2 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3024, .piece_count = 1 },
-  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3025, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3026, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3027, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3028, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3029, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3031, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3033, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3037, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3038, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3039, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3041, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3043, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3047, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3048, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3049, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3051, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3053, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3057, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3058, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3059, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3061, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3063, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3067, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3068, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3069, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3071, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3073, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3075, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3076, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3077, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3078, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3080, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3082, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3084, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3085, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3086, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3087, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3089, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3091, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3093, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3094, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3095, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3096, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 2995, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 2996, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 2997, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 2999, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3001, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3003, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3004, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3005, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3006, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3008, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3010, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3012, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3013, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3015, .piece_count = 2 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3017, .piece_count = 1 },
+  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3018, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3019, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3020, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3021, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3022, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3024, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3026, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3030, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3031, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3032, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3034, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3036, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3040, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3041, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3042, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3044, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3046, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3050, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3051, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3052, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3054, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3056, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3060, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3061, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3062, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3064, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3066, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3068, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3069, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3070, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3071, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3073, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3075, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3077, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3078, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3079, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3080, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3082, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3084, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3086, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3087, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3088, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3089, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3091, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3093, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3095, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3096, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3098, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3100, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3102, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3103, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3105, .piece_count = 2 },
-  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 3107, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3109, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3111, .piece_count = 2 },
-  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 3113, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3115, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3117, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3119, .piece_count = 2 },
-  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 3121, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3123, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3125, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3127, .piece_count = 2 },
-  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 3129, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3131, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3133, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3135, .piece_count = 2 },
-  { .name = "imm", .signed_hint = -1, .bit_width = 14, .piece_start = 3137, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3139, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3141, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3143, .piece_count = 2 },
-  { .name = "imm", .signed_hint = -1, .bit_width = 14, .piece_start = 3145, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3147, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3149, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3151, .piece_count = 2 },
-  { .name = "imm", .signed_hint = -1, .bit_width = 14, .piece_start = 3153, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3155, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3157, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3159, .piece_count = 2 },
-  { .name = "imm", .signed_hint = -1, .bit_width = 14, .piece_start = 3161, .piece_count = 2 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3163, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3164, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3165, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3167, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3169, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3173, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3174, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3175, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3177, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3179, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3183, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3184, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3185, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3187, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3189, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3193, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3194, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3195, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3197, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3199, .piece_count = 4 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3203, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3205, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3207, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3209, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3211, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 3213, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3214, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3216, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3218, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3220, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3222, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 3224, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3225, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3227, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3229, .piece_count = 2 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3231, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3233, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 3235, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3236, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3238, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3240, .piece_count = 2 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 3242, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3243, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3244, .piece_count = 2 },
+  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 3100, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3102, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3104, .piece_count = 2 },
+  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 3106, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3108, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3110, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3112, .piece_count = 2 },
+  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 3114, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3116, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3118, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3120, .piece_count = 2 },
+  { .name = "SrcP", .signed_hint = -1, .bit_width = 10, .piece_start = 3122, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3124, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3126, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3128, .piece_count = 2 },
+  { .name = "imm", .signed_hint = -1, .bit_width = 14, .piece_start = 3130, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3132, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3134, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3136, .piece_count = 2 },
+  { .name = "imm", .signed_hint = -1, .bit_width = 14, .piece_start = 3138, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3140, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3142, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3144, .piece_count = 2 },
+  { .name = "imm", .signed_hint = -1, .bit_width = 14, .piece_start = 3146, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3148, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3150, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3152, .piece_count = 2 },
+  { .name = "imm", .signed_hint = -1, .bit_width = 14, .piece_start = 3154, .piece_count = 2 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3156, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3157, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3158, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3160, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3162, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3166, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3167, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3168, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3170, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3172, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3176, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3177, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3178, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3180, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3182, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3186, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3187, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3188, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3190, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3192, .piece_count = 4 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3196, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3198, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3200, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3202, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3204, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 3206, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3207, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3209, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3211, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3213, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3215, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 3217, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3218, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3220, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3222, .piece_count = 2 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3224, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3226, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 6, .piece_start = 3228, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3229, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3231, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3233, .piece_count = 2 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 3235, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3236, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3237, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3239, .piece_count = 2 },
+  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 3241, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3242, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3243, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3244, .piece_count = 2 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3246, .piece_count = 2 },
-  { .name = "uimm12", .signed_hint = 0, .bit_width = 12, .piece_start = 3248, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3249, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3250, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3251, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3253, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3255, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3257, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3248, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3250, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3251, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3253, .piece_count = 2 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3255, .piece_count = 1 },
+  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3256, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3257, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3258, .piece_count = 2 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3260, .piece_count = 2 },
   { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3262, .piece_count = 1 },
   { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3263, .piece_count = 1 },
   { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3264, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3265, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3267, .piece_count = 2 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3269, .piece_count = 1 },
-  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3270, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3271, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3272, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3273, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3274, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3276, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3278, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3280, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3265, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3266, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3267, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3269, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3271, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3273, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3274, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3276, .piece_count = 2 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3278, .piece_count = 1 },
+  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3279, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3280, .piece_count = 1 },
   { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3281, .piece_count = 2 },
   { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3283, .piece_count = 2 },
   { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3285, .piece_count = 1 },
@@ -5992,76 +5987,71 @@ const linxisa_field linxisa_fields[] = {
   { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3292, .piece_count = 1 },
   { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3293, .piece_count = 1 },
   { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3294, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3295, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3297, .piece_count = 2 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3299, .piece_count = 1 },
-  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3300, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3301, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3302, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3303, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3304, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3306, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3308, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3310, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3311, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3312, .piece_count = 1 },
-  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3313, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3315, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3317, .piece_count = 2 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3319, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3320, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3322, .piece_count = 2 },
-  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3324, .piece_count = 1 },
-  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3325, .piece_count = 1 },
-  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3326, .piece_count = 1 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3327, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3328, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3329, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3331, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3333, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3337, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3338, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3339, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3341, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3343, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3347, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3348, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3349, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3351, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3353, .piece_count = 4 },
-  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3357, .piece_count = 1 },
-  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3358, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3359, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3361, .piece_count = 2 },
-  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3363, .piece_count = 4 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3367, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3369, .piece_count = 2 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3371, .piece_count = 2 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 3373, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3374, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3375, .piece_count = 2 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3377, .piece_count = 2 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 3379, .piece_count = 1 },
-  { .name = "ACR-ID", .signed_hint = -1, .bit_width = 10, .piece_start = 3380, .piece_count = 1 },
-  { .name = "CROSS-BID", .signed_hint = -1, .bit_width = 7, .piece_start = 3381, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 3382, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 3383, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 3384, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 3385, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3386, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 3387, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 3388, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 3389, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 3390, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 3391, .piece_count = 1 },
-  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 3392, .piece_count = 1 },
-  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 3393, .piece_count = 1 },
-  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 3394, .piece_count = 1 },
-  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 3395, .piece_count = 1 },
-  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 3396, .piece_count = 1 },
-  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3397, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3295, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3296, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3297, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3299, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3301, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3303, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3304, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3305, .piece_count = 1 },
+  { .name = "SrcD", .signed_hint = -1, .bit_width = 10, .piece_start = 3306, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3308, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3310, .piece_count = 2 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3312, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3313, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3315, .piece_count = 2 },
+  { .name = "far", .signed_hint = -1, .bit_width = 1, .piece_start = 3317, .piece_count = 1 },
+  { .name = "rd", .signed_hint = -1, .bit_width = 1, .piece_start = 3318, .piece_count = 1 },
+  { .name = "rl", .signed_hint = -1, .bit_width = 1, .piece_start = 3319, .piece_count = 1 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3320, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3321, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3322, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3324, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3326, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3330, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3331, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3332, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3334, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3336, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3340, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3341, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3342, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3344, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3346, .piece_count = 4 },
+  { .name = "C", .signed_hint = -1, .bit_width = 1, .piece_start = 3350, .piece_count = 1 },
+  { .name = "L", .signed_hint = -1, .bit_width = 1, .piece_start = 3351, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3352, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3354, .piece_count = 2 },
+  { .name = "simm24", .signed_hint = 1, .bit_width = 24, .piece_start = 3356, .piece_count = 4 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3360, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3362, .piece_count = 2 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 10, .piece_start = 3364, .piece_count = 2 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 3366, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3367, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 10, .piece_start = 3368, .piece_count = 2 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 10, .piece_start = 3370, .piece_count = 2 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 3372, .piece_count = 1 },
+  { .name = "ACR-ID", .signed_hint = -1, .bit_width = 10, .piece_start = 3373, .piece_count = 1 },
+  { .name = "CROSS-BID", .signed_hint = -1, .bit_width = 7, .piece_start = 3374, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 3375, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 3376, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 3377, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 3378, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3379, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 3380, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 3381, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 3382, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 3383, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 3384, .piece_count = 1 },
+  { .name = "simm12", .signed_hint = 1, .bit_width = 12, .piece_start = 3385, .piece_count = 1 },
+  { .name = "RegDst", .signed_hint = -1, .bit_width = 5, .piece_start = 3386, .piece_count = 1 },
+  { .name = "SrcL", .signed_hint = -1, .bit_width = 5, .piece_start = 3387, .piece_count = 1 },
+  { .name = "SrcR", .signed_hint = -1, .bit_width = 5, .piece_start = 3388, .piece_count = 1 },
+  { .name = "SrcRType", .signed_hint = -1, .bit_width = 2, .piece_start = 3389, .piece_count = 1 },
+  { .name = "shamt", .signed_hint = -1, .bit_width = 5, .piece_start = 3390, .piece_count = 1 },
 };
-const size_t linxisa_fields_count = 2654;
+const size_t linxisa_fields_count = 2651;
 
 const linxisa_inst_form linxisa_inst_forms[] = {
   { .id = "acrc_32_a9c0e33f9904", .mnemonic = "ACRC", .asm_fmt = "acrc rst_type", .length_bits = 32, .mask = 0x00000000ff0fffffULL, .match = 0x000000000000302bULL, .field_start = 0, .field_count = 1 },
@@ -6076,14 +6066,8 @@ const linxisa_inst_form linxisa_inst_forms[] = {
   { .id = "andiw_32_9ec1f7343dbd", .mnemonic = "ANDIW", .asm_fmt = "andiw SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002035ULL, .field_start = 28, .field_count = 3 },
   { .id = "andw_32_6907ed7cec90", .mnemonic = "ANDW", .asm_fmt = "andw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002025ULL, .field_start = 31, .field_count = 5 },
   { .id = "assert_32_f05d67874ae5", .mnemonic = "ASSERT", .asm_fmt = "assert SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000000102bULL, .field_start = 36, .field_count = 1 },
-  { .id = "b_arg_32_374ec956affe", .mnemonic = "B.ARG", .asm_fmt = "B.ARG NORM.normal", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x00000000000fa023ULL, .field_start = 37, .field_count = 0 },
-  { .id = "b_arg_32_47e8ac50ac96", .mnemonic = "B.ARG", .asm_fmt = "B.ARG format", .length_bits = 32, .mask = 0x00000000fffff07fULL, .match = 0x0000000000003043ULL, .field_start = 37, .field_count = 1 },
-  { .id = "b_arg_32_5c8bfa662370", .mnemonic = "B.ARG", .asm_fmt = "B.ARG NZ2DN.canon", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x00000000020fae23ULL, .field_start = 38, .field_count = 0 },
-  { .id = "b_arg_32_95152c29a268", .mnemonic = "B.ARG", .asm_fmt = "B.ARG ND2ZN.normal, FP16, Null", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x00000000180221a3ULL, .field_start = 38, .field_count = 0 },
-  { .id = "b_arg_32_c6d5c49a4ad7", .mnemonic = "B.ARG", .asm_fmt = "B.ARG DN2ZN.normal, FP16, Null", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000018022423ULL, .field_start = 38, .field_count = 0 },
-  { .id = "b_arg_32_f19d18f2126b", .mnemonic = "B.ARG", .asm_fmt = "B.ARG DN2NZ.normal, FP32, Null", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x000000001800a4a3ULL, .field_start = 38, .field_count = 0 },
-  { .id = "b_catr_32_e90bd52fa480", .mnemonic = "B.CATR", .asm_fmt = "B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}", .length_bits = 32, .mask = 0x0000000003ffffffULL, .match = 0x0000000000000023ULL, .field_start = 38, .field_count = 6 },
-  { .id = "b_datr_32_c161a042ff38", .mnemonic = "B.DATR", .asm_fmt = "B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001023ULL, .field_start = 44, .field_count = 6 },
+  { .id = "b_catr_32_8f94bdb16d29", .mnemonic = "B.CATR", .asm_fmt = "B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}", .length_bits = 32, .mask = 0x00000000fbf07fffULL, .match = 0x0000000000000023ULL, .field_start = 37, .field_count = 6 },
+  { .id = "b_datr_32_840f4b8d579d", .mnemonic = "B.DATR", .asm_fmt = "B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}", .length_bits = 32, .mask = 0x00000000000c707fULL, .match = 0x0000000000001023ULL, .field_start = 43, .field_count = 7 },
   { .id = "b_dim_32_1caa1aa2944a", .mnemonic = "B.DIM", .asm_fmt = "B.DIM RegSrc, uimm, ->LB2", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002043ULL, .field_start = 50, .field_count = 2 },
   { .id = "b_dim_32_27602ab68929", .mnemonic = "B.DIM", .asm_fmt = "B.DIM RegSrc, uimm, ->LB0", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000043ULL, .field_start = 52, .field_count = 2 },
   { .id = "b_dim_32_4191099a5f4d", .mnemonic = "B.DIM", .asm_fmt = "B.DIM RegSrc, uimm, ->LB1", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001043ULL, .field_start = 54, .field_count = 2 },
@@ -6093,11 +6077,11 @@ const linxisa_inst_form linxisa_inst_forms[] = {
   { .id = "b_hint_32_69d942ff1583", .mnemonic = "B.HINT", .asm_fmt = "B.HINT {BR.{likely, unlikely}, TEMP.{hot, warm, cool, none}, PRFSIZE}", .length_bits = 32, .mask = 0x0000000000087fffULL, .match = 0x0000000000000033ULL, .field_start = 65, .field_count = 4 },
   { .id = "b_hint_32_f7d01d734925", .mnemonic = "B.HINT", .asm_fmt = "B.HINT TRACE.{begin, end}", .length_bits = 32, .mask = 0x00000000ffff7fffULL, .match = 0x0000000000001033ULL, .field_start = 69, .field_count = 1 },
   { .id = "b_ior_32_c3ea71404eb3", .mnemonic = "B.IOR", .asm_fmt = "B.IOR [RegSrc0, RegSrc1, RegSrc2],[RegDst]", .length_bits = 32, .mask = 0x000000000600707fULL, .match = 0x0000000000000013ULL, .field_start = 70, .field_count = 4 },
-  { .id = "b_iot_32_10db6db84f5d", .mnemonic = "B.IOT", .asm_fmt = "B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>", .length_bits = 32, .mask = 0x00000000803f707fULL, .match = 0x0000000000005013ULL, .field_start = 74, .field_count = 5 },
-  { .id = "b_iot_32_2c07e7177fad", .mnemonic = "B.IOT", .asm_fmt = "B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>", .length_bits = 32, .mask = 0x000000001fc0707fULL, .match = 0x0000000001c04013ULL, .field_start = 79, .field_count = 5 },
-  { .id = "b_iot_32_8b8bce6bffe8", .mnemonic = "B.IOT", .asm_fmt = "B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004013ULL, .field_start = 84, .field_count = 7 },
-  { .id = "b_iot_32_c11eb189dd83", .mnemonic = "B.IOT", .asm_fmt = "B.IOT SrcTile0<.reuse>, <last>", .length_bits = 32, .mask = 0x000000009fff707fULL, .match = 0x0000000001c05013ULL, .field_start = 91, .field_count = 3 },
-  { .id = "b_iot_32_efa0fe3fe49a", .mnemonic = "B.IOT", .asm_fmt = "B.IOT <last>, ->DstTile<Size>", .length_bits = 32, .mask = 0x00000000c03fffffULL, .match = 0x0000000000006013ULL, .field_start = 94, .field_count = 3 },
+  { .id = "b_iot_32_0f23e46d6176", .mnemonic = "B.IOT", .asm_fmt = "B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>", .length_bits = 32, .mask = 0x00000000fc00787fULL, .match = 0x0000000000005013ULL, .field_start = 74, .field_count = 5 },
+  { .id = "b_iot_32_3a6945dec034", .mnemonic = "B.IOT", .asm_fmt = "B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004013ULL, .field_start = 79, .field_count = 7 },
+  { .id = "b_iot_32_778f84340400", .mnemonic = "B.IOT", .asm_fmt = "B.IOT SrcTile0<.reuse>, <last>", .length_bits = 32, .mask = 0x00000000fc07fbffULL, .match = 0x0000000000005013ULL, .field_start = 86, .field_count = 3 },
+  { .id = "b_iot_32_a06b9b6c1965", .mnemonic = "B.IOT", .asm_fmt = "B.IOT <last>, ->DstTile<Size>", .length_bits = 32, .mask = 0x00000000fff07c7fULL, .match = 0x0000000000006013ULL, .field_start = 89, .field_count = 3 },
+  { .id = "b_iot_32_f1ca66bbcce1", .mnemonic = "B.IOT", .asm_fmt = "B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>", .length_bits = 32, .mask = 0x000000000007f3ffULL, .match = 0x0000000000004013ULL, .field_start = 92, .field_count = 5 },
   { .id = "b_lt_32_2ca5ecd25cfb", .mnemonic = "B.LT", .asm_fmt = "b.lt SrcL, SrcR, label", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002027ULL, .field_start = 97, .field_count = 3 },
   { .id = "b_ltu_32_f1ea7ad44e37", .mnemonic = "B.LTU", .asm_fmt = "b.ltu SrcL, SrcR, label", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004027ULL, .field_start = 100, .field_count = 3 },
   { .id = "b_ne_32_831af6a36ff4", .mnemonic = "B.NE", .asm_fmt = "b.ne SrcL, SrcR, label", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001027ULL, .field_start = 103, .field_count = 3 },
@@ -6114,724 +6098,722 @@ const linxisa_inst_form linxisa_inst_forms[] = {
   { .id = "bstart_32_e11e678a32ac", .mnemonic = "BSTART", .asm_fmt = "BSTART COND, <label>", .length_bits = 32, .mask = 0x000000000000007fULL, .match = 0x0000000000000021ULL, .field_start = 124, .field_count = 1 },
   { .id = "bstart_call_32_9404418d1ae5", .mnemonic = "BSTART CALL", .asm_fmt = "BSTART.CALL <br_label>, <rt_label>, ->ra", .length_bits = 32, .mask = 0x00000000f83f000fULL, .match = 0x0000000050160002ULL, .field_start = 125, .field_count = 2 },
   { .id = "bstart_acccvt_32_56c3ce3838c5", .mnemonic = "BSTART.ACCCVT", .asm_fmt = "BSTART.ACCCVT DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000831181ULL, .field_start = 127, .field_count = 1 },
-  { .id = "bstart_cube_32_bd3f337acb9d", .mnemonic = "BSTART.CUBE", .asm_fmt = "BSTART.CUBE Function, DataType", .length_bits = 32, .mask = 0x00000000060fffffULL, .match = 0x0000000000031181ULL, .field_start = 128, .field_count = 2 },
-  { .id = "bstart_fixp_32_3b0ae11126a6", .mnemonic = "BSTART.FIXP", .asm_fmt = "BSTART.FIXP TileOp, DataType", .length_bits = 32, .mask = 0x00000000060fffffULL, .match = 0x0000000000039181ULL, .field_start = 130, .field_count = 2 },
-  { .id = "bstart_fp_32_0c671a644214", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP RET", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000007101ULL, .field_start = 132, .field_count = 0 },
-  { .id = "bstart_fp_32_24db3966d6ba", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP ICALL", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000006101ULL, .field_start = 132, .field_count = 0 },
-  { .id = "bstart_fp_32_58ad7954fb49", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP COND, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000003101ULL, .field_start = 132, .field_count = 1 },
-  { .id = "bstart_fp_32_7978795a29a1", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP IND", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000005101ULL, .field_start = 133, .field_count = 0 },
-  { .id = "bstart_fp_32_d00a708a81f0", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP DIRECT, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000002101ULL, .field_start = 133, .field_count = 1 },
-  { .id = "bstart_fp_32_dd7bc8dd694c", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP CALL, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000004101ULL, .field_start = 134, .field_count = 1 },
-  { .id = "bstart_fp_32_face4f238d84", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP FALL<, fixup_label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000001101ULL, .field_start = 135, .field_count = 1 },
-  { .id = "bstart_mgather_32_c9defbf18276", .mnemonic = "BSTART.MGATHER", .asm_fmt = "BSTART.MGATHER DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000411181ULL, .field_start = 136, .field_count = 1 },
-  { .id = "bstart_mgather_cas_32_fd8c8a3b720a", .mnemonic = "BSTART.MGATHER.CAS", .asm_fmt = "BSTART.MGATHER.CAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000811181ULL, .field_start = 137, .field_count = 1 },
-  { .id = "bstart_mgather_mask_32_5573241cd944", .mnemonic = "BSTART.MGATHER.MASK", .asm_fmt = "BSTART.MGATHER.MASK DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000611181ULL, .field_start = 138, .field_count = 1 },
-  { .id = "bstart_mpar_32_2d163417c615", .mnemonic = "BSTART.MPAR", .asm_fmt = "BSTART.MPAR <VS8, VS16>", .length_bits = 32, .mask = 0x00000000f9ffffffULL, .match = 0x0000000000001181ULL, .field_start = 139, .field_count = 1 },
-  { .id = "bstart_mscatter_32_0f0ba08bd798", .mnemonic = "BSTART.MSCATTER", .asm_fmt = "BSTART.MSCATTER DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000511181ULL, .field_start = 140, .field_count = 1 },
-  { .id = "bstart_mscatter_mask_32_2a33eed646f7", .mnemonic = "BSTART.MSCATTER.MASK", .asm_fmt = "BSTART.MSCATTER.MASK DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000711181ULL, .field_start = 141, .field_count = 1 },
-  { .id = "bstart_mseq_32_39343a456ec5", .mnemonic = "BSTART.MSEQ", .asm_fmt = "BSTART.MSEQ <VS8, VS16>", .length_bits = 32, .mask = 0x00000000f9ffffffULL, .match = 0x0000000000009181ULL, .field_start = 142, .field_count = 1 },
-  { .id = "bstart_std_32_1ef99c4cedcb", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD COND, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000003001ULL, .field_start = 143, .field_count = 1 },
-  { .id = "bstart_std_32_3f6980d013f7", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD ICALL", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000006001ULL, .field_start = 144, .field_count = 0 },
-  { .id = "bstart_std_32_441ad677fffe", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD FALL<, fixup_label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000001001ULL, .field_start = 144, .field_count = 1 },
-  { .id = "bstart_std_32_816dfa76cc4a", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD RET", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000007001ULL, .field_start = 145, .field_count = 0 },
-  { .id = "bstart_std_32_986b7ee2cf6a", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD IND", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000005001ULL, .field_start = 145, .field_count = 0 },
-  { .id = "bstart_std_32_b05390d367cf", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD CALL, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000004001ULL, .field_start = 145, .field_count = 1 },
-  { .id = "bstart_std_32_c1de85e06878", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD DIRECT, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000002001ULL, .field_start = 146, .field_count = 1 },
-  { .id = "bstart_sys_32_762d9d84a6d8", .mnemonic = "BSTART.SYS", .asm_fmt = "BSTART.SYS FALL<, fixup_label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000001081ULL, .field_start = 147, .field_count = 1 },
-  { .id = "bstart_tepl_32_d022db6dacb3", .mnemonic = "BSTART.TEPL", .asm_fmt = "BSTART.TEPL TileOpcode, DataType", .length_bits = 32, .mask = 0x0000000006007fffULL, .match = 0x0000000002001181ULL, .field_start = 148, .field_count = 2 },
-  { .id = "bstart_tgemv_32_ae19f5b678f5", .mnemonic = "BSTART.TGEMV", .asm_fmt = "BSTART.TGEMV DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001031181ULL, .field_start = 150, .field_count = 1 },
-  { .id = "bstart_tgemv_acc_32_9a471b21913e", .mnemonic = "BSTART.TGEMV.ACC", .asm_fmt = "BSTART.TGEMV.ACC DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001231181ULL, .field_start = 151, .field_count = 1 },
-  { .id = "bstart_tgemv_bias_32_186ee96c0a8b", .mnemonic = "BSTART.TGEMV.BIAS", .asm_fmt = "BSTART.TGEMV.BIAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001131181ULL, .field_start = 152, .field_count = 1 },
-  { .id = "bstart_tgemvmx_32_ae5e005f6589", .mnemonic = "BSTART.TGEMVMX", .asm_fmt = "BSTART.TGEMVMX DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001431181ULL, .field_start = 153, .field_count = 1 },
-  { .id = "bstart_tgemvmx_acc_32_368647b04bb0", .mnemonic = "BSTART.TGEMVMX.ACC", .asm_fmt = "BSTART.TGEMVMX.ACC DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001631181ULL, .field_start = 154, .field_count = 1 },
-  { .id = "bstart_tgemvmx_bias_32_d23011f15171", .mnemonic = "BSTART.TGEMVMX.BIAS", .asm_fmt = "BSTART.TGEMVMX.BIAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001531181ULL, .field_start = 155, .field_count = 1 },
-  { .id = "bstart_tload_32_d0c18bb0ab15", .mnemonic = "BSTART.TLOAD", .asm_fmt = "BSTART.TLOAD DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000011181ULL, .field_start = 156, .field_count = 1 },
-  { .id = "bstart_tmatmul_32_f9da70e4e0ad", .mnemonic = "BSTART.TMATMUL", .asm_fmt = "BSTART.TMATMUL DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000031181ULL, .field_start = 157, .field_count = 1 },
-  { .id = "bstart_tmatmul_acc_32_0c8c62e5f00a", .mnemonic = "BSTART.TMATMUL.ACC", .asm_fmt = "BSTART.TMATMUL.ACC DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000231181ULL, .field_start = 158, .field_count = 1 },
-  { .id = "bstart_tmatmul_bias_32_4d5a498d12f3", .mnemonic = "BSTART.TMATMUL.BIAS", .asm_fmt = "BSTART.TMATMUL.BIAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000131181ULL, .field_start = 159, .field_count = 1 },
-  { .id = "bstart_tmatmulmx_32_e26cb3874648", .mnemonic = "BSTART.TMATMULMX", .asm_fmt = "BSTART.TMATMULMX DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000431181ULL, .field_start = 160, .field_count = 1 },
-  { .id = "bstart_tmatmulmx_acc_32_70fa59b0ab4c", .mnemonic = "BSTART.TMATMULMX.ACC", .asm_fmt = "BSTART.TMATMULMX.ACC DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000631181ULL, .field_start = 161, .field_count = 1 },
-  { .id = "bstart_tmatmulmx_bias_32_098c7efa51b0", .mnemonic = "BSTART.TMATMULMX.BIAS", .asm_fmt = "BSTART.TMATMULMX.BIAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000531181ULL, .field_start = 162, .field_count = 1 },
-  { .id = "bstart_tmov_32_211446509efb", .mnemonic = "BSTART.TMOV", .asm_fmt = "BSTART.TMOV DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000211181ULL, .field_start = 163, .field_count = 1 },
-  { .id = "bstart_tprefetch_32_d5f83e5aadf6", .mnemonic = "BSTART.TPREFETCH", .asm_fmt = "BSTART.TPREFETCH DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000311181ULL, .field_start = 164, .field_count = 1 },
-  { .id = "bstart_tstore_32_4048b6e8b0f4", .mnemonic = "BSTART.TSTORE", .asm_fmt = "BSTART.TSTORE DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000111181ULL, .field_start = 165, .field_count = 1 },
-  { .id = "bstart_vpar_32_8998d3fa51f8", .mnemonic = "BSTART.VPAR", .asm_fmt = "BSTART.VPAR <VS8, VS16>", .length_bits = 32, .mask = 0x00000000f9ffffffULL, .match = 0x0000000000021181ULL, .field_start = 166, .field_count = 1 },
-  { .id = "bstart_vseq_32_9324064902ae", .mnemonic = "BSTART.VSEQ", .asm_fmt = "BSTART.VSEQ <VS8, VS16>", .length_bits = 32, .mask = 0x00000000f9ffffffULL, .match = 0x0000000000029181ULL, .field_start = 167, .field_count = 1 },
-  { .id = "bstop_32_d25b09fdd59c", .mnemonic = "BSTOP", .asm_fmt = "BSTOP", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000000001ULL, .field_start = 168, .field_count = 0 },
-  { .id = "bwe_32_e5a5240bdf9b", .mnemonic = "BWE", .asm_fmt = "bwe SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000010002bULL, .field_start = 168, .field_count = 1 },
-  { .id = "bwi_32_d9a0905cb31b", .mnemonic = "BWI", .asm_fmt = "bwi SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000020002bULL, .field_start = 169, .field_count = 1 },
-  { .id = "bwt_32_5a0fe4a8e61f", .mnemonic = "BWT", .asm_fmt = "bwt SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000030002bULL, .field_start = 170, .field_count = 1 },
-  { .id = "bxs_32_b1bb003c1703", .mnemonic = "BXS", .asm_fmt = "bxs SrcL, M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000067ULL, .field_start = 171, .field_count = 4 },
-  { .id = "bxu_32_e9ea9715ba62", .mnemonic = "BXU", .asm_fmt = "bxu SrcL, M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001067ULL, .field_start = 175, .field_count = 4 },
-  { .id = "c_add_16_85136d1e4904", .mnemonic = "C.ADD", .asm_fmt = "c.add srcL, srcR, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000008ULL, .field_start = 179, .field_count = 2 },
-  { .id = "c_addi_16_3050744f2322", .mnemonic = "C.ADDI", .asm_fmt = "c.addi srcL, simm, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000000cULL, .field_start = 181, .field_count = 2 },
-  { .id = "c_and_16_379e5bed3352", .mnemonic = "C.AND", .asm_fmt = "c.and srcL, srcR, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000028ULL, .field_start = 183, .field_count = 2 },
-  { .id = "c_b_dim_16_14f1b8fba5e6", .mnemonic = "C.B.DIM", .asm_fmt = "C.B.DIM RegSrc, ->{LB0, LB1, LB2}", .length_bits = 16, .mask = 0x000000000000c03fULL, .match = 0x000000000000c03cULL, .field_start = 185, .field_count = 2 },
-  { .id = "c_b_dimi_16_3f1b113c76ce", .mnemonic = "C.B.DIMI", .asm_fmt = "C.B.DIMI imm, ->{LB0, LB1, LB2}", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000003cULL, .field_start = 187, .field_count = 2 },
-  { .id = "c_bstart_16_c4e238a9227a", .mnemonic = "C.BSTART", .asm_fmt = "C.BSTART COND,  label", .length_bits = 16, .mask = 0x000000000000000fULL, .match = 0x0000000000000004ULL, .field_start = 189, .field_count = 1 },
-  { .id = "c_bstart_16_f833d2a4753c", .mnemonic = "C.BSTART", .asm_fmt = "C.BSTART DIRECT, label", .length_bits = 16, .mask = 0x000000000000000fULL, .match = 0x0000000000000002ULL, .field_start = 190, .field_count = 1 },
-  { .id = "c_bstart_fp_16_9dcef7e3a85b", .mnemonic = "C.BSTART.FP", .asm_fmt = "C.BSTART.FP BrType", .length_bits = 16, .mask = 0x000000000000c7ffULL, .match = 0x0000000000000080ULL, .field_start = 191, .field_count = 1 },
-  { .id = "c_bstart_mpar_16_66c3ef2226ec", .mnemonic = "C.BSTART.MPAR", .asm_fmt = "C.BSTART.MPAR FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x00000000000008c0ULL, .field_start = 192, .field_count = 0 },
-  { .id = "c_bstart_mseq_16_b5597e0e41c2", .mnemonic = "C.BSTART.MSEQ", .asm_fmt = "C.BSTART.MSEQ FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x00000000000048c0ULL, .field_start = 192, .field_count = 0 },
-  { .id = "c_bstart_std_16_8b40f078c14a", .mnemonic = "C.BSTART.STD", .asm_fmt = "C.BSTART.STD BrType", .length_bits = 16, .mask = 0x000000000000c7ffULL, .match = 0x0000000000000000ULL, .field_start = 192, .field_count = 1 },
-  { .id = "c_bstart_sys_16_ec213ce96eb7", .mnemonic = "C.BSTART.SYS", .asm_fmt = "C.BSTART.SYS FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x0000000000000840ULL, .field_start = 193, .field_count = 0 },
-  { .id = "c_bstart_vpar_16_c4d89efc71ea", .mnemonic = "C.BSTART.VPAR", .asm_fmt = "C.BSTART.VPAR FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x00000000000088c0ULL, .field_start = 193, .field_count = 0 },
-  { .id = "c_bstart_vseq_16_50d70de3f84f", .mnemonic = "C.BSTART.VSEQ", .asm_fmt = "C.BSTART.VSEQ FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x000000000000c8c0ULL, .field_start = 193, .field_count = 0 },
-  { .id = "c_bstop_16_ca4743d8a95e", .mnemonic = "C.BSTOP", .asm_fmt = "C.BSTOP", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x0000000000000000ULL, .field_start = 193, .field_count = 0 },
-  { .id = "c_cmp_eqi_16_e34367883ba1", .mnemonic = "C.CMP.EQI", .asm_fmt = "c.cmp.eqi t#1, simm, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000002cULL, .field_start = 193, .field_count = 1 },
-  { .id = "c_cmp_nei_16_35d1f02063e2", .mnemonic = "C.CMP.NEI", .asm_fmt = "c.cmp.nei t#1, simm, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000082cULL, .field_start = 194, .field_count = 1 },
-  { .id = "c_ebreak_16_7f9c245fa13c", .mnemonic = "C.EBREAK", .asm_fmt = "c.break imm", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000c02cULL, .field_start = 195, .field_count = 1 },
-  { .id = "c_ldi_16_973f42d37f29", .mnemonic = "C.LDI", .asm_fmt = "c.ldi [srcL, simm], ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000001aULL, .field_start = 196, .field_count = 2 },
-  { .id = "c_lwi_16_b224525971da", .mnemonic = "C.LWI", .asm_fmt = "c.lwi [srcL, simm], ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000000aULL, .field_start = 198, .field_count = 2 },
-  { .id = "c_movi_16_2c84faf1bc72", .mnemonic = "C.MOVI", .asm_fmt = "c.movi simm, ->{t, u, Rd}", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000016ULL, .field_start = 200, .field_count = 2 },
-  { .id = "c_movr_16_80d2b5f3580b", .mnemonic = "C.MOVR", .asm_fmt = "c.movr SrcL, ->{t, u, Rd}", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000006ULL, .field_start = 202, .field_count = 2 },
-  { .id = "c_or_16_90864d13a661", .mnemonic = "C.OR", .asm_fmt = "c.or srcL, srcR, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000038ULL, .field_start = 204, .field_count = 2 },
-  { .id = "c_sdi_16_bbec69bcfd5d", .mnemonic = "C.SDI", .asm_fmt = "c.sdi t#1, [srcL, simm]", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000003aULL, .field_start = 206, .field_count = 2 },
-  { .id = "c_setc_eq_16_03e6b07a3699", .mnemonic = "C.SETC.EQ", .asm_fmt = "c.setc.eq srcL, srcR", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000026ULL, .field_start = 208, .field_count = 2 },
-  { .id = "c_setc_ne_16_e9092e487e98", .mnemonic = "C.SETC.NE", .asm_fmt = "c.setc.ne srcL, srcR", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000036ULL, .field_start = 210, .field_count = 2 },
-  { .id = "c_setc_tgt_16_736be9cada01", .mnemonic = "C.SETC.TGT", .asm_fmt = "c.setc.tgt srcL", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000001cULL, .field_start = 212, .field_count = 1 },
-  { .id = "c_setret_16_335651ef6c27", .mnemonic = "C.SETRET", .asm_fmt = "c.setret uimm, - >Ra", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x0000000000005016ULL, .field_start = 213, .field_count = 1 },
-  { .id = "c_sext_b_16_8ffd07d15409", .mnemonic = "C.SEXT.B", .asm_fmt = "c.sext.b srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000401cULL, .field_start = 214, .field_count = 1 },
-  { .id = "c_sext_h_16_90cb7ea36bd3", .mnemonic = "C.SEXT.H", .asm_fmt = "c.sext.h srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000481cULL, .field_start = 215, .field_count = 1 },
-  { .id = "c_sext_w_16_f2bb13f0797b", .mnemonic = "C.SEXT.W", .asm_fmt = "c.sext.w srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000501cULL, .field_start = 216, .field_count = 1 },
-  { .id = "c_slli_16_958a14dc4058", .mnemonic = "C.SLLI", .asm_fmt = "c.slli t#1, uimm, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000102cULL, .field_start = 217, .field_count = 1 },
-  { .id = "c_srli_16_b411862f7820", .mnemonic = "C.SRLI", .asm_fmt = "c.srli t#1, uimm, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000182cULL, .field_start = 218, .field_count = 1 },
-  { .id = "c_ssrget_16_9d83a6f2749a", .mnemonic = "C.SSRGET", .asm_fmt = "c.ssrget SSR-ID, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000802cULL, .field_start = 219, .field_count = 1 },
-  { .id = "c_sub_16_ff0056ac7053", .mnemonic = "C.SUB", .asm_fmt = "c.sub srcL, srcR, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000018ULL, .field_start = 220, .field_count = 2 },
-  { .id = "c_swi_16_ca6c111163e5", .mnemonic = "C.SWI", .asm_fmt = "c.swi t#1, [srcL, simm]", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000002aULL, .field_start = 222, .field_count = 2 },
-  { .id = "c_zext_b_16_7ea1a59fa2da", .mnemonic = "C.ZEXT.B", .asm_fmt = "c.zext.b srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000581cULL, .field_start = 224, .field_count = 1 },
-  { .id = "c_zext_h_16_4c0976791cbc", .mnemonic = "C.ZEXT.H", .asm_fmt = "c.zext.h srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000601cULL, .field_start = 225, .field_count = 1 },
-  { .id = "c_zext_w_16_e8bc051c7e8c", .mnemonic = "C.ZEXT.W", .asm_fmt = "c.zext.w srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000681cULL, .field_start = 226, .field_count = 1 },
-  { .id = "casb_32_7e529b871832", .mnemonic = "CASB", .asm_fmt = "casb<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000001bULL, .field_start = 227, .field_count = 6 },
-  { .id = "casd_32_5852c57277a6", .mnemonic = "CASD", .asm_fmt = "casd<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000301bULL, .field_start = 233, .field_count = 6 },
-  { .id = "cash_32_cb1315ff6cb5", .mnemonic = "CASH", .asm_fmt = "cash<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000101bULL, .field_start = 239, .field_count = 6 },
-  { .id = "casw_32_cb29e4287223", .mnemonic = "CASW", .asm_fmt = "casw<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000201bULL, .field_start = 245, .field_count = 6 },
-  { .id = "clz_32_f890415c15b6", .mnemonic = "CLZ", .asm_fmt = "clz SrcL,  M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005067ULL, .field_start = 251, .field_count = 4 },
-  { .id = "cmp_and_32_036813a12ae8", .mnemonic = "CMP.AND", .asm_fmt = "cmp.and SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000002045ULL, .field_start = 255, .field_count = 4 },
-  { .id = "cmp_andi_32_da7a5391738d", .mnemonic = "CMP.ANDI", .asm_fmt = "cmp.andi SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002055ULL, .field_start = 259, .field_count = 3 },
-  { .id = "cmp_eq_32_6af7c8f41300", .mnemonic = "CMP.EQ", .asm_fmt = "cmp.eq SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000000045ULL, .field_start = 262, .field_count = 4 },
-  { .id = "cmp_eqi_32_252943516dca", .mnemonic = "CMP.EQI", .asm_fmt = "cmp.eqi SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000055ULL, .field_start = 266, .field_count = 3 },
-  { .id = "cmp_ge_32_d88e3a1cfff4", .mnemonic = "CMP.GE", .asm_fmt = "cmp.ge SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000005045ULL, .field_start = 269, .field_count = 4 },
-  { .id = "cmp_gei_32_48bf7ea50737", .mnemonic = "CMP.GEI", .asm_fmt = "cmp.gei SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005055ULL, .field_start = 273, .field_count = 3 },
-  { .id = "cmp_geu_32_0c002dc415ef", .mnemonic = "CMP.GEU", .asm_fmt = "cmp.geu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000007045ULL, .field_start = 276, .field_count = 4 },
-  { .id = "cmp_geui_32_69ec7b908f5d", .mnemonic = "CMP.GEUI", .asm_fmt = "cmp.geui SrcL, uimm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007055ULL, .field_start = 280, .field_count = 3 },
-  { .id = "cmp_lt_32_c0b8cc320f12", .mnemonic = "CMP.LT", .asm_fmt = "cmp.lt SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000004045ULL, .field_start = 283, .field_count = 4 },
-  { .id = "cmp_lti_32_02d3081d120b", .mnemonic = "CMP.LTI", .asm_fmt = "cmp.lti SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004055ULL, .field_start = 287, .field_count = 3 },
-  { .id = "cmp_ltu_32_4377481baebc", .mnemonic = "CMP.LTU", .asm_fmt = "cmp.ltu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000006045ULL, .field_start = 290, .field_count = 4 },
-  { .id = "cmp_ltui_32_8676c7bfd797", .mnemonic = "CMP.LTUI", .asm_fmt = "cmp.ltui SrcL, uimm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006055ULL, .field_start = 294, .field_count = 3 },
-  { .id = "cmp_ne_32_fc47fbb1a0de", .mnemonic = "CMP.NE", .asm_fmt = "cmp.ne SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000001045ULL, .field_start = 297, .field_count = 4 },
-  { .id = "cmp_nei_32_00abf831b572", .mnemonic = "CMP.NEI", .asm_fmt = "cmp.nei SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001055ULL, .field_start = 301, .field_count = 3 },
-  { .id = "cmp_or_32_75e1fa54ba94", .mnemonic = "CMP.OR", .asm_fmt = "cmp.or SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000003045ULL, .field_start = 304, .field_count = 4 },
-  { .id = "cmp_ori_32_6d3efbc3d093", .mnemonic = "CMP.ORI", .asm_fmt = "cmp.ori SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003055ULL, .field_start = 308, .field_count = 3 },
-  { .id = "csel_32_ba77cbad3c99", .mnemonic = "CSEL", .asm_fmt = "csel SrcP, SrcL, SrcR<.neg>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000077ULL, .field_start = 311, .field_count = 5 },
-  { .id = "ctz_32_1761cbcc2a89", .mnemonic = "CTZ", .asm_fmt = "ctz SrcL,  M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004067ULL, .field_start = 316, .field_count = 4 },
-  { .id = "dc_cisw_32_166b7135e3c1", .mnemonic = "DC.CISW", .asm_fmt = "dc.cisw SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000060602bULL, .field_start = 320, .field_count = 1 },
-  { .id = "dc_civa_32_265d686549c8", .mnemonic = "DC.CIVA", .asm_fmt = "dc.civa SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000030602bULL, .field_start = 321, .field_count = 1 },
-  { .id = "dc_csw_32_2719115a9246", .mnemonic = "DC.CSW", .asm_fmt = "dc.csw SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000050602bULL, .field_start = 322, .field_count = 1 },
-  { .id = "dc_cva_32_166d5a076f0e", .mnemonic = "DC.CVA", .asm_fmt = "dc.cva SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000020602bULL, .field_start = 323, .field_count = 1 },
-  { .id = "dc_iall_32_3d61563dd077", .mnemonic = "DC.IALL", .asm_fmt = "dc.iall", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x000000000010602bULL, .field_start = 324, .field_count = 0 },
-  { .id = "dc_isw_32_7940273560b2", .mnemonic = "DC.ISW", .asm_fmt = "dc.isw SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000040602bULL, .field_start = 324, .field_count = 1 },
-  { .id = "dc_iva_32_0131d0cf364f", .mnemonic = "DC.IVA", .asm_fmt = "dc.iva SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000000602bULL, .field_start = 325, .field_count = 1 },
-  { .id = "dc_zva_32_0859a1d7aa5b", .mnemonic = "DC.ZVA", .asm_fmt = "dc.zva SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000070602bULL, .field_start = 326, .field_count = 1 },
-  { .id = "div_32_a6efe85f8662", .mnemonic = "DIV", .asm_fmt = "div SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000000057ULL, .field_start = 327, .field_count = 3 },
-  { .id = "divu_32_cfbc0d1760e4", .mnemonic = "DIVU", .asm_fmt = "divu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000001057ULL, .field_start = 330, .field_count = 3 },
-  { .id = "divuw_32_9c9470ef8982", .mnemonic = "DIVUW", .asm_fmt = "divuw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000003057ULL, .field_start = 333, .field_count = 3 },
-  { .id = "divw_32_b6366c50ac8c", .mnemonic = "DIVW", .asm_fmt = "divw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000002057ULL, .field_start = 336, .field_count = 3 },
-  { .id = "dma_32_a168aeca5fa5", .mnemonic = "DMA", .asm_fmt = "dma [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000fe007fffULL, .match = 0x000000000000700bULL, .field_start = 339, .field_count = 2 },
-  { .id = "ebreak_32_4f122d1e6be3", .mnemonic = "EBREAK", .asm_fmt = "ebreak imm", .length_bits = 32, .mask = 0x00000000f0ffffffULL, .match = 0x000000000010102bULL, .field_start = 341, .field_count = 1 },
-  { .id = "ercov_32_dc0be14a2d8b", .mnemonic = "ERCOV", .asm_fmt = "ERCOV [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind]", .length_bits = 32, .mask = 0x0000000006007fffULL, .match = 0x0000000000003031ULL, .field_start = 342, .field_count = 3 },
-  { .id = "esave_32_4c4f79fe3171", .mnemonic = "ESAVE", .asm_fmt = "ESAVE [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind]", .length_bits = 32, .mask = 0x0000000006007fffULL, .match = 0x0000000000002031ULL, .field_start = 345, .field_count = 3 },
-  { .id = "fabs_32_9515e008bf17", .mnemonic = "FABS", .asm_fmt = "fabs.{T} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f9f0707fULL, .match = 0x000000000000007bULL, .field_start = 348, .field_count = 3 },
-  { .id = "fadd_32_b78b658e6740", .mnemonic = "FADD", .asm_fmt = "fadd.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000004bULL, .field_start = 351, .field_count = 4 },
-  { .id = "fcvt_32_1102f5aeeda9", .mnemonic = "FCVT", .asm_fmt = "fcvt.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000006bULL, .field_start = 355, .field_count = 4 },
-  { .id = "fcvta_32_010837b9acbd", .mnemonic = "FCVTA", .asm_fmt = "fcvta.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000106bULL, .field_start = 359, .field_count = 4 },
-  { .id = "fcvtm_32_8801f1562870", .mnemonic = "FCVTM", .asm_fmt = "fcvtm.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000206bULL, .field_start = 363, .field_count = 4 },
-  { .id = "fcvtn_32_8714ba358d80", .mnemonic = "FCVTN", .asm_fmt = "fcvtn.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000306bULL, .field_start = 367, .field_count = 4 },
-  { .id = "fcvtp_32_84354a7aa6b1", .mnemonic = "FCVTP", .asm_fmt = "fcvtp.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000406bULL, .field_start = 371, .field_count = 4 },
-  { .id = "fcvtz_32_bee01d31217c", .mnemonic = "FCVTZ", .asm_fmt = "fcvtz.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000506bULL, .field_start = 375, .field_count = 4 },
-  { .id = "fdiv_32_04a5bb6ab56f", .mnemonic = "FDIV", .asm_fmt = "fdiv.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000304bULL, .field_start = 379, .field_count = 4 },
-  { .id = "fence_d_32_f4783f17d84d", .mnemonic = "FENCE.D", .asm_fmt = "fence.d pred_imm, succ_imm", .length_bits = 32, .mask = 0x00000000f00fffffULL, .match = 0x000000000000202bULL, .field_start = 383, .field_count = 2 },
-  { .id = "fence_i_32_a321a2a186b1", .mnemonic = "FENCE.I", .asm_fmt = "fence.i", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x000000001000202bULL, .field_start = 385, .field_count = 0 },
-  { .id = "fentry_32_a47584ec13b6", .mnemonic = "FENTRY", .asm_fmt = "FENTRY [RegSrc0 ~ RegSrcn], sp!, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000041ULL, .field_start = 385, .field_count = 3 },
-  { .id = "feq_32_9435d6959c3c", .mnemonic = "FEQ", .asm_fmt = "feq.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000005bULL, .field_start = 388, .field_count = 4 },
-  { .id = "feqs_32_1d3011890fa8", .mnemonic = "FEQS", .asm_fmt = "feqs.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000800005bULL, .field_start = 392, .field_count = 4 },
-  { .id = "fexit_32_37b663f2a34d", .mnemonic = "FEXIT", .asm_fmt = "FEXIT [RegDst0 ~ RegDstn], sp!, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001041ULL, .field_start = 396, .field_count = 3 },
-  { .id = "fexp_32_592ef5288c7d", .mnemonic = "FEXP", .asm_fmt = "fexp.{T} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f9f0707fULL, .match = 0x000000000000307bULL, .field_start = 399, .field_count = 3 },
-  { .id = "fge_32_b3244b2ffa89", .mnemonic = "FGE", .asm_fmt = "fge.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000305bULL, .field_start = 402, .field_count = 4 },
-  { .id = "fges_32_e0301fcee743", .mnemonic = "FGES", .asm_fmt = "fges.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000800305bULL, .field_start = 406, .field_count = 4 },
-  { .id = "flt_32_1c09549d8d3f", .mnemonic = "FLT", .asm_fmt = "flt.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000205bULL, .field_start = 410, .field_count = 4 },
-  { .id = "flts_32_c744c874e6a2", .mnemonic = "FLTS", .asm_fmt = "flts.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000800205bULL, .field_start = 414, .field_count = 4 },
-  { .id = "fmadd_32_c616a17bcb12", .mnemonic = "FMADD", .asm_fmt = "fmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000404bULL, .field_start = 418, .field_count = 5 },
-  { .id = "fmax_32_eaf3880d7739", .mnemonic = "FMAX", .asm_fmt = "fmax.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000605bULL, .field_start = 423, .field_count = 4 },
-  { .id = "fmin_32_b5c106e5cd7e", .mnemonic = "FMIN", .asm_fmt = "fmin.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000705bULL, .field_start = 427, .field_count = 4 },
-  { .id = "fmsub_32_b83012b83148", .mnemonic = "FMSUB", .asm_fmt = "fmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000504bULL, .field_start = 431, .field_count = 5 },
-  { .id = "fmul_32_7d521d9d65e7", .mnemonic = "FMUL", .asm_fmt = "fmul.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000204bULL, .field_start = 436, .field_count = 4 },
-  { .id = "fne_32_822c18caca3b", .mnemonic = "FNE", .asm_fmt = "fne.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000105bULL, .field_start = 440, .field_count = 4 },
-  { .id = "fnes_32_9b4b5a493783", .mnemonic = "FNES", .asm_fmt = "fnes.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000800105bULL, .field_start = 444, .field_count = 4 },
-  { .id = "fnmadd_32_7f45e606d299", .mnemonic = "FNMADD", .asm_fmt = "fnmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000604bULL, .field_start = 448, .field_count = 5 },
-  { .id = "fnmsub_32_6542d56665b3", .mnemonic = "FNMSUB", .asm_fmt = "fnmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000704bULL, .field_start = 453, .field_count = 5 },
-  { .id = "frecip_32_3d51f4f727ea", .mnemonic = "FRECIP", .asm_fmt = "frecip.{T} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f9f0707fULL, .match = 0x000000000000207bULL, .field_start = 458, .field_count = 3 },
-  { .id = "fret_ra_32_659c886221c1", .mnemonic = "FRET.RA", .asm_fmt = "FRET.RA [RegDst0 ~ RegDstn], sp!, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002041ULL, .field_start = 461, .field_count = 3 },
-  { .id = "fret_stk_32_4fe246bd8241", .mnemonic = "FRET.STK", .asm_fmt = "FRET.STK [RegDst0 ~ RegDstn], sp!, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003041ULL, .field_start = 464, .field_count = 3 },
-  { .id = "fsqrt_32_84b3495cc6c7", .mnemonic = "FSQRT", .asm_fmt = "fsqrt.{T} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f9f0707fULL, .match = 0x000000000000107bULL, .field_start = 467, .field_count = 3 },
-  { .id = "fsub_32_a4479d0d4276", .mnemonic = "FSUB", .asm_fmt = "fsub.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000104bULL, .field_start = 470, .field_count = 4 },
-  { .id = "hl_addi_48_9d3818bfbe64", .mnemonic = "HL.ADDI", .asm_fmt = "hl.addi SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000015000eULL, .field_start = 474, .field_count = 3 },
-  { .id = "hl_addiw_48_f6d7f5032964", .mnemonic = "HL.ADDIW", .asm_fmt = "hl.addiw SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000035000eULL, .field_start = 477, .field_count = 3 },
-  { .id = "hl_addtpc_48_2e8e692eea09", .mnemonic = "HL.ADDTPC", .asm_fmt = "hl.addtpc imm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000007f000fULL, .match = 0x000000000007000eULL, .field_start = 480, .field_count = 2 },
-  { .id = "hl_andi_48_fe11c7ebca41", .mnemonic = "HL.ANDI", .asm_fmt = "hl.andi SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002015000eULL, .field_start = 482, .field_count = 3 },
-  { .id = "hl_andiw_48_878c6594c6ff", .mnemonic = "HL.ANDIW", .asm_fmt = "hl.andiw SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002035000eULL, .field_start = 485, .field_count = 3 },
-  { .id = "hl_bfi_48_8adfd476aacc", .mnemonic = "HL.BFI", .asm_fmt = "hl.bfi SrcL, SrcR, M, N, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000fe00707f000fULL, .match = 0x00000000204d000eULL, .field_start = 488, .field_count = 5 },
-  { .id = "hl_bstart_call_48_3c784c583c90", .mnemonic = "HL.BSTART CALL", .asm_fmt = "HL.BSTART.CALL <br_label>, <rt_label>, ->ra", .length_bits = 48, .mask = 0x0000f83f0000007fULL, .match = 0x0000501600000011ULL, .field_start = 493, .field_count = 2 },
-  { .id = "hl_bstart_fp_48_038e2e96cf64", .mnemonic = "HL.BSTART.FP", .asm_fmt = "HL.BSTART.FP COND, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000003101000eULL, .field_start = 495, .field_count = 1 },
-  { .id = "hl_bstart_fp_48_43530d2ebfae", .mnemonic = "HL.BSTART.FP", .asm_fmt = "HL.BSTART.FP FALL<, fixup_label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000001101000eULL, .field_start = 496, .field_count = 1 },
-  { .id = "hl_bstart_fp_48_81b457553844", .mnemonic = "HL.BSTART.FP", .asm_fmt = "HL.BSTART.FP CALL, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000004101000eULL, .field_start = 497, .field_count = 1 },
-  { .id = "hl_bstart_fp_48_eb938e9200eb", .mnemonic = "HL.BSTART.FP", .asm_fmt = "HL.BSTART.FP DIRECT, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000002101000eULL, .field_start = 498, .field_count = 1 },
-  { .id = "hl_bstart_std_48_51f78942222e", .mnemonic = "HL.BSTART.STD", .asm_fmt = "HL.BSTART.STD CALL, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000004001000eULL, .field_start = 499, .field_count = 1 },
-  { .id = "hl_bstart_std_48_9ba705710872", .mnemonic = "HL.BSTART.STD", .asm_fmt = "HL.BSTART.STD FALL<, fixup_label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000001001000eULL, .field_start = 500, .field_count = 1 },
-  { .id = "hl_bstart_std_48_b13f22c7c4a3", .mnemonic = "HL.BSTART.STD", .asm_fmt = "HL.BSTART.STD COND, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000003001000eULL, .field_start = 501, .field_count = 1 },
-  { .id = "hl_bstart_std_48_d814d26508a4", .mnemonic = "HL.BSTART.STD", .asm_fmt = "HL.BSTART.STD DIRECT, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000002001000eULL, .field_start = 502, .field_count = 1 },
-  { .id = "hl_bstart_sys_48_5bf0381f7bf8", .mnemonic = "HL.BSTART.SYS", .asm_fmt = "HL.BSTART.SYS FALL<, fixup_label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000001081000eULL, .field_start = 503, .field_count = 1 },
-  { .id = "hl_casb_48_21fb578617a8", .mnemonic = "HL.CASB", .asm_fmt = "hl.casb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000f000707ff83fULL, .match = 0x00000000600b000eULL, .field_start = 504, .field_count = 7 },
-  { .id = "hl_casd_48_fbb5c4256d30", .mnemonic = "HL.CASD", .asm_fmt = "hl.casd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000f000707ff83fULL, .match = 0x00003000600b000eULL, .field_start = 511, .field_count = 7 },
-  { .id = "hl_cash_48_eee12c324d97", .mnemonic = "HL.CASH", .asm_fmt = "hl.cash<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000f000707ff83fULL, .match = 0x00001000600b000eULL, .field_start = 518, .field_count = 7 },
-  { .id = "hl_casw_48_a89b3d58d8f0", .mnemonic = "HL.CASW", .asm_fmt = "hl.casw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000f000707ff83fULL, .match = 0x00002000600b000eULL, .field_start = 525, .field_count = 7 },
-  { .id = "hl_ccat_48_a1200d8bf5ac", .mnemonic = "HL.CCAT", .asm_fmt = "hl.ccat SrcL, SrcR, shamt, ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x00000000105d000eULL, .field_start = 532, .field_count = 5 },
-  { .id = "hl_ccatw_48_24a85ea4659c", .mnemonic = "HL.CCATW", .asm_fmt = "hl.ccatw SrcL, SrcR, shamt, ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x00000000205d000eULL, .field_start = 537, .field_count = 5 },
-  { .id = "hl_cmp_andi_48_de2aae3f4516", .mnemonic = "HL.CMP.ANDI", .asm_fmt = "hl.cmp.andi SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002055000eULL, .field_start = 542, .field_count = 3 },
-  { .id = "hl_cmp_eqi_48_887accd218b1", .mnemonic = "HL.CMP.EQI", .asm_fmt = "hl.cmp.eqi SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000055000eULL, .field_start = 545, .field_count = 3 },
-  { .id = "hl_cmp_gei_48_b3703d4c4619", .mnemonic = "HL.CMP.GEI", .asm_fmt = "hl.cmp.gei SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000005055000eULL, .field_start = 548, .field_count = 3 },
-  { .id = "hl_cmp_geui_48_c71f4fb29e6b", .mnemonic = "HL.CMP.GEUI", .asm_fmt = "hl.cmp.geui SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000007055000eULL, .field_start = 551, .field_count = 3 },
-  { .id = "hl_cmp_lti_48_bec21b77021a", .mnemonic = "HL.CMP.LTI", .asm_fmt = "hl.cmp.lti SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004055000eULL, .field_start = 554, .field_count = 3 },
-  { .id = "hl_cmp_ltui_48_d12167277d58", .mnemonic = "HL.CMP.LTUI", .asm_fmt = "hl.cmp.ltui SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000006055000eULL, .field_start = 557, .field_count = 3 },
-  { .id = "hl_cmp_nei_48_e77da507704a", .mnemonic = "HL.CMP.NEI", .asm_fmt = "hl.cmp.nei SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001055000eULL, .field_start = 560, .field_count = 3 },
-  { .id = "hl_cmp_ori_48_4167568cb50b", .mnemonic = "HL.CMP.ORI", .asm_fmt = "hl.cmp.ori SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003055000eULL, .field_start = 563, .field_count = 3 },
-  { .id = "hl_div_48_e8ff1fc1cb98", .mnemonic = "HL.DIV", .asm_fmt = "hl.div SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000000057000eULL, .field_start = 566, .field_count = 4 },
-  { .id = "hl_divu_48_597acda29e08", .mnemonic = "HL.DIVU", .asm_fmt = "hl.divu SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000001057000eULL, .field_start = 570, .field_count = 4 },
-  { .id = "hl_divuw_48_9ebe516091b8", .mnemonic = "HL.DIVUW", .asm_fmt = "hl.divuw SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000003057000eULL, .field_start = 574, .field_count = 4 },
-  { .id = "hl_divw_48_9048cdb3b22f", .mnemonic = "HL.DIVW", .asm_fmt = "hl.divw SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000002057000eULL, .field_start = 578, .field_count = 4 },
-  { .id = "hl_lb_pcr_48_c0ba9a54c8e0", .mnemonic = "HL.LB.PCR", .asm_fmt = "hl.lb.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000039000eULL, .field_start = 582, .field_count = 2 },
-  { .id = "hl_lb_po_48_5c7f5c82b186", .mnemonic = "HL.LB.PO", .asm_fmt = "hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000000009003eULL, .field_start = 584, .field_count = 6 },
-  { .id = "hl_lb_pr_48_cf73675cad50", .mnemonic = "HL.LB.PR", .asm_fmt = "hl.lb.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000000009002eULL, .field_start = 590, .field_count = 6 },
-  { .id = "hl_lbi_48_250803040cc8", .mnemonic = "HL.LBI", .asm_fmt = "hl.lbi [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000019000eULL, .field_start = 596, .field_count = 3 },
-  { .id = "hl_lbi_po_48_afbc00c48aba", .mnemonic = "HL.LBI.PO", .asm_fmt = "hl.lbi.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000019003eULL, .field_start = 599, .field_count = 4 },
-  { .id = "hl_lbi_pr_48_b4bdbd29f859", .mnemonic = "HL.LBI.PR", .asm_fmt = "hl.lbi.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000019002eULL, .field_start = 603, .field_count = 4 },
-  { .id = "hl_lbip_48_70a5767aff16", .mnemonic = "HL.LBIP", .asm_fmt = "hl.lbip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000019001eULL, .field_start = 607, .field_count = 4 },
-  { .id = "hl_lbp_48_9d1fd0b3105b", .mnemonic = "HL.LBP", .asm_fmt = "hl.lbp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000000009001eULL, .field_start = 611, .field_count = 6 },
-  { .id = "hl_lbu_pcr_48_504b34c0ec9d", .mnemonic = "HL.LBU.PCR", .asm_fmt = "hl.lbu.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004039000eULL, .field_start = 617, .field_count = 2 },
-  { .id = "hl_lbu_po_48_5c8a5b39e6c5", .mnemonic = "HL.LBU.PO", .asm_fmt = "hl.lbu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000004009003eULL, .field_start = 619, .field_count = 6 },
-  { .id = "hl_lbu_pr_48_bf9a0ea4b0db", .mnemonic = "HL.LBU.PR", .asm_fmt = "hl.lbu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000004009002eULL, .field_start = 625, .field_count = 6 },
-  { .id = "hl_lbui_48_50579e3558f4", .mnemonic = "HL.LBUI", .asm_fmt = "hl.lbui [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000004019000eULL, .field_start = 631, .field_count = 3 },
-  { .id = "hl_lbui_po_48_c889b4445022", .mnemonic = "HL.LBUI.PO", .asm_fmt = "hl.lbui.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000004019003eULL, .field_start = 634, .field_count = 4 },
-  { .id = "hl_lbui_pr_48_78a81538a7fa", .mnemonic = "HL.LBUI.PR", .asm_fmt = "hl.lbui.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000004019002eULL, .field_start = 638, .field_count = 4 },
-  { .id = "hl_lbuip_48_ad419fc474c0", .mnemonic = "HL.LBUIP", .asm_fmt = "hl.lbuip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000004019001eULL, .field_start = 642, .field_count = 4 },
-  { .id = "hl_lbup_48_c9598658dde4", .mnemonic = "HL.LBUP", .asm_fmt = "hl.lbup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000004009001eULL, .field_start = 646, .field_count = 6 },
-  { .id = "hl_ld_pcr_48_703673c266da", .mnemonic = "HL.LD.PCR", .asm_fmt = "hl.ld.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003039000eULL, .field_start = 652, .field_count = 2 },
-  { .id = "hl_ld_po_48_870e30995d10", .mnemonic = "HL.LD.PO", .asm_fmt = "hl.ld.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000003009003eULL, .field_start = 654, .field_count = 6 },
-  { .id = "hl_ld_pr_48_7ec4111b123b", .mnemonic = "HL.LD.PR", .asm_fmt = "hl.ld.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000003009002eULL, .field_start = 660, .field_count = 6 },
-  { .id = "hl_ldi_48_088e69e45b37", .mnemonic = "HL.LDI", .asm_fmt = "hl.ldi [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003019000eULL, .field_start = 666, .field_count = 3 },
-  { .id = "hl_ldi_po_48_0cc539e6798d", .mnemonic = "HL.LDI.PO", .asm_fmt = "hl.ldi.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003019003eULL, .field_start = 669, .field_count = 4 },
-  { .id = "hl_ldi_pr_48_d07cced5a281", .mnemonic = "HL.LDI.PR", .asm_fmt = "hl.ldi.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003019002eULL, .field_start = 673, .field_count = 4 },
-  { .id = "hl_ldi_u_48_894d02c12dcc", .mnemonic = "HL.LDI.U", .asm_fmt = "hl.ldi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003029000eULL, .field_start = 677, .field_count = 3 },
-  { .id = "hl_ldi_upo_48_5126b735cfe8", .mnemonic = "HL.LDI.UPO", .asm_fmt = "hl.ldi.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003029003eULL, .field_start = 680, .field_count = 4 },
-  { .id = "hl_ldi_upr_48_7a8e2794526f", .mnemonic = "HL.LDI.UPR", .asm_fmt = "hl.ldi.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003029002eULL, .field_start = 684, .field_count = 4 },
-  { .id = "hl_ldip_48_60afa6423d39", .mnemonic = "HL.LDIP", .asm_fmt = "hl.ldip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003019001eULL, .field_start = 688, .field_count = 4 },
-  { .id = "hl_ldip_u_48_6813f4fdce5c", .mnemonic = "HL.LDIP.U", .asm_fmt = "hl.ldip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003029001eULL, .field_start = 692, .field_count = 4 },
-  { .id = "hl_ldp_48_a7a45a43dff9", .mnemonic = "HL.LDP", .asm_fmt = "hl.ldp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000003009001eULL, .field_start = 696, .field_count = 6 },
-  { .id = "hl_lh_pcr_48_37df3cfe0d6e", .mnemonic = "HL.LH.PCR", .asm_fmt = "hl.lh.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001039000eULL, .field_start = 702, .field_count = 2 },
-  { .id = "hl_lh_po_48_7ca3e8b77906", .mnemonic = "HL.LH.PO", .asm_fmt = "hl.lh.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000001009003eULL, .field_start = 704, .field_count = 6 },
-  { .id = "hl_lh_pr_48_d59f64cde1dc", .mnemonic = "HL.LH.PR", .asm_fmt = "hl.lh.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000001009002eULL, .field_start = 710, .field_count = 6 },
-  { .id = "hl_lhi_48_6d94cb04aeac", .mnemonic = "HL.LHI", .asm_fmt = "hl.lhi [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001019000eULL, .field_start = 716, .field_count = 3 },
-  { .id = "hl_lhi_po_48_aa393747abda", .mnemonic = "HL.LHI.PO", .asm_fmt = "hl.lhi.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001019003eULL, .field_start = 719, .field_count = 4 },
-  { .id = "hl_lhi_pr_48_9ec8198594ad", .mnemonic = "HL.LHI.PR", .asm_fmt = "hl.lhi.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001019002eULL, .field_start = 723, .field_count = 4 },
-  { .id = "hl_lhi_u_48_4d4b89e63c98", .mnemonic = "HL.LHI.U", .asm_fmt = "hl.lhi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001029000eULL, .field_start = 727, .field_count = 3 },
-  { .id = "hl_lhi_upo_48_81c796b13b12", .mnemonic = "HL.LHI.UPO", .asm_fmt = "hl.lhi.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001029003eULL, .field_start = 730, .field_count = 4 },
-  { .id = "hl_lhi_upr_48_2a7c09d4b645", .mnemonic = "HL.LHI.UPR", .asm_fmt = "hl.lhi.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001029002eULL, .field_start = 734, .field_count = 4 },
-  { .id = "hl_lhip_48_2c664751c537", .mnemonic = "HL.LHIP", .asm_fmt = "hl.lhip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001019001eULL, .field_start = 738, .field_count = 4 },
-  { .id = "hl_lhip_u_48_e37e98d63bfd", .mnemonic = "HL.LHIP.U", .asm_fmt = "hl.lhip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001029001eULL, .field_start = 742, .field_count = 4 },
-  { .id = "hl_lhp_48_128eb429101f", .mnemonic = "HL.LHP", .asm_fmt = "hl.lhp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000001009001eULL, .field_start = 746, .field_count = 6 },
-  { .id = "hl_lhu_pcr_48_444cb4ddde1d", .mnemonic = "HL.LHU.PCR", .asm_fmt = "hl.lhu.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000005039000eULL, .field_start = 752, .field_count = 2 },
-  { .id = "hl_lhu_po_48_c57c3b4a74e8", .mnemonic = "HL.LHU.PO", .asm_fmt = "hl.lhu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000005009003eULL, .field_start = 754, .field_count = 6 },
-  { .id = "hl_lhu_pr_48_f874b126e29c", .mnemonic = "HL.LHU.PR", .asm_fmt = "hl.lhu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000005009002eULL, .field_start = 760, .field_count = 6 },
-  { .id = "hl_lhui_48_6450dca3aad9", .mnemonic = "HL.LHUI", .asm_fmt = "hl.lhui [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005019000eULL, .field_start = 766, .field_count = 3 },
-  { .id = "hl_lhui_po_48_16db8d40eee8", .mnemonic = "HL.LHUI.PO", .asm_fmt = "hl.lhui.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005019003eULL, .field_start = 769, .field_count = 4 },
-  { .id = "hl_lhui_pr_48_6a99a2b99298", .mnemonic = "HL.LHUI.PR", .asm_fmt = "hl.lhui.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005019002eULL, .field_start = 773, .field_count = 4 },
-  { .id = "hl_lhui_u_48_d75649bac1c7", .mnemonic = "HL.LHUI.U", .asm_fmt = "hl.lhui.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005029000eULL, .field_start = 777, .field_count = 3 },
-  { .id = "hl_lhui_upo_48_7f2c3eae793e", .mnemonic = "HL.LHUI.UPO", .asm_fmt = "hl.lhui.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005029003eULL, .field_start = 780, .field_count = 4 },
-  { .id = "hl_lhui_upr_48_7e66aaf61701", .mnemonic = "HL.LHUI.UPR", .asm_fmt = "hl.lhui.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005029002eULL, .field_start = 784, .field_count = 4 },
-  { .id = "hl_lhuip_48_0b0ef5bd2405", .mnemonic = "HL.LHUIP", .asm_fmt = "hl.lhuip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005019001eULL, .field_start = 788, .field_count = 4 },
-  { .id = "hl_lhuip_u_48_11a0e580caf1", .mnemonic = "HL.LHUIP.U", .asm_fmt = "hl.lhuip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005029001eULL, .field_start = 792, .field_count = 4 },
-  { .id = "hl_lhup_48_ea24f978b27a", .mnemonic = "HL.LHUP", .asm_fmt = "hl.lhup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000005009001eULL, .field_start = 796, .field_count = 6 },
-  { .id = "hl_lis_48_908853d6ef87", .mnemonic = "HL.LIS", .asm_fmt = "hl.lis simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000007f000fULL, .match = 0x00000000000d000eULL, .field_start = 802, .field_count = 2 },
-  { .id = "hl_liu_48_9dd207ce3aea", .mnemonic = "HL.LIU", .asm_fmt = "hl.liu uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000007f000fULL, .match = 0x00000000001d000eULL, .field_start = 804, .field_count = 2 },
-  { .id = "hl_lui_48_255991889818", .mnemonic = "HL.LUI", .asm_fmt = "hl.lui imm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000007f000fULL, .match = 0x000000000017000eULL, .field_start = 806, .field_count = 2 },
-  { .id = "hl_lw_pcr_48_00cf25e2ac36", .mnemonic = "HL.LW.PCR", .asm_fmt = "hl.lw.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002039000eULL, .field_start = 808, .field_count = 2 },
-  { .id = "hl_lw_po_48_ff2c6de58064", .mnemonic = "HL.LW.PO", .asm_fmt = "hl.lw.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000002009003eULL, .field_start = 810, .field_count = 6 },
-  { .id = "hl_lw_pr_48_2b0d62d28b57", .mnemonic = "HL.LW.PR", .asm_fmt = "hl.lw.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000002009002eULL, .field_start = 816, .field_count = 6 },
-  { .id = "hl_lwi_48_549c666c56fd", .mnemonic = "HL.LWI", .asm_fmt = "hl.lwi [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002019000eULL, .field_start = 822, .field_count = 3 },
-  { .id = "hl_lwi_po_48_2dc642d88d9d", .mnemonic = "HL.LWI.PO", .asm_fmt = "hl.lwi.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002019003eULL, .field_start = 825, .field_count = 4 },
-  { .id = "hl_lwi_pr_48_3b5e1524de1b", .mnemonic = "HL.LWI.PR", .asm_fmt = "hl.lwi.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002019002eULL, .field_start = 829, .field_count = 4 },
-  { .id = "hl_lwi_u_48_267e0f4a6222", .mnemonic = "HL.LWI.U", .asm_fmt = "hl.lwi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002029000eULL, .field_start = 833, .field_count = 3 },
-  { .id = "hl_lwi_upo_48_1c25d6266934", .mnemonic = "HL.LWI.UPO", .asm_fmt = "hl.lwi.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002029003eULL, .field_start = 836, .field_count = 4 },
-  { .id = "hl_lwi_upr_48_03b5f7994b14", .mnemonic = "HL.LWI.UPR", .asm_fmt = "hl.lwi.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002029002eULL, .field_start = 840, .field_count = 4 },
-  { .id = "hl_lwip_48_e459297b8b7c", .mnemonic = "HL.LWIP", .asm_fmt = "hl.lwip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002019001eULL, .field_start = 844, .field_count = 4 },
-  { .id = "hl_lwip_u_48_c9aca369eab2", .mnemonic = "HL.LWIP.U", .asm_fmt = "hl.lwip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002029001eULL, .field_start = 848, .field_count = 4 },
-  { .id = "hl_lwp_48_10fe25c62553", .mnemonic = "HL.LWP", .asm_fmt = "hl.lwp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000002009001eULL, .field_start = 852, .field_count = 6 },
-  { .id = "hl_lwu_pcr_48_95ba33b7b68c", .mnemonic = "HL.LWU.PCR", .asm_fmt = "hl.lwu.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000006039000eULL, .field_start = 858, .field_count = 2 },
-  { .id = "hl_lwu_po_48_98730d2ddead", .mnemonic = "HL.LWU.PO", .asm_fmt = "hl.lwu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000006009003eULL, .field_start = 860, .field_count = 6 },
-  { .id = "hl_lwu_pr_48_f105cacec36c", .mnemonic = "HL.LWU.PR", .asm_fmt = "hl.lwu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000006009002eULL, .field_start = 866, .field_count = 6 },
-  { .id = "hl_lwui_48_eeb551f8269d", .mnemonic = "HL.LWUI", .asm_fmt = "hl.lwui [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006019000eULL, .field_start = 872, .field_count = 3 },
-  { .id = "hl_lwui_po_48_09a75b628dc4", .mnemonic = "HL.LWUI.PO", .asm_fmt = "hl.lwui.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006019003eULL, .field_start = 875, .field_count = 4 },
-  { .id = "hl_lwui_pr_48_32de19a508f0", .mnemonic = "HL.LWUI.PR", .asm_fmt = "hl.lwui.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006019002eULL, .field_start = 879, .field_count = 4 },
-  { .id = "hl_lwui_u_48_4570cc517629", .mnemonic = "HL.LWUI.U", .asm_fmt = "hl.lwui.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006029000eULL, .field_start = 883, .field_count = 3 },
-  { .id = "hl_lwui_upo_48_33260eb06a2c", .mnemonic = "HL.LWUI.UPO", .asm_fmt = "hl.lwui.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006029003eULL, .field_start = 886, .field_count = 4 },
-  { .id = "hl_lwui_upr_48_998a98c46469", .mnemonic = "HL.LWUI.UPR", .asm_fmt = "hl.lwui.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006029002eULL, .field_start = 890, .field_count = 4 },
-  { .id = "hl_lwuip_48_2a5d6d8f3b70", .mnemonic = "HL.LWUIP", .asm_fmt = "hl.lwuip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006019001eULL, .field_start = 894, .field_count = 4 },
-  { .id = "hl_lwuip_u_48_0fed3b8c43b6", .mnemonic = "HL.LWUIP.U", .asm_fmt = "hl.lwuip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006029001eULL, .field_start = 898, .field_count = 4 },
-  { .id = "hl_lwup_48_30f20380c354", .mnemonic = "HL.LWUP", .asm_fmt = "hl.lwup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000006009001eULL, .field_start = 902, .field_count = 6 },
-  { .id = "hl_madd_48_b062d741fd99", .mnemonic = "HL.MADD", .asm_fmt = "hl.madd SrcL, SrcR, SrcD, ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000600707f07ffULL, .match = 0x000000006047000eULL, .field_start = 908, .field_count = 5 },
-  { .id = "hl_maddw_48_6fac897f0264", .mnemonic = "HL.MADDW", .asm_fmt = "hl.maddw SrcL, SrcR, SrcD, ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000600707f07ffULL, .match = 0x000000007047000eULL, .field_start = 913, .field_count = 5 },
-  { .id = "hl_miadd_48_ec5127b6dfd6", .mnemonic = "HL.MIADD", .asm_fmt = "hl.miadd SrcL, SrcR, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x00000000004d000eULL, .field_start = 918, .field_count = 4 },
-  { .id = "hl_misub_48_e9e4c7b23479", .mnemonic = "HL.MISUB", .asm_fmt = "hl.misub SrcL, SrcR, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x00000000104d000eULL, .field_start = 922, .field_count = 4 },
-  { .id = "hl_mul_48_0d059ff178fb", .mnemonic = "HL.MUL", .asm_fmt = "hl.mul SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000000047000eULL, .field_start = 926, .field_count = 4 },
-  { .id = "hl_mulu_48_85efdc81e8fc", .mnemonic = "HL.MULU", .asm_fmt = "hl.mulu SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000001047000eULL, .field_start = 930, .field_count = 4 },
-  { .id = "hl_ori_48_c6d8ce28a78b", .mnemonic = "HL.ORI", .asm_fmt = "hl.ori SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003015000eULL, .field_start = 934, .field_count = 3 },
-  { .id = "hl_oriw_48_17673d186249", .mnemonic = "HL.ORIW", .asm_fmt = "hl.oriw SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003035000eULL, .field_start = 937, .field_count = 3 },
-  { .id = "hl_prf_48_39641863bb21", .mnemonic = "HL.PRF", .asm_fmt = "hl.prf{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>]", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000007009000eULL, .field_start = 940, .field_count = 5 },
-  { .id = "hl_prf_a_48_267dc57d14f4", .mnemonic = "HL.PRF.A", .asm_fmt = "hl.prf.a{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000007009001eULL, .field_start = 945, .field_count = 6 },
-  { .id = "hl_prfi_u_48_be73891e376e", .mnemonic = "HL.PRFI.U", .asm_fmt = "hl.prfi.u{.l1,.l2,.l3} [SrcL, simm]", .length_bits = 48, .mask = 0x000000007fff003fULL, .match = 0x000000007029000eULL, .field_start = 951, .field_count = 3 },
-  { .id = "hl_prfi_ua_48_c37fb30ecb0f", .mnemonic = "HL.PRFI.UA", .asm_fmt = "hl.prfi.ua{.l1,.l2,.l3} [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007029001eULL, .field_start = 954, .field_count = 4 },
-  { .id = "hl_qmt_48_eb9e41958045", .mnemonic = "HL.QMT", .asm_fmt = "hl.qmt.{i,e,s,r,ie,is,ir,es,er,ies,ier} SrcL, SrcR, ->{t, u}", .length_bits = 48, .mask = 0x0000e000707fffffULL, .match = 0x00000000007d000eULL, .field_start = 958, .field_count = 7 },
-  { .id = "hl_qpop_48_a2c57f5bc27b", .mnemonic = "HL.QPOP", .asm_fmt = "hl.qpop.{e,r,er} SrcL, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000f800707f07ffULL, .match = 0x00000000207d000eULL, .field_start = 965, .field_count = 6 },
-  { .id = "hl_qpush_48_3eab8e05d61a", .mnemonic = "HL.QPUSH", .asm_fmt = "hl.qpush.{h,e,r,he,hr,er,her} SrcL, SrcR, ->{t, u}", .length_bits = 48, .mask = 0x0000f000707fffffULL, .match = 0x00000000107d000eULL, .field_start = 971, .field_count = 6 },
-  { .id = "hl_rem_48_3c13e08615aa", .mnemonic = "HL.REM", .asm_fmt = "hl.rem SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000004057000eULL, .field_start = 977, .field_count = 4 },
-  { .id = "hl_remu_48_3bf4e5a663c1", .mnemonic = "HL.REMU", .asm_fmt = "hl.remu SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000005057000eULL, .field_start = 981, .field_count = 4 },
-  { .id = "hl_remuw_48_26ea6e70f2fc", .mnemonic = "HL.REMUW", .asm_fmt = "hl.remuw SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000007057000eULL, .field_start = 985, .field_count = 4 },
-  { .id = "hl_remw_48_3acb485d39a7", .mnemonic = "HL.REMW", .asm_fmt = "hl.remw SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000006057000eULL, .field_start = 989, .field_count = 4 },
-  { .id = "hl_sb_pcr_48_d0ba4b6e0f54", .mnemonic = "HL.SB.PCR", .asm_fmt = "hl.sb.pcr SrcL, [<symbol>]", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000069000eULL, .field_start = 993, .field_count = 2 },
-  { .id = "hl_sb_po_48_c21837f2c14d", .mnemonic = "HL.SB.PO", .asm_fmt = "hl.sb.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000000049003eULL, .field_start = 995, .field_count = 5 },
-  { .id = "hl_sb_pr_48_40eae4513905", .mnemonic = "HL.SB.PR", .asm_fmt = "hl.sb.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000000049002eULL, .field_start = 1000, .field_count = 5 },
-  { .id = "hl_sbi_48_3504e6935382", .mnemonic = "HL.SBI", .asm_fmt = "hl.sbi SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000059000eULL, .field_start = 1005, .field_count = 3 },
-  { .id = "hl_sbi_po_48_493d9c8b27eb", .mnemonic = "HL.SBI.PO", .asm_fmt = "hl.sbi.po SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000059003eULL, .field_start = 1008, .field_count = 4 },
-  { .id = "hl_sbi_pr_48_d6f48429cca5", .mnemonic = "HL.SBI.PR", .asm_fmt = "hl.sbi.pr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000059002eULL, .field_start = 1012, .field_count = 4 },
-  { .id = "hl_sbip_48_48a212ee655e", .mnemonic = "HL.SBIP", .asm_fmt = "hl.sbip SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000059001eULL, .field_start = 1016, .field_count = 4 },
-  { .id = "hl_sbp_48_12e03c011f0a", .mnemonic = "HL.SBP", .asm_fmt = "hl.sbp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000000049001eULL, .field_start = 1020, .field_count = 5 },
-  { .id = "hl_sd_pcr_48_8ed6bb942a78", .mnemonic = "HL.SD.PCR", .asm_fmt = "hl.sd.pcr SrcL, [<symbol>]", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003069000eULL, .field_start = 1025, .field_count = 2 },
-  { .id = "hl_sd_po_48_9ced722101a8", .mnemonic = "HL.SD.PO", .asm_fmt = "hl.sd.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000003049003eULL, .field_start = 1027, .field_count = 5 },
-  { .id = "hl_sd_pr_48_4f96249f5efe", .mnemonic = "HL.SD.PR", .asm_fmt = "hl.sd.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000003049002eULL, .field_start = 1032, .field_count = 5 },
-  { .id = "hl_sd_upo_48_ba930fbec5c7", .mnemonic = "HL.SD.UPO", .asm_fmt = "hl.sd.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000007049003eULL, .field_start = 1037, .field_count = 5 },
-  { .id = "hl_sd_upr_48_af7118270a90", .mnemonic = "HL.SD.UPR", .asm_fmt = "hl.sd.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000007049002eULL, .field_start = 1042, .field_count = 5 },
-  { .id = "hl_sdi_48_3203094081da", .mnemonic = "HL.SDI", .asm_fmt = "hl.sdi SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003059000eULL, .field_start = 1047, .field_count = 3 },
-  { .id = "hl_sdi_po_48_4b6af4b433bb", .mnemonic = "HL.SDI.PO", .asm_fmt = "hl.sdi.po SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003059003eULL, .field_start = 1050, .field_count = 4 },
-  { .id = "hl_sdi_pr_48_8b2688251991", .mnemonic = "HL.SDI.PR", .asm_fmt = "hl.sdi.pr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003059002eULL, .field_start = 1054, .field_count = 4 },
-  { .id = "hl_sdi_u_48_d9597eeba6b4", .mnemonic = "HL.SDI.U", .asm_fmt = "hl.sdi.u SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007059000eULL, .field_start = 1058, .field_count = 3 },
-  { .id = "hl_sdi_upo_48_0ceed9e5fdb0", .mnemonic = "HL.SDI.UPO", .asm_fmt = "hl.sdi.upo SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007059003eULL, .field_start = 1061, .field_count = 4 },
-  { .id = "hl_sdi_upr_48_f8aba43b65d5", .mnemonic = "HL.SDI.UPR", .asm_fmt = "hl.sdi.upr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007059002eULL, .field_start = 1065, .field_count = 4 },
-  { .id = "hl_sdip_48_6d622cf167ca", .mnemonic = "HL.SDIP", .asm_fmt = "hl.sdip SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003059001eULL, .field_start = 1069, .field_count = 4 },
-  { .id = "hl_sdip_u_48_3260b03bb762", .mnemonic = "HL.SDIP.U", .asm_fmt = "hl.sdip.u SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007059001eULL, .field_start = 1073, .field_count = 4 },
-  { .id = "hl_sdp_48_5884c49a7e55", .mnemonic = "HL.SDP", .asm_fmt = "hl.sdp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<3]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000003049001eULL, .field_start = 1077, .field_count = 5 },
-  { .id = "hl_sdp_u_48_66de58724f2f", .mnemonic = "HL.SDP.U", .asm_fmt = "hl.sdp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000007049001eULL, .field_start = 1082, .field_count = 5 },
-  { .id = "hl_setc_andi_48_f27796612fb3", .mnemonic = "HL.SETC.ANDI", .asm_fmt = "hl.setc.andi SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002075000eULL, .field_start = 1087, .field_count = 3 },
-  { .id = "hl_setc_eqi_48_0fe891fb0890", .mnemonic = "HL.SETC.EQI", .asm_fmt = "hl.setc.eqi SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000075000eULL, .field_start = 1090, .field_count = 3 },
-  { .id = "hl_setc_gei_48_9563d6395d06", .mnemonic = "HL.SETC.GEI", .asm_fmt = "hl.setc.gei SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000005075000eULL, .field_start = 1093, .field_count = 3 },
-  { .id = "hl_setc_geui_48_2390319baf54", .mnemonic = "HL.SETC.GEUI", .asm_fmt = "hl.setc.geui SrcL, uimm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000007075000eULL, .field_start = 1096, .field_count = 3 },
-  { .id = "hl_setc_lti_48_ad4ffebe877c", .mnemonic = "HL.SETC.LTI", .asm_fmt = "hl.setc.lti SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004075000eULL, .field_start = 1099, .field_count = 3 },
-  { .id = "hl_setc_ltui_48_cb7a12ba6ead", .mnemonic = "HL.SETC.LTUI", .asm_fmt = "hl.setc.ltui SrcL, uimm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000006075000eULL, .field_start = 1102, .field_count = 3 },
-  { .id = "hl_setc_nei_48_f0bcf6586274", .mnemonic = "HL.SETC.NEI", .asm_fmt = "hl.setc.nei SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001075000eULL, .field_start = 1105, .field_count = 3 },
-  { .id = "hl_setc_ori_48_137bce8aeb04", .mnemonic = "HL.SETC.ORI", .asm_fmt = "hl.setc.ori SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003075000eULL, .field_start = 1108, .field_count = 3 },
-  { .id = "hl_setret_48_302bb793a800", .mnemonic = "HL.SETRET", .asm_fmt = "hl.setret imm, ->Ra", .length_bits = 48, .mask = 0x000000000fff000fULL, .match = 0x000000000507000eULL, .field_start = 1111, .field_count = 1 },
-  { .id = "hl_sh_pcr_48_705ea4062d0b", .mnemonic = "HL.SH.PCR", .asm_fmt = "hl.sh.pcr SrcL, [<symbol>]", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001069000eULL, .field_start = 1112, .field_count = 2 },
-  { .id = "hl_sh_po_48_e0b543d5b724", .mnemonic = "HL.SH.PO", .asm_fmt = "hl.sh.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000001049003eULL, .field_start = 1114, .field_count = 5 },
-  { .id = "hl_sh_pr_48_40ab17f5a580", .mnemonic = "HL.SH.PR", .asm_fmt = "hl.sh.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000001049002eULL, .field_start = 1119, .field_count = 5 },
-  { .id = "hl_sh_upo_48_5bfb8ea0c992", .mnemonic = "HL.SH.UPO", .asm_fmt = "hl.sh.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000005049003eULL, .field_start = 1124, .field_count = 5 },
-  { .id = "hl_sh_upr_48_719102d66e45", .mnemonic = "HL.SH.UPR", .asm_fmt = "hl.sh.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000005049002eULL, .field_start = 1129, .field_count = 5 },
-  { .id = "hl_shi_48_38ea3f0a4f08", .mnemonic = "HL.SHI", .asm_fmt = "hl.shi SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001059000eULL, .field_start = 1134, .field_count = 3 },
-  { .id = "hl_shi_po_48_636fea832c7b", .mnemonic = "HL.SHI.PO", .asm_fmt = "hl.shi.po SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001059003eULL, .field_start = 1137, .field_count = 4 },
-  { .id = "hl_shi_pr_48_1020eb4dff56", .mnemonic = "HL.SHI.PR", .asm_fmt = "hl.shi.pr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001059002eULL, .field_start = 1141, .field_count = 4 },
-  { .id = "hl_shi_u_48_79dbaa14d2c2", .mnemonic = "HL.SHI.U", .asm_fmt = "hl.shi.u SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005059000eULL, .field_start = 1145, .field_count = 3 },
-  { .id = "hl_shi_upo_48_de81eed370cf", .mnemonic = "HL.SHI.UPO", .asm_fmt = "hl.shi.upo SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005059003eULL, .field_start = 1148, .field_count = 4 },
-  { .id = "hl_shi_upr_48_ca9f1acbb1b2", .mnemonic = "HL.SHI.UPR", .asm_fmt = "hl.shi.upr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005059002eULL, .field_start = 1152, .field_count = 4 },
-  { .id = "hl_ship_48_156afe74f95b", .mnemonic = "HL.SHIP", .asm_fmt = "hl.ship SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001059001eULL, .field_start = 1156, .field_count = 4 },
-  { .id = "hl_ship_u_48_fa5e1d981a8a", .mnemonic = "HL.SHIP.U", .asm_fmt = "hl.ship.u SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005059001eULL, .field_start = 1160, .field_count = 4 },
-  { .id = "hl_shp_48_ccc507e71a27", .mnemonic = "HL.SHP", .asm_fmt = "hl.shp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<1]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000001049001eULL, .field_start = 1164, .field_count = 5 },
-  { .id = "hl_shp_u_48_232b2200b7b9", .mnemonic = "HL.SHP.U", .asm_fmt = "hl.shp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000005049001eULL, .field_start = 1169, .field_count = 5 },
-  { .id = "hl_ssrget_48_fde37e58a3c4", .mnemonic = "HL.SSRGET", .asm_fmt = "hl.ssrget SSR_ID, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000000ff07f000fULL, .match = 0x00000000003b000eULL, .field_start = 1174, .field_count = 2 },
-  { .id = "hl_ssrset_48_dd25753307c2", .mnemonic = "HL.SSRSET", .asm_fmt = "hl.ssrset SrcL, SSR_ID", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x00000000103b000eULL, .field_start = 1176, .field_count = 2 },
-  { .id = "hl_subi_48_e1f491a8aead", .mnemonic = "HL.SUBI", .asm_fmt = "hl.subi SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001015000eULL, .field_start = 1178, .field_count = 3 },
-  { .id = "hl_subiw_48_adc7b127a2f8", .mnemonic = "HL.SUBIW", .asm_fmt = "hl.subiw SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001035000eULL, .field_start = 1181, .field_count = 3 },
-  { .id = "hl_sw_pcr_48_8f8900dfac6b", .mnemonic = "HL.SW.PCR", .asm_fmt = "hl.sw.pcr SrcL, [<symbol>]", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002069000eULL, .field_start = 1184, .field_count = 2 },
-  { .id = "hl_sw_po_48_84cf0cd97fde", .mnemonic = "HL.SW.PO", .asm_fmt = "hl.sw.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000002049003eULL, .field_start = 1186, .field_count = 5 },
-  { .id = "hl_sw_pr_48_d80424b0a9cb", .mnemonic = "HL.SW.PR", .asm_fmt = "hl.sw.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000002049002eULL, .field_start = 1191, .field_count = 5 },
-  { .id = "hl_sw_upo_48_59be7b468f8a", .mnemonic = "HL.SW.UPO", .asm_fmt = "hl.sw.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000006049003eULL, .field_start = 1196, .field_count = 5 },
-  { .id = "hl_sw_upr_48_d4ccb513944a", .mnemonic = "HL.SW.UPR", .asm_fmt = "hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000006049002eULL, .field_start = 1201, .field_count = 5 },
-  { .id = "hl_swi_48_13deb2849df5", .mnemonic = "HL.SWI", .asm_fmt = "hl.swi SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002059000eULL, .field_start = 1206, .field_count = 3 },
-  { .id = "hl_swi_po_48_66a80d0fa7f5", .mnemonic = "HL.SWI.PO", .asm_fmt = "hl.swi.po SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002059003eULL, .field_start = 1209, .field_count = 4 },
-  { .id = "hl_swi_pr_48_68b9003e0421", .mnemonic = "HL.SWI.PR", .asm_fmt = "hl.swi.pr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002059002eULL, .field_start = 1213, .field_count = 4 },
-  { .id = "hl_swi_u_48_fac636330fd6", .mnemonic = "HL.SWI.U", .asm_fmt = "hl.swi.u SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006059000eULL, .field_start = 1217, .field_count = 3 },
-  { .id = "hl_swi_upo_48_243d3c38cd1a", .mnemonic = "HL.SWI.UPO", .asm_fmt = "hl.swi.upo SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006059003eULL, .field_start = 1220, .field_count = 4 },
-  { .id = "hl_swi_upr_48_15c2fb96aab0", .mnemonic = "HL.SWI.UPR", .asm_fmt = "hl.swi.upr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006059002eULL, .field_start = 1224, .field_count = 4 },
-  { .id = "hl_swip_48_e2fca8cde001", .mnemonic = "HL.SWIP", .asm_fmt = "hl.swip SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002059001eULL, .field_start = 1228, .field_count = 4 },
-  { .id = "hl_swip_u_48_e2dc917c8505", .mnemonic = "HL.SWIP.U", .asm_fmt = "hl.swip.u SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006059001eULL, .field_start = 1232, .field_count = 4 },
-  { .id = "hl_swp_48_d0efe96e09f0", .mnemonic = "HL.SWP", .asm_fmt = "hl.swp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<2]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000002049001eULL, .field_start = 1236, .field_count = 5 },
-  { .id = "hl_swp_u_48_c244a576be8e", .mnemonic = "HL.SWP.U", .asm_fmt = "hl.swp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000006049001eULL, .field_start = 1241, .field_count = 5 },
-  { .id = "hl_xori_48_b4d85f91aad8", .mnemonic = "HL.XORI", .asm_fmt = "hl.xori SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004015000eULL, .field_start = 1246, .field_count = 3 },
-  { .id = "hl_xoriw_48_9a3edbd09746", .mnemonic = "HL.XORIW", .asm_fmt = "hl.xoriw SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004035000eULL, .field_start = 1249, .field_count = 3 },
-  { .id = "ic_iall_32_854f0d4d906a", .mnemonic = "IC.IALL", .asm_fmt = "ic.iall", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x000000000010502bULL, .field_start = 1252, .field_count = 0 },
-  { .id = "ic_iva_32_11b9a61dd8b5", .mnemonic = "IC.IVA", .asm_fmt = "ic.iva SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000000502bULL, .field_start = 1252, .field_count = 1 },
-  { .id = "j_32_a303cf05af42", .mnemonic = "J", .asm_fmt = "j label", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000037ULL, .field_start = 1253, .field_count = 1 },
-  { .id = "jr_32_c4128e843b05", .mnemonic = "JR", .asm_fmt = "jr SrcL, label", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006027ULL, .field_start = 1254, .field_count = 3 },
-  { .id = "l_bstart_fp_64_098e57019d7b", .mnemonic = "L.BSTART.FP", .asm_fmt = "L.BSTART.FP COND, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000030810000000fULL, .field_start = 1257, .field_count = 1 },
-  { .id = "l_bstart_fp_64_0cac9941f7d4", .mnemonic = "L.BSTART.FP", .asm_fmt = "L.BSTART.FP DIRECT, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000020810000000fULL, .field_start = 1258, .field_count = 1 },
-  { .id = "l_bstart_fp_64_2067ad6667ed", .mnemonic = "L.BSTART.FP", .asm_fmt = "L.BSTART.FP CALL, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000040810000000fULL, .field_start = 1259, .field_count = 1 },
-  { .id = "l_bstart_fp_64_8115c042ef26", .mnemonic = "L.BSTART.FP", .asm_fmt = "L.BSTART.FP FALL<, fixup_label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000010810000000fULL, .field_start = 1260, .field_count = 1 },
-  { .id = "l_bstart_std_64_37e84068ce61", .mnemonic = "L.BSTART.STD", .asm_fmt = "L.BSTART.STD DIRECT, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000020010000000fULL, .field_start = 1261, .field_count = 1 },
-  { .id = "l_bstart_std_64_463a1567da91", .mnemonic = "L.BSTART.STD", .asm_fmt = "L.BSTART.STD CALL, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000040010000000fULL, .field_start = 1262, .field_count = 1 },
-  { .id = "l_bstart_std_64_72d502fcd30d", .mnemonic = "L.BSTART.STD", .asm_fmt = "L.BSTART.STD COND, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000030010000000fULL, .field_start = 1263, .field_count = 1 },
-  { .id = "l_bstart_std_64_899592f9c5bc", .mnemonic = "L.BSTART.STD", .asm_fmt = "L.BSTART.STD FALL<, fixup_label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000010010000000fULL, .field_start = 1264, .field_count = 1 },
-  { .id = "l_bstart_sys_64_919e576c79e4", .mnemonic = "L.BSTART.SYS", .asm_fmt = "L.BSTART.SYS FALL<, fixup_label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000010110000000fULL, .field_start = 1265, .field_count = 1 },
-  { .id = "lb_32_b718aa88e28f", .mnemonic = "LB", .asm_fmt = "lb [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000009ULL, .field_start = 1266, .field_count = 5 },
-  { .id = "lb_pcr_32_3fa2540b22d0", .mnemonic = "LB.PCR", .asm_fmt = "lb.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000039ULL, .field_start = 1271, .field_count = 2 },
-  { .id = "lbi_32_9af2cdbeb38f", .mnemonic = "LBI", .asm_fmt = "lbi [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000019ULL, .field_start = 1273, .field_count = 3 },
-  { .id = "lbu_32_a9a58ab4ea22", .mnemonic = "LBU", .asm_fmt = "lbu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004009ULL, .field_start = 1276, .field_count = 5 },
-  { .id = "lbu_pcr_32_5b571b0c8dc2", .mnemonic = "LBU.PCR", .asm_fmt = "lbu.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004039ULL, .field_start = 1281, .field_count = 2 },
-  { .id = "lbui_32_c39b9aa11f02", .mnemonic = "LBUI", .asm_fmt = "lbui [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004019ULL, .field_start = 1283, .field_count = 3 },
-  { .id = "ld_32_7c48838bc4e6", .mnemonic = "LD", .asm_fmt = "ld [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003009ULL, .field_start = 1286, .field_count = 5 },
-  { .id = "ld_add_32_a4038a6c7e86", .mnemonic = "LD.ADD", .asm_fmt = "ld.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000400bULL, .field_start = 1291, .field_count = 6 },
-  { .id = "ld_and_32_2a46b3003480", .mnemonic = "LD.AND", .asm_fmt = "ld.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000400bULL, .field_start = 1297, .field_count = 6 },
-  { .id = "ld_or_32_456d270cfc7d", .mnemonic = "LD.OR", .asm_fmt = "ld.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000400bULL, .field_start = 1303, .field_count = 6 },
-  { .id = "ld_pcr_32_99bc3d2d487b", .mnemonic = "LD.PCR", .asm_fmt = "ld.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003039ULL, .field_start = 1309, .field_count = 2 },
-  { .id = "ld_smax_32_a3aad6120226", .mnemonic = "LD.SMAX", .asm_fmt = "ld.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000004000400bULL, .field_start = 1311, .field_count = 6 },
-  { .id = "ld_smin_32_9461d345718f", .mnemonic = "LD.SMIN", .asm_fmt = "ld.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000005000400bULL, .field_start = 1317, .field_count = 6 },
-  { .id = "ld_umax_32_a84af75745d9", .mnemonic = "LD.UMAX", .asm_fmt = "ld.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000006000400bULL, .field_start = 1323, .field_count = 6 },
-  { .id = "ld_umin_32_4bf2f357eff3", .mnemonic = "LD.UMIN", .asm_fmt = "ld.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000007000400bULL, .field_start = 1329, .field_count = 6 },
-  { .id = "ld_xor_32_33072c0fde61", .mnemonic = "LD.XOR", .asm_fmt = "ld.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000400bULL, .field_start = 1335, .field_count = 6 },
-  { .id = "ldi_32_d82a643f7a2b", .mnemonic = "LDI", .asm_fmt = "ldi [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003019ULL, .field_start = 1341, .field_count = 3 },
-  { .id = "ldi_u_32_111bb521a439", .mnemonic = "LDI.U", .asm_fmt = "ldi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003029ULL, .field_start = 1344, .field_count = 3 },
-  { .id = "lh_32_d0f04d7d7696", .mnemonic = "LH", .asm_fmt = "lh [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001009ULL, .field_start = 1347, .field_count = 5 },
-  { .id = "lh_pcr_32_aabf46d21e49", .mnemonic = "LH.PCR", .asm_fmt = "lh.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001039ULL, .field_start = 1352, .field_count = 2 },
-  { .id = "lhi_32_46a45ec7074d", .mnemonic = "LHI", .asm_fmt = "lhi [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001019ULL, .field_start = 1354, .field_count = 3 },
-  { .id = "lhi_u_32_bb0c81c6e61d", .mnemonic = "LHI.U", .asm_fmt = "lhi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001029ULL, .field_start = 1357, .field_count = 3 },
-  { .id = "lhu_32_730caf67ecd1", .mnemonic = "LHU", .asm_fmt = "lhu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005009ULL, .field_start = 1360, .field_count = 5 },
-  { .id = "lhu_pcr_32_9f4a1c04f258", .mnemonic = "LHU.PCR", .asm_fmt = "lhu.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005039ULL, .field_start = 1365, .field_count = 2 },
-  { .id = "lhui_32_6da39bba900b", .mnemonic = "LHUI", .asm_fmt = "lhui [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005019ULL, .field_start = 1367, .field_count = 3 },
-  { .id = "lhui_u_32_748b15cd2ced", .mnemonic = "LHUI.U", .asm_fmt = "lhui.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005029ULL, .field_start = 1370, .field_count = 3 },
-  { .id = "lr_b_32_cf80903a761a", .mnemonic = "LR.B", .asm_fmt = "lr.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000000bULL, .field_start = 1373, .field_count = 6 },
-  { .id = "lr_d_32_84d21a553dc1", .mnemonic = "LR.D", .asm_fmt = "lr.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000000bULL, .field_start = 1379, .field_count = 6 },
-  { .id = "lr_h_32_f936df218d63", .mnemonic = "LR.H", .asm_fmt = "lr.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000000bULL, .field_start = 1385, .field_count = 6 },
-  { .id = "lr_w_32_efecc735bb75", .mnemonic = "LR.W", .asm_fmt = "lr.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000000bULL, .field_start = 1391, .field_count = 6 },
-  { .id = "lsrget_32_448b17d7c20a", .mnemonic = "LSRGET", .asm_fmt = "lsrget LSR_ID, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000000ff07fULL, .match = 0x000000000000303bULL, .field_start = 1397, .field_count = 2 },
-  { .id = "lui_32_982113b541d6", .mnemonic = "LUI", .asm_fmt = "lui simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000007fULL, .match = 0x0000000000000017ULL, .field_start = 1399, .field_count = 2 },
-  { .id = "lw_32_3a77ffafcb34", .mnemonic = "LW", .asm_fmt = "lw [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002009ULL, .field_start = 1401, .field_count = 5 },
-  { .id = "lw_add_32_5be3ad1ad081", .mnemonic = "LW.ADD", .asm_fmt = "lw.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000200bULL, .field_start = 1406, .field_count = 6 },
-  { .id = "lw_and_32_f8dd9866b069", .mnemonic = "LW.AND", .asm_fmt = "lw.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000200bULL, .field_start = 1412, .field_count = 6 },
-  { .id = "lw_or_32_d6d2f87706fd", .mnemonic = "LW.OR", .asm_fmt = "lw.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000200bULL, .field_start = 1418, .field_count = 6 },
-  { .id = "lw_pcr_32_d135a1aa4ffb", .mnemonic = "LW.PCR", .asm_fmt = "lw.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002039ULL, .field_start = 1424, .field_count = 2 },
-  { .id = "lw_smax_32_838b8c673c91", .mnemonic = "LW.SMAX", .asm_fmt = "lw.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000004000200bULL, .field_start = 1426, .field_count = 6 },
-  { .id = "lw_smin_32_44452ae44d02", .mnemonic = "LW.SMIN", .asm_fmt = "lw.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000005000200bULL, .field_start = 1432, .field_count = 6 },
-  { .id = "lw_umax_32_3c6a5a534674", .mnemonic = "LW.UMAX", .asm_fmt = "lw.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000006000200bULL, .field_start = 1438, .field_count = 6 },
-  { .id = "lw_umin_32_fd9b7bb538a3", .mnemonic = "LW.UMIN", .asm_fmt = "lw.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000007000200bULL, .field_start = 1444, .field_count = 6 },
-  { .id = "lw_xor_32_4d4aa82c676a", .mnemonic = "LW.XOR", .asm_fmt = "lw.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000200bULL, .field_start = 1450, .field_count = 6 },
-  { .id = "lwi_32_7085c98058fa", .mnemonic = "LWI", .asm_fmt = "lwi [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002019ULL, .field_start = 1456, .field_count = 3 },
-  { .id = "lwi_u_32_4a7426a70f10", .mnemonic = "LWI.U", .asm_fmt = "lwi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002029ULL, .field_start = 1459, .field_count = 3 },
-  { .id = "lwu_32_678935925636", .mnemonic = "LWU", .asm_fmt = "lwu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006009ULL, .field_start = 1462, .field_count = 5 },
-  { .id = "lwu_pcr_32_df27ea51c564", .mnemonic = "LWU.PCR", .asm_fmt = "lwu.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006039ULL, .field_start = 1467, .field_count = 2 },
-  { .id = "lwui_32_b435f946eb71", .mnemonic = "LWUI", .asm_fmt = "lwui [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006019ULL, .field_start = 1469, .field_count = 3 },
-  { .id = "lwui_u_32_1fcbb98df571", .mnemonic = "LWUI.U", .asm_fmt = "lwui.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006029ULL, .field_start = 1472, .field_count = 3 },
-  { .id = "madd_32_6208e8e59303", .mnemonic = "MADD", .asm_fmt = "madd SrcL, SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000600707fULL, .match = 0x0000000000006047ULL, .field_start = 1475, .field_count = 4 },
-  { .id = "maddw_32_9f922b15e674", .mnemonic = "MADDW", .asm_fmt = "maddw SrcL, SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000600707fULL, .match = 0x0000000000007047ULL, .field_start = 1479, .field_count = 4 },
-  { .id = "max_32_9166468a1db7", .mnemonic = "MAX", .asm_fmt = "max SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x000000000000405bULL, .field_start = 1483, .field_count = 3 },
-  { .id = "maxu_32_b8789571339d", .mnemonic = "MAXU", .asm_fmt = "maxu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x000000000800405bULL, .field_start = 1486, .field_count = 3 },
-  { .id = "mcopy_32_4fc4a803e995", .mnemonic = "MCOPY", .asm_fmt = "MCOPY [RegSrc0, RegSrc1, RegSrc2]", .length_bits = 32, .mask = 0x0000000006007fffULL, .match = 0x0000000000000031ULL, .field_start = 1489, .field_count = 3 },
-  { .id = "min_32_25692b799267", .mnemonic = "MIN", .asm_fmt = "min SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x000000000000505bULL, .field_start = 1492, .field_count = 3 },
-  { .id = "minu_32_9bdb71ef7b19", .mnemonic = "MINU", .asm_fmt = "minu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x000000000800505bULL, .field_start = 1495, .field_count = 3 },
-  { .id = "mset_32_0b932f291932", .mnemonic = "MSET", .asm_fmt = "MSET [RegSrc0, RegSrc1, RegSrc2]", .length_bits = 32, .mask = 0x0000000006007fffULL, .match = 0x0000000000001031ULL, .field_start = 1498, .field_count = 3 },
-  { .id = "mul_32_9f2affd8efb8", .mnemonic = "MUL", .asm_fmt = "mul SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000000047ULL, .field_start = 1501, .field_count = 3 },
-  { .id = "mulu_32_10b9d1936631", .mnemonic = "MULU", .asm_fmt = "mulu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000001047ULL, .field_start = 1504, .field_count = 3 },
-  { .id = "muluw_32_8f52b3d45e53", .mnemonic = "MULUW", .asm_fmt = "muluw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000003047ULL, .field_start = 1507, .field_count = 3 },
-  { .id = "mulw_32_b90cb6a30a23", .mnemonic = "MULW", .asm_fmt = "mulw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000002047ULL, .field_start = 1510, .field_count = 3 },
-  { .id = "or_32_a7fb80e78831", .mnemonic = "OR", .asm_fmt = "or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003005ULL, .field_start = 1513, .field_count = 5 },
-  { .id = "ori_32_413a6cc76e9a", .mnemonic = "ORI", .asm_fmt = "ori SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003015ULL, .field_start = 1518, .field_count = 3 },
-  { .id = "oriw_32_91608caf1ba6", .mnemonic = "ORIW", .asm_fmt = "oriw SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003035ULL, .field_start = 1521, .field_count = 3 },
-  { .id = "orw_32_84f7ac2ed68f", .mnemonic = "ORW", .asm_fmt = "orw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003025ULL, .field_start = 1524, .field_count = 5 },
-  { .id = "prf_32_30e6dfe4e3ce", .mnemonic = "PRF", .asm_fmt = "prf [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007009ULL, .field_start = 1529, .field_count = 5 },
-  { .id = "prfi_u_32_167b42882547", .mnemonic = "PRFI.U", .asm_fmt = "prfi.u [SrcL, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007029ULL, .field_start = 1534, .field_count = 3 },
-  { .id = "rem_32_0abbd6a3b865", .mnemonic = "REM", .asm_fmt = "rem SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000004057ULL, .field_start = 1537, .field_count = 3 },
-  { .id = "remu_32_d7a5d1ebbbf5", .mnemonic = "REMU", .asm_fmt = "remu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000005057ULL, .field_start = 1540, .field_count = 3 },
-  { .id = "remuw_32_f10ade2f5ccb", .mnemonic = "REMUW", .asm_fmt = "remuw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000007057ULL, .field_start = 1543, .field_count = 3 },
-  { .id = "remw_32_22659af46ec0", .mnemonic = "REMW", .asm_fmt = "remw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000006057ULL, .field_start = 1546, .field_count = 3 },
-  { .id = "rev_32_58badc109d49", .mnemonic = "REV", .asm_fmt = "rev SrcL,  M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007067ULL, .field_start = 1549, .field_count = 4 },
-  { .id = "sb_32_43c106ae3749", .mnemonic = "SB", .asm_fmt = "sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000000049ULL, .field_start = 1553, .field_count = 4 },
-  { .id = "sb_pcr_32_7625a9a24c59", .mnemonic = "SB.PCR", .asm_fmt = "sb.pcr SrcL, [symbol]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000069ULL, .field_start = 1557, .field_count = 2 },
-  { .id = "sbi_32_f3c6b796f0d9", .mnemonic = "SBI", .asm_fmt = "sbi SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000059ULL, .field_start = 1559, .field_count = 3 },
-  { .id = "sc_b_32_baf609e1d5c3", .mnemonic = "SC.B", .asm_fmt = "sc.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000100bULL, .field_start = 1562, .field_count = 6 },
-  { .id = "sc_d_32_2e714149031c", .mnemonic = "SC.D", .asm_fmt = "sc.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000100bULL, .field_start = 1568, .field_count = 6 },
-  { .id = "sc_h_32_108941eabac6", .mnemonic = "SC.H", .asm_fmt = "sc.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000100bULL, .field_start = 1574, .field_count = 6 },
-  { .id = "sc_w_32_14b238f02bfd", .mnemonic = "SC.W", .asm_fmt = "sc.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000100bULL, .field_start = 1580, .field_count = 6 },
-  { .id = "scvtf_32_01861bbd5ef2", .mnemonic = "SCVTF", .asm_fmt = "scvtf.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000606bULL, .field_start = 1586, .field_count = 4 },
-  { .id = "sd_32_9dbc40328653", .mnemonic = "SD", .asm_fmt = "sd SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000003049ULL, .field_start = 1590, .field_count = 4 },
-  { .id = "sd_add_32_2a55ae1228bd", .mnemonic = "SD.ADD", .asm_fmt = "sd.add<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000000000500bULL, .field_start = 1594, .field_count = 4 },
-  { .id = "sd_and_32_71963e1769c2", .mnemonic = "SD.AND", .asm_fmt = "sd.and<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000001000500bULL, .field_start = 1598, .field_count = 4 },
-  { .id = "sd_or_32_2a65eedfae0f", .mnemonic = "SD.OR", .asm_fmt = "sd.or<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000002000500bULL, .field_start = 1602, .field_count = 4 },
-  { .id = "sd_pcr_32_2340e0085413", .mnemonic = "SD.PCR", .asm_fmt = "sd.pcr SrcL, [symbol]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003069ULL, .field_start = 1606, .field_count = 2 },
-  { .id = "sd_smax_32_e59bf90b50c3", .mnemonic = "SD.SMAX", .asm_fmt = "sd.smax<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000004000500bULL, .field_start = 1608, .field_count = 4 },
-  { .id = "sd_smin_32_188d93125032", .mnemonic = "SD.SMIN", .asm_fmt = "sd.smin<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000005000500bULL, .field_start = 1612, .field_count = 4 },
-  { .id = "sd_u_32_1602c58c2031", .mnemonic = "SD.U", .asm_fmt = "sd.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000007049ULL, .field_start = 1616, .field_count = 4 },
-  { .id = "sd_umax_32_89c5ec42be68", .mnemonic = "SD.UMAX", .asm_fmt = "sd.umax<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000006000500bULL, .field_start = 1620, .field_count = 4 },
-  { .id = "sd_umin_32_2388cbb378ac", .mnemonic = "SD.UMIN", .asm_fmt = "sd.umin<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000007000500bULL, .field_start = 1624, .field_count = 4 },
-  { .id = "sd_xor_32_7655ceaf9497", .mnemonic = "SD.XOR", .asm_fmt = "sd.xor<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000003000500bULL, .field_start = 1628, .field_count = 4 },
-  { .id = "sdi_32_fab563230a66", .mnemonic = "SDI", .asm_fmt = "sdi SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003059ULL, .field_start = 1632, .field_count = 3 },
-  { .id = "sdi_u_32_cba5a4a04e7b", .mnemonic = "SDI.U", .asm_fmt = "sdi.u SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007059ULL, .field_start = 1635, .field_count = 3 },
-  { .id = "setc_and_32_90b4e93ef9d4", .mnemonic = "SETC.AND", .asm_fmt = "setc.and SrcL, SrcR<.sw, .uw, .not>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000002065ULL, .field_start = 1638, .field_count = 3 },
-  { .id = "setc_andi_32_32fe61c0559b", .mnemonic = "SETC.ANDI", .asm_fmt = "setc.andi SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002075ULL, .field_start = 1641, .field_count = 3 },
-  { .id = "setc_eq_32_fb06e1dddc5c", .mnemonic = "SETC.EQ", .asm_fmt = "setc.eq SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000000065ULL, .field_start = 1644, .field_count = 3 },
-  { .id = "setc_eqi_32_5b2366a4e55d", .mnemonic = "SETC.EQI", .asm_fmt = "setc.eqi SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000075ULL, .field_start = 1647, .field_count = 3 },
-  { .id = "setc_ge_32_56a2b539b072", .mnemonic = "SETC.GE", .asm_fmt = "setc.ge SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000005065ULL, .field_start = 1650, .field_count = 3 },
-  { .id = "setc_gei_32_c3f4fdc4adcc", .mnemonic = "SETC.GEI", .asm_fmt = "setc.gei SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005075ULL, .field_start = 1653, .field_count = 3 },
-  { .id = "setc_geu_32_494f1f79099e", .mnemonic = "SETC.GEU", .asm_fmt = "setc.geu SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000007065ULL, .field_start = 1656, .field_count = 3 },
-  { .id = "setc_geui_32_6c34bc4ad314", .mnemonic = "SETC.GEUI", .asm_fmt = "setc.geui SrcL, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007075ULL, .field_start = 1659, .field_count = 3 },
-  { .id = "setc_lt_32_10de99f3ad6a", .mnemonic = "SETC.LT", .asm_fmt = "setc.lt SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000004065ULL, .field_start = 1662, .field_count = 3 },
-  { .id = "setc_lti_32_89d74d948b74", .mnemonic = "SETC.LTI", .asm_fmt = "setc.lti SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004075ULL, .field_start = 1665, .field_count = 3 },
-  { .id = "setc_ltu_32_4a1ff65ecafb", .mnemonic = "SETC.LTU", .asm_fmt = "setc.ltu SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000006065ULL, .field_start = 1668, .field_count = 3 },
-  { .id = "setc_ltui_32_7908d25901c6", .mnemonic = "SETC.LTUI", .asm_fmt = "setc.ltui SrcL, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006075ULL, .field_start = 1671, .field_count = 3 },
-  { .id = "setc_ne_32_77576a5c690c", .mnemonic = "SETC.NE", .asm_fmt = "setc.ne SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000001065ULL, .field_start = 1674, .field_count = 3 },
-  { .id = "setc_nei_32_fa01e973ab76", .mnemonic = "SETC.NEI", .asm_fmt = "setc.nei SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001075ULL, .field_start = 1677, .field_count = 3 },
-  { .id = "setc_or_32_740134c709d2", .mnemonic = "SETC.OR", .asm_fmt = "setc.or SrcL, SrcR<.sw, .uw, .not>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000003065ULL, .field_start = 1680, .field_count = 3 },
-  { .id = "setc_ori_32_183dc15fad54", .mnemonic = "SETC.ORI", .asm_fmt = "setc.ori SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003075ULL, .field_start = 1683, .field_count = 3 },
-  { .id = "setc_tgt_32_c02656d3a2b8", .mnemonic = "SETC.TGT", .asm_fmt = "setc.tgt SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000000403bULL, .field_start = 1686, .field_count = 1 },
-  { .id = "setret_32_72003dcf3b59", .mnemonic = "SETRET", .asm_fmt = "setret uimm, ->Ra", .length_bits = 32, .mask = 0x0000000000000fffULL, .match = 0x0000000000000507ULL, .field_start = 1687, .field_count = 1 },
-  { .id = "sh_32_bc7d4a7dea28", .mnemonic = "SH", .asm_fmt = "sh SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000001049ULL, .field_start = 1688, .field_count = 4 },
-  { .id = "sh_pcr_32_14ba505eb3c2", .mnemonic = "SH.PCR", .asm_fmt = "sh.pcr SrcL, [symbol]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001069ULL, .field_start = 1692, .field_count = 2 },
-  { .id = "sh_u_32_fa87afbf8f24", .mnemonic = "SH.U", .asm_fmt = "sh.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000005049ULL, .field_start = 1694, .field_count = 4 },
-  { .id = "shi_32_21351c202204", .mnemonic = "SHI", .asm_fmt = "shi SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001059ULL, .field_start = 1698, .field_count = 3 },
-  { .id = "shi_u_32_caaf3ed72a8f", .mnemonic = "SHI.U", .asm_fmt = "shi.u SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005059ULL, .field_start = 1701, .field_count = 3 },
-  { .id = "sll_32_a100b8961e21", .mnemonic = "SLL", .asm_fmt = "sll SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000007005ULL, .field_start = 1704, .field_count = 3 },
-  { .id = "slli_32_b43ca2454e3a", .mnemonic = "SLLI", .asm_fmt = "slli SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fc00707fULL, .match = 0x0000000000007015ULL, .field_start = 1707, .field_count = 3 },
-  { .id = "slliw_32_c6bf463b97ae", .mnemonic = "SLLIW", .asm_fmt = "slliw SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000007035ULL, .field_start = 1710, .field_count = 3 },
-  { .id = "sllw_32_a37b63c16b27", .mnemonic = "SLLW", .asm_fmt = "sllw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000007025ULL, .field_start = 1713, .field_count = 3 },
-  { .id = "sra_32_ba03eea6386b", .mnemonic = "SRA", .asm_fmt = "sra SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000006005ULL, .field_start = 1716, .field_count = 3 },
-  { .id = "srai_32_e471ea84d4fd", .mnemonic = "SRAI", .asm_fmt = "srai SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fc00707fULL, .match = 0x0000000000006015ULL, .field_start = 1719, .field_count = 3 },
-  { .id = "sraiw_32_db04a6299504", .mnemonic = "SRAIW", .asm_fmt = "sraiw SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000006035ULL, .field_start = 1722, .field_count = 3 },
-  { .id = "sraw_32_5baf37f34241", .mnemonic = "SRAW", .asm_fmt = "sraw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000006025ULL, .field_start = 1725, .field_count = 3 },
-  { .id = "srl_32_5cfca42c59f3", .mnemonic = "SRL", .asm_fmt = "srl SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000005005ULL, .field_start = 1728, .field_count = 3 },
-  { .id = "srli_32_dd29ca058cfe", .mnemonic = "SRLI", .asm_fmt = "srli SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fc00707fULL, .match = 0x0000000000005015ULL, .field_start = 1731, .field_count = 3 },
-  { .id = "srliw_32_ef4aa650f46e", .mnemonic = "SRLIW", .asm_fmt = "srliw SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000005035ULL, .field_start = 1734, .field_count = 3 },
-  { .id = "srlw_32_2c6458b2aadb", .mnemonic = "SRLW", .asm_fmt = "srlw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000005025ULL, .field_start = 1737, .field_count = 3 },
-  { .id = "ssrget_32_959957ab6b75", .mnemonic = "SSRGET", .asm_fmt = "ssrget SSR_ID, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000000ff07fULL, .match = 0x000000000000003bULL, .field_start = 1740, .field_count = 2 },
-  { .id = "ssrset_32_4dd3b71802c6", .mnemonic = "SSRSET", .asm_fmt = "ssrset SrcL, SSR_ID", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x000000000000103bULL, .field_start = 1742, .field_count = 2 },
-  { .id = "ssrswap_32_a01c7e2c7c29", .mnemonic = "SSRSWAP", .asm_fmt = "ssrswap SrcL, SSR_ID, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000203bULL, .field_start = 1744, .field_count = 3 },
-  { .id = "sub_32_af383d4a2b42", .mnemonic = "SUB", .asm_fmt = "sub SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001005ULL, .field_start = 1747, .field_count = 5 },
-  { .id = "subi_32_a0c87f5e7ac4", .mnemonic = "SUBI", .asm_fmt = "subi SrcL, uimm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001015ULL, .field_start = 1752, .field_count = 3 },
-  { .id = "subiw_32_51019ff77d0a", .mnemonic = "SUBIW", .asm_fmt = "subiw SrcL, uimm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001035ULL, .field_start = 1755, .field_count = 3 },
-  { .id = "subw_32_3a8d45653c98", .mnemonic = "SUBW", .asm_fmt = "subw SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001025ULL, .field_start = 1758, .field_count = 5 },
-  { .id = "sw_32_28ad317b1b41", .mnemonic = "SW", .asm_fmt = "sw SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000002049ULL, .field_start = 1763, .field_count = 4 },
-  { .id = "sw_add_32_3dca755552cb", .mnemonic = "SW.ADD", .asm_fmt = "sw.add<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000000000300bULL, .field_start = 1767, .field_count = 4 },
-  { .id = "sw_and_32_7ef0872d5502", .mnemonic = "SW.AND", .asm_fmt = "sw.and<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000001000300bULL, .field_start = 1771, .field_count = 4 },
-  { .id = "sw_or_32_354579538c4e", .mnemonic = "SW.OR", .asm_fmt = "sw.or<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000002000300bULL, .field_start = 1775, .field_count = 4 },
-  { .id = "sw_pcr_32_436677679523", .mnemonic = "SW.PCR", .asm_fmt = "sw.pcr SrcL, [symbol]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002069ULL, .field_start = 1779, .field_count = 2 },
-  { .id = "sw_smax_32_8bab38a878d7", .mnemonic = "SW.SMAX", .asm_fmt = "sw.smax<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000004000300bULL, .field_start = 1781, .field_count = 4 },
-  { .id = "sw_smin_32_773e7d83b011", .mnemonic = "SW.SMIN", .asm_fmt = "sw.smin<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000005000300bULL, .field_start = 1785, .field_count = 4 },
-  { .id = "sw_u_32_718a61f75d33", .mnemonic = "SW.U", .asm_fmt = "sw.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000006049ULL, .field_start = 1789, .field_count = 4 },
-  { .id = "sw_umax_32_5530dfa23323", .mnemonic = "SW.UMAX", .asm_fmt = "sw.umax<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000006000300bULL, .field_start = 1793, .field_count = 4 },
-  { .id = "sw_umin_32_3ce114819cfc", .mnemonic = "SW.UMIN", .asm_fmt = "sw.umin<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000007000300bULL, .field_start = 1797, .field_count = 4 },
-  { .id = "sw_xor_32_874c32572226", .mnemonic = "SW.XOR", .asm_fmt = "sw.xor<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000003000300bULL, .field_start = 1801, .field_count = 4 },
-  { .id = "swapb_32_80733f03b77f", .mnemonic = "SWAPB", .asm_fmt = "swapb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000600bULL, .field_start = 1805, .field_count = 6 },
-  { .id = "swapd_32_cd31ccde2303", .mnemonic = "SWAPD", .asm_fmt = "swapd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000600bULL, .field_start = 1811, .field_count = 6 },
-  { .id = "swaph_32_8c2d4a28bf25", .mnemonic = "SWAPH", .asm_fmt = "swaph<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000600bULL, .field_start = 1817, .field_count = 6 },
-  { .id = "swapw_32_ef15c3ebac33", .mnemonic = "SWAPW", .asm_fmt = "swapw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000600bULL, .field_start = 1823, .field_count = 6 },
-  { .id = "swi_32_147e55489c41", .mnemonic = "SWI", .asm_fmt = "swi SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002059ULL, .field_start = 1829, .field_count = 3 },
-  { .id = "swi_u_32_1630e926da1a", .mnemonic = "SWI.U", .asm_fmt = "swi.u SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006059ULL, .field_start = 1832, .field_count = 3 },
-  { .id = "tlb_ia_32_e794d6bf347e", .mnemonic = "TLB.IA", .asm_fmt = "tlb.ia SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000000702bULL, .field_start = 1835, .field_count = 1 },
-  { .id = "tlb_iall_32_0fb421b85c88", .mnemonic = "TLB.IALL", .asm_fmt = "tlb.iall", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x000000000030702bULL, .field_start = 1836, .field_count = 0 },
-  { .id = "tlb_iav_32_95f4937d2917", .mnemonic = "TLB.IAV", .asm_fmt = "tlb.iav SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000020702bULL, .field_start = 1836, .field_count = 1 },
-  { .id = "tlb_iv_32_bf0a5d1ea211", .mnemonic = "TLB.IV", .asm_fmt = "tlb.iv SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000010702bULL, .field_start = 1837, .field_count = 1 },
-  { .id = "ucvtf_32_987f4e019c32", .mnemonic = "UCVTF", .asm_fmt = "ucvtf.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000706bULL, .field_start = 1838, .field_count = 4 },
-  { .id = "v_add_64_394294cc5946", .mnemonic = "V.ADD", .asm_fmt = "v.add SrcL, SrcR<.neg><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000000050000007fULL, .field_start = 1842, .field_count = 5 },
-  { .id = "v_addi_64_2b2209683a13", .mnemonic = "V.ADDI", .asm_fmt = "v.addi SrcL, uimm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000000150000007fULL, .field_start = 1847, .field_count = 3 },
-  { .id = "v_and_64_1ecd348ef07b", .mnemonic = "V.AND", .asm_fmt = "v.and SrcL, SrcR<.not><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000020050000007fULL, .field_start = 1850, .field_count = 5 },
-  { .id = "v_andi_64_169f397546d5", .mnemonic = "V.ANDI", .asm_fmt = "v.andi SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000020150000007fULL, .field_start = 1855, .field_count = 3 },
-  { .id = "v_bcnt_64_42c09bd34fa3", .mnemonic = "V.BCNT", .asm_fmt = "v.bcnt SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000060670000007fULL, .field_start = 1858, .field_count = 4 },
-  { .id = "v_bic_64_e87942a9adfa", .mnemonic = "V.BIC", .asm_fmt = "v.bic SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000020670000007fULL, .field_start = 1862, .field_count = 4 },
-  { .id = "v_bis_64_cefe4375764b", .mnemonic = "V.BIS", .asm_fmt = "v.bis SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000030670000007fULL, .field_start = 1866, .field_count = 4 },
-  { .id = "v_bxs_64_6227f276c17d", .mnemonic = "V.BXS", .asm_fmt = "v.bxs SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000000670000007fULL, .field_start = 1870, .field_count = 4 },
-  { .id = "v_bxu_64_c8bf73694717", .mnemonic = "V.BXU", .asm_fmt = "v.bxu SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000010670000007fULL, .field_start = 1874, .field_count = 4 },
-  { .id = "v_clz_64_193df5d3df15", .mnemonic = "V.CLZ", .asm_fmt = "v.clz SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000050670000007fULL, .field_start = 1878, .field_count = 4 },
-  { .id = "v_cmp_and_64_5b3efc0f7b0a", .mnemonic = "V.CMP.AND", .asm_fmt = "v.cmp.and SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000020450000007fULL, .field_start = 1882, .field_count = 3 },
-  { .id = "v_cmp_andi_64_84769d4e8fa2", .mnemonic = "V.CMP.ANDI", .asm_fmt = "v.cmp.andi SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000020550000007fULL, .field_start = 1885, .field_count = 3 },
-  { .id = "v_cmp_eq_64_81fb556b62ca", .mnemonic = "V.CMP.EQ", .asm_fmt = "v.cmp.eq SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000000450000007fULL, .field_start = 1888, .field_count = 3 },
-  { .id = "v_cmp_eqi_64_e6769858459e", .mnemonic = "V.CMP.EQI", .asm_fmt = "v.cmp.eqi SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000000550000007fULL, .field_start = 1891, .field_count = 3 },
-  { .id = "v_cmp_ge_64_77301f1e67a9", .mnemonic = "V.CMP.GE", .asm_fmt = "v.cmp.ge SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000050450000007fULL, .field_start = 1894, .field_count = 3 },
-  { .id = "v_cmp_gei_64_f226c4f0d640", .mnemonic = "V.CMP.GEI", .asm_fmt = "v.cmp.gei SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000050550000007fULL, .field_start = 1897, .field_count = 3 },
-  { .id = "v_cmp_geu_64_5f66721154a8", .mnemonic = "V.CMP.GEU", .asm_fmt = "v.cmp.geu SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000070450000007fULL, .field_start = 1900, .field_count = 3 },
-  { .id = "v_cmp_geui_64_ae111c2828e9", .mnemonic = "V.CMP.GEUI", .asm_fmt = "v.cmp.geui SrcL, uimm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000070550000007fULL, .field_start = 1903, .field_count = 3 },
-  { .id = "v_cmp_lt_64_3ef2162a77ba", .mnemonic = "V.CMP.LT", .asm_fmt = "v.cmp.lt SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000040450000007fULL, .field_start = 1906, .field_count = 3 },
-  { .id = "v_cmp_lti_64_75af9c62bdfe", .mnemonic = "V.CMP.LTI", .asm_fmt = "v.cmp.lti SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000040550000007fULL, .field_start = 1909, .field_count = 3 },
-  { .id = "v_cmp_ltu_64_48ae80b99c15", .mnemonic = "V.CMP.LTU", .asm_fmt = "v.cmp.ltu SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000060450000007fULL, .field_start = 1912, .field_count = 3 },
-  { .id = "v_cmp_ltui_64_d1b1db22be04", .mnemonic = "V.CMP.LTUI", .asm_fmt = "v.cmp.ltui SrcL, uimm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000060550000007fULL, .field_start = 1915, .field_count = 3 },
-  { .id = "v_cmp_ne_64_84c9e143b8b1", .mnemonic = "V.CMP.NE", .asm_fmt = "v.cmp.ne SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000010450000007fULL, .field_start = 1918, .field_count = 3 },
-  { .id = "v_cmp_nei_64_56b66e30a15d", .mnemonic = "V.CMP.NEI", .asm_fmt = "v.cmp.nei SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000010550000007fULL, .field_start = 1921, .field_count = 3 },
-  { .id = "v_cmp_or_64_c3444f939f6f", .mnemonic = "V.CMP.OR", .asm_fmt = "v.cmp.or SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000030450000007fULL, .field_start = 1924, .field_count = 3 },
-  { .id = "v_cmp_ori_64_2e06ef6e16e7", .mnemonic = "V.CMP.ORI", .asm_fmt = "v.cmp.ori SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000030550000007fULL, .field_start = 1927, .field_count = 3 },
-  { .id = "v_csel_64_791e57f8ff22", .mnemonic = "V.CSEL", .asm_fmt = "v.csel SrcP, SrcL, SrcR<.neg>, ->Dst", .length_bits = 64, .mask = 0x0000707f0600707fULL, .match = 0x000000770000007fULL, .field_start = 1930, .field_count = 5 },
-  { .id = "v_ctz_64_7be9efa90a00", .mnemonic = "V.CTZ", .asm_fmt = "v.ctz SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000040670000007fULL, .field_start = 1935, .field_count = 4 },
-  { .id = "v_div_64_74152b35b49c", .mnemonic = "V.DIV", .asm_fmt = "v.div SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000000570000007fULL, .field_start = 1939, .field_count = 3 },
-  { .id = "v_fabs_64_cd9c01ef8cc4", .mnemonic = "V.FABS", .asm_fmt = "v.fabs SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000007b0000007fULL, .field_start = 1942, .field_count = 2 },
-  { .id = "v_fadd_64_c5c08b2ac830", .mnemonic = "V.FADD", .asm_fmt = "v.fadd SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000004b0000007fULL, .field_start = 1944, .field_count = 3 },
-  { .id = "v_fclass_64_628ee3eaf4ba", .mnemonic = "V.FCLASS", .asm_fmt = "v.fclass SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000707b0000007fULL, .field_start = 1947, .field_count = 2 },
-  { .id = "v_fcvt_64_da9f59421cae", .mnemonic = "V.FCVT", .asm_fmt = "v.fcvt.{st2dt} SrcL, ->Dst", .length_bits = 64, .mask = 0x0600707ffff0707fULL, .match = 0x0000006b0000007fULL, .field_start = 1949, .field_count = 4 },
-  { .id = "v_fcvti_64_00dd1644b48d", .mnemonic = "V.FCVTI", .asm_fmt = "v.fcvti.{st2dt} SrcL, ->Dst", .length_bits = 64, .mask = 0x0600707ffff0707fULL, .match = 0x0000106b0000007fULL, .field_start = 1953, .field_count = 4 },
-  { .id = "v_fdiv_64_0e6eb42a8167", .mnemonic = "V.FDIV", .asm_fmt = "v.fdiv SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000304b0000007fULL, .field_start = 1957, .field_count = 3 },
-  { .id = "v_feq_64_310fa4a0c71c", .mnemonic = "V.FEQ", .asm_fmt = "v.feq SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000005b0000007fULL, .field_start = 1960, .field_count = 3 },
-  { .id = "v_feqs_64_fa03903879d5", .mnemonic = "V.FEQS", .asm_fmt = "v.feqs SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000405b0000007fULL, .field_start = 1963, .field_count = 3 },
-  { .id = "v_fexp_64_9fb55afd6ae9", .mnemonic = "V.FEXP", .asm_fmt = "v.fexp SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000307b0000007fULL, .field_start = 1966, .field_count = 2 },
-  { .id = "v_fge_64_6472fe8862ea", .mnemonic = "V.FGE", .asm_fmt = "v.fge SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000305b0000007fULL, .field_start = 1968, .field_count = 3 },
-  { .id = "v_fges_64_6cad59141271", .mnemonic = "V.FGES", .asm_fmt = "v.fges SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000705b0000007fULL, .field_start = 1971, .field_count = 3 },
-  { .id = "v_flt_64_1f2a82b04cd1", .mnemonic = "V.FLT", .asm_fmt = "v.flt SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000205b0000007fULL, .field_start = 1974, .field_count = 3 },
-  { .id = "v_flts_64_d39b1c33de29", .mnemonic = "V.FLTS", .asm_fmt = "v.flts SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000605b0000007fULL, .field_start = 1977, .field_count = 3 },
-  { .id = "v_fmadd_64_813d061de8ca", .mnemonic = "V.FMADD", .asm_fmt = "v.fmadd SrcL, SrcR, SrcA, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000404b0000007fULL, .field_start = 1980, .field_count = 4 },
-  { .id = "v_fmax_64_b170fb3ede0f", .mnemonic = "V.FMAX", .asm_fmt = "v.fmax SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000205b0000107fULL, .field_start = 1984, .field_count = 3 },
-  { .id = "v_fmin_64_86ba368048a2", .mnemonic = "V.FMIN", .asm_fmt = "v.fmin SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000305b0000107fULL, .field_start = 1987, .field_count = 3 },
-  { .id = "v_fmsub_64_19c6d15b8a1d", .mnemonic = "V.FMSUB", .asm_fmt = "v.fmsub SrcL, SrcR, SrcA, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000504b0000007fULL, .field_start = 1990, .field_count = 4 },
-  { .id = "v_fmul_64_3e2b1576cbfe", .mnemonic = "V.FMUL", .asm_fmt = "v.fmul SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000204b0000007fULL, .field_start = 1994, .field_count = 3 },
-  { .id = "v_fne_64_10a12315c34e", .mnemonic = "V.FNE", .asm_fmt = "v.fne SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000105b0000007fULL, .field_start = 1997, .field_count = 3 },
-  { .id = "v_fnes_64_ae92608cb0ea", .mnemonic = "V.FNES", .asm_fmt = "v.fnes SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000505b0000007fULL, .field_start = 2000, .field_count = 3 },
-  { .id = "v_fnmadd_64_81449b1d3451", .mnemonic = "V.FNMADD", .asm_fmt = "v.fnmadd SrcL, SrcR, SrcA, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000604b0000007fULL, .field_start = 2003, .field_count = 4 },
-  { .id = "v_fnmsub_64_837584633904", .mnemonic = "V.FNMSUB", .asm_fmt = "v.fnmsub SrcL, SrcR, SrcA, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000704b0000007fULL, .field_start = 2007, .field_count = 4 },
-  { .id = "v_frecip_64_2d3f96b8d7db", .mnemonic = "V.FRECIP", .asm_fmt = "v.frecip SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000207b0000007fULL, .field_start = 2011, .field_count = 2 },
-  { .id = "v_fsqrt_64_80e65f8380da", .mnemonic = "V.FSQRT", .asm_fmt = "v.fsqrt SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000107b0000007fULL, .field_start = 2013, .field_count = 2 },
-  { .id = "v_fsub_64_09953704a14a", .mnemonic = "V.FSUB", .asm_fmt = "v.fsub SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000104b0000007fULL, .field_start = 2015, .field_count = 3 },
-  { .id = "v_icvt_64_c8fd1bad81c1", .mnemonic = "V.ICVT", .asm_fmt = "v.icvt.{st2dt} SrcL, ->Dst", .length_bits = 64, .mask = 0x0600707ffff0707fULL, .match = 0x0000606b0000007fULL, .field_start = 2018, .field_count = 4 },
-  { .id = "v_icvtf_64_a0f027af74bd", .mnemonic = "V.ICVTF", .asm_fmt = "v.icvtf.{st2dt} SrcL, ->Dst", .length_bits = 64, .mask = 0x0600707ffff0707fULL, .match = 0x0000706b0000007fULL, .field_start = 2022, .field_count = 4 },
-  { .id = "v_lb_64_67d7ec296657", .mnemonic = "V.LB", .asm_fmt = "v.lb<.local> [SrcL, <lc0>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000000090000007fULL, .field_start = 2026, .field_count = 6 },
-  { .id = "v_lb_brg_64_8766090710da", .mnemonic = "V.LB.BRG", .asm_fmt = "v.lb.brg<.local> [SrcL,  <lc0>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000000090000207fULL, .field_start = 2032, .field_count = 6 },
-  { .id = "v_lbi_64_5338c0a4b01c", .mnemonic = "V.LBI", .asm_fmt = "v.lbi<.local> [SrcL, <lc0>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000000190000007fULL, .field_start = 2038, .field_count = 5 },
-  { .id = "v_lbi_brg_64_5223a985d13b", .mnemonic = "V.LBI.BRG", .asm_fmt = "v.lbi.brg<.local> [SrcL, <lc0>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000000190000207fULL, .field_start = 2043, .field_count = 5 },
-  { .id = "v_lbu_64_08cfacc47e8b", .mnemonic = "V.LBU", .asm_fmt = "v.lbu<.local> [SrcL, <lc0>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000040090000007fULL, .field_start = 2048, .field_count = 6 },
-  { .id = "v_lbu_brg_64_8981c96ac2c4", .mnemonic = "V.LBU.BRG", .asm_fmt = "v.lbu.brg<.local> [SrcL, <lc0>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000040090000207fULL, .field_start = 2054, .field_count = 6 },
-  { .id = "v_lbui_64_129c6d28d8fa", .mnemonic = "V.LBUI", .asm_fmt = "v.lbui<.local> [SrcL, <lc0>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000040190000007fULL, .field_start = 2060, .field_count = 5 },
-  { .id = "v_lbui_brg_64_0d4264b0b4fe", .mnemonic = "V.LBUI.BRG", .asm_fmt = "v.lbui.brg<.local> [SrcL, <lc0>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000040190000207fULL, .field_start = 2065, .field_count = 5 },
-  { .id = "v_ld_64_0bb4e0cd9760", .mnemonic = "V.LD", .asm_fmt = "v.ld<.local> [SrcL, <lc0<<3>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000030090000007fULL, .field_start = 2070, .field_count = 6 },
-  { .id = "v_ld_add_64_b880252ca4af", .mnemonic = "V.LD.ADD", .asm_fmt = "v.ld.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000000b0000207fULL, .field_start = 2076, .field_count = 6 },
-  { .id = "v_ld_and_64_18248e48be84", .mnemonic = "V.LD.AND", .asm_fmt = "v.ld.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000100b0000207fULL, .field_start = 2082, .field_count = 6 },
-  { .id = "v_ld_brg_64_44d932c2c42b", .mnemonic = "V.LD.BRG", .asm_fmt = "v.ld.brg<.local> [SrcL,  <lc0<<3>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000030090000207fULL, .field_start = 2088, .field_count = 6 },
-  { .id = "v_ld_max_64_e35d8e7957c3", .mnemonic = "V.LD.MAX", .asm_fmt = "v.ld.max<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000400b0000207fULL, .field_start = 2094, .field_count = 6 },
-  { .id = "v_ld_min_64_71f54b9b61ae", .mnemonic = "V.LD.MIN", .asm_fmt = "v.ld.min<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000500b0000207fULL, .field_start = 2100, .field_count = 6 },
-  { .id = "v_ld_or_64_4568b99c9e57", .mnemonic = "V.LD.OR", .asm_fmt = "v.ld.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000200b0000207fULL, .field_start = 2106, .field_count = 6 },
-  { .id = "v_ld_xor_64_c7a54911a5fa", .mnemonic = "V.LD.XOR", .asm_fmt = "v.ld.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000300b0000207fULL, .field_start = 2112, .field_count = 6 },
-  { .id = "v_ldi_64_c2dd6f17ebd3", .mnemonic = "V.LDI", .asm_fmt = "v.ldi<.local> [SrcL, <lc0<<3>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030190000007fULL, .field_start = 2118, .field_count = 5 },
-  { .id = "v_ldi_brg_64_1696b123572b", .mnemonic = "V.LDI.BRG", .asm_fmt = "v.ldi.brg<.local> [SrcL, <lc0<<3>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030190000207fULL, .field_start = 2123, .field_count = 5 },
-  { .id = "v_ldi_u_64_35ef4d60d802", .mnemonic = "V.LDI.U", .asm_fmt = "v.ldi.u<.local> [SrcL, <lc0<<3>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030290000007fULL, .field_start = 2128, .field_count = 5 },
-  { .id = "v_ldi_u_brg_64_d8020ef56426", .mnemonic = "V.LDI.U.BRG", .asm_fmt = "v.ldi.u.brg<.local> [SrcL, <lc0<<3>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030290000207fULL, .field_start = 2133, .field_count = 5 },
-  { .id = "v_lh_64_4cc8701b698e", .mnemonic = "V.LH", .asm_fmt = "v.lh<.local> [SrcL, <lc0<<1>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000010090000007fULL, .field_start = 2138, .field_count = 6 },
-  { .id = "v_lh_brg_64_dc8629a69767", .mnemonic = "V.LH.BRG", .asm_fmt = "v.lh.brg<.local> [SrcL,  <lc0<<1>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000010090000207fULL, .field_start = 2144, .field_count = 6 },
-  { .id = "v_lhi_64_66ae52eb7684", .mnemonic = "V.LHI", .asm_fmt = "v.lhi<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010190000007fULL, .field_start = 2150, .field_count = 5 },
-  { .id = "v_lhi_brg_64_d3af43d94f66", .mnemonic = "V.LHI.BRG", .asm_fmt = "v.lhi.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010190000207fULL, .field_start = 2155, .field_count = 5 },
-  { .id = "v_lhi_u_64_17c014a96651", .mnemonic = "V.LHI.U", .asm_fmt = "v.lhi.u<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010290000007fULL, .field_start = 2160, .field_count = 5 },
-  { .id = "v_lhi_u_brg_64_97603a7ac88f", .mnemonic = "V.LHI.U.BRG", .asm_fmt = "v.lhi.u.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010290000207fULL, .field_start = 2165, .field_count = 5 },
-  { .id = "v_lhu_64_83e59201d9ae", .mnemonic = "V.LHU", .asm_fmt = "v.lhu<.local> [SrcL, <lc0<<1>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000050090000007fULL, .field_start = 2170, .field_count = 6 },
-  { .id = "v_lhu_brg_64_5e9d77a562d0", .mnemonic = "V.LHU.BRG", .asm_fmt = "v.lhu.brg<.local> [SrcL,  <lc0<<1>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000050090000207fULL, .field_start = 2176, .field_count = 6 },
-  { .id = "v_lhui_64_0d3046ae3eb8", .mnemonic = "V.LHUI", .asm_fmt = "v.lhui<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050190000007fULL, .field_start = 2182, .field_count = 5 },
-  { .id = "v_lhui_brg_64_e3dba0cc2fea", .mnemonic = "V.LHUI.BRG", .asm_fmt = "v.lhui.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050190000207fULL, .field_start = 2187, .field_count = 5 },
-  { .id = "v_lhui_u_64_85625cdca25f", .mnemonic = "V.LHUI.U", .asm_fmt = "v.lhui.u<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050290000007fULL, .field_start = 2192, .field_count = 5 },
-  { .id = "v_lhui_u_brg_64_3d2e899ff00f", .mnemonic = "V.LHUI.U.BRG", .asm_fmt = "v.lhui.u.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050290000207fULL, .field_start = 2197, .field_count = 5 },
-  { .id = "v_lw_64_5a07f2297805", .mnemonic = "V.LW", .asm_fmt = "v.lw<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000020090000007fULL, .field_start = 2202, .field_count = 6 },
-  { .id = "v_lw_add_64_d603802b2bed", .mnemonic = "V.LW.ADD", .asm_fmt = "v.lw.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000000b0000007fULL, .field_start = 2208, .field_count = 6 },
-  { .id = "v_lw_and_64_c511f6c6aad9", .mnemonic = "V.LW.AND", .asm_fmt = "v.lw.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000100b0000007fULL, .field_start = 2214, .field_count = 6 },
-  { .id = "v_lw_brg_64_6163b7a621fc", .mnemonic = "V.LW.BRG", .asm_fmt = "v.lw.brg<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000020090000207fULL, .field_start = 2220, .field_count = 6 },
-  { .id = "v_lw_max_64_c7e26075c749", .mnemonic = "V.LW.MAX", .asm_fmt = "v.lw.max<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000400b0000007fULL, .field_start = 2226, .field_count = 6 },
-  { .id = "v_lw_min_64_24160fd76a35", .mnemonic = "V.LW.MIN", .asm_fmt = "v.lw.min<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000500b0000007fULL, .field_start = 2232, .field_count = 6 },
-  { .id = "v_lw_or_64_baf9868390da", .mnemonic = "V.LW.OR", .asm_fmt = "v.lw.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000200b0000007fULL, .field_start = 2238, .field_count = 6 },
-  { .id = "v_lw_xor_64_a520a467a6d4", .mnemonic = "V.LW.XOR", .asm_fmt = "v.lw.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000300b0000007fULL, .field_start = 2244, .field_count = 6 },
-  { .id = "v_lwi_64_4170735058bc", .mnemonic = "V.LWI", .asm_fmt = "v.lwi<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020190000007fULL, .field_start = 2250, .field_count = 5 },
-  { .id = "v_lwi_brg_64_3932bb713dc5", .mnemonic = "V.LWI.BRG", .asm_fmt = "v.lwi.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020190000207fULL, .field_start = 2255, .field_count = 5 },
-  { .id = "v_lwi_u_64_d1beea8b7141", .mnemonic = "V.LWI.U", .asm_fmt = "v.lwi.u<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020290000007fULL, .field_start = 2260, .field_count = 5 },
-  { .id = "v_lwi_u_brg_64_b45d0f75f04f", .mnemonic = "V.LWI.U.BRG", .asm_fmt = "v.lwi.u.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020290000207fULL, .field_start = 2265, .field_count = 5 },
-  { .id = "v_lwu_64_aa72372808ed", .mnemonic = "V.LWU", .asm_fmt = "v.lwu<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000060090000007fULL, .field_start = 2270, .field_count = 6 },
-  { .id = "v_lwu_brg_64_c457e812a9a5", .mnemonic = "V.LWU.BRG", .asm_fmt = "v.lwu.brg<.local> [SrcL,  <lc0<<2>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000060090000207fULL, .field_start = 2276, .field_count = 6 },
-  { .id = "v_lwui_64_f96d1ab639ad", .mnemonic = "V.LWUI", .asm_fmt = "v.lwui<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060190000007fULL, .field_start = 2282, .field_count = 5 },
-  { .id = "v_lwui_brg_64_340c2e2b1ddb", .mnemonic = "V.LWUI.BRG", .asm_fmt = "v.lwui.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060190000207fULL, .field_start = 2287, .field_count = 5 },
-  { .id = "v_lwui_u_64_88aa7700d8b1", .mnemonic = "V.LWUI.U", .asm_fmt = "v.lwui.u<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060290000007fULL, .field_start = 2292, .field_count = 5 },
-  { .id = "v_lwui_u_brg_64_2b7c4722c62c", .mnemonic = "V.LWUI.U.BRG", .asm_fmt = "v.lwui.u.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060290000207fULL, .field_start = 2297, .field_count = 5 },
-  { .id = "v_madd_64_2f35316993e7", .mnemonic = "V.MADD", .asm_fmt = "v.madd SrcL, SrcR, SrcD, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x000060470000007fULL, .field_start = 2302, .field_count = 4 },
-  { .id = "v_max_64_55094376ca8f", .mnemonic = "V.MAX", .asm_fmt = "v.max SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000005b0000107fULL, .field_start = 2306, .field_count = 3 },
-  { .id = "v_min_64_12f02fa489a3", .mnemonic = "V.MIN", .asm_fmt = "v.min SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000105b0000107fULL, .field_start = 2309, .field_count = 3 },
-  { .id = "v_mul_64_06ac4ba10daf", .mnemonic = "V.MUL", .asm_fmt = "v.mul SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000000470000007fULL, .field_start = 2312, .field_count = 3 },
-  { .id = "v_or_64_78638ca1ae6f", .mnemonic = "V.OR", .asm_fmt = "v.or SrcL, SrcR<.not><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000030050000007fULL, .field_start = 2315, .field_count = 5 },
-  { .id = "v_ori_64_291c8721af33", .mnemonic = "V.ORI", .asm_fmt = "v.ori SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000030150000007fULL, .field_start = 2320, .field_count = 3 },
-  { .id = "v_psel_64_81ba051be364", .mnemonic = "V.PSEL", .asm_fmt = "v.psel  SrcP, SrcL, SrcR<.neg>, ->Dst", .length_bits = 64, .mask = 0x0000707f0600707fULL, .match = 0x000010770000007fULL, .field_start = 2323, .field_count = 5 },
-  { .id = "v_qpop_64_7938584b79ed", .mnemonic = "V.QPOP", .asm_fmt = "v.qpop SrcL.ud, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000207d0000007fULL, .field_start = 2328, .field_count = 2 },
-  { .id = "v_qpush_64_b1e840184b4c", .mnemonic = "V.QPUSH", .asm_fmt = "v.qpush SrcL.ud, SrcR.ud, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000107d0000007fULL, .field_start = 2330, .field_count = 3 },
-  { .id = "v_rdadd_64_63d092ba608e", .mnemonic = "V.RDADD", .asm_fmt = "v.rdadd SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000000d0000007fULL, .field_start = 2333, .field_count = 2 },
-  { .id = "v_rdand_64_fe7c23ec9e7d", .mnemonic = "V.RDAND", .asm_fmt = "v.rdand SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000100d0000007fULL, .field_start = 2335, .field_count = 2 },
-  { .id = "v_rdfadd_64_bc0fe646d243", .mnemonic = "V.RDFADD", .asm_fmt = "v.rdfadd SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000400d0000007fULL, .field_start = 2337, .field_count = 2 },
-  { .id = "v_rdfmax_64_ca8b0184cd49", .mnemonic = "V.RDFMAX", .asm_fmt = "v.rdfmax SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000200d0000107fULL, .field_start = 2339, .field_count = 2 },
-  { .id = "v_rdfmin_64_f5219d0eca5d", .mnemonic = "V.RDFMIN", .asm_fmt = "v.rdfmin SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000300d0000107fULL, .field_start = 2341, .field_count = 2 },
-  { .id = "v_rdmax_64_97dc8ada3b96", .mnemonic = "V.RDMAX", .asm_fmt = "v.rdmax SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000000d0000107fULL, .field_start = 2343, .field_count = 2 },
-  { .id = "v_rdmin_64_5b3c823f5a19", .mnemonic = "V.RDMIN", .asm_fmt = "v.rdmin SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000100d0000107fULL, .field_start = 2345, .field_count = 2 },
-  { .id = "v_rdor_64_ef5693869e58", .mnemonic = "V.RDOR", .asm_fmt = "v.rdor SrcL,  ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000200d0000007fULL, .field_start = 2347, .field_count = 2 },
-  { .id = "v_rdxor_64_6d27d9e02c62", .mnemonic = "V.RDXOR", .asm_fmt = "v.rdxor SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000300d0000007fULL, .field_start = 2349, .field_count = 2 },
-  { .id = "v_rem_64_b3ed504ae3f4", .mnemonic = "V.REM", .asm_fmt = "v.rem SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000040570000007fULL, .field_start = 2351, .field_count = 3 },
-  { .id = "v_rev_64_3670c780708d", .mnemonic = "V.REV", .asm_fmt = "v.rev SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000070670000007fULL, .field_start = 2354, .field_count = 4 },
-  { .id = "v_sb_64_271c7fb69b1d", .mnemonic = "V.SB", .asm_fmt = "v.sb<.local> SrcD.<T1>, [SrcL, <lc0>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000000490000007fULL, .field_start = 2358, .field_count = 6 },
-  { .id = "v_sb_brg_64_e267665cc8e1", .mnemonic = "V.SB.BRG", .asm_fmt = "v.sb.brg<.local> SrcD.<T1>, [SrcL, <lc0>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000000490000207fULL, .field_start = 2364, .field_count = 6 },
-  { .id = "v_sbi_64_7ee65c84adb3", .mnemonic = "V.SBI", .asm_fmt = "v.sbi<.local> SrcL, [SrcR, <lc0>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000000590000007fULL, .field_start = 2370, .field_count = 5 },
-  { .id = "v_sbi_brg_64_2c1623f8e7ec", .mnemonic = "V.SBI.BRG", .asm_fmt = "v.sbi.brg<.local> SrcL, [SrcR, <lc0>,  simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000000590000207fULL, .field_start = 2375, .field_count = 5 },
-  { .id = "v_sd_64_babe74d4ce5e", .mnemonic = "V.SD", .asm_fmt = "v.sd<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<(3+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000030490000007fULL, .field_start = 2380, .field_count = 6 },
-  { .id = "v_sd_add_64_9d01cd1060a2", .mnemonic = "V.SD.ADD", .asm_fmt = "v.sd.add<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000000b0000307fULL, .field_start = 2386, .field_count = 5 },
-  { .id = "v_sd_and_64_bd9bc82be46e", .mnemonic = "V.SD.AND", .asm_fmt = "v.sd.and<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000100b0000307fULL, .field_start = 2391, .field_count = 5 },
-  { .id = "v_sd_brg_64_e63e61e10a94", .mnemonic = "V.SD.BRG", .asm_fmt = "v.sd.brg<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<(3+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000030490000207fULL, .field_start = 2396, .field_count = 6 },
-  { .id = "v_sd_max_64_498ca2576e7c", .mnemonic = "V.SD.MAX", .asm_fmt = "v.sd.max<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000400b0000307fULL, .field_start = 2402, .field_count = 5 },
-  { .id = "v_sd_min_64_0cd2fc3707d5", .mnemonic = "V.SD.MIN", .asm_fmt = "v.sd.min<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000500b0000307fULL, .field_start = 2407, .field_count = 5 },
-  { .id = "v_sd_or_64_67395fafaca6", .mnemonic = "V.SD.OR", .asm_fmt = "v.sd.or<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000200b0000307fULL, .field_start = 2412, .field_count = 5 },
-  { .id = "v_sd_u_64_69b8bc4ab948", .mnemonic = "V.SD.U", .asm_fmt = "v.sd.u<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000070490000007fULL, .field_start = 2417, .field_count = 6 },
-  { .id = "v_sd_u_brg_64_08efd0674013", .mnemonic = "V.SD.U.BRG", .asm_fmt = "v.sd.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000070490000207fULL, .field_start = 2423, .field_count = 6 },
-  { .id = "v_sd_xor_64_8549b91dcf30", .mnemonic = "V.SD.XOR", .asm_fmt = "v.sd.xor<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000300b0000307fULL, .field_start = 2429, .field_count = 5 },
-  { .id = "v_sdi_64_f297b9d43bbe", .mnemonic = "V.SDI", .asm_fmt = "v.sdi<.local> SrcL, [SrcR, <lc0<3>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030590000007fULL, .field_start = 2434, .field_count = 5 },
-  { .id = "v_sdi_brg_64_dccd7436a506", .mnemonic = "V.SDI.BRG", .asm_fmt = "v.sdi.brg<.local> SrcL, [SrcR, <lc0<<3>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030590000207fULL, .field_start = 2439, .field_count = 5 },
-  { .id = "v_sdi_u_64_b26a79626935", .mnemonic = "V.SDI.U", .asm_fmt = "v.sdi.u<.local> SrcL, [SrcR, <lc0<<3>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000070590000007fULL, .field_start = 2444, .field_count = 5 },
-  { .id = "v_sdi_u_brg_64_0473fe6671f7", .mnemonic = "V.SDI.U.BRG", .asm_fmt = "v.sdi.u.brg<.local> SrcL, [SrcR, <lc0<<3>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000070590000207fULL, .field_start = 2449, .field_count = 5 },
-  { .id = "v_sh_64_06aa6975e679", .mnemonic = "V.SH", .asm_fmt = "v.sh<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<(1+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000010490000007fULL, .field_start = 2454, .field_count = 6 },
-  { .id = "v_sh_brg_64_755523148db8", .mnemonic = "V.SH.BRG", .asm_fmt = "v.sh.brg<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<(1+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000010490000207fULL, .field_start = 2460, .field_count = 6 },
-  { .id = "v_sh_u_64_7944c8319265", .mnemonic = "V.SH.U", .asm_fmt = "v.sh.u<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000050490000007fULL, .field_start = 2466, .field_count = 6 },
-  { .id = "v_sh_u_brg_64_fd1b68d36363", .mnemonic = "V.SH.U.BRG", .asm_fmt = "v.sh.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000050490000207fULL, .field_start = 2472, .field_count = 6 },
-  { .id = "v_shfl_bfly_64_3ebce3493a01", .mnemonic = "V.SHFL.BFLY", .asm_fmt = "v.shfl.bfly SrcL, SrcP, ->Dst", .length_bits = 64, .mask = 0x07f0707f07f0707fULL, .match = 0x0000201d0000007fULL, .field_start = 2478, .field_count = 3 },
-  { .id = "v_shfl_down_64_7b9a1851d32c", .mnemonic = "V.SHFL.DOWN", .asm_fmt = "v.shfl.down SrcL, SrcR, SrcP, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000101d0000007fULL, .field_start = 2481, .field_count = 4 },
-  { .id = "v_shfl_idx_64_f2e31314195c", .mnemonic = "V.SHFL.IDX", .asm_fmt = "v.shfl.idx SrcL, SrcR, SrcP, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000301d0000007fULL, .field_start = 2485, .field_count = 4 },
-  { .id = "v_shfl_up_64_05a2a5b0d9c5", .mnemonic = "V.SHFL.UP", .asm_fmt = "v.shfl.up SrcL, SrcR, SrcP, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000001d0000007fULL, .field_start = 2489, .field_count = 4 },
-  { .id = "v_shfli_bfly_64_6d0ac980b3e9", .mnemonic = "V.SHFLI.BFLY", .asm_fmt = "v.shfli.bfly SrcL, imm, ->Dst", .length_bits = 64, .mask = 0x01f0707f01f0707fULL, .match = 0x0000602d0000007fULL, .field_start = 2493, .field_count = 3 },
-  { .id = "v_shfli_down_64_95a67c6ded00", .mnemonic = "V.SHFLI.DOWN", .asm_fmt = "v.shfli.down SrcL, SrcR, imm, ->Dst", .length_bits = 64, .mask = 0x0000707f0000707fULL, .match = 0x0000502d0000007fULL, .field_start = 2496, .field_count = 4 },
-  { .id = "v_shfli_idx_64_468726b85bf8", .mnemonic = "V.SHFLI.IDX", .asm_fmt = "v.shfli.idx SrcL, SrcR, imm, ->Dst", .length_bits = 64, .mask = 0x0000707f0000707fULL, .match = 0x0000702d0000007fULL, .field_start = 2500, .field_count = 4 },
-  { .id = "v_shfli_up_64_6fa557b5a93d", .mnemonic = "V.SHFLI.UP", .asm_fmt = "v.shfli.up SrcL, SrcR, imm, ->Dst", .length_bits = 64, .mask = 0x0000707f0000707fULL, .match = 0x0000402d0000007fULL, .field_start = 2504, .field_count = 4 },
-  { .id = "v_shi_64_fb4b951ffd01", .mnemonic = "V.SHI", .asm_fmt = "v.shi<.local> SrcL, [SrcR, <lc0<<1>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010590000007fULL, .field_start = 2508, .field_count = 5 },
-  { .id = "v_shi_brg_64_df38ab889894", .mnemonic = "V.SHI.BRG", .asm_fmt = "v.shi.brg<.local> SrcL, [SrcR, <lc0<<1>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010590000207fULL, .field_start = 2513, .field_count = 5 },
-  { .id = "v_shi_u_64_b6cdb14d38de", .mnemonic = "V.SHI.U", .asm_fmt = "v.shi.u<.local> SrcL, [SrcR, <lc0<<1>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050590000007fULL, .field_start = 2518, .field_count = 5 },
-  { .id = "v_shi_u_brg_64_74e1295ffdda", .mnemonic = "V.SHI.U.BRG", .asm_fmt = "v.shi.u.brg<.local> SrcL, [SrcR, <lc0<<1>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050590000207fULL, .field_start = 2523, .field_count = 5 },
-  { .id = "v_sll_64_4d67efb816b8", .mnemonic = "V.SLL", .asm_fmt = "v.sll SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000070050000007fULL, .field_start = 2528, .field_count = 3 },
-  { .id = "v_slli_64_1b2532001de6", .mnemonic = "V.SLLI", .asm_fmt = "v.slli SrcL, shamt, ->Dst", .length_bits = 64, .mask = 0xfc00707ffff0707fULL, .match = 0x000070150000007fULL, .field_start = 2531, .field_count = 3 },
-  { .id = "v_sra_64_068f59a0b708", .mnemonic = "V.SRA", .asm_fmt = "v.sra SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000060050000007fULL, .field_start = 2534, .field_count = 3 },
-  { .id = "v_srai_64_cf7be1dfb701", .mnemonic = "V.SRAI", .asm_fmt = "v.srai SrcL, shamt, ->Dst", .length_bits = 64, .mask = 0xfc00707ffff0707fULL, .match = 0x000060150000007fULL, .field_start = 2537, .field_count = 3 },
-  { .id = "v_srl_64_889ad1b7ceb9", .mnemonic = "V.SRL", .asm_fmt = "v.srl SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000050050000007fULL, .field_start = 2540, .field_count = 3 },
-  { .id = "v_srli_64_cdec0ca1c073", .mnemonic = "V.SRLI", .asm_fmt = "v.srli SrcL, shamt, ->Dst", .length_bits = 64, .mask = 0xfc00707ffff0707fULL, .match = 0x000050150000007fULL, .field_start = 2543, .field_count = 3 },
-  { .id = "v_sub_64_3c88cf0158f8", .mnemonic = "V.SUB", .asm_fmt = "v.sub SrcL, SrcR<.neg><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000010050000007fULL, .field_start = 2546, .field_count = 5 },
-  { .id = "v_subi_64_0226b3e654bf", .mnemonic = "V.SUBI", .asm_fmt = "v.subi SrcL, uimm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000010150000007fULL, .field_start = 2551, .field_count = 3 },
-  { .id = "v_sw_64_47af61b44300", .mnemonic = "V.SW", .asm_fmt = "v.sw<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<(2+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000020490000007fULL, .field_start = 2554, .field_count = 6 },
-  { .id = "v_sw_add_64_559073c4e3f7", .mnemonic = "V.SW.ADD", .asm_fmt = "v.sw.add<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000000b0000107fULL, .field_start = 2560, .field_count = 5 },
-  { .id = "v_sw_and_64_9773aef54030", .mnemonic = "V.SW.AND", .asm_fmt = "v.sw.and<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000100b0000107fULL, .field_start = 2565, .field_count = 5 },
-  { .id = "v_sw_brg_64_d78368c708bd", .mnemonic = "V.SW.BRG", .asm_fmt = "v.sw.brg<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<(2+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000020490000207fULL, .field_start = 2570, .field_count = 6 },
-  { .id = "v_sw_max_64_2404ff65efac", .mnemonic = "V.SW.MAX", .asm_fmt = "v.sw.max<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000400b0000107fULL, .field_start = 2576, .field_count = 5 },
-  { .id = "v_sw_min_64_1ee3543106bd", .mnemonic = "V.SW.MIN", .asm_fmt = "v.sw.min<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000500b0000107fULL, .field_start = 2581, .field_count = 5 },
-  { .id = "v_sw_or_64_c82ad77db84c", .mnemonic = "V.SW.OR", .asm_fmt = "v.sw.or<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000200b0000107fULL, .field_start = 2586, .field_count = 5 },
-  { .id = "v_sw_u_64_0cf3ad373367", .mnemonic = "V.SW.U", .asm_fmt = "v.sw.u<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000060490000007fULL, .field_start = 2591, .field_count = 6 },
-  { .id = "v_sw_u_brg_64_702c78da59f4", .mnemonic = "V.SW.U.BRG", .asm_fmt = "v.sw.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000060490000207fULL, .field_start = 2597, .field_count = 6 },
-  { .id = "v_sw_xor_64_db3db9f0dce5", .mnemonic = "V.SW.XOR", .asm_fmt = "v.sw.xor<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000300b0000107fULL, .field_start = 2603, .field_count = 5 },
-  { .id = "v_swi_64_da10b8e7bf20", .mnemonic = "V.SWI", .asm_fmt = "v.swi<.local> SrcL, [SrcR, <lc0<<2>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020590000007fULL, .field_start = 2608, .field_count = 5 },
-  { .id = "v_swi_brg_64_a9cdf55c0d1b", .mnemonic = "V.SWI.BRG", .asm_fmt = "v.swi.brg<.local> SrcL, [SrcR, <lc0<<2>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020590000207fULL, .field_start = 2613, .field_count = 5 },
-  { .id = "v_swi_u_64_ff93f1677aa7", .mnemonic = "V.SWI.U", .asm_fmt = "v.swi.u<.local> SrcL, [SrcR, <lc0<<2>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060590000007fULL, .field_start = 2618, .field_count = 5 },
-  { .id = "v_swi_u_brg_64_5b46ac2ed36c", .mnemonic = "V.SWI.U.BRG", .asm_fmt = "v.swi.u.brg<.local> SrcL, [SrcR, <lc0<<2>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060590000207fULL, .field_start = 2623, .field_count = 5 },
-  { .id = "v_xor_64_d6d77c14a0be", .mnemonic = "V.XOR", .asm_fmt = "v.xor SrcL, SrcR<.not><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000040050000007fULL, .field_start = 2628, .field_count = 5 },
-  { .id = "v_xori_64_16519d21b271", .mnemonic = "V.XORI", .asm_fmt = "v.xori SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000040150000007fULL, .field_start = 2633, .field_count = 3 },
-  { .id = "xb_32_40ad190a0a7f", .mnemonic = "XB", .asm_fmt = "XB ACR-ID, C-ID", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000006f81ULL, .field_start = 2636, .field_count = 2 },
-  { .id = "xor_32_33510860c585", .mnemonic = "XOR", .asm_fmt = "xor SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004005ULL, .field_start = 2638, .field_count = 5 },
-  { .id = "xori_32_5cf7e5be17e7", .mnemonic = "XORI", .asm_fmt = "xori SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004015ULL, .field_start = 2643, .field_count = 3 },
-  { .id = "xoriw_32_1f8c6f43e2bd", .mnemonic = "XORIW", .asm_fmt = "xoriw SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004035ULL, .field_start = 2646, .field_count = 3 },
-  { .id = "xorw_32_32282566e32d", .mnemonic = "XORW", .asm_fmt = "xorw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004025ULL, .field_start = 2649, .field_count = 5 },
+  { .id = "bstart_fp_32_0c671a644214", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP RET", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000007101ULL, .field_start = 128, .field_count = 0 },
+  { .id = "bstart_fp_32_24db3966d6ba", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP ICALL", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000006101ULL, .field_start = 128, .field_count = 0 },
+  { .id = "bstart_fp_32_58ad7954fb49", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP COND, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000003101ULL, .field_start = 128, .field_count = 1 },
+  { .id = "bstart_fp_32_7978795a29a1", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP IND", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000005101ULL, .field_start = 129, .field_count = 0 },
+  { .id = "bstart_fp_32_d00a708a81f0", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP DIRECT, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000002101ULL, .field_start = 129, .field_count = 1 },
+  { .id = "bstart_fp_32_dd7bc8dd694c", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP CALL, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000004101ULL, .field_start = 130, .field_count = 1 },
+  { .id = "bstart_fp_32_face4f238d84", .mnemonic = "BSTART.FP", .asm_fmt = "BSTART.FP FALL<, fixup_label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000001101ULL, .field_start = 131, .field_count = 1 },
+  { .id = "bstart_mgather_32_c9defbf18276", .mnemonic = "BSTART.MGATHER", .asm_fmt = "BSTART.MGATHER DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000411181ULL, .field_start = 132, .field_count = 1 },
+  { .id = "bstart_mgather_cas_32_fd8c8a3b720a", .mnemonic = "BSTART.MGATHER.CAS", .asm_fmt = "BSTART.MGATHER.CAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000811181ULL, .field_start = 133, .field_count = 1 },
+  { .id = "bstart_mgather_mask_32_5573241cd944", .mnemonic = "BSTART.MGATHER.MASK", .asm_fmt = "BSTART.MGATHER.MASK DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000611181ULL, .field_start = 134, .field_count = 1 },
+  { .id = "bstart_mpar_32_2d163417c615", .mnemonic = "BSTART.MPAR", .asm_fmt = "BSTART.MPAR <VS8, VS16>", .length_bits = 32, .mask = 0x00000000f9ffffffULL, .match = 0x0000000000001181ULL, .field_start = 135, .field_count = 1 },
+  { .id = "bstart_mscatter_32_0f0ba08bd798", .mnemonic = "BSTART.MSCATTER", .asm_fmt = "BSTART.MSCATTER DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000511181ULL, .field_start = 136, .field_count = 1 },
+  { .id = "bstart_mscatter_mask_32_2a33eed646f7", .mnemonic = "BSTART.MSCATTER.MASK", .asm_fmt = "BSTART.MSCATTER.MASK DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000711181ULL, .field_start = 137, .field_count = 1 },
+  { .id = "bstart_mseq_32_39343a456ec5", .mnemonic = "BSTART.MSEQ", .asm_fmt = "BSTART.MSEQ <VS8, VS16>", .length_bits = 32, .mask = 0x00000000f9ffffffULL, .match = 0x0000000000009181ULL, .field_start = 138, .field_count = 1 },
+  { .id = "bstart_std_32_1ef99c4cedcb", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD COND, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000003001ULL, .field_start = 139, .field_count = 1 },
+  { .id = "bstart_std_32_3f6980d013f7", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD ICALL", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000006001ULL, .field_start = 140, .field_count = 0 },
+  { .id = "bstart_std_32_441ad677fffe", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD FALL<, fixup_label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000001001ULL, .field_start = 140, .field_count = 1 },
+  { .id = "bstart_std_32_816dfa76cc4a", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD RET", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000007001ULL, .field_start = 141, .field_count = 0 },
+  { .id = "bstart_std_32_986b7ee2cf6a", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD IND", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000005001ULL, .field_start = 141, .field_count = 0 },
+  { .id = "bstart_std_32_b05390d367cf", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD CALL, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000004001ULL, .field_start = 141, .field_count = 1 },
+  { .id = "bstart_std_32_c1de85e06878", .mnemonic = "BSTART.STD", .asm_fmt = "BSTART.STD DIRECT, <label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000002001ULL, .field_start = 142, .field_count = 1 },
+  { .id = "bstart_sys_32_762d9d84a6d8", .mnemonic = "BSTART.SYS", .asm_fmt = "BSTART.SYS FALL<, fixup_label>", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000001081ULL, .field_start = 143, .field_count = 1 },
+  { .id = "bstart_tepl_32_bff5143d4fe3", .mnemonic = "BSTART.TEPL", .asm_fmt = "BSTART.TEPL Mode, Function, DataType", .length_bits = 32, .mask = 0x00000000000fffffULL, .match = 0x0000000000019181ULL, .field_start = 144, .field_count = 3 },
+  { .id = "bstart_tgemv_32_ae19f5b678f5", .mnemonic = "BSTART.TGEMV", .asm_fmt = "BSTART.TGEMV DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001031181ULL, .field_start = 147, .field_count = 1 },
+  { .id = "bstart_tgemv_acc_32_9a471b21913e", .mnemonic = "BSTART.TGEMV.ACC", .asm_fmt = "BSTART.TGEMV.ACC DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001231181ULL, .field_start = 148, .field_count = 1 },
+  { .id = "bstart_tgemv_bias_32_186ee96c0a8b", .mnemonic = "BSTART.TGEMV.BIAS", .asm_fmt = "BSTART.TGEMV.BIAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001131181ULL, .field_start = 149, .field_count = 1 },
+  { .id = "bstart_tgemvmx_32_ae5e005f6589", .mnemonic = "BSTART.TGEMVMX", .asm_fmt = "BSTART.TGEMVMX DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001431181ULL, .field_start = 150, .field_count = 1 },
+  { .id = "bstart_tgemvmx_acc_32_368647b04bb0", .mnemonic = "BSTART.TGEMVMX.ACC", .asm_fmt = "BSTART.TGEMVMX.ACC DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001631181ULL, .field_start = 151, .field_count = 1 },
+  { .id = "bstart_tgemvmx_bias_32_d23011f15171", .mnemonic = "BSTART.TGEMVMX.BIAS", .asm_fmt = "BSTART.TGEMVMX.BIAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000001531181ULL, .field_start = 152, .field_count = 1 },
+  { .id = "bstart_tload_32_d0c18bb0ab15", .mnemonic = "BSTART.TLOAD", .asm_fmt = "BSTART.TLOAD DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000011181ULL, .field_start = 153, .field_count = 1 },
+  { .id = "bstart_tmatmul_32_f9da70e4e0ad", .mnemonic = "BSTART.TMATMUL", .asm_fmt = "BSTART.TMATMUL DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000031181ULL, .field_start = 154, .field_count = 1 },
+  { .id = "bstart_tmatmul_acc_32_0c8c62e5f00a", .mnemonic = "BSTART.TMATMUL.ACC", .asm_fmt = "BSTART.TMATMUL.ACC DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000231181ULL, .field_start = 155, .field_count = 1 },
+  { .id = "bstart_tmatmul_bias_32_4d5a498d12f3", .mnemonic = "BSTART.TMATMUL.BIAS", .asm_fmt = "BSTART.TMATMUL.BIAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000131181ULL, .field_start = 156, .field_count = 1 },
+  { .id = "bstart_tmatmulmx_32_e26cb3874648", .mnemonic = "BSTART.TMATMULMX", .asm_fmt = "BSTART.TMATMULMX DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000431181ULL, .field_start = 157, .field_count = 1 },
+  { .id = "bstart_tmatmulmx_acc_32_70fa59b0ab4c", .mnemonic = "BSTART.TMATMULMX.ACC", .asm_fmt = "BSTART.TMATMULMX.ACC DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000631181ULL, .field_start = 158, .field_count = 1 },
+  { .id = "bstart_tmatmulmx_bias_32_098c7efa51b0", .mnemonic = "BSTART.TMATMULMX.BIAS", .asm_fmt = "BSTART.TMATMULMX.BIAS DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000531181ULL, .field_start = 159, .field_count = 1 },
+  { .id = "bstart_tmov_32_211446509efb", .mnemonic = "BSTART.TMOV", .asm_fmt = "BSTART.TMOV DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000211181ULL, .field_start = 160, .field_count = 1 },
+  { .id = "bstart_tprefetch_32_d5f83e5aadf6", .mnemonic = "BSTART.TPREFETCH", .asm_fmt = "BSTART.TPREFETCH DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000311181ULL, .field_start = 161, .field_count = 1 },
+  { .id = "bstart_tstore_32_4048b6e8b0f4", .mnemonic = "BSTART.TSTORE", .asm_fmt = "BSTART.TSTORE DataType", .length_bits = 32, .mask = 0x0000000007ffffffULL, .match = 0x0000000000111181ULL, .field_start = 162, .field_count = 1 },
+  { .id = "bstart_vpar_32_8998d3fa51f8", .mnemonic = "BSTART.VPAR", .asm_fmt = "BSTART.VPAR <VS8, VS16>", .length_bits = 32, .mask = 0x00000000f9ffffffULL, .match = 0x0000000000021181ULL, .field_start = 163, .field_count = 1 },
+  { .id = "bstart_vseq_32_9324064902ae", .mnemonic = "BSTART.VSEQ", .asm_fmt = "BSTART.VSEQ <VS8, VS16>", .length_bits = 32, .mask = 0x00000000f9ffffffULL, .match = 0x0000000000029181ULL, .field_start = 164, .field_count = 1 },
+  { .id = "bstop_32_d25b09fdd59c", .mnemonic = "BSTOP", .asm_fmt = "BSTOP", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x0000000000000001ULL, .field_start = 165, .field_count = 0 },
+  { .id = "bwe_32_e5a5240bdf9b", .mnemonic = "BWE", .asm_fmt = "bwe SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000010002bULL, .field_start = 165, .field_count = 1 },
+  { .id = "bwi_32_d9a0905cb31b", .mnemonic = "BWI", .asm_fmt = "bwi SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000020002bULL, .field_start = 166, .field_count = 1 },
+  { .id = "bwt_32_5a0fe4a8e61f", .mnemonic = "BWT", .asm_fmt = "bwt SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000030002bULL, .field_start = 167, .field_count = 1 },
+  { .id = "bxs_32_b1bb003c1703", .mnemonic = "BXS", .asm_fmt = "bxs SrcL, M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000067ULL, .field_start = 168, .field_count = 4 },
+  { .id = "bxu_32_e9ea9715ba62", .mnemonic = "BXU", .asm_fmt = "bxu SrcL, M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001067ULL, .field_start = 172, .field_count = 4 },
+  { .id = "c_add_16_85136d1e4904", .mnemonic = "C.ADD", .asm_fmt = "c.add srcL, srcR, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000008ULL, .field_start = 176, .field_count = 2 },
+  { .id = "c_addi_16_3050744f2322", .mnemonic = "C.ADDI", .asm_fmt = "c.addi srcL, simm, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000000cULL, .field_start = 178, .field_count = 2 },
+  { .id = "c_and_16_379e5bed3352", .mnemonic = "C.AND", .asm_fmt = "c.and srcL, srcR, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000028ULL, .field_start = 180, .field_count = 2 },
+  { .id = "c_b_dim_16_14f1b8fba5e6", .mnemonic = "C.B.DIM", .asm_fmt = "C.B.DIM RegSrc, ->{LB0, LB1, LB2}", .length_bits = 16, .mask = 0x000000000000c03fULL, .match = 0x000000000000c03cULL, .field_start = 182, .field_count = 2 },
+  { .id = "c_b_dimi_16_3f1b113c76ce", .mnemonic = "C.B.DIMI", .asm_fmt = "C.B.DIMI imm, ->{LB0, LB1, LB2}", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000003cULL, .field_start = 184, .field_count = 2 },
+  { .id = "c_bstart_16_c4e238a9227a", .mnemonic = "C.BSTART", .asm_fmt = "C.BSTART COND,  label", .length_bits = 16, .mask = 0x000000000000000fULL, .match = 0x0000000000000004ULL, .field_start = 186, .field_count = 1 },
+  { .id = "c_bstart_16_f833d2a4753c", .mnemonic = "C.BSTART", .asm_fmt = "C.BSTART DIRECT, label", .length_bits = 16, .mask = 0x000000000000000fULL, .match = 0x0000000000000002ULL, .field_start = 187, .field_count = 1 },
+  { .id = "c_bstart_fp_16_9dcef7e3a85b", .mnemonic = "C.BSTART.FP", .asm_fmt = "C.BSTART.FP BrType", .length_bits = 16, .mask = 0x000000000000c7ffULL, .match = 0x0000000000000080ULL, .field_start = 188, .field_count = 1 },
+  { .id = "c_bstart_mpar_16_66c3ef2226ec", .mnemonic = "C.BSTART.MPAR", .asm_fmt = "C.BSTART.MPAR FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x00000000000008c0ULL, .field_start = 189, .field_count = 0 },
+  { .id = "c_bstart_mseq_16_b5597e0e41c2", .mnemonic = "C.BSTART.MSEQ", .asm_fmt = "C.BSTART.MSEQ FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x00000000000048c0ULL, .field_start = 189, .field_count = 0 },
+  { .id = "c_bstart_std_16_8b40f078c14a", .mnemonic = "C.BSTART.STD", .asm_fmt = "C.BSTART.STD BrType", .length_bits = 16, .mask = 0x000000000000c7ffULL, .match = 0x0000000000000000ULL, .field_start = 189, .field_count = 1 },
+  { .id = "c_bstart_sys_16_ec213ce96eb7", .mnemonic = "C.BSTART.SYS", .asm_fmt = "C.BSTART.SYS FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x0000000000000840ULL, .field_start = 190, .field_count = 0 },
+  { .id = "c_bstart_vpar_16_c4d89efc71ea", .mnemonic = "C.BSTART.VPAR", .asm_fmt = "C.BSTART.VPAR FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x00000000000088c0ULL, .field_start = 190, .field_count = 0 },
+  { .id = "c_bstart_vseq_16_50d70de3f84f", .mnemonic = "C.BSTART.VSEQ", .asm_fmt = "C.BSTART.VSEQ FALL", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x000000000000c8c0ULL, .field_start = 190, .field_count = 0 },
+  { .id = "c_bstop_16_ca4743d8a95e", .mnemonic = "C.BSTOP", .asm_fmt = "C.BSTOP", .length_bits = 16, .mask = 0x000000000000ffffULL, .match = 0x0000000000000000ULL, .field_start = 190, .field_count = 0 },
+  { .id = "c_cmp_eqi_16_e34367883ba1", .mnemonic = "C.CMP.EQI", .asm_fmt = "c.cmp.eqi t#1, simm, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000002cULL, .field_start = 190, .field_count = 1 },
+  { .id = "c_cmp_nei_16_35d1f02063e2", .mnemonic = "C.CMP.NEI", .asm_fmt = "c.cmp.nei t#1, simm, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000082cULL, .field_start = 191, .field_count = 1 },
+  { .id = "c_ebreak_16_7f9c245fa13c", .mnemonic = "C.EBREAK", .asm_fmt = "c.break imm", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000c02cULL, .field_start = 192, .field_count = 1 },
+  { .id = "c_ldi_16_973f42d37f29", .mnemonic = "C.LDI", .asm_fmt = "c.ldi [srcL, simm], ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000001aULL, .field_start = 193, .field_count = 2 },
+  { .id = "c_lwi_16_b224525971da", .mnemonic = "C.LWI", .asm_fmt = "c.lwi [srcL, simm], ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000000aULL, .field_start = 195, .field_count = 2 },
+  { .id = "c_movi_16_2c84faf1bc72", .mnemonic = "C.MOVI", .asm_fmt = "c.movi simm, ->{t, u, Rd}", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000016ULL, .field_start = 197, .field_count = 2 },
+  { .id = "c_movr_16_80d2b5f3580b", .mnemonic = "C.MOVR", .asm_fmt = "c.movr SrcL, ->{t, u, Rd}", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000006ULL, .field_start = 199, .field_count = 2 },
+  { .id = "c_or_16_90864d13a661", .mnemonic = "C.OR", .asm_fmt = "c.or srcL, srcR, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000038ULL, .field_start = 201, .field_count = 2 },
+  { .id = "c_sdi_16_bbec69bcfd5d", .mnemonic = "C.SDI", .asm_fmt = "c.sdi t#1, [srcL, simm]", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000003aULL, .field_start = 203, .field_count = 2 },
+  { .id = "c_setc_eq_16_03e6b07a3699", .mnemonic = "C.SETC.EQ", .asm_fmt = "c.setc.eq srcL, srcR", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000026ULL, .field_start = 205, .field_count = 2 },
+  { .id = "c_setc_ne_16_e9092e487e98", .mnemonic = "C.SETC.NE", .asm_fmt = "c.setc.ne srcL, srcR", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000036ULL, .field_start = 207, .field_count = 2 },
+  { .id = "c_setc_tgt_16_736be9cada01", .mnemonic = "C.SETC.TGT", .asm_fmt = "c.setc.tgt srcL", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000001cULL, .field_start = 209, .field_count = 1 },
+  { .id = "c_setret_16_335651ef6c27", .mnemonic = "C.SETRET", .asm_fmt = "c.setret uimm, - >Ra", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x0000000000005016ULL, .field_start = 210, .field_count = 1 },
+  { .id = "c_sext_b_16_8ffd07d15409", .mnemonic = "C.SEXT.B", .asm_fmt = "c.sext.b srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000401cULL, .field_start = 211, .field_count = 1 },
+  { .id = "c_sext_h_16_90cb7ea36bd3", .mnemonic = "C.SEXT.H", .asm_fmt = "c.sext.h srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000481cULL, .field_start = 212, .field_count = 1 },
+  { .id = "c_sext_w_16_f2bb13f0797b", .mnemonic = "C.SEXT.W", .asm_fmt = "c.sext.w srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000501cULL, .field_start = 213, .field_count = 1 },
+  { .id = "c_slli_16_958a14dc4058", .mnemonic = "C.SLLI", .asm_fmt = "c.slli t#1, uimm, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000102cULL, .field_start = 214, .field_count = 1 },
+  { .id = "c_srli_16_b411862f7820", .mnemonic = "C.SRLI", .asm_fmt = "c.srli t#1, uimm, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000182cULL, .field_start = 215, .field_count = 1 },
+  { .id = "c_ssrget_16_9d83a6f2749a", .mnemonic = "C.SSRGET", .asm_fmt = "c.ssrget SSR-ID, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000802cULL, .field_start = 216, .field_count = 1 },
+  { .id = "c_sub_16_ff0056ac7053", .mnemonic = "C.SUB", .asm_fmt = "c.sub srcL, srcR, ->t", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x0000000000000018ULL, .field_start = 217, .field_count = 2 },
+  { .id = "c_swi_16_ca6c111163e5", .mnemonic = "C.SWI", .asm_fmt = "c.swi t#1, [srcL, simm]", .length_bits = 16, .mask = 0x000000000000003fULL, .match = 0x000000000000002aULL, .field_start = 219, .field_count = 2 },
+  { .id = "c_zext_b_16_7ea1a59fa2da", .mnemonic = "C.ZEXT.B", .asm_fmt = "c.zext.b srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000581cULL, .field_start = 221, .field_count = 1 },
+  { .id = "c_zext_h_16_4c0976791cbc", .mnemonic = "C.ZEXT.H", .asm_fmt = "c.zext.h srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000601cULL, .field_start = 222, .field_count = 1 },
+  { .id = "c_zext_w_16_e8bc051c7e8c", .mnemonic = "C.ZEXT.W", .asm_fmt = "c.zext.w srcL, ->t", .length_bits = 16, .mask = 0x000000000000f83fULL, .match = 0x000000000000681cULL, .field_start = 223, .field_count = 1 },
+  { .id = "casb_32_7e529b871832", .mnemonic = "CASB", .asm_fmt = "casb<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000001bULL, .field_start = 224, .field_count = 6 },
+  { .id = "casd_32_5852c57277a6", .mnemonic = "CASD", .asm_fmt = "casd<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000301bULL, .field_start = 230, .field_count = 6 },
+  { .id = "cash_32_cb1315ff6cb5", .mnemonic = "CASH", .asm_fmt = "cash<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000101bULL, .field_start = 236, .field_count = 6 },
+  { .id = "casw_32_cb29e4287223", .mnemonic = "CASW", .asm_fmt = "casw<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000201bULL, .field_start = 242, .field_count = 6 },
+  { .id = "clz_32_f890415c15b6", .mnemonic = "CLZ", .asm_fmt = "clz SrcL,  M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005067ULL, .field_start = 248, .field_count = 4 },
+  { .id = "cmp_and_32_036813a12ae8", .mnemonic = "CMP.AND", .asm_fmt = "cmp.and SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000002045ULL, .field_start = 252, .field_count = 4 },
+  { .id = "cmp_andi_32_da7a5391738d", .mnemonic = "CMP.ANDI", .asm_fmt = "cmp.andi SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002055ULL, .field_start = 256, .field_count = 3 },
+  { .id = "cmp_eq_32_6af7c8f41300", .mnemonic = "CMP.EQ", .asm_fmt = "cmp.eq SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000000045ULL, .field_start = 259, .field_count = 4 },
+  { .id = "cmp_eqi_32_252943516dca", .mnemonic = "CMP.EQI", .asm_fmt = "cmp.eqi SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000055ULL, .field_start = 263, .field_count = 3 },
+  { .id = "cmp_ge_32_d88e3a1cfff4", .mnemonic = "CMP.GE", .asm_fmt = "cmp.ge SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000005045ULL, .field_start = 266, .field_count = 4 },
+  { .id = "cmp_gei_32_48bf7ea50737", .mnemonic = "CMP.GEI", .asm_fmt = "cmp.gei SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005055ULL, .field_start = 270, .field_count = 3 },
+  { .id = "cmp_geu_32_0c002dc415ef", .mnemonic = "CMP.GEU", .asm_fmt = "cmp.geu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000007045ULL, .field_start = 273, .field_count = 4 },
+  { .id = "cmp_geui_32_69ec7b908f5d", .mnemonic = "CMP.GEUI", .asm_fmt = "cmp.geui SrcL, uimm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007055ULL, .field_start = 277, .field_count = 3 },
+  { .id = "cmp_lt_32_c0b8cc320f12", .mnemonic = "CMP.LT", .asm_fmt = "cmp.lt SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000004045ULL, .field_start = 280, .field_count = 4 },
+  { .id = "cmp_lti_32_02d3081d120b", .mnemonic = "CMP.LTI", .asm_fmt = "cmp.lti SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004055ULL, .field_start = 284, .field_count = 3 },
+  { .id = "cmp_ltu_32_4377481baebc", .mnemonic = "CMP.LTU", .asm_fmt = "cmp.ltu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000006045ULL, .field_start = 287, .field_count = 4 },
+  { .id = "cmp_ltui_32_8676c7bfd797", .mnemonic = "CMP.LTUI", .asm_fmt = "cmp.ltui SrcL, uimm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006055ULL, .field_start = 291, .field_count = 3 },
+  { .id = "cmp_ne_32_fc47fbb1a0de", .mnemonic = "CMP.NE", .asm_fmt = "cmp.ne SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000001045ULL, .field_start = 294, .field_count = 4 },
+  { .id = "cmp_nei_32_00abf831b572", .mnemonic = "CMP.NEI", .asm_fmt = "cmp.nei SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001055ULL, .field_start = 298, .field_count = 3 },
+  { .id = "cmp_or_32_75e1fa54ba94", .mnemonic = "CMP.OR", .asm_fmt = "cmp.or SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x0000000000003045ULL, .field_start = 301, .field_count = 4 },
+  { .id = "cmp_ori_32_6d3efbc3d093", .mnemonic = "CMP.ORI", .asm_fmt = "cmp.ori SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003055ULL, .field_start = 305, .field_count = 3 },
+  { .id = "csel_32_ba77cbad3c99", .mnemonic = "CSEL", .asm_fmt = "csel SrcP, SrcL, SrcR<.neg>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000077ULL, .field_start = 308, .field_count = 5 },
+  { .id = "ctz_32_1761cbcc2a89", .mnemonic = "CTZ", .asm_fmt = "ctz SrcL,  M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004067ULL, .field_start = 313, .field_count = 4 },
+  { .id = "dc_cisw_32_166b7135e3c1", .mnemonic = "DC.CISW", .asm_fmt = "dc.cisw SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000060602bULL, .field_start = 317, .field_count = 1 },
+  { .id = "dc_civa_32_265d686549c8", .mnemonic = "DC.CIVA", .asm_fmt = "dc.civa SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000030602bULL, .field_start = 318, .field_count = 1 },
+  { .id = "dc_csw_32_2719115a9246", .mnemonic = "DC.CSW", .asm_fmt = "dc.csw SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000050602bULL, .field_start = 319, .field_count = 1 },
+  { .id = "dc_cva_32_166d5a076f0e", .mnemonic = "DC.CVA", .asm_fmt = "dc.cva SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000020602bULL, .field_start = 320, .field_count = 1 },
+  { .id = "dc_iall_32_3d61563dd077", .mnemonic = "DC.IALL", .asm_fmt = "dc.iall", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x000000000010602bULL, .field_start = 321, .field_count = 0 },
+  { .id = "dc_isw_32_7940273560b2", .mnemonic = "DC.ISW", .asm_fmt = "dc.isw SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000040602bULL, .field_start = 321, .field_count = 1 },
+  { .id = "dc_iva_32_0131d0cf364f", .mnemonic = "DC.IVA", .asm_fmt = "dc.iva SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000000602bULL, .field_start = 322, .field_count = 1 },
+  { .id = "dc_zva_32_0859a1d7aa5b", .mnemonic = "DC.ZVA", .asm_fmt = "dc.zva SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000070602bULL, .field_start = 323, .field_count = 1 },
+  { .id = "div_32_a6efe85f8662", .mnemonic = "DIV", .asm_fmt = "div SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000000057ULL, .field_start = 324, .field_count = 3 },
+  { .id = "divu_32_cfbc0d1760e4", .mnemonic = "DIVU", .asm_fmt = "divu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000001057ULL, .field_start = 327, .field_count = 3 },
+  { .id = "divuw_32_9c9470ef8982", .mnemonic = "DIVUW", .asm_fmt = "divuw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000003057ULL, .field_start = 330, .field_count = 3 },
+  { .id = "divw_32_b6366c50ac8c", .mnemonic = "DIVW", .asm_fmt = "divw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000002057ULL, .field_start = 333, .field_count = 3 },
+  { .id = "dma_32_a168aeca5fa5", .mnemonic = "DMA", .asm_fmt = "dma [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000fe007fffULL, .match = 0x000000000000700bULL, .field_start = 336, .field_count = 2 },
+  { .id = "ebreak_32_4f122d1e6be3", .mnemonic = "EBREAK", .asm_fmt = "ebreak imm", .length_bits = 32, .mask = 0x00000000f0ffffffULL, .match = 0x000000000010102bULL, .field_start = 338, .field_count = 1 },
+  { .id = "ercov_32_dc0be14a2d8b", .mnemonic = "ERCOV", .asm_fmt = "ERCOV [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind]", .length_bits = 32, .mask = 0x0000000006007fffULL, .match = 0x0000000000003031ULL, .field_start = 339, .field_count = 3 },
+  { .id = "esave_32_4c4f79fe3171", .mnemonic = "ESAVE", .asm_fmt = "ESAVE [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind]", .length_bits = 32, .mask = 0x0000000006007fffULL, .match = 0x0000000000002031ULL, .field_start = 342, .field_count = 3 },
+  { .id = "fabs_32_9515e008bf17", .mnemonic = "FABS", .asm_fmt = "fabs.{T} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f9f0707fULL, .match = 0x000000000000007bULL, .field_start = 345, .field_count = 3 },
+  { .id = "fadd_32_b78b658e6740", .mnemonic = "FADD", .asm_fmt = "fadd.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000004bULL, .field_start = 348, .field_count = 4 },
+  { .id = "fcvt_32_1102f5aeeda9", .mnemonic = "FCVT", .asm_fmt = "fcvt.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000006bULL, .field_start = 352, .field_count = 4 },
+  { .id = "fcvta_32_010837b9acbd", .mnemonic = "FCVTA", .asm_fmt = "fcvta.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000106bULL, .field_start = 356, .field_count = 4 },
+  { .id = "fcvtm_32_8801f1562870", .mnemonic = "FCVTM", .asm_fmt = "fcvtm.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000206bULL, .field_start = 360, .field_count = 4 },
+  { .id = "fcvtn_32_8714ba358d80", .mnemonic = "FCVTN", .asm_fmt = "fcvtn.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000306bULL, .field_start = 364, .field_count = 4 },
+  { .id = "fcvtp_32_84354a7aa6b1", .mnemonic = "FCVTP", .asm_fmt = "fcvtp.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000406bULL, .field_start = 368, .field_count = 4 },
+  { .id = "fcvtz_32_bee01d31217c", .mnemonic = "FCVTZ", .asm_fmt = "fcvtz.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000506bULL, .field_start = 372, .field_count = 4 },
+  { .id = "fdiv_32_04a5bb6ab56f", .mnemonic = "FDIV", .asm_fmt = "fdiv.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000304bULL, .field_start = 376, .field_count = 4 },
+  { .id = "fence_d_32_f4783f17d84d", .mnemonic = "FENCE.D", .asm_fmt = "fence.d pred_imm, succ_imm", .length_bits = 32, .mask = 0x00000000f00fffffULL, .match = 0x000000000000202bULL, .field_start = 380, .field_count = 2 },
+  { .id = "fence_i_32_a321a2a186b1", .mnemonic = "FENCE.I", .asm_fmt = "fence.i", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x000000001000202bULL, .field_start = 382, .field_count = 0 },
+  { .id = "fentry_32_a47584ec13b6", .mnemonic = "FENTRY", .asm_fmt = "FENTRY [RegSrc0 ~ RegSrcn], sp!, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000041ULL, .field_start = 382, .field_count = 3 },
+  { .id = "feq_32_9435d6959c3c", .mnemonic = "FEQ", .asm_fmt = "feq.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000005bULL, .field_start = 385, .field_count = 4 },
+  { .id = "feqs_32_1d3011890fa8", .mnemonic = "FEQS", .asm_fmt = "feqs.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000800005bULL, .field_start = 389, .field_count = 4 },
+  { .id = "fexit_32_37b663f2a34d", .mnemonic = "FEXIT", .asm_fmt = "FEXIT [RegDst0 ~ RegDstn], sp!, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001041ULL, .field_start = 393, .field_count = 3 },
+  { .id = "fexp_32_592ef5288c7d", .mnemonic = "FEXP", .asm_fmt = "fexp.{T} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f9f0707fULL, .match = 0x000000000000307bULL, .field_start = 396, .field_count = 3 },
+  { .id = "fge_32_b3244b2ffa89", .mnemonic = "FGE", .asm_fmt = "fge.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000305bULL, .field_start = 399, .field_count = 4 },
+  { .id = "fges_32_e0301fcee743", .mnemonic = "FGES", .asm_fmt = "fges.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000800305bULL, .field_start = 403, .field_count = 4 },
+  { .id = "flt_32_1c09549d8d3f", .mnemonic = "FLT", .asm_fmt = "flt.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000205bULL, .field_start = 407, .field_count = 4 },
+  { .id = "flts_32_c744c874e6a2", .mnemonic = "FLTS", .asm_fmt = "flts.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000800205bULL, .field_start = 411, .field_count = 4 },
+  { .id = "fmadd_32_c616a17bcb12", .mnemonic = "FMADD", .asm_fmt = "fmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000404bULL, .field_start = 415, .field_count = 5 },
+  { .id = "fmax_32_eaf3880d7739", .mnemonic = "FMAX", .asm_fmt = "fmax.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000605bULL, .field_start = 420, .field_count = 4 },
+  { .id = "fmin_32_b5c106e5cd7e", .mnemonic = "FMIN", .asm_fmt = "fmin.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000705bULL, .field_start = 424, .field_count = 4 },
+  { .id = "fmsub_32_b83012b83148", .mnemonic = "FMSUB", .asm_fmt = "fmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000504bULL, .field_start = 428, .field_count = 5 },
+  { .id = "fmul_32_7d521d9d65e7", .mnemonic = "FMUL", .asm_fmt = "fmul.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000204bULL, .field_start = 433, .field_count = 4 },
+  { .id = "fne_32_822c18caca3b", .mnemonic = "FNE", .asm_fmt = "fne.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000105bULL, .field_start = 437, .field_count = 4 },
+  { .id = "fnes_32_9b4b5a493783", .mnemonic = "FNES", .asm_fmt = "fnes.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000800105bULL, .field_start = 441, .field_count = 4 },
+  { .id = "fnmadd_32_7f45e606d299", .mnemonic = "FNMADD", .asm_fmt = "fnmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000604bULL, .field_start = 445, .field_count = 5 },
+  { .id = "fnmsub_32_6542d56665b3", .mnemonic = "FNMSUB", .asm_fmt = "fnmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000704bULL, .field_start = 450, .field_count = 5 },
+  { .id = "frecip_32_3d51f4f727ea", .mnemonic = "FRECIP", .asm_fmt = "frecip.{T} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f9f0707fULL, .match = 0x000000000000207bULL, .field_start = 455, .field_count = 3 },
+  { .id = "fret_ra_32_659c886221c1", .mnemonic = "FRET.RA", .asm_fmt = "FRET.RA [RegDst0 ~ RegDstn], sp!, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002041ULL, .field_start = 458, .field_count = 3 },
+  { .id = "fret_stk_32_4fe246bd8241", .mnemonic = "FRET.STK", .asm_fmt = "FRET.STK [RegDst0 ~ RegDstn], sp!, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003041ULL, .field_start = 461, .field_count = 3 },
+  { .id = "fsqrt_32_84b3495cc6c7", .mnemonic = "FSQRT", .asm_fmt = "fsqrt.{T} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f9f0707fULL, .match = 0x000000000000107bULL, .field_start = 464, .field_count = 3 },
+  { .id = "fsub_32_a4479d0d4276", .mnemonic = "FSUB", .asm_fmt = "fsub.{T} SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000f800707fULL, .match = 0x000000000000104bULL, .field_start = 467, .field_count = 4 },
+  { .id = "hl_addi_48_9d3818bfbe64", .mnemonic = "HL.ADDI", .asm_fmt = "hl.addi SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000015000eULL, .field_start = 471, .field_count = 3 },
+  { .id = "hl_addiw_48_f6d7f5032964", .mnemonic = "HL.ADDIW", .asm_fmt = "hl.addiw SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000035000eULL, .field_start = 474, .field_count = 3 },
+  { .id = "hl_addtpc_48_2e8e692eea09", .mnemonic = "HL.ADDTPC", .asm_fmt = "hl.addtpc imm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000007f000fULL, .match = 0x000000000007000eULL, .field_start = 477, .field_count = 2 },
+  { .id = "hl_andi_48_fe11c7ebca41", .mnemonic = "HL.ANDI", .asm_fmt = "hl.andi SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002015000eULL, .field_start = 479, .field_count = 3 },
+  { .id = "hl_andiw_48_878c6594c6ff", .mnemonic = "HL.ANDIW", .asm_fmt = "hl.andiw SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002035000eULL, .field_start = 482, .field_count = 3 },
+  { .id = "hl_bfi_48_8adfd476aacc", .mnemonic = "HL.BFI", .asm_fmt = "hl.bfi SrcL, SrcR, M, N, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000fe00707f000fULL, .match = 0x00000000204d000eULL, .field_start = 485, .field_count = 5 },
+  { .id = "hl_bstart_call_48_3c784c583c90", .mnemonic = "HL.BSTART CALL", .asm_fmt = "HL.BSTART.CALL <br_label>, <rt_label>, ->ra", .length_bits = 48, .mask = 0x0000f83f0000007fULL, .match = 0x0000501600000011ULL, .field_start = 490, .field_count = 2 },
+  { .id = "hl_bstart_fp_48_038e2e96cf64", .mnemonic = "HL.BSTART.FP", .asm_fmt = "HL.BSTART.FP COND, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000003101000eULL, .field_start = 492, .field_count = 1 },
+  { .id = "hl_bstart_fp_48_43530d2ebfae", .mnemonic = "HL.BSTART.FP", .asm_fmt = "HL.BSTART.FP FALL<, fixup_label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000001101000eULL, .field_start = 493, .field_count = 1 },
+  { .id = "hl_bstart_fp_48_81b457553844", .mnemonic = "HL.BSTART.FP", .asm_fmt = "HL.BSTART.FP CALL, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000004101000eULL, .field_start = 494, .field_count = 1 },
+  { .id = "hl_bstart_fp_48_eb938e9200eb", .mnemonic = "HL.BSTART.FP", .asm_fmt = "HL.BSTART.FP DIRECT, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000002101000eULL, .field_start = 495, .field_count = 1 },
+  { .id = "hl_bstart_std_48_51f78942222e", .mnemonic = "HL.BSTART.STD", .asm_fmt = "HL.BSTART.STD CALL, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000004001000eULL, .field_start = 496, .field_count = 1 },
+  { .id = "hl_bstart_std_48_9ba705710872", .mnemonic = "HL.BSTART.STD", .asm_fmt = "HL.BSTART.STD FALL<, fixup_label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000001001000eULL, .field_start = 497, .field_count = 1 },
+  { .id = "hl_bstart_std_48_b13f22c7c4a3", .mnemonic = "HL.BSTART.STD", .asm_fmt = "HL.BSTART.STD COND, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000003001000eULL, .field_start = 498, .field_count = 1 },
+  { .id = "hl_bstart_std_48_d814d26508a4", .mnemonic = "HL.BSTART.STD", .asm_fmt = "HL.BSTART.STD DIRECT, <label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000002001000eULL, .field_start = 499, .field_count = 1 },
+  { .id = "hl_bstart_sys_48_5bf0381f7bf8", .mnemonic = "HL.BSTART.SYS", .asm_fmt = "HL.BSTART.SYS FALL<, fixup_label>", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x000000001081000eULL, .field_start = 500, .field_count = 1 },
+  { .id = "hl_casb_48_21fb578617a8", .mnemonic = "HL.CASB", .asm_fmt = "hl.casb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000f000707ff83fULL, .match = 0x00000000600b000eULL, .field_start = 501, .field_count = 7 },
+  { .id = "hl_casd_48_fbb5c4256d30", .mnemonic = "HL.CASD", .asm_fmt = "hl.casd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000f000707ff83fULL, .match = 0x00003000600b000eULL, .field_start = 508, .field_count = 7 },
+  { .id = "hl_cash_48_eee12c324d97", .mnemonic = "HL.CASH", .asm_fmt = "hl.cash<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000f000707ff83fULL, .match = 0x00001000600b000eULL, .field_start = 515, .field_count = 7 },
+  { .id = "hl_casw_48_a89b3d58d8f0", .mnemonic = "HL.CASW", .asm_fmt = "hl.casw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000f000707ff83fULL, .match = 0x00002000600b000eULL, .field_start = 522, .field_count = 7 },
+  { .id = "hl_ccat_48_a1200d8bf5ac", .mnemonic = "HL.CCAT", .asm_fmt = "hl.ccat SrcL, SrcR, shamt, ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x00000000105d000eULL, .field_start = 529, .field_count = 5 },
+  { .id = "hl_ccatw_48_24a85ea4659c", .mnemonic = "HL.CCATW", .asm_fmt = "hl.ccatw SrcL, SrcR, shamt, ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x00000000205d000eULL, .field_start = 534, .field_count = 5 },
+  { .id = "hl_cmp_andi_48_de2aae3f4516", .mnemonic = "HL.CMP.ANDI", .asm_fmt = "hl.cmp.andi SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002055000eULL, .field_start = 539, .field_count = 3 },
+  { .id = "hl_cmp_eqi_48_887accd218b1", .mnemonic = "HL.CMP.EQI", .asm_fmt = "hl.cmp.eqi SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000055000eULL, .field_start = 542, .field_count = 3 },
+  { .id = "hl_cmp_gei_48_b3703d4c4619", .mnemonic = "HL.CMP.GEI", .asm_fmt = "hl.cmp.gei SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000005055000eULL, .field_start = 545, .field_count = 3 },
+  { .id = "hl_cmp_geui_48_c71f4fb29e6b", .mnemonic = "HL.CMP.GEUI", .asm_fmt = "hl.cmp.geui SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000007055000eULL, .field_start = 548, .field_count = 3 },
+  { .id = "hl_cmp_lti_48_bec21b77021a", .mnemonic = "HL.CMP.LTI", .asm_fmt = "hl.cmp.lti SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004055000eULL, .field_start = 551, .field_count = 3 },
+  { .id = "hl_cmp_ltui_48_d12167277d58", .mnemonic = "HL.CMP.LTUI", .asm_fmt = "hl.cmp.ltui SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000006055000eULL, .field_start = 554, .field_count = 3 },
+  { .id = "hl_cmp_nei_48_e77da507704a", .mnemonic = "HL.CMP.NEI", .asm_fmt = "hl.cmp.nei SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001055000eULL, .field_start = 557, .field_count = 3 },
+  { .id = "hl_cmp_ori_48_4167568cb50b", .mnemonic = "HL.CMP.ORI", .asm_fmt = "hl.cmp.ori SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003055000eULL, .field_start = 560, .field_count = 3 },
+  { .id = "hl_div_48_e8ff1fc1cb98", .mnemonic = "HL.DIV", .asm_fmt = "hl.div SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000000057000eULL, .field_start = 563, .field_count = 4 },
+  { .id = "hl_divu_48_597acda29e08", .mnemonic = "HL.DIVU", .asm_fmt = "hl.divu SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000001057000eULL, .field_start = 567, .field_count = 4 },
+  { .id = "hl_divuw_48_9ebe516091b8", .mnemonic = "HL.DIVUW", .asm_fmt = "hl.divuw SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000003057000eULL, .field_start = 571, .field_count = 4 },
+  { .id = "hl_divw_48_9048cdb3b22f", .mnemonic = "HL.DIVW", .asm_fmt = "hl.divw SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000002057000eULL, .field_start = 575, .field_count = 4 },
+  { .id = "hl_lb_pcr_48_c0ba9a54c8e0", .mnemonic = "HL.LB.PCR", .asm_fmt = "hl.lb.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000039000eULL, .field_start = 579, .field_count = 2 },
+  { .id = "hl_lb_po_48_5c7f5c82b186", .mnemonic = "HL.LB.PO", .asm_fmt = "hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000000009003eULL, .field_start = 581, .field_count = 6 },
+  { .id = "hl_lb_pr_48_cf73675cad50", .mnemonic = "HL.LB.PR", .asm_fmt = "hl.lb.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000000009002eULL, .field_start = 587, .field_count = 6 },
+  { .id = "hl_lbi_48_250803040cc8", .mnemonic = "HL.LBI", .asm_fmt = "hl.lbi [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000019000eULL, .field_start = 593, .field_count = 3 },
+  { .id = "hl_lbi_po_48_afbc00c48aba", .mnemonic = "HL.LBI.PO", .asm_fmt = "hl.lbi.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000019003eULL, .field_start = 596, .field_count = 4 },
+  { .id = "hl_lbi_pr_48_b4bdbd29f859", .mnemonic = "HL.LBI.PR", .asm_fmt = "hl.lbi.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000019002eULL, .field_start = 600, .field_count = 4 },
+  { .id = "hl_lbip_48_70a5767aff16", .mnemonic = "HL.LBIP", .asm_fmt = "hl.lbip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000019001eULL, .field_start = 604, .field_count = 4 },
+  { .id = "hl_lbp_48_9d1fd0b3105b", .mnemonic = "HL.LBP", .asm_fmt = "hl.lbp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000000009001eULL, .field_start = 608, .field_count = 6 },
+  { .id = "hl_lbu_pcr_48_504b34c0ec9d", .mnemonic = "HL.LBU.PCR", .asm_fmt = "hl.lbu.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004039000eULL, .field_start = 614, .field_count = 2 },
+  { .id = "hl_lbu_po_48_5c8a5b39e6c5", .mnemonic = "HL.LBU.PO", .asm_fmt = "hl.lbu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000004009003eULL, .field_start = 616, .field_count = 6 },
+  { .id = "hl_lbu_pr_48_bf9a0ea4b0db", .mnemonic = "HL.LBU.PR", .asm_fmt = "hl.lbu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000004009002eULL, .field_start = 622, .field_count = 6 },
+  { .id = "hl_lbui_48_50579e3558f4", .mnemonic = "HL.LBUI", .asm_fmt = "hl.lbui [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000004019000eULL, .field_start = 628, .field_count = 3 },
+  { .id = "hl_lbui_po_48_c889b4445022", .mnemonic = "HL.LBUI.PO", .asm_fmt = "hl.lbui.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000004019003eULL, .field_start = 631, .field_count = 4 },
+  { .id = "hl_lbui_pr_48_78a81538a7fa", .mnemonic = "HL.LBUI.PR", .asm_fmt = "hl.lbui.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000004019002eULL, .field_start = 635, .field_count = 4 },
+  { .id = "hl_lbuip_48_ad419fc474c0", .mnemonic = "HL.LBUIP", .asm_fmt = "hl.lbuip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000004019001eULL, .field_start = 639, .field_count = 4 },
+  { .id = "hl_lbup_48_c9598658dde4", .mnemonic = "HL.LBUP", .asm_fmt = "hl.lbup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000004009001eULL, .field_start = 643, .field_count = 6 },
+  { .id = "hl_ld_pcr_48_703673c266da", .mnemonic = "HL.LD.PCR", .asm_fmt = "hl.ld.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003039000eULL, .field_start = 649, .field_count = 2 },
+  { .id = "hl_ld_po_48_870e30995d10", .mnemonic = "HL.LD.PO", .asm_fmt = "hl.ld.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000003009003eULL, .field_start = 651, .field_count = 6 },
+  { .id = "hl_ld_pr_48_7ec4111b123b", .mnemonic = "HL.LD.PR", .asm_fmt = "hl.ld.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000003009002eULL, .field_start = 657, .field_count = 6 },
+  { .id = "hl_ldi_48_088e69e45b37", .mnemonic = "HL.LDI", .asm_fmt = "hl.ldi [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003019000eULL, .field_start = 663, .field_count = 3 },
+  { .id = "hl_ldi_po_48_0cc539e6798d", .mnemonic = "HL.LDI.PO", .asm_fmt = "hl.ldi.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003019003eULL, .field_start = 666, .field_count = 4 },
+  { .id = "hl_ldi_pr_48_d07cced5a281", .mnemonic = "HL.LDI.PR", .asm_fmt = "hl.ldi.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003019002eULL, .field_start = 670, .field_count = 4 },
+  { .id = "hl_ldi_u_48_894d02c12dcc", .mnemonic = "HL.LDI.U", .asm_fmt = "hl.ldi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003029000eULL, .field_start = 674, .field_count = 3 },
+  { .id = "hl_ldi_upo_48_5126b735cfe8", .mnemonic = "HL.LDI.UPO", .asm_fmt = "hl.ldi.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003029003eULL, .field_start = 677, .field_count = 4 },
+  { .id = "hl_ldi_upr_48_7a8e2794526f", .mnemonic = "HL.LDI.UPR", .asm_fmt = "hl.ldi.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003029002eULL, .field_start = 681, .field_count = 4 },
+  { .id = "hl_ldip_48_60afa6423d39", .mnemonic = "HL.LDIP", .asm_fmt = "hl.ldip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003019001eULL, .field_start = 685, .field_count = 4 },
+  { .id = "hl_ldip_u_48_6813f4fdce5c", .mnemonic = "HL.LDIP.U", .asm_fmt = "hl.ldip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003029001eULL, .field_start = 689, .field_count = 4 },
+  { .id = "hl_ldp_48_a7a45a43dff9", .mnemonic = "HL.LDP", .asm_fmt = "hl.ldp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000003009001eULL, .field_start = 693, .field_count = 6 },
+  { .id = "hl_lh_pcr_48_37df3cfe0d6e", .mnemonic = "HL.LH.PCR", .asm_fmt = "hl.lh.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001039000eULL, .field_start = 699, .field_count = 2 },
+  { .id = "hl_lh_po_48_7ca3e8b77906", .mnemonic = "HL.LH.PO", .asm_fmt = "hl.lh.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000001009003eULL, .field_start = 701, .field_count = 6 },
+  { .id = "hl_lh_pr_48_d59f64cde1dc", .mnemonic = "HL.LH.PR", .asm_fmt = "hl.lh.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000001009002eULL, .field_start = 707, .field_count = 6 },
+  { .id = "hl_lhi_48_6d94cb04aeac", .mnemonic = "HL.LHI", .asm_fmt = "hl.lhi [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001019000eULL, .field_start = 713, .field_count = 3 },
+  { .id = "hl_lhi_po_48_aa393747abda", .mnemonic = "HL.LHI.PO", .asm_fmt = "hl.lhi.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001019003eULL, .field_start = 716, .field_count = 4 },
+  { .id = "hl_lhi_pr_48_9ec8198594ad", .mnemonic = "HL.LHI.PR", .asm_fmt = "hl.lhi.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001019002eULL, .field_start = 720, .field_count = 4 },
+  { .id = "hl_lhi_u_48_4d4b89e63c98", .mnemonic = "HL.LHI.U", .asm_fmt = "hl.lhi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001029000eULL, .field_start = 724, .field_count = 3 },
+  { .id = "hl_lhi_upo_48_81c796b13b12", .mnemonic = "HL.LHI.UPO", .asm_fmt = "hl.lhi.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001029003eULL, .field_start = 727, .field_count = 4 },
+  { .id = "hl_lhi_upr_48_2a7c09d4b645", .mnemonic = "HL.LHI.UPR", .asm_fmt = "hl.lhi.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001029002eULL, .field_start = 731, .field_count = 4 },
+  { .id = "hl_lhip_48_2c664751c537", .mnemonic = "HL.LHIP", .asm_fmt = "hl.lhip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001019001eULL, .field_start = 735, .field_count = 4 },
+  { .id = "hl_lhip_u_48_e37e98d63bfd", .mnemonic = "HL.LHIP.U", .asm_fmt = "hl.lhip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001029001eULL, .field_start = 739, .field_count = 4 },
+  { .id = "hl_lhp_48_128eb429101f", .mnemonic = "HL.LHP", .asm_fmt = "hl.lhp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000001009001eULL, .field_start = 743, .field_count = 6 },
+  { .id = "hl_lhu_pcr_48_444cb4ddde1d", .mnemonic = "HL.LHU.PCR", .asm_fmt = "hl.lhu.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000005039000eULL, .field_start = 749, .field_count = 2 },
+  { .id = "hl_lhu_po_48_c57c3b4a74e8", .mnemonic = "HL.LHU.PO", .asm_fmt = "hl.lhu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000005009003eULL, .field_start = 751, .field_count = 6 },
+  { .id = "hl_lhu_pr_48_f874b126e29c", .mnemonic = "HL.LHU.PR", .asm_fmt = "hl.lhu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000005009002eULL, .field_start = 757, .field_count = 6 },
+  { .id = "hl_lhui_48_6450dca3aad9", .mnemonic = "HL.LHUI", .asm_fmt = "hl.lhui [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005019000eULL, .field_start = 763, .field_count = 3 },
+  { .id = "hl_lhui_po_48_16db8d40eee8", .mnemonic = "HL.LHUI.PO", .asm_fmt = "hl.lhui.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005019003eULL, .field_start = 766, .field_count = 4 },
+  { .id = "hl_lhui_pr_48_6a99a2b99298", .mnemonic = "HL.LHUI.PR", .asm_fmt = "hl.lhui.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005019002eULL, .field_start = 770, .field_count = 4 },
+  { .id = "hl_lhui_u_48_d75649bac1c7", .mnemonic = "HL.LHUI.U", .asm_fmt = "hl.lhui.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005029000eULL, .field_start = 774, .field_count = 3 },
+  { .id = "hl_lhui_upo_48_7f2c3eae793e", .mnemonic = "HL.LHUI.UPO", .asm_fmt = "hl.lhui.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005029003eULL, .field_start = 777, .field_count = 4 },
+  { .id = "hl_lhui_upr_48_7e66aaf61701", .mnemonic = "HL.LHUI.UPR", .asm_fmt = "hl.lhui.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005029002eULL, .field_start = 781, .field_count = 4 },
+  { .id = "hl_lhuip_48_0b0ef5bd2405", .mnemonic = "HL.LHUIP", .asm_fmt = "hl.lhuip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005019001eULL, .field_start = 785, .field_count = 4 },
+  { .id = "hl_lhuip_u_48_11a0e580caf1", .mnemonic = "HL.LHUIP.U", .asm_fmt = "hl.lhuip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005029001eULL, .field_start = 789, .field_count = 4 },
+  { .id = "hl_lhup_48_ea24f978b27a", .mnemonic = "HL.LHUP", .asm_fmt = "hl.lhup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000005009001eULL, .field_start = 793, .field_count = 6 },
+  { .id = "hl_lis_48_908853d6ef87", .mnemonic = "HL.LIS", .asm_fmt = "hl.lis simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000007f000fULL, .match = 0x00000000000d000eULL, .field_start = 799, .field_count = 2 },
+  { .id = "hl_liu_48_9dd207ce3aea", .mnemonic = "HL.LIU", .asm_fmt = "hl.liu uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000007f000fULL, .match = 0x00000000001d000eULL, .field_start = 801, .field_count = 2 },
+  { .id = "hl_lui_48_255991889818", .mnemonic = "HL.LUI", .asm_fmt = "hl.lui imm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000007f000fULL, .match = 0x000000000017000eULL, .field_start = 803, .field_count = 2 },
+  { .id = "hl_lw_pcr_48_00cf25e2ac36", .mnemonic = "HL.LW.PCR", .asm_fmt = "hl.lw.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002039000eULL, .field_start = 805, .field_count = 2 },
+  { .id = "hl_lw_po_48_ff2c6de58064", .mnemonic = "HL.LW.PO", .asm_fmt = "hl.lw.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000002009003eULL, .field_start = 807, .field_count = 6 },
+  { .id = "hl_lw_pr_48_2b0d62d28b57", .mnemonic = "HL.LW.PR", .asm_fmt = "hl.lw.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000002009002eULL, .field_start = 813, .field_count = 6 },
+  { .id = "hl_lwi_48_549c666c56fd", .mnemonic = "HL.LWI", .asm_fmt = "hl.lwi [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002019000eULL, .field_start = 819, .field_count = 3 },
+  { .id = "hl_lwi_po_48_2dc642d88d9d", .mnemonic = "HL.LWI.PO", .asm_fmt = "hl.lwi.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002019003eULL, .field_start = 822, .field_count = 4 },
+  { .id = "hl_lwi_pr_48_3b5e1524de1b", .mnemonic = "HL.LWI.PR", .asm_fmt = "hl.lwi.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002019002eULL, .field_start = 826, .field_count = 4 },
+  { .id = "hl_lwi_u_48_267e0f4a6222", .mnemonic = "HL.LWI.U", .asm_fmt = "hl.lwi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002029000eULL, .field_start = 830, .field_count = 3 },
+  { .id = "hl_lwi_upo_48_1c25d6266934", .mnemonic = "HL.LWI.UPO", .asm_fmt = "hl.lwi.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002029003eULL, .field_start = 833, .field_count = 4 },
+  { .id = "hl_lwi_upr_48_03b5f7994b14", .mnemonic = "HL.LWI.UPR", .asm_fmt = "hl.lwi.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002029002eULL, .field_start = 837, .field_count = 4 },
+  { .id = "hl_lwip_48_e459297b8b7c", .mnemonic = "HL.LWIP", .asm_fmt = "hl.lwip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002019001eULL, .field_start = 841, .field_count = 4 },
+  { .id = "hl_lwip_u_48_c9aca369eab2", .mnemonic = "HL.LWIP.U", .asm_fmt = "hl.lwip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002029001eULL, .field_start = 845, .field_count = 4 },
+  { .id = "hl_lwp_48_10fe25c62553", .mnemonic = "HL.LWP", .asm_fmt = "hl.lwp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000002009001eULL, .field_start = 849, .field_count = 6 },
+  { .id = "hl_lwu_pcr_48_95ba33b7b68c", .mnemonic = "HL.LWU.PCR", .asm_fmt = "hl.lwu.pcr [<symbol>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000006039000eULL, .field_start = 855, .field_count = 2 },
+  { .id = "hl_lwu_po_48_98730d2ddead", .mnemonic = "HL.LWU.PO", .asm_fmt = "hl.lwu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000006009003eULL, .field_start = 857, .field_count = 6 },
+  { .id = "hl_lwu_pr_48_f105cacec36c", .mnemonic = "HL.LWU.PR", .asm_fmt = "hl.lwu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000006009002eULL, .field_start = 863, .field_count = 6 },
+  { .id = "hl_lwui_48_eeb551f8269d", .mnemonic = "HL.LWUI", .asm_fmt = "hl.lwui [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006019000eULL, .field_start = 869, .field_count = 3 },
+  { .id = "hl_lwui_po_48_09a75b628dc4", .mnemonic = "HL.LWUI.PO", .asm_fmt = "hl.lwui.po [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006019003eULL, .field_start = 872, .field_count = 4 },
+  { .id = "hl_lwui_pr_48_32de19a508f0", .mnemonic = "HL.LWUI.PR", .asm_fmt = "hl.lwui.pr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006019002eULL, .field_start = 876, .field_count = 4 },
+  { .id = "hl_lwui_u_48_4570cc517629", .mnemonic = "HL.LWUI.U", .asm_fmt = "hl.lwui.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006029000eULL, .field_start = 880, .field_count = 3 },
+  { .id = "hl_lwui_upo_48_33260eb06a2c", .mnemonic = "HL.LWUI.UPO", .asm_fmt = "hl.lwui.upo [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006029003eULL, .field_start = 883, .field_count = 4 },
+  { .id = "hl_lwui_upr_48_998a98c46469", .mnemonic = "HL.LWUI.UPR", .asm_fmt = "hl.lwui.upr [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006029002eULL, .field_start = 887, .field_count = 4 },
+  { .id = "hl_lwuip_48_2a5d6d8f3b70", .mnemonic = "HL.LWUIP", .asm_fmt = "hl.lwuip [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006019001eULL, .field_start = 891, .field_count = 4 },
+  { .id = "hl_lwuip_u_48_0fed3b8c43b6", .mnemonic = "HL.LWUIP.U", .asm_fmt = "hl.lwuip.u [SrcL, simm], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006029001eULL, .field_start = 895, .field_count = 4 },
+  { .id = "hl_lwup_48_30f20380c354", .mnemonic = "HL.LWUP", .asm_fmt = "hl.lwup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000006009001eULL, .field_start = 899, .field_count = 6 },
+  { .id = "hl_madd_48_b062d741fd99", .mnemonic = "HL.MADD", .asm_fmt = "hl.madd SrcL, SrcR, SrcD, ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000600707f07ffULL, .match = 0x000000006047000eULL, .field_start = 905, .field_count = 5 },
+  { .id = "hl_maddw_48_6fac897f0264", .mnemonic = "HL.MADDW", .asm_fmt = "hl.maddw SrcL, SrcR, SrcD, ->Dst0, Dst1", .length_bits = 48, .mask = 0x00000600707f07ffULL, .match = 0x000000007047000eULL, .field_start = 910, .field_count = 5 },
+  { .id = "hl_miadd_48_ec5127b6dfd6", .mnemonic = "HL.MIADD", .asm_fmt = "hl.miadd SrcL, SrcR, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x00000000004d000eULL, .field_start = 915, .field_count = 4 },
+  { .id = "hl_misub_48_e9e4c7b23479", .mnemonic = "HL.MISUB", .asm_fmt = "hl.misub SrcL, SrcR, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x00000000104d000eULL, .field_start = 919, .field_count = 4 },
+  { .id = "hl_mul_48_0d059ff178fb", .mnemonic = "HL.MUL", .asm_fmt = "hl.mul SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000000047000eULL, .field_start = 923, .field_count = 4 },
+  { .id = "hl_mulu_48_85efdc81e8fc", .mnemonic = "HL.MULU", .asm_fmt = "hl.mulu SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000001047000eULL, .field_start = 927, .field_count = 4 },
+  { .id = "hl_ori_48_c6d8ce28a78b", .mnemonic = "HL.ORI", .asm_fmt = "hl.ori SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003015000eULL, .field_start = 931, .field_count = 3 },
+  { .id = "hl_oriw_48_17673d186249", .mnemonic = "HL.ORIW", .asm_fmt = "hl.oriw SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003035000eULL, .field_start = 934, .field_count = 3 },
+  { .id = "hl_prf_48_39641863bb21", .mnemonic = "HL.PRF", .asm_fmt = "hl.prf{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>]", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000007009000eULL, .field_start = 937, .field_count = 5 },
+  { .id = "hl_prf_a_48_267dc57d14f4", .mnemonic = "HL.PRF.A", .asm_fmt = "hl.prf.a{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f07ffULL, .match = 0x000000007009001eULL, .field_start = 942, .field_count = 6 },
+  { .id = "hl_prfi_u_48_be73891e376e", .mnemonic = "HL.PRFI.U", .asm_fmt = "hl.prfi.u{.l1,.l2,.l3} [SrcL, simm]", .length_bits = 48, .mask = 0x000000007fff003fULL, .match = 0x000000007029000eULL, .field_start = 948, .field_count = 3 },
+  { .id = "hl_prfi_ua_48_c37fb30ecb0f", .mnemonic = "HL.PRFI.UA", .asm_fmt = "hl.prfi.ua{.l1,.l2,.l3} [SrcL, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007029001eULL, .field_start = 951, .field_count = 4 },
+  { .id = "hl_qmt_48_eb9e41958045", .mnemonic = "HL.QMT", .asm_fmt = "hl.qmt.{i,e,s,r,ie,is,ir,es,er,ies,ier} SrcL, SrcR, ->{t, u}", .length_bits = 48, .mask = 0x0000e000707fffffULL, .match = 0x00000000007d000eULL, .field_start = 955, .field_count = 7 },
+  { .id = "hl_qpop_48_a2c57f5bc27b", .mnemonic = "HL.QPOP", .asm_fmt = "hl.qpop.{e,r,er} SrcL, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000f800707f07ffULL, .match = 0x00000000207d000eULL, .field_start = 962, .field_count = 6 },
+  { .id = "hl_qpush_48_3eab8e05d61a", .mnemonic = "HL.QPUSH", .asm_fmt = "hl.qpush.{h,e,r,he,hr,er,her} SrcL, SrcR, ->{t, u}", .length_bits = 48, .mask = 0x0000f000707fffffULL, .match = 0x00000000107d000eULL, .field_start = 968, .field_count = 6 },
+  { .id = "hl_rem_48_3c13e08615aa", .mnemonic = "HL.REM", .asm_fmt = "hl.rem SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000004057000eULL, .field_start = 974, .field_count = 4 },
+  { .id = "hl_remu_48_3bf4e5a663c1", .mnemonic = "HL.REMU", .asm_fmt = "hl.remu SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000005057000eULL, .field_start = 978, .field_count = 4 },
+  { .id = "hl_remuw_48_26ea6e70f2fc", .mnemonic = "HL.REMUW", .asm_fmt = "hl.remuw SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000007057000eULL, .field_start = 982, .field_count = 4 },
+  { .id = "hl_remw_48_3acb485d39a7", .mnemonic = "HL.REMW", .asm_fmt = "hl.remw SrcL, SrcR, ->Dst0, Dst1", .length_bits = 48, .mask = 0x0000fe00707f07ffULL, .match = 0x000000006057000eULL, .field_start = 986, .field_count = 4 },
+  { .id = "hl_sb_pcr_48_d0ba4b6e0f54", .mnemonic = "HL.SB.PCR", .asm_fmt = "hl.sb.pcr SrcL, [<symbol>]", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000069000eULL, .field_start = 990, .field_count = 2 },
+  { .id = "hl_sb_po_48_c21837f2c14d", .mnemonic = "HL.SB.PO", .asm_fmt = "hl.sb.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000000049003eULL, .field_start = 992, .field_count = 5 },
+  { .id = "hl_sb_pr_48_40eae4513905", .mnemonic = "HL.SB.PR", .asm_fmt = "hl.sb.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000000049002eULL, .field_start = 997, .field_count = 5 },
+  { .id = "hl_sbi_48_3504e6935382", .mnemonic = "HL.SBI", .asm_fmt = "hl.sbi SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000059000eULL, .field_start = 1002, .field_count = 3 },
+  { .id = "hl_sbi_po_48_493d9c8b27eb", .mnemonic = "HL.SBI.PO", .asm_fmt = "hl.sbi.po SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000059003eULL, .field_start = 1005, .field_count = 4 },
+  { .id = "hl_sbi_pr_48_d6f48429cca5", .mnemonic = "HL.SBI.PR", .asm_fmt = "hl.sbi.pr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000059002eULL, .field_start = 1009, .field_count = 4 },
+  { .id = "hl_sbip_48_48a212ee655e", .mnemonic = "HL.SBIP", .asm_fmt = "hl.sbip SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000000059001eULL, .field_start = 1013, .field_count = 4 },
+  { .id = "hl_sbp_48_12e03c011f0a", .mnemonic = "HL.SBP", .asm_fmt = "hl.sbp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000000049001eULL, .field_start = 1017, .field_count = 5 },
+  { .id = "hl_sd_pcr_48_8ed6bb942a78", .mnemonic = "HL.SD.PCR", .asm_fmt = "hl.sd.pcr SrcL, [<symbol>]", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003069000eULL, .field_start = 1022, .field_count = 2 },
+  { .id = "hl_sd_po_48_9ced722101a8", .mnemonic = "HL.SD.PO", .asm_fmt = "hl.sd.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000003049003eULL, .field_start = 1024, .field_count = 5 },
+  { .id = "hl_sd_pr_48_4f96249f5efe", .mnemonic = "HL.SD.PR", .asm_fmt = "hl.sd.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000003049002eULL, .field_start = 1029, .field_count = 5 },
+  { .id = "hl_sd_upo_48_ba930fbec5c7", .mnemonic = "HL.SD.UPO", .asm_fmt = "hl.sd.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000007049003eULL, .field_start = 1034, .field_count = 5 },
+  { .id = "hl_sd_upr_48_af7118270a90", .mnemonic = "HL.SD.UPR", .asm_fmt = "hl.sd.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000007049002eULL, .field_start = 1039, .field_count = 5 },
+  { .id = "hl_sdi_48_3203094081da", .mnemonic = "HL.SDI", .asm_fmt = "hl.sdi SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003059000eULL, .field_start = 1044, .field_count = 3 },
+  { .id = "hl_sdi_po_48_4b6af4b433bb", .mnemonic = "HL.SDI.PO", .asm_fmt = "hl.sdi.po SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003059003eULL, .field_start = 1047, .field_count = 4 },
+  { .id = "hl_sdi_pr_48_8b2688251991", .mnemonic = "HL.SDI.PR", .asm_fmt = "hl.sdi.pr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003059002eULL, .field_start = 1051, .field_count = 4 },
+  { .id = "hl_sdi_u_48_d9597eeba6b4", .mnemonic = "HL.SDI.U", .asm_fmt = "hl.sdi.u SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007059000eULL, .field_start = 1055, .field_count = 3 },
+  { .id = "hl_sdi_upo_48_0ceed9e5fdb0", .mnemonic = "HL.SDI.UPO", .asm_fmt = "hl.sdi.upo SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007059003eULL, .field_start = 1058, .field_count = 4 },
+  { .id = "hl_sdi_upr_48_f8aba43b65d5", .mnemonic = "HL.SDI.UPR", .asm_fmt = "hl.sdi.upr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007059002eULL, .field_start = 1062, .field_count = 4 },
+  { .id = "hl_sdip_48_6d622cf167ca", .mnemonic = "HL.SDIP", .asm_fmt = "hl.sdip SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000003059001eULL, .field_start = 1066, .field_count = 4 },
+  { .id = "hl_sdip_u_48_3260b03bb762", .mnemonic = "HL.SDIP.U", .asm_fmt = "hl.sdip.u SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000007059001eULL, .field_start = 1070, .field_count = 4 },
+  { .id = "hl_sdp_48_5884c49a7e55", .mnemonic = "HL.SDP", .asm_fmt = "hl.sdp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<3]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000003049001eULL, .field_start = 1074, .field_count = 5 },
+  { .id = "hl_sdp_u_48_66de58724f2f", .mnemonic = "HL.SDP.U", .asm_fmt = "hl.sdp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000007049001eULL, .field_start = 1079, .field_count = 5 },
+  { .id = "hl_setc_andi_48_f27796612fb3", .mnemonic = "HL.SETC.ANDI", .asm_fmt = "hl.setc.andi SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002075000eULL, .field_start = 1084, .field_count = 3 },
+  { .id = "hl_setc_eqi_48_0fe891fb0890", .mnemonic = "HL.SETC.EQI", .asm_fmt = "hl.setc.eqi SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000000075000eULL, .field_start = 1087, .field_count = 3 },
+  { .id = "hl_setc_gei_48_9563d6395d06", .mnemonic = "HL.SETC.GEI", .asm_fmt = "hl.setc.gei SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000005075000eULL, .field_start = 1090, .field_count = 3 },
+  { .id = "hl_setc_geui_48_2390319baf54", .mnemonic = "HL.SETC.GEUI", .asm_fmt = "hl.setc.geui SrcL, uimm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000007075000eULL, .field_start = 1093, .field_count = 3 },
+  { .id = "hl_setc_lti_48_ad4ffebe877c", .mnemonic = "HL.SETC.LTI", .asm_fmt = "hl.setc.lti SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004075000eULL, .field_start = 1096, .field_count = 3 },
+  { .id = "hl_setc_ltui_48_cb7a12ba6ead", .mnemonic = "HL.SETC.LTUI", .asm_fmt = "hl.setc.ltui SrcL, uimm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000006075000eULL, .field_start = 1099, .field_count = 3 },
+  { .id = "hl_setc_nei_48_f0bcf6586274", .mnemonic = "HL.SETC.NEI", .asm_fmt = "hl.setc.nei SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001075000eULL, .field_start = 1102, .field_count = 3 },
+  { .id = "hl_setc_ori_48_137bce8aeb04", .mnemonic = "HL.SETC.ORI", .asm_fmt = "hl.setc.ori SrcL, simm", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000003075000eULL, .field_start = 1105, .field_count = 3 },
+  { .id = "hl_setret_48_302bb793a800", .mnemonic = "HL.SETRET", .asm_fmt = "hl.setret imm, ->Ra", .length_bits = 48, .mask = 0x000000000fff000fULL, .match = 0x000000000507000eULL, .field_start = 1108, .field_count = 1 },
+  { .id = "hl_sh_pcr_48_705ea4062d0b", .mnemonic = "HL.SH.PCR", .asm_fmt = "hl.sh.pcr SrcL, [<symbol>]", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001069000eULL, .field_start = 1109, .field_count = 2 },
+  { .id = "hl_sh_po_48_e0b543d5b724", .mnemonic = "HL.SH.PO", .asm_fmt = "hl.sh.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000001049003eULL, .field_start = 1111, .field_count = 5 },
+  { .id = "hl_sh_pr_48_40ab17f5a580", .mnemonic = "HL.SH.PR", .asm_fmt = "hl.sh.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000001049002eULL, .field_start = 1116, .field_count = 5 },
+  { .id = "hl_sh_upo_48_5bfb8ea0c992", .mnemonic = "HL.SH.UPO", .asm_fmt = "hl.sh.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000005049003eULL, .field_start = 1121, .field_count = 5 },
+  { .id = "hl_sh_upr_48_719102d66e45", .mnemonic = "HL.SH.UPR", .asm_fmt = "hl.sh.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000005049002eULL, .field_start = 1126, .field_count = 5 },
+  { .id = "hl_shi_48_38ea3f0a4f08", .mnemonic = "HL.SHI", .asm_fmt = "hl.shi SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001059000eULL, .field_start = 1131, .field_count = 3 },
+  { .id = "hl_shi_po_48_636fea832c7b", .mnemonic = "HL.SHI.PO", .asm_fmt = "hl.shi.po SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001059003eULL, .field_start = 1134, .field_count = 4 },
+  { .id = "hl_shi_pr_48_1020eb4dff56", .mnemonic = "HL.SHI.PR", .asm_fmt = "hl.shi.pr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001059002eULL, .field_start = 1138, .field_count = 4 },
+  { .id = "hl_shi_u_48_79dbaa14d2c2", .mnemonic = "HL.SHI.U", .asm_fmt = "hl.shi.u SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005059000eULL, .field_start = 1142, .field_count = 3 },
+  { .id = "hl_shi_upo_48_de81eed370cf", .mnemonic = "HL.SHI.UPO", .asm_fmt = "hl.shi.upo SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005059003eULL, .field_start = 1145, .field_count = 4 },
+  { .id = "hl_shi_upr_48_ca9f1acbb1b2", .mnemonic = "HL.SHI.UPR", .asm_fmt = "hl.shi.upr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005059002eULL, .field_start = 1149, .field_count = 4 },
+  { .id = "hl_ship_48_156afe74f95b", .mnemonic = "HL.SHIP", .asm_fmt = "hl.ship SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000001059001eULL, .field_start = 1153, .field_count = 4 },
+  { .id = "hl_ship_u_48_fa5e1d981a8a", .mnemonic = "HL.SHIP.U", .asm_fmt = "hl.ship.u SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000005059001eULL, .field_start = 1157, .field_count = 4 },
+  { .id = "hl_shp_48_ccc507e71a27", .mnemonic = "HL.SHP", .asm_fmt = "hl.shp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<1]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000001049001eULL, .field_start = 1161, .field_count = 5 },
+  { .id = "hl_shp_u_48_232b2200b7b9", .mnemonic = "HL.SHP.U", .asm_fmt = "hl.shp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000005049001eULL, .field_start = 1166, .field_count = 5 },
+  { .id = "hl_ssrget_48_fde37e58a3c4", .mnemonic = "HL.SSRGET", .asm_fmt = "hl.ssrget SSR_ID, ->{t, u, Rd}", .length_bits = 48, .mask = 0x0000000ff07f000fULL, .match = 0x00000000003b000eULL, .field_start = 1171, .field_count = 2 },
+  { .id = "hl_ssrset_48_dd25753307c2", .mnemonic = "HL.SSRSET", .asm_fmt = "hl.ssrset SrcL, SSR_ID", .length_bits = 48, .mask = 0x000000007fff000fULL, .match = 0x00000000103b000eULL, .field_start = 1173, .field_count = 2 },
+  { .id = "hl_subi_48_e1f491a8aead", .mnemonic = "HL.SUBI", .asm_fmt = "hl.subi SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001015000eULL, .field_start = 1175, .field_count = 3 },
+  { .id = "hl_subiw_48_adc7b127a2f8", .mnemonic = "HL.SUBIW", .asm_fmt = "hl.subiw SrcL, uimm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000001035000eULL, .field_start = 1178, .field_count = 3 },
+  { .id = "hl_sw_pcr_48_8f8900dfac6b", .mnemonic = "HL.SW.PCR", .asm_fmt = "hl.sw.pcr SrcL, [<symbol>]", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000002069000eULL, .field_start = 1181, .field_count = 2 },
+  { .id = "hl_sw_po_48_84cf0cd97fde", .mnemonic = "HL.SW.PO", .asm_fmt = "hl.sw.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000002049003eULL, .field_start = 1183, .field_count = 5 },
+  { .id = "hl_sw_pr_48_d80424b0a9cb", .mnemonic = "HL.SW.PR", .asm_fmt = "hl.sw.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000002049002eULL, .field_start = 1188, .field_count = 5 },
+  { .id = "hl_sw_upo_48_59be7b468f8a", .mnemonic = "HL.SW.UPO", .asm_fmt = "hl.sw.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000006049003eULL, .field_start = 1193, .field_count = 5 },
+  { .id = "hl_sw_upr_48_d4ccb513944a", .mnemonic = "HL.SW.UPR", .asm_fmt = "hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd}", .length_bits = 48, .mask = 0x000000007fff07ffULL, .match = 0x000000006049002eULL, .field_start = 1198, .field_count = 5 },
+  { .id = "hl_swi_48_13deb2849df5", .mnemonic = "HL.SWI", .asm_fmt = "hl.swi SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002059000eULL, .field_start = 1203, .field_count = 3 },
+  { .id = "hl_swi_po_48_66a80d0fa7f5", .mnemonic = "HL.SWI.PO", .asm_fmt = "hl.swi.po SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002059003eULL, .field_start = 1206, .field_count = 4 },
+  { .id = "hl_swi_pr_48_68b9003e0421", .mnemonic = "HL.SWI.PR", .asm_fmt = "hl.swi.pr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002059002eULL, .field_start = 1210, .field_count = 4 },
+  { .id = "hl_swi_u_48_fac636330fd6", .mnemonic = "HL.SWI.U", .asm_fmt = "hl.swi.u SrcD, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006059000eULL, .field_start = 1214, .field_count = 3 },
+  { .id = "hl_swi_upo_48_243d3c38cd1a", .mnemonic = "HL.SWI.UPO", .asm_fmt = "hl.swi.upo SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006059003eULL, .field_start = 1217, .field_count = 4 },
+  { .id = "hl_swi_upr_48_15c2fb96aab0", .mnemonic = "HL.SWI.UPR", .asm_fmt = "hl.swi.upr SrcD, [SrcR, simm], ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006059002eULL, .field_start = 1221, .field_count = 4 },
+  { .id = "hl_swip_48_e2fca8cde001", .mnemonic = "HL.SWIP", .asm_fmt = "hl.swip SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000002059001eULL, .field_start = 1225, .field_count = 4 },
+  { .id = "hl_swip_u_48_e2dc917c8505", .mnemonic = "HL.SWIP.U", .asm_fmt = "hl.swip.u SrcD, SrcD1, [SrcR, simm]", .length_bits = 48, .mask = 0x00000000707f003fULL, .match = 0x000000006059001eULL, .field_start = 1229, .field_count = 4 },
+  { .id = "hl_swp_48_d0efe96e09f0", .mnemonic = "HL.SWP", .asm_fmt = "hl.swp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<2]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000002049001eULL, .field_start = 1233, .field_count = 5 },
+  { .id = "hl_swp_u_48_c244a576be8e", .mnemonic = "HL.SWP.U", .asm_fmt = "hl.swp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 48, .mask = 0x000000007ffff83fULL, .match = 0x000000006049001eULL, .field_start = 1238, .field_count = 5 },
+  { .id = "hl_xori_48_b4d85f91aad8", .mnemonic = "HL.XORI", .asm_fmt = "hl.xori SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004015000eULL, .field_start = 1243, .field_count = 3 },
+  { .id = "hl_xoriw_48_9a3edbd09746", .mnemonic = "HL.XORIW", .asm_fmt = "hl.xoriw SrcL, simm, ->{t, u, Rd}", .length_bits = 48, .mask = 0x00000000707f000fULL, .match = 0x000000004035000eULL, .field_start = 1246, .field_count = 3 },
+  { .id = "ic_iall_32_854f0d4d906a", .mnemonic = "IC.IALL", .asm_fmt = "ic.iall", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x000000000010502bULL, .field_start = 1249, .field_count = 0 },
+  { .id = "ic_iva_32_11b9a61dd8b5", .mnemonic = "IC.IVA", .asm_fmt = "ic.iva SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000000502bULL, .field_start = 1249, .field_count = 1 },
+  { .id = "j_32_a303cf05af42", .mnemonic = "J", .asm_fmt = "j label", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000037ULL, .field_start = 1250, .field_count = 1 },
+  { .id = "jr_32_c4128e843b05", .mnemonic = "JR", .asm_fmt = "jr SrcL, label", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006027ULL, .field_start = 1251, .field_count = 3 },
+  { .id = "l_bstart_fp_64_098e57019d7b", .mnemonic = "L.BSTART.FP", .asm_fmt = "L.BSTART.FP COND, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000030810000000fULL, .field_start = 1254, .field_count = 1 },
+  { .id = "l_bstart_fp_64_0cac9941f7d4", .mnemonic = "L.BSTART.FP", .asm_fmt = "L.BSTART.FP DIRECT, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000020810000000fULL, .field_start = 1255, .field_count = 1 },
+  { .id = "l_bstart_fp_64_2067ad6667ed", .mnemonic = "L.BSTART.FP", .asm_fmt = "L.BSTART.FP CALL, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000040810000000fULL, .field_start = 1256, .field_count = 1 },
+  { .id = "l_bstart_fp_64_8115c042ef26", .mnemonic = "L.BSTART.FP", .asm_fmt = "L.BSTART.FP FALL<, fixup_label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000010810000000fULL, .field_start = 1257, .field_count = 1 },
+  { .id = "l_bstart_std_64_37e84068ce61", .mnemonic = "L.BSTART.STD", .asm_fmt = "L.BSTART.STD DIRECT, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000020010000000fULL, .field_start = 1258, .field_count = 1 },
+  { .id = "l_bstart_std_64_463a1567da91", .mnemonic = "L.BSTART.STD", .asm_fmt = "L.BSTART.STD CALL, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000040010000000fULL, .field_start = 1259, .field_count = 1 },
+  { .id = "l_bstart_std_64_72d502fcd30d", .mnemonic = "L.BSTART.STD", .asm_fmt = "L.BSTART.STD COND, <label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000030010000000fULL, .field_start = 1260, .field_count = 1 },
+  { .id = "l_bstart_std_64_899592f9c5bc", .mnemonic = "L.BSTART.STD", .asm_fmt = "L.BSTART.STD FALL<, fixup_label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000010010000000fULL, .field_start = 1261, .field_count = 1 },
+  { .id = "l_bstart_sys_64_919e576c79e4", .mnemonic = "L.BSTART.SYS", .asm_fmt = "L.BSTART.SYS FALL<, fixup_label>", .length_bits = 64, .mask = 0x00007fff0000007fULL, .match = 0x000010110000000fULL, .field_start = 1262, .field_count = 1 },
+  { .id = "lb_32_b718aa88e28f", .mnemonic = "LB", .asm_fmt = "lb [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000009ULL, .field_start = 1263, .field_count = 5 },
+  { .id = "lb_pcr_32_3fa2540b22d0", .mnemonic = "LB.PCR", .asm_fmt = "lb.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000039ULL, .field_start = 1268, .field_count = 2 },
+  { .id = "lbi_32_9af2cdbeb38f", .mnemonic = "LBI", .asm_fmt = "lbi [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000019ULL, .field_start = 1270, .field_count = 3 },
+  { .id = "lbu_32_a9a58ab4ea22", .mnemonic = "LBU", .asm_fmt = "lbu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004009ULL, .field_start = 1273, .field_count = 5 },
+  { .id = "lbu_pcr_32_5b571b0c8dc2", .mnemonic = "LBU.PCR", .asm_fmt = "lbu.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004039ULL, .field_start = 1278, .field_count = 2 },
+  { .id = "lbui_32_c39b9aa11f02", .mnemonic = "LBUI", .asm_fmt = "lbui [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004019ULL, .field_start = 1280, .field_count = 3 },
+  { .id = "ld_32_7c48838bc4e6", .mnemonic = "LD", .asm_fmt = "ld [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003009ULL, .field_start = 1283, .field_count = 5 },
+  { .id = "ld_add_32_a4038a6c7e86", .mnemonic = "LD.ADD", .asm_fmt = "ld.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000400bULL, .field_start = 1288, .field_count = 6 },
+  { .id = "ld_and_32_2a46b3003480", .mnemonic = "LD.AND", .asm_fmt = "ld.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000400bULL, .field_start = 1294, .field_count = 6 },
+  { .id = "ld_or_32_456d270cfc7d", .mnemonic = "LD.OR", .asm_fmt = "ld.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000400bULL, .field_start = 1300, .field_count = 6 },
+  { .id = "ld_pcr_32_99bc3d2d487b", .mnemonic = "LD.PCR", .asm_fmt = "ld.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003039ULL, .field_start = 1306, .field_count = 2 },
+  { .id = "ld_smax_32_a3aad6120226", .mnemonic = "LD.SMAX", .asm_fmt = "ld.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000004000400bULL, .field_start = 1308, .field_count = 6 },
+  { .id = "ld_smin_32_9461d345718f", .mnemonic = "LD.SMIN", .asm_fmt = "ld.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000005000400bULL, .field_start = 1314, .field_count = 6 },
+  { .id = "ld_umax_32_a84af75745d9", .mnemonic = "LD.UMAX", .asm_fmt = "ld.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000006000400bULL, .field_start = 1320, .field_count = 6 },
+  { .id = "ld_umin_32_4bf2f357eff3", .mnemonic = "LD.UMIN", .asm_fmt = "ld.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000007000400bULL, .field_start = 1326, .field_count = 6 },
+  { .id = "ld_xor_32_33072c0fde61", .mnemonic = "LD.XOR", .asm_fmt = "ld.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000400bULL, .field_start = 1332, .field_count = 6 },
+  { .id = "ldi_32_d82a643f7a2b", .mnemonic = "LDI", .asm_fmt = "ldi [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003019ULL, .field_start = 1338, .field_count = 3 },
+  { .id = "ldi_u_32_111bb521a439", .mnemonic = "LDI.U", .asm_fmt = "ldi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003029ULL, .field_start = 1341, .field_count = 3 },
+  { .id = "lh_32_d0f04d7d7696", .mnemonic = "LH", .asm_fmt = "lh [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001009ULL, .field_start = 1344, .field_count = 5 },
+  { .id = "lh_pcr_32_aabf46d21e49", .mnemonic = "LH.PCR", .asm_fmt = "lh.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001039ULL, .field_start = 1349, .field_count = 2 },
+  { .id = "lhi_32_46a45ec7074d", .mnemonic = "LHI", .asm_fmt = "lhi [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001019ULL, .field_start = 1351, .field_count = 3 },
+  { .id = "lhi_u_32_bb0c81c6e61d", .mnemonic = "LHI.U", .asm_fmt = "lhi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001029ULL, .field_start = 1354, .field_count = 3 },
+  { .id = "lhu_32_730caf67ecd1", .mnemonic = "LHU", .asm_fmt = "lhu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005009ULL, .field_start = 1357, .field_count = 5 },
+  { .id = "lhu_pcr_32_9f4a1c04f258", .mnemonic = "LHU.PCR", .asm_fmt = "lhu.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005039ULL, .field_start = 1362, .field_count = 2 },
+  { .id = "lhui_32_6da39bba900b", .mnemonic = "LHUI", .asm_fmt = "lhui [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005019ULL, .field_start = 1364, .field_count = 3 },
+  { .id = "lhui_u_32_748b15cd2ced", .mnemonic = "LHUI.U", .asm_fmt = "lhui.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005029ULL, .field_start = 1367, .field_count = 3 },
+  { .id = "lr_b_32_cf80903a761a", .mnemonic = "LR.B", .asm_fmt = "lr.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000000bULL, .field_start = 1370, .field_count = 6 },
+  { .id = "lr_d_32_84d21a553dc1", .mnemonic = "LR.D", .asm_fmt = "lr.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000000bULL, .field_start = 1376, .field_count = 6 },
+  { .id = "lr_h_32_f936df218d63", .mnemonic = "LR.H", .asm_fmt = "lr.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000000bULL, .field_start = 1382, .field_count = 6 },
+  { .id = "lr_w_32_efecc735bb75", .mnemonic = "LR.W", .asm_fmt = "lr.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000000bULL, .field_start = 1388, .field_count = 6 },
+  { .id = "lsrget_32_448b17d7c20a", .mnemonic = "LSRGET", .asm_fmt = "lsrget LSR_ID, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000000ff07fULL, .match = 0x000000000000303bULL, .field_start = 1394, .field_count = 2 },
+  { .id = "lui_32_982113b541d6", .mnemonic = "LUI", .asm_fmt = "lui simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000007fULL, .match = 0x0000000000000017ULL, .field_start = 1396, .field_count = 2 },
+  { .id = "lw_32_3a77ffafcb34", .mnemonic = "LW", .asm_fmt = "lw [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002009ULL, .field_start = 1398, .field_count = 5 },
+  { .id = "lw_add_32_5be3ad1ad081", .mnemonic = "LW.ADD", .asm_fmt = "lw.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000200bULL, .field_start = 1403, .field_count = 6 },
+  { .id = "lw_and_32_f8dd9866b069", .mnemonic = "LW.AND", .asm_fmt = "lw.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000200bULL, .field_start = 1409, .field_count = 6 },
+  { .id = "lw_or_32_d6d2f87706fd", .mnemonic = "LW.OR", .asm_fmt = "lw.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000200bULL, .field_start = 1415, .field_count = 6 },
+  { .id = "lw_pcr_32_d135a1aa4ffb", .mnemonic = "LW.PCR", .asm_fmt = "lw.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002039ULL, .field_start = 1421, .field_count = 2 },
+  { .id = "lw_smax_32_838b8c673c91", .mnemonic = "LW.SMAX", .asm_fmt = "lw.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000004000200bULL, .field_start = 1423, .field_count = 6 },
+  { .id = "lw_smin_32_44452ae44d02", .mnemonic = "LW.SMIN", .asm_fmt = "lw.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000005000200bULL, .field_start = 1429, .field_count = 6 },
+  { .id = "lw_umax_32_3c6a5a534674", .mnemonic = "LW.UMAX", .asm_fmt = "lw.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000006000200bULL, .field_start = 1435, .field_count = 6 },
+  { .id = "lw_umin_32_fd9b7bb538a3", .mnemonic = "LW.UMIN", .asm_fmt = "lw.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000007000200bULL, .field_start = 1441, .field_count = 6 },
+  { .id = "lw_xor_32_4d4aa82c676a", .mnemonic = "LW.XOR", .asm_fmt = "lw.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000200bULL, .field_start = 1447, .field_count = 6 },
+  { .id = "lwi_32_7085c98058fa", .mnemonic = "LWI", .asm_fmt = "lwi [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002019ULL, .field_start = 1453, .field_count = 3 },
+  { .id = "lwi_u_32_4a7426a70f10", .mnemonic = "LWI.U", .asm_fmt = "lwi.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002029ULL, .field_start = 1456, .field_count = 3 },
+  { .id = "lwu_32_678935925636", .mnemonic = "LWU", .asm_fmt = "lwu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006009ULL, .field_start = 1459, .field_count = 5 },
+  { .id = "lwu_pcr_32_df27ea51c564", .mnemonic = "LWU.PCR", .asm_fmt = "lwu.pcr [symbol], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006039ULL, .field_start = 1464, .field_count = 2 },
+  { .id = "lwui_32_b435f946eb71", .mnemonic = "LWUI", .asm_fmt = "lwui [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006019ULL, .field_start = 1466, .field_count = 3 },
+  { .id = "lwui_u_32_1fcbb98df571", .mnemonic = "LWUI.U", .asm_fmt = "lwui.u [SrcL, simm], ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006029ULL, .field_start = 1469, .field_count = 3 },
+  { .id = "madd_32_6208e8e59303", .mnemonic = "MADD", .asm_fmt = "madd SrcL, SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000600707fULL, .match = 0x0000000000006047ULL, .field_start = 1472, .field_count = 4 },
+  { .id = "maddw_32_9f922b15e674", .mnemonic = "MADDW", .asm_fmt = "maddw SrcL, SrcR, SrcD, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000600707fULL, .match = 0x0000000000007047ULL, .field_start = 1476, .field_count = 4 },
+  { .id = "max_32_9166468a1db7", .mnemonic = "MAX", .asm_fmt = "max SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x000000000000405bULL, .field_start = 1480, .field_count = 3 },
+  { .id = "maxu_32_b8789571339d", .mnemonic = "MAXU", .asm_fmt = "maxu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x000000000800405bULL, .field_start = 1483, .field_count = 3 },
+  { .id = "mcopy_32_4fc4a803e995", .mnemonic = "MCOPY", .asm_fmt = "MCOPY [RegSrc0, RegSrc1, RegSrc2]", .length_bits = 32, .mask = 0x0000000006007fffULL, .match = 0x0000000000000031ULL, .field_start = 1486, .field_count = 3 },
+  { .id = "min_32_25692b799267", .mnemonic = "MIN", .asm_fmt = "min SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x000000000000505bULL, .field_start = 1489, .field_count = 3 },
+  { .id = "minu_32_9bdb71ef7b19", .mnemonic = "MINU", .asm_fmt = "minu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x000000000800505bULL, .field_start = 1492, .field_count = 3 },
+  { .id = "mset_32_0b932f291932", .mnemonic = "MSET", .asm_fmt = "MSET [RegSrc0, RegSrc1, RegSrc2]", .length_bits = 32, .mask = 0x0000000006007fffULL, .match = 0x0000000000001031ULL, .field_start = 1495, .field_count = 3 },
+  { .id = "mul_32_9f2affd8efb8", .mnemonic = "MUL", .asm_fmt = "mul SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000000047ULL, .field_start = 1498, .field_count = 3 },
+  { .id = "mulu_32_10b9d1936631", .mnemonic = "MULU", .asm_fmt = "mulu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000001047ULL, .field_start = 1501, .field_count = 3 },
+  { .id = "muluw_32_8f52b3d45e53", .mnemonic = "MULUW", .asm_fmt = "muluw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000003047ULL, .field_start = 1504, .field_count = 3 },
+  { .id = "mulw_32_b90cb6a30a23", .mnemonic = "MULW", .asm_fmt = "mulw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000002047ULL, .field_start = 1507, .field_count = 3 },
+  { .id = "or_32_a7fb80e78831", .mnemonic = "OR", .asm_fmt = "or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003005ULL, .field_start = 1510, .field_count = 5 },
+  { .id = "ori_32_413a6cc76e9a", .mnemonic = "ORI", .asm_fmt = "ori SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003015ULL, .field_start = 1515, .field_count = 3 },
+  { .id = "oriw_32_91608caf1ba6", .mnemonic = "ORIW", .asm_fmt = "oriw SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003035ULL, .field_start = 1518, .field_count = 3 },
+  { .id = "orw_32_84f7ac2ed68f", .mnemonic = "ORW", .asm_fmt = "orw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003025ULL, .field_start = 1521, .field_count = 5 },
+  { .id = "prf_32_30e6dfe4e3ce", .mnemonic = "PRF", .asm_fmt = "prf [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007009ULL, .field_start = 1526, .field_count = 5 },
+  { .id = "prfi_u_32_167b42882547", .mnemonic = "PRFI.U", .asm_fmt = "prfi.u [SrcL, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007029ULL, .field_start = 1531, .field_count = 3 },
+  { .id = "rem_32_0abbd6a3b865", .mnemonic = "REM", .asm_fmt = "rem SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000004057ULL, .field_start = 1534, .field_count = 3 },
+  { .id = "remu_32_d7a5d1ebbbf5", .mnemonic = "REMU", .asm_fmt = "remu SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000005057ULL, .field_start = 1537, .field_count = 3 },
+  { .id = "remuw_32_f10ade2f5ccb", .mnemonic = "REMUW", .asm_fmt = "remuw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000007057ULL, .field_start = 1540, .field_count = 3 },
+  { .id = "remw_32_22659af46ec0", .mnemonic = "REMW", .asm_fmt = "remw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000006057ULL, .field_start = 1543, .field_count = 3 },
+  { .id = "rev_32_58badc109d49", .mnemonic = "REV", .asm_fmt = "rev SrcL,  M, N, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007067ULL, .field_start = 1546, .field_count = 4 },
+  { .id = "sb_32_43c106ae3749", .mnemonic = "SB", .asm_fmt = "sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000000049ULL, .field_start = 1550, .field_count = 4 },
+  { .id = "sb_pcr_32_7625a9a24c59", .mnemonic = "SB.PCR", .asm_fmt = "sb.pcr SrcL, [symbol]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000069ULL, .field_start = 1554, .field_count = 2 },
+  { .id = "sbi_32_f3c6b796f0d9", .mnemonic = "SBI", .asm_fmt = "sbi SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000059ULL, .field_start = 1556, .field_count = 3 },
+  { .id = "sc_b_32_baf609e1d5c3", .mnemonic = "SC.B", .asm_fmt = "sc.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000100bULL, .field_start = 1559, .field_count = 6 },
+  { .id = "sc_d_32_2e714149031c", .mnemonic = "SC.D", .asm_fmt = "sc.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000100bULL, .field_start = 1565, .field_count = 6 },
+  { .id = "sc_h_32_108941eabac6", .mnemonic = "SC.H", .asm_fmt = "sc.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000100bULL, .field_start = 1571, .field_count = 6 },
+  { .id = "sc_w_32_14b238f02bfd", .mnemonic = "SC.W", .asm_fmt = "sc.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000100bULL, .field_start = 1577, .field_count = 6 },
+  { .id = "scvtf_32_01861bbd5ef2", .mnemonic = "SCVTF", .asm_fmt = "scvtf.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000606bULL, .field_start = 1583, .field_count = 4 },
+  { .id = "sd_32_9dbc40328653", .mnemonic = "SD", .asm_fmt = "sd SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000003049ULL, .field_start = 1587, .field_count = 4 },
+  { .id = "sd_add_32_2a55ae1228bd", .mnemonic = "SD.ADD", .asm_fmt = "sd.add<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000000000500bULL, .field_start = 1591, .field_count = 4 },
+  { .id = "sd_and_32_71963e1769c2", .mnemonic = "SD.AND", .asm_fmt = "sd.and<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000001000500bULL, .field_start = 1595, .field_count = 4 },
+  { .id = "sd_or_32_2a65eedfae0f", .mnemonic = "SD.OR", .asm_fmt = "sd.or<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000002000500bULL, .field_start = 1599, .field_count = 4 },
+  { .id = "sd_pcr_32_2340e0085413", .mnemonic = "SD.PCR", .asm_fmt = "sd.pcr SrcL, [symbol]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003069ULL, .field_start = 1603, .field_count = 2 },
+  { .id = "sd_smax_32_e59bf90b50c3", .mnemonic = "SD.SMAX", .asm_fmt = "sd.smax<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000004000500bULL, .field_start = 1605, .field_count = 4 },
+  { .id = "sd_smin_32_188d93125032", .mnemonic = "SD.SMIN", .asm_fmt = "sd.smin<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000005000500bULL, .field_start = 1609, .field_count = 4 },
+  { .id = "sd_u_32_1602c58c2031", .mnemonic = "SD.U", .asm_fmt = "sd.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000007049ULL, .field_start = 1613, .field_count = 4 },
+  { .id = "sd_umax_32_89c5ec42be68", .mnemonic = "SD.UMAX", .asm_fmt = "sd.umax<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000006000500bULL, .field_start = 1617, .field_count = 4 },
+  { .id = "sd_umin_32_2388cbb378ac", .mnemonic = "SD.UMIN", .asm_fmt = "sd.umin<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000007000500bULL, .field_start = 1621, .field_count = 4 },
+  { .id = "sd_xor_32_7655ceaf9497", .mnemonic = "SD.XOR", .asm_fmt = "sd.xor<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000003000500bULL, .field_start = 1625, .field_count = 4 },
+  { .id = "sdi_32_fab563230a66", .mnemonic = "SDI", .asm_fmt = "sdi SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003059ULL, .field_start = 1629, .field_count = 3 },
+  { .id = "sdi_u_32_cba5a4a04e7b", .mnemonic = "SDI.U", .asm_fmt = "sdi.u SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007059ULL, .field_start = 1632, .field_count = 3 },
+  { .id = "setc_and_32_90b4e93ef9d4", .mnemonic = "SETC.AND", .asm_fmt = "setc.and SrcL, SrcR<.sw, .uw, .not>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000002065ULL, .field_start = 1635, .field_count = 3 },
+  { .id = "setc_andi_32_32fe61c0559b", .mnemonic = "SETC.ANDI", .asm_fmt = "setc.andi SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002075ULL, .field_start = 1638, .field_count = 3 },
+  { .id = "setc_eq_32_fb06e1dddc5c", .mnemonic = "SETC.EQ", .asm_fmt = "setc.eq SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000000065ULL, .field_start = 1641, .field_count = 3 },
+  { .id = "setc_eqi_32_5b2366a4e55d", .mnemonic = "SETC.EQI", .asm_fmt = "setc.eqi SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000000075ULL, .field_start = 1644, .field_count = 3 },
+  { .id = "setc_ge_32_56a2b539b072", .mnemonic = "SETC.GE", .asm_fmt = "setc.ge SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000005065ULL, .field_start = 1647, .field_count = 3 },
+  { .id = "setc_gei_32_c3f4fdc4adcc", .mnemonic = "SETC.GEI", .asm_fmt = "setc.gei SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005075ULL, .field_start = 1650, .field_count = 3 },
+  { .id = "setc_geu_32_494f1f79099e", .mnemonic = "SETC.GEU", .asm_fmt = "setc.geu SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000007065ULL, .field_start = 1653, .field_count = 3 },
+  { .id = "setc_geui_32_6c34bc4ad314", .mnemonic = "SETC.GEUI", .asm_fmt = "setc.geui SrcL, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000007075ULL, .field_start = 1656, .field_count = 3 },
+  { .id = "setc_lt_32_10de99f3ad6a", .mnemonic = "SETC.LT", .asm_fmt = "setc.lt SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000004065ULL, .field_start = 1659, .field_count = 3 },
+  { .id = "setc_lti_32_89d74d948b74", .mnemonic = "SETC.LTI", .asm_fmt = "setc.lti SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004075ULL, .field_start = 1662, .field_count = 3 },
+  { .id = "setc_ltu_32_4a1ff65ecafb", .mnemonic = "SETC.LTU", .asm_fmt = "setc.ltu SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000006065ULL, .field_start = 1665, .field_count = 3 },
+  { .id = "setc_ltui_32_7908d25901c6", .mnemonic = "SETC.LTUI", .asm_fmt = "setc.ltui SrcL, uimm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006075ULL, .field_start = 1668, .field_count = 3 },
+  { .id = "setc_ne_32_77576a5c690c", .mnemonic = "SETC.NE", .asm_fmt = "setc.ne SrcL, SrcR<{.sw, .uw}>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000001065ULL, .field_start = 1671, .field_count = 3 },
+  { .id = "setc_nei_32_fa01e973ab76", .mnemonic = "SETC.NEI", .asm_fmt = "setc.nei SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001075ULL, .field_start = 1674, .field_count = 3 },
+  { .id = "setc_or_32_740134c709d2", .mnemonic = "SETC.OR", .asm_fmt = "setc.or SrcL, SrcR<.sw, .uw, .not>", .length_bits = 32, .mask = 0x00000000f8007fffULL, .match = 0x0000000000003065ULL, .field_start = 1677, .field_count = 3 },
+  { .id = "setc_ori_32_183dc15fad54", .mnemonic = "SETC.ORI", .asm_fmt = "setc.ori SrcL, simm", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000003075ULL, .field_start = 1680, .field_count = 3 },
+  { .id = "setc_tgt_32_c02656d3a2b8", .mnemonic = "SETC.TGT", .asm_fmt = "setc.tgt SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000000403bULL, .field_start = 1683, .field_count = 1 },
+  { .id = "setret_32_72003dcf3b59", .mnemonic = "SETRET", .asm_fmt = "setret uimm, ->Ra", .length_bits = 32, .mask = 0x0000000000000fffULL, .match = 0x0000000000000507ULL, .field_start = 1684, .field_count = 1 },
+  { .id = "sh_32_bc7d4a7dea28", .mnemonic = "SH", .asm_fmt = "sh SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000001049ULL, .field_start = 1685, .field_count = 4 },
+  { .id = "sh_pcr_32_14ba505eb3c2", .mnemonic = "SH.PCR", .asm_fmt = "sh.pcr SrcL, [symbol]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001069ULL, .field_start = 1689, .field_count = 2 },
+  { .id = "sh_u_32_fa87afbf8f24", .mnemonic = "SH.U", .asm_fmt = "sh.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000005049ULL, .field_start = 1691, .field_count = 4 },
+  { .id = "shi_32_21351c202204", .mnemonic = "SHI", .asm_fmt = "shi SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001059ULL, .field_start = 1695, .field_count = 3 },
+  { .id = "shi_u_32_caaf3ed72a8f", .mnemonic = "SHI.U", .asm_fmt = "shi.u SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000005059ULL, .field_start = 1698, .field_count = 3 },
+  { .id = "sll_32_a100b8961e21", .mnemonic = "SLL", .asm_fmt = "sll SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000007005ULL, .field_start = 1701, .field_count = 3 },
+  { .id = "slli_32_b43ca2454e3a", .mnemonic = "SLLI", .asm_fmt = "slli SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fc00707fULL, .match = 0x0000000000007015ULL, .field_start = 1704, .field_count = 3 },
+  { .id = "slliw_32_c6bf463b97ae", .mnemonic = "SLLIW", .asm_fmt = "slliw SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000007035ULL, .field_start = 1707, .field_count = 3 },
+  { .id = "sllw_32_a37b63c16b27", .mnemonic = "SLLW", .asm_fmt = "sllw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000007025ULL, .field_start = 1710, .field_count = 3 },
+  { .id = "sra_32_ba03eea6386b", .mnemonic = "SRA", .asm_fmt = "sra SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000006005ULL, .field_start = 1713, .field_count = 3 },
+  { .id = "srai_32_e471ea84d4fd", .mnemonic = "SRAI", .asm_fmt = "srai SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fc00707fULL, .match = 0x0000000000006015ULL, .field_start = 1716, .field_count = 3 },
+  { .id = "sraiw_32_db04a6299504", .mnemonic = "SRAIW", .asm_fmt = "sraiw SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000006035ULL, .field_start = 1719, .field_count = 3 },
+  { .id = "sraw_32_5baf37f34241", .mnemonic = "SRAW", .asm_fmt = "sraw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000006025ULL, .field_start = 1722, .field_count = 3 },
+  { .id = "srl_32_5cfca42c59f3", .mnemonic = "SRL", .asm_fmt = "srl SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000005005ULL, .field_start = 1725, .field_count = 3 },
+  { .id = "srli_32_dd29ca058cfe", .mnemonic = "SRLI", .asm_fmt = "srli SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fc00707fULL, .match = 0x0000000000005015ULL, .field_start = 1728, .field_count = 3 },
+  { .id = "srliw_32_ef4aa650f46e", .mnemonic = "SRLIW", .asm_fmt = "srliw SrcL, shamt, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000005035ULL, .field_start = 1731, .field_count = 3 },
+  { .id = "srlw_32_2c6458b2aadb", .mnemonic = "SRLW", .asm_fmt = "srlw SrcL, SrcR, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000fe00707fULL, .match = 0x0000000000005025ULL, .field_start = 1734, .field_count = 3 },
+  { .id = "ssrget_32_959957ab6b75", .mnemonic = "SSRGET", .asm_fmt = "ssrget SSR_ID, ->{t, u, Rd}", .length_bits = 32, .mask = 0x00000000000ff07fULL, .match = 0x000000000000003bULL, .field_start = 1737, .field_count = 2 },
+  { .id = "ssrset_32_4dd3b71802c6", .mnemonic = "SSRSET", .asm_fmt = "ssrset SrcL, SSR_ID", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x000000000000103bULL, .field_start = 1739, .field_count = 2 },
+  { .id = "ssrswap_32_a01c7e2c7c29", .mnemonic = "SSRSWAP", .asm_fmt = "ssrswap SrcL, SSR_ID, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x000000000000203bULL, .field_start = 1741, .field_count = 3 },
+  { .id = "sub_32_af383d4a2b42", .mnemonic = "SUB", .asm_fmt = "sub SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001005ULL, .field_start = 1744, .field_count = 5 },
+  { .id = "subi_32_a0c87f5e7ac4", .mnemonic = "SUBI", .asm_fmt = "subi SrcL, uimm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001015ULL, .field_start = 1749, .field_count = 3 },
+  { .id = "subiw_32_51019ff77d0a", .mnemonic = "SUBIW", .asm_fmt = "subiw SrcL, uimm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001035ULL, .field_start = 1752, .field_count = 3 },
+  { .id = "subw_32_3a8d45653c98", .mnemonic = "SUBW", .asm_fmt = "subw SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000001025ULL, .field_start = 1755, .field_count = 5 },
+  { .id = "sw_32_28ad317b1b41", .mnemonic = "SW", .asm_fmt = "sw SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000002049ULL, .field_start = 1760, .field_count = 4 },
+  { .id = "sw_add_32_3dca755552cb", .mnemonic = "SW.ADD", .asm_fmt = "sw.add<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000000000300bULL, .field_start = 1764, .field_count = 4 },
+  { .id = "sw_and_32_7ef0872d5502", .mnemonic = "SW.AND", .asm_fmt = "sw.and<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000001000300bULL, .field_start = 1768, .field_count = 4 },
+  { .id = "sw_or_32_354579538c4e", .mnemonic = "SW.OR", .asm_fmt = "sw.or<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000002000300bULL, .field_start = 1772, .field_count = 4 },
+  { .id = "sw_pcr_32_436677679523", .mnemonic = "SW.PCR", .asm_fmt = "sw.pcr SrcL, [symbol]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002069ULL, .field_start = 1776, .field_count = 2 },
+  { .id = "sw_smax_32_8bab38a878d7", .mnemonic = "SW.SMAX", .asm_fmt = "sw.smax<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000004000300bULL, .field_start = 1778, .field_count = 4 },
+  { .id = "sw_smin_32_773e7d83b011", .mnemonic = "SW.SMIN", .asm_fmt = "sw.smin<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000005000300bULL, .field_start = 1782, .field_count = 4 },
+  { .id = "sw_u_32_718a61f75d33", .mnemonic = "SW.U", .asm_fmt = "sw.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>]", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000006049ULL, .field_start = 1786, .field_count = 4 },
+  { .id = "sw_umax_32_5530dfa23323", .mnemonic = "SW.UMAX", .asm_fmt = "sw.umax<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000006000300bULL, .field_start = 1790, .field_count = 4 },
+  { .id = "sw_umin_32_3ce114819cfc", .mnemonic = "SW.UMIN", .asm_fmt = "sw.umin<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000007000300bULL, .field_start = 1794, .field_count = 4 },
+  { .id = "sw_xor_32_874c32572226", .mnemonic = "SW.XOR", .asm_fmt = "sw.xor<.{rl, f, rlf}> [SrcL], SrcR", .length_bits = 32, .mask = 0x00000000f4007fffULL, .match = 0x000000003000300bULL, .field_start = 1798, .field_count = 4 },
+  { .id = "swapb_32_80733f03b77f", .mnemonic = "SWAPB", .asm_fmt = "swapb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000000000600bULL, .field_start = 1802, .field_count = 6 },
+  { .id = "swapd_32_cd31ccde2303", .mnemonic = "SWAPD", .asm_fmt = "swapd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000003000600bULL, .field_start = 1808, .field_count = 6 },
+  { .id = "swaph_32_8c2d4a28bf25", .mnemonic = "SWAPH", .asm_fmt = "swaph<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000001000600bULL, .field_start = 1814, .field_count = 6 },
+  { .id = "swapw_32_ef15c3ebac33", .mnemonic = "SWAPW", .asm_fmt = "swapw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd}", .length_bits = 32, .mask = 0x00000000f000707fULL, .match = 0x000000002000600bULL, .field_start = 1820, .field_count = 6 },
+  { .id = "swi_32_147e55489c41", .mnemonic = "SWI", .asm_fmt = "swi SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000002059ULL, .field_start = 1826, .field_count = 3 },
+  { .id = "swi_u_32_1630e926da1a", .mnemonic = "SWI.U", .asm_fmt = "swi.u SrcL, [SrcR, simm]", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000006059ULL, .field_start = 1829, .field_count = 3 },
+  { .id = "tlb_ia_32_e794d6bf347e", .mnemonic = "TLB.IA", .asm_fmt = "tlb.ia SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000000702bULL, .field_start = 1832, .field_count = 1 },
+  { .id = "tlb_iall_32_0fb421b85c88", .mnemonic = "TLB.IALL", .asm_fmt = "tlb.iall", .length_bits = 32, .mask = 0x00000000ffffffffULL, .match = 0x000000000030702bULL, .field_start = 1833, .field_count = 0 },
+  { .id = "tlb_iav_32_95f4937d2917", .mnemonic = "TLB.IAV", .asm_fmt = "tlb.iav SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000020702bULL, .field_start = 1833, .field_count = 1 },
+  { .id = "tlb_iv_32_bf0a5d1ea211", .mnemonic = "TLB.IV", .asm_fmt = "tlb.iv SrcL", .length_bits = 32, .mask = 0x00000000fff07fffULL, .match = 0x000000000010702bULL, .field_start = 1834, .field_count = 1 },
+  { .id = "ucvtf_32_987f4e019c32", .mnemonic = "UCVTF", .asm_fmt = "ucvtf.{srcT2dstT} SrcL, ->{t, u, Rd}", .length_bits = 32, .mask = 0x0000000001f0707fULL, .match = 0x000000000000706bULL, .field_start = 1835, .field_count = 4 },
+  { .id = "v_add_64_394294cc5946", .mnemonic = "V.ADD", .asm_fmt = "v.add SrcL, SrcR<.neg><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000000050000007fULL, .field_start = 1839, .field_count = 5 },
+  { .id = "v_addi_64_2b2209683a13", .mnemonic = "V.ADDI", .asm_fmt = "v.addi SrcL, uimm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000000150000007fULL, .field_start = 1844, .field_count = 3 },
+  { .id = "v_and_64_1ecd348ef07b", .mnemonic = "V.AND", .asm_fmt = "v.and SrcL, SrcR<.not><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000020050000007fULL, .field_start = 1847, .field_count = 5 },
+  { .id = "v_andi_64_169f397546d5", .mnemonic = "V.ANDI", .asm_fmt = "v.andi SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000020150000007fULL, .field_start = 1852, .field_count = 3 },
+  { .id = "v_bcnt_64_42c09bd34fa3", .mnemonic = "V.BCNT", .asm_fmt = "v.bcnt SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000060670000007fULL, .field_start = 1855, .field_count = 4 },
+  { .id = "v_bic_64_e87942a9adfa", .mnemonic = "V.BIC", .asm_fmt = "v.bic SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000020670000007fULL, .field_start = 1859, .field_count = 4 },
+  { .id = "v_bis_64_cefe4375764b", .mnemonic = "V.BIS", .asm_fmt = "v.bis SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000030670000007fULL, .field_start = 1863, .field_count = 4 },
+  { .id = "v_bxs_64_6227f276c17d", .mnemonic = "V.BXS", .asm_fmt = "v.bxs SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000000670000007fULL, .field_start = 1867, .field_count = 4 },
+  { .id = "v_bxu_64_c8bf73694717", .mnemonic = "V.BXU", .asm_fmt = "v.bxu SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000010670000007fULL, .field_start = 1871, .field_count = 4 },
+  { .id = "v_clz_64_193df5d3df15", .mnemonic = "V.CLZ", .asm_fmt = "v.clz SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000050670000007fULL, .field_start = 1875, .field_count = 4 },
+  { .id = "v_cmp_and_64_5b3efc0f7b0a", .mnemonic = "V.CMP.AND", .asm_fmt = "v.cmp.and SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000020450000007fULL, .field_start = 1879, .field_count = 3 },
+  { .id = "v_cmp_andi_64_84769d4e8fa2", .mnemonic = "V.CMP.ANDI", .asm_fmt = "v.cmp.andi SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000020550000007fULL, .field_start = 1882, .field_count = 3 },
+  { .id = "v_cmp_eq_64_81fb556b62ca", .mnemonic = "V.CMP.EQ", .asm_fmt = "v.cmp.eq SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000000450000007fULL, .field_start = 1885, .field_count = 3 },
+  { .id = "v_cmp_eqi_64_e6769858459e", .mnemonic = "V.CMP.EQI", .asm_fmt = "v.cmp.eqi SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000000550000007fULL, .field_start = 1888, .field_count = 3 },
+  { .id = "v_cmp_ge_64_77301f1e67a9", .mnemonic = "V.CMP.GE", .asm_fmt = "v.cmp.ge SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000050450000007fULL, .field_start = 1891, .field_count = 3 },
+  { .id = "v_cmp_gei_64_f226c4f0d640", .mnemonic = "V.CMP.GEI", .asm_fmt = "v.cmp.gei SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000050550000007fULL, .field_start = 1894, .field_count = 3 },
+  { .id = "v_cmp_geu_64_5f66721154a8", .mnemonic = "V.CMP.GEU", .asm_fmt = "v.cmp.geu SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000070450000007fULL, .field_start = 1897, .field_count = 3 },
+  { .id = "v_cmp_geui_64_ae111c2828e9", .mnemonic = "V.CMP.GEUI", .asm_fmt = "v.cmp.geui SrcL, uimm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000070550000007fULL, .field_start = 1900, .field_count = 3 },
+  { .id = "v_cmp_lt_64_3ef2162a77ba", .mnemonic = "V.CMP.LT", .asm_fmt = "v.cmp.lt SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000040450000007fULL, .field_start = 1903, .field_count = 3 },
+  { .id = "v_cmp_lti_64_75af9c62bdfe", .mnemonic = "V.CMP.LTI", .asm_fmt = "v.cmp.lti SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000040550000007fULL, .field_start = 1906, .field_count = 3 },
+  { .id = "v_cmp_ltu_64_48ae80b99c15", .mnemonic = "V.CMP.LTU", .asm_fmt = "v.cmp.ltu SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000060450000007fULL, .field_start = 1909, .field_count = 3 },
+  { .id = "v_cmp_ltui_64_d1b1db22be04", .mnemonic = "V.CMP.LTUI", .asm_fmt = "v.cmp.ltui SrcL, uimm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000060550000007fULL, .field_start = 1912, .field_count = 3 },
+  { .id = "v_cmp_ne_64_84c9e143b8b1", .mnemonic = "V.CMP.NE", .asm_fmt = "v.cmp.ne SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000010450000007fULL, .field_start = 1915, .field_count = 3 },
+  { .id = "v_cmp_nei_64_56b66e30a15d", .mnemonic = "V.CMP.NEI", .asm_fmt = "v.cmp.nei SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000010550000007fULL, .field_start = 1918, .field_count = 3 },
+  { .id = "v_cmp_or_64_c3444f939f6f", .mnemonic = "V.CMP.OR", .asm_fmt = "v.cmp.or SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000030450000007fULL, .field_start = 1921, .field_count = 3 },
+  { .id = "v_cmp_ori_64_2e06ef6e16e7", .mnemonic = "V.CMP.ORI", .asm_fmt = "v.cmp.ori SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000030550000007fULL, .field_start = 1924, .field_count = 3 },
+  { .id = "v_csel_64_791e57f8ff22", .mnemonic = "V.CSEL", .asm_fmt = "v.csel SrcP, SrcL, SrcR<.neg>, ->Dst", .length_bits = 64, .mask = 0x0000707f0600707fULL, .match = 0x000000770000007fULL, .field_start = 1927, .field_count = 5 },
+  { .id = "v_ctz_64_7be9efa90a00", .mnemonic = "V.CTZ", .asm_fmt = "v.ctz SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000040670000007fULL, .field_start = 1932, .field_count = 4 },
+  { .id = "v_div_64_74152b35b49c", .mnemonic = "V.DIV", .asm_fmt = "v.div SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000000570000007fULL, .field_start = 1936, .field_count = 3 },
+  { .id = "v_fabs_64_cd9c01ef8cc4", .mnemonic = "V.FABS", .asm_fmt = "v.fabs SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000007b0000007fULL, .field_start = 1939, .field_count = 2 },
+  { .id = "v_fadd_64_c5c08b2ac830", .mnemonic = "V.FADD", .asm_fmt = "v.fadd SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000004b0000007fULL, .field_start = 1941, .field_count = 3 },
+  { .id = "v_fclass_64_628ee3eaf4ba", .mnemonic = "V.FCLASS", .asm_fmt = "v.fclass SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000707b0000007fULL, .field_start = 1944, .field_count = 2 },
+  { .id = "v_fcvt_64_da9f59421cae", .mnemonic = "V.FCVT", .asm_fmt = "v.fcvt.{st2dt} SrcL, ->Dst", .length_bits = 64, .mask = 0x0600707ffff0707fULL, .match = 0x0000006b0000007fULL, .field_start = 1946, .field_count = 4 },
+  { .id = "v_fcvti_64_00dd1644b48d", .mnemonic = "V.FCVTI", .asm_fmt = "v.fcvti.{st2dt} SrcL, ->Dst", .length_bits = 64, .mask = 0x0600707ffff0707fULL, .match = 0x0000106b0000007fULL, .field_start = 1950, .field_count = 4 },
+  { .id = "v_fdiv_64_0e6eb42a8167", .mnemonic = "V.FDIV", .asm_fmt = "v.fdiv SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000304b0000007fULL, .field_start = 1954, .field_count = 3 },
+  { .id = "v_feq_64_310fa4a0c71c", .mnemonic = "V.FEQ", .asm_fmt = "v.feq SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000005b0000007fULL, .field_start = 1957, .field_count = 3 },
+  { .id = "v_feqs_64_fa03903879d5", .mnemonic = "V.FEQS", .asm_fmt = "v.feqs SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000405b0000007fULL, .field_start = 1960, .field_count = 3 },
+  { .id = "v_fexp_64_9fb55afd6ae9", .mnemonic = "V.FEXP", .asm_fmt = "v.fexp SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000307b0000007fULL, .field_start = 1963, .field_count = 2 },
+  { .id = "v_fge_64_6472fe8862ea", .mnemonic = "V.FGE", .asm_fmt = "v.fge SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000305b0000007fULL, .field_start = 1965, .field_count = 3 },
+  { .id = "v_fges_64_6cad59141271", .mnemonic = "V.FGES", .asm_fmt = "v.fges SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000705b0000007fULL, .field_start = 1968, .field_count = 3 },
+  { .id = "v_flt_64_1f2a82b04cd1", .mnemonic = "V.FLT", .asm_fmt = "v.flt SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000205b0000007fULL, .field_start = 1971, .field_count = 3 },
+  { .id = "v_flts_64_d39b1c33de29", .mnemonic = "V.FLTS", .asm_fmt = "v.flts SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000605b0000007fULL, .field_start = 1974, .field_count = 3 },
+  { .id = "v_fmadd_64_813d061de8ca", .mnemonic = "V.FMADD", .asm_fmt = "v.fmadd SrcL, SrcR, SrcA, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000404b0000007fULL, .field_start = 1977, .field_count = 4 },
+  { .id = "v_fmax_64_b170fb3ede0f", .mnemonic = "V.FMAX", .asm_fmt = "v.fmax SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000205b0000107fULL, .field_start = 1981, .field_count = 3 },
+  { .id = "v_fmin_64_86ba368048a2", .mnemonic = "V.FMIN", .asm_fmt = "v.fmin SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000305b0000107fULL, .field_start = 1984, .field_count = 3 },
+  { .id = "v_fmsub_64_19c6d15b8a1d", .mnemonic = "V.FMSUB", .asm_fmt = "v.fmsub SrcL, SrcR, SrcA, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000504b0000007fULL, .field_start = 1987, .field_count = 4 },
+  { .id = "v_fmul_64_3e2b1576cbfe", .mnemonic = "V.FMUL", .asm_fmt = "v.fmul SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000204b0000007fULL, .field_start = 1991, .field_count = 3 },
+  { .id = "v_fne_64_10a12315c34e", .mnemonic = "V.FNE", .asm_fmt = "v.fne SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000105b0000007fULL, .field_start = 1994, .field_count = 3 },
+  { .id = "v_fnes_64_ae92608cb0ea", .mnemonic = "V.FNES", .asm_fmt = "v.fnes SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000505b0000007fULL, .field_start = 1997, .field_count = 3 },
+  { .id = "v_fnmadd_64_81449b1d3451", .mnemonic = "V.FNMADD", .asm_fmt = "v.fnmadd SrcL, SrcR, SrcA, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000604b0000007fULL, .field_start = 2000, .field_count = 4 },
+  { .id = "v_fnmsub_64_837584633904", .mnemonic = "V.FNMSUB", .asm_fmt = "v.fnmsub SrcL, SrcR, SrcA, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000704b0000007fULL, .field_start = 2004, .field_count = 4 },
+  { .id = "v_frecip_64_2d3f96b8d7db", .mnemonic = "V.FRECIP", .asm_fmt = "v.frecip SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000207b0000007fULL, .field_start = 2008, .field_count = 2 },
+  { .id = "v_fsqrt_64_80e65f8380da", .mnemonic = "V.FSQRT", .asm_fmt = "v.fsqrt SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000107b0000007fULL, .field_start = 2010, .field_count = 2 },
+  { .id = "v_fsub_64_09953704a14a", .mnemonic = "V.FSUB", .asm_fmt = "v.fsub SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000104b0000007fULL, .field_start = 2012, .field_count = 3 },
+  { .id = "v_icvt_64_c8fd1bad81c1", .mnemonic = "V.ICVT", .asm_fmt = "v.icvt.{st2dt} SrcL, ->Dst", .length_bits = 64, .mask = 0x0600707ffff0707fULL, .match = 0x0000606b0000007fULL, .field_start = 2015, .field_count = 4 },
+  { .id = "v_icvtf_64_a0f027af74bd", .mnemonic = "V.ICVTF", .asm_fmt = "v.icvtf.{st2dt} SrcL, ->Dst", .length_bits = 64, .mask = 0x0600707ffff0707fULL, .match = 0x0000706b0000007fULL, .field_start = 2019, .field_count = 4 },
+  { .id = "v_lb_64_67d7ec296657", .mnemonic = "V.LB", .asm_fmt = "v.lb<.local> [SrcL, <lc0>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000000090000007fULL, .field_start = 2023, .field_count = 6 },
+  { .id = "v_lb_brg_64_8766090710da", .mnemonic = "V.LB.BRG", .asm_fmt = "v.lb.brg<.local> [SrcL,  <lc0>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000000090000207fULL, .field_start = 2029, .field_count = 6 },
+  { .id = "v_lbi_64_5338c0a4b01c", .mnemonic = "V.LBI", .asm_fmt = "v.lbi<.local> [SrcL, <lc0>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000000190000007fULL, .field_start = 2035, .field_count = 5 },
+  { .id = "v_lbi_brg_64_5223a985d13b", .mnemonic = "V.LBI.BRG", .asm_fmt = "v.lbi.brg<.local> [SrcL, <lc0>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000000190000207fULL, .field_start = 2040, .field_count = 5 },
+  { .id = "v_lbu_64_08cfacc47e8b", .mnemonic = "V.LBU", .asm_fmt = "v.lbu<.local> [SrcL, <lc0>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000040090000007fULL, .field_start = 2045, .field_count = 6 },
+  { .id = "v_lbu_brg_64_8981c96ac2c4", .mnemonic = "V.LBU.BRG", .asm_fmt = "v.lbu.brg<.local> [SrcL, <lc0>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000040090000207fULL, .field_start = 2051, .field_count = 6 },
+  { .id = "v_lbui_64_129c6d28d8fa", .mnemonic = "V.LBUI", .asm_fmt = "v.lbui<.local> [SrcL, <lc0>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000040190000007fULL, .field_start = 2057, .field_count = 5 },
+  { .id = "v_lbui_brg_64_0d4264b0b4fe", .mnemonic = "V.LBUI.BRG", .asm_fmt = "v.lbui.brg<.local> [SrcL, <lc0>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000040190000207fULL, .field_start = 2062, .field_count = 5 },
+  { .id = "v_ld_64_0bb4e0cd9760", .mnemonic = "V.LD", .asm_fmt = "v.ld<.local> [SrcL, <lc0<<3>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000030090000007fULL, .field_start = 2067, .field_count = 6 },
+  { .id = "v_ld_add_64_b880252ca4af", .mnemonic = "V.LD.ADD", .asm_fmt = "v.ld.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000000b0000207fULL, .field_start = 2073, .field_count = 6 },
+  { .id = "v_ld_and_64_18248e48be84", .mnemonic = "V.LD.AND", .asm_fmt = "v.ld.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000100b0000207fULL, .field_start = 2079, .field_count = 6 },
+  { .id = "v_ld_brg_64_44d932c2c42b", .mnemonic = "V.LD.BRG", .asm_fmt = "v.ld.brg<.local> [SrcL,  <lc0<<3>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000030090000207fULL, .field_start = 2085, .field_count = 6 },
+  { .id = "v_ld_max_64_e35d8e7957c3", .mnemonic = "V.LD.MAX", .asm_fmt = "v.ld.max<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000400b0000207fULL, .field_start = 2091, .field_count = 6 },
+  { .id = "v_ld_min_64_71f54b9b61ae", .mnemonic = "V.LD.MIN", .asm_fmt = "v.ld.min<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000500b0000207fULL, .field_start = 2097, .field_count = 6 },
+  { .id = "v_ld_or_64_4568b99c9e57", .mnemonic = "V.LD.OR", .asm_fmt = "v.ld.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000200b0000207fULL, .field_start = 2103, .field_count = 6 },
+  { .id = "v_ld_xor_64_c7a54911a5fa", .mnemonic = "V.LD.XOR", .asm_fmt = "v.ld.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000300b0000207fULL, .field_start = 2109, .field_count = 6 },
+  { .id = "v_ldi_64_c2dd6f17ebd3", .mnemonic = "V.LDI", .asm_fmt = "v.ldi<.local> [SrcL, <lc0<<3>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030190000007fULL, .field_start = 2115, .field_count = 5 },
+  { .id = "v_ldi_brg_64_1696b123572b", .mnemonic = "V.LDI.BRG", .asm_fmt = "v.ldi.brg<.local> [SrcL, <lc0<<3>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030190000207fULL, .field_start = 2120, .field_count = 5 },
+  { .id = "v_ldi_u_64_35ef4d60d802", .mnemonic = "V.LDI.U", .asm_fmt = "v.ldi.u<.local> [SrcL, <lc0<<3>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030290000007fULL, .field_start = 2125, .field_count = 5 },
+  { .id = "v_ldi_u_brg_64_d8020ef56426", .mnemonic = "V.LDI.U.BRG", .asm_fmt = "v.ldi.u.brg<.local> [SrcL, <lc0<<3>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030290000207fULL, .field_start = 2130, .field_count = 5 },
+  { .id = "v_lh_64_4cc8701b698e", .mnemonic = "V.LH", .asm_fmt = "v.lh<.local> [SrcL, <lc0<<1>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000010090000007fULL, .field_start = 2135, .field_count = 6 },
+  { .id = "v_lh_brg_64_dc8629a69767", .mnemonic = "V.LH.BRG", .asm_fmt = "v.lh.brg<.local> [SrcL,  <lc0<<1>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000010090000207fULL, .field_start = 2141, .field_count = 6 },
+  { .id = "v_lhi_64_66ae52eb7684", .mnemonic = "V.LHI", .asm_fmt = "v.lhi<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010190000007fULL, .field_start = 2147, .field_count = 5 },
+  { .id = "v_lhi_brg_64_d3af43d94f66", .mnemonic = "V.LHI.BRG", .asm_fmt = "v.lhi.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010190000207fULL, .field_start = 2152, .field_count = 5 },
+  { .id = "v_lhi_u_64_17c014a96651", .mnemonic = "V.LHI.U", .asm_fmt = "v.lhi.u<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010290000007fULL, .field_start = 2157, .field_count = 5 },
+  { .id = "v_lhi_u_brg_64_97603a7ac88f", .mnemonic = "V.LHI.U.BRG", .asm_fmt = "v.lhi.u.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010290000207fULL, .field_start = 2162, .field_count = 5 },
+  { .id = "v_lhu_64_83e59201d9ae", .mnemonic = "V.LHU", .asm_fmt = "v.lhu<.local> [SrcL, <lc0<<1>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000050090000007fULL, .field_start = 2167, .field_count = 6 },
+  { .id = "v_lhu_brg_64_5e9d77a562d0", .mnemonic = "V.LHU.BRG", .asm_fmt = "v.lhu.brg<.local> [SrcL,  <lc0<<1>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000050090000207fULL, .field_start = 2173, .field_count = 6 },
+  { .id = "v_lhui_64_0d3046ae3eb8", .mnemonic = "V.LHUI", .asm_fmt = "v.lhui<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050190000007fULL, .field_start = 2179, .field_count = 5 },
+  { .id = "v_lhui_brg_64_e3dba0cc2fea", .mnemonic = "V.LHUI.BRG", .asm_fmt = "v.lhui.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050190000207fULL, .field_start = 2184, .field_count = 5 },
+  { .id = "v_lhui_u_64_85625cdca25f", .mnemonic = "V.LHUI.U", .asm_fmt = "v.lhui.u<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050290000007fULL, .field_start = 2189, .field_count = 5 },
+  { .id = "v_lhui_u_brg_64_3d2e899ff00f", .mnemonic = "V.LHUI.U.BRG", .asm_fmt = "v.lhui.u.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050290000207fULL, .field_start = 2194, .field_count = 5 },
+  { .id = "v_lw_64_5a07f2297805", .mnemonic = "V.LW", .asm_fmt = "v.lw<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000020090000007fULL, .field_start = 2199, .field_count = 6 },
+  { .id = "v_lw_add_64_d603802b2bed", .mnemonic = "V.LW.ADD", .asm_fmt = "v.lw.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000000b0000007fULL, .field_start = 2205, .field_count = 6 },
+  { .id = "v_lw_and_64_c511f6c6aad9", .mnemonic = "V.LW.AND", .asm_fmt = "v.lw.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000100b0000007fULL, .field_start = 2211, .field_count = 6 },
+  { .id = "v_lw_brg_64_6163b7a621fc", .mnemonic = "V.LW.BRG", .asm_fmt = "v.lw.brg<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000020090000207fULL, .field_start = 2217, .field_count = 6 },
+  { .id = "v_lw_max_64_c7e26075c749", .mnemonic = "V.LW.MAX", .asm_fmt = "v.lw.max<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000400b0000007fULL, .field_start = 2223, .field_count = 6 },
+  { .id = "v_lw_min_64_24160fd76a35", .mnemonic = "V.LW.MIN", .asm_fmt = "v.lw.min<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000500b0000007fULL, .field_start = 2229, .field_count = 6 },
+  { .id = "v_lw_or_64_baf9868390da", .mnemonic = "V.LW.OR", .asm_fmt = "v.lw.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000200b0000007fULL, .field_start = 2235, .field_count = 6 },
+  { .id = "v_lw_xor_64_a520a467a6d4", .mnemonic = "V.LW.XOR", .asm_fmt = "v.lw.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst", .length_bits = 64, .mask = 0xf800707ffc00707fULL, .match = 0x0000300b0000007fULL, .field_start = 2241, .field_count = 6 },
+  { .id = "v_lwi_64_4170735058bc", .mnemonic = "V.LWI", .asm_fmt = "v.lwi<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020190000007fULL, .field_start = 2247, .field_count = 5 },
+  { .id = "v_lwi_brg_64_3932bb713dc5", .mnemonic = "V.LWI.BRG", .asm_fmt = "v.lwi.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020190000207fULL, .field_start = 2252, .field_count = 5 },
+  { .id = "v_lwi_u_64_d1beea8b7141", .mnemonic = "V.LWI.U", .asm_fmt = "v.lwi.u<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020290000007fULL, .field_start = 2257, .field_count = 5 },
+  { .id = "v_lwi_u_brg_64_b45d0f75f04f", .mnemonic = "V.LWI.U.BRG", .asm_fmt = "v.lwi.u.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020290000207fULL, .field_start = 2262, .field_count = 5 },
+  { .id = "v_lwu_64_aa72372808ed", .mnemonic = "V.LWU", .asm_fmt = "v.lwu<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000060090000007fULL, .field_start = 2267, .field_count = 6 },
+  { .id = "v_lwu_brg_64_c457e812a9a5", .mnemonic = "V.LWU.BRG", .asm_fmt = "v.lwu.brg<.local> [SrcL,  <lc0<<2>, SrcR<<<shamt>], ->Dst", .length_bits = 64, .mask = 0x0600707ffe00207fULL, .match = 0x000060090000207fULL, .field_start = 2273, .field_count = 6 },
+  { .id = "v_lwui_64_f96d1ab639ad", .mnemonic = "V.LWUI", .asm_fmt = "v.lwui<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060190000007fULL, .field_start = 2279, .field_count = 5 },
+  { .id = "v_lwui_brg_64_340c2e2b1ddb", .mnemonic = "V.LWUI.BRG", .asm_fmt = "v.lwui.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060190000207fULL, .field_start = 2284, .field_count = 5 },
+  { .id = "v_lwui_u_64_88aa7700d8b1", .mnemonic = "V.LWUI.U", .asm_fmt = "v.lwui.u<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060290000007fULL, .field_start = 2289, .field_count = 5 },
+  { .id = "v_lwui_u_brg_64_2b7c4722c62c", .mnemonic = "V.LWUI.U.BRG", .asm_fmt = "v.lwui.u.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060290000207fULL, .field_start = 2294, .field_count = 5 },
+  { .id = "v_madd_64_2f35316993e7", .mnemonic = "V.MADD", .asm_fmt = "v.madd SrcL, SrcR, SrcD, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x000060470000007fULL, .field_start = 2299, .field_count = 4 },
+  { .id = "v_max_64_55094376ca8f", .mnemonic = "V.MAX", .asm_fmt = "v.max SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000005b0000107fULL, .field_start = 2303, .field_count = 3 },
+  { .id = "v_min_64_12f02fa489a3", .mnemonic = "V.MIN", .asm_fmt = "v.min SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000105b0000107fULL, .field_start = 2306, .field_count = 3 },
+  { .id = "v_mul_64_06ac4ba10daf", .mnemonic = "V.MUL", .asm_fmt = "v.mul SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000000470000007fULL, .field_start = 2309, .field_count = 3 },
+  { .id = "v_or_64_78638ca1ae6f", .mnemonic = "V.OR", .asm_fmt = "v.or SrcL, SrcR<.not><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000030050000007fULL, .field_start = 2312, .field_count = 5 },
+  { .id = "v_ori_64_291c8721af33", .mnemonic = "V.ORI", .asm_fmt = "v.ori SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000030150000007fULL, .field_start = 2317, .field_count = 3 },
+  { .id = "v_psel_64_81ba051be364", .mnemonic = "V.PSEL", .asm_fmt = "v.psel  SrcP, SrcL, SrcR<.neg>, ->Dst", .length_bits = 64, .mask = 0x0000707f0600707fULL, .match = 0x000010770000007fULL, .field_start = 2320, .field_count = 5 },
+  { .id = "v_qpop_64_7938584b79ed", .mnemonic = "V.QPOP", .asm_fmt = "v.qpop SrcL.ud, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000207d0000007fULL, .field_start = 2325, .field_count = 2 },
+  { .id = "v_qpush_64_b1e840184b4c", .mnemonic = "V.QPUSH", .asm_fmt = "v.qpush SrcL.ud, SrcR.ud, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x0000107d0000007fULL, .field_start = 2327, .field_count = 3 },
+  { .id = "v_rdadd_64_63d092ba608e", .mnemonic = "V.RDADD", .asm_fmt = "v.rdadd SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000000d0000007fULL, .field_start = 2330, .field_count = 2 },
+  { .id = "v_rdand_64_fe7c23ec9e7d", .mnemonic = "V.RDAND", .asm_fmt = "v.rdand SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000100d0000007fULL, .field_start = 2332, .field_count = 2 },
+  { .id = "v_rdfadd_64_bc0fe646d243", .mnemonic = "V.RDFADD", .asm_fmt = "v.rdfadd SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000400d0000007fULL, .field_start = 2334, .field_count = 2 },
+  { .id = "v_rdfmax_64_ca8b0184cd49", .mnemonic = "V.RDFMAX", .asm_fmt = "v.rdfmax SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000200d0000107fULL, .field_start = 2336, .field_count = 2 },
+  { .id = "v_rdfmin_64_f5219d0eca5d", .mnemonic = "V.RDFMIN", .asm_fmt = "v.rdfmin SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000300d0000107fULL, .field_start = 2338, .field_count = 2 },
+  { .id = "v_rdmax_64_97dc8ada3b96", .mnemonic = "V.RDMAX", .asm_fmt = "v.rdmax SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000000d0000107fULL, .field_start = 2340, .field_count = 2 },
+  { .id = "v_rdmin_64_5b3c823f5a19", .mnemonic = "V.RDMIN", .asm_fmt = "v.rdmin SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000100d0000107fULL, .field_start = 2342, .field_count = 2 },
+  { .id = "v_rdor_64_ef5693869e58", .mnemonic = "V.RDOR", .asm_fmt = "v.rdor SrcL,  ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000200d0000007fULL, .field_start = 2344, .field_count = 2 },
+  { .id = "v_rdxor_64_6d27d9e02c62", .mnemonic = "V.RDXOR", .asm_fmt = "v.rdxor SrcL, ->Dst", .length_bits = 64, .mask = 0xfff0707ffff0707fULL, .match = 0x0000300d0000007fULL, .field_start = 2346, .field_count = 2 },
+  { .id = "v_rem_64_b3ed504ae3f4", .mnemonic = "V.REM", .asm_fmt = "v.rem SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000040570000007fULL, .field_start = 2348, .field_count = 3 },
+  { .id = "v_rev_64_3670c780708d", .mnemonic = "V.REV", .asm_fmt = "v.rev SrcL, M, N, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000070670000007fULL, .field_start = 2351, .field_count = 4 },
+  { .id = "v_sb_64_271c7fb69b1d", .mnemonic = "V.SB", .asm_fmt = "v.sb<.local> SrcD.<T1>, [SrcL, <lc0>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000000490000007fULL, .field_start = 2355, .field_count = 6 },
+  { .id = "v_sb_brg_64_e267665cc8e1", .mnemonic = "V.SB.BRG", .asm_fmt = "v.sb.brg<.local> SrcD.<T1>, [SrcL, <lc0>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000000490000207fULL, .field_start = 2361, .field_count = 6 },
+  { .id = "v_sbi_64_7ee65c84adb3", .mnemonic = "V.SBI", .asm_fmt = "v.sbi<.local> SrcL, [SrcR, <lc0>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000000590000007fULL, .field_start = 2367, .field_count = 5 },
+  { .id = "v_sbi_brg_64_2c1623f8e7ec", .mnemonic = "V.SBI.BRG", .asm_fmt = "v.sbi.brg<.local> SrcL, [SrcR, <lc0>,  simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000000590000207fULL, .field_start = 2372, .field_count = 5 },
+  { .id = "v_sd_64_babe74d4ce5e", .mnemonic = "V.SD", .asm_fmt = "v.sd<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<(3+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000030490000007fULL, .field_start = 2377, .field_count = 6 },
+  { .id = "v_sd_add_64_9d01cd1060a2", .mnemonic = "V.SD.ADD", .asm_fmt = "v.sd.add<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000000b0000307fULL, .field_start = 2383, .field_count = 5 },
+  { .id = "v_sd_and_64_bd9bc82be46e", .mnemonic = "V.SD.AND", .asm_fmt = "v.sd.and<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000100b0000307fULL, .field_start = 2388, .field_count = 5 },
+  { .id = "v_sd_brg_64_e63e61e10a94", .mnemonic = "V.SD.BRG", .asm_fmt = "v.sd.brg<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<(3+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000030490000207fULL, .field_start = 2393, .field_count = 6 },
+  { .id = "v_sd_max_64_498ca2576e7c", .mnemonic = "V.SD.MAX", .asm_fmt = "v.sd.max<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000400b0000307fULL, .field_start = 2399, .field_count = 5 },
+  { .id = "v_sd_min_64_0cd2fc3707d5", .mnemonic = "V.SD.MIN", .asm_fmt = "v.sd.min<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000500b0000307fULL, .field_start = 2404, .field_count = 5 },
+  { .id = "v_sd_or_64_67395fafaca6", .mnemonic = "V.SD.OR", .asm_fmt = "v.sd.or<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000200b0000307fULL, .field_start = 2409, .field_count = 5 },
+  { .id = "v_sd_u_64_69b8bc4ab948", .mnemonic = "V.SD.U", .asm_fmt = "v.sd.u<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000070490000007fULL, .field_start = 2414, .field_count = 6 },
+  { .id = "v_sd_u_brg_64_08efd0674013", .mnemonic = "V.SD.U.BRG", .asm_fmt = "v.sd.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000070490000207fULL, .field_start = 2420, .field_count = 6 },
+  { .id = "v_sd_xor_64_8549b91dcf30", .mnemonic = "V.SD.XOR", .asm_fmt = "v.sd.xor<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000300b0000307fULL, .field_start = 2426, .field_count = 5 },
+  { .id = "v_sdi_64_f297b9d43bbe", .mnemonic = "V.SDI", .asm_fmt = "v.sdi<.local> SrcL, [SrcR, <lc0<3>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030590000007fULL, .field_start = 2431, .field_count = 5 },
+  { .id = "v_sdi_brg_64_dccd7436a506", .mnemonic = "V.SDI.BRG", .asm_fmt = "v.sdi.brg<.local> SrcL, [SrcR, <lc0<<3>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000030590000207fULL, .field_start = 2436, .field_count = 5 },
+  { .id = "v_sdi_u_64_b26a79626935", .mnemonic = "V.SDI.U", .asm_fmt = "v.sdi.u<.local> SrcL, [SrcR, <lc0<<3>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000070590000007fULL, .field_start = 2441, .field_count = 5 },
+  { .id = "v_sdi_u_brg_64_0473fe6671f7", .mnemonic = "V.SDI.U.BRG", .asm_fmt = "v.sdi.u.brg<.local> SrcL, [SrcR, <lc0<<3>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000070590000207fULL, .field_start = 2446, .field_count = 5 },
+  { .id = "v_sh_64_06aa6975e679", .mnemonic = "V.SH", .asm_fmt = "v.sh<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<(1+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000010490000007fULL, .field_start = 2451, .field_count = 6 },
+  { .id = "v_sh_brg_64_755523148db8", .mnemonic = "V.SH.BRG", .asm_fmt = "v.sh.brg<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<(1+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000010490000207fULL, .field_start = 2457, .field_count = 6 },
+  { .id = "v_sh_u_64_7944c8319265", .mnemonic = "V.SH.U", .asm_fmt = "v.sh.u<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000050490000007fULL, .field_start = 2463, .field_count = 6 },
+  { .id = "v_sh_u_brg_64_fd1b68d36363", .mnemonic = "V.SH.U.BRG", .asm_fmt = "v.sh.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000050490000207fULL, .field_start = 2469, .field_count = 6 },
+  { .id = "v_shfl_bfly_64_3ebce3493a01", .mnemonic = "V.SHFL.BFLY", .asm_fmt = "v.shfl.bfly SrcL, SrcP, ->Dst", .length_bits = 64, .mask = 0x07f0707f07f0707fULL, .match = 0x0000201d0000007fULL, .field_start = 2475, .field_count = 3 },
+  { .id = "v_shfl_down_64_7b9a1851d32c", .mnemonic = "V.SHFL.DOWN", .asm_fmt = "v.shfl.down SrcL, SrcR, SrcP, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000101d0000007fULL, .field_start = 2478, .field_count = 4 },
+  { .id = "v_shfl_idx_64_f2e31314195c", .mnemonic = "V.SHFL.IDX", .asm_fmt = "v.shfl.idx SrcL, SrcR, SrcP, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000301d0000007fULL, .field_start = 2482, .field_count = 4 },
+  { .id = "v_shfl_up_64_05a2a5b0d9c5", .mnemonic = "V.SHFL.UP", .asm_fmt = "v.shfl.up SrcL, SrcR, SrcP, ->Dst", .length_bits = 64, .mask = 0x0600707f0600707fULL, .match = 0x0000001d0000007fULL, .field_start = 2486, .field_count = 4 },
+  { .id = "v_shfli_bfly_64_6d0ac980b3e9", .mnemonic = "V.SHFLI.BFLY", .asm_fmt = "v.shfli.bfly SrcL, imm, ->Dst", .length_bits = 64, .mask = 0x01f0707f01f0707fULL, .match = 0x0000602d0000007fULL, .field_start = 2490, .field_count = 3 },
+  { .id = "v_shfli_down_64_95a67c6ded00", .mnemonic = "V.SHFLI.DOWN", .asm_fmt = "v.shfli.down SrcL, SrcR, imm, ->Dst", .length_bits = 64, .mask = 0x0000707f0000707fULL, .match = 0x0000502d0000007fULL, .field_start = 2493, .field_count = 4 },
+  { .id = "v_shfli_idx_64_468726b85bf8", .mnemonic = "V.SHFLI.IDX", .asm_fmt = "v.shfli.idx SrcL, SrcR, imm, ->Dst", .length_bits = 64, .mask = 0x0000707f0000707fULL, .match = 0x0000702d0000007fULL, .field_start = 2497, .field_count = 4 },
+  { .id = "v_shfli_up_64_6fa557b5a93d", .mnemonic = "V.SHFLI.UP", .asm_fmt = "v.shfli.up SrcL, SrcR, imm, ->Dst", .length_bits = 64, .mask = 0x0000707f0000707fULL, .match = 0x0000402d0000007fULL, .field_start = 2501, .field_count = 4 },
+  { .id = "v_shi_64_fb4b951ffd01", .mnemonic = "V.SHI", .asm_fmt = "v.shi<.local> SrcL, [SrcR, <lc0<<1>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010590000007fULL, .field_start = 2505, .field_count = 5 },
+  { .id = "v_shi_brg_64_df38ab889894", .mnemonic = "V.SHI.BRG", .asm_fmt = "v.shi.brg<.local> SrcL, [SrcR, <lc0<<1>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000010590000207fULL, .field_start = 2510, .field_count = 5 },
+  { .id = "v_shi_u_64_b6cdb14d38de", .mnemonic = "V.SHI.U", .asm_fmt = "v.shi.u<.local> SrcL, [SrcR, <lc0<<1>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050590000007fULL, .field_start = 2515, .field_count = 5 },
+  { .id = "v_shi_u_brg_64_74e1295ffdda", .mnemonic = "V.SHI.U.BRG", .asm_fmt = "v.shi.u.brg<.local> SrcL, [SrcR, <lc0<<1>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000050590000207fULL, .field_start = 2520, .field_count = 5 },
+  { .id = "v_sll_64_4d67efb816b8", .mnemonic = "V.SLL", .asm_fmt = "v.sll SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000070050000007fULL, .field_start = 2525, .field_count = 3 },
+  { .id = "v_slli_64_1b2532001de6", .mnemonic = "V.SLLI", .asm_fmt = "v.slli SrcL, shamt, ->Dst", .length_bits = 64, .mask = 0xfc00707ffff0707fULL, .match = 0x000070150000007fULL, .field_start = 2528, .field_count = 3 },
+  { .id = "v_sra_64_068f59a0b708", .mnemonic = "V.SRA", .asm_fmt = "v.sra SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000060050000007fULL, .field_start = 2531, .field_count = 3 },
+  { .id = "v_srai_64_cf7be1dfb701", .mnemonic = "V.SRAI", .asm_fmt = "v.srai SrcL, shamt, ->Dst", .length_bits = 64, .mask = 0xfc00707ffff0707fULL, .match = 0x000060150000007fULL, .field_start = 2534, .field_count = 3 },
+  { .id = "v_srl_64_889ad1b7ceb9", .mnemonic = "V.SRL", .asm_fmt = "v.srl SrcL, SrcR, ->Dst", .length_bits = 64, .mask = 0xfe00707ffe00707fULL, .match = 0x000050050000007fULL, .field_start = 2537, .field_count = 3 },
+  { .id = "v_srli_64_cdec0ca1c073", .mnemonic = "V.SRLI", .asm_fmt = "v.srli SrcL, shamt, ->Dst", .length_bits = 64, .mask = 0xfc00707ffff0707fULL, .match = 0x000050150000007fULL, .field_start = 2540, .field_count = 3 },
+  { .id = "v_sub_64_3c88cf0158f8", .mnemonic = "V.SUB", .asm_fmt = "v.sub SrcL, SrcR<.neg><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000010050000007fULL, .field_start = 2543, .field_count = 5 },
+  { .id = "v_subi_64_0226b3e654bf", .mnemonic = "V.SUBI", .asm_fmt = "v.subi SrcL, uimm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000010150000007fULL, .field_start = 2548, .field_count = 3 },
+  { .id = "v_sw_64_47af61b44300", .mnemonic = "V.SW", .asm_fmt = "v.sw<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<(2+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000020490000007fULL, .field_start = 2551, .field_count = 6 },
+  { .id = "v_sw_add_64_559073c4e3f7", .mnemonic = "V.SW.ADD", .asm_fmt = "v.sw.add<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000000b0000107fULL, .field_start = 2557, .field_count = 5 },
+  { .id = "v_sw_and_64_9773aef54030", .mnemonic = "V.SW.AND", .asm_fmt = "v.sw.and<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000100b0000107fULL, .field_start = 2562, .field_count = 5 },
+  { .id = "v_sw_brg_64_d78368c708bd", .mnemonic = "V.SW.BRG", .asm_fmt = "v.sw.brg<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<(2+shamt)]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000020490000207fULL, .field_start = 2567, .field_count = 6 },
+  { .id = "v_sw_max_64_2404ff65efac", .mnemonic = "V.SW.MAX", .asm_fmt = "v.sw.max<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000400b0000107fULL, .field_start = 2573, .field_count = 5 },
+  { .id = "v_sw_min_64_1ee3543106bd", .mnemonic = "V.SW.MIN", .asm_fmt = "v.sw.min<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000500b0000107fULL, .field_start = 2578, .field_count = 5 },
+  { .id = "v_sw_or_64_c82ad77db84c", .mnemonic = "V.SW.OR", .asm_fmt = "v.sw.or<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000200b0000107fULL, .field_start = 2583, .field_count = 5 },
+  { .id = "v_sw_u_64_0cf3ad373367", .mnemonic = "V.SW.U", .asm_fmt = "v.sw.u<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000060490000007fULL, .field_start = 2588, .field_count = 6 },
+  { .id = "v_sw_u_brg_64_702c78da59f4", .mnemonic = "V.SW.U.BRG", .asm_fmt = "v.sw.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<<shamt>]", .length_bits = 64, .mask = 0x06007fff0600207fULL, .match = 0x000060490000207fULL, .field_start = 2594, .field_count = 6 },
+  { .id = "v_sw_xor_64_db3db9f0dce5", .mnemonic = "V.SW.XOR", .asm_fmt = "v.sw.xor<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR", .length_bits = 64, .mask = 0xfc007ffff8007fffULL, .match = 0x0000300b0000107fULL, .field_start = 2600, .field_count = 5 },
+  { .id = "v_swi_64_da10b8e7bf20", .mnemonic = "V.SWI", .asm_fmt = "v.swi<.local> SrcL, [SrcR, <lc0<<2>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020590000007fULL, .field_start = 2605, .field_count = 5 },
+  { .id = "v_swi_brg_64_a9cdf55c0d1b", .mnemonic = "V.SWI.BRG", .asm_fmt = "v.swi.brg<.local> SrcL, [SrcR, <lc0<<2>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000020590000207fULL, .field_start = 2610, .field_count = 5 },
+  { .id = "v_swi_u_64_ff93f1677aa7", .mnemonic = "V.SWI.U", .asm_fmt = "v.swi.u<.local> SrcL, [SrcR, <lc0<<2>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060590000007fULL, .field_start = 2615, .field_count = 5 },
+  { .id = "v_swi_u_brg_64_5b46ac2ed36c", .mnemonic = "V.SWI.U.BRG", .asm_fmt = "v.swi.u.brg<.local> SrcL, [SrcR, <lc0<<2>, simm]", .length_bits = 64, .mask = 0x0000707f0000207fULL, .match = 0x000060590000207fULL, .field_start = 2620, .field_count = 5 },
+  { .id = "v_xor_64_d6d77c14a0be", .mnemonic = "V.XOR", .asm_fmt = "v.xor SrcL, SrcR<.not><<<shamt>, ->Dst", .length_bits = 64, .mask = 0x0000707ffe00707fULL, .match = 0x000040050000007fULL, .field_start = 2625, .field_count = 5 },
+  { .id = "v_xori_64_16519d21b271", .mnemonic = "V.XORI", .asm_fmt = "v.xori SrcL, simm, ->Dst", .length_bits = 64, .mask = 0x0000707ffff0707fULL, .match = 0x000040150000007fULL, .field_start = 2630, .field_count = 3 },
+  { .id = "xb_32_40ad190a0a7f", .mnemonic = "XB", .asm_fmt = "XB ACR-ID, C-ID", .length_bits = 32, .mask = 0x0000000000007fffULL, .match = 0x0000000000006f81ULL, .field_start = 2633, .field_count = 2 },
+  { .id = "xor_32_33510860c585", .mnemonic = "XOR", .asm_fmt = "xor SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004005ULL, .field_start = 2635, .field_count = 5 },
+  { .id = "xori_32_5cf7e5be17e7", .mnemonic = "XORI", .asm_fmt = "xori SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004015ULL, .field_start = 2640, .field_count = 3 },
+  { .id = "xoriw_32_1f8c6f43e2bd", .mnemonic = "XORIW", .asm_fmt = "xoriw SrcL, simm, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004035ULL, .field_start = 2643, .field_count = 3 },
+  { .id = "xorw_32_32282566e32d", .mnemonic = "XORW", .asm_fmt = "xorw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}", .length_bits = 32, .mask = 0x000000000000707fULL, .match = 0x0000000000004025ULL, .field_start = 2646, .field_count = 5 },
 };
-const size_t linxisa_inst_forms_count = 769;
+const size_t linxisa_inst_forms_count = 761;
diff --git a/isa/sail/coverage.json b/isa/sail/coverage.json
index 1c452ea4..af3eb5e9 100644
--- a/isa/sail/coverage.json
+++ b/isa/sail/coverage.json
@@ -1 +1,740 @@
-{"decode_only_forms":17,"grade_counts":{"decode-only":17,"executable-subset":752},"modeled_forms":752,"modeled_mnemonics":["ACRC","ACRE","ADD","ADDI","ADDIW","ADDTPC","ADDW","AND","ANDI","ANDIW","ANDW","ASSERT","B.ARG","B.CATR","B.DATR","B.DIM","B.EQ","B.GE","B.GEU","B.HINT","B.IOR","B.IOT","B.LT","B.LTU","B.NE","B.NZ","B.TEXT","B.Z","BC.IALL","BC.IVA","BCNT","BIC","BIS","BSE","BSTART","BSTART CALL","BSTART.ACCCVT","BSTART.CUBE","BSTART.FIXP","BSTART.FP","BSTART.MPAR","BSTART.MSEQ","BSTART.STD","BSTART.SYS","BSTART.TEPL","BSTART.TLOAD","BSTART.TMATMUL","BSTART.TMATMUL.ACC","BSTART.TMOV","BSTART.TSTORE","BSTART.VPAR","BSTART.VSEQ","BSTOP","BWE","BWI","BWT","BXS","BXU","C.ADD","C.ADDI","C.AND","C.B.DIM","C.B.DIMI","C.BSTART","C.BSTART.FP","C.BSTART.MPAR","C.BSTART.MSEQ","C.BSTART.STD","C.BSTART.SYS","C.BSTART.VPAR","C.BSTART.VSEQ","C.BSTOP","C.CMP.EQI","C.CMP.NEI","C.EBREAK","C.LDI","C.LWI","C.MOVI","C.MOVR","C.OR","C.SDI","C.SETC.EQ","C.SETC.NE","C.SETC.TGT","C.SETRET","C.SEXT.B","C.SEXT.H","C.SEXT.W","C.SLLI","C.SRLI","C.SSRGET","C.SUB","C.SWI","C.ZEXT.B","C.ZEXT.H","C.ZEXT.W","CASB","CASD","CASH","CASW","CLZ","CMP.AND","CMP.ANDI","CMP.EQ","CMP.EQI","CMP.GE","CMP.GEI","CMP.GEU","CMP.GEUI","CMP.LT","CMP.LTI","CMP.LTU","CMP.LTUI","CMP.NE","CMP.NEI","CMP.OR","CMP.ORI","CSEL","CTZ","DC.CISW","DC.CIVA","DC.CSW","DC.CVA","DC.IALL","DC.ISW","DC.IVA","DC.ZVA","DIV","DIVU","DIVUW","DIVW","EBREAK","ERCOV","ESAVE","FABS","FADD","FCVT","FCVTA","FCVTM","FCVTN","FCVTP","FCVTZ","FDIV","FENCE.D","FENCE.I","FENTRY","FEQ","FEQS","FEXIT","FEXP","FGE","FGES","FLT","FLTS","FMADD","FMAX","FMIN","FMSUB","FMUL","FNE","FNES","FNMADD","FNMSUB","FRECIP","FRET.RA","FRET.STK","FSQRT","FSUB","HL.ADDI","HL.ADDIW","HL.ADDTPC","HL.ANDI","HL.ANDIW","HL.BFI","HL.BSTART CALL","HL.BSTART.FP","HL.BSTART.STD","HL.BSTART.SYS","HL.CASB","HL.CASD","HL.CASH","HL.CASW","HL.CCAT","HL.CCATW","HL.CMP.ANDI","HL.CMP.EQI","HL.CMP.GEI","HL.CMP.GEUI","HL.CMP.LTI","HL.CMP.LTUI","HL.CMP.NEI","HL.CMP.ORI","HL.DIV","HL.DIVU","HL.DIVUW","HL.DIVW","HL.LB.PCR","HL.LB.PO","HL.LB.PR","HL.LBI","HL.LBI.PO","HL.LBI.PR","HL.LBIP","HL.LBP","HL.LBU.PCR","HL.LBU.PO","HL.LBU.PR","HL.LBUI","HL.LBUI.PO","HL.LBUI.PR","HL.LBUIP","HL.LBUP","HL.LD.PCR","HL.LD.PO","HL.LD.PR","HL.LDI","HL.LDI.PO","HL.LDI.PR","HL.LDI.U","HL.LDI.UPO","HL.LDI.UPR","HL.LDIP","HL.LDIP.U","HL.LDP","HL.LH.PCR","HL.LH.PO","HL.LH.PR","HL.LHI","HL.LHI.PO","HL.LHI.PR","HL.LHI.U","HL.LHI.UPO","HL.LHI.UPR","HL.LHIP","HL.LHIP.U","HL.LHP","HL.LHU.PCR","HL.LHU.PO","HL.LHU.PR","HL.LHUI","HL.LHUI.PO","HL.LHUI.PR","HL.LHUI.U","HL.LHUI.UPO","HL.LHUI.UPR","HL.LHUIP","HL.LHUIP.U","HL.LHUP","HL.LIS","HL.LIU","HL.LUI","HL.LW.PCR","HL.LW.PO","HL.LW.PR","HL.LWI","HL.LWI.PO","HL.LWI.PR","HL.LWI.U","HL.LWI.UPO","HL.LWI.UPR","HL.LWIP","HL.LWIP.U","HL.LWP","HL.LWU.PCR","HL.LWU.PO","HL.LWU.PR","HL.LWUI","HL.LWUI.PO","HL.LWUI.PR","HL.LWUI.U","HL.LWUI.UPO","HL.LWUI.UPR","HL.LWUIP","HL.LWUIP.U","HL.LWUP","HL.MADD","HL.MADDW","HL.MIADD","HL.MISUB","HL.MUL","HL.MULU","HL.ORI","HL.ORIW","HL.PRF","HL.PRF.A","HL.PRFI.U","HL.PRFI.UA","HL.QMT","HL.QPOP","HL.QPUSH","HL.REM","HL.REMU","HL.REMUW","HL.REMW","HL.SB.PCR","HL.SB.PO","HL.SB.PR","HL.SBI","HL.SBI.PO","HL.SBI.PR","HL.SBIP","HL.SBP","HL.SD.PCR","HL.SD.PO","HL.SD.PR","HL.SD.UPO","HL.SD.UPR","HL.SDI","HL.SDI.PO","HL.SDI.PR","HL.SDI.U","HL.SDI.UPO","HL.SDI.UPR","HL.SDIP","HL.SDIP.U","HL.SDP","HL.SDP.U","HL.SETC.ANDI","HL.SETC.EQI","HL.SETC.GEI","HL.SETC.GEUI","HL.SETC.LTI","HL.SETC.LTUI","HL.SETC.NEI","HL.SETC.ORI","HL.SETRET","HL.SH.PCR","HL.SH.PO","HL.SH.PR","HL.SH.UPO","HL.SH.UPR","HL.SHI","HL.SHI.PO","HL.SHI.PR","HL.SHI.U","HL.SHI.UPO","HL.SHI.UPR","HL.SHIP","HL.SHIP.U","HL.SHP","HL.SHP.U","HL.SSRGET","HL.SSRSET","HL.SUBI","HL.SUBIW","HL.SW.PCR","HL.SW.PO","HL.SW.PR","HL.SW.UPO","HL.SW.UPR","HL.SWI","HL.SWI.PO","HL.SWI.PR","HL.SWI.U","HL.SWI.UPO","HL.SWI.UPR","HL.SWIP","HL.SWIP.U","HL.SWP","HL.SWP.U","HL.XORI","HL.XORIW","IC.IALL","IC.IVA","J","JR","L.BSTART.FP","L.BSTART.STD","L.BSTART.SYS","LB","LB.PCR","LBI","LBU","LBU.PCR","LBUI","LD","LD.ADD","LD.AND","LD.OR","LD.PCR","LD.SMAX","LD.SMIN","LD.UMAX","LD.UMIN","LD.XOR","LDI","LDI.U","LH","LH.PCR","LHI","LHI.U","LHU","LHU.PCR","LHUI","LHUI.U","LR.B","LR.D","LR.H","LR.W","LSRGET","LUI","LW","LW.ADD","LW.AND","LW.OR","LW.PCR","LW.SMAX","LW.SMIN","LW.UMAX","LW.UMIN","LW.XOR","LWI","LWI.U","LWU","LWU.PCR","LWUI","LWUI.U","MADD","MADDW","MAX","MAXU","MCOPY","MIN","MINU","MSET","MUL","MULU","MULUW","MULW","OR","ORI","ORIW","ORW","PRF","PRFI.U","REM","REMU","REMUW","REMW","REV","SB","SB.PCR","SBI","SC.B","SC.D","SC.H","SC.W","SCVTF","SD","SD.ADD","SD.AND","SD.OR","SD.PCR","SD.SMAX","SD.SMIN","SD.U","SD.UMAX","SD.UMIN","SD.XOR","SDI","SDI.U","SETC.AND","SETC.ANDI","SETC.EQ","SETC.EQI","SETC.GE","SETC.GEI","SETC.GEU","SETC.GEUI","SETC.LT","SETC.LTI","SETC.LTU","SETC.LTUI","SETC.NE","SETC.NEI","SETC.OR","SETC.ORI","SETC.TGT","SETRET","SH","SH.PCR","SH.U","SHI","SHI.U","SLL","SLLI","SLLIW","SLLW","SRA","SRAI","SRAIW","SRAW","SRL","SRLI","SRLIW","SRLW","SSRGET","SSRSET","SSRSWAP","SUB","SUBI","SUBIW","SUBW","SW","SW.ADD","SW.AND","SW.OR","SW.PCR","SW.SMAX","SW.SMIN","SW.U","SW.UMAX","SW.UMIN","SW.XOR","SWAPB","SWAPD","SWAPH","SWAPW","SWI","SWI.U","TLB.IA","TLB.IALL","TLB.IAV","TLB.IV","UCVTF","V.ADD","V.ADDI","V.AND","V.ANDI","V.BCNT","V.BIC","V.BIS","V.BXS","V.BXU","V.CLZ","V.CMP.AND","V.CMP.ANDI","V.CMP.EQ","V.CMP.EQI","V.CMP.GE","V.CMP.GEI","V.CMP.GEU","V.CMP.GEUI","V.CMP.LT","V.CMP.LTI","V.CMP.LTU","V.CMP.LTUI","V.CMP.NE","V.CMP.NEI","V.CMP.OR","V.CMP.ORI","V.CSEL","V.CTZ","V.DIV","V.FABS","V.FADD","V.FCLASS","V.FCVT","V.FCVTI","V.FDIV","V.FEQ","V.FEQS","V.FEXP","V.FGE","V.FGES","V.FLT","V.FLTS","V.FMADD","V.FMAX","V.FMIN","V.FMSUB","V.FMUL","V.FNE","V.FNES","V.FNMADD","V.FNMSUB","V.FRECIP","V.FSQRT","V.FSUB","V.ICVT","V.ICVTF","V.LB","V.LB.BRG","V.LBI","V.LBI.BRG","V.LBU","V.LBU.BRG","V.LBUI","V.LBUI.BRG","V.LD","V.LD.ADD","V.LD.AND","V.LD.BRG","V.LD.MAX","V.LD.MIN","V.LD.OR","V.LD.XOR","V.LDI","V.LDI.BRG","V.LDI.U","V.LDI.U.BRG","V.LH","V.LH.BRG","V.LHI","V.LHI.BRG","V.LHI.U","V.LHI.U.BRG","V.LHU","V.LHU.BRG","V.LHUI","V.LHUI.BRG","V.LHUI.U","V.LHUI.U.BRG","V.LW","V.LW.ADD","V.LW.AND","V.LW.BRG","V.LW.MAX","V.LW.MIN","V.LW.OR","V.LW.XOR","V.LWI","V.LWI.BRG","V.LWI.U","V.LWI.U.BRG","V.LWU","V.LWU.BRG","V.LWUI","V.LWUI.BRG","V.LWUI.U","V.LWUI.U.BRG","V.MADD","V.MAX","V.MIN","V.MUL","V.OR","V.ORI","V.PSEL","V.QPOP","V.QPUSH","V.RDADD","V.RDAND","V.RDFADD","V.RDFMAX","V.RDFMIN","V.RDMAX","V.RDMIN","V.RDOR","V.RDXOR","V.REM","V.REV","V.SB","V.SB.BRG","V.SBI","V.SBI.BRG","V.SD","V.SD.ADD","V.SD.AND","V.SD.BRG","V.SD.MAX","V.SD.MIN","V.SD.OR","V.SD.U","V.SD.U.BRG","V.SD.XOR","V.SDI","V.SDI.BRG","V.SDI.U","V.SDI.U.BRG","V.SH","V.SH.BRG","V.SH.U","V.SH.U.BRG","V.SHFL.BFLY","V.SHFL.DOWN","V.SHFL.IDX","V.SHFL.UP","V.SHFLI.BFLY","V.SHFLI.DOWN","V.SHFLI.IDX","V.SHFLI.UP","V.SHI","V.SHI.BRG","V.SHI.U","V.SHI.U.BRG","V.SLL","V.SLLI","V.SRA","V.SRAI","V.SRL","V.SRLI","V.SUB","V.SUBI","V.SW","V.SW.ADD","V.SW.AND","V.SW.BRG","V.SW.MAX","V.SW.MIN","V.SW.OR","V.SW.U","V.SW.U.BRG","V.SW.XOR","V.SWI","V.SWI.BRG","V.SWI.U","V.SWI.U.BRG","V.XOR","V.XORI","XB","XOR","XORI","XORIW","XORW"],"semantic_status":"isa/sail/semantics_status.json","spec":"isa/v0.57/linxisa-v0.57.json","total_forms":769}
+{
+  "decode_only_forms": 1,
+  "grade_counts": {
+    "decode-only": 1,
+    "executable-subset": 760
+  },
+  "modeled_forms": 760,
+  "modeled_mnemonics": [
+    "ACRC",
+    "ACRE",
+    "ADD",
+    "ADDI",
+    "ADDIW",
+    "ADDTPC",
+    "ADDW",
+    "AND",
+    "ANDI",
+    "ANDIW",
+    "ANDW",
+    "ASSERT",
+    "B.CATR",
+    "B.DATR",
+    "B.DIM",
+    "B.EQ",
+    "B.GE",
+    "B.GEU",
+    "B.HINT",
+    "B.IOR",
+    "B.IOT",
+    "B.LT",
+    "B.LTU",
+    "B.NE",
+    "B.NZ",
+    "B.TEXT",
+    "B.Z",
+    "BC.IALL",
+    "BC.IVA",
+    "BCNT",
+    "BIC",
+    "BIS",
+    "BSE",
+    "BSTART",
+    "BSTART CALL",
+    "BSTART.ACCCVT",
+    "BSTART.FP",
+    "BSTART.MGATHER",
+    "BSTART.MGATHER.CAS",
+    "BSTART.MGATHER.MASK",
+    "BSTART.MPAR",
+    "BSTART.MSCATTER",
+    "BSTART.MSCATTER.MASK",
+    "BSTART.MSEQ",
+    "BSTART.STD",
+    "BSTART.SYS",
+    "BSTART.TEPL",
+    "BSTART.TGEMV",
+    "BSTART.TGEMV.ACC",
+    "BSTART.TGEMV.BIAS",
+    "BSTART.TGEMVMX",
+    "BSTART.TGEMVMX.ACC",
+    "BSTART.TGEMVMX.BIAS",
+    "BSTART.TLOAD",
+    "BSTART.TMATMUL",
+    "BSTART.TMATMUL.ACC",
+    "BSTART.TMATMUL.BIAS",
+    "BSTART.TMATMULMX",
+    "BSTART.TMATMULMX.ACC",
+    "BSTART.TMATMULMX.BIAS",
+    "BSTART.TMOV",
+    "BSTART.TPREFETCH",
+    "BSTART.TSTORE",
+    "BSTART.VPAR",
+    "BSTART.VSEQ",
+    "BSTOP",
+    "BWE",
+    "BWI",
+    "BWT",
+    "BXS",
+    "BXU",
+    "C.ADD",
+    "C.ADDI",
+    "C.AND",
+    "C.B.DIM",
+    "C.B.DIMI",
+    "C.BSTART",
+    "C.BSTART.FP",
+    "C.BSTART.MPAR",
+    "C.BSTART.MSEQ",
+    "C.BSTART.STD",
+    "C.BSTART.SYS",
+    "C.BSTART.VPAR",
+    "C.BSTART.VSEQ",
+    "C.BSTOP",
+    "C.CMP.EQI",
+    "C.CMP.NEI",
+    "C.EBREAK",
+    "C.LDI",
+    "C.LWI",
+    "C.MOVI",
+    "C.MOVR",
+    "C.OR",
+    "C.SDI",
+    "C.SETC.EQ",
+    "C.SETC.NE",
+    "C.SETC.TGT",
+    "C.SETRET",
+    "C.SEXT.B",
+    "C.SEXT.H",
+    "C.SEXT.W",
+    "C.SLLI",
+    "C.SRLI",
+    "C.SSRGET",
+    "C.SUB",
+    "C.SWI",
+    "C.ZEXT.B",
+    "C.ZEXT.H",
+    "C.ZEXT.W",
+    "CASB",
+    "CASD",
+    "CASH",
+    "CASW",
+    "CLZ",
+    "CMP.AND",
+    "CMP.ANDI",
+    "CMP.EQ",
+    "CMP.EQI",
+    "CMP.GE",
+    "CMP.GEI",
+    "CMP.GEU",
+    "CMP.GEUI",
+    "CMP.LT",
+    "CMP.LTI",
+    "CMP.LTU",
+    "CMP.LTUI",
+    "CMP.NE",
+    "CMP.NEI",
+    "CMP.OR",
+    "CMP.ORI",
+    "CSEL",
+    "CTZ",
+    "DC.CISW",
+    "DC.CIVA",
+    "DC.CSW",
+    "DC.CVA",
+    "DC.IALL",
+    "DC.ISW",
+    "DC.IVA",
+    "DC.ZVA",
+    "DIV",
+    "DIVU",
+    "DIVUW",
+    "DIVW",
+    "EBREAK",
+    "ERCOV",
+    "ESAVE",
+    "FABS",
+    "FADD",
+    "FCVT",
+    "FCVTA",
+    "FCVTM",
+    "FCVTN",
+    "FCVTP",
+    "FCVTZ",
+    "FDIV",
+    "FENCE.D",
+    "FENCE.I",
+    "FENTRY",
+    "FEQ",
+    "FEQS",
+    "FEXIT",
+    "FEXP",
+    "FGE",
+    "FGES",
+    "FLT",
+    "FLTS",
+    "FMADD",
+    "FMAX",
+    "FMIN",
+    "FMSUB",
+    "FMUL",
+    "FNE",
+    "FNES",
+    "FNMADD",
+    "FNMSUB",
+    "FRECIP",
+    "FRET.RA",
+    "FRET.STK",
+    "FSQRT",
+    "FSUB",
+    "HL.ADDI",
+    "HL.ADDIW",
+    "HL.ADDTPC",
+    "HL.ANDI",
+    "HL.ANDIW",
+    "HL.BFI",
+    "HL.BSTART CALL",
+    "HL.BSTART.FP",
+    "HL.BSTART.STD",
+    "HL.BSTART.SYS",
+    "HL.CASB",
+    "HL.CASD",
+    "HL.CASH",
+    "HL.CASW",
+    "HL.CCAT",
+    "HL.CCATW",
+    "HL.CMP.ANDI",
+    "HL.CMP.EQI",
+    "HL.CMP.GEI",
+    "HL.CMP.GEUI",
+    "HL.CMP.LTI",
+    "HL.CMP.LTUI",
+    "HL.CMP.NEI",
+    "HL.CMP.ORI",
+    "HL.DIV",
+    "HL.DIVU",
+    "HL.DIVUW",
+    "HL.DIVW",
+    "HL.LB.PCR",
+    "HL.LB.PO",
+    "HL.LB.PR",
+    "HL.LBI",
+    "HL.LBI.PO",
+    "HL.LBI.PR",
+    "HL.LBIP",
+    "HL.LBP",
+    "HL.LBU.PCR",
+    "HL.LBU.PO",
+    "HL.LBU.PR",
+    "HL.LBUI",
+    "HL.LBUI.PO",
+    "HL.LBUI.PR",
+    "HL.LBUIP",
+    "HL.LBUP",
+    "HL.LD.PCR",
+    "HL.LD.PO",
+    "HL.LD.PR",
+    "HL.LDI",
+    "HL.LDI.PO",
+    "HL.LDI.PR",
+    "HL.LDI.U",
+    "HL.LDI.UPO",
+    "HL.LDI.UPR",
+    "HL.LDIP",
+    "HL.LDIP.U",
+    "HL.LDP",
+    "HL.LH.PCR",
+    "HL.LH.PO",
+    "HL.LH.PR",
+    "HL.LHI",
+    "HL.LHI.PO",
+    "HL.LHI.PR",
+    "HL.LHI.U",
+    "HL.LHI.UPO",
+    "HL.LHI.UPR",
+    "HL.LHIP",
+    "HL.LHIP.U",
+    "HL.LHP",
+    "HL.LHU.PCR",
+    "HL.LHU.PO",
+    "HL.LHU.PR",
+    "HL.LHUI",
+    "HL.LHUI.PO",
+    "HL.LHUI.PR",
+    "HL.LHUI.U",
+    "HL.LHUI.UPO",
+    "HL.LHUI.UPR",
+    "HL.LHUIP",
+    "HL.LHUIP.U",
+    "HL.LHUP",
+    "HL.LIS",
+    "HL.LIU",
+    "HL.LUI",
+    "HL.LW.PCR",
+    "HL.LW.PO",
+    "HL.LW.PR",
+    "HL.LWI",
+    "HL.LWI.PO",
+    "HL.LWI.PR",
+    "HL.LWI.U",
+    "HL.LWI.UPO",
+    "HL.LWI.UPR",
+    "HL.LWIP",
+    "HL.LWIP.U",
+    "HL.LWP",
+    "HL.LWU.PCR",
+    "HL.LWU.PO",
+    "HL.LWU.PR",
+    "HL.LWUI",
+    "HL.LWUI.PO",
+    "HL.LWUI.PR",
+    "HL.LWUI.U",
+    "HL.LWUI.UPO",
+    "HL.LWUI.UPR",
+    "HL.LWUIP",
+    "HL.LWUIP.U",
+    "HL.LWUP",
+    "HL.MADD",
+    "HL.MADDW",
+    "HL.MIADD",
+    "HL.MISUB",
+    "HL.MUL",
+    "HL.MULU",
+    "HL.ORI",
+    "HL.ORIW",
+    "HL.PRF",
+    "HL.PRF.A",
+    "HL.PRFI.U",
+    "HL.PRFI.UA",
+    "HL.QMT",
+    "HL.QPOP",
+    "HL.QPUSH",
+    "HL.REM",
+    "HL.REMU",
+    "HL.REMUW",
+    "HL.REMW",
+    "HL.SB.PCR",
+    "HL.SB.PO",
+    "HL.SB.PR",
+    "HL.SBI",
+    "HL.SBI.PO",
+    "HL.SBI.PR",
+    "HL.SBIP",
+    "HL.SBP",
+    "HL.SD.PCR",
+    "HL.SD.PO",
+    "HL.SD.PR",
+    "HL.SD.UPO",
+    "HL.SD.UPR",
+    "HL.SDI",
+    "HL.SDI.PO",
+    "HL.SDI.PR",
+    "HL.SDI.U",
+    "HL.SDI.UPO",
+    "HL.SDI.UPR",
+    "HL.SDIP",
+    "HL.SDIP.U",
+    "HL.SDP",
+    "HL.SDP.U",
+    "HL.SETC.ANDI",
+    "HL.SETC.EQI",
+    "HL.SETC.GEI",
+    "HL.SETC.GEUI",
+    "HL.SETC.LTI",
+    "HL.SETC.LTUI",
+    "HL.SETC.NEI",
+    "HL.SETC.ORI",
+    "HL.SETRET",
+    "HL.SH.PCR",
+    "HL.SH.PO",
+    "HL.SH.PR",
+    "HL.SH.UPO",
+    "HL.SH.UPR",
+    "HL.SHI",
+    "HL.SHI.PO",
+    "HL.SHI.PR",
+    "HL.SHI.U",
+    "HL.SHI.UPO",
+    "HL.SHI.UPR",
+    "HL.SHIP",
+    "HL.SHIP.U",
+    "HL.SHP",
+    "HL.SHP.U",
+    "HL.SSRGET",
+    "HL.SSRSET",
+    "HL.SUBI",
+    "HL.SUBIW",
+    "HL.SW.PCR",
+    "HL.SW.PO",
+    "HL.SW.PR",
+    "HL.SW.UPO",
+    "HL.SW.UPR",
+    "HL.SWI",
+    "HL.SWI.PO",
+    "HL.SWI.PR",
+    "HL.SWI.U",
+    "HL.SWI.UPO",
+    "HL.SWI.UPR",
+    "HL.SWIP",
+    "HL.SWIP.U",
+    "HL.SWP",
+    "HL.SWP.U",
+    "HL.XORI",
+    "HL.XORIW",
+    "IC.IALL",
+    "IC.IVA",
+    "J",
+    "JR",
+    "L.BSTART.FP",
+    "L.BSTART.STD",
+    "L.BSTART.SYS",
+    "LB",
+    "LB.PCR",
+    "LBI",
+    "LBU",
+    "LBU.PCR",
+    "LBUI",
+    "LD",
+    "LD.ADD",
+    "LD.AND",
+    "LD.OR",
+    "LD.PCR",
+    "LD.SMAX",
+    "LD.SMIN",
+    "LD.UMAX",
+    "LD.UMIN",
+    "LD.XOR",
+    "LDI",
+    "LDI.U",
+    "LH",
+    "LH.PCR",
+    "LHI",
+    "LHI.U",
+    "LHU",
+    "LHU.PCR",
+    "LHUI",
+    "LHUI.U",
+    "LR.B",
+    "LR.D",
+    "LR.H",
+    "LR.W",
+    "LSRGET",
+    "LUI",
+    "LW",
+    "LW.ADD",
+    "LW.AND",
+    "LW.OR",
+    "LW.PCR",
+    "LW.SMAX",
+    "LW.SMIN",
+    "LW.UMAX",
+    "LW.UMIN",
+    "LW.XOR",
+    "LWI",
+    "LWI.U",
+    "LWU",
+    "LWU.PCR",
+    "LWUI",
+    "LWUI.U",
+    "MADD",
+    "MADDW",
+    "MAX",
+    "MAXU",
+    "MCOPY",
+    "MIN",
+    "MINU",
+    "MSET",
+    "MUL",
+    "MULU",
+    "MULUW",
+    "MULW",
+    "OR",
+    "ORI",
+    "ORIW",
+    "ORW",
+    "PRF",
+    "PRFI.U",
+    "REM",
+    "REMU",
+    "REMUW",
+    "REMW",
+    "REV",
+    "SB",
+    "SB.PCR",
+    "SBI",
+    "SC.B",
+    "SC.D",
+    "SC.H",
+    "SC.W",
+    "SCVTF",
+    "SD",
+    "SD.ADD",
+    "SD.AND",
+    "SD.OR",
+    "SD.PCR",
+    "SD.SMAX",
+    "SD.SMIN",
+    "SD.U",
+    "SD.UMAX",
+    "SD.UMIN",
+    "SD.XOR",
+    "SDI",
+    "SDI.U",
+    "SETC.AND",
+    "SETC.ANDI",
+    "SETC.EQ",
+    "SETC.EQI",
+    "SETC.GE",
+    "SETC.GEI",
+    "SETC.GEU",
+    "SETC.GEUI",
+    "SETC.LT",
+    "SETC.LTI",
+    "SETC.LTU",
+    "SETC.LTUI",
+    "SETC.NE",
+    "SETC.NEI",
+    "SETC.OR",
+    "SETC.ORI",
+    "SETC.TGT",
+    "SETRET",
+    "SH",
+    "SH.PCR",
+    "SH.U",
+    "SHI",
+    "SHI.U",
+    "SLL",
+    "SLLI",
+    "SLLIW",
+    "SLLW",
+    "SRA",
+    "SRAI",
+    "SRAIW",
+    "SRAW",
+    "SRL",
+    "SRLI",
+    "SRLIW",
+    "SRLW",
+    "SSRGET",
+    "SSRSET",
+    "SSRSWAP",
+    "SUB",
+    "SUBI",
+    "SUBIW",
+    "SUBW",
+    "SW",
+    "SW.ADD",
+    "SW.AND",
+    "SW.OR",
+    "SW.PCR",
+    "SW.SMAX",
+    "SW.SMIN",
+    "SW.U",
+    "SW.UMAX",
+    "SW.UMIN",
+    "SW.XOR",
+    "SWAPB",
+    "SWAPD",
+    "SWAPH",
+    "SWAPW",
+    "SWI",
+    "SWI.U",
+    "TLB.IA",
+    "TLB.IALL",
+    "TLB.IAV",
+    "TLB.IV",
+    "UCVTF",
+    "V.ADD",
+    "V.ADDI",
+    "V.AND",
+    "V.ANDI",
+    "V.BCNT",
+    "V.BIC",
+    "V.BIS",
+    "V.BXS",
+    "V.BXU",
+    "V.CLZ",
+    "V.CMP.AND",
+    "V.CMP.ANDI",
+    "V.CMP.EQ",
+    "V.CMP.EQI",
+    "V.CMP.GE",
+    "V.CMP.GEI",
+    "V.CMP.GEU",
+    "V.CMP.GEUI",
+    "V.CMP.LT",
+    "V.CMP.LTI",
+    "V.CMP.LTU",
+    "V.CMP.LTUI",
+    "V.CMP.NE",
+    "V.CMP.NEI",
+    "V.CMP.OR",
+    "V.CMP.ORI",
+    "V.CSEL",
+    "V.CTZ",
+    "V.DIV",
+    "V.FABS",
+    "V.FADD",
+    "V.FCLASS",
+    "V.FCVT",
+    "V.FCVTI",
+    "V.FDIV",
+    "V.FEQ",
+    "V.FEQS",
+    "V.FEXP",
+    "V.FGE",
+    "V.FGES",
+    "V.FLT",
+    "V.FLTS",
+    "V.FMADD",
+    "V.FMAX",
+    "V.FMIN",
+    "V.FMSUB",
+    "V.FMUL",
+    "V.FNE",
+    "V.FNES",
+    "V.FNMADD",
+    "V.FNMSUB",
+    "V.FRECIP",
+    "V.FSQRT",
+    "V.FSUB",
+    "V.ICVT",
+    "V.ICVTF",
+    "V.LB",
+    "V.LB.BRG",
+    "V.LBI",
+    "V.LBI.BRG",
+    "V.LBU",
+    "V.LBU.BRG",
+    "V.LBUI",
+    "V.LBUI.BRG",
+    "V.LD",
+    "V.LD.ADD",
+    "V.LD.AND",
+    "V.LD.BRG",
+    "V.LD.MAX",
+    "V.LD.MIN",
+    "V.LD.OR",
+    "V.LD.XOR",
+    "V.LDI",
+    "V.LDI.BRG",
+    "V.LDI.U",
+    "V.LDI.U.BRG",
+    "V.LH",
+    "V.LH.BRG",
+    "V.LHI",
+    "V.LHI.BRG",
+    "V.LHI.U",
+    "V.LHI.U.BRG",
+    "V.LHU",
+    "V.LHU.BRG",
+    "V.LHUI",
+    "V.LHUI.BRG",
+    "V.LHUI.U",
+    "V.LHUI.U.BRG",
+    "V.LW",
+    "V.LW.ADD",
+    "V.LW.AND",
+    "V.LW.BRG",
+    "V.LW.MAX",
+    "V.LW.MIN",
+    "V.LW.OR",
+    "V.LW.XOR",
+    "V.LWI",
+    "V.LWI.BRG",
+    "V.LWI.U",
+    "V.LWI.U.BRG",
+    "V.LWU",
+    "V.LWU.BRG",
+    "V.LWUI",
+    "V.LWUI.BRG",
+    "V.LWUI.U",
+    "V.LWUI.U.BRG",
+    "V.MADD",
+    "V.MAX",
+    "V.MIN",
+    "V.MUL",
+    "V.OR",
+    "V.ORI",
+    "V.PSEL",
+    "V.QPOP",
+    "V.QPUSH",
+    "V.RDADD",
+    "V.RDAND",
+    "V.RDFADD",
+    "V.RDFMAX",
+    "V.RDFMIN",
+    "V.RDMAX",
+    "V.RDMIN",
+    "V.RDOR",
+    "V.RDXOR",
+    "V.REM",
+    "V.REV",
+    "V.SB",
+    "V.SB.BRG",
+    "V.SBI",
+    "V.SBI.BRG",
+    "V.SD",
+    "V.SD.ADD",
+    "V.SD.AND",
+    "V.SD.BRG",
+    "V.SD.MAX",
+    "V.SD.MIN",
+    "V.SD.OR",
+    "V.SD.U",
+    "V.SD.U.BRG",
+    "V.SD.XOR",
+    "V.SDI",
+    "V.SDI.BRG",
+    "V.SDI.U",
+    "V.SDI.U.BRG",
+    "V.SH",
+    "V.SH.BRG",
+    "V.SH.U",
+    "V.SH.U.BRG",
+    "V.SHFL.BFLY",
+    "V.SHFL.DOWN",
+    "V.SHFL.IDX",
+    "V.SHFL.UP",
+    "V.SHFLI.BFLY",
+    "V.SHFLI.DOWN",
+    "V.SHFLI.IDX",
+    "V.SHFLI.UP",
+    "V.SHI",
+    "V.SHI.BRG",
+    "V.SHI.U",
+    "V.SHI.U.BRG",
+    "V.SLL",
+    "V.SLLI",
+    "V.SRA",
+    "V.SRAI",
+    "V.SRL",
+    "V.SRLI",
+    "V.SUB",
+    "V.SUBI",
+    "V.SW",
+    "V.SW.ADD",
+    "V.SW.AND",
+    "V.SW.BRG",
+    "V.SW.MAX",
+    "V.SW.MIN",
+    "V.SW.OR",
+    "V.SW.U",
+    "V.SW.U.BRG",
+    "V.SW.XOR",
+    "V.SWI",
+    "V.SWI.BRG",
+    "V.SWI.U",
+    "V.SWI.U.BRG",
+    "V.XOR",
+    "V.XORI",
+    "XB",
+    "XOR",
+    "XORI",
+    "XORIW",
+    "XORW"
+  ],
+  "semantic_status": "isa/sail/semantics_status.json",
+  "spec": "isa/v0.57/linxisa-v0.57.json",
+  "total_forms": 761
+}
diff --git a/isa/sail/model/decode/decode.sail b/isa/sail/model/decode/decode.sail
index 9e04ae85..4aae52e3 100644
--- a/isa/sail/model/decode/decode.sail
+++ b/isa/sail/model/decode/decode.sail
@@ -47,8 +47,164 @@ function decode_block_target42(simm42 : bits(42)) -> bits(64) = {
   read_pc_or_tpc() + sail_shiftleft(sext42_to64(simm42), 1)
 }
 
+function decode_execute16_match_0(inst : bits(16)) -> bool = {
+  (inst & 0xffff) == 0x08c0
+}
+
+function decode_execute16_match_1(inst : bits(16)) -> bool = {
+  (inst & 0xffff) == 0x48c0
+}
+
+function decode_execute16_match_2(inst : bits(16)) -> bool = {
+  (inst & 0xffff) == 0x0840
+}
+
+function decode_execute16_match_3(inst : bits(16)) -> bool = {
+  (inst & 0xffff) == 0x88c0
+}
+
+function decode_execute16_match_4(inst : bits(16)) -> bool = {
+  (inst & 0xffff) == 0xc8c0
+}
+
+function decode_execute16_match_5(inst : bits(16)) -> bool = {
+  (inst & 0xffff) == 0x0000
+}
+
+function decode_execute16_match_6(inst : bits(16)) -> bool = {
+  and_bool_no_flow((inst & 0xc7ff) == 0x0080, (inst[13..11] != 0b000))
+}
+
+function decode_execute16_match_7(inst : bits(16)) -> bool = {
+  and_bool_no_flow((inst & 0xc7ff) == 0x0000, (inst[13..11] != 0b000))
+}
+
+function decode_execute16_match_8(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x002c
+}
+
+function decode_execute16_match_9(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x082c
+}
+
+function decode_execute16_match_10(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0xc02c
+}
+
+function decode_execute16_match_11(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x001c
+}
+
+function decode_execute16_match_12(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x5016
+}
+
+function decode_execute16_match_13(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x401c
+}
+
+function decode_execute16_match_14(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x481c
+}
+
+function decode_execute16_match_15(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x501c
+}
+
+function decode_execute16_match_16(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x102c
+}
+
+function decode_execute16_match_17(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x182c
+}
+
+function decode_execute16_match_18(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x802c
+}
+
+function decode_execute16_match_19(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x581c
+}
+
+function decode_execute16_match_20(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x601c
+}
+
+function decode_execute16_match_21(inst : bits(16)) -> bool = {
+  (inst & 0xf83f) == 0x681c
+}
+
+function decode_execute16_match_22(inst : bits(16)) -> bool = {
+  (inst & 0xc03f) == 0xc03c
+}
+
+function decode_execute16_match_23(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x0008
+}
+
+function decode_execute16_match_24(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x000c
+}
+
+function decode_execute16_match_25(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x0028
+}
+
+function decode_execute16_match_26(inst : bits(16)) -> bool = {
+  and_bool_no_flow((inst & 0x003f) == 0x003c, (inst[15..14] != 0b11))
+}
+
+function decode_execute16_match_27(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x001a
+}
+
+function decode_execute16_match_28(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x000a
+}
+
+function decode_execute16_match_29(inst : bits(16)) -> bool = {
+  and_bool_no_flow((inst & 0x003f) == 0x0016, (inst[15..11] != 0b01010))
+}
+
+function decode_execute16_match_30(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x0006
+}
+
+function decode_execute16_match_31(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x0038
+}
+
+function decode_execute16_match_32(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x003a
+}
+
+function decode_execute16_match_33(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x0026
+}
+
+function decode_execute16_match_34(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x0036
+}
+
+function decode_execute16_match_35(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x0018
+}
+
+function decode_execute16_match_36(inst : bits(16)) -> bool = {
+  (inst & 0x003f) == 0x002a
+}
+
+function decode_execute16_match_37(inst : bits(16)) -> bool = {
+  (inst & 0x000f) == 0x0004
+}
+
+function decode_execute16_match_38(inst : bits(16)) -> bool = {
+  (inst & 0x000f) == 0x0002
+}
+
 function decode_execute16(inst : bits(16)) -> unit = {
-  if (inst & 0xffff) == 0x08c0 then {
+  if decode_execute16_match_0(inst) then {
     // C.BSTART.MPAR | C.BSTART.MPAR FALL | {'file': 'opcodes/lx_c.opc', 'line': 19}
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b0101;
@@ -56,7 +212,7 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0001;
     exec_c_bstart_mpar()
   }
-  else if (inst & 0xffff) == 0x48c0 then {
+  else if decode_execute16_match_1(inst) then {
     // C.BSTART.MSEQ | C.BSTART.MSEQ FALL | {'file': 'opcodes/lx_c.opc', 'line': 20}
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b0110;
@@ -64,7 +220,7 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0001;
     exec_c_bstart_mseq()
   }
-  else if (inst & 0xffff) == 0x0840 then {
+  else if decode_execute16_match_2(inst) then {
     // C.BSTART.SYS | C.BSTART.SYS FALL | {'file': 'opcodes/lx_c.opc', 'line': 22}
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b0001;
@@ -72,7 +228,7 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_c_bstart_sys()
   }
-  else if (inst & 0xffff) == 0x88c0 then {
+  else if decode_execute16_match_3(inst) then {
     // C.BSTART.VPAR | C.BSTART.VPAR FALL | {'file': 'opcodes/lx_c.opc', 'line': 23}
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b0011;
@@ -80,7 +236,7 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0001;
     exec_c_bstart_vpar()
   }
-  else if (inst & 0xffff) == 0xc8c0 then {
+  else if decode_execute16_match_4(inst) then {
     // C.BSTART.VSEQ | C.BSTART.VSEQ FALL | {'file': 'opcodes/lx_c.opc', 'line': 24}
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b0100;
@@ -88,11 +244,11 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0001;
     exec_c_bstart_vseq()
   }
-  else if (inst & 0xffff) == 0x0000 then {
+  else if decode_execute16_match_5(inst) then {
     // C.BSTOP | C.BSTOP | {'file': 'opcodes/lx_c.opc', 'line': 25}
     exec_c_bstop()
   }
-  else if (inst & 0xc7ff) == 0x0080 & (inst[13..11] != 0b000) then {
+  else if decode_execute16_match_6(inst) then {
     // C.BSTART.FP | C.BSTART.FP BrType | {'file': 'opcodes/lx_c.opc', 'line': 18}
     let brtype : bits(3) = inst[13..11];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
@@ -101,7 +257,7 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_c_bstart_fp()
   }
-  else if (inst & 0xc7ff) == 0x0000 & (inst[13..11] != 0b000) then {
+  else if decode_execute16_match_7(inst) then {
     // C.BSTART.STD | C.BSTART.STD BrType | {'file': 'opcodes/lx_c.opc', 'line': 21}
     let brtype : bits(3) = inst[13..11];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
@@ -110,77 +266,77 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_c_bstart_std()
   }
-  else if (inst & 0xf83f) == 0x002c then {
+  else if decode_execute16_match_8(inst) then {
     // C.CMP.EQI | c.cmp.eqi t#1, simm, ->t | {'file': 'opcodes/lx_c.opc', 'line': 26}
     let simm5 : bits(5) = inst[10..6];
     exec_c_cmp_eqi(simm5)
   }
-  else if (inst & 0xf83f) == 0x082c then {
+  else if decode_execute16_match_9(inst) then {
     // C.CMP.NEI | c.cmp.nei t#1, simm, ->t | {'file': 'opcodes/lx_c.opc', 'line': 27}
     let simm5 : bits(5) = inst[10..6];
     exec_c_cmp_nei(simm5)
   }
-  else if (inst & 0xf83f) == 0xc02c then {
+  else if decode_execute16_match_10(inst) then {
     // C.EBREAK | c.break imm | {'file': 'opcodes/lx_c.opc', 'line': 28}
     let imm5 : bits(5) = inst[10..6];
     exec_c_ebreak(imm5)
   }
-  else if (inst & 0xf83f) == 0x001c then {
+  else if decode_execute16_match_11(inst) then {
     // C.SETC.TGT | c.setc.tgt srcL | {'file': 'opcodes/lx_c.opc', 'line': 37}
     let srcl : bits(5) = inst[10..6];
     exec_c_setc_tgt(srcl)
   }
-  else if (inst & 0xf83f) == 0x5016 then {
+  else if decode_execute16_match_12(inst) then {
     // C.SETRET | c.setret uimm, - >Ra | {'file': 'opcodes/lx_c.opc', 'line': 38}
     let uimm5 : bits(5) = inst[10..6];
     exec_c_setret(uimm5)
   }
-  else if (inst & 0xf83f) == 0x401c then {
+  else if decode_execute16_match_13(inst) then {
     // C.SEXT.B | c.sext.b srcL, ->t | {'file': 'opcodes/lx_c.opc', 'line': 39}
     let srcl : bits(5) = inst[10..6];
     exec_c_sext_b(srcl)
   }
-  else if (inst & 0xf83f) == 0x481c then {
+  else if decode_execute16_match_14(inst) then {
     // C.SEXT.H | c.sext.h srcL, ->t | {'file': 'opcodes/lx_c.opc', 'line': 40}
     let srcl : bits(5) = inst[10..6];
     exec_c_sext_h(srcl)
   }
-  else if (inst & 0xf83f) == 0x501c then {
+  else if decode_execute16_match_15(inst) then {
     // C.SEXT.W | c.sext.w srcL, ->t | {'file': 'opcodes/lx_c.opc', 'line': 41}
     let srcl : bits(5) = inst[10..6];
     exec_c_sext_w(srcl)
   }
-  else if (inst & 0xf83f) == 0x102c then {
+  else if decode_execute16_match_16(inst) then {
     // C.SLLI | c.slli t#1, uimm, ->t | {'file': 'opcodes/lx_c.opc', 'line': 42}
     let uimm5 : bits(5) = inst[10..6];
     exec_c_slli(reg_t(), reg_t1(), uimm5)
   }
-  else if (inst & 0xf83f) == 0x182c then {
+  else if decode_execute16_match_17(inst) then {
     // C.SRLI | c.srli t#1, uimm, ->t | {'file': 'opcodes/lx_c.opc', 'line': 43}
     let uimm5 : bits(5) = inst[10..6];
     exec_c_srli(reg_t(), reg_t1(), uimm5)
   }
-  else if (inst & 0xf83f) == 0x802c then {
+  else if decode_execute16_match_18(inst) then {
     // C.SSRGET | c.ssrget SSR-ID, ->t | {'file': 'opcodes/lx_c.opc', 'line': 44}
     let ssrid : bits(5) = inst[10..6];
     exec_c_ssrget(ssrid)
   }
-  else if (inst & 0xf83f) == 0x581c then {
+  else if decode_execute16_match_19(inst) then {
     // C.ZEXT.B | c.zext.b srcL, ->t | {'file': 'opcodes/lx_c.opc', 'line': 47}
     let srcl : bits(5) = inst[10..6];
     exec_c_zext_b(srcl)
   }
-  else if (inst & 0xf83f) == 0x601c then {
+  else if decode_execute16_match_20(inst) then {
     // C.ZEXT.H | c.zext.h srcL, ->t | {'file': 'opcodes/lx_c.opc', 'line': 48}
     let srcl : bits(5) = inst[10..6];
     exec_c_zext_h(srcl)
   }
-  else if (inst & 0xf83f) == 0x681c then {
+  else if decode_execute16_match_21(inst) then {
     // C.ZEXT.W | c.zext.w srcL, ->t | {'file': 'opcodes/lx_c.opc', 'line': 49}
     let srcl : bits(5) = inst[10..6];
     exec_c_zext_w(srcl)
   }
-  else if (inst & 0xc03f) == 0xc03c then {
+  else if decode_execute16_match_22(inst) then {
     // C.B.DIM | C.B.DIM RegSrc, ->{LB0, LB1, LB2} | {'file': 'opcodes/lx_c.opc', 'line': 14}
     let loopnest : bits(3) = inst[13..11];
     let regsrc : bits(5) = inst[10..6];
@@ -188,25 +344,25 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_bdim_value_shadow = read_reg5(regsrc);
     exec_c_b_dim()
   }
-  else if (inst & 0x003f) == 0x0008 then {
+  else if decode_execute16_match_23(inst) then {
     // C.ADD | c.add srcL, srcR, ->t | {'file': 'opcodes/lx_c.opc', 'line': 11}
     let srcl : bits(5) = inst[10..6];
     let srcr : bits(5) = inst[15..11];
     exec_c_add(srcl, srcr)
   }
-  else if (inst & 0x003f) == 0x000c then {
+  else if decode_execute16_match_24(inst) then {
     // C.ADDI | c.addi srcL, simm, ->t | {'file': 'opcodes/lx_c.opc', 'line': 12}
     let srcl : bits(5) = inst[10..6];
     let simm5 : bits(5) = inst[15..11];
     exec_c_addi(srcl, simm5)
   }
-  else if (inst & 0x003f) == 0x0028 then {
+  else if decode_execute16_match_25(inst) then {
     // C.AND | c.and srcL, srcR, ->t | {'file': 'opcodes/lx_c.opc', 'line': 13}
     let srcl : bits(5) = inst[10..6];
     let srcr : bits(5) = inst[15..11];
     exec_c_and(srcl, srcr)
   }
-  else if (inst & 0x003f) == 0x003c & (inst[15..14] != 0b11) then {
+  else if decode_execute16_match_26(inst) then {
     // C.B.DIMI | C.B.DIMI imm, ->{LB0, LB1, LB2} | {'file': 'opcodes/lx_c.opc', 'line': 15}
     let loopnest : bits(2) = inst[15..14];
     let imm8 : bits(8) = inst[13..6];
@@ -214,67 +370,67 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_bdim_value_shadow = sail_zero_extend(imm8, 64);
     exec_c_b_dimi()
   }
-  else if (inst & 0x003f) == 0x001a then {
+  else if decode_execute16_match_27(inst) then {
     // C.LDI | c.ldi [srcL, simm], ->t | {'file': 'opcodes/lx_c.opc', 'line': 29}
     let srcl : bits(5) = inst[10..6];
     let simm5 : bits(5) = inst[15..11];
     exec_c_ldi(srcl, simm5)
   }
-  else if (inst & 0x003f) == 0x000a then {
+  else if decode_execute16_match_28(inst) then {
     // C.LWI | c.lwi [srcL, simm], ->t | {'file': 'opcodes/lx_c.opc', 'line': 30}
     let srcl : bits(5) = inst[10..6];
     let simm5 : bits(5) = inst[15..11];
     exec_c_lwi(srcl, simm5)
   }
-  else if (inst & 0x003f) == 0x0016 & (inst[15..11] != 0b01010) then {
+  else if decode_execute16_match_29(inst) then {
     // C.MOVI | c.movi simm, ->{t, u, Rd} | {'file': 'opcodes/lx_c.opc', 'line': 31}
     let regdst : bits(5) = inst[15..11];
     let simm5 : bits(5) = inst[10..6];
     exec_c_movi(regdst, simm5)
   }
-  else if (inst & 0x003f) == 0x0006 then {
+  else if decode_execute16_match_30(inst) then {
     // C.MOVR | c.movr SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_c.opc', 'line': 32}
     let regdst : bits(5) = inst[15..11];
     let srcl : bits(5) = inst[10..6];
     exec_c_movr(regdst, srcl)
   }
-  else if (inst & 0x003f) == 0x0038 then {
+  else if decode_execute16_match_31(inst) then {
     // C.OR | c.or srcL, srcR, ->t | {'file': 'opcodes/lx_c.opc', 'line': 33}
     let srcl : bits(5) = inst[10..6];
     let srcr : bits(5) = inst[15..11];
     exec_c_or(srcl, srcr)
   }
-  else if (inst & 0x003f) == 0x003a then {
+  else if decode_execute16_match_32(inst) then {
     // C.SDI | c.sdi t#1, [srcL, simm] | {'file': 'opcodes/lx_c.opc', 'line': 34}
     let srcl : bits(5) = inst[10..6];
     let simm5 : bits(5) = inst[15..11];
     exec_c_sdi(srcl, simm5)
   }
-  else if (inst & 0x003f) == 0x0026 then {
+  else if decode_execute16_match_33(inst) then {
     // C.SETC.EQ | c.setc.eq srcL, srcR | {'file': 'opcodes/lx_c.opc', 'line': 35}
     let srcl : bits(5) = inst[10..6];
     let srcr : bits(5) = inst[15..11];
     exec_c_setc_eq(srcl, srcr)
   }
-  else if (inst & 0x003f) == 0x0036 then {
+  else if decode_execute16_match_34(inst) then {
     // C.SETC.NE | c.setc.ne srcL, srcR | {'file': 'opcodes/lx_c.opc', 'line': 36}
     let srcl : bits(5) = inst[10..6];
     let srcr : bits(5) = inst[15..11];
     exec_c_setc_ne(srcl, srcr)
   }
-  else if (inst & 0x003f) == 0x0018 then {
+  else if decode_execute16_match_35(inst) then {
     // C.SUB | c.sub srcL, srcR, ->t | {'file': 'opcodes/lx_c.opc', 'line': 45}
     let srcl : bits(5) = inst[10..6];
     let srcr : bits(5) = inst[15..11];
     exec_c_sub(srcl, srcr)
   }
-  else if (inst & 0x003f) == 0x002a then {
+  else if decode_execute16_match_36(inst) then {
     // C.SWI | c.swi t#1, [srcL, simm] | {'file': 'opcodes/lx_c.opc', 'line': 46}
     let srcl : bits(5) = inst[10..6];
     let simm5 : bits(5) = inst[15..11];
     exec_c_swi(srcl, simm5)
   }
-  else if (inst & 0x000f) == 0x0004 then {
+  else if decode_execute16_match_37(inst) then {
     // C.BSTART | C.BSTART COND,  label | {'file': 'opcodes/lx_c.opc', 'line': 16}
     let simm12 : bits(12) = inst[15..4];
     decoded_block_target_pc_shadow = decode_block_target12(simm12);
@@ -283,7 +439,7 @@ function decode_execute16(inst : bits(16)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_c_bstart()
   }
-  else if (inst & 0x000f) == 0x0002 then {
+  else if decode_execute16_match_38(inst) then {
     // C.BSTART | C.BSTART DIRECT, label | {'file': 'opcodes/lx_c.opc', 'line': 17}
     let simm12 : bits(12) = inst[15..4];
     decoded_block_target_pc_shadow = decode_block_target12(simm12);
@@ -297,4210 +453,9353 @@ function decode_execute16(inst : bits(16)) -> unit = {
   }
 }
 
-function decode_execute32(inst : bits(32)) -> unit = {
-  if (inst & 0xffffffff) == 0x000fa023 then {
-    // B.ARG | B.ARG NORM.normal | {'file': 'opcodes/lx_32.opc', 'line': 30}
-    exec_b_arg()
-  }
-  else if (inst & 0xffffffff) == 0x020fae23 then {
-    // B.ARG | B.ARG NZ2DN.canon | {'file': 'opcodes/lx_32.opc', 'line': 29}
-    exec_b_arg()
-  }
-  else if (inst & 0xffffffff) == 0x180221a3 then {
-    // B.ARG | B.ARG ND2ZN.normal, FP16, Null | {'file': 'opcodes/lx_32.opc', 'line': 26}
-    exec_b_arg()
-  }
-  else if (inst & 0xffffffff) == 0x18022423 then {
-    // B.ARG | B.ARG DN2ZN.normal, FP16, Null | {'file': 'opcodes/lx_32.opc', 'line': 28}
-    exec_b_arg()
-  }
-  else if (inst & 0xffffffff) == 0x1800a4a3 then {
-    // B.ARG | B.ARG DN2NZ.normal, FP32, Null | {'file': 'opcodes/lx_32.opc', 'line': 27}
-    exec_b_arg()
-  }
-  else if (inst & 0xffffffff) == 0x0010402b then {
-    // BC.IALL | bc.iall | {'file': 'opcodes/lx_32.opc', 'line': 51}
-    exec_bc_iall()
-  }
-  else if (inst & 0xffffffff) == 0x00007101 then {
-    // BSTART.FP | BSTART.FP RET | {'file': 'opcodes/lx_32.opc', 'line': 69}
-    decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_ret();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_fp()
+function decode_execute32_opcode_0b0000001_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x00000001
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000001_funct3_0b000_match_0(inst) then {
+    // BSTOP | BSTOP | {'file': 'opcodes/lx_32.opc', 'line': 103}
+    exec_bstop()
   }
-  else if (inst & 0xffffffff) == 0x00006101 then {
-    // BSTART.FP | BSTART.FP ICALL | {'file': 'opcodes/lx_32.opc', 'line': 73}
-    decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_call();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_fp()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xffffffff) == 0x00005101 then {
-    // BSTART.FP | BSTART.FP IND | {'file': 'opcodes/lx_32.opc', 'line': 70}
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf9ffffff) == 0x00001181
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf9ffffff) == 0x00009181
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xf9ffffff) == 0x00021181
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xf9ffffff) == 0x00029181
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_4(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00831181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_5(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00411181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_6(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00811181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_7(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00611181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_8(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00511181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_9(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00711181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_10(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x01031181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_11(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x01231181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_12(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x01131181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_13(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x01431181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_14(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x01631181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_15(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x01531181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_16(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00011181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_17(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00031181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_18(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00231181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_19(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00131181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_20(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00431181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_21(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00631181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_22(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00531181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_23(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00211181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_24(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00311181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_25(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x07ffffff) == 0x00111181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_26(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x000fffff) == 0x00019181, (inst[31..27] != 0b01111)), and_bool_no_flow((inst[31..27] != 0b10101), (inst[31..27] != 0b10110))), and_bool_no_flow(and_bool_no_flow((inst[31..27] != 0b10111), (inst[31..27] != 0b11101)), and_bool_no_flow((inst[31..27] != 0b11110), (inst[31..27] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_27(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00001101
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_28(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00001001
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001_match_29(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00001081
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000001_funct3_0b001_match_0(inst) then {
+    // BSTART.MPAR | BSTART.MPAR <VS8, VS16> | {'file': 'opcodes/lx_32.opc', 'line': 68}
+    let mode : bits(2) = inst[26..25];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_ind();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_fp()
+    decoded_block_type_shadow = 0b0101;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0001;
+    exec_bstart_mpar()
   }
-  else if (inst & 0xffffffff) == 0x00006001 then {
-    // BSTART.STD | BSTART.STD ICALL | {'file': 'opcodes/lx_32.opc', 'line': 81}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_1(inst) then {
+    // BSTART.MSEQ | BSTART.MSEQ <VS8, VS16> | {'file': 'opcodes/lx_32.opc', 'line': 69}
+    let mode : bits(2) = inst[26..25];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_call();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_std()
+    decoded_block_type_shadow = 0b0110;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0001;
+    exec_bstart_mseq()
   }
-  else if (inst & 0xffffffff) == 0x00007001 then {
-    // BSTART.STD | BSTART.STD RET | {'file': 'opcodes/lx_32.opc', 'line': 79}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_2(inst) then {
+    // BSTART.VPAR | BSTART.VPAR <VS8, VS16> | {'file': 'opcodes/lx_32.opc', 'line': 101}
+    let mode : bits(2) = inst[26..25];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_ret();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_std()
+    decoded_block_type_shadow = 0b0011;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0001;
+    exec_bstart_vpar()
   }
-  else if (inst & 0xffffffff) == 0x00005001 then {
-    // BSTART.STD | BSTART.STD IND | {'file': 'opcodes/lx_32.opc', 'line': 83}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_3(inst) then {
+    // BSTART.VSEQ | BSTART.VSEQ <VS8, VS16> | {'file': 'opcodes/lx_32.opc', 'line': 102}
+    let mode : bits(2) = inst[26..25];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_ind();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_std()
-  }
-  else if (inst & 0xffffffff) == 0x00000001 then {
-    // BSTOP | BSTOP | {'file': 'opcodes/lx_32.opc', 'line': 111}
-    exec_bstop()
-  }
-  else if (inst & 0xffffffff) == 0x0010602b then {
-    // DC.IALL | dc.iall | {'file': 'opcodes/lx_32.opc', 'line': 144}
-    exec_dc_iall()
-  }
-  else if (inst & 0xffffffff) == 0x1000202b then {
-    // FENCE.I | fence.i | {'file': 'opcodes/lx_32.opc', 'line': 164}
-    exec_fence_i()
-  }
-  else if (inst & 0xffffffff) == 0x0010502b then {
-    // IC.IALL | ic.iall | {'file': 'opcodes/lx_32.opc', 'line': 188}
-    exec_ic_iall()
-  }
-  else if (inst & 0xffffffff) == 0x0030702b then {
-    // TLB.IALL | tlb.iall | {'file': 'opcodes/lx_32.opc', 'line': 346}
-    exec_tlb_iall()
-  }
-  else if (inst & 0xffff7fff) == 0x00001033 then {
-    // B.HINT | B.HINT TRACE.{begin, end} | {'file': 'opcodes/lx_32.opc', 'line': 38}
-    let b_e : bits(1) = inst[15];
-    exec_b_hint()
-  }
-  else if (inst & 0xff0fffff) == 0x0000302b then {
-    // ACRC | acrc rst_type | {'file': 'opcodes/lx_32.opc', 'line': 11}
-    let rst_type : bits(4) = inst[23..20];
-    exec_acrc(rst_type)
-  }
-  else if (inst & 0xff0fffff) == 0x0100302b then {
-    // ACRE | acre rra_type | {'file': 'opcodes/lx_32.opc', 'line': 12}
-    let rra_type : bits(4) = inst[23..20];
-    exec_acre(rra_type)
-  }
-  else if (inst & 0xf0ffffff) == 0x0010102b then {
-    // EBREAK | ebreak imm | {'file': 'opcodes/lx_32.opc', 'line': 153}
-    let imm4 : bits(4) = inst[27..24];
-    exec_ebreak()
-  }
-  else if (inst & 0xfff07fff) == 0x0000102b then {
-    // ASSERT | assert SrcL | {'file': 'opcodes/lx_32.opc', 'line': 22}
-    let srcl : bits(5) = inst[19..15];
-    exec_assert(srcl)
-  }
-  else if (inst & 0xfffff07f) == 0x00003043 then {
-    // B.ARG | B.ARG format | {'file': 'opcodes/lx_32.opc', 'line': 25}
-    let format : bits(5) = inst[11..7];
-    exec_b_arg()
-  }
-  else if (inst & 0xfff07fff) == 0x0000402b then {
-    // BC.IVA | bc.iva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 52}
-    let srcl : bits(5) = inst[19..15];
-    exec_bc_iva(srcl)
-  }
-  else if (inst & 0xfff07fff) == 0x0000002b then {
-    // BSE | bse SrcL | {'file': 'opcodes/lx_32.opc', 'line': 56}
-    let srcl : bits(5) = inst[19..15];
-    exec_bse()
+    decoded_block_type_shadow = 0b0100;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0001;
+    exec_bstart_vseq()
   }
-  else if (inst & 0x07ffffff) == 0x00831181 then {
-    // BSTART.ACCCVT | BSTART.ACCCVT DataType | {'file': 'opcodes/lx_32.opc', 'line': 66}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_4(inst) then {
+    // BSTART.ACCCVT | BSTART.ACCCVT DataType | {'file': 'opcodes/lx_32.opc', 'line': 60}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0101;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_acccvt()
   }
-  else if (inst & 0x07ffffff) == 0x00411181 then {
-    // BSTART.MGATHER | BSTART.MGATHER DataType | {'file': 'opcodes/lx_32.opc', 'line': 89}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_5(inst) then {
+    // BSTART.MGATHER | BSTART.MGATHER DataType | {'file': 'opcodes/lx_32.opc', 'line': 81}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1000;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0010;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_mgather()
   }
-  else if (inst & 0x07ffffff) == 0x00811181 then {
-    // BSTART.MGATHER.CAS | BSTART.MGATHER.CAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 90}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_6(inst) then {
+    // BSTART.MGATHER.CAS | BSTART.MGATHER.CAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 82}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1000;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0010;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_mgather_cas()
   }
-  else if (inst & 0x07ffffff) == 0x00611181 then {
-    // BSTART.MGATHER.MASK | BSTART.MGATHER.MASK DataType | {'file': 'opcodes/lx_32.opc', 'line': 91}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_7(inst) then {
+    // BSTART.MGATHER.MASK | BSTART.MGATHER.MASK DataType | {'file': 'opcodes/lx_32.opc', 'line': 83}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1000;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0010;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_mgather_mask()
   }
-  else if (inst & 0x07ffffff) == 0x00511181 then {
-    // BSTART.MSCATTER | BSTART.MSCATTER DataType | {'file': 'opcodes/lx_32.opc', 'line': 92}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_8(inst) then {
+    // BSTART.MSCATTER | BSTART.MSCATTER DataType | {'file': 'opcodes/lx_32.opc', 'line': 84}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1001;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0010;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_mscatter()
   }
-  else if (inst & 0x07ffffff) == 0x00711181 then {
-    // BSTART.MSCATTER.MASK | BSTART.MSCATTER.MASK DataType | {'file': 'opcodes/lx_32.opc', 'line': 93}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_9(inst) then {
+    // BSTART.MSCATTER.MASK | BSTART.MSCATTER.MASK DataType | {'file': 'opcodes/lx_32.opc', 'line': 85}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1001;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0010;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_mscatter_mask()
   }
-  else if (inst & 0x07ffffff) == 0x01031181 then {
-    // BSTART.TGEMV | BSTART.TGEMV DataType | {'file': 'opcodes/lx_32.opc', 'line': 100}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_10(inst) then {
+    // BSTART.TGEMV | BSTART.TGEMV DataType | {'file': 'opcodes/lx_32.opc', 'line': 92}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tgemv()
   }
-  else if (inst & 0x07ffffff) == 0x01231181 then {
-    // BSTART.TGEMV.ACC | BSTART.TGEMV.ACC DataType | {'file': 'opcodes/lx_32.opc', 'line': 102}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_11(inst) then {
+    // BSTART.TGEMV.ACC | BSTART.TGEMV.ACC DataType | {'file': 'opcodes/lx_32.opc', 'line': 94}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tgemv_acc()
   }
-  else if (inst & 0x07ffffff) == 0x01131181 then {
-    // BSTART.TGEMV.BIAS | BSTART.TGEMV.BIAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 101}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_12(inst) then {
+    // BSTART.TGEMV.BIAS | BSTART.TGEMV.BIAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 93}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tgemv_bias()
   }
-  else if (inst & 0x07ffffff) == 0x01431181 then {
-    // BSTART.TGEMVMX | BSTART.TGEMVMX DataType | {'file': 'opcodes/lx_32.opc', 'line': 103}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_13(inst) then {
+    // BSTART.TGEMVMX | BSTART.TGEMVMX DataType | {'file': 'opcodes/lx_32.opc', 'line': 95}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tgemvmx()
   }
-  else if (inst & 0x07ffffff) == 0x01631181 then {
-    // BSTART.TGEMVMX.ACC | BSTART.TGEMVMX.ACC DataType | {'file': 'opcodes/lx_32.opc', 'line': 105}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_14(inst) then {
+    // BSTART.TGEMVMX.ACC | BSTART.TGEMVMX.ACC DataType | {'file': 'opcodes/lx_32.opc', 'line': 97}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tgemvmx_acc()
   }
-  else if (inst & 0x07ffffff) == 0x01531181 then {
-    // BSTART.TGEMVMX.BIAS | BSTART.TGEMVMX.BIAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 104}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_15(inst) then {
+    // BSTART.TGEMVMX.BIAS | BSTART.TGEMVMX.BIAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 96}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tgemvmx_bias()
   }
-  else if (inst & 0x07ffffff) == 0x00011181 then {
-    // BSTART.TLOAD | BSTART.TLOAD DataType | {'file': 'opcodes/lx_32.opc', 'line': 87}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_16(inst) then {
+    // BSTART.TLOAD | BSTART.TLOAD DataType | {'file': 'opcodes/lx_32.opc', 'line': 79}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1000;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0010;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tload()
   }
-  else if (inst & 0x07ffffff) == 0x00031181 then {
-    // BSTART.TMATMUL | BSTART.TMATMUL DataType | {'file': 'opcodes/lx_32.opc', 'line': 94}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_17(inst) then {
+    // BSTART.TMATMUL | BSTART.TMATMUL DataType | {'file': 'opcodes/lx_32.opc', 'line': 86}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tmatmul()
   }
-  else if (inst & 0x07ffffff) == 0x00231181 then {
-    // BSTART.TMATMUL.ACC | BSTART.TMATMUL.ACC DataType | {'file': 'opcodes/lx_32.opc', 'line': 96}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_18(inst) then {
+    // BSTART.TMATMUL.ACC | BSTART.TMATMUL.ACC DataType | {'file': 'opcodes/lx_32.opc', 'line': 88}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tmatmul_acc()
   }
-  else if (inst & 0x07ffffff) == 0x00131181 then {
-    // BSTART.TMATMUL.BIAS | BSTART.TMATMUL.BIAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 95}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_19(inst) then {
+    // BSTART.TMATMUL.BIAS | BSTART.TMATMUL.BIAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 87}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tmatmul_bias()
   }
-  else if (inst & 0x07ffffff) == 0x00431181 then {
-    // BSTART.TMATMULMX | BSTART.TMATMULMX DataType | {'file': 'opcodes/lx_32.opc', 'line': 97}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_20(inst) then {
+    // BSTART.TMATMULMX | BSTART.TMATMULMX DataType | {'file': 'opcodes/lx_32.opc', 'line': 89}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tmatmulmx()
   }
-  else if (inst & 0x07ffffff) == 0x00631181 then {
-    // BSTART.TMATMULMX.ACC | BSTART.TMATMULMX.ACC DataType | {'file': 'opcodes/lx_32.opc', 'line': 99}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_21(inst) then {
+    // BSTART.TMATMULMX.ACC | BSTART.TMATMULMX.ACC DataType | {'file': 'opcodes/lx_32.opc', 'line': 91}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tmatmulmx_acc()
   }
-  else if (inst & 0x07ffffff) == 0x00531181 then {
-    // BSTART.TMATMULMX.BIAS | BSTART.TMATMULMX.BIAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 98}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_22(inst) then {
+    // BSTART.TMATMULMX.BIAS | BSTART.TMATMULMX.BIAS DataType | {'file': 'opcodes/lx_32.opc', 'line': 90}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1111;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0100;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tmatmulmx_bias()
   }
-  else if (inst & 0x07ffffff) == 0x00211181 then {
-    // BSTART.TMOV | BSTART.TMOV DataType | {'file': 'opcodes/lx_32.opc', 'line': 106}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_23(inst) then {
+    // BSTART.TMOV | BSTART.TMOV DataType | {'file': 'opcodes/lx_32.opc', 'line': 98}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1010;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0011;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tmov()
   }
-  else if (inst & 0x07ffffff) == 0x00311181 then {
-    // BSTART.TPREFETCH | BSTART.TPREFETCH DataType | {'file': 'opcodes/lx_32.opc', 'line': 107}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_24(inst) then {
+    // BSTART.TPREFETCH | BSTART.TPREFETCH DataType | {'file': 'opcodes/lx_32.opc', 'line': 99}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1000;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0010;
+    decoded_block_contract_kind_shadow = 0b0110;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tprefetch()
   }
-  else if (inst & 0x07ffffff) == 0x00111181 then {
-    // BSTART.TSTORE | BSTART.TSTORE DataType | {'file': 'opcodes/lx_32.opc', 'line': 108}
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_25(inst) then {
+    // BSTART.TSTORE | BSTART.TSTORE DataType | {'file': 'opcodes/lx_32.opc', 'line': 100}
     let datatype : bits(5) = inst[31..27];
     decoded_block_target_pc_shadow = read_pc_or_tpc();
     decoded_block_type_shadow = 0b1001;
     decoded_block_xfer_kind_shadow = block_xfer_fall();
     decoded_block_contract_kind_shadow = 0b0010;
+    decoded_tile_datatype_shadow = datatype;
     exec_bstart_tstore()
   }
-  else if (inst & 0xfff07fff) == 0x0010002b then {
-    // BWE | bwe SrcL | {'file': 'opcodes/lx_32.opc', 'line': 112}
-    let srcl : bits(5) = inst[19..15];
-    exec_bwe()
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_26(inst) then {
+    // BSTART.TEPL | BSTART.TEPL Mode, Function, DataType | {'file': 'opcodes/lx_32.opc', 'line': 78}
+    let datatype : bits(5) = inst[31..27];
+    let function_field : bits(5) = inst[24..20];
+    let mode : bits(2) = inst[26..25];
+    decoded_block_target_pc_shadow = read_pc_or_tpc();
+    decoded_block_type_shadow = 0b1101;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0110;
+    decoded_tile_datatype_shadow = datatype;
+    exec_bstart_tepl()
   }
-  else if (inst & 0xfff07fff) == 0x0020002b then {
-    // BWI | bwi SrcL | {'file': 'opcodes/lx_32.opc', 'line': 113}
-    let srcl : bits(5) = inst[19..15];
-    exec_bwi()
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_27(inst) then {
+    // BSTART.FP | BSTART.FP FALL<, fixup_label> | {'file': 'opcodes/lx_32.opc', 'line': 67}
+    let simm17 : bits(17) = inst[31..15];
+    decoded_block_target_pc_shadow = decode_block_target17(simm17);
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_fp()
   }
-  else if (inst & 0xfff07fff) == 0x0030002b then {
-    // BWT | bwt SrcL | {'file': 'opcodes/lx_32.opc', 'line': 114}
-    let srcl : bits(5) = inst[19..15];
-    exec_bwt()
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_28(inst) then {
+    // BSTART.STD | BSTART.STD FALL<, fixup_label> | {'file': 'opcodes/lx_32.opc', 'line': 72}
+    let simm17 : bits(17) = inst[31..15];
+    decoded_block_target_pc_shadow = decode_block_target17(simm17);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_std()
   }
-  else if (inst & 0xfff07fff) == 0x0060602b then {
-    // DC.CISW | dc.cisw SrcL | {'file': 'opcodes/lx_32.opc', 'line': 140}
-    let srcl : bits(5) = inst[19..15];
-    exec_dc_cisw(srcl)
+  else if decode_execute32_opcode_0b0000001_funct3_0b001_match_29(inst) then {
+    // BSTART.SYS | BSTART.SYS FALL<, fixup_label> | {'file': 'opcodes/lx_32.opc', 'line': 77}
+    let simm17 : bits(17) = inst[31..15];
+    decoded_block_target_pc_shadow = decode_block_target17(simm17);
+    decoded_block_type_shadow = 0b0001;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_sys()
   }
-  else if (inst & 0xfff07fff) == 0x0030602b then {
-    // DC.CIVA | dc.civa SrcL | {'file': 'opcodes/lx_32.opc', 'line': 141}
-    let srcl : bits(5) = inst[19..15];
-    exec_dc_civa(srcl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfff07fff) == 0x0050602b then {
-    // DC.CSW | dc.csw SrcL | {'file': 'opcodes/lx_32.opc', 'line': 142}
-    let srcl : bits(5) = inst[19..15];
-    exec_dc_csw(srcl)
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00002101
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b010_match_1(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00002001
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000001_funct3_0b010_match_0(inst) then {
+    // BSTART.FP | BSTART.FP DIRECT, <label> | {'file': 'opcodes/lx_32.opc', 'line': 64}
+    let simm17 : bits(17) = inst[31..15];
+    decoded_block_target_pc_shadow = decode_block_target17(simm17);
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_direct();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_fp()
   }
-  else if (inst & 0xfff07fff) == 0x0020602b then {
-    // DC.CVA | dc.cva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 143}
-    let srcl : bits(5) = inst[19..15];
-    exec_dc_cva(srcl)
+  else if decode_execute32_opcode_0b0000001_funct3_0b010_match_1(inst) then {
+    // BSTART.STD | BSTART.STD DIRECT, <label> | {'file': 'opcodes/lx_32.opc', 'line': 76}
+    let simm17 : bits(17) = inst[31..15];
+    decoded_block_target_pc_shadow = decode_block_target17(simm17);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_direct();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_std()
   }
-  else if (inst & 0xfff07fff) == 0x0040602b then {
-    // DC.ISW | dc.isw SrcL | {'file': 'opcodes/lx_32.opc', 'line': 145}
-    let srcl : bits(5) = inst[19..15];
-    exec_dc_isw(srcl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfff07fff) == 0x0000602b then {
-    // DC.IVA | dc.iva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 146}
-    let srcl : bits(5) = inst[19..15];
-    exec_dc_iva(srcl)
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00003101
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b011_match_1(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00003001
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000001_funct3_0b011_match_0(inst) then {
+    // BSTART.FP | BSTART.FP COND, <label> | {'file': 'opcodes/lx_32.opc', 'line': 63}
+    let simm17 : bits(17) = inst[31..15];
+    decoded_block_target_pc_shadow = decode_block_target17(simm17);
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_cond();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_fp()
   }
-  else if (inst & 0xfff07fff) == 0x0070602b then {
-    // DC.ZVA | dc.zva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 147}
-    let srcl : bits(5) = inst[19..15];
-    exec_dc_zva(srcl)
+  else if decode_execute32_opcode_0b0000001_funct3_0b011_match_1(inst) then {
+    // BSTART.STD | BSTART.STD COND, <label> | {'file': 'opcodes/lx_32.opc', 'line': 70}
+    let simm17 : bits(17) = inst[31..15];
+    decoded_block_target_pc_shadow = decode_block_target17(simm17);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_cond();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_std()
   }
-  else if (inst & 0xfff07fff) == 0x0000502b then {
-    // IC.IVA | ic.iva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 189}
-    let srcl : bits(5) = inst[19..15];
-    exec_ic_iva(srcl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfff07fff) == 0x0000403b then {
-    // SETC.TGT | setc.tgt SrcL | {'file': 'opcodes/lx_32.opc', 'line': 302}
-    let srcl : bits(5) = inst[19..15];
-    exec_setc_tgt(srcl, 0b00)
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00004101
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b100_match_1(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00004001
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000001_funct3_0b100_match_0(inst) then {
+    // BSTART.FP | BSTART.FP CALL, <label> | {'file': 'opcodes/lx_32.opc', 'line': 66}
+    let simm17 : bits(17) = inst[31..15];
+    decoded_block_target_pc_shadow = decode_block_target17(simm17);
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_call();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_fp()
   }
-  else if (inst & 0xfff07fff) == 0x0000702b then {
-    // TLB.IA | tlb.ia SrcL | {'file': 'opcodes/lx_32.opc', 'line': 345}
-    let srcl : bits(5) = inst[19..15];
-    exec_tlb_ia(srcl)
+  else if decode_execute32_opcode_0b0000001_funct3_0b100_match_1(inst) then {
+    // BSTART.STD | BSTART.STD CALL, <label> | {'file': 'opcodes/lx_32.opc', 'line': 74}
+    let simm17 : bits(17) = inst[31..15];
+    decoded_block_target_pc_shadow = decode_block_target17(simm17);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_call();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_std()
   }
-  else if (inst & 0xfff07fff) == 0x0020702b then {
-    // TLB.IAV | tlb.iav SrcL | {'file': 'opcodes/lx_32.opc', 'line': 347}
-    let srcl : bits(5) = inst[19..15];
-    exec_tlb_iav(srcl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfff07fff) == 0x0010702b then {
-    // TLB.IV | tlb.iv SrcL | {'file': 'opcodes/lx_32.opc', 'line': 348}
-    let srcl : bits(5) = inst[19..15];
-    exec_tlb_iv(srcl)
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x00005101
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b101_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x00005001
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000001_funct3_0b101_match_0(inst) then {
+    // BSTART.FP | BSTART.FP IND | {'file': 'opcodes/lx_32.opc', 'line': 62}
+    decoded_block_target_pc_shadow = read_pc_or_tpc();
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_ind();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_fp()
   }
-  else if (inst & 0x03ffffff) == 0x00000023 then {
-    // B.CATR | B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr} | {'file': 'opcodes/lx_32.opc', 'line': 23}
-    let dr : bits(1) = inst[26];
-    let aq : bits(1) = inst[29];
-    let atom : bits(1) = inst[30];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[28];
-    let trap : bits(1) = inst[31];
-    decoded_bcatr_raw_shadow = sail_zero_extend(inst, 64);
-    exec_b_catr()
+  else if decode_execute32_opcode_0b0000001_funct3_0b101_match_1(inst) then {
+    // BSTART.STD | BSTART.STD IND | {'file': 'opcodes/lx_32.opc', 'line': 75}
+    decoded_block_target_pc_shadow = read_pc_or_tpc();
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_ind();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_std()
   }
-  else if (inst & 0x9fff707f) == 0x01c05013 then {
-    // B.IOT | B.IOT SrcTile0<.reuse>, <last> | {'file': 'opcodes/lx_32.opc', 'line': 44}
-    let l : bits(1) = inst[29];
-    let s0r : bits(1) = inst[30];
-    let srctile0 : bits(6) = inst[15] @ inst[11..7];
-    exec_b_iot()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xc03fffff) == 0x00006013 then {
-    // B.IOT | B.IOT <last>, ->DstTile<Size> | {'file': 'opcodes/lx_32.opc', 'line': 42}
-    let dsttile : bits(3) = inst[24..22];
-    let l : bits(1) = inst[29];
-    let imm4 : bits(4) = inst[28..25];
-    exec_b_iot()
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x00006101
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b110_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x00006001
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b110_match_2(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00006f81
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000001_funct3_0b110_match_0(inst) then {
+    // BSTART.FP | BSTART.FP ICALL | {'file': 'opcodes/lx_32.opc', 'line': 65}
+    decoded_block_target_pc_shadow = read_pc_or_tpc();
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_call();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_fp()
   }
-  else if (inst & 0xf00fffff) == 0x0000202b then {
-    // FENCE.D | fence.d pred_imm, succ_imm | {'file': 'opcodes/lx_32.opc', 'line': 163}
-    let pred_imm : bits(4) = inst[27..24];
-    let succ_imm : bits(4) = inst[23..20];
-    exec_fence_d()
+  else if decode_execute32_opcode_0b0000001_funct3_0b110_match_1(inst) then {
+    // BSTART.STD | BSTART.STD ICALL | {'file': 'opcodes/lx_32.opc', 'line': 73}
+    decoded_block_target_pc_shadow = read_pc_or_tpc();
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_call();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_std()
   }
-  else if (inst & 0x060fffff) == 0x00031181 & (inst[24..20] != 0b00000) & (inst[24..20] != 0b00001) & (inst[24..20] != 0b00010) & (inst[24..20] != 0b00100) & (inst[24..20] != 0b00101) & (inst[24..20] != 0b00110) & (inst[24..20] != 0b01000) & (inst[24..20] != 0b10000) & (inst[24..20] != 0b10001) & (inst[24..20] != 0b10010) & (inst[24..20] != 0b10100) & (inst[24..20] != 0b10101) & (inst[24..20] != 0b10110) then {
-    // BSTART.CUBE | BSTART.CUBE Function, DataType | {'file': 'opcodes/lx_32.opc', 'line': 67}
-    let datatype : bits(5) = inst[31..27];
-    let function_field : bits(5) = inst[24..20];
+  else if decode_execute32_opcode_0b0000001_funct3_0b110_match_2(inst) then {
+    // XB | XB ACR-ID, C-ID | {'file': 'opcodes/lx_32.opc', 'line': 342}
+    let acr_id : bits(10) = inst[24..15];
+    let cross_bid : bits(7) = inst[31..25];
+    exec_xb(sail_zero_extend(acr_id, 12), sail_zero_extend(cross_bid, 8))
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x00007101
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b111_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x00007001
+}
+
+function decode_execute32_opcode_0b0000001_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000001_funct3_0b111_match_0(inst) then {
+    // BSTART.FP | BSTART.FP RET | {'file': 'opcodes/lx_32.opc', 'line': 61}
     decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b1011;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0110;
-    exec_bstart_cube()
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_ret();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_fp()
   }
-  else if (inst & 0x060fffff) == 0x00039181 then {
-    // BSTART.FIXP | BSTART.FIXP TileOp, DataType | {'file': 'opcodes/lx_32.opc', 'line': 68}
-    let datatype : bits(5) = inst[31..27];
-    let function_field : bits(5) = inst[24..20];
+  else if decode_execute32_opcode_0b0000001_funct3_0b111_match_1(inst) then {
+    // BSTART.STD | BSTART.STD RET | {'file': 'opcodes/lx_32.opc', 'line': 71}
     decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b1110;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0110;
-    exec_bstart_fixp()
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_ret();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_std()
   }
-  else if (inst & 0xfe007fff) == 0x0000700b then {
-    // DMA | dma [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 148}
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    exec_dma(srcl, srcr)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf9f0707f) == 0x0000007b then {
-    // FABS | fabs.{T} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 154}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_fabs(regdst, srcl, srctype)
+}
+
+function decode_execute32_opcode_0b0000001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0000001_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0000001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0000001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0000001_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0000001_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0000001_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0000001_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b0000001_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf9f0707f) == 0x0000307b then {
-    // FEXP | fexp.{T} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 169}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_fexp(regdst, srcl, srctype)
+}
+
+function decode_execute32_opcode_0b0000011_fallback_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000007f) == 0x00000003
+}
+
+function decode_execute32_opcode_0b0000011_fallback(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000011_fallback_match_0(inst) then {
+    // B.TEXT | B.TEXT <label> | {'file': 'opcodes/lx_32.opc', 'line': 43}
+    let simm25 : bits(25) = inst[31..7];
+    exec_b_text()
   }
-  else if (inst & 0xf9f0707f) == 0x0000207b then {
-    // FRECIP | frecip.{T} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 183}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_frecip(regdst, srcl, srctype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf9f0707f) == 0x0000107b then {
-    // FSQRT | fsqrt.{T} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 186}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_fsqrt(regdst, srcl, srctype)
+}
+
+function decode_execute32_opcode_0b0000011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    _ => decode_execute32_opcode_0b0000011_fallback(inst)
   }
-  else if (inst & 0xf4007fff) == 0x0000500b then {
-    // SD.ADD | sd.add<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 274}
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000005
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000101_funct3_0b000_match_0(inst) then {
+    // ADD | add SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 13}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_sd_add(srcl, srcr, far, rl)
+    let srcrtype : bits(2) = inst[26..25];
+    let shamt : bits(5) = inst[31..27];
+    exec_add(regdst, srcl, srcr, srcrtype, shamt)
   }
-  else if (inst & 0xf4007fff) == 0x1000500b then {
-    // SD.AND | sd.and<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 275}
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_sd_and(srcl, srcr, far, rl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf4007fff) == 0x2000500b then {
-    // SD.OR | sd.or<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 276}
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001005
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000101_funct3_0b001_match_0(inst) then {
+    // SUB | sub SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 316}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_sd_or(srcl, srcr, far, rl)
+    let srcrtype : bits(2) = inst[26..25];
+    let shamt : bits(5) = inst[31..27];
+    exec_sub(regdst, srcl, srcr, srcrtype, shamt)
   }
-  else if (inst & 0xf4007fff) == 0x4000500b then {
-    // SD.SMAX | sd.smax<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 278}
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_sd_smax(srcl, srcr, far, rl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf4007fff) == 0x5000500b then {
-    // SD.SMIN | sd.smin<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 279}
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002005
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000101_funct3_0b010_match_0(inst) then {
+    // AND | and SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 18}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_sd_smin(srcl, srcr, far, rl)
+    let srcrtype : bits(2) = inst[26..25];
+    let shamt : bits(5) = inst[31..27];
+    exec_and(regdst, srcl, srcr, srcrtype, shamt)
   }
-  else if (inst & 0xf4007fff) == 0x6000500b then {
-    // SD.UMAX | sd.umax<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 281}
-    let srcl : bits(5) = inst[19..15];
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003005
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000101_funct3_0b011_match_0(inst) then {
+    // OR | or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 246}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_sd_umax(srcl, srcr, far, rl)
+    let srcrtype : bits(2) = inst[26..25];
+    let shamt : bits(5) = inst[31..27];
+    exec_or(regdst, srcl, srcr, srcrtype, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf4007fff) == 0x7000500b then {
-    // SD.UMIN | sd.umin<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 282}
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004005
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000101_funct3_0b100_match_0(inst) then {
+    // XOR | xor SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 343}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_sd_umin(srcl, srcr, far, rl)
+    let srcrtype : bits(2) = inst[26..25];
+    let shamt : bits(5) = inst[31..27];
+    exec_xor(regdst, srcl, srcr, srcrtype, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf4007fff) == 0x3000500b then {
-    // SD.XOR | sd.xor<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 283}
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00005005
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000101_funct3_0b101_match_0(inst) then {
+    // SRL | srl SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 309}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_sd_xor(srcl, srcr, far, rl)
+    exec_srl(regdst, srcl, srcr)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00006005
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000101_funct3_0b110_match_0(inst) then {
+    // SRA | sra SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 305}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_sra(regdst, srcl, srcr)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf8007fff) == 0x00002065 then {
-    // SETC.AND | setc.and SrcL, SrcR<.sw, .uw, .not> | {'file': 'opcodes/lx_32.opc', 'line': 286}
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00007005
+}
+
+function decode_execute32_opcode_0b0000101_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000101_funct3_0b111_match_0(inst) then {
+    // SLL | sll SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 301}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_setc_and(srcl, srcr, srcrtype)
+    exec_sll(regdst, srcl, srcr)
   }
-  else if (inst & 0xf8007fff) == 0x00000065 then {
-    // SETC.EQ | setc.eq SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 288}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0000101(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0000101_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0000101_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0000101_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0000101_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0000101_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0000101_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0000101_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b0000101_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0000111_fallback_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00000fff) == 0x00000507
+}
+
+function decode_execute32_opcode_0b0000111_fallback_match_1(inst : bits(32)) -> bool = {
+  and_bool_no_flow((inst & 0x0000007f) == 0x00000007, (inst[11..7] != 0b01010))
+}
+
+function decode_execute32_opcode_0b0000111_fallback(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0000111_fallback_match_0(inst) then {
+    // SETRET | setret uimm, ->Ra | {'file': 'opcodes/lx_32.opc', 'line': 295}
+    let imm20 : bits(20) = inst[31..12];
+    exec_setret(imm20)
+  }
+  else if decode_execute32_opcode_0b0000111_fallback_match_1(inst) then {
+    // ADDTPC | addtpc simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 16}
+    let regdst : bits(5) = inst[11..7];
+    let imm20 : bits(20) = inst[31..12];
+    exec_addtpc(regdst, imm20)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0000111(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    _ => decode_execute32_opcode_0b0000111_fallback(inst)
+  }
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000009
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001001_funct3_0b000_match_0(inst) then {
+    // LB | lb [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 184}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let srcrtype : bits(2) = inst[26..25];
-    exec_setc_eq(srcl, srcr, srcrtype)
+    let shamt : bits(5) = inst[31..27];
+    exec_lb(regdst, srcl, srcr, srcrtype, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf8007fff) == 0x00005065 then {
-    // SETC.GE | setc.ge SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 290}
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001009
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001001_funct3_0b001_match_0(inst) then {
+    // LH | lh [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 202}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let srcrtype : bits(2) = inst[26..25];
-    exec_setc_ge(srcl, srcr, srcrtype)
+    let shamt : bits(5) = inst[31..27];
+    exec_lh(regdst, srcl, srcr, srcrtype, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf8007fff) == 0x00007065 then {
-    // SETC.GEU | setc.geu SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 292}
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002009
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001001_funct3_0b010_match_0(inst) then {
+    // LW | lw [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 216}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let srcrtype : bits(2) = inst[26..25];
-    exec_setc_geu(srcl, srcr, srcrtype)
+    let shamt : bits(5) = inst[31..27];
+    exec_lw(regdst, srcl, srcr, srcrtype, shamt)
   }
-  else if (inst & 0xf8007fff) == 0x00004065 then {
-    // SETC.LT | setc.lt SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 294}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003009
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001001_funct3_0b011_match_0(inst) then {
+    // LD | ld [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 190}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let srcrtype : bits(2) = inst[26..25];
-    exec_setc_lt(srcl, srcr, srcrtype)
+    let shamt : bits(5) = inst[31..27];
+    exec_ld(regdst, srcl, srcr, srcrtype, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf8007fff) == 0x00006065 then {
-    // SETC.LTU | setc.ltu SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 296}
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004009
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001001_funct3_0b100_match_0(inst) then {
+    // LBU | lbu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 187}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let srcrtype : bits(2) = inst[26..25];
-    exec_setc_ltu(srcl, srcr, srcrtype)
+    let shamt : bits(5) = inst[31..27];
+    exec_lbu(regdst, srcl, srcr, srcrtype, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf8007fff) == 0x00001065 then {
-    // SETC.NE | setc.ne SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 298}
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00005009
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001001_funct3_0b101_match_0(inst) then {
+    // LHU | lhu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 206}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let srcrtype : bits(2) = inst[26..25];
-    exec_setc_ne(srcl, srcr, srcrtype)
+    let shamt : bits(5) = inst[31..27];
+    exec_lhu(regdst, srcl, srcr, srcrtype, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf8007fff) == 0x00003065 then {
-    // SETC.OR | setc.or SrcL, SrcR<.sw, .uw, .not> | {'file': 'opcodes/lx_32.opc', 'line': 300}
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00006009
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001001_funct3_0b110_match_0(inst) then {
+    // LWU | lwu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 228}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let srcrtype : bits(2) = inst[26..25];
-    exec_setc_or(srcl, srcr, srcrtype)
+    let shamt : bits(5) = inst[31..27];
+    exec_lwu(regdst, srcl, srcr, srcrtype, shamt)
   }
-  else if (inst & 0xf4007fff) == 0x0000300b then {
-    // SW.ADD | sw.add<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 329}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00007009
+}
+
+function decode_execute32_opcode_0b0001001_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001001_funct3_0b111_match_0(inst) then {
+    // PRF | prf [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>] | {'file': 'opcodes/lx_32.opc', 'line': 250}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    let shamt : bits(5) = inst[31..27];
+    exec_prf(regdst, srcl, srcr, srcrtype, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0001001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0001001_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0001001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0001001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0001001_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0001001_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0001001_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0001001_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b0001001_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x0000000b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b000_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x3000000b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b000_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x1000000b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b000_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x2000000b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001011_funct3_0b000_match_0(inst) then {
+    // LR.B | lr.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 210}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srczero : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
     let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sw_add(srcl, srcr, far, rl)
+    exec_lr_b(regdst, srcl, aq, far, rl)
   }
-  else if (inst & 0xf4007fff) == 0x1000300b then {
-    // SW.AND | sw.and<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 330}
+  else if decode_execute32_opcode_0b0001011_funct3_0b000_match_1(inst) then {
+    // LR.D | lr.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 211}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
+    let srczero : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
     let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sw_and(srcl, srcr, far, rl)
+    exec_lr_d(regdst, srcl, aq, far, rl)
   }
-  else if (inst & 0xf4007fff) == 0x2000300b then {
-    // SW.OR | sw.or<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 331}
+  else if decode_execute32_opcode_0b0001011_funct3_0b000_match_2(inst) then {
+    // LR.H | lr.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 212}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
+    let srczero : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
     let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sw_or(srcl, srcr, far, rl)
+    exec_lr_h(regdst, srcl, aq, far, rl)
   }
-  else if (inst & 0xf4007fff) == 0x4000300b then {
-    // SW.SMAX | sw.smax<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 333}
+  else if decode_execute32_opcode_0b0001011_funct3_0b000_match_3(inst) then {
+    // LR.W | lr.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 213}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
+    let srczero : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
     let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sw_smax(srcl, srcr, far, rl)
+    exec_lr_w(regdst, srcl, aq, far, rl)
   }
-  else if (inst & 0xf4007fff) == 0x5000300b then {
-    // SW.SMIN | sw.smin<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 334}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x0000100b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b001_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x3000100b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b001_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x1000100b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b001_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x2000100b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001011_funct3_0b001_match_0(inst) then {
+    // SC.B | sc.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 260}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
     let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sw_smin(srcl, srcr, far, rl)
+    exec_sc_b(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xf4007fff) == 0x6000300b then {
-    // SW.UMAX | sw.umax<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 336}
+  else if decode_execute32_opcode_0b0001011_funct3_0b001_match_1(inst) then {
+    // SC.D | sc.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 261}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
     let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sw_umax(srcl, srcr, far, rl)
+    exec_sc_d(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xf4007fff) == 0x7000300b then {
-    // SW.UMIN | sw.umin<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 337}
+  else if decode_execute32_opcode_0b0001011_funct3_0b001_match_2(inst) then {
+    // SC.H | sc.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 262}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
     let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sw_umin(srcl, srcr, far, rl)
+    exec_sc_h(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xf4007fff) == 0x3000300b then {
-    // SW.XOR | sw.xor<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 338}
+  else if decode_execute32_opcode_0b0001011_funct3_0b001_match_3(inst) then {
+    // SC.W | sc.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 263}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
     let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sw_xor(srcl, srcr, far, rl)
-  }
-  else if (inst & 0x803f707f) == 0x00005013 & (inst[24..22] != 0b111) then {
-    // B.IOT | B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size> | {'file': 'opcodes/lx_32.opc', 'line': 41}
-    let dsttile : bits(3) = inst[24..22];
-    let l : bits(1) = inst[29];
-    let s0r : bits(1) = inst[30];
-    let srctile0 : bits(6) = inst[15] @ inst[11..7];
-    let imm4 : bits(4) = inst[28..25];
-    exec_b_iot()
+    exec_sc_w(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0x1fc0707f) == 0x01c04013 then {
-    // B.IOT | B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last> | {'file': 'opcodes/lx_32.opc', 'line': 43}
-    let l : bits(1) = inst[29];
-    let s0r : bits(1) = inst[30];
-    let s1r : bits(1) = inst[31];
-    let srctile0 : bits(6) = inst[15] @ inst[11..7];
-    let srctile1 : bits(6) = inst[21..16];
-    exec_b_iot()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x06007fff) == 0x02001181 then {
-    // BSTART.TEPL | BSTART.TEPL TileOpcode, DataType | {'file': 'opcodes/lx_32.opc', 'line': 86}
-    let datatype : bits(5) = inst[31..27];
-    let tileopcode : bits(10) = inst[24..15];
-    decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b1101;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0110;
-    exec_bstart_tepl()
-  }
-  else if (inst & 0xf9ffffff) == 0x00001181 then {
-    // BSTART.MPAR | BSTART.MPAR <VS8, VS16> | {'file': 'opcodes/lx_32.opc', 'line': 76}
-    let mode : bits(2) = inst[26..25];
-    decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0101;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0001;
-    exec_bstart_mpar()
-  }
-  else if (inst & 0xf9ffffff) == 0x00009181 then {
-    // BSTART.MSEQ | BSTART.MSEQ <VS8, VS16> | {'file': 'opcodes/lx_32.opc', 'line': 77}
-    let mode : bits(2) = inst[26..25];
-    decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0110;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0001;
-    exec_bstart_mseq()
-  }
-  else if (inst & 0xf9ffffff) == 0x00021181 then {
-    // BSTART.VPAR | BSTART.VPAR <VS8, VS16> | {'file': 'opcodes/lx_32.opc', 'line': 109}
-    let mode : bits(2) = inst[26..25];
-    decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0011;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0001;
-    exec_bstart_vpar()
-  }
-  else if (inst & 0xf9ffffff) == 0x00029181 then {
-    // BSTART.VSEQ | BSTART.VSEQ <VS8, VS16> | {'file': 'opcodes/lx_32.opc', 'line': 110}
-    let mode : bits(2) = inst[26..25];
-    decoded_block_target_pc_shadow = read_pc_or_tpc();
-    decoded_block_type_shadow = 0b0100;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0001;
-    exec_bstart_vseq()
-  }
-  else if (inst & 0xfe00707f) == 0x00000057 then {
-    // DIV | div SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 149}
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x0000200b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b010_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x1000200b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b010_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x2000200b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b010_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x4000200b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b010_match_4(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x5000200b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b010_match_5(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x6000200b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b010_match_6(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x7000200b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b010_match_7(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x3000200b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001011_funct3_0b010_match_0(inst) then {
+    // LW.ADD | lw.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 217}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_div(regdst, srcl, srcr)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_lw_add(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00001057 then {
-    // DIVU | divu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 150}
+  else if decode_execute32_opcode_0b0001011_funct3_0b010_match_1(inst) then {
+    // LW.AND | lw.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 218}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_divu(regdst, srcl, srcr)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_lw_and(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00003057 then {
-    // DIVUW | divuw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 151}
+  else if decode_execute32_opcode_0b0001011_funct3_0b010_match_2(inst) then {
+    // LW.OR | lw.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 219}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_divuw(regdst, srcl, srcr)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_lw_or(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00002057 then {
-    // DIVW | divw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 152}
+  else if decode_execute32_opcode_0b0001011_funct3_0b010_match_3(inst) then {
+    // LW.SMAX | lw.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 221}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_divw(regdst, srcl, srcr)
-  }
-  else if (inst & 0x06007fff) == 0x00003031 then {
-    // ERCOV | ERCOV [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind] | {'file': 'opcodes/lx_32.opc', 'line': 249}
-    let regsrc0 : bits(5) = inst[19..15];
-    let regsrc1 : bits(5) = inst[24..20];
-    let regsrc2 : bits(5) = inst[31..27];
-    exec_ercov(regsrc0, regsrc1, regsrc2)
-  }
-  else if (inst & 0x06007fff) == 0x00002031 then {
-    // ESAVE | ESAVE [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind] | {'file': 'opcodes/lx_32.opc', 'line': 248}
-    let regsrc0 : bits(5) = inst[19..15];
-    let regsrc1 : bits(5) = inst[24..20];
-    let regsrc2 : bits(5) = inst[31..27];
-    exec_esave(regsrc0, regsrc1, regsrc2)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_lw_smax(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x0000405b then {
-    // MAX | max SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 242}
+  else if decode_execute32_opcode_0b0001011_funct3_0b010_match_4(inst) then {
+    // LW.SMIN | lw.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 222}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_max(regdst, srcl, srcr)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_lw_smin(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x0800405b then {
-    // MAXU | maxu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 243}
+  else if decode_execute32_opcode_0b0001011_funct3_0b010_match_5(inst) then {
+    // LW.UMAX | lw.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 223}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_maxu(regdst, srcl, srcr)
-  }
-  else if (inst & 0x06007fff) == 0x00000031 then {
-    // MCOPY | MCOPY [RegSrc0, RegSrc1, RegSrc2] | {'file': 'opcodes/lx_32.opc', 'line': 244}
-    let regsrc0 : bits(5) = inst[19..15];
-    let regsrc1 : bits(5) = inst[24..20];
-    let regsrc2 : bits(5) = inst[31..27];
-    exec_mcopy(regsrc0, regsrc1, regsrc2)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_lw_umax(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x0000505b then {
-    // MIN | min SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 245}
+  else if decode_execute32_opcode_0b0001011_funct3_0b010_match_6(inst) then {
+    // LW.UMIN | lw.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 224}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_min(regdst, srcl, srcr)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_lw_umin(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x0800505b then {
-    // MINU | minu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 246}
+  else if decode_execute32_opcode_0b0001011_funct3_0b010_match_7(inst) then {
+    // LW.XOR | lw.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 225}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_minu(regdst, srcl, srcr)
-  }
-  else if (inst & 0x06007fff) == 0x00001031 then {
-    // MSET | MSET [RegSrc0, RegSrc1, RegSrc2] | {'file': 'opcodes/lx_32.opc', 'line': 247}
-    let regsrc0 : bits(5) = inst[19..15];
-    let regsrc1 : bits(5) = inst[24..20];
-    let regsrc2 : bits(5) = inst[31..27];
-    exec_mset(regsrc0, regsrc1, regsrc2)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_lw_xor(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00000047 then {
-    // MUL | mul SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 250}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    exec_mul(regdst, srcl, srcr)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfe00707f) == 0x00001047 then {
-    // MULU | mulu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 251}
-    let regdst : bits(5) = inst[11..7];
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x0000300b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b011_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x1000300b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b011_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x2000300b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b011_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x4000300b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b011_match_4(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x5000300b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b011_match_5(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x6000300b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b011_match_6(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x7000300b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b011_match_7(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x3000300b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001011_funct3_0b011_match_0(inst) then {
+    // SW.ADD | sw.add<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 321}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_mulu(regdst, srcl, srcr)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sw_add(srcl, srcr, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00003047 then {
-    // MULUW | muluw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 252}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b011_match_1(inst) then {
+    // SW.AND | sw.and<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 322}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_muluw(regdst, srcl, srcr)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sw_and(srcl, srcr, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00002047 then {
-    // MULW | mulw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 253}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b011_match_2(inst) then {
+    // SW.OR | sw.or<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 323}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_mulw(regdst, srcl, srcr)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sw_or(srcl, srcr, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00004057 then {
-    // REM | rem SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 260}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b011_match_3(inst) then {
+    // SW.SMAX | sw.smax<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 325}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_rem(regdst, srcl, srcr)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sw_smax(srcl, srcr, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00005057 then {
-    // REMU | remu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 261}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b011_match_4(inst) then {
+    // SW.SMIN | sw.smin<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 326}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_remu(regdst, srcl, srcr)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sw_smin(srcl, srcr, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00007057 then {
-    // REMUW | remuw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 262}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b011_match_5(inst) then {
+    // SW.UMAX | sw.umax<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 328}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_remuw(regdst, srcl, srcr)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sw_umax(srcl, srcr, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00006057 then {
-    // REMW | remw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 263}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b011_match_6(inst) then {
+    // SW.UMIN | sw.umin<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 329}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_remw(regdst, srcl, srcr)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sw_umin(srcl, srcr, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00007005 then {
-    // SLL | sll SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 309}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b011_match_7(inst) then {
+    // SW.XOR | sw.xor<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 330}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_sll(regdst, srcl, srcr)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sw_xor(srcl, srcr, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00007035 then {
-    // SLLIW | slliw SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 311}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[24..20];
-    exec_slliw(regdst, srcl, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfe00707f) == 0x00007025 then {
-    // SLLW | sllw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 312}
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x0000400b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b100_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x1000400b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b100_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x2000400b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b100_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x4000400b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b100_match_4(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x5000400b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b100_match_5(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x6000400b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b100_match_6(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x7000400b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b100_match_7(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x3000400b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001011_funct3_0b100_match_0(inst) then {
+    // LD.ADD | ld.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 191}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_sllw(regdst, srcl, srcr)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_ld_add(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00006005 then {
-    // SRA | sra SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 313}
+  else if decode_execute32_opcode_0b0001011_funct3_0b100_match_1(inst) then {
+    // LD.AND | ld.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 192}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_sra(regdst, srcl, srcr)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_ld_and(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00006035 then {
-    // SRAIW | sraiw SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 315}
+  else if decode_execute32_opcode_0b0001011_funct3_0b100_match_2(inst) then {
+    // LD.OR | ld.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 193}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[24..20];
-    exec_sraiw(regdst, srcl, shamt)
+    let srcr : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_ld_or(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00006025 then {
-    // SRAW | sraw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 316}
+  else if decode_execute32_opcode_0b0001011_funct3_0b100_match_3(inst) then {
+    // LD.SMAX | ld.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 195}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_sraw(regdst, srcl, srcr)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_ld_smax(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00005005 then {
-    // SRL | srl SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 317}
+  else if decode_execute32_opcode_0b0001011_funct3_0b100_match_4(inst) then {
+    // LD.SMIN | ld.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 196}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_srl(regdst, srcl, srcr)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_ld_smin(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00005035 then {
-    // SRLIW | srliw SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 319}
+  else if decode_execute32_opcode_0b0001011_funct3_0b100_match_5(inst) then {
+    // LD.UMAX | ld.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 197}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[24..20];
-    exec_srliw(regdst, srcl, shamt)
+    let srcr : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_ld_umax(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfe00707f) == 0x00005025 then {
-    // SRLW | srlw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 320}
+  else if decode_execute32_opcode_0b0001011_funct3_0b100_match_6(inst) then {
+    // LD.UMIN | ld.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 198}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    exec_srlw(regdst, srcl, srcr)
-  }
-  else if (inst & 0x00087fff) == 0x00000033 then {
-    // B.HINT | B.HINT {BR.{likely, unlikely}, TEMP.{hot, warm, cool, none}, PRFSIZE} | {'file': 'opcodes/lx_32.opc', 'line': 37}
-    let l_ul : bits(1) = inst[16];
-    let v : bits(1) = inst[15];
-    let prefetch_size : bits(12) = inst[31..20];
-    let temp : bits(2) = inst[18..17];
-    exec_b_hint()
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_ld_umin(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfc00707f) == 0x00007015 then {
-    // SLLI | slli SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 310}
+  else if decode_execute32_opcode_0b0001011_funct3_0b100_match_7(inst) then {
+    // LD.XOR | ld.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 199}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let shamt : bits(6) = inst[25..20];
-    exec_slli(regdst, srcl, shamt)
+    let srcr : bits(5) = inst[24..20];
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_ld_xor(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xfc00707f) == 0x00006015 then {
-    // SRAI | srai SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 314}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(6) = inst[25..20];
-    exec_srai(regdst, srcl, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfc00707f) == 0x00005015 then {
-    // SRLI | srli SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 318}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(6) = inst[25..20];
-    exec_srli(regdst, srcl, shamt)
-  }
-  else if (inst & 0xf83f000f) == 0x50160002 then {
-    // BSTART CALL | BSTART.CALL <br_label>, <rt_label>, ->ra | {'file': 'opcodes/lx_32.opc', 'line': 59}
-    let simm12 : bits(12) = inst[15..4];
-    let uimm5 : bits(5) = inst[26..22];
-    decoded_block_target_pc_shadow = decode_block_target12(simm12);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_call();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_call(uimm5)
-  }
-  else if (inst & 0x00007fff) == 0x00003101 then {
-    // BSTART.FP | BSTART.FP COND, <label> | {'file': 'opcodes/lx_32.opc', 'line': 71}
-    let simm17 : bits(17) = inst[31..15];
-    decoded_block_target_pc_shadow = decode_block_target17(simm17);
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_cond();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_fp()
-  }
-  else if (inst & 0x00007fff) == 0x00002101 then {
-    // BSTART.FP | BSTART.FP DIRECT, <label> | {'file': 'opcodes/lx_32.opc', 'line': 72}
-    let simm17 : bits(17) = inst[31..15];
-    decoded_block_target_pc_shadow = decode_block_target17(simm17);
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_direct();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_fp()
-  }
-  else if (inst & 0x00007fff) == 0x00004101 then {
-    // BSTART.FP | BSTART.FP CALL, <label> | {'file': 'opcodes/lx_32.opc', 'line': 74}
-    let simm17 : bits(17) = inst[31..15];
-    decoded_block_target_pc_shadow = decode_block_target17(simm17);
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_call();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_fp()
-  }
-  else if (inst & 0x00007fff) == 0x00001101 then {
-    // BSTART.FP | BSTART.FP FALL<, fixup_label> | {'file': 'opcodes/lx_32.opc', 'line': 75}
-    let simm17 : bits(17) = inst[31..15];
-    decoded_block_target_pc_shadow = decode_block_target17(simm17);
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_fp()
-  }
-  else if (inst & 0x00007fff) == 0x00003001 then {
-    // BSTART.STD | BSTART.STD COND, <label> | {'file': 'opcodes/lx_32.opc', 'line': 78}
-    let simm17 : bits(17) = inst[31..15];
-    decoded_block_target_pc_shadow = decode_block_target17(simm17);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_cond();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_std()
-  }
-  else if (inst & 0x00007fff) == 0x00001001 then {
-    // BSTART.STD | BSTART.STD FALL<, fixup_label> | {'file': 'opcodes/lx_32.opc', 'line': 80}
-    let simm17 : bits(17) = inst[31..15];
-    decoded_block_target_pc_shadow = decode_block_target17(simm17);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_std()
-  }
-  else if (inst & 0x00007fff) == 0x00004001 then {
-    // BSTART.STD | BSTART.STD CALL, <label> | {'file': 'opcodes/lx_32.opc', 'line': 82}
-    let simm17 : bits(17) = inst[31..15];
-    decoded_block_target_pc_shadow = decode_block_target17(simm17);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_call();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_std()
-  }
-  else if (inst & 0x00007fff) == 0x00002001 then {
-    // BSTART.STD | BSTART.STD DIRECT, <label> | {'file': 'opcodes/lx_32.opc', 'line': 84}
-    let simm17 : bits(17) = inst[31..15];
-    decoded_block_target_pc_shadow = decode_block_target17(simm17);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_direct();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_std()
-  }
-  else if (inst & 0x00007fff) == 0x00001081 then {
-    // BSTART.SYS | BSTART.SYS FALL<, fixup_label> | {'file': 'opcodes/lx_32.opc', 'line': 85}
-    let simm17 : bits(17) = inst[31..15];
-    decoded_block_target_pc_shadow = decode_block_target17(simm17);
-    decoded_block_type_shadow = 0b0001;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart_sys()
-  }
-  else if (inst & 0xf800707f) == 0x00002045 then {
-    // CMP.AND | cmp.and SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 122}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_cmp_and(regdst, srcl, srcr, srcrtype)
-  }
-  else if (inst & 0xf800707f) == 0x00000045 then {
-    // CMP.EQ | cmp.eq SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 124}
-    let regdst : bits(5) = inst[11..7];
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x0000500b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b101_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x1000500b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b101_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x2000500b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b101_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x4000500b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b101_match_4(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x5000500b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b101_match_5(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x6000500b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b101_match_6(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x7000500b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b101_match_7(inst : bits(32)) -> bool = {
+  (inst & 0xf4007fff) == 0x3000500b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001011_funct3_0b101_match_0(inst) then {
+    // SD.ADD | sd.add<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 266}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_cmp_eq(regdst, srcl, srcr, srcrtype)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sd_add(srcl, srcr, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x00005045 then {
-    // CMP.GE | cmp.ge SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 126}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b101_match_1(inst) then {
+    // SD.AND | sd.and<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 267}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_cmp_ge(regdst, srcl, srcr, srcrtype)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sd_and(srcl, srcr, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x00007045 then {
-    // CMP.GEU | cmp.geu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 128}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b101_match_2(inst) then {
+    // SD.OR | sd.or<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 268}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_cmp_geu(regdst, srcl, srcr, srcrtype)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sd_or(srcl, srcr, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x00004045 then {
-    // CMP.LT | cmp.lt SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 130}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b101_match_3(inst) then {
+    // SD.SMAX | sd.smax<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 270}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_cmp_lt(regdst, srcl, srcr, srcrtype)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sd_smax(srcl, srcr, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x00006045 then {
-    // CMP.LTU | cmp.ltu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 132}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b101_match_4(inst) then {
+    // SD.SMIN | sd.smin<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 271}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_cmp_ltu(regdst, srcl, srcr, srcrtype)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sd_smin(srcl, srcr, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x00001045 then {
-    // CMP.NE | cmp.ne SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 134}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b101_match_5(inst) then {
+    // SD.UMAX | sd.umax<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 273}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_cmp_ne(regdst, srcl, srcr, srcrtype)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sd_umax(srcl, srcr, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x00003045 then {
-    // CMP.OR | cmp.or SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 136}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b101_match_6(inst) then {
+    // SD.UMIN | sd.umin<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 274}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_cmp_or(regdst, srcl, srcr, srcrtype)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sd_umin(srcl, srcr, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x0000004b then {
-    // FADD | fadd.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 155}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0001011_funct3_0b101_match_7(inst) then {
+    // SD.XOR | sd.xor<.{rl, f, rlf}> [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 275}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fadd(regdst, srcl, srcr, srctype)
-  }
-  else if (inst & 0x01f0707f) == 0x0000006b then {
-    // FCVT | fcvt.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 156}
-    let dsttype : bits(5) = inst[31..27];
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_fcvt(dsttype, regdst, srcl, srctype)
-  }
-  else if (inst & 0x01f0707f) == 0x0000106b then {
-    // FCVTA | fcvta.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 157}
-    let dsttype : bits(5) = inst[31..27];
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_fcvta(dsttype, regdst, srcl, srctype)
-  }
-  else if (inst & 0x01f0707f) == 0x0000206b then {
-    // FCVTM | fcvtm.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 158}
-    let dsttype : bits(5) = inst[31..27];
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_fcvtm(dsttype, regdst, srcl, srctype)
-  }
-  else if (inst & 0x01f0707f) == 0x0000306b then {
-    // FCVTN | fcvtn.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 159}
-    let dsttype : bits(5) = inst[31..27];
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_fcvtn(dsttype, regdst, srcl, srctype)
-  }
-  else if (inst & 0x01f0707f) == 0x0000406b then {
-    // FCVTP | fcvtp.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 160}
-    let dsttype : bits(5) = inst[31..27];
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_fcvtp(dsttype, regdst, srcl, srctype)
-  }
-  else if (inst & 0x01f0707f) == 0x0000506b then {
-    // FCVTZ | fcvtz.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 161}
-    let dsttype : bits(5) = inst[31..27];
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_fcvtz(dsttype, regdst, srcl, srctype)
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_sd_xor(srcl, srcr, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x0000304b then {
-    // FDIV | fdiv.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 162}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fdiv(regdst, srcl, srcr, srctype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf800707f) == 0x0000005b then {
-    // FEQ | feq.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 166}
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x0000600b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b110_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x3000600b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b110_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x1000600b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b110_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xf000707f) == 0x2000600b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001011_funct3_0b110_match_0(inst) then {
+    // SWAPB | swapb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 331}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_feq(regdst, srcl, srcr, srctype)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_swapb(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x0800005b then {
-    // FEQS | feqs.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 167}
+  else if decode_execute32_opcode_0b0001011_funct3_0b110_match_1(inst) then {
+    // SWAPD | swapd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 332}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_feqs(regdst, srcl, srcr, srctype)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_swapd(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x0000305b then {
-    // FGE | fge.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 170}
+  else if decode_execute32_opcode_0b0001011_funct3_0b110_match_2(inst) then {
+    // SWAPH | swaph<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 333}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fge(regdst, srcl, srcr, srctype)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_swaph(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x0800305b then {
-    // FGES | fges.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 171}
+  else if decode_execute32_opcode_0b0001011_funct3_0b110_match_3(inst) then {
+    // SWAPW | swapw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 334}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fges(regdst, srcl, srcr, srctype)
+    let aq : bits(1) = inst[26];
+    let far : bits(1) = inst[27];
+    let rl : bits(1) = inst[25];
+    exec_swapw(regdst, srcl, srcr, aq, far, rl)
   }
-  else if (inst & 0xf800707f) == 0x0000205b then {
-    // FLT | flt.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 172}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_flt(regdst, srcl, srcr, srctype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf800707f) == 0x0800205b then {
-    // FLTS | flts.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 173}
-    let regdst : bits(5) = inst[11..7];
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe007fff) == 0x0000700b
+}
+
+function decode_execute32_opcode_0b0001011_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0001011_funct3_0b111_match_0(inst) then {
+    // DMA | dma [SrcL], SrcR | {'file': 'opcodes/lx_32.opc', 'line': 140}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_flts(regdst, srcl, srcr, srctype)
+    exec_dma(srcl, srcr)
   }
-  else if (inst & 0xf800707f) == 0x0000605b then {
-    // FMAX | fmax.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 175}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fmax(regdst, srcl, srcr, srctype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf800707f) == 0x0000705b then {
-    // FMIN | fmin.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 176}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fmin(regdst, srcl, srcr, srctype)
+}
+
+function decode_execute32_opcode_0b0001011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0001011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0001011_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0001011_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0001011_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0001011_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0001011_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0001011_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b0001011_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf800707f) == 0x0000204b then {
-    // FMUL | fmul.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 178}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fmul(regdst, srcl, srcr, srctype)
-  }
-  else if (inst & 0xf800707f) == 0x0000105b then {
-    // FNE | fne.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 179}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fne(regdst, srcl, srcr, srctype)
+}
+
+function decode_execute32_opcode_0b0010001_fallback_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000007f) == 0x00000011
+}
+
+function decode_execute32_opcode_0b0010001_fallback(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010001_fallback_match_0(inst) then {
+    // BSTART | BSTART {DIRECT, CALL}, <label> | {'file': 'opcodes/lx_32.opc', 'line': 51}
+    let simm25 : bits(25) = inst[31..7];
+    decoded_block_target_pc_shadow = decode_block_target25(simm25);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_direct();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart()
   }
-  else if (inst & 0xf800707f) == 0x0800105b then {
-    // FNES | fnes.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 180}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fnes(regdst, srcl, srcr, srctype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf800707f) == 0x0000104b then {
-    // FSUB | fsub.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 187}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fsub(regdst, srcl, srcr, srctype)
+}
+
+function decode_execute32_opcode_0b0010001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    _ => decode_execute32_opcode_0b0010001_fallback(inst)
   }
-  else if (inst & 0x000ff07f) == 0x0000303b then {
-    // LSRGET | lsrget LSR_ID, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 222}
-    let lsr_id : bits(12) = inst[31..20];
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0600707f) == 0x00000013
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010011_funct3_0b000_match_0(inst) then {
+    // B.IOR | B.IOR [RegSrc0, RegSrc1, RegSrc2],[RegDst] | {'file': 'opcodes/lx_32.opc', 'line': 33}
     let regdst : bits(5) = inst[11..7];
-    exec_lsrget(regdst, lsr_id)
+    let regsrc0 : bits(5) = inst[19..15];
+    let regsrc1 : bits(5) = inst[24..20];
+    let regsrc2 : bits(5) = inst[31..27];
+    set_decoded_bior(regsrc0, regsrc1, regsrc2, regdst);
+    exec_b_ior()
   }
-  else if (inst & 0x00007fff) == 0x00000049 then {
-    // SB | sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_32.opc', 'line': 265}
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_sb(srcd, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x01f0707f) == 0x0000606b then {
-    // SCVTF | scvtf.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 272}
-    let dsttype : bits(5) = inst[31..27];
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_scvtf(dsttype, regdst, srcl, srctype)
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0007f3ff) == 0x00004013
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b100_match_1(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x0000707f) == 0x00004013, (inst[9..7] != 0b100)), and_bool_no_flow((inst[9..7] != 0b101), (inst[9..7] != 0b110))), and_bool_no_flow(and_bool_no_flow((inst[9..7] != 0b111), (inst[18..15] != 0b0000)), and_bool_no_flow((inst[18..15] != 0b0001), (inst[18..15] != 0b0010)))), and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst[18..15] != 0b1010), (inst[18..15] != 0b1011)), and_bool_no_flow((inst[18..15] != 0b1100), (inst[18..15] != 0b1101))), and_bool_no_flow((inst[18..15] != 0b1110), (inst[18..15] != 0b1111))))
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010011_funct3_0b100_match_0(inst) then {
+    // B.IOT | B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last> | {'file': 'opcodes/lx_32.opc', 'line': 37}
+    let l : bits(1) = inst[19];
+    let s0r : bits(1) = inst[10];
+    let s1r : bits(1) = inst[11];
+    let srctile0 : bits(6) = inst[25..20];
+    let srctile1 : bits(6) = inst[31..26];
+    decoded_biot_raw_shadow = sail_zero_extend(inst, 64);
+    exec_b_iot()
   }
-  else if (inst & 0x00007fff) == 0x00003049 then {
-    // SD | sd SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3] | {'file': 'opcodes/lx_32.opc', 'line': 273}
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_sd(srcd, srcl, srcr, srcrtype)
+  else if decode_execute32_opcode_0b0010011_funct3_0b100_match_1(inst) then {
+    // B.IOT | B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size> | {'file': 'opcodes/lx_32.opc', 'line': 34}
+    let dsttile : bits(3) = inst[9..7];
+    let l : bits(1) = inst[19];
+    let s0r : bits(1) = inst[10];
+    let s1r : bits(1) = inst[11];
+    let srctile0 : bits(6) = inst[25..20];
+    let srctile1 : bits(6) = inst[31..26];
+    let imm4 : bits(4) = inst[18..15];
+    decoded_biot_raw_shadow = sail_zero_extend(inst, 64);
+    exec_b_iot()
   }
-  else if (inst & 0x00007fff) == 0x00007049 then {
-    // SD.U | sd.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_32.opc', 'line': 280}
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_sd_u(srcd, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff) == 0x00001049 then {
-    // SH | sh SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1] | {'file': 'opcodes/lx_32.opc', 'line': 304}
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_sh(srcd, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfc07fbff) == 0x00005013
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b101_match_1(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0xfc00787f) == 0x00005013, (inst[9..7] != 0b100)), and_bool_no_flow((inst[9..7] != 0b101), (inst[9..7] != 0b110))), and_bool_no_flow(and_bool_no_flow((inst[9..7] != 0b111), (inst[18..15] != 0b0000)), and_bool_no_flow((inst[18..15] != 0b0001), (inst[18..15] != 0b0010)))), and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst[18..15] != 0b1010), (inst[18..15] != 0b1011)), and_bool_no_flow((inst[18..15] != 0b1100), (inst[18..15] != 0b1101))), and_bool_no_flow((inst[18..15] != 0b1110), (inst[18..15] != 0b1111))))
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010011_funct3_0b101_match_0(inst) then {
+    // B.IOT | B.IOT SrcTile0<.reuse>, <last> | {'file': 'opcodes/lx_32.opc', 'line': 38}
+    let l : bits(1) = inst[19];
+    let s0r : bits(1) = inst[10];
+    let srctile0 : bits(6) = inst[25..20];
+    decoded_biot_raw_shadow = sail_zero_extend(inst, 64);
+    exec_b_iot()
   }
-  else if (inst & 0x00007fff) == 0x00005049 then {
-    // SH.U | sh.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_32.opc', 'line': 306}
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_sh_u(srcd, srcl, srcr, srcrtype)
+  else if decode_execute32_opcode_0b0010011_funct3_0b101_match_1(inst) then {
+    // B.IOT | B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size> | {'file': 'opcodes/lx_32.opc', 'line': 35}
+    let dsttile : bits(3) = inst[9..7];
+    let l : bits(1) = inst[19];
+    let s0r : bits(1) = inst[10];
+    let srctile0 : bits(6) = inst[25..20];
+    let imm4 : bits(4) = inst[18..15];
+    decoded_biot_raw_shadow = sail_zero_extend(inst, 64);
+    exec_b_iot()
   }
-  else if (inst & 0x000ff07f) == 0x0000003b then {
-    // SSRGET | ssrget SSR_ID, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 321}
-    let regdst : bits(5) = inst[11..7];
-    let ssr_id : bits(12) = inst[31..20];
-    exec_ssrget(regdst, ssr_id)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff) == 0x0000103b then {
-    // SSRSET | ssrset SrcL, SSR_ID | {'file': 'opcodes/lx_32.opc', 'line': 322}
-    let ssr_id : bits(12) = inst[31..20];
-    let srcl : bits(5) = inst[19..15];
-    exec_ssrset(srcl, ssr_id)
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0xfff07c7f) == 0x00006013, (inst[9..7] != 0b100)), and_bool_no_flow((inst[9..7] != 0b101), (inst[9..7] != 0b110))), and_bool_no_flow(and_bool_no_flow((inst[9..7] != 0b111), (inst[18..15] != 0b0000)), and_bool_no_flow((inst[18..15] != 0b0001), (inst[18..15] != 0b0010)))), and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst[18..15] != 0b1010), (inst[18..15] != 0b1011)), and_bool_no_flow((inst[18..15] != 0b1100), (inst[18..15] != 0b1101))), and_bool_no_flow((inst[18..15] != 0b1110), (inst[18..15] != 0b1111))))
+}
+
+function decode_execute32_opcode_0b0010011_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010011_funct3_0b110_match_0(inst) then {
+    // B.IOT | B.IOT <last>, ->DstTile<Size> | {'file': 'opcodes/lx_32.opc', 'line': 36}
+    let dsttile : bits(3) = inst[9..7];
+    let l : bits(1) = inst[19];
+    let imm4 : bits(4) = inst[18..15];
+    decoded_biot_raw_shadow = sail_zero_extend(inst, 64);
+    exec_b_iot()
   }
-  else if (inst & 0x00007fff) == 0x00002049 then {
-    // SW | sw SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2] | {'file': 'opcodes/lx_32.opc', 'line': 328}
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_sw(srcd, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff) == 0x00006049 then {
-    // SW.U | sw.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_32.opc', 'line': 335}
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_sw_u(srcd, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b0010011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0010011_funct3_0b000(inst),
+    0b100 => decode_execute32_opcode_0b0010011_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0010011_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0010011_funct3_0b110(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x01f0707f) == 0x0000706b then {
-    // UCVTF | ucvtf.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 349}
-    let dsttype : bits(5) = inst[31..27];
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000015
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010101_funct3_0b000_match_0(inst) then {
+    // ADDI | addi SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 14}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srctype : bits(2) = inst[26..25];
-    exec_ucvtf(dsttype, regdst, srcl, srctype)
+    let uimm12 : bits(12) = inst[31..20];
+    exec_addi(regdst, srcl, uimm12)
   }
-  else if (inst & 0x00007fff) == 0x00006f81 then {
-    // XB | XB ACR-ID, C-ID | {'file': 'opcodes/lx_32.opc', 'line': 350}
-    let acr_id : bits(10) = inst[24..15];
-    let cross_bid : bits(7) = inst[31..25];
-    exec_xb(sail_zero_extend(acr_id, 12), sail_zero_extend(cross_bid, 8))
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x0000400b then {
-    // LD.ADD | ld.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 199}
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001015
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010101_funct3_0b001_match_0(inst) then {
+    // SUBI | subi SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 317}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_ld_add(regdst, srcl, srcr, aq, far, rl)
+    let uimm12 : bits(12) = inst[31..20];
+    exec_subi(regdst, srcl, uimm12)
   }
-  else if (inst & 0xf000707f) == 0x1000400b then {
-    // LD.AND | ld.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 200}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_ld_and(regdst, srcl, srcr, aq, far, rl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x2000400b then {
-    // LD.OR | ld.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 201}
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002015
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010101_funct3_0b010_match_0(inst) then {
+    // ANDI | andi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 19}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_ld_or(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_andi(regdst, srcl, simm12)
   }
-  else if (inst & 0xf000707f) == 0x4000400b then {
-    // LD.SMAX | ld.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 203}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_ld_smax(regdst, srcl, srcr, aq, far, rl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x5000400b then {
-    // LD.SMIN | ld.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 204}
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003015
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010101_funct3_0b011_match_0(inst) then {
+    // ORI | ori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 247}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_ld_smin(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_ori(regdst, srcl, simm12)
   }
-  else if (inst & 0xf000707f) == 0x6000400b then {
-    // LD.UMAX | ld.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 205}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_ld_umax(regdst, srcl, srcr, aq, far, rl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x7000400b then {
-    // LD.UMIN | ld.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 206}
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004015
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010101_funct3_0b100_match_0(inst) then {
+    // XORI | xori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 344}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_ld_umin(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_xori(regdst, srcl, simm12)
   }
-  else if (inst & 0xf000707f) == 0x3000400b then {
-    // LD.XOR | ld.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 207}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_ld_xor(regdst, srcl, srcr, aq, far, rl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x0000000b then {
-    // LR.B | lr.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 218}
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfc00707f) == 0x00005015
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010101_funct3_0b101_match_0(inst) then {
+    // SRLI | srli SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 310}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srczero : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lr_b(regdst, srcl, aq, far, rl)
+    let shamt : bits(6) = inst[25..20];
+    exec_srli(regdst, srcl, shamt)
   }
-  else if (inst & 0xf000707f) == 0x3000000b then {
-    // LR.D | lr.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 219}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srczero : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lr_d(regdst, srcl, aq, far, rl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x1000000b then {
-    // LR.H | lr.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 220}
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfc00707f) == 0x00006015
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010101_funct3_0b110_match_0(inst) then {
+    // SRAI | srai SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 306}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srczero : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lr_h(regdst, srcl, aq, far, rl)
+    let shamt : bits(6) = inst[25..20];
+    exec_srai(regdst, srcl, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x2000000b then {
-    // LR.W | lr.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 221}
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfc00707f) == 0x00007015
+}
+
+function decode_execute32_opcode_0b0010101_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010101_funct3_0b111_match_0(inst) then {
+    // SLLI | slli SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 302}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srczero : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lr_w(regdst, srcl, aq, far, rl)
+    let shamt : bits(6) = inst[25..20];
+    exec_slli(regdst, srcl, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x0000200b then {
-    // LW.ADD | lw.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 225}
+}
+
+function decode_execute32_opcode_0b0010101(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0010101_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0010101_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0010101_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0010101_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0010101_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0010101_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0010101_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b0010101_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0010111_fallback_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000007f) == 0x00000017
+}
+
+function decode_execute32_opcode_0b0010111_fallback(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0010111_fallback_match_0(inst) then {
+    // LUI | lui simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 215}
     let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lw_add(regdst, srcl, srcr, aq, far, rl)
+    let imm20 : bits(20) = inst[31..12];
+    exec_lui(regdst, imm20)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0010111(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    _ => decode_execute32_opcode_0b0010111_fallback(inst)
   }
-  else if (inst & 0xf000707f) == 0x1000200b then {
-    // LW.AND | lw.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 226}
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000019
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011001_funct3_0b000_match_0(inst) then {
+    // LBI | lbi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 186}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lw_and(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_lbi(regdst, srcl, simm12)
   }
-  else if (inst & 0xf000707f) == 0x2000200b then {
-    // LW.OR | lw.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 227}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001019
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011001_funct3_0b001_match_0(inst) then {
+    // LHI | lhi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 204}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lw_or(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_lhi(regdst, srcl, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x4000200b then {
-    // LW.SMAX | lw.smax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 229}
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002019
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011001_funct3_0b010_match_0(inst) then {
+    // LWI | lwi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 226}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lw_smax(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_lwi(regdst, srcl, simm12)
   }
-  else if (inst & 0xf000707f) == 0x5000200b then {
-    // LW.SMIN | lw.smin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 230}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003019
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011001_funct3_0b011_match_0(inst) then {
+    // LDI | ldi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 200}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lw_smin(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_ldi(regdst, srcl, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x6000200b then {
-    // LW.UMAX | lw.umax<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 231}
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004019
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011001_funct3_0b100_match_0(inst) then {
+    // LBUI | lbui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 189}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lw_umax(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_lbui(regdst, srcl, simm12)
   }
-  else if (inst & 0xf000707f) == 0x7000200b then {
-    // LW.UMIN | lw.umin<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 232}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00005019
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011001_funct3_0b101_match_0(inst) then {
+    // LHUI | lhui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 208}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lw_umin(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_lhui(regdst, srcl, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x3000200b then {
-    // LW.XOR | lw.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 233}
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00006019
+}
+
+function decode_execute32_opcode_0b0011001_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011001_funct3_0b110_match_0(inst) then {
+    // LWUI | lwui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 230}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_lw_xor(regdst, srcl, srcr, aq, far, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_lwui(regdst, srcl, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0011001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0011001_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0011001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0011001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0011001_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0011001_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0011001_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0011001_funct3_0b110(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x0000100b then {
-    // SC.B | sc.b<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 268}
+}
+
+function decode_execute32_opcode_0b0011011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x0000001b
+}
+
+function decode_execute32_opcode_0b0011011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011011_funct3_0b000_match_0(inst) then {
+    // CASB | casb<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 109}
     let regdst : bits(5) = inst[11..7];
+    let srcd : bits(5) = inst[31..27];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sc_b(regdst, srcl, srcr, aq, far, rl)
+    exec_casb(regdst, srcd, srcl, srcr, aq, rl)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x3000100b then {
-    // SC.D | sc.d<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 269}
+}
+
+function decode_execute32_opcode_0b0011011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x0000101b
+}
+
+function decode_execute32_opcode_0b0011011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011011_funct3_0b001_match_0(inst) then {
+    // CASH | cash<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 111}
     let regdst : bits(5) = inst[11..7];
+    let srcd : bits(5) = inst[31..27];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sc_d(regdst, srcl, srcr, aq, far, rl)
+    exec_cash(regdst, srcd, srcl, srcr, aq, rl)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x1000100b then {
-    // SC.H | sc.h<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 270}
+}
+
+function decode_execute32_opcode_0b0011011_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x0000201b
+}
+
+function decode_execute32_opcode_0b0011011_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011011_funct3_0b010_match_0(inst) then {
+    // CASW | casw<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 112}
     let regdst : bits(5) = inst[11..7];
+    let srcd : bits(5) = inst[31..27];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sc_h(regdst, srcl, srcr, aq, far, rl)
+    exec_casw(regdst, srcd, srcl, srcr, aq, rl)
   }
-  else if (inst & 0xf000707f) == 0x2000100b then {
-    // SC.W | sc.w<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> SrcL, [SrcR], {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 271}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0011011_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x0000301b
+}
+
+function decode_execute32_opcode_0b0011011_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0011011_funct3_0b011_match_0(inst) then {
+    // CASD | casd<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 110}
     let regdst : bits(5) = inst[11..7];
+    let srcd : bits(5) = inst[31..27];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
     let rl : bits(1) = inst[25];
-    exec_sc_w(regdst, srcl, srcr, aq, far, rl)
+    exec_casd(regdst, srcd, srcl, srcr, aq, rl)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0011011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0011011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0011011_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0011011_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0011011_funct3_0b011(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100001_fallback_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000007f) == 0x00000021
+}
+
+function decode_execute32_opcode_0b0100001_fallback(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100001_fallback_match_0(inst) then {
+    // BSTART | BSTART COND, <label> | {'file': 'opcodes/lx_32.opc', 'line': 52}
+    let simm25 : bits(25) = inst[31..7];
+    decoded_block_target_pc_shadow = decode_block_target25(simm25);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_cond();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart()
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    _ => decode_execute32_opcode_0b0100001_fallback(inst)
+  }
+}
+
+function decode_execute32_opcode_0b0100011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfbf07fff) == 0x00000023
+}
+
+function decode_execute32_opcode_0b0100011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100011_funct3_0b000_match_0(inst) then {
+    // B.CATR | B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr} | {'file': 'opcodes/lx_32.opc', 'line': 23}
+    let dr : bits(1) = inst[26];
+    let aq : bits(1) = inst[16];
+    let atom : bits(1) = inst[17];
+    let far : bits(1) = inst[18];
+    let rl : bits(1) = inst[15];
+    let trap : bits(1) = inst[19];
+    decoded_bcatr_raw_shadow = sail_zero_extend(inst, 64);
+    exec_b_catr()
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  and_bool_no_flow(and_bool_no_flow(and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst & 0x000c707f) == 0x00001023, (inst[31..29] != 0b110)), and_bool_no_flow((inst[31..29] != 0b111), (inst[24..20] != 0b01111))), and_bool_no_flow(and_bool_no_flow((inst[24..20] != 0b10101), (inst[24..20] != 0b10110)), and_bool_no_flow((inst[24..20] != 0b10111), (inst[24..20] != 0b11101)))), and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst[24..20] != 0b11110), (inst[24..20] != 0b11111)), and_bool_no_flow((inst[11..7] != 0b00010), (inst[11..7] != 0b00101))), and_bool_no_flow(and_bool_no_flow((inst[11..7] != 0b00111), (inst[11..7] != 0b01010)), and_bool_no_flow((inst[11..7] != 0b01011), (inst[11..7] != 0b01100))))), and_bool_no_flow(and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst[11..7] != 0b01101), (inst[11..7] != 0b01110)), and_bool_no_flow((inst[11..7] != 0b01111), (inst[11..7] != 0b10000))), and_bool_no_flow(and_bool_no_flow((inst[11..7] != 0b10011), (inst[11..7] != 0b10101)), and_bool_no_flow((inst[11..7] != 0b10110), (inst[11..7] != 0b10111)))), and_bool_no_flow(and_bool_no_flow(and_bool_no_flow((inst[11..7] != 0b11000), (inst[11..7] != 0b11001)), and_bool_no_flow((inst[11..7] != 0b11010), (inst[11..7] != 0b11101))), (inst[11..7] != 0b11111))))
+}
+
+function decode_execute32_opcode_0b0100011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100011_funct3_0b001_match_0(inst) then {
+    // B.DATR | B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize} | {'file': 'opcodes/lx_32.opc', 'line': 24}
+    let cmode : bits(3) = inst[31..29];
+    let canonicalize : bits(1) = inst[25];
+    let datatype : bits(5) = inst[24..20];
+    let layout : bits(5) = inst[11..7];
+    let padvalueorbyteid : bits(2) = inst[28..27];
+    let rmode : bits(3) = inst[17..15];
+    let sat : bits(1) = inst[26];
+    decoded_bdatr_raw_shadow = sail_zero_extend(inst, 64);
+    exec_b_datr()
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0100011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0100011_funct3_0b001(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x0000600b then {
-    // SWAPB | swapb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 339}
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000025
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100101_funct3_0b000_match_0(inst) then {
+    // ADDW | addw SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 17}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_swapb(regdst, srcl, srcr, aq, far, rl)
+    let srcrtype : bits(2) = inst[26..25];
+    let shamt : bits(5) = inst[31..27];
+    exec_addw(regdst, srcl, srcr, srcrtype, shamt)
   }
-  else if (inst & 0xf000707f) == 0x3000600b then {
-    // SWAPD | swapd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 340}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001025
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100101_funct3_0b001_match_0(inst) then {
+    // SUBW | subw SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 319}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_swapd(regdst, srcl, srcr, aq, far, rl)
+    let srcrtype : bits(2) = inst[26..25];
+    let shamt : bits(5) = inst[31..27];
+    exec_subw(regdst, srcl, srcr, srcrtype, shamt)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707f) == 0x1000600b then {
-    // SWAPH | swaph<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 341}
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002025
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100101_funct3_0b010_match_0(inst) then {
+    // ANDW | andw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 21}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_swaph(regdst, srcl, srcr, aq, far, rl)
-  }
-  else if (inst & 0xf000707f) == 0x2000600b then {
-    // SWAPW | swapw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, {->t, ->u, ->Rd} | {'file': 'opcodes/lx_32.opc', 'line': 342}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let far : bits(1) = inst[27];
-    let rl : bits(1) = inst[25];
-    exec_swapw(regdst, srcl, srcr, aq, far, rl)
-  }
-  else if (inst & 0x0600707f) == 0x00000013 then {
-    // B.IOR | B.IOR [RegSrc0, RegSrc1, RegSrc2],[RegDst] | {'file': 'opcodes/lx_32.opc', 'line': 39}
-    let regdst : bits(5) = inst[11..7];
-    let regsrc0 : bits(5) = inst[19..15];
-    let regsrc1 : bits(5) = inst[24..20];
-    let regsrc2 : bits(5) = inst[31..27];
-    set_decoded_bior(regsrc0, regsrc1, regsrc2, regdst);
-    exec_b_ior()
-  }
-  else if (inst & 0x0600707f) == 0x00006047 then {
-    // MADD | madd SrcL, SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 240}
-    let regdst : bits(5) = inst[11..7];
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    exec_madd(regdst, srcd, srcl, srcr)
-  }
-  else if (inst & 0x0600707f) == 0x00007047 then {
-    // MADDW | maddw SrcL, SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 241}
-    let regdst : bits(5) = inst[11..7];
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    exec_maddw(regdst, srcd, srcl, srcr)
+    let srcrtype : bits(2) = inst[26..25];
+    let shamt : bits(5) = inst[31..27];
+    exec_andw(regdst, srcl, srcr, srcrtype, shamt)
   }
-  else if (inst & 0x00000fff) == 0x00000507 then {
-    // SETRET | setret uimm, ->Ra | {'file': 'opcodes/lx_32.opc', 'line': 303}
-    let imm20 : bits(20) = inst[31..12];
-    exec_setret(imm20)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00000005 then {
-    // ADD | add SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 13}
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003025
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100101_funct3_0b011_match_0(inst) then {
+    // ORW | orw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 249}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let srcrtype : bits(2) = inst[26..25];
     let shamt : bits(5) = inst[31..27];
-    exec_add(regdst, srcl, srcr, srcrtype, shamt)
-  }
-  else if (inst & 0x0000707f) == 0x00000015 then {
-    // ADDI | addi SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 14}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let uimm12 : bits(12) = inst[31..20];
-    exec_addi(regdst, srcl, uimm12)
+    exec_orw(regdst, srcl, srcr, srcrtype, shamt)
   }
-  else if (inst & 0x0000707f) == 0x00000035 then {
-    // ADDIW | addiw SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 15}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let uimm12 : bits(12) = inst[31..20];
-    exec_addiw(regdst, srcl, uimm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00000025 then {
-    // ADDW | addw SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 17}
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004025
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100101_funct3_0b100_match_0(inst) then {
+    // XORW | xorw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 346}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let srcrtype : bits(2) = inst[26..25];
     let shamt : bits(5) = inst[31..27];
-    exec_addw(regdst, srcl, srcr, srcrtype, shamt)
+    exec_xorw(regdst, srcl, srcr, srcrtype, shamt)
   }
-  else if (inst & 0x0000707f) == 0x00002005 then {
-    // AND | and SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 18}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00005025
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100101_funct3_0b101_match_0(inst) then {
+    // SRLW | srlw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 312}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_and(regdst, srcl, srcr, srcrtype, shamt)
+    exec_srlw(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f) == 0x00002015 then {
-    // ANDI | andi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 19}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_andi(regdst, srcl, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00002035 then {
-    // ANDIW | andiw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 20}
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00006025
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100101_funct3_0b110_match_0(inst) then {
+    // SRAW | sraw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 308}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_andiw(regdst, srcl, simm12)
+    let srcr : bits(5) = inst[24..20];
+    exec_sraw(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f) == 0x00002025 then {
-    // ANDW | andw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 21}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00007025
+}
+
+function decode_execute32_opcode_0b0100101_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100101_funct3_0b111_match_0(inst) then {
+    // SLLW | sllw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 304}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_andw(regdst, srcl, srcr, srcrtype, shamt)
-  }
-  else if (inst & 0x0000707f) == 0x00001023 then {
-    // B.DATR | B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat} | {'file': 'opcodes/lx_32.opc', 'line': 24}
-    let cmode : bits(3) = inst[27..25];
-    let datalayout : bits(5) = inst[11..7];
-    let datatype : bits(5) = inst[24..20];
-    let padvalue : bits(5) = inst[19..15];
-    let rmode : bits(3) = inst[30..28];
-    let sat : bits(1) = inst[31];
-    decoded_bdatr_raw_shadow = sail_zero_extend(inst, 64);
-    exec_b_datr()
-  }
-  else if (inst & 0x0000707f) == 0x00002043 then {
-    // B.DIM | B.DIM RegSrc, uimm, ->LB2 | {'file': 'opcodes/lx_32.opc', 'line': 31}
-    let regsrc : bits(5) = inst[19..15];
-    let uimm17 : bits(17) = inst[11..7] @ inst[31..20];
-    decoded_bdim_index_shadow = 0b10;
-    decoded_bdim_value_shadow = read_reg5(regsrc) + sail_zero_extend(uimm17, 64);
-    exec_b_dim()
+    exec_sllw(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f) == 0x00000043 then {
-    // B.DIM | B.DIM RegSrc, uimm, ->LB0 | {'file': 'opcodes/lx_32.opc', 'line': 32}
-    let regsrc : bits(5) = inst[19..15];
-    let uimm17 : bits(17) = inst[11..7] @ inst[31..20];
-    decoded_bdim_index_shadow = 0b00;
-    decoded_bdim_value_shadow = read_reg5(regsrc) + sail_zero_extend(uimm17, 64);
-    exec_b_dim()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00001043 then {
-    // B.DIM | B.DIM RegSrc, uimm, ->LB1 | {'file': 'opcodes/lx_32.opc', 'line': 33}
-    let regsrc : bits(5) = inst[19..15];
-    let uimm17 : bits(17) = inst[11..7] @ inst[31..20];
-    decoded_bdim_index_shadow = 0b01;
-    decoded_bdim_value_shadow = read_reg5(regsrc) + sail_zero_extend(uimm17, 64);
-    exec_b_dim()
+}
+
+function decode_execute32_opcode_0b0100101(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0100101_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0100101_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0100101_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0100101_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0100101_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0100101_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0100101_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b0100101_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00000027 then {
-    // B.EQ | b.eq SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 34}
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000027
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100111_funct3_0b000_match_0(inst) then {
+    // B.EQ | b.eq SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 28}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let simm12 : bits(12) = inst[11..7] @ inst[31..25];
     exec_b_eq(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00003027 then {
-    // B.GE | b.ge SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 35}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001027
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100111_funct3_0b001_match_0(inst) then {
+    // B.NE | b.ne SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 41}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_b_ge(srcl, srcr, simm12)
+    exec_b_ne(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00005027 then {
-    // B.GEU | b.geu SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 36}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002027
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100111_funct3_0b010_match_0(inst) then {
+    // B.LT | b.lt SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 39}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_b_geu(srcl, srcr, simm12)
+    exec_b_lt(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00004013 & (inst[24..22] != 0b111) then {
-    // B.IOT | B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size> | {'file': 'opcodes/lx_32.opc', 'line': 40}
-    let dsttile : bits(3) = inst[24..22];
-    let l : bits(1) = inst[29];
-    let s0r : bits(1) = inst[30];
-    let s1r : bits(1) = inst[31];
-    let srctile0 : bits(6) = inst[15] @ inst[11..7];
-    let srctile1 : bits(6) = inst[21..16];
-    let imm4 : bits(4) = inst[28..25];
-    exec_b_iot()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00002027 then {
-    // B.LT | b.lt SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 45}
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003027
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100111_funct3_0b011_match_0(inst) then {
+    // B.GE | b.ge SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 29}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_b_lt(srcl, srcr, simm12)
+    exec_b_ge(srcl, srcr, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00004027 then {
-    // B.LTU | b.ltu SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 46}
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004027
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100111_funct3_0b100_match_0(inst) then {
+    // B.LTU | b.ltu SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 40}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let simm12 : bits(12) = inst[11..7] @ inst[31..25];
     exec_b_ltu(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00001027 then {
-    // B.NE | b.ne SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 47}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00005027
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100111_funct3_0b101_match_0(inst) then {
+    // B.GEU | b.geu SrcL, SrcR, label | {'file': 'opcodes/lx_32.opc', 'line': 30}
     let srcl : bits(5) = inst[19..15];
     let srcr : bits(5) = inst[24..20];
     let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_b_ne(srcl, srcr, simm12)
-  }
-  else if (inst & 0x0000707f) == 0x00002037 then {
-    // B.NZ | b.nz label | {'file': 'opcodes/lx_32.opc', 'line': 48}
-    let simm22 : bits(22) = inst[11..7] @ inst[31..15];
-    exec_b_nz(simm22)
+    exec_b_geu(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00001037 then {
-    // B.Z | b.z label | {'file': 'opcodes/lx_32.opc', 'line': 50}
-    let simm22 : bits(22) = inst[11..7] @ inst[31..15];
-    exec_b_z(simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00006067 then {
-    // BCNT | bcnt srcL,  M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 53}
-    let regdst : bits(5) = inst[11..7];
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00006027
+}
+
+function decode_execute32_opcode_0b0100111_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0100111_funct3_0b110_match_0(inst) then {
+    // JR | jr SrcL, label | {'file': 'opcodes/lx_32.opc', 'line': 183}
     let srcl : bits(5) = inst[19..15];
-    let imml : bits(6) = inst[25..20];
-    let imms : bits(6) = inst[31..26];
-    exec_bcnt(regdst, srcl, imms, imml)
+    let srczero : bits(5) = inst[24..20];
+    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
+    exec_jr(srcl, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00002067 then {
-    // BIC | bic SrcL, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 54}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let imml : bits(6) = inst[25..20];
-    let imms : bits(6) = inst[31..26];
-    exec_bic(regdst, srcl, imms, imml)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00003067 then {
-    // BIS | bis SrcL, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 55}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let imml : bits(6) = inst[25..20];
-    let imms : bits(6) = inst[31..26];
-    exec_bis(regdst, srcl, imms, imml)
+}
+
+function decode_execute32_opcode_0b0100111(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0100111_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0100111_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0100111_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0100111_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0100111_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0100111_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0100111_funct3_0b110(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00000067 then {
-    // BXS | bxs SrcL, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 115}
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001029
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101001_funct3_0b001_match_0(inst) then {
+    // LHI.U | lhi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 205}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let imml : bits(6) = inst[25..20];
-    let imms : bits(6) = inst[31..26];
-    exec_bxs(regdst, srcl, imms, imml)
+    let simm12 : bits(12) = inst[31..20];
+    exec_lhi_u(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00001067 then {
-    // BXU | bxu SrcL, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 116}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let imml : bits(6) = inst[25..20];
-    let imms : bits(6) = inst[31..26];
-    exec_bxu(regdst, srcl, imms, imml)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x0000001b then {
-    // CASB | casb<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 117}
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002029
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101001_funct3_0b010_match_0(inst) then {
+    // LWI.U | lwi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 227}
     let regdst : bits(5) = inst[11..7];
-    let srcd : bits(5) = inst[31..27];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let rl : bits(1) = inst[25];
-    exec_casb(regdst, srcd, srcl, srcr, aq, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_lwi_u(regdst, srcl, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x0000301b then {
-    // CASD | casd<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 118}
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003029
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101001_funct3_0b011_match_0(inst) then {
+    // LDI.U | ldi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 201}
     let regdst : bits(5) = inst[11..7];
-    let srcd : bits(5) = inst[31..27];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let rl : bits(1) = inst[25];
-    exec_casd(regdst, srcd, srcl, srcr, aq, rl)
+    let simm12 : bits(12) = inst[31..20];
+    exec_ldi_u(regdst, srcl, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x0000101b then {
-    // CASH | cash<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 119}
-    let regdst : bits(5) = inst[11..7];
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let rl : bits(1) = inst[25];
-    exec_cash(regdst, srcd, srcl, srcr, aq, rl)
-  }
-  else if (inst & 0x0000707f) == 0x0000201b then {
-    // CASW | casw<.{aq, rl, aqrl}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 120}
-    let regdst : bits(5) = inst[11..7];
-    let srcd : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let aq : bits(1) = inst[26];
-    let rl : bits(1) = inst[25];
-    exec_casw(regdst, srcd, srcl, srcr, aq, rl)
-  }
-  else if (inst & 0x0000707f) == 0x00005067 then {
-    // CLZ | clz SrcL,  M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 121}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let imml : bits(6) = inst[25..20];
-    let imms : bits(6) = inst[31..26];
-    exec_clz(regdst, srcl, imms, imml)
-  }
-  else if (inst & 0x0000707f) == 0x00002055 then {
-    // CMP.ANDI | cmp.andi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 123}
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00005029
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101001_funct3_0b101_match_0(inst) then {
+    // LHUI.U | lhui.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 209}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let simm12 : bits(12) = inst[31..20];
-    exec_cmp_andi(regdst, srcl, simm12)
+    exec_lhui_u(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00000055 then {
-    // CMP.EQI | cmp.eqi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 125}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_cmp_eqi(regdst, srcl, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00005055 then {
-    // CMP.GEI | cmp.gei SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 127}
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00006029
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101001_funct3_0b110_match_0(inst) then {
+    // LWUI.U | lwui.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 231}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let simm12 : bits(12) = inst[31..20];
-    exec_cmp_gei(regdst, srcl, simm12)
+    exec_lwui_u(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00007055 then {
-    // CMP.GEUI | cmp.geui SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 129}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let uimm12 : bits(12) = inst[31..20];
-    exec_cmp_geui(regdst, srcl, uimm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00004055 then {
-    // CMP.LTI | cmp.lti SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 131}
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00007029
+}
+
+function decode_execute32_opcode_0b0101001_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101001_funct3_0b111_match_0(inst) then {
+    // PRFI.U | prfi.u [SrcL, simm] | {'file': 'opcodes/lx_32.opc', 'line': 251}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let simm12 : bits(12) = inst[31..20];
-    exec_cmp_lti(regdst, srcl, simm12)
+    exec_prfi_u(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00006055 then {
-    // CMP.LTUI | cmp.ltui SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 133}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let uimm12 : bits(12) = inst[31..20];
-    exec_cmp_ltui(regdst, srcl, uimm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00001055 then {
-    // CMP.NEI | cmp.nei SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 135}
-    let regdst : bits(5) = inst[11..7];
+}
+
+function decode_execute32_opcode_0b0101001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b001 => decode_execute32_opcode_0b0101001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0101001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0101001_funct3_0b011(inst),
+    0b101 => decode_execute32_opcode_0b0101001_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0101001_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b0101001_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0000002b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b000_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0010002b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b000_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0020002b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b000_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0030002b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101011_funct3_0b000_match_0(inst) then {
+    // BSE | bse SrcL | {'file': 'opcodes/lx_32.opc', 'line': 50}
     let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_cmp_nei(regdst, srcl, simm12)
+    exec_bse()
   }
-  else if (inst & 0x0000707f) == 0x00003055 then {
-    // CMP.ORI | cmp.ori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 137}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b000_match_1(inst) then {
+    // BWE | bwe SrcL | {'file': 'opcodes/lx_32.opc', 'line': 104}
     let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_cmp_ori(regdst, srcl, simm12)
+    exec_bwe()
   }
-  else if (inst & 0x0000707f) == 0x00000077 then {
-    // CSEL | csel SrcP, SrcL, SrcR<.neg>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 138}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b000_match_2(inst) then {
+    // BWI | bwi SrcL | {'file': 'opcodes/lx_32.opc', 'line': 105}
     let srcl : bits(5) = inst[19..15];
-    let srcp : bits(5) = inst[31..27];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    exec_csel(regdst, srcp, srcl, srcr, srcrtype)
+    exec_bwi()
   }
-  else if (inst & 0x0000707f) == 0x00004067 then {
-    // CTZ | ctz SrcL,  M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 139}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b000_match_3(inst) then {
+    // BWT | bwt SrcL | {'file': 'opcodes/lx_32.opc', 'line': 106}
     let srcl : bits(5) = inst[19..15];
-    let imml : bits(6) = inst[25..20];
-    let imms : bits(6) = inst[31..26];
-    exec_ctz(regdst, srcl, imms, imml)
+    exec_bwt()
   }
-  else if (inst & 0x0000707f) == 0x00000041 then {
-    // FENTRY | FENTRY [RegSrc0 ~ RegSrcn], sp!, uimm | {'file': 'opcodes/lx_32.opc', 'line': 165}
-    let srcbegin : bits(5) = inst[19..15];
-    let srcend : bits(5) = inst[24..20];
-    let uimm : bits(15) = inst[11..7] @ inst[31..25] @ 0b000;
-    exec_fentry(srcbegin, srcend, uimm)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00001041 then {
-    // FEXIT | FEXIT [RegDst0 ~ RegDstn], sp!, uimm | {'file': 'opcodes/lx_32.opc', 'line': 168}
-    let dstbegin : bits(5) = inst[19..15];
-    let dstend : bits(5) = inst[24..20];
-    let uimm : bits(15) = inst[11..7] @ inst[31..25] @ 0b000;
-    exec_fexit(dstbegin, dstend, uimm)
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf0ffffff) == 0x0010102b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b001_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0000102b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101011_funct3_0b001_match_0(inst) then {
+    // EBREAK | ebreak imm | {'file': 'opcodes/lx_32.opc', 'line': 145}
+    let imm4 : bits(4) = inst[27..24];
+    exec_ebreak()
   }
-  else if (inst & 0x0000707f) == 0x0000404b then {
-    // FMADD | fmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 174}
-    let regdst : bits(5) = inst[11..7];
-    let srca : bits(5) = inst[31..27];
+  else if decode_execute32_opcode_0b0101011_funct3_0b001_match_1(inst) then {
+    // ASSERT | assert SrcL | {'file': 'opcodes/lx_32.opc', 'line': 22}
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fmadd(regdst, srca, srcl, srcr, srctype)
+    exec_assert(srcl)
   }
-  else if (inst & 0x0000707f) == 0x0000504b then {
-    // FMSUB | fmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 177}
-    let regdst : bits(5) = inst[11..7];
-    let srca : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fmsub(regdst, srca, srcl, srcr, srctype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x0000604b then {
-    // FNMADD | fnmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 181}
-    let regdst : bits(5) = inst[11..7];
-    let srca : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fnmadd(regdst, srca, srcl, srcr, srctype)
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x1000202b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b010_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf00fffff) == 0x0000202b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101011_funct3_0b010_match_0(inst) then {
+    // FENCE.I | fence.i | {'file': 'opcodes/lx_32.opc', 'line': 156}
+    exec_fence_i()
   }
-  else if (inst & 0x0000707f) == 0x0000704b then {
-    // FNMSUB | fnmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 182}
-    let regdst : bits(5) = inst[11..7];
-    let srca : bits(5) = inst[31..27];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srctype : bits(2) = inst[26..25];
-    exec_fnmsub(regdst, srca, srcl, srcr, srctype)
+  else if decode_execute32_opcode_0b0101011_funct3_0b010_match_1(inst) then {
+    // FENCE.D | fence.d pred_imm, succ_imm | {'file': 'opcodes/lx_32.opc', 'line': 155}
+    let pred_imm : bits(4) = inst[27..24];
+    let succ_imm : bits(4) = inst[23..20];
+    exec_fence_d()
   }
-  else if (inst & 0x0000707f) == 0x00002041 then {
-    // FRET.RA | FRET.RA [RegDst0 ~ RegDstn], sp!, uimm | {'file': 'opcodes/lx_32.opc', 'line': 184}
-    let dstbegin : bits(5) = inst[19..15];
-    let dstend : bits(5) = inst[24..20];
-    let uimm : bits(15) = inst[11..7] @ inst[31..25] @ 0b000;
-    exec_fret_ra(dstbegin, dstend, uimm)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00003041 then {
-    // FRET.STK | FRET.STK [RegDst0 ~ RegDstn], sp!, uimm | {'file': 'opcodes/lx_32.opc', 'line': 185}
-    let dstbegin : bits(5) = inst[19..15];
-    let dstend : bits(5) = inst[24..20];
-    let uimm : bits(15) = inst[11..7] @ inst[31..25] @ 0b000;
-    exec_fret_stk(dstbegin, dstend, uimm)
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xff0fffff) == 0x0000302b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b011_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xff0fffff) == 0x0100302b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101011_funct3_0b011_match_0(inst) then {
+    // ACRC | acrc rst_type | {'file': 'opcodes/lx_32.opc', 'line': 11}
+    let rst_type : bits(4) = inst[23..20];
+    exec_acrc(rst_type)
   }
-  else if (inst & 0x0000707f) == 0x00000037 then {
-    // J | j label | {'file': 'opcodes/lx_32.opc', 'line': 190}
-    let simm22 : bits(22) = inst[11..7] @ inst[31..15];
-    exec_j(simm22)
+  else if decode_execute32_opcode_0b0101011_funct3_0b011_match_1(inst) then {
+    // ACRE | acre rra_type | {'file': 'opcodes/lx_32.opc', 'line': 12}
+    let rra_type : bits(4) = inst[23..20];
+    exec_acre(rra_type)
   }
-  else if (inst & 0x0000707f) == 0x00006027 then {
-    // JR | jr SrcL, label | {'file': 'opcodes/lx_32.opc', 'line': 191}
-    let srcl : bits(5) = inst[19..15];
-    let srczero : bits(5) = inst[24..20];
-    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_jr(srcl, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00000009 then {
-    // LB | lb [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 192}
-    let regdst : bits(5) = inst[11..7];
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x0010402b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b100_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0000402b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101011_funct3_0b100_match_0(inst) then {
+    // BC.IALL | bc.iall | {'file': 'opcodes/lx_32.opc', 'line': 45}
+    exec_bc_iall()
+  }
+  else if decode_execute32_opcode_0b0101011_funct3_0b100_match_1(inst) then {
+    // BC.IVA | bc.iva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 46}
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_lb(regdst, srcl, srcr, srcrtype, shamt)
+    exec_bc_iva(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00000039 then {
-    // LB.PCR | lb.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 193}
-    let regdst : bits(5) = inst[11..7];
-    let simm17 : bits(17) = inst[31..15];
-    exec_lb_pcr(regdst, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00000019 then {
-    // LBI | lbi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 194}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lbi(regdst, srcl, simm12)
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x0010502b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b101_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0000502b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101011_funct3_0b101_match_0(inst) then {
+    // IC.IALL | ic.iall | {'file': 'opcodes/lx_32.opc', 'line': 180}
+    exec_ic_iall()
   }
-  else if (inst & 0x0000707f) == 0x00004009 then {
-    // LBU | lbu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 195}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b101_match_1(inst) then {
+    // IC.IVA | ic.iva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 181}
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_lbu(regdst, srcl, srcr, srcrtype, shamt)
+    exec_ic_iva(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00004039 then {
-    // LBU.PCR | lbu.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 196}
-    let regdst : bits(5) = inst[11..7];
-    let simm17 : bits(17) = inst[31..15];
-    exec_lbu_pcr(regdst, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00004019 then {
-    // LBUI | lbui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 197}
-    let regdst : bits(5) = inst[11..7];
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x0010602b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b110_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0060602b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b110_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0030602b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b110_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0050602b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b110_match_4(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0020602b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b110_match_5(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0040602b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b110_match_6(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0000602b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b110_match_7(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0070602b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101011_funct3_0b110_match_0(inst) then {
+    // DC.IALL | dc.iall | {'file': 'opcodes/lx_32.opc', 'line': 136}
+    exec_dc_iall()
+  }
+  else if decode_execute32_opcode_0b0101011_funct3_0b110_match_1(inst) then {
+    // DC.CISW | dc.cisw SrcL | {'file': 'opcodes/lx_32.opc', 'line': 132}
     let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lbui(regdst, srcl, simm12)
+    exec_dc_cisw(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00003009 then {
-    // LD | ld [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 198}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b110_match_2(inst) then {
+    // DC.CIVA | dc.civa SrcL | {'file': 'opcodes/lx_32.opc', 'line': 133}
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_ld(regdst, srcl, srcr, srcrtype, shamt)
+    exec_dc_civa(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00003039 then {
-    // LD.PCR | ld.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 202}
-    let regdst : bits(5) = inst[11..7];
-    let simm17 : bits(17) = inst[31..15];
-    exec_ld_pcr(regdst, simm17)
+  else if decode_execute32_opcode_0b0101011_funct3_0b110_match_3(inst) then {
+    // DC.CSW | dc.csw SrcL | {'file': 'opcodes/lx_32.opc', 'line': 134}
+    let srcl : bits(5) = inst[19..15];
+    exec_dc_csw(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00003019 then {
-    // LDI | ldi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 208}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b110_match_4(inst) then {
+    // DC.CVA | dc.cva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 135}
     let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_ldi(regdst, srcl, simm12)
+    exec_dc_cva(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00003029 then {
-    // LDI.U | ldi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 209}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b110_match_5(inst) then {
+    // DC.ISW | dc.isw SrcL | {'file': 'opcodes/lx_32.opc', 'line': 137}
     let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_ldi_u(regdst, srcl, simm12)
+    exec_dc_isw(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00001009 then {
-    // LH | lh [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 210}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b110_match_6(inst) then {
+    // DC.IVA | dc.iva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 138}
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_lh(regdst, srcl, srcr, srcrtype, shamt)
+    exec_dc_iva(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00001039 then {
-    // LH.PCR | lh.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 211}
-    let regdst : bits(5) = inst[11..7];
-    let simm17 : bits(17) = inst[31..15];
-    exec_lh_pcr(regdst, simm17)
+  else if decode_execute32_opcode_0b0101011_funct3_0b110_match_7(inst) then {
+    // DC.ZVA | dc.zva SrcL | {'file': 'opcodes/lx_32.opc', 'line': 139}
+    let srcl : bits(5) = inst[19..15];
+    exec_dc_zva(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00001019 then {
-    // LHI | lhi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 212}
-    let regdst : bits(5) = inst[11..7];
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffffffff) == 0x0030702b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b111_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0000702b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b111_match_2(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0020702b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b111_match_3(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0010702b
+}
+
+function decode_execute32_opcode_0b0101011_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0101011_funct3_0b111_match_0(inst) then {
+    // TLB.IALL | tlb.iall | {'file': 'opcodes/lx_32.opc', 'line': 338}
+    exec_tlb_iall()
+  }
+  else if decode_execute32_opcode_0b0101011_funct3_0b111_match_1(inst) then {
+    // TLB.IA | tlb.ia SrcL | {'file': 'opcodes/lx_32.opc', 'line': 337}
     let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lhi(regdst, srcl, simm12)
+    exec_tlb_ia(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00001029 then {
-    // LHI.U | lhi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 213}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b111_match_2(inst) then {
+    // TLB.IAV | tlb.iav SrcL | {'file': 'opcodes/lx_32.opc', 'line': 339}
     let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lhi_u(regdst, srcl, simm12)
+    exec_tlb_iav(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00005009 then {
-    // LHU | lhu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 214}
-    let regdst : bits(5) = inst[11..7];
+  else if decode_execute32_opcode_0b0101011_funct3_0b111_match_3(inst) then {
+    // TLB.IV | tlb.iv SrcL | {'file': 'opcodes/lx_32.opc', 'line': 340}
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_lhu(regdst, srcl, srcr, srcrtype, shamt)
+    exec_tlb_iv(srcl)
   }
-  else if (inst & 0x0000707f) == 0x00005039 then {
-    // LHU.PCR | lhu.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 215}
-    let regdst : bits(5) = inst[11..7];
-    let simm17 : bits(17) = inst[31..15];
-    exec_lhu_pcr(regdst, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00005019 then {
-    // LHUI | lhui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 216}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lhui(regdst, srcl, simm12)
+}
+
+function decode_execute32_opcode_0b0101011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0101011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0101011_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0101011_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0101011_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0101011_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0101011_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0101011_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b0101011_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00005029 then {
-    // LHUI.U | lhui.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 217}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lhui_u(regdst, srcl, simm12)
+}
+
+function decode_execute32_opcode_0b0110001_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x06007fff) == 0x00000031
+}
+
+function decode_execute32_opcode_0b0110001_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110001_funct3_0b000_match_0(inst) then {
+    // MCOPY | MCOPY [RegSrc0, RegSrc1, RegSrc2] | {'file': 'opcodes/lx_32.opc', 'line': 236}
+    let regsrc0 : bits(5) = inst[19..15];
+    let regsrc1 : bits(5) = inst[24..20];
+    let regsrc2 : bits(5) = inst[31..27];
+    exec_mcopy(regsrc0, regsrc1, regsrc2)
   }
-  else if (inst & 0x0000707f) == 0x00002009 then {
-    // LW | lw [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 224}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_lw(regdst, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00002039 then {
-    // LW.PCR | lw.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 228}
-    let regdst : bits(5) = inst[11..7];
-    let simm17 : bits(17) = inst[31..15];
-    exec_lw_pcr(regdst, simm17)
+}
+
+function decode_execute32_opcode_0b0110001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x06007fff) == 0x00001031
+}
+
+function decode_execute32_opcode_0b0110001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110001_funct3_0b001_match_0(inst) then {
+    // MSET | MSET [RegSrc0, RegSrc1, RegSrc2] | {'file': 'opcodes/lx_32.opc', 'line': 239}
+    let regsrc0 : bits(5) = inst[19..15];
+    let regsrc1 : bits(5) = inst[24..20];
+    let regsrc2 : bits(5) = inst[31..27];
+    exec_mset(regsrc0, regsrc1, regsrc2)
   }
-  else if (inst & 0x0000707f) == 0x00002019 then {
-    // LWI | lwi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 234}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lwi(regdst, srcl, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00002029 then {
-    // LWI.U | lwi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 235}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lwi_u(regdst, srcl, simm12)
+}
+
+function decode_execute32_opcode_0b0110001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x06007fff) == 0x00002031
+}
+
+function decode_execute32_opcode_0b0110001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110001_funct3_0b010_match_0(inst) then {
+    // ESAVE | ESAVE [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind] | {'file': 'opcodes/lx_32.opc', 'line': 240}
+    let regsrc0 : bits(5) = inst[19..15];
+    let regsrc1 : bits(5) = inst[24..20];
+    let regsrc2 : bits(5) = inst[31..27];
+    exec_esave(regsrc0, regsrc1, regsrc2)
   }
-  else if (inst & 0x0000707f) == 0x00006009 then {
-    // LWU | lwu [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 236}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_lwu(regdst, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00006039 then {
-    // LWU.PCR | lwu.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 237}
-    let regdst : bits(5) = inst[11..7];
-    let simm17 : bits(17) = inst[31..15];
-    exec_lwu_pcr(regdst, simm17)
+}
+
+function decode_execute32_opcode_0b0110001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x06007fff) == 0x00003031
+}
+
+function decode_execute32_opcode_0b0110001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110001_funct3_0b011_match_0(inst) then {
+    // ERCOV | ERCOV [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind] | {'file': 'opcodes/lx_32.opc', 'line': 241}
+    let regsrc0 : bits(5) = inst[19..15];
+    let regsrc1 : bits(5) = inst[24..20];
+    let regsrc2 : bits(5) = inst[31..27];
+    exec_ercov(regsrc0, regsrc1, regsrc2)
   }
-  else if (inst & 0x0000707f) == 0x00006019 then {
-    // LWUI | lwui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 238}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lwui(regdst, srcl, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0110001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0110001_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0110001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0110001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0110001_funct3_0b011(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0110011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00087fff) == 0x00000033
+}
+
+function decode_execute32_opcode_0b0110011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110011_funct3_0b000_match_0(inst) then {
+    // B.HINT | B.HINT {BR.{likely, unlikely}, TEMP.{hot, warm, cool, none}, PRFSIZE} | {'file': 'opcodes/lx_32.opc', 'line': 31}
+    let l_ul : bits(1) = inst[16];
+    let v : bits(1) = inst[15];
+    let prefetch_size : bits(12) = inst[31..20];
+    let temp : bits(2) = inst[18..17];
+    exec_b_hint()
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0110011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xffff7fff) == 0x00001033
+}
+
+function decode_execute32_opcode_0b0110011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110011_funct3_0b001_match_0(inst) then {
+    // B.HINT | B.HINT TRACE.{begin, end} | {'file': 'opcodes/lx_32.opc', 'line': 32}
+    let b_e : bits(1) = inst[15];
+    exec_b_hint()
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00006029 then {
-    // LWUI.U | lwui.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 239}
+}
+
+function decode_execute32_opcode_0b0110011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0110011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0110011_funct3_0b001(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000035
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110101_funct3_0b000_match_0(inst) then {
+    // ADDIW | addiw SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 15}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_lwui_u(regdst, srcl, simm12)
+    let uimm12 : bits(12) = inst[31..20];
+    exec_addiw(regdst, srcl, uimm12)
   }
-  else if (inst & 0x0000707f) == 0x00003005 then {
-    // OR | or SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 254}
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001035
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110101_funct3_0b001_match_0(inst) then {
+    // SUBIW | subiw SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 318}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_or(regdst, srcl, srcr, srcrtype, shamt)
+    let uimm12 : bits(12) = inst[31..20];
+    exec_subiw(regdst, srcl, uimm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00003015 then {
-    // ORI | ori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 255}
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002035
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110101_funct3_0b010_match_0(inst) then {
+    // ANDIW | andiw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 20}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let simm12 : bits(12) = inst[31..20];
-    exec_ori(regdst, srcl, simm12)
+    exec_andiw(regdst, srcl, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00003035 then {
-    // ORIW | oriw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 256}
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003035
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110101_funct3_0b011_match_0(inst) then {
+    // ORIW | oriw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 248}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let simm12 : bits(12) = inst[31..20];
     exec_orizw(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f) == 0x00003025 then {
-    // ORW | orw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 257}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_orw(regdst, srcl, srcr, srcrtype, shamt)
-  }
-  else if (inst & 0x0000707f) == 0x00007009 then {
-    // PRF | prf [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>] | {'file': 'opcodes/lx_32.opc', 'line': 258}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_prf(regdst, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00007029 then {
-    // PRFI.U | prfi.u [SrcL, simm] | {'file': 'opcodes/lx_32.opc', 'line': 259}
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004035
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110101_funct3_0b100_match_0(inst) then {
+    // XORIW | xoriw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 345}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
     let simm12 : bits(12) = inst[31..20];
-    exec_prfi_u(regdst, srcl, simm12)
+    exec_xoriw(regdst, srcl, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00007067 then {
-    // REV | rev SrcL,  M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 264}
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00005035
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110101_funct3_0b101_match_0(inst) then {
+    // SRLIW | srliw SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 311}
     let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let imml : bits(6) = inst[25..20];
-    let immr : bits(6) = inst[31..26];
-    exec_rev(regdst, srcl, imml, imml)
+    let shamt : bits(5) = inst[24..20];
+    exec_srliw(regdst, srcl, shamt)
   }
-  else if (inst & 0x0000707f) == 0x00000069 then {
-    // SB.PCR | sb.pcr SrcL, [symbol] | {'file': 'opcodes/lx_32.opc', 'line': 266}
-    let srcl : bits(5) = inst[19..15];
-    let simm : bits(17) = inst[11..7] @ inst[31..20];
-    exec_sb_pcr(srcl, simm)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00000059 then {
-    // SBI | sbi SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 267}
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00006035
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110101_funct3_0b110_match_0(inst) then {
+    // SRAIW | sraiw SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 307}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_sbi(srcl, srcr, simm12)
+    let shamt : bits(5) = inst[24..20];
+    exec_sraiw(regdst, srcl, shamt)
   }
-  else if (inst & 0x0000707f) == 0x00003069 then {
-    // SD.PCR | sd.pcr SrcL, [symbol] | {'file': 'opcodes/lx_32.opc', 'line': 277}
-    let srcl : bits(5) = inst[19..15];
-    let simm : bits(17) = inst[11..7] @ inst[31..20];
-    exec_sd_pcr(srcl, simm)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00003059 then {
-    // SDI | sdi SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 284}
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00007035
+}
+
+function decode_execute32_opcode_0b0110101_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110101_funct3_0b111_match_0(inst) then {
+    // SLLIW | slliw SrcL, shamt, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 303}
+    let regdst : bits(5) = inst[11..7];
     let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_sdi(srcl, srcr, simm12)
+    let shamt : bits(5) = inst[24..20];
+    exec_slliw(regdst, srcl, shamt)
   }
-  else if (inst & 0x0000707f) == 0x00007059 then {
-    // SDI.U | sdi.u SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 285}
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_sdi_u(srcl, srcr, simm12)
-  }
-  else if (inst & 0x0000707f) == 0x00002075 then {
-    // SETC.ANDI | setc.andi SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 287}
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[11..7];
-    let simm12 : bits(12) = inst[31..20];
-    exec_setc_andi(srcl, shamt, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00000075 then {
-    // SETC.EQI | setc.eqi SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 289}
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[11..7];
-    let simm12 : bits(12) = inst[31..20];
-    exec_setc_eqi(srcl, shamt, simm12)
+}
+
+function decode_execute32_opcode_0b0110101(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0110101_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0110101_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0110101_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0110101_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0110101_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0110101_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0110101_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b0110101_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00005075 then {
-    // SETC.GEI | setc.gei SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 291}
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[11..7];
-    let simm12 : bits(12) = inst[31..20];
-    exec_setc_gei(srcl, shamt, simm12)
+}
+
+function decode_execute32_opcode_0b0110111_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000037
+}
+
+function decode_execute32_opcode_0b0110111_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110111_funct3_0b000_match_0(inst) then {
+    // J | j label | {'file': 'opcodes/lx_32.opc', 'line': 182}
+    let simm22 : bits(22) = inst[11..7] @ inst[31..15];
+    exec_j(simm22)
   }
-  else if (inst & 0x0000707f) == 0x00007075 then {
-    // SETC.GEUI | setc.geui SrcL, uimm | {'file': 'opcodes/lx_32.opc', 'line': 293}
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[11..7];
-    let uimm12 : bits(12) = inst[31..20];
-    exec_setc_geui(srcl, shamt, uimm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00004075 then {
-    // SETC.LTI | setc.lti SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 295}
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[11..7];
-    let simm12 : bits(12) = inst[31..20];
-    exec_setc_lti(srcl, shamt, simm12)
+}
+
+function decode_execute32_opcode_0b0110111_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001037
+}
+
+function decode_execute32_opcode_0b0110111_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110111_funct3_0b001_match_0(inst) then {
+    // B.Z | b.z label | {'file': 'opcodes/lx_32.opc', 'line': 44}
+    let simm22 : bits(22) = inst[11..7] @ inst[31..15];
+    exec_b_z(simm22)
   }
-  else if (inst & 0x0000707f) == 0x00006075 then {
-    // SETC.LTUI | setc.ltui SrcL, uimm | {'file': 'opcodes/lx_32.opc', 'line': 297}
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[11..7];
-    let uimm12 : bits(12) = inst[31..20];
-    exec_setc_ltui(srcl, shamt, uimm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00001075 then {
-    // SETC.NEI | setc.nei SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 299}
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[11..7];
-    let simm12 : bits(12) = inst[31..20];
-    exec_setc_nei(srcl, shamt, simm12)
+}
+
+function decode_execute32_opcode_0b0110111_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002037
+}
+
+function decode_execute32_opcode_0b0110111_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0110111_funct3_0b010_match_0(inst) then {
+    // B.NZ | b.nz label | {'file': 'opcodes/lx_32.opc', 'line': 42}
+    let simm22 : bits(22) = inst[11..7] @ inst[31..15];
+    exec_b_nz(simm22)
   }
-  else if (inst & 0x0000707f) == 0x00003075 then {
-    // SETC.ORI | setc.ori SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 301}
-    let srcl : bits(5) = inst[19..15];
-    let shamt : bits(5) = inst[11..7];
-    let simm12 : bits(12) = inst[31..20];
-    exec_setc_ori(srcl, shamt, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00001069 then {
-    // SH.PCR | sh.pcr SrcL, [symbol] | {'file': 'opcodes/lx_32.opc', 'line': 305}
-    let srcl : bits(5) = inst[19..15];
-    let simm : bits(17) = inst[11..7] @ inst[31..20];
-    exec_sh_pcr(srcl, simm)
+}
+
+function decode_execute32_opcode_0b0110111(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0110111_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0110111_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0110111_funct3_0b010(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00001059 then {
-    // SHI | shi SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 307}
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_shi(srcl, srcr, simm12)
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000039
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111001_funct3_0b000_match_0(inst) then {
+    // LB.PCR | lb.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 185}
+    let regdst : bits(5) = inst[11..7];
+    let simm17 : bits(17) = inst[31..15];
+    exec_lb_pcr(regdst, simm17)
   }
-  else if (inst & 0x0000707f) == 0x00005059 then {
-    // SHI.U | shi.u SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 308}
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_shi_u(srcl, srcr, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x0000203b then {
-    // SSRSWAP | ssrswap SrcL, SSR_ID, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 323}
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001039
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111001_funct3_0b001_match_0(inst) then {
+    // LH.PCR | lh.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 203}
     let regdst : bits(5) = inst[11..7];
-    let ssr_id : bits(12) = inst[31..20];
-    let srcl : bits(5) = inst[19..15];
-    exec_ssrswap(regdst, srcl, ssr_id)
+    let simm17 : bits(17) = inst[31..15];
+    exec_lh_pcr(regdst, simm17)
   }
-  else if (inst & 0x0000707f) == 0x00001005 then {
-    // SUB | sub SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 324}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_sub(regdst, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00001015 then {
-    // SUBI | subi SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 325}
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002039
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111001_funct3_0b010_match_0(inst) then {
+    // LW.PCR | lw.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 220}
     let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let uimm12 : bits(12) = inst[31..20];
-    exec_subi(regdst, srcl, uimm12)
+    let simm17 : bits(17) = inst[31..15];
+    exec_lw_pcr(regdst, simm17)
   }
-  else if (inst & 0x0000707f) == 0x00001035 then {
-    // SUBIW | subiw SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 326}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let uimm12 : bits(12) = inst[31..20];
-    exec_subiw(regdst, srcl, uimm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00001025 then {
-    // SUBW | subw SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 327}
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003039
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111001_funct3_0b011_match_0(inst) then {
+    // LD.PCR | ld.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 194}
     let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_subw(regdst, srcl, srcr, srcrtype, shamt)
+    let simm17 : bits(17) = inst[31..15];
+    exec_ld_pcr(regdst, simm17)
   }
-  else if (inst & 0x0000707f) == 0x00002069 then {
-    // SW.PCR | sw.pcr SrcL, [symbol] | {'file': 'opcodes/lx_32.opc', 'line': 332}
-    let srcl : bits(5) = inst[19..15];
-    let simm : bits(17) = inst[11..7] @ inst[31..20];
-    exec_sw_pcr(srcl, simm)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00002059 then {
-    // SWI | swi SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 343}
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_swi(srcl, srcr, simm12)
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004039
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111001_funct3_0b100_match_0(inst) then {
+    // LBU.PCR | lbu.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 188}
+    let regdst : bits(5) = inst[11..7];
+    let simm17 : bits(17) = inst[31..15];
+    exec_lbu_pcr(regdst, simm17)
   }
-  else if (inst & 0x0000707f) == 0x00006059 then {
-    // SWI.U | swi.u SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 344}
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
-    exec_swi_u(srcl, srcr, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00004005 then {
-    // XOR | xor SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 351}
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00005039
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111001_funct3_0b101_match_0(inst) then {
+    // LHU.PCR | lhu.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 207}
     let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_xor(regdst, srcl, srcr, srcrtype, shamt)
+    let simm17 : bits(17) = inst[31..15];
+    exec_lhu_pcr(regdst, simm17)
   }
-  else if (inst & 0x0000707f) == 0x00004015 then {
-    // XORI | xori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 352}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_xori(regdst, srcl, simm12)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f) == 0x00004035 then {
-    // XORIW | xoriw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 353}
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00006039
+}
+
+function decode_execute32_opcode_0b0111001_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111001_funct3_0b110_match_0(inst) then {
+    // LWU.PCR | lwu.pcr [symbol], ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 229}
     let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let simm12 : bits(12) = inst[31..20];
-    exec_xoriw(regdst, srcl, simm12)
+    let simm17 : bits(17) = inst[31..15];
+    exec_lwu_pcr(regdst, simm17)
   }
-  else if (inst & 0x0000707f) == 0x00004025 then {
-    // XORW | xorw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 354}
-    let regdst : bits(5) = inst[11..7];
-    let srcl : bits(5) = inst[19..15];
-    let srcr : bits(5) = inst[24..20];
-    let srcrtype : bits(2) = inst[26..25];
-    let shamt : bits(5) = inst[31..27];
-    exec_xorw(regdst, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000007f) == 0x00000007 & (inst[11..7] != 0b01010) then {
-    // ADDTPC | addtpc simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 16}
+}
+
+function decode_execute32_opcode_0b0111001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0111001_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0111001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0111001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0111001_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0111001_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b0111001_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b0111001_funct3_0b110(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b0111011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x000ff07f) == 0x0000003b
+}
+
+function decode_execute32_opcode_0b0111011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111011_funct3_0b000_match_0(inst) then {
+    // SSRGET | ssrget SSR_ID, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 313}
     let regdst : bits(5) = inst[11..7];
-    let imm20 : bits(20) = inst[31..12];
-    exec_addtpc(regdst, imm20)
+    let ssr_id : bits(12) = inst[31..20];
+    exec_ssrget(regdst, ssr_id)
   }
-  else if (inst & 0x0000007f) == 0x00000003 then {
-    // B.TEXT | B.TEXT <label> | {'file': 'opcodes/lx_32.opc', 'line': 49}
-    let simm25 : bits(25) = inst[31..7];
-    exec_b_text()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000007f) == 0x00000011 then {
-    // BSTART | BSTART {DIRECT, CALL}, <label> | {'file': 'opcodes/lx_32.opc', 'line': 57}
-    let simm25 : bits(25) = inst[31..7];
-    decoded_block_target_pc_shadow = decode_block_target25(simm25);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_direct();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart()
+}
+
+function decode_execute32_opcode_0b0111011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x0000103b
+}
+
+function decode_execute32_opcode_0b0111011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111011_funct3_0b001_match_0(inst) then {
+    // SSRSET | ssrset SrcL, SSR_ID | {'file': 'opcodes/lx_32.opc', 'line': 314}
+    let ssr_id : bits(12) = inst[31..20];
+    let srcl : bits(5) = inst[19..15];
+    exec_ssrset(srcl, ssr_id)
   }
-  else if (inst & 0x0000007f) == 0x00000021 then {
-    // BSTART | BSTART COND, <label> | {'file': 'opcodes/lx_32.opc', 'line': 58}
-    let simm25 : bits(25) = inst[31..7];
-    decoded_block_target_pc_shadow = decode_block_target25(simm25);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_cond();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_bstart()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000007f) == 0x00000017 then {
-    // LUI | lui simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 223}
+}
+
+function decode_execute32_opcode_0b0111011_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x0000203b
+}
+
+function decode_execute32_opcode_0b0111011_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111011_funct3_0b010_match_0(inst) then {
+    // SSRSWAP | ssrswap SrcL, SSR_ID, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 315}
     let regdst : bits(5) = inst[11..7];
-    let imm20 : bits(20) = inst[31..12];
-    exec_lui(regdst, imm20)
+    let ssr_id : bits(12) = inst[31..20];
+    let srcl : bits(5) = inst[19..15];
+    exec_ssrswap(regdst, srcl, ssr_id)
   }
   else {
     trap_illegal_inst(read_pc_or_tpc())
   }
 }
 
-function decode_execute48(inst : bits(48)) -> unit = {
-  if (inst & 0xf000707fffff) == 0x0000107d000e then {
-    // HL.QPUSH | hl.qpush.{h,e,r,he,hr,er,her} SrcL, SrcR, ->{t, u} | {'file': 'opcodes/lx_hl48.opc', 'line': 138}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let e : bits(1) = inst[41];
-    let h : bits(1) = inst[43];
-    let r : bits(1) = inst[42];
-    exec_hl_qpush(regdst, srcl, srcr, e, h, r)
+function decode_execute32_opcode_0b0111011_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x000ff07f) == 0x0000303b
+}
+
+function decode_execute32_opcode_0b0111011_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111011_funct3_0b011_match_0(inst) then {
+    // LSRGET | lsrget LSR_ID, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 214}
+    let lsr_id : bits(12) = inst[31..20];
+    let regdst : bits(5) = inst[11..7];
+    exec_lsrget(regdst, lsr_id)
   }
-  else if (inst & 0xe000707fffff) == 0x0000007d000e then {
-    // HL.QMT | hl.qmt.{i,e,s,r,ie,is,ir,es,er,ies,ier} SrcL, SrcR, ->{t, u} | {'file': 'opcodes/lx_hl48.opc', 'line': 136}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let e : bits(1) = inst[41];
-    let i : bits(1) = inst[44];
-    let r : bits(1) = inst[42];
-    let s : bits(1) = inst[43];
-    exec_hl_qmt(regdst, srcl, srcr, e, i, r, s)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfe00707f07ff) == 0x00000057000e then {
-    // HL.DIV | hl.div SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 41}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_div(regdst0, regdst1, srcl, srcr)
+}
+
+function decode_execute32_opcode_0b0111011_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfff07fff) == 0x0000403b
+}
+
+function decode_execute32_opcode_0b0111011_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b0111011_funct3_0b100_match_0(inst) then {
+    // SETC.TGT | setc.tgt SrcL | {'file': 'opcodes/lx_32.opc', 'line': 294}
+    let srcl : bits(5) = inst[19..15];
+    exec_setc_tgt(srcl, 0b00)
   }
-  else if (inst & 0xfe00707f07ff) == 0x00001057000e then {
-    // HL.DIVU | hl.divu SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 42}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_divu(regdst0, regdst1, srcl, srcr)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfe00707f07ff) == 0x00003057000e then {
-    // HL.DIVUW | hl.divuw SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 43}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_divuw(regdst0, regdst1, srcl, srcr)
+}
+
+function decode_execute32_opcode_0b0111011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b0111011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b0111011_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b0111011_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b0111011_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b0111011_funct3_0b100(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfe00707f07ff) == 0x00002057000e then {
-    // HL.DIVW | hl.divw SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 44}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_divw(regdst0, regdst1, srcl, srcr)
+}
+
+function decode_execute32_opcode_0b1000001_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000041
+}
+
+function decode_execute32_opcode_0b1000001_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000001_funct3_0b000_match_0(inst) then {
+    // FENTRY | FENTRY [RegSrc0 ~ RegSrcn], sp!, uimm | {'file': 'opcodes/lx_32.opc', 'line': 157}
+    let srcbegin : bits(5) = inst[19..15];
+    let srcend : bits(5) = inst[24..20];
+    let uimm : bits(15) = inst[11..7] @ inst[31..25] @ 0b000;
+    exec_fentry(srcbegin, srcend, uimm)
   }
-  else if (inst & 0xfe00707f07ff) == 0x00000047000e then {
-    // HL.MUL | hl.mul SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 128}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_mul(regdst0, regdst1, srcl, srcr)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfe00707f07ff) == 0x00001047000e then {
-    // HL.MULU | hl.mulu SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 129}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_mulu(regdst0, regdst1, srcl, srcr)
+}
+
+function decode_execute32_opcode_0b1000001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001041
+}
+
+function decode_execute32_opcode_0b1000001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000001_funct3_0b001_match_0(inst) then {
+    // FEXIT | FEXIT [RegDst0 ~ RegDstn], sp!, uimm | {'file': 'opcodes/lx_32.opc', 'line': 160}
+    let dstbegin : bits(5) = inst[19..15];
+    let dstend : bits(5) = inst[24..20];
+    let uimm : bits(15) = inst[11..7] @ inst[31..25] @ 0b000;
+    exec_fexit(dstbegin, dstend, uimm)
   }
-  else if (inst & 0xfe00707f07ff) == 0x00004057000e then {
-    // HL.REM | hl.rem SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 139}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_rem(regdst0, regdst1, srcl, srcr)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfe00707f07ff) == 0x00005057000e then {
-    // HL.REMU | hl.remu SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 140}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_remu(regdst0, regdst1, srcl, srcr)
+}
+
+function decode_execute32_opcode_0b1000001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002041
+}
+
+function decode_execute32_opcode_0b1000001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000001_funct3_0b010_match_0(inst) then {
+    // FRET.RA | FRET.RA [RegDst0 ~ RegDstn], sp!, uimm | {'file': 'opcodes/lx_32.opc', 'line': 176}
+    let dstbegin : bits(5) = inst[19..15];
+    let dstend : bits(5) = inst[24..20];
+    let uimm : bits(15) = inst[11..7] @ inst[31..25] @ 0b000;
+    exec_fret_ra(dstbegin, dstend, uimm)
   }
-  else if (inst & 0xfe00707f07ff) == 0x00007057000e then {
-    // HL.REMUW | hl.remuw SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 141}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_remuw(regdst0, regdst1, srcl, srcr)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfe00707f07ff) == 0x00006057000e then {
-    // HL.REMW | hl.remw SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 142}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_remw(regdst0, regdst1, srcl, srcr)
+}
+
+function decode_execute32_opcode_0b1000001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003041
+}
+
+function decode_execute32_opcode_0b1000001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000001_funct3_0b011_match_0(inst) then {
+    // FRET.STK | FRET.STK [RegDst0 ~ RegDstn], sp!, uimm | {'file': 'opcodes/lx_32.opc', 'line': 177}
+    let dstbegin : bits(5) = inst[19..15];
+    let dstend : bits(5) = inst[24..20];
+    let uimm : bits(15) = inst[11..7] @ inst[31..25] @ 0b000;
+    exec_fret_stk(dstbegin, dstend, uimm)
   }
-  else if (inst & 0x00007fff07ff) == 0x00007009000e then {
-    // HL.PRF | hl.prf{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>] | {'file': 'opcodes/lx_hl48.opc', 'line': 132}
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let model : bits(5) = inst[15..11];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_prf(srcl, srcr, srcrtype, model, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf800707f07ff) == 0x0000207d000e then {
-    // HL.QPOP | hl.qpop.{e,r,er} SrcL, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 137}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let e : bits(1) = inst[41];
-    let r : bits(1) = inst[42];
-    exec_hl_qpop(regdst0, regdst1, srcl, srcr, e, r)
+}
+
+function decode_execute32_opcode_0b1000001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1000001_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1000001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1000001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1000001_funct3_0b011(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff07ff) == 0x00000049003e then {
-    // HL.SB.PO | hl.sb.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 144}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sb_po(regdst, srcd, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000043
+}
+
+function decode_execute32_opcode_0b1000011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000011_funct3_0b000_match_0(inst) then {
+    // B.DIM | B.DIM RegSrc, uimm, ->LB0 | {'file': 'opcodes/lx_32.opc', 'line': 26}
+    let regsrc : bits(5) = inst[19..15];
+    let uimm17 : bits(17) = inst[11..7] @ inst[31..20];
+    decoded_bdim_index_shadow = 0b00;
+    decoded_bdim_value_shadow = read_reg5(regsrc) + sail_zero_extend(uimm17, 64);
+    exec_b_dim()
   }
-  else if (inst & 0x00007fff07ff) == 0x00000049002e then {
-    // HL.SB.PR | hl.sb.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 145}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sb_pr(regdst, srcd, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007ffff83f) == 0x00000049001e then {
-    // HL.SBP | hl.sbp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_hl48.opc', 'line': 150}
-    let srcd : bits(5) = inst[47..43];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sbp(srcd, srcd1, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001043
+}
+
+function decode_execute32_opcode_0b1000011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000011_funct3_0b001_match_0(inst) then {
+    // B.DIM | B.DIM RegSrc, uimm, ->LB1 | {'file': 'opcodes/lx_32.opc', 'line': 27}
+    let regsrc : bits(5) = inst[19..15];
+    let uimm17 : bits(17) = inst[11..7] @ inst[31..20];
+    decoded_bdim_index_shadow = 0b01;
+    decoded_bdim_value_shadow = read_reg5(regsrc) + sail_zero_extend(uimm17, 64);
+    exec_b_dim()
   }
-  else if (inst & 0x00007fff07ff) == 0x00003049003e then {
-    // HL.SD.PO | hl.sd.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 152}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sd_po(regdst, srcd, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff07ff) == 0x00003049002e then {
-    // HL.SD.PR | hl.sd.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 153}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sd_pr(regdst, srcd, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000011_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002043
+}
+
+function decode_execute32_opcode_0b1000011_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000011_funct3_0b010_match_0(inst) then {
+    // B.DIM | B.DIM RegSrc, uimm, ->LB2 | {'file': 'opcodes/lx_32.opc', 'line': 25}
+    let regsrc : bits(5) = inst[19..15];
+    let uimm17 : bits(17) = inst[11..7] @ inst[31..20];
+    decoded_bdim_index_shadow = 0b10;
+    decoded_bdim_value_shadow = read_reg5(regsrc) + sail_zero_extend(uimm17, 64);
+    exec_b_dim()
   }
-  else if (inst & 0x00007fff07ff) == 0x00007049003e then {
-    // HL.SD.UPO | hl.sd.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 154}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sd_upo(regdst, srcd, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff07ff) == 0x00007049002e then {
-    // HL.SD.UPR | hl.sd.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 155}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sd_upr(regdst, srcd, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1000011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1000011_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1000011_funct3_0b010(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007ffff83f) == 0x00003049001e then {
-    // HL.SDP | hl.sdp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<3] | {'file': 'opcodes/lx_hl48.opc', 'line': 164}
-    let srcd : bits(5) = inst[47..43];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sdp(srcd, srcd1, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x00000045
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000101_funct3_0b000_match_0(inst) then {
+    // CMP.EQ | cmp.eq SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 116}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_cmp_eq(regdst, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x00007ffff83f) == 0x00007049001e then {
-    // HL.SDP.U | hl.sdp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_hl48.opc', 'line': 165}
-    let srcd : bits(5) = inst[47..43];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sdp_u(srcd, srcd1, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff07ff) == 0x00001049003e then {
-    // HL.SH.PO | hl.sh.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 176}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sh_po(regdst, srcd, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x00001045
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000101_funct3_0b001_match_0(inst) then {
+    // CMP.NE | cmp.ne SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 126}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_cmp_ne(regdst, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x00007fff07ff) == 0x00001049002e then {
-    // HL.SH.PR | hl.sh.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 177}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sh_pr(regdst, srcd, srcl, srcr, srcrtype)
-  }
-  else if (inst & 0x00007fff07ff) == 0x00005049003e then {
-    // HL.SH.UPO | hl.sh.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 178}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sh_upo(regdst, srcd, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff07ff) == 0x00005049002e then {
-    // HL.SH.UPR | hl.sh.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 179}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sh_upr(regdst, srcd, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x00002045
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000101_funct3_0b010_match_0(inst) then {
+    // CMP.AND | cmp.and SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 114}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_cmp_and(regdst, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x00007ffff83f) == 0x00001049001e then {
-    // HL.SHP | hl.shp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<1] | {'file': 'opcodes/lx_hl48.opc', 'line': 188}
-    let srcd : bits(5) = inst[47..43];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_shp(srcd, srcd1, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007ffff83f) == 0x00005049001e then {
-    // HL.SHP.U | hl.shp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_hl48.opc', 'line': 189}
-    let srcd : bits(5) = inst[47..43];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_shp_u(srcd, srcd1, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x00003045
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000101_funct3_0b011_match_0(inst) then {
+    // CMP.OR | cmp.or SrcL, SrcR<.sw, .uw, .not>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 128}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_cmp_or(regdst, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x00007fff07ff) == 0x00002049003e then {
-    // HL.SW.PO | hl.sw.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 195}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sw_po(regdst, srcd, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff07ff) == 0x00002049002e then {
-    // HL.SW.PR | hl.sw.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 196}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sw_pr(regdst, srcd, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x00004045
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000101_funct3_0b100_match_0(inst) then {
+    // CMP.LT | cmp.lt SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 122}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_cmp_lt(regdst, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x00007fff07ff) == 0x00006049003e then {
-    // HL.SW.UPO | hl.sw.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 197}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sw_upo(regdst, srcd, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff07ff) == 0x00006049002e then {
-    // HL.SW.UPR | hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 198}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_sw_upr(regdst, srcd, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x00005045
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000101_funct3_0b101_match_0(inst) then {
+    // CMP.GE | cmp.ge SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 118}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_cmp_ge(regdst, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x00007ffff83f) == 0x00002049001e then {
-    // HL.SWP | hl.swp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<2] | {'file': 'opcodes/lx_hl48.opc', 'line': 207}
-    let srcd : bits(5) = inst[47..43];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_swp(srcd, srcd1, srcl, srcr, srcrtype)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007ffff83f) == 0x00006049001e then {
-    // HL.SWP.U | hl.swp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_hl48.opc', 'line': 208}
-    let srcd : bits(5) = inst[47..43];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    exec_hl_swp_u(srcd, srcd1, srcl, srcr, srcrtype)
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x00006045
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000101_funct3_0b110_match_0(inst) then {
+    // CMP.LTU | cmp.ltu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 124}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_cmp_ltu(regdst, srcl, srcr, srcrtype)
   }
-  else if (inst & 0xf000707ff83f) == 0x0000600b000e then {
-    // HL.CASB | hl.casb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 27}
-    let regdst : bits(5) = inst[27..23];
-    let srcd : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let aq : bits(1) = inst[42];
-    let far : bits(1) = inst[43];
-    let rl : bits(1) = inst[41];
-    exec_hl_casb(regdst, srcl, srcr, srcd, aq, far, rl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707ff83f) == 0x3000600b000e then {
-    // HL.CASD | hl.casd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 28}
-    let regdst : bits(5) = inst[27..23];
-    let srcd : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let aq : bits(1) = inst[42];
-    let far : bits(1) = inst[43];
-    let rl : bits(1) = inst[41];
-    exec_hl_casd(regdst, srcl, srcr, srcd, aq, far, rl)
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x00007045
+}
+
+function decode_execute32_opcode_0b1000101_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000101_funct3_0b111_match_0(inst) then {
+    // CMP.GEU | cmp.geu SrcL, SrcR<{.sw, .uw}>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 120}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_cmp_geu(regdst, srcl, srcr, srcrtype)
   }
-  else if (inst & 0xf000707ff83f) == 0x1000600b000e then {
-    // HL.CASH | hl.cash<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 29}
-    let regdst : bits(5) = inst[27..23];
-    let srcd : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let aq : bits(1) = inst[42];
-    let far : bits(1) = inst[43];
-    let rl : bits(1) = inst[41];
-    exec_hl_cash(regdst, srcl, srcr, srcd, aq, far, rl)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf000707ff83f) == 0x2000600b000e then {
-    // HL.CASW | hl.casw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 30}
-    let regdst : bits(5) = inst[27..23];
-    let srcd : bits(5) = inst[10..6];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let aq : bits(1) = inst[42];
-    let far : bits(1) = inst[43];
-    let rl : bits(1) = inst[41];
-    exec_hl_casw(regdst, srcl, srcr, srcd, aq, far, rl)
+}
+
+function decode_execute32_opcode_0b1000101(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1000101_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1000101_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1000101_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1000101_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b1000101_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b1000101_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1000101_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1000101_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0600707f07ff) == 0x00006047000e then {
-    // HL.MADD | hl.madd SrcL, SrcR, SrcD, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 124}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_madd(regdst0, regdst1, srcd, srcl, srcr)
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00000047
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000111_funct3_0b000_match_0(inst) then {
+    // MUL | mul SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 242}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_mul(regdst, srcl, srcr)
   }
-  else if (inst & 0x0600707f07ff) == 0x00007047000e then {
-    // HL.MADDW | hl.maddw SrcL, SrcR, SrcD, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 125}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[47..43];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    exec_hl_maddw(regdst0, regdst1, srcd, srcl, srcr)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xfe00707f000f) == 0x0000204d000e then {
-    // HL.BFI | hl.bfi SrcL, SrcR, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 16}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let immr : bits(6) = inst[9..4];
-    let imms : bits(6) = inst[15..10];
-    exec_hl_bfi(regdst, srcl, srcr, immr, imms)
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00001047
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000111_funct3_0b001_match_0(inst) then {
+    // MULU | mulu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 243}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_mulu(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f07ff) == 0x0000105d000e then {
-    // HL.CCAT | hl.ccat SrcL, SrcR, shamt, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 31}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let shamt : bits(7) = inst[47..41];
-    exec_hl_ccat(regdst0, regdst1, srcl, srcr, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x0000205d000e then {
-    // HL.CCATW | hl.ccatw SrcL, SrcR, shamt, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 32}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let shamt : bits(7) = inst[47..41];
-    exec_hl_ccatw(regdst0, regdst1, srcl, srcr, shamt)
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00002047
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000111_funct3_0b010_match_0(inst) then {
+    // MULW | mulw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 245}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_mulw(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f07ff) == 0x00000009003e then {
-    // HL.LB.PO | hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 46}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lb_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00000009002e then {
-    // HL.LB.PR | hl.lb.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 47}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lb_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
-  }
-  else if (inst & 0x0000707f07ff) == 0x00000009001e then {
-    // HL.LBP | hl.lbp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 52}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lbp(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00003047
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000111_funct3_0b011_match_0(inst) then {
+    // MULUW | muluw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 244}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_muluw(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f07ff) == 0x00004009003e then {
-    // HL.LBU.PO | hl.lbu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 54}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lbu_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00004009002e then {
-    // HL.LBU.PR | hl.lbu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 55}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lbu_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0600707f) == 0x00006047
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000111_funct3_0b110_match_0(inst) then {
+    // MADD | madd SrcL, SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 232}
+    let regdst : bits(5) = inst[11..7];
+    let srcd : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_madd(regdst, srcd, srcl, srcr)
   }
-  else if (inst & 0x0000707f07ff) == 0x00004009001e then {
-    // HL.LBUP | hl.lbup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 60}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lbup(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00003009003e then {
-    // HL.LD.PO | hl.ld.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 62}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_ld_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0600707f) == 0x00007047
+}
+
+function decode_execute32_opcode_0b1000111_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1000111_funct3_0b111_match_0(inst) then {
+    // MADDW | maddw SrcL, SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 233}
+    let regdst : bits(5) = inst[11..7];
+    let srcd : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_maddw(regdst, srcd, srcl, srcr)
   }
-  else if (inst & 0x0000707f07ff) == 0x00003009002e then {
-    // HL.LD.PR | hl.ld.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 63}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_ld_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00003009001e then {
-    // HL.LDP | hl.ldp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 72}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_ldp(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1000111(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1000111_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1000111_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1000111_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1000111_funct3_0b011(inst),
+    0b110 => decode_execute32_opcode_0b1000111_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1000111_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00001009003e then {
-    // HL.LH.PO | hl.lh.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 74}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lh_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00000049
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001001_funct3_0b000_match_0(inst) then {
+    // SB | sb SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_32.opc', 'line': 257}
+    let srcd : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_sb(srcd, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f07ff) == 0x00001009002e then {
-    // HL.LH.PR | hl.lh.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 75}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lh_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00001009001e then {
-    // HL.LHP | hl.lhp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 84}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lhp(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00001049
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001001_funct3_0b001_match_0(inst) then {
+    // SH | sh SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1] | {'file': 'opcodes/lx_32.opc', 'line': 296}
+    let srcd : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_sh(srcd, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f07ff) == 0x00005009003e then {
-    // HL.LHU.PO | hl.lhu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 86}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lhu_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00005009002e then {
-    // HL.LHU.PR | hl.lhu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 87}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lhu_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00002049
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001001_funct3_0b010_match_0(inst) then {
+    // SW | sw SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2] | {'file': 'opcodes/lx_32.opc', 'line': 320}
+    let srcd : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_sw(srcd, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f07ff) == 0x00005009001e then {
-    // HL.LHUP | hl.lhup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 96}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lhup(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00002009003e then {
-    // HL.LW.PO | hl.lw.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 101}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lw_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00003049
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001001_funct3_0b011_match_0(inst) then {
+    // SD | sd SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3] | {'file': 'opcodes/lx_32.opc', 'line': 265}
+    let srcd : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_sd(srcd, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f07ff) == 0x00002009002e then {
-    // HL.LW.PR | hl.lw.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 102}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lw_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00002009001e then {
-    // HL.LWP | hl.lwp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 111}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lwp(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00005049
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001001_funct3_0b101_match_0(inst) then {
+    // SH.U | sh.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_32.opc', 'line': 298}
+    let srcd : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_sh_u(srcd, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f07ff) == 0x00006009003e then {
-    // HL.LWU.PO | hl.lwu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 113}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lwu_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00006009002e then {
-    // HL.LWU.PR | hl.lwu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 114}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lwu_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00006049
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001001_funct3_0b110_match_0(inst) then {
+    // SW.U | sw.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_32.opc', 'line': 327}
+    let srcd : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_sw_u(srcd, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f07ff) == 0x00006009001e then {
-    // HL.LWUP | hl.lwup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 123}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_lwup(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f07ff) == 0x00007009001e then {
-    // HL.PRF.A | hl.prf.a{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 133}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let srcrtype : bits(2) = inst[42..41];
-    let model : bits(5) = inst[15..11];
-    let shamt : bits(5) = inst[47..43];
-    exec_hl_prf_a(regdst, srcl, srcr, srcrtype, model, shamt)
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x00007fff) == 0x00007049
+}
+
+function decode_execute32_opcode_0b1001001_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001001_funct3_0b111_match_0(inst) then {
+    // SD.U | sd.u SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_32.opc', 'line': 272}
+    let srcd : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_sd_u(srcd, srcl, srcr, srcrtype)
   }
-  else if (inst & 0x00007fff003f) == 0x00007029000e then {
-    // HL.PRFI.U | hl.prfi.u{.l1,.l2,.l3} [SrcL, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 134}
-    let srcl : bits(5) = inst[35..31];
-    let model : bits(5) = inst[15..11];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_prfi_u(srcl, model, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff000f) == 0x00003101000e then {
-    // HL.BSTART.FP | HL.BSTART.FP COND, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 18}
-    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
-    decoded_block_target_pc_shadow = decode_block_target30(simm);
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_cond();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_fp()
+}
+
+function decode_execute32_opcode_0b1001001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1001001_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1001001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1001001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1001001_funct3_0b011(inst),
+    0b101 => decode_execute32_opcode_0b1001001_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1001001_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1001001_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff000f) == 0x00001101000e then {
-    // HL.BSTART.FP | HL.BSTART.FP FALL<, fixup_label> | {'file': 'opcodes/lx_hl48.opc', 'line': 19}
-    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
-    decoded_block_target_pc_shadow = decode_block_target30(simm);
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_fp()
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000004b
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001011_funct3_0b000_match_0(inst) then {
+    // FADD | fadd.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 147}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fadd(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x00007fff000f) == 0x00004101000e then {
-    // HL.BSTART.FP | HL.BSTART.FP CALL, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 20}
-    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
-    decoded_block_target_pc_shadow = decode_block_target30(simm);
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_call();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_fp()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff000f) == 0x00002101000e then {
-    // HL.BSTART.FP | HL.BSTART.FP DIRECT, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 21}
-    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
-    decoded_block_target_pc_shadow = decode_block_target30(simm);
-    decoded_block_type_shadow = 0b0010;
-    decoded_block_xfer_kind_shadow = block_xfer_direct();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_fp()
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000104b
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001011_funct3_0b001_match_0(inst) then {
+    // FSUB | fsub.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 179}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fsub(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x00007fff000f) == 0x00004001000e then {
-    // HL.BSTART.STD | HL.BSTART.STD CALL, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 22}
-    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
-    decoded_block_target_pc_shadow = decode_block_target30(simm);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_call();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_std()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff000f) == 0x00001001000e then {
-    // HL.BSTART.STD | HL.BSTART.STD FALL<, fixup_label> | {'file': 'opcodes/lx_hl48.opc', 'line': 23}
-    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
-    decoded_block_target_pc_shadow = decode_block_target30(simm);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_std()
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000204b
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001011_funct3_0b010_match_0(inst) then {
+    // FMUL | fmul.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 170}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fmul(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x00007fff000f) == 0x00003001000e then {
-    // HL.BSTART.STD | HL.BSTART.STD COND, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 24}
-    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
-    decoded_block_target_pc_shadow = decode_block_target30(simm);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_cond();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_std()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x00007fff000f) == 0x00002001000e then {
-    // HL.BSTART.STD | HL.BSTART.STD DIRECT, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 25}
-    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
-    decoded_block_target_pc_shadow = decode_block_target30(simm);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_direct();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_std()
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000304b
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001011_funct3_0b011_match_0(inst) then {
+    // FDIV | fdiv.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 154}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fdiv(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x00007fff000f) == 0x00001081000e then {
-    // HL.BSTART.SYS | HL.BSTART.SYS FALL<, fixup_label> | {'file': 'opcodes/lx_hl48.opc', 'line': 26}
-    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
-    decoded_block_target_pc_shadow = decode_block_target30(simm);
-    decoded_block_type_shadow = 0b0001;
-    decoded_block_xfer_kind_shadow = block_xfer_fall();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_sys()
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x000ff07f000f) == 0x0000003b000e then {
-    // HL.SSRGET | hl.ssrget SSR_ID, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 190}
-    let regdst : bits(5) = inst[27..23];
-    let ssr_id : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_ssrget(regdst, ssr_id)
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x0000404b
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001011_funct3_0b100_match_0(inst) then {
+    // FMADD | fmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 166}
+    let regdst : bits(5) = inst[11..7];
+    let srca : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fmadd(regdst, srca, srcl, srcr, srctype)
   }
-  else if (inst & 0x00007fff000f) == 0x0000103b000e then {
-    // HL.SSRSET | hl.ssrset SrcL, SSR_ID | {'file': 'opcodes/lx_hl48.opc', 'line': 191}
-    let ssr_id : bits(24) = inst[15..4] @ inst[47..36];
-    let srcl : bits(5) = inst[35..31];
-    exec_hl_ssrset(srcl, ssr_id)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0xf83f0000007f) == 0x501600000011 then {
-    // HL.BSTART CALL | HL.BSTART.CALL <br_label>, <rt_label>, ->ra | {'file': 'opcodes/lx_hl48.opc', 'line': 17}
-    let simm25 : bits(25) = inst[31..7];
-    let uimm5 : bits(5) = inst[42..38];
-    decoded_block_target_pc_shadow = decode_block_target25(simm25);
-    decoded_block_type_shadow = 0b0000;
-    decoded_block_xfer_kind_shadow = block_xfer_call();
-    decoded_block_contract_kind_shadow = 0b0000;
-    exec_hl_bstart_call(uimm5)
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x0000504b
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001011_funct3_0b101_match_0(inst) then {
+    // FMSUB | fmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 169}
+    let regdst : bits(5) = inst[11..7];
+    let srca : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fmsub(regdst, srca, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00000019000e then {
-    // HL.LBI | hl.lbi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 48}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lbi(regdst, srcl, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00000019003e then {
-    // HL.LBI.PO | hl.lbi.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 49}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lbi_po(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x0000604b
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001011_funct3_0b110_match_0(inst) then {
+    // FNMADD | fnmadd.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 173}
+    let regdst : bits(5) = inst[11..7];
+    let srca : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fnmadd(regdst, srca, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00000019002e then {
-    // HL.LBI.PR | hl.lbi.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 50}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lbi_pr(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00000019001e then {
-    // HL.LBIP | hl.lbip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 51}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lbip(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x0000704b
+}
+
+function decode_execute32_opcode_0b1001011_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1001011_funct3_0b111_match_0(inst) then {
+    // FNMSUB | fnmsub.{T} SrcL, SrcR, SrcA, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 174}
+    let regdst : bits(5) = inst[11..7];
+    let srca : bits(5) = inst[31..27];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fnmsub(regdst, srca, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00004019000e then {
-    // HL.LBUI | hl.lbui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 56}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lbui(regdst, srcl, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00004019003e then {
-    // HL.LBUI.PO | hl.lbui.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 57}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lbui_po(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1001011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1001011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1001011_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1001011_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1001011_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b1001011_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b1001011_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1001011_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1001011_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00004019002e then {
-    // HL.LBUI.PR | hl.lbui.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 58}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lbui_pr(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000055
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010101_funct3_0b000_match_0(inst) then {
+    // CMP.EQI | cmp.eqi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 117}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let simm12 : bits(12) = inst[31..20];
+    exec_cmp_eqi(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00004019001e then {
-    // HL.LBUIP | hl.lbuip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 59}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lbuip(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00003019000e then {
-    // HL.LDI | hl.ldi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 64}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_ldi(regdst, srcl, simm22)
-  }
-  else if (inst & 0x0000707f003f) == 0x00003019003e then {
-    // HL.LDI.PO | hl.ldi.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 65}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_ldi_po(regdst0, regdst1, srcl, simm17)
-  }
-  else if (inst & 0x0000707f003f) == 0x00003019002e then {
-    // HL.LDI.PR | hl.ldi.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 66}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_ldi_pr(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001055
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010101_funct3_0b001_match_0(inst) then {
+    // CMP.NEI | cmp.nei SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 127}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let simm12 : bits(12) = inst[31..20];
+    exec_cmp_nei(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00003029000e then {
-    // HL.LDI.U | hl.ldi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 67}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_ldi_u(regdst, srcl, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00003029003e then {
-    // HL.LDI.UPO | hl.ldi.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 68}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_ldi_upo(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002055
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010101_funct3_0b010_match_0(inst) then {
+    // CMP.ANDI | cmp.andi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 115}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let simm12 : bits(12) = inst[31..20];
+    exec_cmp_andi(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00003029002e then {
-    // HL.LDI.UPR | hl.ldi.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 69}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_ldi_upr(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00003019001e then {
-    // HL.LDIP | hl.ldip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 70}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_ldip(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003055
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010101_funct3_0b011_match_0(inst) then {
+    // CMP.ORI | cmp.ori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 129}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let simm12 : bits(12) = inst[31..20];
+    exec_cmp_ori(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00003029001e then {
-    // HL.LDIP.U | hl.ldip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 71}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_ldip_u(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00001019000e then {
-    // HL.LHI | hl.lhi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 76}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lhi(regdst, srcl, simm22)
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004055
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010101_funct3_0b100_match_0(inst) then {
+    // CMP.LTI | cmp.lti SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 123}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let simm12 : bits(12) = inst[31..20];
+    exec_cmp_lti(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00001019003e then {
-    // HL.LHI.PO | hl.lhi.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 77}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhi_po(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00001019002e then {
-    // HL.LHI.PR | hl.lhi.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 78}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhi_pr(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00005055
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010101_funct3_0b101_match_0(inst) then {
+    // CMP.GEI | cmp.gei SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 119}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let simm12 : bits(12) = inst[31..20];
+    exec_cmp_gei(regdst, srcl, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00001029000e then {
-    // HL.LHI.U | hl.lhi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 79}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lhi_u(regdst, srcl, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00001029003e then {
-    // HL.LHI.UPO | hl.lhi.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 80}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhi_upo(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00006055
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010101_funct3_0b110_match_0(inst) then {
+    // CMP.LTUI | cmp.ltui SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 125}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let uimm12 : bits(12) = inst[31..20];
+    exec_cmp_ltui(regdst, srcl, uimm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00001029002e then {
-    // HL.LHI.UPR | hl.lhi.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 81}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhi_upr(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00001019001e then {
-    // HL.LHIP | hl.lhip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 82}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhip(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00007055
+}
+
+function decode_execute32_opcode_0b1010101_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010101_funct3_0b111_match_0(inst) then {
+    // CMP.GEUI | cmp.geui SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 121}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let uimm12 : bits(12) = inst[31..20];
+    exec_cmp_geui(regdst, srcl, uimm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00001029001e then {
-    // HL.LHIP.U | hl.lhip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 83}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhip_u(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00005019000e then {
-    // HL.LHUI | hl.lhui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 88}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lhui(regdst, srcl, simm22)
+}
+
+function decode_execute32_opcode_0b1010101(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1010101_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1010101_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1010101_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1010101_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b1010101_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b1010101_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1010101_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1010101_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00005019003e then {
-    // HL.LHUI.PO | hl.lhui.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 89}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhui_po(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00000057
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010111_funct3_0b000_match_0(inst) then {
+    // DIV | div SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 141}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_div(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00005019002e then {
-    // HL.LHUI.PR | hl.lhui.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 90}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhui_pr(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00005029000e then {
-    // HL.LHUI.U | hl.lhui.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 91}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lhui_u(regdst, srcl, simm22)
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00001057
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010111_funct3_0b001_match_0(inst) then {
+    // DIVU | divu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 142}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_divu(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00005029003e then {
-    // HL.LHUI.UPO | hl.lhui.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 92}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhui_upo(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00005029002e then {
-    // HL.LHUI.UPR | hl.lhui.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 93}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhui_upr(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00002057
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010111_funct3_0b010_match_0(inst) then {
+    // DIVW | divw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 144}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_divw(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00005019001e then {
-    // HL.LHUIP | hl.lhuip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 94}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhuip(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00005029001e then {
-    // HL.LHUIP.U | hl.lhuip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 95}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lhuip_u(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00003057
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010111_funct3_0b011_match_0(inst) then {
+    // DIVUW | divuw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 143}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_divuw(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00002019000e then {
-    // HL.LWI | hl.lwi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 103}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lwi(regdst, srcl, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00002019003e then {
-    // HL.LWI.PO | hl.lwi.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 104}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwi_po(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00004057
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010111_funct3_0b100_match_0(inst) then {
+    // REM | rem SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 252}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_rem(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00002019002e then {
-    // HL.LWI.PR | hl.lwi.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 105}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwi_pr(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00002029000e then {
-    // HL.LWI.U | hl.lwi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 106}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lwi_u(regdst, srcl, simm22)
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00005057
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010111_funct3_0b101_match_0(inst) then {
+    // REMU | remu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 253}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_remu(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00002029003e then {
-    // HL.LWI.UPO | hl.lwi.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 107}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwi_upo(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00002029002e then {
-    // HL.LWI.UPR | hl.lwi.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 108}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwi_upr(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00006057
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010111_funct3_0b110_match_0(inst) then {
+    // REMW | remw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 255}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_remw(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00002019001e then {
-    // HL.LWIP | hl.lwip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 109}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwip(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00002029001e then {
-    // HL.LWIP.U | hl.lwip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 110}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwip_u(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x00007057
+}
+
+function decode_execute32_opcode_0b1010111_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1010111_funct3_0b111_match_0(inst) then {
+    // REMUW | remuw SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 254}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_remuw(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00006019000e then {
-    // HL.LWUI | hl.lwui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 115}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lwui(regdst, srcl, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00006019003e then {
-    // HL.LWUI.PO | hl.lwui.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 116}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwui_po(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1010111(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1010111_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1010111_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1010111_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1010111_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b1010111_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b1010111_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1010111_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1010111_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00006019002e then {
-    // HL.LWUI.PR | hl.lwui.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 117}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwui_pr(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000059
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011001_funct3_0b000_match_0(inst) then {
+    // SBI | sbi SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 259}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
+    exec_sbi(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00006029000e then {
-    // HL.LWUI.U | hl.lwui.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 118}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
-    exec_hl_lwui_u(regdst, srcl, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00006029003e then {
-    // HL.LWUI.UPO | hl.lwui.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 119}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwui_upo(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001059
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011001_funct3_0b001_match_0(inst) then {
+    // SHI | shi SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 299}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
+    exec_shi(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00006029002e then {
-    // HL.LWUI.UPR | hl.lwui.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 120}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwui_upr(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00006019001e then {
-    // HL.LWUIP | hl.lwuip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 121}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwuip(regdst0, regdst1, srcl, simm17)
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002059
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011001_funct3_0b010_match_0(inst) then {
+    // SWI | swi SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 335}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
+    exec_swi(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00006029001e then {
-    // HL.LWUIP.U | hl.lwuip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 122}
-    let regdst0 : bits(5) = inst[27..23];
-    let regdst1 : bits(5) = inst[15..11];
-    let srcl : bits(5) = inst[35..31];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_lwuip_u(regdst0, regdst1, srcl, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00007029001e then {
-    // HL.PRFI.UA | hl.prfi.ua{.l1,.l2,.l3} [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 135}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let model : bits(5) = inst[15..11];
-    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
-    exec_hl_prfi_ua(regdst, srcl, model, simm17)
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003059
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011001_funct3_0b011_match_0(inst) then {
+    // SDI | sdi SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 276}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
+    exec_sdi(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00000059000e then {
-    // HL.SBI | hl.sbi SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 146}
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_sbi(srcd, srcr, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00000059003e then {
-    // HL.SBI.PO | hl.sbi.po SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 147}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_sbi_po(regdst, srcd, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00005059
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011001_funct3_0b101_match_0(inst) then {
+    // SHI.U | shi.u SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 300}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
+    exec_shi_u(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00000059002e then {
-    // HL.SBI.PR | hl.sbi.pr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 148}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_sbi_pr(regdst, srcd, srcr, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00000059001e then {
-    // HL.SBIP | hl.sbip SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 149}
-    let srcd : bits(5) = inst[35..31];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
-    exec_hl_sbip(srcd, srcd1, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00006059
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011001_funct3_0b110_match_0(inst) then {
+    // SWI.U | swi.u SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 336}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
+    exec_swi_u(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00003059000e then {
-    // HL.SDI | hl.sdi SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 156}
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_sdi(srcd, srcr, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00003059003e then {
-    // HL.SDI.PO | hl.sdi.po SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 157}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_sdi_po(regdst, srcd, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00007059
+}
+
+function decode_execute32_opcode_0b1011001_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011001_funct3_0b111_match_0(inst) then {
+    // SDI.U | sdi.u SrcL, [SrcR, simm] | {'file': 'opcodes/lx_32.opc', 'line': 277}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let simm12 : bits(12) = inst[11..7] @ inst[31..25];
+    exec_sdi_u(srcl, srcr, simm12)
   }
-  else if (inst & 0x0000707f003f) == 0x00003059002e then {
-    // HL.SDI.PR | hl.sdi.pr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 158}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_sdi_pr(regdst, srcd, srcr, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00007059000e then {
-    // HL.SDI.U | hl.sdi.u SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 159}
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_sdi_u(srcd, srcr, simm22)
+}
+
+function decode_execute32_opcode_0b1011001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1011001_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1011001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1011001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1011001_funct3_0b011(inst),
+    0b101 => decode_execute32_opcode_0b1011001_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1011001_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1011001_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00007059003e then {
-    // HL.SDI.UPO | hl.sdi.upo SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 160}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_sdi_upo(regdst, srcd, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000005b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b000_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0800005b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011011_funct3_0b000_match_0(inst) then {
+    // FEQ | feq.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 158}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_feq(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00007059002e then {
-    // HL.SDI.UPR | hl.sdi.upr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 161}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_sdi_upr(regdst, srcd, srcr, simm17)
+  else if decode_execute32_opcode_0b1011011_funct3_0b000_match_1(inst) then {
+    // FEQS | feqs.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 159}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_feqs(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00003059001e then {
-    // HL.SDIP | hl.sdip SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 162}
-    let srcd : bits(5) = inst[35..31];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
-    exec_hl_sdip(srcd, srcd1, srcr, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00007059001e then {
-    // HL.SDIP.U | hl.sdip.u SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 163}
-    let srcd : bits(5) = inst[35..31];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
-    exec_hl_sdip_u(srcd, srcd1, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000105b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b001_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0800105b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011011_funct3_0b001_match_0(inst) then {
+    // FNE | fne.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 171}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fne(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x00000fff000f) == 0x00000507000e then {
-    // HL.SETRET | hl.setret imm, ->Ra | {'file': 'opcodes/lx_hl48.opc', 'line': 174}
-    let imm32 : bits(32) = inst[15..4] @ inst[47..28];
-    exec_hl_setret(imm32)
+  else if decode_execute32_opcode_0b1011011_funct3_0b001_match_1(inst) then {
+    // FNES | fnes.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 172}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fnes(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00001059000e then {
-    // HL.SHI | hl.shi SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 180}
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_shi(srcd, srcr, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00001059003e then {
-    // HL.SHI.PO | hl.shi.po SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 181}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_shi_po(regdst, srcd, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000205b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b010_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0800205b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011011_funct3_0b010_match_0(inst) then {
+    // FLT | flt.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 164}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_flt(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00001059002e then {
-    // HL.SHI.PR | hl.shi.pr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 182}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_shi_pr(regdst, srcd, srcr, simm17)
+  else if decode_execute32_opcode_0b1011011_funct3_0b010_match_1(inst) then {
+    // FLTS | flts.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 165}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_flts(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00005059000e then {
-    // HL.SHI.U | hl.shi.u SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 183}
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_shi_u(srcd, srcr, simm22)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00005059003e then {
-    // HL.SHI.UPO | hl.shi.upo SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 184}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_shi_upo(regdst, srcd, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000305b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b011_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0800305b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011011_funct3_0b011_match_0(inst) then {
+    // FGE | fge.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 162}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fge(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00005059002e then {
-    // HL.SHI.UPR | hl.shi.upr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 185}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_shi_upr(regdst, srcd, srcr, simm17)
+  else if decode_execute32_opcode_0b1011011_funct3_0b011_match_1(inst) then {
+    // FGES | fges.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 163}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fges(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00001059001e then {
-    // HL.SHIP | hl.ship SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 186}
-    let srcd : bits(5) = inst[35..31];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
-    exec_hl_ship(srcd, srcd1, srcr, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00005059001e then {
-    // HL.SHIP.U | hl.ship.u SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 187}
-    let srcd : bits(5) = inst[35..31];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
-    exec_hl_ship_u(srcd, srcd1, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x0000405b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b100_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x0800405b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011011_funct3_0b100_match_0(inst) then {
+    // MAX | max SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 234}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_max(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00002059000e then {
-    // HL.SWI | hl.swi SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 199}
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_swi(srcd, srcr, simm22)
+  else if decode_execute32_opcode_0b1011011_funct3_0b100_match_1(inst) then {
+    // MAXU | maxu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 235}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_maxu(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00002059003e then {
-    // HL.SWI.PO | hl.swi.po SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 200}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_swi_po(regdst, srcd, srcr, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00002059002e then {
-    // HL.SWI.PR | hl.swi.pr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 201}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_swi_pr(regdst, srcd, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x0000505b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b101_match_1(inst : bits(32)) -> bool = {
+  (inst & 0xfe00707f) == 0x0800505b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011011_funct3_0b101_match_0(inst) then {
+    // MIN | min SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 237}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_min(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00006059000e then {
-    // HL.SWI.U | hl.swi.u SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 202}
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_swi_u(srcd, srcr, simm22)
+  else if decode_execute32_opcode_0b1011011_funct3_0b101_match_1(inst) then {
+    // MINU | minu SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 238}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    exec_minu(regdst, srcl, srcr)
   }
-  else if (inst & 0x0000707f003f) == 0x00006059003e then {
-    // HL.SWI.UPO | hl.swi.upo SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 203}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_swi_upo(regdst, srcd, srcr, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00006059002e then {
-    // HL.SWI.UPR | hl.swi.upr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 204}
-    let regdst : bits(5) = inst[15..11];
-    let srcd : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
-    exec_hl_swi_upr(regdst, srcd, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000605b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011011_funct3_0b110_match_0(inst) then {
+    // FMAX | fmax.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 167}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fmax(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f003f) == 0x00002059001e then {
-    // HL.SWIP | hl.swip SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 205}
-    let srcd : bits(5) = inst[35..31];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
-    exec_hl_swip(srcd, srcd1, srcr, simm17)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f003f) == 0x00006059001e then {
-    // HL.SWIP.U | hl.swip.u SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 206}
-    let srcd : bits(5) = inst[35..31];
-    let srcd1 : bits(5) = inst[10..6];
-    let srcr : bits(5) = inst[40..36];
-    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
-    exec_hl_swip_u(srcd, srcd1, srcr, simm17)
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf800707f) == 0x0000705b
+}
+
+function decode_execute32_opcode_0b1011011_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1011011_funct3_0b111_match_0(inst) then {
+    // FMIN | fmin.{T} SrcL, SrcR, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 168}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srctype : bits(2) = inst[26..25];
+    exec_fmin(regdst, srcl, srcr, srctype)
   }
-  else if (inst & 0x0000707f000f) == 0x00000015000e then {
-    // HL.ADDI | hl.addi SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 11}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_addi(regdst, srcl, uimm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00000035000e then {
-    // HL.ADDIW | hl.addiw SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 12}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_addiw(regdst, srcl, uimm24)
+}
+
+function decode_execute32_opcode_0b1011011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1011011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1011011_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1011011_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1011011_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b1011011_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b1011011_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1011011_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1011011_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00002015000e then {
-    // HL.ANDI | hl.andi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 14}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_andi(regdst, srcl, simm24)
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf8007fff) == 0x00000065
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100101_funct3_0b000_match_0(inst) then {
+    // SETC.EQ | setc.eq SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 280}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_setc_eq(srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f000f) == 0x00002035000e then {
-    // HL.ANDIW | hl.andiw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 15}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_andiw(regdst, srcl, simm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00002055000e then {
-    // HL.CMP.ANDI | hl.cmp.andi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 33}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_cmp_andi(regdst, srcl, simm24)
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf8007fff) == 0x00001065
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100101_funct3_0b001_match_0(inst) then {
+    // SETC.NE | setc.ne SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 290}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_setc_ne(srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f000f) == 0x00000055000e then {
-    // HL.CMP.EQI | hl.cmp.eqi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 34}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_cmp_eqi(regdst, srcl, simm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00005055000e then {
-    // HL.CMP.GEI | hl.cmp.gei SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 35}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_cmp_gei(regdst, srcl, simm24)
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf8007fff) == 0x00002065
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100101_funct3_0b010_match_0(inst) then {
+    // SETC.AND | setc.and SrcL, SrcR<.sw, .uw, .not> | {'file': 'opcodes/lx_32.opc', 'line': 278}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_setc_and(srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f000f) == 0x00007055000e then {
-    // HL.CMP.GEUI | hl.cmp.geui SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 36}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_cmp_geui(regdst, srcl, uimm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00004055000e then {
-    // HL.CMP.LTI | hl.cmp.lti SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 37}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_cmp_lti(regdst, srcl, simm24)
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf8007fff) == 0x00003065
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100101_funct3_0b011_match_0(inst) then {
+    // SETC.OR | setc.or SrcL, SrcR<.sw, .uw, .not> | {'file': 'opcodes/lx_32.opc', 'line': 292}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_setc_or(srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f000f) == 0x00006055000e then {
-    // HL.CMP.LTUI | hl.cmp.ltui SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 38}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_cmp_ltui(regdst, srcl, uimm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00001055000e then {
-    // HL.CMP.NEI | hl.cmp.nei SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 39}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_cmp_nei(regdst, srcl, simm24)
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf8007fff) == 0x00004065
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100101_funct3_0b100_match_0(inst) then {
+    // SETC.LT | setc.lt SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 286}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_setc_lt(srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f000f) == 0x00003055000e then {
-    // HL.CMP.ORI | hl.cmp.ori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 40}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_cmp_ori(regdst, srcl, simm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00000039000e then {
-    // HL.LB.PCR | hl.lb.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 45}
-    let regdst : bits(5) = inst[27..23];
-    let simm : bits(29) = inst[15..4] @ inst[47..31];
-    exec_hl_lb_pcr(regdst, simm)
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf8007fff) == 0x00005065
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100101_funct3_0b101_match_0(inst) then {
+    // SETC.GE | setc.ge SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 282}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_setc_ge(srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f000f) == 0x00004039000e then {
-    // HL.LBU.PCR | hl.lbu.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 53}
-    let regdst : bits(5) = inst[27..23];
-    let simm : bits(29) = inst[15..4] @ inst[47..31];
-    exec_hl_lbu_pcr(regdst, simm)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00003039000e then {
-    // HL.LD.PCR | hl.ld.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 61}
-    let regdst : bits(5) = inst[27..23];
-    let simm : bits(29) = inst[15..4] @ inst[47..31];
-    exec_hl_ld_pcr(regdst, simm)
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf8007fff) == 0x00006065
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100101_funct3_0b110_match_0(inst) then {
+    // SETC.LTU | setc.ltu SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 288}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_setc_ltu(srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f000f) == 0x00001039000e then {
-    // HL.LH.PCR | hl.lh.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 73}
-    let regdst : bits(5) = inst[27..23];
-    let simm : bits(29) = inst[15..4] @ inst[47..31];
-    exec_hl_lh_pcr(regdst, simm)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00005039000e then {
-    // HL.LHU.PCR | hl.lhu.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 85}
-    let regdst : bits(5) = inst[27..23];
-    let simm : bits(29) = inst[15..4] @ inst[47..31];
-    exec_hl_lhu_pcr(regdst, simm)
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf8007fff) == 0x00007065
+}
+
+function decode_execute32_opcode_0b1100101_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100101_funct3_0b111_match_0(inst) then {
+    // SETC.GEU | setc.geu SrcL, SrcR<{.sw, .uw}> | {'file': 'opcodes/lx_32.opc', 'line': 284}
+    let srcl : bits(5) = inst[19..15];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_setc_geu(srcl, srcr, srcrtype)
   }
-  else if (inst & 0x0000707f000f) == 0x00002039000e then {
-    // HL.LW.PCR | hl.lw.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 100}
-    let regdst : bits(5) = inst[27..23];
-    let simm : bits(29) = inst[15..4] @ inst[47..31];
-    exec_hl_lw_pcr(regdst, simm)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00006039000e then {
-    // HL.LWU.PCR | hl.lwu.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 112}
-    let regdst : bits(5) = inst[27..23];
-    let simm : bits(29) = inst[15..4] @ inst[47..31];
-    exec_hl_lwu_pcr(regdst, simm)
+}
+
+function decode_execute32_opcode_0b1100101(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1100101_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1100101_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1100101_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1100101_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b1100101_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b1100101_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1100101_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1100101_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x0000004d000e then {
-    // HL.MIADD | hl.miadd SrcL, SrcR, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 126}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let uimm19 : bits(19) = inst[15..4] @ inst[47..41];
-    exec_hl_miadd(regdst, srcl, srcr, uimm19)
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000067
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100111_funct3_0b000_match_0(inst) then {
+    // BXS | bxs SrcL, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 107}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let imml : bits(6) = inst[25..20];
+    let imms : bits(6) = inst[31..26];
+    exec_bxs(regdst, srcl, imms, imml)
   }
-  else if (inst & 0x0000707f000f) == 0x0000104d000e then {
-    // HL.MISUB | hl.misub SrcL, SrcR, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 127}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let srcr : bits(5) = inst[40..36];
-    let uimm19 : bits(19) = inst[15..4] @ inst[47..41];
-    exec_hl_misub(regdst, srcl, srcr, uimm19)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00003015000e then {
-    // HL.ORI | hl.ori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 130}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_ori(regdst, srcl, simm24)
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001067
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100111_funct3_0b001_match_0(inst) then {
+    // BXU | bxu SrcL, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 108}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let imml : bits(6) = inst[25..20];
+    let imms : bits(6) = inst[31..26];
+    exec_bxu(regdst, srcl, imms, imml)
   }
-  else if (inst & 0x0000707f000f) == 0x00003035000e then {
-    // HL.ORIW | hl.oriw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 131}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_oriw(regdst, srcl, simm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00000069000e then {
-    // HL.SB.PCR | hl.sb.pcr SrcL, [<symbol>] | {'file': 'opcodes/lx_hl48.opc', 'line': 143}
-    let srcl : bits(5) = inst[35..31];
-    let simm : bits(29) = inst[15..4] @ inst[27..23] @ inst[47..36];
-    exec_hl_sb_pcr(srcl, simm)
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002067
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100111_funct3_0b010_match_0(inst) then {
+    // BIC | bic SrcL, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 48}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let imml : bits(6) = inst[25..20];
+    let imms : bits(6) = inst[31..26];
+    exec_bic(regdst, srcl, imms, imml)
   }
-  else if (inst & 0x0000707f000f) == 0x00003069000e then {
-    // HL.SD.PCR | hl.sd.pcr SrcL, [<symbol>] | {'file': 'opcodes/lx_hl48.opc', 'line': 151}
-    let srcl : bits(5) = inst[35..31];
-    let simm : bits(29) = inst[15..4] @ inst[27..23] @ inst[47..36];
-    exec_hl_sd_pcr(srcl, simm)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00002075000e then {
-    // HL.SETC.ANDI | hl.setc.andi SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 166}
-    let srcl : bits(5) = inst[35..31];
-    let shamt : bits(5) = inst[27..23];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_setc_andi(srcl, shamt, simm24)
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003067
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100111_funct3_0b011_match_0(inst) then {
+    // BIS | bis SrcL, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 49}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let imml : bits(6) = inst[25..20];
+    let imms : bits(6) = inst[31..26];
+    exec_bis(regdst, srcl, imms, imml)
   }
-  else if (inst & 0x0000707f000f) == 0x00000075000e then {
-    // HL.SETC.EQI | hl.setc.eqi SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 167}
-    let srcl : bits(5) = inst[35..31];
-    let shamt : bits(5) = inst[27..23];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_setc_eqi(srcl, shamt, simm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00005075000e then {
-    // HL.SETC.GEI | hl.setc.gei SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 168}
-    let srcl : bits(5) = inst[35..31];
-    let shamt : bits(5) = inst[27..23];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_setc_gei(srcl, shamt, simm24)
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004067
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100111_funct3_0b100_match_0(inst) then {
+    // CTZ | ctz SrcL,  M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 131}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let imml : bits(6) = inst[25..20];
+    let imms : bits(6) = inst[31..26];
+    exec_ctz(regdst, srcl, imms, imml)
   }
-  else if (inst & 0x0000707f000f) == 0x00007075000e then {
-    // HL.SETC.GEUI | hl.setc.geui SrcL, uimm | {'file': 'opcodes/lx_hl48.opc', 'line': 169}
-    let srcl : bits(5) = inst[35..31];
-    let shamt : bits(5) = inst[27..23];
-    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_setc_geui(srcl, shamt, uimm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00004075000e then {
-    // HL.SETC.LTI | hl.setc.lti SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 170}
-    let srcl : bits(5) = inst[35..31];
-    let shamt : bits(5) = inst[27..23];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_setc_lti(srcl, shamt, simm24)
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00005067
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100111_funct3_0b101_match_0(inst) then {
+    // CLZ | clz SrcL,  M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 113}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let imml : bits(6) = inst[25..20];
+    let imms : bits(6) = inst[31..26];
+    exec_clz(regdst, srcl, imms, imml)
   }
-  else if (inst & 0x0000707f000f) == 0x00006075000e then {
-    // HL.SETC.LTUI | hl.setc.ltui SrcL, uimm | {'file': 'opcodes/lx_hl48.opc', 'line': 171}
-    let srcl : bits(5) = inst[35..31];
-    let shamt : bits(5) = inst[27..23];
-    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_setc_ltui(srcl, shamt, uimm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00001075000e then {
-    // HL.SETC.NEI | hl.setc.nei SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 172}
-    let srcl : bits(5) = inst[35..31];
-    let shamt : bits(5) = inst[27..23];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_setc_nei(srcl, shamt, simm24)
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00006067
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100111_funct3_0b110_match_0(inst) then {
+    // BCNT | bcnt srcL,  M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 47}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let imml : bits(6) = inst[25..20];
+    let imms : bits(6) = inst[31..26];
+    exec_bcnt(regdst, srcl, imms, imml)
   }
-  else if (inst & 0x0000707f000f) == 0x00003075000e then {
-    // HL.SETC.ORI | hl.setc.ori SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 173}
-    let srcl : bits(5) = inst[35..31];
-    let shamt : bits(5) = inst[27..23];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_setc_ori(srcl, shamt, simm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00001069000e then {
-    // HL.SH.PCR | hl.sh.pcr SrcL, [<symbol>] | {'file': 'opcodes/lx_hl48.opc', 'line': 175}
-    let srcl : bits(5) = inst[35..31];
-    let simm : bits(29) = inst[15..4] @ inst[27..23] @ inst[47..36];
-    exec_hl_sh_pcr(srcl, simm)
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00007067
+}
+
+function decode_execute32_opcode_0b1100111_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1100111_funct3_0b111_match_0(inst) then {
+    // REV | rev SrcL,  M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 256}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let imml : bits(6) = inst[25..20];
+    let immr : bits(6) = inst[31..26];
+    exec_rev(regdst, srcl, imml, imml)
   }
-  else if (inst & 0x0000707f000f) == 0x00001015000e then {
-    // HL.SUBI | hl.subi SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 192}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_subi(regdst, srcl, uimm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00001035000e then {
-    // HL.SUBIW | hl.subiw SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 193}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_subiw(regdst, srcl, uimm24)
+}
+
+function decode_execute32_opcode_0b1100111(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1100111_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1100111_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1100111_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1100111_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b1100111_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b1100111_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1100111_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1100111_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00002069000e then {
-    // HL.SW.PCR | hl.sw.pcr SrcL, [<symbol>] | {'file': 'opcodes/lx_hl48.opc', 'line': 194}
-    let srcl : bits(5) = inst[35..31];
-    let simm : bits(29) = inst[15..4] @ inst[27..23] @ inst[47..36];
-    exec_hl_sw_pcr(srcl, simm)
+}
+
+function decode_execute32_opcode_0b1101001_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000069
+}
+
+function decode_execute32_opcode_0b1101001_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101001_funct3_0b000_match_0(inst) then {
+    // SB.PCR | sb.pcr SrcL, [symbol] | {'file': 'opcodes/lx_32.opc', 'line': 258}
+    let srcl : bits(5) = inst[19..15];
+    let simm : bits(17) = inst[11..7] @ inst[31..20];
+    exec_sb_pcr(srcl, simm)
   }
-  else if (inst & 0x0000707f000f) == 0x00004015000e then {
-    // HL.XORI | hl.xori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 209}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_xori(regdst, srcl, simm24)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000707f000f) == 0x00004035000e then {
-    // HL.XORIW | hl.xoriw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 210}
-    let regdst : bits(5) = inst[27..23];
-    let srcl : bits(5) = inst[35..31];
-    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
-    exec_hl_xoriw(regdst, srcl, simm24)
+}
+
+function decode_execute32_opcode_0b1101001_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001069
+}
+
+function decode_execute32_opcode_0b1101001_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101001_funct3_0b001_match_0(inst) then {
+    // SH.PCR | sh.pcr SrcL, [symbol] | {'file': 'opcodes/lx_32.opc', 'line': 297}
+    let srcl : bits(5) = inst[19..15];
+    let simm : bits(17) = inst[11..7] @ inst[31..20];
+    exec_sh_pcr(srcl, simm)
   }
-  else if (inst & 0x0000007f000f) == 0x00000007000e & (inst[27..23] != 0b01010) then {
-    // HL.ADDTPC | hl.addtpc imm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 13}
-    let regdst : bits(5) = inst[27..23];
-    let imm32 : bits(32) = inst[15..4] @ inst[47..28];
-    exec_hl_addtpc(regdst, imm32)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000007f000f) == 0x0000000d000e then {
-    // HL.LIS | hl.lis simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 97}
-    let regdst : bits(5) = inst[27..23];
-    let simm32 : bits(32) = inst[15..4] @ inst[47..28];
-    exec_hl_lis(regdst, simm32)
+}
+
+function decode_execute32_opcode_0b1101001_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002069
+}
+
+function decode_execute32_opcode_0b1101001_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101001_funct3_0b010_match_0(inst) then {
+    // SW.PCR | sw.pcr SrcL, [symbol] | {'file': 'opcodes/lx_32.opc', 'line': 324}
+    let srcl : bits(5) = inst[19..15];
+    let simm : bits(17) = inst[11..7] @ inst[31..20];
+    exec_sw_pcr(srcl, simm)
   }
-  else if (inst & 0x0000007f000f) == 0x0000001d000e then {
-    // HL.LIU | hl.liu uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 98}
-    let regdst : bits(5) = inst[27..23];
-    let uimm32 : bits(32) = inst[15..4] @ inst[47..28];
-    exec_hl_liu(regdst, uimm32)
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
   }
-  else if (inst & 0x0000007f000f) == 0x00000017000e then {
-    // HL.LUI | hl.lui imm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 99}
-    let regdst : bits(5) = inst[27..23];
-    let imm : bits(32) = inst[15..4] @ inst[47..28];
-    exec_hl_lui(regdst, imm)
+}
+
+function decode_execute32_opcode_0b1101001_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003069
+}
+
+function decode_execute32_opcode_0b1101001_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101001_funct3_0b011_match_0(inst) then {
+    // SD.PCR | sd.pcr SrcL, [symbol] | {'file': 'opcodes/lx_32.opc', 'line': 269}
+    let srcl : bits(5) = inst[19..15];
+    let simm : bits(17) = inst[11..7] @ inst[31..20];
+    exec_sd_pcr(srcl, simm)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1101001(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1101001_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1101001_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1101001_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1101001_funct3_0b011(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x01f0707f) == 0x0000006b
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101011_funct3_0b000_match_0(inst) then {
+    // FCVT | fcvt.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 148}
+    let dsttype : bits(5) = inst[31..27];
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_fcvt(dsttype, regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x01f0707f) == 0x0000106b
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101011_funct3_0b001_match_0(inst) then {
+    // FCVTA | fcvta.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 149}
+    let dsttype : bits(5) = inst[31..27];
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_fcvta(dsttype, regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x01f0707f) == 0x0000206b
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101011_funct3_0b010_match_0(inst) then {
+    // FCVTM | fcvtm.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 150}
+    let dsttype : bits(5) = inst[31..27];
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_fcvtm(dsttype, regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x01f0707f) == 0x0000306b
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101011_funct3_0b011_match_0(inst) then {
+    // FCVTN | fcvtn.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 151}
+    let dsttype : bits(5) = inst[31..27];
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_fcvtn(dsttype, regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x01f0707f) == 0x0000406b
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101011_funct3_0b100_match_0(inst) then {
+    // FCVTP | fcvtp.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 152}
+    let dsttype : bits(5) = inst[31..27];
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_fcvtp(dsttype, regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x01f0707f) == 0x0000506b
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101011_funct3_0b101_match_0(inst) then {
+    // FCVTZ | fcvtz.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 153}
+    let dsttype : bits(5) = inst[31..27];
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_fcvtz(dsttype, regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x01f0707f) == 0x0000606b
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101011_funct3_0b110_match_0(inst) then {
+    // SCVTF | scvtf.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 264}
+    let dsttype : bits(5) = inst[31..27];
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_scvtf(dsttype, regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x01f0707f) == 0x0000706b
+}
+
+function decode_execute32_opcode_0b1101011_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1101011_funct3_0b111_match_0(inst) then {
+    // UCVTF | ucvtf.{srcT2dstT} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 341}
+    let dsttype : bits(5) = inst[31..27];
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_ucvtf(dsttype, regdst, srcl, srctype)
   }
   else {
     trap_illegal_inst(read_pc_or_tpc())
   }
 }
 
+function decode_execute32_opcode_0b1101011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1101011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1101011_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1101011_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1101011_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b1101011_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b1101011_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1101011_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1101011_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000075
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1110101_funct3_0b000_match_0(inst) then {
+    // SETC.EQI | setc.eqi SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 281}
+    let srcl : bits(5) = inst[19..15];
+    let shamt : bits(5) = inst[11..7];
+    let simm12 : bits(12) = inst[31..20];
+    exec_setc_eqi(srcl, shamt, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00001075
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1110101_funct3_0b001_match_0(inst) then {
+    // SETC.NEI | setc.nei SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 291}
+    let srcl : bits(5) = inst[19..15];
+    let shamt : bits(5) = inst[11..7];
+    let simm12 : bits(12) = inst[31..20];
+    exec_setc_nei(srcl, shamt, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00002075
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1110101_funct3_0b010_match_0(inst) then {
+    // SETC.ANDI | setc.andi SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 279}
+    let srcl : bits(5) = inst[19..15];
+    let shamt : bits(5) = inst[11..7];
+    let simm12 : bits(12) = inst[31..20];
+    exec_setc_andi(srcl, shamt, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00003075
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1110101_funct3_0b011_match_0(inst) then {
+    // SETC.ORI | setc.ori SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 293}
+    let srcl : bits(5) = inst[19..15];
+    let shamt : bits(5) = inst[11..7];
+    let simm12 : bits(12) = inst[31..20];
+    exec_setc_ori(srcl, shamt, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b100_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00004075
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b100(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1110101_funct3_0b100_match_0(inst) then {
+    // SETC.LTI | setc.lti SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 287}
+    let srcl : bits(5) = inst[19..15];
+    let shamt : bits(5) = inst[11..7];
+    let simm12 : bits(12) = inst[31..20];
+    exec_setc_lti(srcl, shamt, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b101_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00005075
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b101(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1110101_funct3_0b101_match_0(inst) then {
+    // SETC.GEI | setc.gei SrcL, simm | {'file': 'opcodes/lx_32.opc', 'line': 283}
+    let srcl : bits(5) = inst[19..15];
+    let shamt : bits(5) = inst[11..7];
+    let simm12 : bits(12) = inst[31..20];
+    exec_setc_gei(srcl, shamt, simm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b110_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00006075
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b110(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1110101_funct3_0b110_match_0(inst) then {
+    // SETC.LTUI | setc.ltui SrcL, uimm | {'file': 'opcodes/lx_32.opc', 'line': 289}
+    let srcl : bits(5) = inst[19..15];
+    let shamt : bits(5) = inst[11..7];
+    let uimm12 : bits(12) = inst[31..20];
+    exec_setc_ltui(srcl, shamt, uimm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b111_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00007075
+}
+
+function decode_execute32_opcode_0b1110101_funct3_0b111(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1110101_funct3_0b111_match_0(inst) then {
+    // SETC.GEUI | setc.geui SrcL, uimm | {'file': 'opcodes/lx_32.opc', 'line': 285}
+    let srcl : bits(5) = inst[19..15];
+    let shamt : bits(5) = inst[11..7];
+    let uimm12 : bits(12) = inst[31..20];
+    exec_setc_geui(srcl, shamt, uimm12)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110101(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1110101_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1110101_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1110101_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1110101_funct3_0b011(inst),
+    0b100 => decode_execute32_opcode_0b1110101_funct3_0b100(inst),
+    0b101 => decode_execute32_opcode_0b1110101_funct3_0b101(inst),
+    0b110 => decode_execute32_opcode_0b1110101_funct3_0b110(inst),
+    0b111 => decode_execute32_opcode_0b1110101_funct3_0b111(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110111_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0x0000707f) == 0x00000077
+}
+
+function decode_execute32_opcode_0b1110111_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1110111_funct3_0b000_match_0(inst) then {
+    // CSEL | csel SrcP, SrcL, SrcR<.neg>, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 130}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srcp : bits(5) = inst[31..27];
+    let srcr : bits(5) = inst[24..20];
+    let srcrtype : bits(2) = inst[26..25];
+    exec_csel(regdst, srcp, srcl, srcr, srcrtype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1110111(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1110111_funct3_0b000(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1111011_funct3_0b000_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf9f0707f) == 0x0000007b
+}
+
+function decode_execute32_opcode_0b1111011_funct3_0b000(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1111011_funct3_0b000_match_0(inst) then {
+    // FABS | fabs.{T} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 146}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_fabs(regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1111011_funct3_0b001_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf9f0707f) == 0x0000107b
+}
+
+function decode_execute32_opcode_0b1111011_funct3_0b001(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1111011_funct3_0b001_match_0(inst) then {
+    // FSQRT | fsqrt.{T} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 178}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_fsqrt(regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1111011_funct3_0b010_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf9f0707f) == 0x0000207b
+}
+
+function decode_execute32_opcode_0b1111011_funct3_0b010(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1111011_funct3_0b010_match_0(inst) then {
+    // FRECIP | frecip.{T} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 175}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_frecip(regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1111011_funct3_0b011_match_0(inst : bits(32)) -> bool = {
+  (inst & 0xf9f0707f) == 0x0000307b
+}
+
+function decode_execute32_opcode_0b1111011_funct3_0b011(inst : bits(32)) -> unit = {
+  if decode_execute32_opcode_0b1111011_funct3_0b011_match_0(inst) then {
+    // FEXP | fexp.{T} SrcL, ->{t, u, Rd} | {'file': 'opcodes/lx_32.opc', 'line': 161}
+    let regdst : bits(5) = inst[11..7];
+    let srcl : bits(5) = inst[19..15];
+    let srctype : bits(2) = inst[26..25];
+    exec_fexp(regdst, srcl, srctype)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32_opcode_0b1111011(inst : bits(32)) -> unit = {
+  match inst[14..12] {
+    0b000 => decode_execute32_opcode_0b1111011_funct3_0b000(inst),
+    0b001 => decode_execute32_opcode_0b1111011_funct3_0b001(inst),
+    0b010 => decode_execute32_opcode_0b1111011_funct3_0b010(inst),
+    0b011 => decode_execute32_opcode_0b1111011_funct3_0b011(inst),
+    _ => trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute32(inst : bits(32)) -> unit = {
+  if (inst & 0x0600707f) == 0x00001013 then {
+    // Reserved retired encoding: B.IOD
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+  else if (inst & 0x06007fff) == 0x02001181 then {
+    // Reserved retired encoding: BSTART.PAR
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+  else if (inst & 0xf83f000f) == 0x50160002 then {
+    // BSTART CALL | BSTART.CALL <br_label>, <rt_label>, ->ra | {'file': 'opcodes/lx_32.opc', 'line': 53}
+    let simm12 : bits(12) = inst[15..4];
+    let uimm5 : bits(5) = inst[26..22];
+    decoded_block_target_pc_shadow = decode_block_target12(simm12);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_call();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_bstart_call(uimm5)
+  }
+  else {
+    match inst[6..0] {
+      0b0000001 => decode_execute32_opcode_0b0000001(inst),
+      0b0000011 => decode_execute32_opcode_0b0000011(inst),
+      0b0000101 => decode_execute32_opcode_0b0000101(inst),
+      0b0000111 => decode_execute32_opcode_0b0000111(inst),
+      0b0001001 => decode_execute32_opcode_0b0001001(inst),
+      0b0001011 => decode_execute32_opcode_0b0001011(inst),
+      0b0010001 => decode_execute32_opcode_0b0010001(inst),
+      0b0010011 => decode_execute32_opcode_0b0010011(inst),
+      0b0010101 => decode_execute32_opcode_0b0010101(inst),
+      0b0010111 => decode_execute32_opcode_0b0010111(inst),
+      0b0011001 => decode_execute32_opcode_0b0011001(inst),
+      0b0011011 => decode_execute32_opcode_0b0011011(inst),
+      0b0100001 => decode_execute32_opcode_0b0100001(inst),
+      0b0100011 => decode_execute32_opcode_0b0100011(inst),
+      0b0100101 => decode_execute32_opcode_0b0100101(inst),
+      0b0100111 => decode_execute32_opcode_0b0100111(inst),
+      0b0101001 => decode_execute32_opcode_0b0101001(inst),
+      0b0101011 => decode_execute32_opcode_0b0101011(inst),
+      0b0110001 => decode_execute32_opcode_0b0110001(inst),
+      0b0110011 => decode_execute32_opcode_0b0110011(inst),
+      0b0110101 => decode_execute32_opcode_0b0110101(inst),
+      0b0110111 => decode_execute32_opcode_0b0110111(inst),
+      0b0111001 => decode_execute32_opcode_0b0111001(inst),
+      0b0111011 => decode_execute32_opcode_0b0111011(inst),
+      0b1000001 => decode_execute32_opcode_0b1000001(inst),
+      0b1000011 => decode_execute32_opcode_0b1000011(inst),
+      0b1000101 => decode_execute32_opcode_0b1000101(inst),
+      0b1000111 => decode_execute32_opcode_0b1000111(inst),
+      0b1001001 => decode_execute32_opcode_0b1001001(inst),
+      0b1001011 => decode_execute32_opcode_0b1001011(inst),
+      0b1010101 => decode_execute32_opcode_0b1010101(inst),
+      0b1010111 => decode_execute32_opcode_0b1010111(inst),
+      0b1011001 => decode_execute32_opcode_0b1011001(inst),
+      0b1011011 => decode_execute32_opcode_0b1011011(inst),
+      0b1100101 => decode_execute32_opcode_0b1100101(inst),
+      0b1100111 => decode_execute32_opcode_0b1100111(inst),
+      0b1101001 => decode_execute32_opcode_0b1101001(inst),
+      0b1101011 => decode_execute32_opcode_0b1101011(inst),
+      0b1110101 => decode_execute32_opcode_0b1110101(inst),
+      0b1110111 => decode_execute32_opcode_0b1110111(inst),
+      0b1111011 => decode_execute32_opcode_0b1111011(inst),
+      _ => trap_illegal_inst(read_pc_or_tpc())
+    }
+  }
+}
+
+function decode_execute48_match_0(inst : bits(48)) -> bool = {
+  (inst & 0xf000707fffff) == 0x0000107d000e
+}
+
+function decode_execute48_match_1(inst : bits(48)) -> bool = {
+  (inst & 0xe000707fffff) == 0x0000007d000e
+}
+
+function decode_execute48_match_2(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00000057000e
+}
+
+function decode_execute48_match_3(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00001057000e
+}
+
+function decode_execute48_match_4(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00003057000e
+}
+
+function decode_execute48_match_5(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00002057000e
+}
+
+function decode_execute48_match_6(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00000047000e
+}
+
+function decode_execute48_match_7(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00001047000e
+}
+
+function decode_execute48_match_8(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00004057000e
+}
+
+function decode_execute48_match_9(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00005057000e
+}
+
+function decode_execute48_match_10(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00007057000e
+}
+
+function decode_execute48_match_11(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f07ff) == 0x00006057000e
+}
+
+function decode_execute48_match_12(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00007009000e
+}
+
+function decode_execute48_match_13(inst : bits(48)) -> bool = {
+  (inst & 0xf800707f07ff) == 0x0000207d000e
+}
+
+function decode_execute48_match_14(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00000049003e
+}
+
+function decode_execute48_match_15(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00000049002e
+}
+
+function decode_execute48_match_16(inst : bits(48)) -> bool = {
+  (inst & 0x00007ffff83f) == 0x00000049001e
+}
+
+function decode_execute48_match_17(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00003049003e
+}
+
+function decode_execute48_match_18(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00003049002e
+}
+
+function decode_execute48_match_19(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00007049003e
+}
+
+function decode_execute48_match_20(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00007049002e
+}
+
+function decode_execute48_match_21(inst : bits(48)) -> bool = {
+  (inst & 0x00007ffff83f) == 0x00003049001e
+}
+
+function decode_execute48_match_22(inst : bits(48)) -> bool = {
+  (inst & 0x00007ffff83f) == 0x00007049001e
+}
+
+function decode_execute48_match_23(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00001049003e
+}
+
+function decode_execute48_match_24(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00001049002e
+}
+
+function decode_execute48_match_25(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00005049003e
+}
+
+function decode_execute48_match_26(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00005049002e
+}
+
+function decode_execute48_match_27(inst : bits(48)) -> bool = {
+  (inst & 0x00007ffff83f) == 0x00001049001e
+}
+
+function decode_execute48_match_28(inst : bits(48)) -> bool = {
+  (inst & 0x00007ffff83f) == 0x00005049001e
+}
+
+function decode_execute48_match_29(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00002049003e
+}
+
+function decode_execute48_match_30(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00002049002e
+}
+
+function decode_execute48_match_31(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00006049003e
+}
+
+function decode_execute48_match_32(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff07ff) == 0x00006049002e
+}
+
+function decode_execute48_match_33(inst : bits(48)) -> bool = {
+  (inst & 0x00007ffff83f) == 0x00002049001e
+}
+
+function decode_execute48_match_34(inst : bits(48)) -> bool = {
+  (inst & 0x00007ffff83f) == 0x00006049001e
+}
+
+function decode_execute48_match_35(inst : bits(48)) -> bool = {
+  (inst & 0xf000707ff83f) == 0x0000600b000e
+}
+
+function decode_execute48_match_36(inst : bits(48)) -> bool = {
+  (inst & 0xf000707ff83f) == 0x3000600b000e
+}
+
+function decode_execute48_match_37(inst : bits(48)) -> bool = {
+  (inst & 0xf000707ff83f) == 0x1000600b000e
+}
+
+function decode_execute48_match_38(inst : bits(48)) -> bool = {
+  (inst & 0xf000707ff83f) == 0x2000600b000e
+}
+
+function decode_execute48_match_39(inst : bits(48)) -> bool = {
+  (inst & 0x0600707f07ff) == 0x00006047000e
+}
+
+function decode_execute48_match_40(inst : bits(48)) -> bool = {
+  (inst & 0x0600707f07ff) == 0x00007047000e
+}
+
+function decode_execute48_match_41(inst : bits(48)) -> bool = {
+  (inst & 0xfe00707f000f) == 0x0000204d000e
+}
+
+function decode_execute48_match_42(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x0000105d000e
+}
+
+function decode_execute48_match_43(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x0000205d000e
+}
+
+function decode_execute48_match_44(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00000009003e
+}
+
+function decode_execute48_match_45(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00000009002e
+}
+
+function decode_execute48_match_46(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00000009001e
+}
+
+function decode_execute48_match_47(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00004009003e
+}
+
+function decode_execute48_match_48(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00004009002e
+}
+
+function decode_execute48_match_49(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00004009001e
+}
+
+function decode_execute48_match_50(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00003009003e
+}
+
+function decode_execute48_match_51(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00003009002e
+}
+
+function decode_execute48_match_52(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00003009001e
+}
+
+function decode_execute48_match_53(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00001009003e
+}
+
+function decode_execute48_match_54(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00001009002e
+}
+
+function decode_execute48_match_55(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00001009001e
+}
+
+function decode_execute48_match_56(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00005009003e
+}
+
+function decode_execute48_match_57(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00005009002e
+}
+
+function decode_execute48_match_58(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00005009001e
+}
+
+function decode_execute48_match_59(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00002009003e
+}
+
+function decode_execute48_match_60(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00002009002e
+}
+
+function decode_execute48_match_61(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00002009001e
+}
+
+function decode_execute48_match_62(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00006009003e
+}
+
+function decode_execute48_match_63(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00006009002e
+}
+
+function decode_execute48_match_64(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00006009001e
+}
+
+function decode_execute48_match_65(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f07ff) == 0x00007009001e
+}
+
+function decode_execute48_match_66(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff003f) == 0x00007029000e
+}
+
+function decode_execute48_match_67(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x00003101000e
+}
+
+function decode_execute48_match_68(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x00001101000e
+}
+
+function decode_execute48_match_69(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x00004101000e
+}
+
+function decode_execute48_match_70(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x00002101000e
+}
+
+function decode_execute48_match_71(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x00004001000e
+}
+
+function decode_execute48_match_72(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x00001001000e
+}
+
+function decode_execute48_match_73(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x00003001000e
+}
+
+function decode_execute48_match_74(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x00002001000e
+}
+
+function decode_execute48_match_75(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x00001081000e
+}
+
+function decode_execute48_match_76(inst : bits(48)) -> bool = {
+  (inst & 0x000ff07f000f) == 0x0000003b000e
+}
+
+function decode_execute48_match_77(inst : bits(48)) -> bool = {
+  (inst & 0x00007fff000f) == 0x0000103b000e
+}
+
+function decode_execute48_match_78(inst : bits(48)) -> bool = {
+  (inst & 0xf83f0000007f) == 0x501600000011
+}
+
+function decode_execute48_match_79(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00000019000e
+}
+
+function decode_execute48_match_80(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00000019003e
+}
+
+function decode_execute48_match_81(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00000019002e
+}
+
+function decode_execute48_match_82(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00000019001e
+}
+
+function decode_execute48_match_83(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00004019000e
+}
+
+function decode_execute48_match_84(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00004019003e
+}
+
+function decode_execute48_match_85(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00004019002e
+}
+
+function decode_execute48_match_86(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00004019001e
+}
+
+function decode_execute48_match_87(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003019000e
+}
+
+function decode_execute48_match_88(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003019003e
+}
+
+function decode_execute48_match_89(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003019002e
+}
+
+function decode_execute48_match_90(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003029000e
+}
+
+function decode_execute48_match_91(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003029003e
+}
+
+function decode_execute48_match_92(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003029002e
+}
+
+function decode_execute48_match_93(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003019001e
+}
+
+function decode_execute48_match_94(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003029001e
+}
+
+function decode_execute48_match_95(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001019000e
+}
+
+function decode_execute48_match_96(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001019003e
+}
+
+function decode_execute48_match_97(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001019002e
+}
+
+function decode_execute48_match_98(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001029000e
+}
+
+function decode_execute48_match_99(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001029003e
+}
+
+function decode_execute48_match_100(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001029002e
+}
+
+function decode_execute48_match_101(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001019001e
+}
+
+function decode_execute48_match_102(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001029001e
+}
+
+function decode_execute48_match_103(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005019000e
+}
+
+function decode_execute48_match_104(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005019003e
+}
+
+function decode_execute48_match_105(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005019002e
+}
+
+function decode_execute48_match_106(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005029000e
+}
+
+function decode_execute48_match_107(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005029003e
+}
+
+function decode_execute48_match_108(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005029002e
+}
+
+function decode_execute48_match_109(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005019001e
+}
+
+function decode_execute48_match_110(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005029001e
+}
+
+function decode_execute48_match_111(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002019000e
+}
+
+function decode_execute48_match_112(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002019003e
+}
+
+function decode_execute48_match_113(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002019002e
+}
+
+function decode_execute48_match_114(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002029000e
+}
+
+function decode_execute48_match_115(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002029003e
+}
+
+function decode_execute48_match_116(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002029002e
+}
+
+function decode_execute48_match_117(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002019001e
+}
+
+function decode_execute48_match_118(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002029001e
+}
+
+function decode_execute48_match_119(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006019000e
+}
+
+function decode_execute48_match_120(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006019003e
+}
+
+function decode_execute48_match_121(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006019002e
+}
+
+function decode_execute48_match_122(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006029000e
+}
+
+function decode_execute48_match_123(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006029003e
+}
+
+function decode_execute48_match_124(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006029002e
+}
+
+function decode_execute48_match_125(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006019001e
+}
+
+function decode_execute48_match_126(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006029001e
+}
+
+function decode_execute48_match_127(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00007029001e
+}
+
+function decode_execute48_match_128(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00000059000e
+}
+
+function decode_execute48_match_129(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00000059003e
+}
+
+function decode_execute48_match_130(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00000059002e
+}
+
+function decode_execute48_match_131(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00000059001e
+}
+
+function decode_execute48_match_132(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003059000e
+}
+
+function decode_execute48_match_133(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003059003e
+}
+
+function decode_execute48_match_134(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003059002e
+}
+
+function decode_execute48_match_135(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00007059000e
+}
+
+function decode_execute48_match_136(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00007059003e
+}
+
+function decode_execute48_match_137(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00007059002e
+}
+
+function decode_execute48_match_138(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00003059001e
+}
+
+function decode_execute48_match_139(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00007059001e
+}
+
+function decode_execute48_match_140(inst : bits(48)) -> bool = {
+  (inst & 0x00000fff000f) == 0x00000507000e
+}
+
+function decode_execute48_match_141(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001059000e
+}
+
+function decode_execute48_match_142(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001059003e
+}
+
+function decode_execute48_match_143(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001059002e
+}
+
+function decode_execute48_match_144(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005059000e
+}
+
+function decode_execute48_match_145(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005059003e
+}
+
+function decode_execute48_match_146(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005059002e
+}
+
+function decode_execute48_match_147(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00001059001e
+}
+
+function decode_execute48_match_148(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00005059001e
+}
+
+function decode_execute48_match_149(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002059000e
+}
+
+function decode_execute48_match_150(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002059003e
+}
+
+function decode_execute48_match_151(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002059002e
+}
+
+function decode_execute48_match_152(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006059000e
+}
+
+function decode_execute48_match_153(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006059003e
+}
+
+function decode_execute48_match_154(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006059002e
+}
+
+function decode_execute48_match_155(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00002059001e
+}
+
+function decode_execute48_match_156(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f003f) == 0x00006059001e
+}
+
+function decode_execute48_match_157(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00000015000e
+}
+
+function decode_execute48_match_158(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00000035000e
+}
+
+function decode_execute48_match_159(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00002015000e
+}
+
+function decode_execute48_match_160(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00002035000e
+}
+
+function decode_execute48_match_161(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00002055000e
+}
+
+function decode_execute48_match_162(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00000055000e
+}
+
+function decode_execute48_match_163(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00005055000e
+}
+
+function decode_execute48_match_164(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00007055000e
+}
+
+function decode_execute48_match_165(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00004055000e
+}
+
+function decode_execute48_match_166(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00006055000e
+}
+
+function decode_execute48_match_167(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00001055000e
+}
+
+function decode_execute48_match_168(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00003055000e
+}
+
+function decode_execute48_match_169(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00000039000e
+}
+
+function decode_execute48_match_170(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00004039000e
+}
+
+function decode_execute48_match_171(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00003039000e
+}
+
+function decode_execute48_match_172(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00001039000e
+}
+
+function decode_execute48_match_173(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00005039000e
+}
+
+function decode_execute48_match_174(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00002039000e
+}
+
+function decode_execute48_match_175(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00006039000e
+}
+
+function decode_execute48_match_176(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x0000004d000e
+}
+
+function decode_execute48_match_177(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x0000104d000e
+}
+
+function decode_execute48_match_178(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00003015000e
+}
+
+function decode_execute48_match_179(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00003035000e
+}
+
+function decode_execute48_match_180(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00000069000e
+}
+
+function decode_execute48_match_181(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00003069000e
+}
+
+function decode_execute48_match_182(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00002075000e
+}
+
+function decode_execute48_match_183(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00000075000e
+}
+
+function decode_execute48_match_184(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00005075000e
+}
+
+function decode_execute48_match_185(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00007075000e
+}
+
+function decode_execute48_match_186(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00004075000e
+}
+
+function decode_execute48_match_187(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00006075000e
+}
+
+function decode_execute48_match_188(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00001075000e
+}
+
+function decode_execute48_match_189(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00003075000e
+}
+
+function decode_execute48_match_190(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00001069000e
+}
+
+function decode_execute48_match_191(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00001015000e
+}
+
+function decode_execute48_match_192(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00001035000e
+}
+
+function decode_execute48_match_193(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00002069000e
+}
+
+function decode_execute48_match_194(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00004015000e
+}
+
+function decode_execute48_match_195(inst : bits(48)) -> bool = {
+  (inst & 0x0000707f000f) == 0x00004035000e
+}
+
+function decode_execute48_match_196(inst : bits(48)) -> bool = {
+  and_bool_no_flow((inst & 0x0000007f000f) == 0x00000007000e, (inst[27..23] != 0b01010))
+}
+
+function decode_execute48_match_197(inst : bits(48)) -> bool = {
+  (inst & 0x0000007f000f) == 0x0000000d000e
+}
+
+function decode_execute48_match_198(inst : bits(48)) -> bool = {
+  (inst & 0x0000007f000f) == 0x0000001d000e
+}
+
+function decode_execute48_match_199(inst : bits(48)) -> bool = {
+  (inst & 0x0000007f000f) == 0x00000017000e
+}
+
+function decode_execute48(inst : bits(48)) -> unit = {
+  if decode_execute48_match_0(inst) then {
+    // HL.QPUSH | hl.qpush.{h,e,r,he,hr,er,her} SrcL, SrcR, ->{t, u} | {'file': 'opcodes/lx_hl48.opc', 'line': 138}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let e : bits(1) = inst[41];
+    let h : bits(1) = inst[43];
+    let r : bits(1) = inst[42];
+    exec_hl_qpush(regdst, srcl, srcr, e, h, r)
+  }
+  else if decode_execute48_match_1(inst) then {
+    // HL.QMT | hl.qmt.{i,e,s,r,ie,is,ir,es,er,ies,ier} SrcL, SrcR, ->{t, u} | {'file': 'opcodes/lx_hl48.opc', 'line': 136}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let e : bits(1) = inst[41];
+    let i : bits(1) = inst[44];
+    let r : bits(1) = inst[42];
+    let s : bits(1) = inst[43];
+    exec_hl_qmt(regdst, srcl, srcr, e, i, r, s)
+  }
+  else if decode_execute48_match_2(inst) then {
+    // HL.DIV | hl.div SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 41}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_div(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_3(inst) then {
+    // HL.DIVU | hl.divu SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 42}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_divu(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_4(inst) then {
+    // HL.DIVUW | hl.divuw SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 43}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_divuw(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_5(inst) then {
+    // HL.DIVW | hl.divw SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 44}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_divw(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_6(inst) then {
+    // HL.MUL | hl.mul SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 128}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_mul(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_7(inst) then {
+    // HL.MULU | hl.mulu SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 129}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_mulu(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_8(inst) then {
+    // HL.REM | hl.rem SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 139}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_rem(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_9(inst) then {
+    // HL.REMU | hl.remu SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 140}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_remu(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_10(inst) then {
+    // HL.REMUW | hl.remuw SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 141}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_remuw(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_11(inst) then {
+    // HL.REMW | hl.remw SrcL, SrcR, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 142}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_remw(regdst0, regdst1, srcl, srcr)
+  }
+  else if decode_execute48_match_12(inst) then {
+    // HL.PRF | hl.prf{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>] | {'file': 'opcodes/lx_hl48.opc', 'line': 132}
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let model : bits(5) = inst[15..11];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_prf(srcl, srcr, srcrtype, model, shamt)
+  }
+  else if decode_execute48_match_13(inst) then {
+    // HL.QPOP | hl.qpop.{e,r,er} SrcL, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 137}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let e : bits(1) = inst[41];
+    let r : bits(1) = inst[42];
+    exec_hl_qpop(regdst0, regdst1, srcl, srcr, e, r)
+  }
+  else if decode_execute48_match_14(inst) then {
+    // HL.SB.PO | hl.sb.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 144}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sb_po(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_15(inst) then {
+    // HL.SB.PR | hl.sb.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 145}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sb_pr(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_16(inst) then {
+    // HL.SBP | hl.sbp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_hl48.opc', 'line': 150}
+    let srcd : bits(5) = inst[47..43];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sbp(srcd, srcd1, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_17(inst) then {
+    // HL.SD.PO | hl.sd.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 152}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sd_po(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_18(inst) then {
+    // HL.SD.PR | hl.sd.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<3], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 153}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sd_pr(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_19(inst) then {
+    // HL.SD.UPO | hl.sd.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 154}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sd_upo(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_20(inst) then {
+    // HL.SD.UPR | hl.sd.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 155}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sd_upr(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_21(inst) then {
+    // HL.SDP | hl.sdp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<3] | {'file': 'opcodes/lx_hl48.opc', 'line': 164}
+    let srcd : bits(5) = inst[47..43];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sdp(srcd, srcd1, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_22(inst) then {
+    // HL.SDP.U | hl.sdp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_hl48.opc', 'line': 165}
+    let srcd : bits(5) = inst[47..43];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sdp_u(srcd, srcd1, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_23(inst) then {
+    // HL.SH.PO | hl.sh.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 176}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sh_po(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_24(inst) then {
+    // HL.SH.PR | hl.sh.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<1], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 177}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sh_pr(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_25(inst) then {
+    // HL.SH.UPO | hl.sh.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 178}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sh_upo(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_26(inst) then {
+    // HL.SH.UPR | hl.sh.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 179}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sh_upr(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_27(inst) then {
+    // HL.SHP | hl.shp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<1] | {'file': 'opcodes/lx_hl48.opc', 'line': 188}
+    let srcd : bits(5) = inst[47..43];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_shp(srcd, srcd1, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_28(inst) then {
+    // HL.SHP.U | hl.shp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_hl48.opc', 'line': 189}
+    let srcd : bits(5) = inst[47..43];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_shp_u(srcd, srcd1, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_29(inst) then {
+    // HL.SW.PO | hl.sw.po SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 195}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sw_po(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_30(inst) then {
+    // HL.SW.PR | hl.sw.pr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}><<2], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 196}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sw_pr(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_31(inst) then {
+    // HL.SW.UPO | hl.sw.upo SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 197}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sw_upo(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_32(inst) then {
+    // HL.SW.UPR | hl.sw.upr SrcD, [SrcL, SrcR<{.sw,.uw,.neg}>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 198}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_sw_upr(regdst, srcd, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_33(inst) then {
+    // HL.SWP | hl.swp SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}><<2] | {'file': 'opcodes/lx_hl48.opc', 'line': 207}
+    let srcd : bits(5) = inst[47..43];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_swp(srcd, srcd1, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_34(inst) then {
+    // HL.SWP.U | hl.swp.u SrcD, SrcD1, [SrcL, SrcR<{.sw,.uw,.neg}>] | {'file': 'opcodes/lx_hl48.opc', 'line': 208}
+    let srcd : bits(5) = inst[47..43];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    exec_hl_swp_u(srcd, srcd1, srcl, srcr, srcrtype)
+  }
+  else if decode_execute48_match_35(inst) then {
+    // HL.CASB | hl.casb<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 27}
+    let regdst : bits(5) = inst[27..23];
+    let srcd : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let aq : bits(1) = inst[42];
+    let far : bits(1) = inst[43];
+    let rl : bits(1) = inst[41];
+    exec_hl_casb(regdst, srcl, srcr, srcd, aq, far, rl)
+  }
+  else if decode_execute48_match_36(inst) then {
+    // HL.CASD | hl.casd<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 28}
+    let regdst : bits(5) = inst[27..23];
+    let srcd : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let aq : bits(1) = inst[42];
+    let far : bits(1) = inst[43];
+    let rl : bits(1) = inst[41];
+    exec_hl_casd(regdst, srcl, srcr, srcd, aq, far, rl)
+  }
+  else if decode_execute48_match_37(inst) then {
+    // HL.CASH | hl.cash<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 29}
+    let regdst : bits(5) = inst[27..23];
+    let srcd : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let aq : bits(1) = inst[42];
+    let far : bits(1) = inst[43];
+    let rl : bits(1) = inst[41];
+    exec_hl_cash(regdst, srcl, srcr, srcd, aq, far, rl)
+  }
+  else if decode_execute48_match_38(inst) then {
+    // HL.CASW | hl.casw<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, SrcD, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 30}
+    let regdst : bits(5) = inst[27..23];
+    let srcd : bits(5) = inst[10..6];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let aq : bits(1) = inst[42];
+    let far : bits(1) = inst[43];
+    let rl : bits(1) = inst[41];
+    exec_hl_casw(regdst, srcl, srcr, srcd, aq, far, rl)
+  }
+  else if decode_execute48_match_39(inst) then {
+    // HL.MADD | hl.madd SrcL, SrcR, SrcD, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 124}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_madd(regdst0, regdst1, srcd, srcl, srcr)
+  }
+  else if decode_execute48_match_40(inst) then {
+    // HL.MADDW | hl.maddw SrcL, SrcR, SrcD, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 125}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[47..43];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    exec_hl_maddw(regdst0, regdst1, srcd, srcl, srcr)
+  }
+  else if decode_execute48_match_41(inst) then {
+    // HL.BFI | hl.bfi SrcL, SrcR, M, N, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 16}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let immr : bits(6) = inst[9..4];
+    let imms : bits(6) = inst[15..10];
+    exec_hl_bfi(regdst, srcl, srcr, immr, imms)
+  }
+  else if decode_execute48_match_42(inst) then {
+    // HL.CCAT | hl.ccat SrcL, SrcR, shamt, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 31}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let shamt : bits(7) = inst[47..41];
+    exec_hl_ccat(regdst0, regdst1, srcl, srcr, shamt)
+  }
+  else if decode_execute48_match_43(inst) then {
+    // HL.CCATW | hl.ccatw SrcL, SrcR, shamt, ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 32}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let shamt : bits(7) = inst[47..41];
+    exec_hl_ccatw(regdst0, regdst1, srcl, srcr, shamt)
+  }
+  else if decode_execute48_match_44(inst) then {
+    // HL.LB.PO | hl.lb.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 46}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lb_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_45(inst) then {
+    // HL.LB.PR | hl.lb.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 47}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lb_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_46(inst) then {
+    // HL.LBP | hl.lbp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 52}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lbp(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_47(inst) then {
+    // HL.LBU.PO | hl.lbu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 54}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lbu_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_48(inst) then {
+    // HL.LBU.PR | hl.lbu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 55}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lbu_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_49(inst) then {
+    // HL.LBUP | hl.lbup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 60}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lbup(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_50(inst) then {
+    // HL.LD.PO | hl.ld.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 62}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_ld_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_51(inst) then {
+    // HL.LD.PR | hl.ld.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 63}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_ld_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_52(inst) then {
+    // HL.LDP | hl.ldp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 72}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_ldp(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_53(inst) then {
+    // HL.LH.PO | hl.lh.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 74}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lh_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_54(inst) then {
+    // HL.LH.PR | hl.lh.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 75}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lh_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_55(inst) then {
+    // HL.LHP | hl.lhp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 84}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lhp(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_56(inst) then {
+    // HL.LHU.PO | hl.lhu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 86}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lhu_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_57(inst) then {
+    // HL.LHU.PR | hl.lhu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 87}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lhu_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_58(inst) then {
+    // HL.LHUP | hl.lhup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 96}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lhup(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_59(inst) then {
+    // HL.LW.PO | hl.lw.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 101}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lw_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_60(inst) then {
+    // HL.LW.PR | hl.lw.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 102}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lw_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_61(inst) then {
+    // HL.LWP | hl.lwp [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 111}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lwp(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_62(inst) then {
+    // HL.LWU.PO | hl.lwu.po [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 113}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lwu_po(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_63(inst) then {
+    // HL.LWU.PR | hl.lwu.pr [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 114}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lwu_pr(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_64(inst) then {
+    // HL.LWUP | hl.lwup [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 123}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_lwup(regdst0, regdst1, srcl, srcr, srcrtype, shamt)
+  }
+  else if decode_execute48_match_65(inst) then {
+    // HL.PRF.A | hl.prf.a{.l1,.l2,.l3} [SrcL, SrcR<{.sw,.uw,.neg}><<<shamt>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 133}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let srcrtype : bits(2) = inst[42..41];
+    let model : bits(5) = inst[15..11];
+    let shamt : bits(5) = inst[47..43];
+    exec_hl_prf_a(regdst, srcl, srcr, srcrtype, model, shamt)
+  }
+  else if decode_execute48_match_66(inst) then {
+    // HL.PRFI.U | hl.prfi.u{.l1,.l2,.l3} [SrcL, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 134}
+    let srcl : bits(5) = inst[35..31];
+    let model : bits(5) = inst[15..11];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_prfi_u(srcl, model, simm17)
+  }
+  else if decode_execute48_match_67(inst) then {
+    // HL.BSTART.FP | HL.BSTART.FP COND, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 18}
+    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
+    decoded_block_target_pc_shadow = decode_block_target30(simm);
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_cond();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_fp()
+  }
+  else if decode_execute48_match_68(inst) then {
+    // HL.BSTART.FP | HL.BSTART.FP FALL<, fixup_label> | {'file': 'opcodes/lx_hl48.opc', 'line': 19}
+    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
+    decoded_block_target_pc_shadow = decode_block_target30(simm);
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_fp()
+  }
+  else if decode_execute48_match_69(inst) then {
+    // HL.BSTART.FP | HL.BSTART.FP CALL, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 20}
+    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
+    decoded_block_target_pc_shadow = decode_block_target30(simm);
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_call();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_fp()
+  }
+  else if decode_execute48_match_70(inst) then {
+    // HL.BSTART.FP | HL.BSTART.FP DIRECT, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 21}
+    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
+    decoded_block_target_pc_shadow = decode_block_target30(simm);
+    decoded_block_type_shadow = 0b0010;
+    decoded_block_xfer_kind_shadow = block_xfer_direct();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_fp()
+  }
+  else if decode_execute48_match_71(inst) then {
+    // HL.BSTART.STD | HL.BSTART.STD CALL, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 22}
+    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
+    decoded_block_target_pc_shadow = decode_block_target30(simm);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_call();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_std()
+  }
+  else if decode_execute48_match_72(inst) then {
+    // HL.BSTART.STD | HL.BSTART.STD FALL<, fixup_label> | {'file': 'opcodes/lx_hl48.opc', 'line': 23}
+    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
+    decoded_block_target_pc_shadow = decode_block_target30(simm);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_std()
+  }
+  else if decode_execute48_match_73(inst) then {
+    // HL.BSTART.STD | HL.BSTART.STD COND, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 24}
+    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
+    decoded_block_target_pc_shadow = decode_block_target30(simm);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_cond();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_std()
+  }
+  else if decode_execute48_match_74(inst) then {
+    // HL.BSTART.STD | HL.BSTART.STD DIRECT, <label> | {'file': 'opcodes/lx_hl48.opc', 'line': 25}
+    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
+    decoded_block_target_pc_shadow = decode_block_target30(simm);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_direct();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_std()
+  }
+  else if decode_execute48_match_75(inst) then {
+    // HL.BSTART.SYS | HL.BSTART.SYS FALL<, fixup_label> | {'file': 'opcodes/lx_hl48.opc', 'line': 26}
+    let simm : bits(30) = inst[15..4] @ inst[47..31] @ 0b0;
+    decoded_block_target_pc_shadow = decode_block_target30(simm);
+    decoded_block_type_shadow = 0b0001;
+    decoded_block_xfer_kind_shadow = block_xfer_fall();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_sys()
+  }
+  else if decode_execute48_match_76(inst) then {
+    // HL.SSRGET | hl.ssrget SSR_ID, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 190}
+    let regdst : bits(5) = inst[27..23];
+    let ssr_id : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_ssrget(regdst, ssr_id)
+  }
+  else if decode_execute48_match_77(inst) then {
+    // HL.SSRSET | hl.ssrset SrcL, SSR_ID | {'file': 'opcodes/lx_hl48.opc', 'line': 191}
+    let ssr_id : bits(24) = inst[15..4] @ inst[47..36];
+    let srcl : bits(5) = inst[35..31];
+    exec_hl_ssrset(srcl, ssr_id)
+  }
+  else if decode_execute48_match_78(inst) then {
+    // HL.BSTART CALL | HL.BSTART.CALL <br_label>, <rt_label>, ->ra | {'file': 'opcodes/lx_hl48.opc', 'line': 17}
+    let simm25 : bits(25) = inst[31..7];
+    let uimm5 : bits(5) = inst[42..38];
+    decoded_block_target_pc_shadow = decode_block_target25(simm25);
+    decoded_block_type_shadow = 0b0000;
+    decoded_block_xfer_kind_shadow = block_xfer_call();
+    decoded_block_contract_kind_shadow = 0b0000;
+    exec_hl_bstart_call(uimm5)
+  }
+  else if decode_execute48_match_79(inst) then {
+    // HL.LBI | hl.lbi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 48}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lbi(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_80(inst) then {
+    // HL.LBI.PO | hl.lbi.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 49}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lbi_po(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_81(inst) then {
+    // HL.LBI.PR | hl.lbi.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 50}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lbi_pr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_82(inst) then {
+    // HL.LBIP | hl.lbip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 51}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lbip(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_83(inst) then {
+    // HL.LBUI | hl.lbui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 56}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lbui(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_84(inst) then {
+    // HL.LBUI.PO | hl.lbui.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 57}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lbui_po(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_85(inst) then {
+    // HL.LBUI.PR | hl.lbui.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 58}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lbui_pr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_86(inst) then {
+    // HL.LBUIP | hl.lbuip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 59}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lbuip(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_87(inst) then {
+    // HL.LDI | hl.ldi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 64}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_ldi(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_88(inst) then {
+    // HL.LDI.PO | hl.ldi.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 65}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_ldi_po(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_89(inst) then {
+    // HL.LDI.PR | hl.ldi.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 66}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_ldi_pr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_90(inst) then {
+    // HL.LDI.U | hl.ldi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 67}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_ldi_u(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_91(inst) then {
+    // HL.LDI.UPO | hl.ldi.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 68}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_ldi_upo(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_92(inst) then {
+    // HL.LDI.UPR | hl.ldi.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 69}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_ldi_upr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_93(inst) then {
+    // HL.LDIP | hl.ldip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 70}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_ldip(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_94(inst) then {
+    // HL.LDIP.U | hl.ldip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 71}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_ldip_u(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_95(inst) then {
+    // HL.LHI | hl.lhi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 76}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lhi(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_96(inst) then {
+    // HL.LHI.PO | hl.lhi.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 77}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhi_po(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_97(inst) then {
+    // HL.LHI.PR | hl.lhi.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 78}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhi_pr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_98(inst) then {
+    // HL.LHI.U | hl.lhi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 79}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lhi_u(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_99(inst) then {
+    // HL.LHI.UPO | hl.lhi.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 80}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhi_upo(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_100(inst) then {
+    // HL.LHI.UPR | hl.lhi.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 81}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhi_upr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_101(inst) then {
+    // HL.LHIP | hl.lhip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 82}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhip(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_102(inst) then {
+    // HL.LHIP.U | hl.lhip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 83}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhip_u(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_103(inst) then {
+    // HL.LHUI | hl.lhui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 88}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lhui(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_104(inst) then {
+    // HL.LHUI.PO | hl.lhui.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 89}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhui_po(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_105(inst) then {
+    // HL.LHUI.PR | hl.lhui.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 90}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhui_pr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_106(inst) then {
+    // HL.LHUI.U | hl.lhui.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 91}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lhui_u(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_107(inst) then {
+    // HL.LHUI.UPO | hl.lhui.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 92}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhui_upo(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_108(inst) then {
+    // HL.LHUI.UPR | hl.lhui.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 93}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhui_upr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_109(inst) then {
+    // HL.LHUIP | hl.lhuip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 94}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhuip(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_110(inst) then {
+    // HL.LHUIP.U | hl.lhuip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 95}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lhuip_u(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_111(inst) then {
+    // HL.LWI | hl.lwi [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 103}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lwi(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_112(inst) then {
+    // HL.LWI.PO | hl.lwi.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 104}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwi_po(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_113(inst) then {
+    // HL.LWI.PR | hl.lwi.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 105}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwi_pr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_114(inst) then {
+    // HL.LWI.U | hl.lwi.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 106}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lwi_u(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_115(inst) then {
+    // HL.LWI.UPO | hl.lwi.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 107}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwi_upo(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_116(inst) then {
+    // HL.LWI.UPR | hl.lwi.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 108}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwi_upr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_117(inst) then {
+    // HL.LWIP | hl.lwip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 109}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwip(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_118(inst) then {
+    // HL.LWIP.U | hl.lwip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 110}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwip_u(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_119(inst) then {
+    // HL.LWUI | hl.lwui [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 115}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lwui(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_120(inst) then {
+    // HL.LWUI.PO | hl.lwui.po [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 116}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwui_po(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_121(inst) then {
+    // HL.LWUI.PR | hl.lwui.pr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 117}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwui_pr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_122(inst) then {
+    // HL.LWUI.U | hl.lwui.u [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 118}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm22 : bits(22) = inst[15..6] @ inst[47..36];
+    exec_hl_lwui_u(regdst, srcl, simm22)
+  }
+  else if decode_execute48_match_123(inst) then {
+    // HL.LWUI.UPO | hl.lwui.upo [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 119}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwui_upo(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_124(inst) then {
+    // HL.LWUI.UPR | hl.lwui.upr [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 120}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwui_upr(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_125(inst) then {
+    // HL.LWUIP | hl.lwuip [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 121}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwuip(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_126(inst) then {
+    // HL.LWUIP.U | hl.lwuip.u [SrcL, simm], ->Dst0, Dst1 | {'file': 'opcodes/lx_hl48.opc', 'line': 122}
+    let regdst0 : bits(5) = inst[27..23];
+    let regdst1 : bits(5) = inst[15..11];
+    let srcl : bits(5) = inst[35..31];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_lwuip_u(regdst0, regdst1, srcl, simm17)
+  }
+  else if decode_execute48_match_127(inst) then {
+    // HL.PRFI.UA | hl.prfi.ua{.l1,.l2,.l3} [SrcL, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 135}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let model : bits(5) = inst[15..11];
+    let simm17 : bits(17) = inst[10..6] @ inst[47..36];
+    exec_hl_prfi_ua(regdst, srcl, model, simm17)
+  }
+  else if decode_execute48_match_128(inst) then {
+    // HL.SBI | hl.sbi SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 146}
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_sbi(srcd, srcr, simm22)
+  }
+  else if decode_execute48_match_129(inst) then {
+    // HL.SBI.PO | hl.sbi.po SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 147}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_sbi_po(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_130(inst) then {
+    // HL.SBI.PR | hl.sbi.pr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 148}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_sbi_pr(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_131(inst) then {
+    // HL.SBIP | hl.sbip SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 149}
+    let srcd : bits(5) = inst[35..31];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
+    exec_hl_sbip(srcd, srcd1, srcr, simm17)
+  }
+  else if decode_execute48_match_132(inst) then {
+    // HL.SDI | hl.sdi SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 156}
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_sdi(srcd, srcr, simm22)
+  }
+  else if decode_execute48_match_133(inst) then {
+    // HL.SDI.PO | hl.sdi.po SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 157}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_sdi_po(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_134(inst) then {
+    // HL.SDI.PR | hl.sdi.pr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 158}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_sdi_pr(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_135(inst) then {
+    // HL.SDI.U | hl.sdi.u SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 159}
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_sdi_u(srcd, srcr, simm22)
+  }
+  else if decode_execute48_match_136(inst) then {
+    // HL.SDI.UPO | hl.sdi.upo SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 160}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_sdi_upo(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_137(inst) then {
+    // HL.SDI.UPR | hl.sdi.upr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 161}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_sdi_upr(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_138(inst) then {
+    // HL.SDIP | hl.sdip SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 162}
+    let srcd : bits(5) = inst[35..31];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
+    exec_hl_sdip(srcd, srcd1, srcr, simm17)
+  }
+  else if decode_execute48_match_139(inst) then {
+    // HL.SDIP.U | hl.sdip.u SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 163}
+    let srcd : bits(5) = inst[35..31];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
+    exec_hl_sdip_u(srcd, srcd1, srcr, simm17)
+  }
+  else if decode_execute48_match_140(inst) then {
+    // HL.SETRET | hl.setret imm, ->Ra | {'file': 'opcodes/lx_hl48.opc', 'line': 174}
+    let imm32 : bits(32) = inst[15..4] @ inst[47..28];
+    exec_hl_setret(imm32)
+  }
+  else if decode_execute48_match_141(inst) then {
+    // HL.SHI | hl.shi SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 180}
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_shi(srcd, srcr, simm22)
+  }
+  else if decode_execute48_match_142(inst) then {
+    // HL.SHI.PO | hl.shi.po SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 181}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_shi_po(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_143(inst) then {
+    // HL.SHI.PR | hl.shi.pr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 182}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_shi_pr(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_144(inst) then {
+    // HL.SHI.U | hl.shi.u SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 183}
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_shi_u(srcd, srcr, simm22)
+  }
+  else if decode_execute48_match_145(inst) then {
+    // HL.SHI.UPO | hl.shi.upo SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 184}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_shi_upo(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_146(inst) then {
+    // HL.SHI.UPR | hl.shi.upr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 185}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_shi_upr(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_147(inst) then {
+    // HL.SHIP | hl.ship SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 186}
+    let srcd : bits(5) = inst[35..31];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
+    exec_hl_ship(srcd, srcd1, srcr, simm17)
+  }
+  else if decode_execute48_match_148(inst) then {
+    // HL.SHIP.U | hl.ship.u SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 187}
+    let srcd : bits(5) = inst[35..31];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
+    exec_hl_ship_u(srcd, srcd1, srcr, simm17)
+  }
+  else if decode_execute48_match_149(inst) then {
+    // HL.SWI | hl.swi SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 199}
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_swi(srcd, srcr, simm22)
+  }
+  else if decode_execute48_match_150(inst) then {
+    // HL.SWI.PO | hl.swi.po SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 200}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_swi_po(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_151(inst) then {
+    // HL.SWI.PR | hl.swi.pr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 201}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_swi_pr(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_152(inst) then {
+    // HL.SWI.U | hl.swi.u SrcD, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 202}
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm22 : bits(22) = inst[15..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_swi_u(srcd, srcr, simm22)
+  }
+  else if decode_execute48_match_153(inst) then {
+    // HL.SWI.UPO | hl.swi.upo SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 203}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_swi_upo(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_154(inst) then {
+    // HL.SWI.UPR | hl.swi.upr SrcD, [SrcR, simm], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 204}
+    let regdst : bits(5) = inst[15..11];
+    let srcd : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[10..6] @ inst[27..23] @ inst[47..41];
+    exec_hl_swi_upr(regdst, srcd, srcr, simm17)
+  }
+  else if decode_execute48_match_155(inst) then {
+    // HL.SWIP | hl.swip SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 205}
+    let srcd : bits(5) = inst[35..31];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
+    exec_hl_swip(srcd, srcd1, srcr, simm17)
+  }
+  else if decode_execute48_match_156(inst) then {
+    // HL.SWIP.U | hl.swip.u SrcD, SrcD1, [SrcR, simm] | {'file': 'opcodes/lx_hl48.opc', 'line': 206}
+    let srcd : bits(5) = inst[35..31];
+    let srcd1 : bits(5) = inst[10..6];
+    let srcr : bits(5) = inst[40..36];
+    let simm17 : bits(17) = inst[15..11] @ inst[27..23] @ inst[47..41];
+    exec_hl_swip_u(srcd, srcd1, srcr, simm17)
+  }
+  else if decode_execute48_match_157(inst) then {
+    // HL.ADDI | hl.addi SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 11}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_addi(regdst, srcl, uimm24)
+  }
+  else if decode_execute48_match_158(inst) then {
+    // HL.ADDIW | hl.addiw SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 12}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_addiw(regdst, srcl, uimm24)
+  }
+  else if decode_execute48_match_159(inst) then {
+    // HL.ANDI | hl.andi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 14}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_andi(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_160(inst) then {
+    // HL.ANDIW | hl.andiw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 15}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_andiw(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_161(inst) then {
+    // HL.CMP.ANDI | hl.cmp.andi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 33}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_cmp_andi(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_162(inst) then {
+    // HL.CMP.EQI | hl.cmp.eqi SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 34}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_cmp_eqi(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_163(inst) then {
+    // HL.CMP.GEI | hl.cmp.gei SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 35}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_cmp_gei(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_164(inst) then {
+    // HL.CMP.GEUI | hl.cmp.geui SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 36}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_cmp_geui(regdst, srcl, uimm24)
+  }
+  else if decode_execute48_match_165(inst) then {
+    // HL.CMP.LTI | hl.cmp.lti SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 37}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_cmp_lti(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_166(inst) then {
+    // HL.CMP.LTUI | hl.cmp.ltui SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 38}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_cmp_ltui(regdst, srcl, uimm24)
+  }
+  else if decode_execute48_match_167(inst) then {
+    // HL.CMP.NEI | hl.cmp.nei SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 39}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_cmp_nei(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_168(inst) then {
+    // HL.CMP.ORI | hl.cmp.ori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 40}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_cmp_ori(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_169(inst) then {
+    // HL.LB.PCR | hl.lb.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 45}
+    let regdst : bits(5) = inst[27..23];
+    let simm : bits(29) = inst[15..4] @ inst[47..31];
+    exec_hl_lb_pcr(regdst, simm)
+  }
+  else if decode_execute48_match_170(inst) then {
+    // HL.LBU.PCR | hl.lbu.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 53}
+    let regdst : bits(5) = inst[27..23];
+    let simm : bits(29) = inst[15..4] @ inst[47..31];
+    exec_hl_lbu_pcr(regdst, simm)
+  }
+  else if decode_execute48_match_171(inst) then {
+    // HL.LD.PCR | hl.ld.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 61}
+    let regdst : bits(5) = inst[27..23];
+    let simm : bits(29) = inst[15..4] @ inst[47..31];
+    exec_hl_ld_pcr(regdst, simm)
+  }
+  else if decode_execute48_match_172(inst) then {
+    // HL.LH.PCR | hl.lh.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 73}
+    let regdst : bits(5) = inst[27..23];
+    let simm : bits(29) = inst[15..4] @ inst[47..31];
+    exec_hl_lh_pcr(regdst, simm)
+  }
+  else if decode_execute48_match_173(inst) then {
+    // HL.LHU.PCR | hl.lhu.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 85}
+    let regdst : bits(5) = inst[27..23];
+    let simm : bits(29) = inst[15..4] @ inst[47..31];
+    exec_hl_lhu_pcr(regdst, simm)
+  }
+  else if decode_execute48_match_174(inst) then {
+    // HL.LW.PCR | hl.lw.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 100}
+    let regdst : bits(5) = inst[27..23];
+    let simm : bits(29) = inst[15..4] @ inst[47..31];
+    exec_hl_lw_pcr(regdst, simm)
+  }
+  else if decode_execute48_match_175(inst) then {
+    // HL.LWU.PCR | hl.lwu.pcr [<symbol>], ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 112}
+    let regdst : bits(5) = inst[27..23];
+    let simm : bits(29) = inst[15..4] @ inst[47..31];
+    exec_hl_lwu_pcr(regdst, simm)
+  }
+  else if decode_execute48_match_176(inst) then {
+    // HL.MIADD | hl.miadd SrcL, SrcR, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 126}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let uimm19 : bits(19) = inst[15..4] @ inst[47..41];
+    exec_hl_miadd(regdst, srcl, srcr, uimm19)
+  }
+  else if decode_execute48_match_177(inst) then {
+    // HL.MISUB | hl.misub SrcL, SrcR, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 127}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let srcr : bits(5) = inst[40..36];
+    let uimm19 : bits(19) = inst[15..4] @ inst[47..41];
+    exec_hl_misub(regdst, srcl, srcr, uimm19)
+  }
+  else if decode_execute48_match_178(inst) then {
+    // HL.ORI | hl.ori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 130}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_ori(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_179(inst) then {
+    // HL.ORIW | hl.oriw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 131}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_oriw(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_180(inst) then {
+    // HL.SB.PCR | hl.sb.pcr SrcL, [<symbol>] | {'file': 'opcodes/lx_hl48.opc', 'line': 143}
+    let srcl : bits(5) = inst[35..31];
+    let simm : bits(29) = inst[15..4] @ inst[27..23] @ inst[47..36];
+    exec_hl_sb_pcr(srcl, simm)
+  }
+  else if decode_execute48_match_181(inst) then {
+    // HL.SD.PCR | hl.sd.pcr SrcL, [<symbol>] | {'file': 'opcodes/lx_hl48.opc', 'line': 151}
+    let srcl : bits(5) = inst[35..31];
+    let simm : bits(29) = inst[15..4] @ inst[27..23] @ inst[47..36];
+    exec_hl_sd_pcr(srcl, simm)
+  }
+  else if decode_execute48_match_182(inst) then {
+    // HL.SETC.ANDI | hl.setc.andi SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 166}
+    let srcl : bits(5) = inst[35..31];
+    let shamt : bits(5) = inst[27..23];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_setc_andi(srcl, shamt, simm24)
+  }
+  else if decode_execute48_match_183(inst) then {
+    // HL.SETC.EQI | hl.setc.eqi SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 167}
+    let srcl : bits(5) = inst[35..31];
+    let shamt : bits(5) = inst[27..23];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_setc_eqi(srcl, shamt, simm24)
+  }
+  else if decode_execute48_match_184(inst) then {
+    // HL.SETC.GEI | hl.setc.gei SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 168}
+    let srcl : bits(5) = inst[35..31];
+    let shamt : bits(5) = inst[27..23];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_setc_gei(srcl, shamt, simm24)
+  }
+  else if decode_execute48_match_185(inst) then {
+    // HL.SETC.GEUI | hl.setc.geui SrcL, uimm | {'file': 'opcodes/lx_hl48.opc', 'line': 169}
+    let srcl : bits(5) = inst[35..31];
+    let shamt : bits(5) = inst[27..23];
+    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_setc_geui(srcl, shamt, uimm24)
+  }
+  else if decode_execute48_match_186(inst) then {
+    // HL.SETC.LTI | hl.setc.lti SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 170}
+    let srcl : bits(5) = inst[35..31];
+    let shamt : bits(5) = inst[27..23];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_setc_lti(srcl, shamt, simm24)
+  }
+  else if decode_execute48_match_187(inst) then {
+    // HL.SETC.LTUI | hl.setc.ltui SrcL, uimm | {'file': 'opcodes/lx_hl48.opc', 'line': 171}
+    let srcl : bits(5) = inst[35..31];
+    let shamt : bits(5) = inst[27..23];
+    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_setc_ltui(srcl, shamt, uimm24)
+  }
+  else if decode_execute48_match_188(inst) then {
+    // HL.SETC.NEI | hl.setc.nei SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 172}
+    let srcl : bits(5) = inst[35..31];
+    let shamt : bits(5) = inst[27..23];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_setc_nei(srcl, shamt, simm24)
+  }
+  else if decode_execute48_match_189(inst) then {
+    // HL.SETC.ORI | hl.setc.ori SrcL, simm | {'file': 'opcodes/lx_hl48.opc', 'line': 173}
+    let srcl : bits(5) = inst[35..31];
+    let shamt : bits(5) = inst[27..23];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_setc_ori(srcl, shamt, simm24)
+  }
+  else if decode_execute48_match_190(inst) then {
+    // HL.SH.PCR | hl.sh.pcr SrcL, [<symbol>] | {'file': 'opcodes/lx_hl48.opc', 'line': 175}
+    let srcl : bits(5) = inst[35..31];
+    let simm : bits(29) = inst[15..4] @ inst[27..23] @ inst[47..36];
+    exec_hl_sh_pcr(srcl, simm)
+  }
+  else if decode_execute48_match_191(inst) then {
+    // HL.SUBI | hl.subi SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 192}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_subi(regdst, srcl, uimm24)
+  }
+  else if decode_execute48_match_192(inst) then {
+    // HL.SUBIW | hl.subiw SrcL, uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 193}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let uimm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_subiw(regdst, srcl, uimm24)
+  }
+  else if decode_execute48_match_193(inst) then {
+    // HL.SW.PCR | hl.sw.pcr SrcL, [<symbol>] | {'file': 'opcodes/lx_hl48.opc', 'line': 194}
+    let srcl : bits(5) = inst[35..31];
+    let simm : bits(29) = inst[15..4] @ inst[27..23] @ inst[47..36];
+    exec_hl_sw_pcr(srcl, simm)
+  }
+  else if decode_execute48_match_194(inst) then {
+    // HL.XORI | hl.xori SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 209}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_xori(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_195(inst) then {
+    // HL.XORIW | hl.xoriw SrcL, simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 210}
+    let regdst : bits(5) = inst[27..23];
+    let srcl : bits(5) = inst[35..31];
+    let simm24 : bits(24) = inst[15..4] @ inst[47..36];
+    exec_hl_xoriw(regdst, srcl, simm24)
+  }
+  else if decode_execute48_match_196(inst) then {
+    // HL.ADDTPC | hl.addtpc imm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 13}
+    let regdst : bits(5) = inst[27..23];
+    let imm32 : bits(32) = inst[15..4] @ inst[47..28];
+    exec_hl_addtpc(regdst, imm32)
+  }
+  else if decode_execute48_match_197(inst) then {
+    // HL.LIS | hl.lis simm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 97}
+    let regdst : bits(5) = inst[27..23];
+    let simm32 : bits(32) = inst[15..4] @ inst[47..28];
+    exec_hl_lis(regdst, simm32)
+  }
+  else if decode_execute48_match_198(inst) then {
+    // HL.LIU | hl.liu uimm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 98}
+    let regdst : bits(5) = inst[27..23];
+    let uimm32 : bits(32) = inst[15..4] @ inst[47..28];
+    exec_hl_liu(regdst, uimm32)
+  }
+  else if decode_execute48_match_199(inst) then {
+    // HL.LUI | hl.lui imm, ->{t, u, Rd} | {'file': 'opcodes/lx_hl48.opc', 'line': 99}
+    let regdst : bits(5) = inst[27..23];
+    let imm : bits(32) = inst[15..4] @ inst[47..28];
+    exec_hl_lui(regdst, imm)
+  }
+  else {
+    trap_illegal_inst(read_pc_or_tpc())
+  }
+}
+
+function decode_execute64_match_0(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000007b)
+}
+
+function decode_execute64_match_1(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000707b)
+}
+
+function decode_execute64_match_2(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000307b)
+}
+
+function decode_execute64_match_3(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000207b)
+}
+
+function decode_execute64_match_4(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000107b)
+}
+
+function decode_execute64_match_5(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000207d)
+}
+
+function decode_execute64_match_6(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000000d)
+}
+
+function decode_execute64_match_7(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000100d)
+}
+
+function decode_execute64_match_8(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000400d)
+}
+
+function decode_execute64_match_9(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000107f, (part1 & 0xfff0707f) == 0x0000200d)
+}
+
+function decode_execute64_match_10(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000107f, (part1 & 0xfff0707f) == 0x0000300d)
+}
+
+function decode_execute64_match_11(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000107f, (part1 & 0xfff0707f) == 0x0000000d)
+}
+
+function decode_execute64_match_12(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000107f, (part1 & 0xfff0707f) == 0x0000100d)
+}
+
+function decode_execute64_match_13(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000200d)
+}
+
+function decode_execute64_match_14(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfff0707f) == 0x0000300d)
+}
+
+function decode_execute64_match_15(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000307f, (part1 & 0xfc007fff) == 0x0000000b)
+}
+
+function decode_execute64_match_16(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000307f, (part1 & 0xfc007fff) == 0x0000100b)
+}
+
+function decode_execute64_match_17(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000307f, (part1 & 0xfc007fff) == 0x0000400b)
+}
+
+function decode_execute64_match_18(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000307f, (part1 & 0xfc007fff) == 0x0000500b)
+}
+
+function decode_execute64_match_19(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000307f, (part1 & 0xfc007fff) == 0x0000200b)
+}
+
+function decode_execute64_match_20(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000307f, (part1 & 0xfc007fff) == 0x0000300b)
+}
+
+function decode_execute64_match_21(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000107f, (part1 & 0xfc007fff) == 0x0000000b)
+}
+
+function decode_execute64_match_22(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000107f, (part1 & 0xfc007fff) == 0x0000100b)
+}
+
+function decode_execute64_match_23(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000107f, (part1 & 0xfc007fff) == 0x0000400b)
+}
+
+function decode_execute64_match_24(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000107f, (part1 & 0xfc007fff) == 0x0000500b)
+}
+
+function decode_execute64_match_25(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000107f, (part1 & 0xfc007fff) == 0x0000200b)
+}
+
+function decode_execute64_match_26(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xf8007fff) == 0x0000107f, (part1 & 0xfc007fff) == 0x0000300b)
+}
+
+function decode_execute64_match_27(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfc00707f) == 0x00007015)
+}
+
+function decode_execute64_match_28(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfc00707f) == 0x00006015)
+}
+
+function decode_execute64_match_29(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0xfc00707f) == 0x00005015)
+}
+
+function decode_execute64_match_30(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00002045)
+}
+
+function decode_execute64_match_31(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00000045)
+}
+
+function decode_execute64_match_32(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00005045)
+}
+
+function decode_execute64_match_33(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00007045)
+}
+
+function decode_execute64_match_34(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00004045)
+}
+
+function decode_execute64_match_35(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00006045)
+}
+
+function decode_execute64_match_36(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00001045)
+}
+
+function decode_execute64_match_37(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00003045)
+}
+
+function decode_execute64_match_38(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00000057)
+}
+
+function decode_execute64_match_39(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000004b)
+}
+
+function decode_execute64_match_40(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000006b)
+}
+
+function decode_execute64_match_41(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000106b)
+}
+
+function decode_execute64_match_42(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000304b)
+}
+
+function decode_execute64_match_43(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000005b)
+}
+
+function decode_execute64_match_44(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000405b)
+}
+
+function decode_execute64_match_45(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000305b)
+}
+
+function decode_execute64_match_46(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000705b)
+}
+
+function decode_execute64_match_47(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000205b)
+}
+
+function decode_execute64_match_48(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000605b)
+}
+
+function decode_execute64_match_49(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000107f, (part1 & 0xfe00707f) == 0x0000205b)
+}
+
+function decode_execute64_match_50(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000107f, (part1 & 0xfe00707f) == 0x0000305b)
+}
+
+function decode_execute64_match_51(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000204b)
+}
+
+function decode_execute64_match_52(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000105b)
+}
+
+function decode_execute64_match_53(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000505b)
+}
+
+function decode_execute64_match_54(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000104b)
+}
+
+function decode_execute64_match_55(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000606b)
+}
+
+function decode_execute64_match_56(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000706b)
+}
+
+function decode_execute64_match_57(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000107f, (part1 & 0xfe00707f) == 0x0000005b)
+}
+
+function decode_execute64_match_58(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000107f, (part1 & 0xfe00707f) == 0x0000105b)
+}
+
+function decode_execute64_match_59(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00000047)
+}
+
+function decode_execute64_match_60(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x0000107d)
+}
+
+function decode_execute64_match_61(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00004057)
+}
+
+function decode_execute64_match_62(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x07f0707f) == 0x0000007f, (part1 & 0x07f0707f) == 0x0000201d)
+}
+
+function decode_execute64_match_63(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00007005)
+}
+
+function decode_execute64_match_64(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00006005)
+}
+
+function decode_execute64_match_65(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0xfe00707f) == 0x00005005)
+}
+
+function decode_execute64_match_66(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00000015)
+}
+
+function decode_execute64_match_67(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00002015)
+}
+
+function decode_execute64_match_68(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00006067)
+}
+
+function decode_execute64_match_69(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00002067)
+}
+
+function decode_execute64_match_70(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00003067)
+}
+
+function decode_execute64_match_71(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00000067)
+}
+
+function decode_execute64_match_72(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00001067)
+}
+
+function decode_execute64_match_73(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00005067)
+}
+
+function decode_execute64_match_74(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00002055)
+}
+
+function decode_execute64_match_75(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00000055)
+}
+
+function decode_execute64_match_76(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00005055)
+}
+
+function decode_execute64_match_77(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00007055)
+}
+
+function decode_execute64_match_78(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00004055)
+}
+
+function decode_execute64_match_79(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00006055)
+}
+
+function decode_execute64_match_80(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00001055)
+}
+
+function decode_execute64_match_81(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00003055)
+}
+
+function decode_execute64_match_82(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00004067)
+}
+
+function decode_execute64_match_83(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00003015)
+}
+
+function decode_execute64_match_84(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00007067)
+}
+
+function decode_execute64_match_85(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00001015)
+}
+
+function decode_execute64_match_86(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfff0707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00004015)
+}
+
+function decode_execute64_match_87(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000207f, (part1 & 0xf800707f) == 0x0000000b)
+}
+
+function decode_execute64_match_88(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000207f, (part1 & 0xf800707f) == 0x0000100b)
+}
+
+function decode_execute64_match_89(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000207f, (part1 & 0xf800707f) == 0x0000400b)
+}
+
+function decode_execute64_match_90(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000207f, (part1 & 0xf800707f) == 0x0000500b)
+}
+
+function decode_execute64_match_91(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000207f, (part1 & 0xf800707f) == 0x0000200b)
+}
+
+function decode_execute64_match_92(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000207f, (part1 & 0xf800707f) == 0x0000300b)
+}
+
+function decode_execute64_match_93(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000007f, (part1 & 0xf800707f) == 0x0000000b)
+}
+
+function decode_execute64_match_94(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000007f, (part1 & 0xf800707f) == 0x0000100b)
+}
+
+function decode_execute64_match_95(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000007f, (part1 & 0xf800707f) == 0x0000400b)
+}
+
+function decode_execute64_match_96(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000007f, (part1 & 0xf800707f) == 0x0000500b)
+}
+
+function decode_execute64_match_97(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000007f, (part1 & 0xf800707f) == 0x0000200b)
+}
+
+function decode_execute64_match_98(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfc00707f) == 0x0000007f, (part1 & 0xf800707f) == 0x0000300b)
+}
+
+function decode_execute64_match_99(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x01f0707f) == 0x0000007f, (part1 & 0x01f0707f) == 0x0000602d)
+}
+
+function decode_execute64_match_100(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00000005)
+}
+
+function decode_execute64_match_101(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00002005)
+}
+
+function decode_execute64_match_102(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000007f, (part1 & 0x0600707f) == 0x00000009)
+}
+
+function decode_execute64_match_103(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000207f, (part1 & 0x0600707f) == 0x00000009)
+}
+
+function decode_execute64_match_104(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000007f, (part1 & 0x0600707f) == 0x00004009)
+}
+
+function decode_execute64_match_105(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000207f, (part1 & 0x0600707f) == 0x00004009)
+}
+
+function decode_execute64_match_106(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000007f, (part1 & 0x0600707f) == 0x00003009)
+}
+
+function decode_execute64_match_107(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000207f, (part1 & 0x0600707f) == 0x00003009)
+}
+
+function decode_execute64_match_108(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000007f, (part1 & 0x0600707f) == 0x00001009)
+}
+
+function decode_execute64_match_109(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000207f, (part1 & 0x0600707f) == 0x00001009)
+}
+
+function decode_execute64_match_110(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000007f, (part1 & 0x0600707f) == 0x00005009)
+}
+
+function decode_execute64_match_111(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000207f, (part1 & 0x0600707f) == 0x00005009)
+}
+
+function decode_execute64_match_112(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000007f, (part1 & 0x0600707f) == 0x00002009)
+}
+
+function decode_execute64_match_113(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000207f, (part1 & 0x0600707f) == 0x00002009)
+}
+
+function decode_execute64_match_114(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000007f, (part1 & 0x0600707f) == 0x00006009)
+}
+
+function decode_execute64_match_115(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00207f) == 0x0000207f, (part1 & 0x0600707f) == 0x00006009)
+}
+
+function decode_execute64_match_116(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00003005)
+}
+
+function decode_execute64_match_117(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000007f, (part1 & 0x06007fff) == 0x00000049)
+}
+
+function decode_execute64_match_118(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000207f, (part1 & 0x06007fff) == 0x00000049)
+}
+
+function decode_execute64_match_119(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000007f, (part1 & 0x06007fff) == 0x00003049)
+}
+
+function decode_execute64_match_120(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000207f, (part1 & 0x06007fff) == 0x00003049)
+}
+
+function decode_execute64_match_121(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000007f, (part1 & 0x06007fff) == 0x00007049)
+}
+
+function decode_execute64_match_122(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000207f, (part1 & 0x06007fff) == 0x00007049)
+}
+
+function decode_execute64_match_123(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000007f, (part1 & 0x06007fff) == 0x00001049)
+}
+
+function decode_execute64_match_124(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000207f, (part1 & 0x06007fff) == 0x00001049)
+}
+
+function decode_execute64_match_125(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000007f, (part1 & 0x06007fff) == 0x00005049)
+}
+
+function decode_execute64_match_126(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000207f, (part1 & 0x06007fff) == 0x00005049)
+}
+
+function decode_execute64_match_127(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00001005)
+}
+
+function decode_execute64_match_128(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000007f, (part1 & 0x06007fff) == 0x00002049)
+}
+
+function decode_execute64_match_129(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000207f, (part1 & 0x06007fff) == 0x00002049)
+}
+
+function decode_execute64_match_130(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000007f, (part1 & 0x06007fff) == 0x00006049)
+}
+
+function decode_execute64_match_131(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600207f) == 0x0000207f, (part1 & 0x06007fff) == 0x00006049)
+}
+
+function decode_execute64_match_132(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0xfe00707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00004005)
+}
+
+function decode_execute64_match_133(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000404b)
+}
+
+function decode_execute64_match_134(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000504b)
+}
+
+function decode_execute64_match_135(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000604b)
+}
+
+function decode_execute64_match_136(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000704b)
+}
+
+function decode_execute64_match_137(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0600707f) == 0x00006047)
+}
+
+function decode_execute64_match_138(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000101d)
+}
+
+function decode_execute64_match_139(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000301d)
+}
+
+function decode_execute64_match_140(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0600707f) == 0x0000001d)
+}
+
+function decode_execute64_match_141(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000007f) == 0x0000000f, (part1 & 0x00007fff) == 0x00003081)
+}
+
+function decode_execute64_match_142(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000007f) == 0x0000000f, (part1 & 0x00007fff) == 0x00002081)
+}
+
+function decode_execute64_match_143(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000007f) == 0x0000000f, (part1 & 0x00007fff) == 0x00004081)
+}
+
+function decode_execute64_match_144(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000007f) == 0x0000000f, (part1 & 0x00007fff) == 0x00001081)
+}
+
+function decode_execute64_match_145(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000007f) == 0x0000000f, (part1 & 0x00007fff) == 0x00002001)
+}
+
+function decode_execute64_match_146(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000007f) == 0x0000000f, (part1 & 0x00007fff) == 0x00004001)
+}
+
+function decode_execute64_match_147(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000007f) == 0x0000000f, (part1 & 0x00007fff) == 0x00003001)
+}
+
+function decode_execute64_match_148(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000007f) == 0x0000000f, (part1 & 0x00007fff) == 0x00001001)
+}
+
+function decode_execute64_match_149(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000007f) == 0x0000000f, (part1 & 0x00007fff) == 0x00001011)
+}
+
+function decode_execute64_match_150(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00000077)
+}
+
+function decode_execute64_match_151(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0600707f) == 0x0000007f, (part1 & 0x0000707f) == 0x00001077)
+}
+
+function decode_execute64_match_152(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000707f) == 0x0000007f, (part1 & 0x0000707f) == 0x0000502d)
+}
+
+function decode_execute64_match_153(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000707f) == 0x0000007f, (part1 & 0x0000707f) == 0x0000702d)
+}
+
+function decode_execute64_match_154(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000707f) == 0x0000007f, (part1 & 0x0000707f) == 0x0000402d)
+}
+
+function decode_execute64_match_155(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00000019)
+}
+
+function decode_execute64_match_156(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00000019)
+}
+
+function decode_execute64_match_157(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00004019)
+}
+
+function decode_execute64_match_158(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00004019)
+}
+
+function decode_execute64_match_159(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00003019)
+}
+
+function decode_execute64_match_160(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00003019)
+}
+
+function decode_execute64_match_161(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00003029)
+}
+
+function decode_execute64_match_162(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00003029)
+}
+
+function decode_execute64_match_163(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00001019)
+}
+
+function decode_execute64_match_164(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00001019)
+}
+
+function decode_execute64_match_165(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00001029)
+}
+
+function decode_execute64_match_166(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00001029)
+}
+
+function decode_execute64_match_167(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00005019)
+}
+
+function decode_execute64_match_168(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00005019)
+}
+
+function decode_execute64_match_169(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00005029)
+}
+
+function decode_execute64_match_170(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00005029)
+}
+
+function decode_execute64_match_171(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00002019)
+}
+
+function decode_execute64_match_172(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00002019)
+}
+
+function decode_execute64_match_173(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00002029)
+}
+
+function decode_execute64_match_174(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00002029)
+}
+
+function decode_execute64_match_175(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00006019)
+}
+
+function decode_execute64_match_176(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00006019)
+}
+
+function decode_execute64_match_177(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00006029)
+}
+
+function decode_execute64_match_178(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00006029)
+}
+
+function decode_execute64_match_179(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00000059)
+}
+
+function decode_execute64_match_180(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00000059)
+}
+
+function decode_execute64_match_181(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00003059)
+}
+
+function decode_execute64_match_182(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00003059)
+}
+
+function decode_execute64_match_183(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00007059)
+}
+
+function decode_execute64_match_184(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00007059)
+}
+
+function decode_execute64_match_185(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00001059)
+}
+
+function decode_execute64_match_186(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00001059)
+}
+
+function decode_execute64_match_187(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00005059)
+}
+
+function decode_execute64_match_188(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00005059)
+}
+
+function decode_execute64_match_189(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00002059)
+}
+
+function decode_execute64_match_190(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00002059)
+}
+
+function decode_execute64_match_191(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000007f, (part1 & 0x0000707f) == 0x00006059)
+}
+
+function decode_execute64_match_192(inst : bits(64)) -> bool = {
+  let part0 : bits(32) = inst[63..32];
+  let part1 : bits(32) = inst[31..0];
+  and_bool_no_flow((part0 & 0x0000207f) == 0x0000207f, (part1 & 0x0000707f) == 0x00006059)
+}
+
 function decode_execute64(inst : bits(64)) -> unit = {
   let part0 : bits(32) = inst[63..32];
   let part1 : bits(32) = inst[31..0];
-  if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000007b then {
+  if decode_execute64_match_0(inst) then {
     // V.FABS | v.fabs SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 50}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4512,7 +9811,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fabs(decode_vec_reg_selector(srcl), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000707b then {
+  else if decode_execute64_match_1(inst) then {
     // V.FCLASS | v.fclass SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 52}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4524,7 +9823,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fclass(decode_vec_reg_selector(srcl), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000307b then {
+  else if decode_execute64_match_2(inst) then {
     // V.FEXP | v.fexp SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 58}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4536,7 +9835,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fexp(decode_vec_reg_selector(srcl), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000207b then {
+  else if decode_execute64_match_3(inst) then {
     // V.FRECIP | v.frecip SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 72}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4548,7 +9847,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_frecip(decode_vec_reg_selector(srcl), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000107b then {
+  else if decode_execute64_match_4(inst) then {
     // V.FSQRT | v.fsqrt SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 73}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4560,7 +9859,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fsqrt(decode_vec_reg_selector(srcl), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000207d then {
+  else if decode_execute64_match_5(inst) then {
     // V.QPOP | v.qpop SrcL.ud, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 134}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4572,7 +9871,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_qpop(decode_vec_reg_selector(srcl), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000000d then {
+  else if decode_execute64_match_6(inst) then {
     // V.RDADD | v.rdadd SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 136}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4584,7 +9883,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rdadd(regdst[4..0], decode_vec_reg_selector(srcl))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000100d then {
+  else if decode_execute64_match_7(inst) then {
     // V.RDAND | v.rdand SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 137}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4596,7 +9895,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rdand(regdst[4..0], decode_vec_reg_selector(srcl))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000400d then {
+  else if decode_execute64_match_8(inst) then {
     // V.RDFADD | v.rdfadd SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 138}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4608,7 +9907,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rdfadd(regdst[4..0], decode_vec_reg_selector(srcl))
   }
-  else if (part0 & 0xfff0707f) == 0x0000107f & (part1 & 0xfff0707f) == 0x0000200d then {
+  else if decode_execute64_match_9(inst) then {
     // V.RDFMAX | v.rdfmax SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 139}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4620,7 +9919,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rdfmax(regdst[4..0], decode_vec_reg_selector(srcl))
   }
-  else if (part0 & 0xfff0707f) == 0x0000107f & (part1 & 0xfff0707f) == 0x0000300d then {
+  else if decode_execute64_match_10(inst) then {
     // V.RDFMIN | v.rdfmin SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 140}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4632,7 +9931,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rdfmin(regdst[4..0], decode_vec_reg_selector(srcl))
   }
-  else if (part0 & 0xfff0707f) == 0x0000107f & (part1 & 0xfff0707f) == 0x0000000d then {
+  else if decode_execute64_match_11(inst) then {
     // V.RDMAX | v.rdmax SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 141}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4644,7 +9943,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rdmax(regdst[4..0], decode_vec_reg_selector(srcl))
   }
-  else if (part0 & 0xfff0707f) == 0x0000107f & (part1 & 0xfff0707f) == 0x0000100d then {
+  else if decode_execute64_match_12(inst) then {
     // V.RDMIN | v.rdmin SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 142}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4656,7 +9955,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rdmin(regdst[4..0], decode_vec_reg_selector(srcl))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000200d then {
+  else if decode_execute64_match_13(inst) then {
     // V.RDOR | v.rdor SrcL,  ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 143}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4668,7 +9967,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rdor(regdst[4..0], decode_vec_reg_selector(srcl))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfff0707f) == 0x0000300d then {
+  else if decode_execute64_match_14(inst) then {
     // V.RDXOR | v.rdxor SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 144}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4680,7 +9979,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rdxor(regdst[4..0], decode_vec_reg_selector(srcl))
   }
-  else if (part0 & 0xf8007fff) == 0x0000307f & (part1 & 0xfc007fff) == 0x0000000b then {
+  else if decode_execute64_match_15(inst) then {
     // V.SD.ADD | v.sd.add<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 152}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4695,7 +9994,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd_add(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000307f & (part1 & 0xfc007fff) == 0x0000100b then {
+  else if decode_execute64_match_16(inst) then {
     // V.SD.AND | v.sd.and<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 153}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4710,7 +10009,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd_and(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000307f & (part1 & 0xfc007fff) == 0x0000400b then {
+  else if decode_execute64_match_17(inst) then {
     // V.SD.MAX | v.sd.max<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 155}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4725,7 +10024,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd_max(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000307f & (part1 & 0xfc007fff) == 0x0000500b then {
+  else if decode_execute64_match_18(inst) then {
     // V.SD.MIN | v.sd.min<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 156}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4740,7 +10039,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd_min(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000307f & (part1 & 0xfc007fff) == 0x0000200b then {
+  else if decode_execute64_match_19(inst) then {
     // V.SD.OR | v.sd.or<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 157}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4755,7 +10054,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd_or(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000307f & (part1 & 0xfc007fff) == 0x0000300b then {
+  else if decode_execute64_match_20(inst) then {
     // V.SD.XOR | v.sd.xor<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 160}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4770,7 +10069,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd_xor(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000107f & (part1 & 0xfc007fff) == 0x0000000b then {
+  else if decode_execute64_match_21(inst) then {
     // V.SW.ADD | v.sw.add<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 190}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4785,7 +10084,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw_add(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000107f & (part1 & 0xfc007fff) == 0x0000100b then {
+  else if decode_execute64_match_22(inst) then {
     // V.SW.AND | v.sw.and<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 191}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4800,7 +10099,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw_and(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000107f & (part1 & 0xfc007fff) == 0x0000400b then {
+  else if decode_execute64_match_23(inst) then {
     // V.SW.MAX | v.sw.max<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 193}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4815,7 +10114,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw_max(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000107f & (part1 & 0xfc007fff) == 0x0000500b then {
+  else if decode_execute64_match_24(inst) then {
     // V.SW.MIN | v.sw.min<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 194}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4830,7 +10129,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw_min(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000107f & (part1 & 0xfc007fff) == 0x0000200b then {
+  else if decode_execute64_match_25(inst) then {
     // V.SW.OR | v.sw.or<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 195}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4845,7 +10144,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw_or(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xf8007fff) == 0x0000107f & (part1 & 0xfc007fff) == 0x0000300b then {
+  else if decode_execute64_match_26(inst) then {
     // V.SW.XOR | v.sw.xor<.{rl, f, rd, rlf, rdf, rlrd, rlrdf}> [SrcL], SrcR | {'file': 'opcodes/lx_64_prefix.opc', 'line': 198}
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
     let srcr : bits(10) = part0[24..20] @ part1[24..20];
@@ -4860,7 +10159,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw_xor(srcl[4..0], decode_vec_reg_selector(srcr), rl, far, rd)
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfc00707f) == 0x00007015 then {
+  else if decode_execute64_match_27(inst) then {
     // V.SLLI | v.slli SrcL, shamt, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 182}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4873,7 +10172,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_slli(decode_vec_reg_selector(srcl), shamt, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfc00707f) == 0x00006015 then {
+  else if decode_execute64_match_28(inst) then {
     // V.SRAI | v.srai SrcL, shamt, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 184}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4886,7 +10185,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_srai(decode_vec_reg_selector(srcl), shamt, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0xfc00707f) == 0x00005015 then {
+  else if decode_execute64_match_29(inst) then {
     // V.SRLI | v.srli SrcL, shamt, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 186}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4899,7 +10198,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_srli(decode_vec_reg_selector(srcl), shamt, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00002045 then {
+  else if decode_execute64_match_30(inst) then {
     // V.CMP.AND | v.cmp.and SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 31}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4912,7 +10211,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_and(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00000045 then {
+  else if decode_execute64_match_31(inst) then {
     // V.CMP.EQ | v.cmp.eq SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 33}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4925,7 +10224,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_eq(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00005045 then {
+  else if decode_execute64_match_32(inst) then {
     // V.CMP.GE | v.cmp.ge SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 35}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4938,7 +10237,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_ge(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00007045 then {
+  else if decode_execute64_match_33(inst) then {
     // V.CMP.GEU | v.cmp.geu SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 37}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4951,7 +10250,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_geu(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00004045 then {
+  else if decode_execute64_match_34(inst) then {
     // V.CMP.LT | v.cmp.lt SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 39}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4964,7 +10263,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_lt(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00006045 then {
+  else if decode_execute64_match_35(inst) then {
     // V.CMP.LTU | v.cmp.ltu SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 41}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4977,7 +10276,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_ltu(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00001045 then {
+  else if decode_execute64_match_36(inst) then {
     // V.CMP.NE | v.cmp.ne SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 43}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -4990,7 +10289,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_ne(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00003045 then {
+  else if decode_execute64_match_37(inst) then {
     // V.CMP.OR | v.cmp.or SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 45}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5003,7 +10302,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_or(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00000057 then {
+  else if decode_execute64_match_38(inst) then {
     // V.DIV | v.div SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 49}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5016,7 +10315,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_div(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000004b then {
+  else if decode_execute64_match_39(inst) then {
     // V.FADD | v.fadd SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 51}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5029,7 +10328,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fadd(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000006b then {
+  else if decode_execute64_match_40(inst) then {
     // V.FCVT | v.fcvt.{st2dt} SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 53}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5043,7 +10342,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fcvt(decode_vec_reg_selector(srcl), srctype, dsttype, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000106b then {
+  else if decode_execute64_match_41(inst) then {
     // V.FCVTI | v.fcvti.{st2dt} SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 54}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5057,7 +10356,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fcvti(decode_vec_reg_selector(srcl), srctype, dsttype, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000304b then {
+  else if decode_execute64_match_42(inst) then {
     // V.FDIV | v.fdiv SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 55}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5070,7 +10369,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fdiv(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000005b then {
+  else if decode_execute64_match_43(inst) then {
     // V.FEQ | v.feq SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 56}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5083,7 +10382,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_feq(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000405b then {
+  else if decode_execute64_match_44(inst) then {
     // V.FEQS | v.feqs SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 57}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5096,7 +10395,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_feqs(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000305b then {
+  else if decode_execute64_match_45(inst) then {
     // V.FGE | v.fge SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 59}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5109,7 +10408,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fge(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000705b then {
+  else if decode_execute64_match_46(inst) then {
     // V.FGES | v.fges SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 60}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5122,7 +10421,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fges(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000205b then {
+  else if decode_execute64_match_47(inst) then {
     // V.FLT | v.flt SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 61}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5135,7 +10434,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_flt(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000605b then {
+  else if decode_execute64_match_48(inst) then {
     // V.FLTS | v.flts SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 62}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5148,7 +10447,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_flts(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000107f & (part1 & 0xfe00707f) == 0x0000205b then {
+  else if decode_execute64_match_49(inst) then {
     // V.FMAX | v.fmax SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 64}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5161,7 +10460,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fmax(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000107f & (part1 & 0xfe00707f) == 0x0000305b then {
+  else if decode_execute64_match_50(inst) then {
     // V.FMIN | v.fmin SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 65}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5174,7 +10473,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fmin(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000204b then {
+  else if decode_execute64_match_51(inst) then {
     // V.FMUL | v.fmul SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 67}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5187,7 +10486,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fmul(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000105b then {
+  else if decode_execute64_match_52(inst) then {
     // V.FNE | v.fne SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 68}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5200,7 +10499,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fne(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000505b then {
+  else if decode_execute64_match_53(inst) then {
     // V.FNES | v.fnes SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 69}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5213,7 +10512,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fnes(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000104b then {
+  else if decode_execute64_match_54(inst) then {
     // V.FSUB | v.fsub SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 74}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5226,7 +10525,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_fsub(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000606b then {
+  else if decode_execute64_match_55(inst) then {
     // V.ICVT | v.icvt.{st2dt} SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 75}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5240,7 +10539,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_icvt(decode_vec_reg_selector(srcl), srctype, dsttype, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000706b then {
+  else if decode_execute64_match_56(inst) then {
     // V.ICVTF | v.icvtf.{st2dt} SrcL, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 76}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5254,7 +10553,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_icvtf(decode_vec_reg_selector(srcl), srctype, dsttype, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000107f & (part1 & 0xfe00707f) == 0x0000005b then {
+  else if decode_execute64_match_57(inst) then {
     // V.MAX | v.max SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 128}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5267,7 +10566,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_max(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000107f & (part1 & 0xfe00707f) == 0x0000105b then {
+  else if decode_execute64_match_58(inst) then {
     // V.MIN | v.min SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 129}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5280,7 +10579,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_min(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00000047 then {
+  else if decode_execute64_match_59(inst) then {
     // V.MUL | v.mul SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 130}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5293,7 +10592,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_mul(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x0000107d then {
+  else if decode_execute64_match_60(inst) then {
     // V.QPUSH | v.qpush SrcL.ud, SrcR.ud, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 135}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5306,7 +10605,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_qpush(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00004057 then {
+  else if decode_execute64_match_61(inst) then {
     // V.REM | v.rem SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 145}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5319,7 +10618,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rem(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x07f0707f) == 0x0000007f & (part1 & 0x07f0707f) == 0x0000201d then {
+  else if decode_execute64_match_62(inst) then {
     // V.SHFL.BFLY | v.shfl.bfly SrcL, SrcP, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 169}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5332,7 +10631,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, srcp, regdst);
     exec_v_shfl_bfly(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcp), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00007005 then {
+  else if decode_execute64_match_63(inst) then {
     // V.SLL | v.sll SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 181}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5345,7 +10644,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_sll(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00006005 then {
+  else if decode_execute64_match_64(inst) then {
     // V.SRA | v.sra SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 183}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5358,7 +10657,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_sra(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0xfe00707f) == 0x00005005 then {
+  else if decode_execute64_match_65(inst) then {
     // V.SRL | v.srl SrcL, SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 185}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5371,7 +10670,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_srl(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00000015 then {
+  else if decode_execute64_match_66(inst) then {
     // V.ADDI | v.addi SrcL, uimm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 22}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5384,7 +10683,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_addi(decode_vec_reg_selector(srcl), uimm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00002015 then {
+  else if decode_execute64_match_67(inst) then {
     // V.ANDI | v.andi SrcL, simm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 24}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5397,7 +10696,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_andi(decode_vec_reg_selector(srcl), simm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00006067 then {
+  else if decode_execute64_match_68(inst) then {
     // V.BCNT | v.bcnt SrcL, M, N, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 25}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5411,7 +10710,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_bcnt(decode_vec_reg_selector(srcl), imms, imml, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00002067 then {
+  else if decode_execute64_match_69(inst) then {
     // V.BIC | v.bic SrcL, M, N, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 26}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5425,7 +10724,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_bic(decode_vec_reg_selector(srcl), imms, imml, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00003067 then {
+  else if decode_execute64_match_70(inst) then {
     // V.BIS | v.bis SrcL, M, N, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 27}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5439,7 +10738,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_bis(decode_vec_reg_selector(srcl), imms, imml, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00000067 then {
+  else if decode_execute64_match_71(inst) then {
     // V.BXS | v.bxs SrcL, M, N, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 28}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5453,7 +10752,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_bxs(decode_vec_reg_selector(srcl), imms, imml, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00001067 then {
+  else if decode_execute64_match_72(inst) then {
     // V.BXU | v.bxu SrcL, M, N, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 29}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5467,7 +10766,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_bxu(decode_vec_reg_selector(srcl), imms, imml, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00005067 then {
+  else if decode_execute64_match_73(inst) then {
     // V.CLZ | v.clz SrcL, M, N, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 30}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5481,7 +10780,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_clz(decode_vec_reg_selector(srcl), imms, imml, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00002055 then {
+  else if decode_execute64_match_74(inst) then {
     // V.CMP.ANDI | v.cmp.andi SrcL, simm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 32}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5494,7 +10793,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_andi(decode_vec_reg_selector(srcl), simm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00000055 then {
+  else if decode_execute64_match_75(inst) then {
     // V.CMP.EQI | v.cmp.eqi SrcL, simm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 34}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5507,7 +10806,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_eqi(decode_vec_reg_selector(srcl), simm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00005055 then {
+  else if decode_execute64_match_76(inst) then {
     // V.CMP.GEI | v.cmp.gei SrcL, simm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 36}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5520,7 +10819,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_gei(decode_vec_reg_selector(srcl), simm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00007055 then {
+  else if decode_execute64_match_77(inst) then {
     // V.CMP.GEUI | v.cmp.geui SrcL, uimm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 38}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5533,7 +10832,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_geui(decode_vec_reg_selector(srcl), uimm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00004055 then {
+  else if decode_execute64_match_78(inst) then {
     // V.CMP.LTI | v.cmp.lti SrcL, simm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 40}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5546,7 +10845,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_lti(decode_vec_reg_selector(srcl), simm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00006055 then {
+  else if decode_execute64_match_79(inst) then {
     // V.CMP.LTUI | v.cmp.ltui SrcL, uimm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 42}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5559,7 +10858,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_ltui(decode_vec_reg_selector(srcl), uimm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00001055 then {
+  else if decode_execute64_match_80(inst) then {
     // V.CMP.NEI | v.cmp.nei SrcL, simm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 44}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5572,7 +10871,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_nei(decode_vec_reg_selector(srcl), simm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00003055 then {
+  else if decode_execute64_match_81(inst) then {
     // V.CMP.ORI | v.cmp.ori SrcL, simm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 46}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5585,7 +10884,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_cmp_ori(decode_vec_reg_selector(srcl), simm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00004067 then {
+  else if decode_execute64_match_82(inst) then {
     // V.CTZ | v.ctz SrcL, M, N, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 48}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5599,7 +10898,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ctz(decode_vec_reg_selector(srcl), imms, imml, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00003015 then {
+  else if decode_execute64_match_83(inst) then {
     // V.ORI | v.ori SrcL, simm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 132}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5612,7 +10911,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ori(decode_vec_reg_selector(srcl), simm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00007067 then {
+  else if decode_execute64_match_84(inst) then {
     // V.REV | v.rev SrcL, M, N, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 146}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5626,7 +10925,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_rev(decode_vec_reg_selector(srcl), immr, imml, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00001015 then {
+  else if decode_execute64_match_85(inst) then {
     // V.SUBI | v.subi SrcL, uimm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 188}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5639,7 +10938,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_subi(decode_vec_reg_selector(srcl), uimm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfff0707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00004015 then {
+  else if decode_execute64_match_86(inst) then {
     // V.XORI | v.xori SrcL, simm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 204}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5652,7 +10951,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_xori(decode_vec_reg_selector(srcl), simm12, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfc00707f) == 0x0000207f & (part1 & 0xf800707f) == 0x0000000b then {
+  else if decode_execute64_match_87(inst) then {
     // V.LD.ADD | v.ld.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 86}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5668,7 +10967,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ld_add(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000207f & (part1 & 0xf800707f) == 0x0000100b then {
+  else if decode_execute64_match_88(inst) then {
     // V.LD.AND | v.ld.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 87}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5684,7 +10983,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ld_and(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000207f & (part1 & 0xf800707f) == 0x0000400b then {
+  else if decode_execute64_match_89(inst) then {
     // V.LD.MAX | v.ld.max<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 89}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5700,7 +10999,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ld_max(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000207f & (part1 & 0xf800707f) == 0x0000500b then {
+  else if decode_execute64_match_90(inst) then {
     // V.LD.MIN | v.ld.min<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 90}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5716,7 +11015,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ld_min(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000207f & (part1 & 0xf800707f) == 0x0000200b then {
+  else if decode_execute64_match_91(inst) then {
     // V.LD.OR | v.ld.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 91}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5732,7 +11031,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ld_or(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000207f & (part1 & 0xf800707f) == 0x0000300b then {
+  else if decode_execute64_match_92(inst) then {
     // V.LD.XOR | v.ld.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 92}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5748,7 +11047,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ld_xor(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000007f & (part1 & 0xf800707f) == 0x0000000b then {
+  else if decode_execute64_match_93(inst) then {
     // V.LW.ADD | v.lw.add<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 110}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5764,7 +11063,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lw_add(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000007f & (part1 & 0xf800707f) == 0x0000100b then {
+  else if decode_execute64_match_94(inst) then {
     // V.LW.AND | v.lw.and<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 111}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5780,7 +11079,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lw_and(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000007f & (part1 & 0xf800707f) == 0x0000400b then {
+  else if decode_execute64_match_95(inst) then {
     // V.LW.MAX | v.lw.max<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 113}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5796,7 +11095,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lw_max(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000007f & (part1 & 0xf800707f) == 0x0000500b then {
+  else if decode_execute64_match_96(inst) then {
     // V.LW.MIN | v.lw.min<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 114}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5812,7 +11111,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lw_min(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000007f & (part1 & 0xf800707f) == 0x0000200b then {
+  else if decode_execute64_match_97(inst) then {
     // V.LW.OR | v.lw.or<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 115}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5828,7 +11127,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lw_or(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0xfc00707f) == 0x0000007f & (part1 & 0xf800707f) == 0x0000300b then {
+  else if decode_execute64_match_98(inst) then {
     // V.LW.XOR | v.lw.xor<.{aq, rl, f, aqrl, aqf, rlf, aqrlf}> [SrcL], SrcR, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 116}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5844,7 +11143,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lw_xor(decode_vec_reg_selector(regdst), srcl[4..0], decode_vec_reg_selector(srcr), aq, far, rl)
   }
-  else if (part0 & 0x01f0707f) == 0x0000007f & (part1 & 0x01f0707f) == 0x0000602d then {
+  else if decode_execute64_match_99(inst) then {
     // V.SHFLI.BFLY | v.shfli.bfly SrcL, imm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 173}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5857,7 +11156,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_shfli_bfly(decode_vec_reg_selector(srcl), imm, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00000005 then {
+  else if decode_execute64_match_100(inst) then {
     // V.ADD | v.add SrcL, SrcR<.neg><<<shamt>, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 21}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5872,7 +11171,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_add(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00002005 then {
+  else if decode_execute64_match_101(inst) then {
     // V.AND | v.and SrcL, SrcR<.not><<<shamt>, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 23}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -5887,7 +11186,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_and(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0xfe00207f) == 0x0000007f & (part1 & 0x0600707f) == 0x00000009 then {
+  else if decode_execute64_match_102(inst) then {
     // V.LB | v.lb<.local> [SrcL, <lc0>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 77}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -5903,7 +11202,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lb(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000207f & (part1 & 0x0600707f) == 0x00000009 then {
+  else if decode_execute64_match_103(inst) then {
     // V.LB.BRG | v.lb.brg<.local> [SrcL,  <lc0>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 78}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -5919,7 +11218,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lb_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000007f & (part1 & 0x0600707f) == 0x00004009 then {
+  else if decode_execute64_match_104(inst) then {
     // V.LBU | v.lbu<.local> [SrcL, <lc0>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 81}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -5935,7 +11234,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lbu(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000207f & (part1 & 0x0600707f) == 0x00004009 then {
+  else if decode_execute64_match_105(inst) then {
     // V.LBU.BRG | v.lbu.brg<.local> [SrcL, <lc0>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 82}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -5951,7 +11250,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lbu_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000007f & (part1 & 0x0600707f) == 0x00003009 then {
+  else if decode_execute64_match_106(inst) then {
     // V.LD | v.ld<.local> [SrcL, <lc0<<3>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 85}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -5967,7 +11266,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ld(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000207f & (part1 & 0x0600707f) == 0x00003009 then {
+  else if decode_execute64_match_107(inst) then {
     // V.LD.BRG | v.ld.brg<.local> [SrcL,  <lc0<<3>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 88}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -5983,7 +11282,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ld_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000007f & (part1 & 0x0600707f) == 0x00001009 then {
+  else if decode_execute64_match_108(inst) then {
     // V.LH | v.lh<.local> [SrcL, <lc0<<1>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 97}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -5999,7 +11298,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lh(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000207f & (part1 & 0x0600707f) == 0x00001009 then {
+  else if decode_execute64_match_109(inst) then {
     // V.LH.BRG | v.lh.brg<.local> [SrcL,  <lc0<<1>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 98}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6015,7 +11314,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lh_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000007f & (part1 & 0x0600707f) == 0x00005009 then {
+  else if decode_execute64_match_110(inst) then {
     // V.LHU | v.lhu<.local> [SrcL, <lc0<<1>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 103}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6031,7 +11330,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhu(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000207f & (part1 & 0x0600707f) == 0x00005009 then {
+  else if decode_execute64_match_111(inst) then {
     // V.LHU.BRG | v.lhu.brg<.local> [SrcL,  <lc0<<1>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 104}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6047,7 +11346,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhu_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000007f & (part1 & 0x0600707f) == 0x00002009 then {
+  else if decode_execute64_match_112(inst) then {
     // V.LW | v.lw<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 109}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6063,7 +11362,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lw(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000207f & (part1 & 0x0600707f) == 0x00002009 then {
+  else if decode_execute64_match_113(inst) then {
     // V.LW.BRG | v.lw.brg<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 112}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6079,7 +11378,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lw_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000007f & (part1 & 0x0600707f) == 0x00006009 then {
+  else if decode_execute64_match_114(inst) then {
     // V.LWU | v.lwu<.local> [SrcL, <lc0<<2>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 121}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6095,7 +11394,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwu(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00207f) == 0x0000207f & (part1 & 0x0600707f) == 0x00006009 then {
+  else if decode_execute64_match_115(inst) then {
     // V.LWU.BRG | v.lwu.brg<.local> [SrcL,  <lc0<<2>, SrcR<<<shamt>], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 122}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6111,7 +11410,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwu_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00003005 then {
+  else if decode_execute64_match_116(inst) then {
     // V.OR | v.or SrcL, SrcR<.not><<<shamt>, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 131}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6126,7 +11425,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_or(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600207f) == 0x0000007f & (part1 & 0x06007fff) == 0x00000049 then {
+  else if decode_execute64_match_117(inst) then {
     // V.SB | v.sb<.local> SrcD.<T1>, [SrcL, <lc0>, SrcR.<T2><<<shamt>] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 147}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6142,7 +11441,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sb(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000207f & (part1 & 0x06007fff) == 0x00000049 then {
+  else if decode_execute64_match_118(inst) then {
     // V.SB.BRG | v.sb.brg<.local> SrcD.<T1>, [SrcL, <lc0>, SrcR.<T2><<<shamt>] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 148}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6158,7 +11457,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sb_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000007f & (part1 & 0x06007fff) == 0x00003049 then {
+  else if decode_execute64_match_119(inst) then {
     // V.SD | v.sd<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<(3+shamt)] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 151}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6174,7 +11473,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000207f & (part1 & 0x06007fff) == 0x00003049 then {
+  else if decode_execute64_match_120(inst) then {
     // V.SD.BRG | v.sd.brg<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<(3+shamt)] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 154}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6190,7 +11489,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000007f & (part1 & 0x06007fff) == 0x00007049 then {
+  else if decode_execute64_match_121(inst) then {
     // V.SD.U | v.sd.u<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<<shamt>] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 158}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6206,7 +11505,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd_u(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000207f & (part1 & 0x06007fff) == 0x00007049 then {
+  else if decode_execute64_match_122(inst) then {
     // V.SD.U.BRG | v.sd.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<3>, SrcR.<T2><<<shamt>] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 159}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6222,7 +11521,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sd_u_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000007f & (part1 & 0x06007fff) == 0x00001049 then {
+  else if decode_execute64_match_123(inst) then {
     // V.SH | v.sh<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<(1+shamt)] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 165}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6238,7 +11537,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sh(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000207f & (part1 & 0x06007fff) == 0x00001049 then {
+  else if decode_execute64_match_124(inst) then {
     // V.SH.BRG | v.sh.brg<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<(1+shamt)] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 166}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6254,7 +11553,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sh_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000007f & (part1 & 0x06007fff) == 0x00005049 then {
+  else if decode_execute64_match_125(inst) then {
     // V.SH.U | v.sh.u<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<<shamt>] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 167}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6270,7 +11569,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sh_u(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000207f & (part1 & 0x06007fff) == 0x00005049 then {
+  else if decode_execute64_match_126(inst) then {
     // V.SH.U.BRG | v.sh.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<1>, SrcR.<T2><<<shamt>] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 168}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6286,7 +11585,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sh_u_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00001005 then {
+  else if decode_execute64_match_127(inst) then {
     // V.SUB | v.sub SrcL, SrcR<.neg><<<shamt>, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 187}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6301,7 +11600,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_sub(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600207f) == 0x0000007f & (part1 & 0x06007fff) == 0x00002049 then {
+  else if decode_execute64_match_128(inst) then {
     // V.SW | v.sw<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<(2+shamt)] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 189}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6317,7 +11616,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000207f & (part1 & 0x06007fff) == 0x00002049 then {
+  else if decode_execute64_match_129(inst) then {
     // V.SW.BRG | v.sw.brg<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<(2+shamt)] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 192}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6333,7 +11632,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000007f & (part1 & 0x06007fff) == 0x00006049 then {
+  else if decode_execute64_match_130(inst) then {
     // V.SW.U | v.sw.u<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<<shamt>] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 196}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6349,7 +11648,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw_u(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0x0600207f) == 0x0000207f & (part1 & 0x06007fff) == 0x00006049 then {
+  else if decode_execute64_match_131(inst) then {
     // V.SW.U.BRG | v.sw.u.brg<.local> SrcD.<T1>, [SrcL, <lc0<<2>, SrcR.<T2><<<shamt>] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 197}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6365,7 +11664,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sw_u_brg(srcl[4..0], decode_vec_reg_selector(srcr), shamt, decode_vec_reg_selector(srcd), l)
   }
-  else if (part0 & 0xfe00707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00004005 then {
+  else if decode_execute64_match_132(inst) then {
     // V.XOR | v.xor SrcL, SrcR<.not><<<shamt>, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 203}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6380,7 +11679,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_xor(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000404b then {
+  else if decode_execute64_match_133(inst) then {
     // V.FMADD | v.fmadd SrcL, SrcR, SrcA, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 63}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srca : bits(10) = part0[31..27] @ part1[31..27];
@@ -6394,7 +11693,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, srca, 0b00_0000_0000, regdst);
     exec_v_fmadd(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(srca), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000504b then {
+  else if decode_execute64_match_134(inst) then {
     // V.FMSUB | v.fmsub SrcL, SrcR, SrcA, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 66}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srca : bits(10) = part0[31..27] @ part1[31..27];
@@ -6408,7 +11707,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, srca, 0b00_0000_0000, regdst);
     exec_v_fmsub(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(srca), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000604b then {
+  else if decode_execute64_match_135(inst) then {
     // V.FNMADD | v.fnmadd SrcL, SrcR, SrcA, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 70}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srca : bits(10) = part0[31..27] @ part1[31..27];
@@ -6422,7 +11721,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, srca, 0b00_0000_0000, regdst);
     exec_v_fnmadd(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(srca), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000704b then {
+  else if decode_execute64_match_136(inst) then {
     // V.FNMSUB | v.fnmsub SrcL, SrcR, SrcA, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 71}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srca : bits(10) = part0[31..27] @ part1[31..27];
@@ -6436,7 +11735,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, srca, 0b00_0000_0000, regdst);
     exec_v_fnmsub(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(srca), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0600707f) == 0x00006047 then {
+  else if decode_execute64_match_137(inst) then {
     // V.MADD | v.madd SrcL, SrcR, SrcD, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 127}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcd : bits(10) = part0[31..27] @ part1[31..27];
@@ -6450,7 +11749,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_madd(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(srcd), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000101d then {
+  else if decode_execute64_match_138(inst) then {
     // V.SHFL.DOWN | v.shfl.down SrcL, SrcR, SrcP, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 170}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6464,7 +11763,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, srcp, regdst);
     exec_v_shfl_down(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(srcp), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000301d then {
+  else if decode_execute64_match_139(inst) then {
     // V.SHFL.IDX | v.shfl.idx SrcL, SrcR, SrcP, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 171}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6478,7 +11777,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, srcp, regdst);
     exec_v_shfl_idx(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(srcp), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0600707f) == 0x0000001d then {
+  else if decode_execute64_match_140(inst) then {
     // V.SHFL.UP | v.shfl.up SrcL, SrcR, SrcP, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 172}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6492,7 +11791,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, srcp, regdst);
     exec_v_shfl_up(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(srcp), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0000007f) == 0x0000000f & (part1 & 0x00007fff) == 0x00003081 then {
+  else if decode_execute64_match_141(inst) then {
     // L.BSTART.FP | L.BSTART.FP COND, <label> | {'file': 'opcodes/lx_64_prefix.opc', 'line': 17}
     let simm : bits(42) = part1[31..15] @ part0[31..7];
     decoded_block_target_pc_shadow = decode_block_target42(simm);
@@ -6501,7 +11800,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_bstart_fp()
   }
-  else if (part0 & 0x0000007f) == 0x0000000f & (part1 & 0x00007fff) == 0x00002081 then {
+  else if decode_execute64_match_142(inst) then {
     // L.BSTART.FP | L.BSTART.FP DIRECT, <label> | {'file': 'opcodes/lx_64_prefix.opc', 'line': 16}
     let simm : bits(42) = part1[31..15] @ part0[31..7];
     decoded_block_target_pc_shadow = decode_block_target42(simm);
@@ -6510,7 +11809,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_bstart_fp()
   }
-  else if (part0 & 0x0000007f) == 0x0000000f & (part1 & 0x00007fff) == 0x00004081 then {
+  else if decode_execute64_match_143(inst) then {
     // L.BSTART.FP | L.BSTART.FP CALL, <label> | {'file': 'opcodes/lx_64_prefix.opc', 'line': 18}
     let simm : bits(42) = part1[31..15] @ part0[31..7];
     decoded_block_target_pc_shadow = decode_block_target42(simm);
@@ -6519,7 +11818,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_bstart_fp()
   }
-  else if (part0 & 0x0000007f) == 0x0000000f & (part1 & 0x00007fff) == 0x00001081 then {
+  else if decode_execute64_match_144(inst) then {
     // L.BSTART.FP | L.BSTART.FP FALL<, fixup_label> | {'file': 'opcodes/lx_64_prefix.opc', 'line': 15}
     let simm : bits(42) = part1[31..15] @ part0[31..7];
     decoded_block_target_pc_shadow = decode_block_target42(simm);
@@ -6528,7 +11827,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_bstart_fp()
   }
-  else if (part0 & 0x0000007f) == 0x0000000f & (part1 & 0x00007fff) == 0x00002001 then {
+  else if decode_execute64_match_145(inst) then {
     // L.BSTART.STD | L.BSTART.STD DIRECT, <label> | {'file': 'opcodes/lx_64_prefix.opc', 'line': 12}
     let simm : bits(42) = part1[31..15] @ part0[31..7];
     decoded_block_target_pc_shadow = decode_block_target42(simm);
@@ -6537,7 +11836,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_bstart_std()
   }
-  else if (part0 & 0x0000007f) == 0x0000000f & (part1 & 0x00007fff) == 0x00004001 then {
+  else if decode_execute64_match_146(inst) then {
     // L.BSTART.STD | L.BSTART.STD CALL, <label> | {'file': 'opcodes/lx_64_prefix.opc', 'line': 14}
     let simm : bits(42) = part1[31..15] @ part0[31..7];
     decoded_block_target_pc_shadow = decode_block_target42(simm);
@@ -6546,7 +11845,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_bstart_std()
   }
-  else if (part0 & 0x0000007f) == 0x0000000f & (part1 & 0x00007fff) == 0x00003001 then {
+  else if decode_execute64_match_147(inst) then {
     // L.BSTART.STD | L.BSTART.STD COND, <label> | {'file': 'opcodes/lx_64_prefix.opc', 'line': 13}
     let simm : bits(42) = part1[31..15] @ part0[31..7];
     decoded_block_target_pc_shadow = decode_block_target42(simm);
@@ -6555,7 +11854,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_bstart_std()
   }
-  else if (part0 & 0x0000007f) == 0x0000000f & (part1 & 0x00007fff) == 0x00001001 then {
+  else if decode_execute64_match_148(inst) then {
     // L.BSTART.STD | L.BSTART.STD FALL<, fixup_label> | {'file': 'opcodes/lx_64_prefix.opc', 'line': 11}
     let simm : bits(42) = part1[31..15] @ part0[31..7];
     decoded_block_target_pc_shadow = decode_block_target42(simm);
@@ -6564,7 +11863,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_bstart_std()
   }
-  else if (part0 & 0x0000007f) == 0x0000000f & (part1 & 0x00007fff) == 0x00001011 then {
+  else if decode_execute64_match_149(inst) then {
     // L.BSTART.SYS | L.BSTART.SYS FALL<, fixup_label> | {'file': 'opcodes/lx_64_prefix.opc', 'line': 19}
     let simm : bits(42) = part1[31..15] @ part0[31..7];
     decoded_block_target_pc_shadow = decode_block_target42(simm);
@@ -6573,7 +11872,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     decoded_block_contract_kind_shadow = 0b0000;
     exec_bstart_sys()
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00000077 then {
+  else if decode_execute64_match_150(inst) then {
     // V.CSEL | v.csel SrcP, SrcL, SrcR<.neg>, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 47}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6588,7 +11887,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, srcp, regdst);
     exec_v_csel(decode_vec_reg_selector(srcp), decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0600707f) == 0x0000007f & (part1 & 0x0000707f) == 0x00001077 then {
+  else if decode_execute64_match_151(inst) then {
     // V.PSEL | v.psel  SrcP, SrcL, SrcR<.neg>, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 133}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6603,7 +11902,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, srczero, regdst);
     exec_v_psel(decode_vec_reg_selector(srczero), decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), decode_srcrtype_neg(srcrtype), decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0000707f) == 0x0000007f & (part1 & 0x0000707f) == 0x0000502d then {
+  else if decode_execute64_match_152(inst) then {
     // V.SHFLI.DOWN | v.shfli.down SrcL, SrcR, imm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 174}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6617,7 +11916,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_shfli_down(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), imm, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0000707f) == 0x0000007f & (part1 & 0x0000707f) == 0x0000702d then {
+  else if decode_execute64_match_153(inst) then {
     // V.SHFLI.IDX | v.shfli.idx SrcL, SrcR, imm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 175}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6631,7 +11930,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_shfli_idx(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), imm, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0000707f) == 0x0000007f & (part1 & 0x0000707f) == 0x0000402d then {
+  else if decode_execute64_match_154(inst) then {
     // V.SHFLI.UP | v.shfli.up SrcL, SrcR, imm, ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 176}
     let regdst : bits(10) = part0[11..7] @ part1[11..7];
     let srcl : bits(10) = part0[19..15] @ part1[19..15];
@@ -6645,7 +11944,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_shfli_up(decode_vec_reg_selector(srcl), decode_vec_reg_selector(srcr), imm, decode_vec_reg_selector(regdst))
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00000019 then {
+  else if decode_execute64_match_155(inst) then {
     // V.LBI | v.lbi<.local> [SrcL, <lc0>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 79}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6660,7 +11959,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lbi(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00000019 then {
+  else if decode_execute64_match_156(inst) then {
     // V.LBI.BRG | v.lbi.brg<.local> [SrcL, <lc0>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 80}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6675,7 +11974,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lbi_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00004019 then {
+  else if decode_execute64_match_157(inst) then {
     // V.LBUI | v.lbui<.local> [SrcL, <lc0>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 83}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6690,7 +11989,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lbui(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00004019 then {
+  else if decode_execute64_match_158(inst) then {
     // V.LBUI.BRG | v.lbui.brg<.local> [SrcL, <lc0>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 84}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6705,7 +12004,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lbui_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00003019 then {
+  else if decode_execute64_match_159(inst) then {
     // V.LDI | v.ldi<.local> [SrcL, <lc0<<3>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 93}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6720,7 +12019,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ldi(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00003019 then {
+  else if decode_execute64_match_160(inst) then {
     // V.LDI.BRG | v.ldi.brg<.local> [SrcL, <lc0<<3>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 94}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6735,7 +12034,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ldi_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00003029 then {
+  else if decode_execute64_match_161(inst) then {
     // V.LDI.U | v.ldi.u<.local> [SrcL, <lc0<<3>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 95}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6750,7 +12049,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ldi_u(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00003029 then {
+  else if decode_execute64_match_162(inst) then {
     // V.LDI.U.BRG | v.ldi.u.brg<.local> [SrcL, <lc0<<3>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 96}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6765,7 +12064,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_ldi_u_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00001019 then {
+  else if decode_execute64_match_163(inst) then {
     // V.LHI | v.lhi<.local> [SrcL, <lc0<<1>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 99}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6780,7 +12079,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhi(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00001019 then {
+  else if decode_execute64_match_164(inst) then {
     // V.LHI.BRG | v.lhi.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 100}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6795,7 +12094,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhi_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00001029 then {
+  else if decode_execute64_match_165(inst) then {
     // V.LHI.U | v.lhi.u<.local> [SrcL, <lc0<<1>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 101}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6810,7 +12109,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhi_u(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00001029 then {
+  else if decode_execute64_match_166(inst) then {
     // V.LHI.U.BRG | v.lhi.u.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 102}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6825,7 +12124,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhi_u_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00005019 then {
+  else if decode_execute64_match_167(inst) then {
     // V.LHUI | v.lhui<.local> [SrcL, <lc0<<1>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 105}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6840,7 +12139,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhui(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00005019 then {
+  else if decode_execute64_match_168(inst) then {
     // V.LHUI.BRG | v.lhui.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 106}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6855,7 +12154,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhui_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00005029 then {
+  else if decode_execute64_match_169(inst) then {
     // V.LHUI.U | v.lhui.u<.local> [SrcL, <lc0<<1>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 107}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6870,7 +12169,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhui_u(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00005029 then {
+  else if decode_execute64_match_170(inst) then {
     // V.LHUI.U.BRG | v.lhui.u.brg<.local> [SrcL, <lc0<<1>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 108}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6885,7 +12184,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lhui_u_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00002019 then {
+  else if decode_execute64_match_171(inst) then {
     // V.LWI | v.lwi<.local> [SrcL, <lc0<<2>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 117}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6900,7 +12199,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwi(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00002019 then {
+  else if decode_execute64_match_172(inst) then {
     // V.LWI.BRG | v.lwi.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 118}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6915,7 +12214,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwi_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00002029 then {
+  else if decode_execute64_match_173(inst) then {
     // V.LWI.U | v.lwi.u<.local> [SrcL, <lc0<<2>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 119}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6930,7 +12229,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwi_u(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00002029 then {
+  else if decode_execute64_match_174(inst) then {
     // V.LWI.U.BRG | v.lwi.u.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 120}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6945,7 +12244,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwi_u_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00006019 then {
+  else if decode_execute64_match_175(inst) then {
     // V.LWUI | v.lwui<.local> [SrcL, <lc0<<2>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 123}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6960,7 +12259,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwui(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00006019 then {
+  else if decode_execute64_match_176(inst) then {
     // V.LWUI.BRG | v.lwui.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 124}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6975,7 +12274,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwui_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00006029 then {
+  else if decode_execute64_match_177(inst) then {
     // V.LWUI.U | v.lwui.u<.local> [SrcL, <lc0<<2>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 125}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -6990,7 +12289,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwui_u(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00006029 then {
+  else if decode_execute64_match_178(inst) then {
     // V.LWUI.U.BRG | v.lwui.u.brg<.local> [SrcL, <lc0<<2>, simm], ->Dst | {'file': 'opcodes/lx_64_prefix.opc', 'line': 126}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7005,7 +12304,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000, regdst);
     exec_v_lwui_u_brg(srcl[4..0], simm24, decode_vec_reg_selector(regdst), l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00000059 then {
+  else if decode_execute64_match_179(inst) then {
     // V.SBI | v.sbi<.local> SrcL, [SrcR, <lc0>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 149}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7020,7 +12319,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sbi(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00000059 then {
+  else if decode_execute64_match_180(inst) then {
     // V.SBI.BRG | v.sbi.brg<.local> SrcL, [SrcR, <lc0>,  simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 150}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7035,7 +12334,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sbi_brg(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00003059 then {
+  else if decode_execute64_match_181(inst) then {
     // V.SDI | v.sdi<.local> SrcL, [SrcR, <lc0<3>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 161}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7050,7 +12349,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sdi(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00003059 then {
+  else if decode_execute64_match_182(inst) then {
     // V.SDI.BRG | v.sdi.brg<.local> SrcL, [SrcR, <lc0<<3>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 162}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7065,7 +12364,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sdi_brg(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00007059 then {
+  else if decode_execute64_match_183(inst) then {
     // V.SDI.U | v.sdi.u<.local> SrcL, [SrcR, <lc0<<3>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 163}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7080,7 +12379,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sdi_u(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00007059 then {
+  else if decode_execute64_match_184(inst) then {
     // V.SDI.U.BRG | v.sdi.u.brg<.local> SrcL, [SrcR, <lc0<<3>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 164}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7095,7 +12394,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_sdi_u_brg(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00001059 then {
+  else if decode_execute64_match_185(inst) then {
     // V.SHI | v.shi<.local> SrcL, [SrcR, <lc0<<1>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 177}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7110,7 +12409,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_shi(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00001059 then {
+  else if decode_execute64_match_186(inst) then {
     // V.SHI.BRG | v.shi.brg<.local> SrcL, [SrcR, <lc0<<1>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 178}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7125,7 +12424,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_shi_brg(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00005059 then {
+  else if decode_execute64_match_187(inst) then {
     // V.SHI.U | v.shi.u<.local> SrcL, [SrcR, <lc0<<1>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 179}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7140,7 +12439,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_shi_u(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00005059 then {
+  else if decode_execute64_match_188(inst) then {
     // V.SHI.U.BRG | v.shi.u.brg<.local> SrcL, [SrcR, <lc0<<1>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 180}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7155,7 +12454,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_shi_u_brg(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00002059 then {
+  else if decode_execute64_match_189(inst) then {
     // V.SWI | v.swi<.local> SrcL, [SrcR, <lc0<<2>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 199}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7170,7 +12469,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_swi(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00002059 then {
+  else if decode_execute64_match_190(inst) then {
     // V.SWI.BRG | v.swi.brg<.local> SrcL, [SrcR, <lc0<<2>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 200}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7185,7 +12484,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_swi_brg(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000007f & (part1 & 0x0000707f) == 0x00006059 then {
+  else if decode_execute64_match_191(inst) then {
     // V.SWI.U | v.swi.u<.local> SrcL, [SrcR, <lc0<<2>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 201}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
@@ -7200,7 +12499,7 @@ function decode_execute64(inst : bits(64)) -> unit = {
     set_decoded_vec_regids(srcl, srcr, 0b00_0000_0000, 0b00_0000_0000, 0b00_0000_0000);
     exec_v_swi_u(decode_vec_reg_selector(srcl), srcr[4..0], simm24, l)
   }
-  else if (part0 & 0x0000207f) == 0x0000207f & (part1 & 0x0000707f) == 0x00006059 then {
+  else if decode_execute64_match_192(inst) then {
     // V.SWI.U.BRG | v.swi.u.brg<.local> SrcL, [SrcR, <lc0<<2>, simm] | {'file': 'opcodes/lx_64_prefix.opc', 'line': 202}
     let c : bits(1) = part0[12];
     let l : bits(1) = part0[14];
diff --git a/isa/sail/model/execute/execute.sail b/isa/sail/model/execute/execute.sail
index fb16e348..53bd842c 100644
--- a/isa/sail/model/execute/execute.sail
+++ b/isa/sail/model/execute/execute.sail
@@ -2820,6 +2820,204 @@ function exec_bwi() -> unit = { () }
 function exec_bwe() -> unit = { () }
 function exec_bse() -> unit = { () }
 
+// -----------------------------------------------------------------------------
+// PTO ISA 0.57.1 tile transaction envelope
+
+function tile_effect_begin(family : bits(2), selector : bits(5)) -> unit = {
+  tile_effect_pending = true;
+  tile_effect_family = family;
+  tile_effect_function = selector;
+  tile_effect_datatype = decoded_tile_datatype();
+  tile_effect_restart_pending = false;
+  tile_effect_reset_descriptors()
+}
+
+function tile_effect_append_iot(raw : bits(64)) -> unit = {
+  let func : bits(3) = raw[14..12];
+  let source_count : bits(6) =
+    if func == 0b100 then 0b00_0010
+    else if func == 0b101 then 0b00_0001
+    else if func == 0b110 then 0b00_0000
+    else 0b00_0000;
+  let size : bits(4) = raw[18..15];
+  let dst : bits(3) = raw[9..7];
+  let output_active = (unsigned(size) >= 3) & (unsigned(size) <= 9) & (unsigned(dst) <= 3);
+  let last = raw[19] == 0b1;
+  if tile_effect_last_seen then tile_effect_after_last = true else ();
+  if last then tile_effect_last_seen = true else ();
+  tile_effect_iot_count = tile_effect_iot_count + 0b00_0001;
+  tile_effect_source_count = tile_effect_source_count + source_count;
+  if output_active then tile_effect_output_count = tile_effect_output_count + 0b00_0001 else ();
+  if (func != 0b100) & (func != 0b101) & (func != 0b110) then tile_effect_iot_legal = false else ();
+  if (size != 0b0000) & not_bool(output_active) then tile_effect_iot_legal = false else ();
+  if (unsigned(source_count) >= 1) & (raw[10] == 0b0) then
+    tile_effect_release_count = tile_effect_release_count + 0b00_0001
+  else ();
+  if (source_count == 0b00_0010) & (raw[11] == 0b0) then
+    tile_effect_release_count = tile_effect_release_count + 0b00_0001
+  else ();
+  bdesc_mark_iot()
+}
+
+function tile_tma_required_sources(selector : bits(5)) -> bits(6) = {
+  if selector == 0b00100 then 0b00_0001       // MGATHER
+  else if selector == 0b00110 then 0b00_0010  // MGATHER.MASK
+  else if selector == 0b00101 then 0b00_0010  // MSCATTER
+  else if selector == 0b00111 then 0b00_0011  // MSCATTER.MASK
+  else if selector == 0b01000 then 0b00_0011  // MGATHER.CAS
+  else 0b00_0000
+}
+
+function tile_tma_produces_output(selector : bits(5)) -> bool = {
+  (selector == 0b00100) | (selector == 0b00110) | (selector == 0b01000)
+}
+
+function tile_cube_required_sources(selector : bits(5)) -> bits(6) = {
+  if (selector == 0b00000) | (selector == 0b00010) |
+     (selector == 0b10000) | (selector == 0b10010) then 0b00_0010
+  else if (selector == 0b00001) | (selector == 0b10001) then 0b00_0011
+  else if (selector == 0b00100) | (selector == 0b00110) |
+          (selector == 0b10100) | (selector == 0b10110) then 0b00_0100
+  else if (selector == 0b00101) | (selector == 0b10101) then 0b00_0101
+  else 0b00_0000
+}
+
+function tile_cube_is_mx(selector : bits(5)) -> bool = {
+  (selector == 0b00100) | (selector == 0b00101) | (selector == 0b00110) |
+  (selector == 0b10100) | (selector == 0b10101) | (selector == 0b10110)
+}
+
+function tile_cube_is_bias(selector : bits(5)) -> bool = {
+  (selector == 0b00001) | (selector == 0b00101) |
+  (selector == 0b10001) | (selector == 0b10101)
+}
+
+function tile_cube_is_accumulate(selector : bits(5)) -> bool = {
+  (selector == 0b00010) | (selector == 0b00110) |
+  (selector == 0b10010) | (selector == 0b10110)
+}
+
+function tile_numeric_ordinary(dtype : bits(5)) -> bool = {
+  (unsigned(dtype) <= 12) | (dtype == 0b01110) |
+  ((unsigned(dtype) >= 16) & (unsigned(dtype) <= 20)) |
+  ((unsigned(dtype) >= 24) & (unsigned(dtype) <= 28))
+}
+
+function tile_cube_dim(value : bits(64)) -> bits(64) = {
+  if value == 0x0000_0000_0000_0000 then 0x0000_0000_0000_0008 else value
+}
+
+function tile_effect_header_legal() -> bool = {
+  if tile_effect_family == 0b01 then {
+    if tile_effect_function == 0b00011 then {
+      // TPREFETCH has scalar address/byte-count operands and no Tile IO.
+      bdesc_seen_datr & bdesc_seen_ior & not_bool(bdesc_seen_text) &
+      (tile_effect_iot_count == 0b00_0000)
+    } else {
+      let required = tile_tma_required_sources(tile_effect_function);
+      let output_ok =
+        if tile_tma_produces_output(tile_effect_function) then tile_effect_output_count == 0b00_0001
+        else tile_effect_output_count == 0b00_0000;
+      (required != 0b00_0000) & bdesc_seen_datr & bdesc_seen_ior & bdesc_seen_iot &
+      not_bool(bdesc_seen_text) & tile_effect_iot_legal & tile_effect_last_seen &
+      not_bool(tile_effect_after_last) & (tile_effect_source_count == required) & output_ok &
+      ((tile_effect_function != 0b01000) | (bcatr_raw[17] == 0b1))
+    }
+  } else if tile_effect_family == 0b10 then {
+    if tile_effect_function == 0b01000 then {
+      bdesc_seen_datr & bdesc_seen_iot & not_bool(bdesc_seen_text) & tile_effect_iot_legal &
+      tile_effect_last_seen & not_bool(tile_effect_after_last) & tile_acc_valid &
+      (tile_effect_source_count == 0b00_0000) & (tile_effect_output_count == 0b00_0001)
+    } else {
+      let required = tile_cube_required_sources(tile_effect_function);
+      let mx = tile_cube_is_mx(tile_effect_function);
+      let accumulate = tile_cube_is_accumulate(tile_effect_function);
+      let m = tile_cube_dim(ssr_lb0);
+      let n = tile_cube_dim(ssr_lb1);
+      let k = tile_cube_dim(ssr_lb2);
+      let dtype_ok = if mx then tile_effect_datatype == 0b00001 else tile_numeric_ordinary(tile_effect_datatype);
+      let acc_ok =
+        if accumulate then tile_acc_valid & (tile_acc_rows == m) & (tile_acc_cols == n) &
+          (tile_acc_k == k) & (tile_acc_datatype == (if mx then 0b00001 else tile_effect_datatype))
+        else true;
+      (required != 0b00_0000) & bdesc_seen_datr & bdesc_seen_dim & bdesc_seen_iot &
+      not_bool(bdesc_seen_text) & tile_effect_iot_legal & tile_effect_last_seen &
+      not_bool(tile_effect_after_last) & (tile_effect_source_count == required) &
+      (tile_effect_output_count == 0b00_0000) & dtype_ok & acc_ok
+    }
+  } else false
+}
+
+function tile_effect_publish() -> unit = {
+  let family = tile_effect_family;
+  let selector = tile_effect_function;
+  let mx = (family == 0b10) & tile_cube_is_mx(selector);
+  let bias = (family == 0b10) & tile_cube_is_bias(selector);
+  let accumulate = (family == 0b10) & tile_cube_is_accumulate(selector);
+  tile_effect_preflight_seq = tile_effect_preflight_seq + 1;
+  tile_effect_commit_seq = tile_effect_commit_seq + 1;
+  tile_effect_lifetime_releases = tile_effect_lifetime_releases + sail_zero_extend(tile_effect_release_count, 64);
+  tile_effect_last_family = family;
+  tile_effect_last_function = selector;
+  tile_effect_last_datatype = tile_effect_datatype;
+  tile_effect_last_masked = (family == 0b01) & ((selector == 0b00110) | (selector == 0b00111));
+  tile_effect_last_mask_suppresses_access = tile_effect_last_masked;
+  tile_effect_last_pad = bdatr_raw[28..27];
+  tile_effect_last_mx = mx;
+  tile_effect_last_bias = bias;
+  tile_effect_last_accumulate = accumulate;
+  if family == 0b01 then {
+    if selector != 0b00011 then tile_effect_memory_seq = tile_effect_memory_seq + 1 else ();
+    if tile_tma_produces_output(selector) then tile_effect_tile_seq = tile_effect_tile_seq + 1 else ()
+  } else if family == 0b10 then {
+    if selector == 0b01000 then {
+      tile_effect_tile_seq = tile_effect_tile_seq + 1;
+      tile_acc_valid = false
+    } else {
+      let m = tile_cube_dim(ssr_lb0);
+      let n = tile_cube_dim(ssr_lb1);
+      let k = tile_cube_dim(ssr_lb2);
+      tile_effect_acc_seq = tile_effect_acc_seq + 1;
+      tile_acc_valid = true;
+      tile_acc_datatype = if mx then 0b00001 else tile_effect_datatype;
+      tile_acc_rows = m;
+      tile_acc_cols = n;
+      tile_acc_k = k;
+      if mx then {
+        let groups_i : int = tdiv_int(unsigned(k) + 31, 32);
+        let groups : bits(64) = sail_zeros(64) + groups_i;
+        tile_effect_last_scale_a_rows = m;
+        tile_effect_last_scale_a_cols = groups;
+        tile_effect_last_scale_b_rows = groups;
+        tile_effect_last_scale_b_cols = n;
+        // B.IOT authored source order: A, B, ScaleA, ScaleB, optional Bias.
+        tile_effect_last_scale_a_source = 0b00_0010;
+        tile_effect_last_scale_b_source = 0b00_0011
+      } else ()
+    }
+  } else ();
+  tile_effect_pending = false;
+  tile_effect_restart_pending = false
+}
+
+function tile_effect_finalize() -> bool = {
+  if not_bool(tile_effect_pending) then true
+  else if not_bool(tile_effect_header_legal()) then {
+    // Descriptor/operand preflight fails before every architectural effect.
+    trap_blockfmt(0x05, 0x01, read_pc_or_tpc());
+    tile_effect_restart_pending = true;
+    false
+  } else if not_bool(tile_effect_access_set_valid) then {
+    // The host memory/IOMMU hook reports the first failing original address.
+    trap_data_page_fault(tile_effect_fault_address);
+    tile_effect_restart_pending = true;
+    false
+  } else {
+    tile_effect_publish();
+    true
+  }
+}
+
 // -----------------------------------------------------------------------------
 // CMD: Block boundary markers (BSTART/BSTOP)
 //
@@ -2829,7 +3027,7 @@ function exec_bse() -> unit = { () }
 // Architectural rule: every control-flow target must land on a block start marker;
 // violations trap with E_BLOCK(EC_CFI), kind=CFI_BAD_TARGET.
 
-function exec_bstart() -> unit = {
+function exec_bstart_transition() -> bool = {
   // Generic BSTART (COND, <label>) form.
   // - Terminates previous block (commit boundary).
   // - Starts a new block and initializes BARG.
@@ -2839,7 +3037,12 @@ function exec_bstart() -> unit = {
   let tgt = decoded_block_target_pc();
   if not_bool(is_block_start_marker(tgt)) then {
     // EC_CFI_KIND=1 (CFI_BAD_TARGET)
-    trap_block_cfi(0x1, read_pc_or_tpc())
+    trap_block_cfi(0x1, read_pc_or_tpc());
+    false
+  } else if tile_effect_pending & not_bool(tile_effect_finalize()) then {
+    // A next BSTART also terminates the prior header.  Failed preflight leaves
+    // the old operation pending and must not install the new block.
+    false
   } else {
     block_commit_boundary();
     barg_reset_at_block_start();
@@ -2847,10 +3050,17 @@ function exec_bstart() -> unit = {
     bdesc_reset();
     barg_set_block_type(decoded_block_type());
     barg_set_xfer_kind(decoded_block_xfer_kind());
-    barg_set_next_pc_target(tgt)
+    barg_set_next_pc_target(tgt);
+    true
   }
 }
 
+function exec_bstart() -> unit = { let _accepted = exec_bstart_transition(); () }
+
+function exec_tile_bstart(family : bits(2), selector : bits(5)) -> unit = {
+  if exec_bstart_transition() then tile_effect_begin(family, selector) else ()
+}
+
 // Typed 32/48-bit BSTART variants share the same boundary semantics; the decoder
 // distinguishes the specific block type/xfer kind encoding.
 function exec_bstart_std() -> unit = { exec_bstart() }
@@ -2862,29 +3072,28 @@ function exec_bstart_vpar() -> unit = { exec_bstart() }
 function exec_bstart_vseq() -> unit = { exec_bstart() }
 function exec_bstart_cube() -> unit = { exec_bstart() }
 function exec_bstart_tepl() -> unit = { exec_bstart() }
-function exec_bstart_fixp() -> unit = { exec_bstart() }
 function exec_bstart_tload() -> unit = { exec_bstart() }
 function exec_bstart_tstore() -> unit = { exec_bstart() }
 function exec_bstart_tmov() -> unit = { exec_bstart() }
-function exec_bstart_tmatmul() -> unit = { exec_bstart() }
-function exec_bstart_tmatmul_acc() -> unit = { exec_bstart() }
-function exec_bstart_acccvt() -> unit = { exec_bstart() }
-function exec_bstart_mgather() -> unit = { exec_bstart() }
-function exec_bstart_mgather_cas() -> unit = { exec_bstart() }
-function exec_bstart_mgather_mask() -> unit = { exec_bstart() }
-function exec_bstart_mscatter() -> unit = { exec_bstart() }
-function exec_bstart_mscatter_mask() -> unit = { exec_bstart() }
-function exec_bstart_tgemv() -> unit = { exec_bstart() }
-function exec_bstart_tgemv_acc() -> unit = { exec_bstart() }
-function exec_bstart_tgemv_bias() -> unit = { exec_bstart() }
-function exec_bstart_tgemvmx() -> unit = { exec_bstart() }
-function exec_bstart_tgemvmx_acc() -> unit = { exec_bstart() }
-function exec_bstart_tgemvmx_bias() -> unit = { exec_bstart() }
-function exec_bstart_tmatmul_bias() -> unit = { exec_bstart() }
-function exec_bstart_tmatmulmx() -> unit = { exec_bstart() }
-function exec_bstart_tmatmulmx_acc() -> unit = { exec_bstart() }
-function exec_bstart_tmatmulmx_bias() -> unit = { exec_bstart() }
-function exec_bstart_tprefetch() -> unit = { exec_bstart_tload() }
+function exec_bstart_tmatmul() -> unit = { exec_tile_bstart(0b10, 0b00000) }
+function exec_bstart_tmatmul_acc() -> unit = { exec_tile_bstart(0b10, 0b00010) }
+function exec_bstart_acccvt() -> unit = { exec_tile_bstart(0b10, 0b01000) }
+function exec_bstart_mgather() -> unit = { exec_tile_bstart(0b01, 0b00100) }
+function exec_bstart_mgather_cas() -> unit = { exec_tile_bstart(0b01, 0b01000) }
+function exec_bstart_mgather_mask() -> unit = { exec_tile_bstart(0b01, 0b00110) }
+function exec_bstart_mscatter() -> unit = { exec_tile_bstart(0b01, 0b00101) }
+function exec_bstart_mscatter_mask() -> unit = { exec_tile_bstart(0b01, 0b00111) }
+function exec_bstart_tgemv() -> unit = { exec_tile_bstart(0b10, 0b10000) }
+function exec_bstart_tgemv_acc() -> unit = { exec_tile_bstart(0b10, 0b10010) }
+function exec_bstart_tgemv_bias() -> unit = { exec_tile_bstart(0b10, 0b10001) }
+function exec_bstart_tgemvmx() -> unit = { exec_tile_bstart(0b10, 0b10100) }
+function exec_bstart_tgemvmx_acc() -> unit = { exec_tile_bstart(0b10, 0b10110) }
+function exec_bstart_tgemvmx_bias() -> unit = { exec_tile_bstart(0b10, 0b10101) }
+function exec_bstart_tmatmul_bias() -> unit = { exec_tile_bstart(0b10, 0b00001) }
+function exec_bstart_tmatmulmx() -> unit = { exec_tile_bstart(0b10, 0b00100) }
+function exec_bstart_tmatmulmx_acc() -> unit = { exec_tile_bstart(0b10, 0b00110) }
+function exec_bstart_tmatmulmx_bias() -> unit = { exec_tile_bstart(0b10, 0b00101) }
+function exec_bstart_tprefetch() -> unit = { exec_tile_bstart(0b01, 0b00011) }
 function exec_fused_bstart_call(uimm5 : bits(5), embedded_setret_bytes : bits(64)) -> unit = {
   // The exact aggregate form is one atomic CALL transition composed from a
   // block-start target and an embedded C.SETRET.  The fields are independent:
@@ -2930,8 +3139,12 @@ function exec_bstop() -> unit = {
   // Explicit block terminator.
   // For staged tile/vector headers, perform mandatory-descriptor validation at
   // the end of the header stream before committing the boundary.
-  bdesc_validate_header_end(read_pc_or_tpc());
-  block_commit_boundary()
+  if tile_effect_pending then {
+    if tile_effect_finalize() then block_commit_boundary() else ()
+  } else {
+    bdesc_validate_header_end(read_pc_or_tpc());
+    block_commit_boundary()
+  }
 }
 
 function exec_c_bstop() -> unit = { exec_bstop() }
@@ -2959,7 +3172,6 @@ function exec_c_b_dim() -> unit = { exec_b_dim() }
 function exec_c_b_dimi() -> unit = { exec_b_dim() }
 
 function exec_b_text() -> unit = { bdesc_mark_text() }
-function exec_b_arg() -> unit = { bdesc_mark_arg() }
 function exec_b_ior() -> unit = {
   let src0 : bits(5) = decoded_bior_regsrc0();
   let src1 : bits(5) = decoded_bior_regsrc1();
@@ -2972,7 +3184,7 @@ function exec_b_ior() -> unit = {
   if src2 != 0b00000 then allocate_ri_binding(src2) else ();
   bdesc_mark_ior()
 }
-function exec_b_iot() -> unit = { bdesc_mark_iot() }
+function exec_b_iot() -> unit = { tile_effect_append_iot(decoded_biot_raw()) }
 
 function exec_b_catr() -> unit = {
   // Staged semantics: latch raw control-attribute word so DR (bit 26) can be consulted.
@@ -2981,7 +3193,8 @@ function exec_b_catr() -> unit = {
 
 function exec_b_datr() -> unit = {
   // Staged semantics: latch raw data-attribute word so datatype/layout/rmode/sat can be consulted.
-  bdatr_raw = decoded_bdatr_raw()
+  bdatr_raw = decoded_bdatr_raw();
+  bdesc_mark_datr()
 }
 function exec_b_hint() -> unit = { () }
 // -----------------------------------------------------------------------------
diff --git a/isa/sail/model/state/state.sail b/isa/sail/model/state/state.sail
index 6b286513..90112eb6 100644
--- a/isa/sail/model/state/state.sail
+++ b/isa/sail/model/state/state.sail
@@ -181,6 +181,8 @@ register decoded_bdim_index_shadow : bits(2) = 0b00
 register decoded_bdim_value_shadow : bits(64) = 0x0000_0000_0000_0000
 register decoded_bcatr_raw_shadow : bits(64) = 0x0000_0000_0000_0000
 register decoded_bdatr_raw_shadow : bits(64) = 0x0000_0000_0000_0000
+register decoded_biot_raw_shadow : bits(64) = 0x0000_0000_0000_0000
+register decoded_tile_datatype_shadow : bits(5) = 0b00000
 register decoded_bior_regsrc0_shadow : bits(5) = 0b00000
 register decoded_bior_regsrc1_shadow : bits(5) = 0b00000
 register decoded_bior_regsrc2_shadow : bits(5) = 0b00000
@@ -205,6 +207,9 @@ function decoded_bdatr_raw() -> bits(64) = {
   decoded_bdatr_raw_shadow
 }
 
+function decoded_biot_raw() -> bits(64) = { decoded_biot_raw_shadow }
+function decoded_tile_datatype() -> bits(5) = { decoded_tile_datatype_shadow }
+
 function decoded_bior_regsrc0() -> bits(5) = { decoded_bior_regsrc0_shadow }
 function decoded_bior_regsrc1() -> bits(5) = { decoded_bior_regsrc1_shadow }
 function decoded_bior_regsrc2() -> bits(5) = { decoded_bior_regsrc2_shadow }
@@ -221,7 +226,113 @@ function set_decoded_bior(regsrc0 : bits(5), regsrc1 : bits(5), regsrc2 : bits(5
 register bcatr_raw : bits(64) = 0x0000_0000_0000_0000
 register bdatr_raw : bits(64) = 0x0000_0000_0000_0000
 function bcatr_dr() -> bool = { bcatr_raw[26] == 0b1 }
-function bdatr_sat() -> bool = { bdatr_raw[31] == 0b1 }
+function bdatr_sat() -> bool = { bdatr_raw[26] == 0b1 }
+
+// -----------------------------------------------------------------------------
+// Tile-engine architectural effect envelope (PTO ISA 0.57.1 subset)
+//
+// The current Sail carrier does not yet contain a byte-addressable Tile payload
+// array.  These registers nevertheless model the architectural transaction:
+// decoded family/function and DataType, B.IOT legality/lifetime facts, complete
+// preflight, memory/Tile/implicit-ACC publication, and full-instruction retry.
+// Payload arithmetic remains a separately graded numeric-oracle gap.
+
+register tile_effect_pending : bool = false
+register tile_effect_family : bits(2) = 0b00 // 1=TMA, 2=CUBE
+register tile_effect_function : bits(5) = 0b00000
+register tile_effect_datatype : bits(5) = 0b00000
+register tile_effect_iot_count : bits(6) = 0b00_0000
+register tile_effect_source_count : bits(6) = 0b00_0000
+register tile_effect_output_count : bits(6) = 0b00_0000
+register tile_effect_release_count : bits(6) = 0b00_0000
+register tile_effect_iot_legal : bool = true
+register tile_effect_last_seen : bool = false
+register tile_effect_after_last : bool = false
+register tile_effect_access_set_valid : bool = true
+register tile_effect_fault_address : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_restart_pending : bool = false
+
+register tile_effect_commit_seq : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_preflight_seq : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_memory_seq : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_tile_seq : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_acc_seq : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_lifetime_releases : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_last_family : bits(2) = 0b00
+register tile_effect_last_function : bits(5) = 0b00000
+register tile_effect_last_datatype : bits(5) = 0b00000
+register tile_effect_last_masked : bool = false
+register tile_effect_last_mask_suppresses_access : bool = false
+register tile_effect_last_pad : bits(2) = 0b00
+register tile_effect_last_mx : bool = false
+register tile_effect_last_bias : bool = false
+register tile_effect_last_accumulate : bool = false
+register tile_effect_last_scale_a_rows : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_last_scale_a_cols : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_last_scale_b_rows : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_last_scale_b_cols : bits(64) = 0x0000_0000_0000_0000
+register tile_effect_last_scale_a_source : bits(6) = 0b00_0000
+register tile_effect_last_scale_b_source : bits(6) = 0b00_0000
+
+register tile_acc_valid : bool = false
+register tile_acc_datatype : bits(5) = 0b00000
+register tile_acc_rows : bits(64) = 0x0000_0000_0000_0000
+register tile_acc_cols : bits(64) = 0x0000_0000_0000_0000
+register tile_acc_k : bits(64) = 0x0000_0000_0000_0000
+
+function tile_effect_reset_descriptors() -> unit = {
+  tile_effect_iot_count = 0b00_0000;
+  tile_effect_source_count = 0b00_0000;
+  tile_effect_output_count = 0b00_0000;
+  tile_effect_release_count = 0b00_0000;
+  tile_effect_iot_legal = true;
+  tile_effect_last_seen = false;
+  tile_effect_after_last = false
+}
+
+function tile_effect_reset_arch() -> unit = {
+  tile_effect_pending = false;
+  tile_effect_family = 0b00;
+  tile_effect_function = 0b00000;
+  tile_effect_datatype = 0b00000;
+  tile_effect_reset_descriptors();
+  tile_effect_access_set_valid = true;
+  tile_effect_fault_address = sail_zeros(64);
+  tile_effect_restart_pending = false;
+  tile_effect_commit_seq = sail_zeros(64);
+  tile_effect_preflight_seq = sail_zeros(64);
+  tile_effect_memory_seq = sail_zeros(64);
+  tile_effect_tile_seq = sail_zeros(64);
+  tile_effect_acc_seq = sail_zeros(64);
+  tile_effect_lifetime_releases = sail_zeros(64);
+  tile_effect_last_family = 0b00;
+  tile_effect_last_function = 0b00000;
+  tile_effect_last_datatype = 0b00000;
+  tile_effect_last_masked = false;
+  tile_effect_last_mask_suppresses_access = false;
+  tile_effect_last_pad = 0b00;
+  tile_effect_last_mx = false;
+  tile_effect_last_bias = false;
+  tile_effect_last_accumulate = false;
+  tile_effect_last_scale_a_rows = sail_zeros(64);
+  tile_effect_last_scale_a_cols = sail_zeros(64);
+  tile_effect_last_scale_b_rows = sail_zeros(64);
+  tile_effect_last_scale_b_cols = sail_zeros(64);
+  tile_effect_last_scale_a_source = 0b00_0000;
+  tile_effect_last_scale_b_source = 0b00_0000;
+  tile_acc_valid = false;
+  tile_acc_datatype = 0b00000;
+  tile_acc_rows = sail_zeros(64);
+  tile_acc_cols = sail_zeros(64);
+  tile_acc_k = sail_zeros(64)
+}
+
+// False mask lanes are architecturally silent: no source read, memory access,
+// destination write, or fault check.  The bit result makes this contract easy
+// to exercise without pretending the model has a numeric Tile payload.
+function tile_mask_lane_effect(active : bool) -> bits(4) = {
+  if active then 0b1111 else 0b0000
+}
 
 // LCFR (core feature) (staged): only LaneNum is currently consulted.
 // LaneNum is encoded in LCFR[19:16] and represents log2(vec_length).
@@ -1549,28 +1660,29 @@ function template_integrity_assert_fail(reason : bits(8)) -> unit = {
 // - docs/bringup/plan/isa_clarifications.md
 //
 // MissingDescFamily IDs (TRAPARG0[7:0]):
-//   1=B.DIM, 2=B.TEXT, 3=B.ARG, 4=B.IOR, 5=B.IOT
+//   1=B.DIM, 2=B.TEXT, 3=B.DATR, 4=B.IOR, 5=B.IOT
 // MissingDetail (TRAPARG0[15:8]):
 //   0x00 missing, 0x01 invalid/out-of-range, 0x02 illegal combination
 
 register bdesc_seen_dim : bool = false
 register bdesc_seen_text : bool = false
-register bdesc_seen_arg : bool = false
+register bdesc_seen_datr : bool = false
 register bdesc_seen_ior : bool = false
 register bdesc_seen_iot : bool = false
 
 function bdesc_reset() -> unit = {
   bdesc_seen_dim = false;
   bdesc_seen_text = false;
-  bdesc_seen_arg = false;
+  bdesc_seen_datr = false;
   bdesc_seen_ior = false;
   bdesc_seen_iot = false;
-  clear_ri_bindings()
+  clear_ri_bindings();
+  tile_effect_reset_descriptors()
 }
 
 function bdesc_mark_dim() -> unit = { bdesc_seen_dim = true }
 function bdesc_mark_text() -> unit = { bdesc_seen_text = true }
-function bdesc_mark_arg() -> unit = { bdesc_seen_arg = true }
+function bdesc_mark_datr() -> unit = { bdesc_seen_datr = true }
 function bdesc_mark_ior() -> unit = { bdesc_seen_ior = true }
 function bdesc_mark_iot() -> unit = { bdesc_seen_iot = true }
 
@@ -1593,7 +1705,7 @@ function bdesc_illegal_combo_or_trap(family : bits(8), src_pc_or_tpc : bits(64))
 function bdesc_validate_header_end(src_pc_or_tpc : bits(64)) -> unit = {
   // Enforce mandatory descriptor families per tile/vector block type.
   // If multiple are missing, report exactly one using the priority order:
-  //   B.ARG > B.TEXT > B.IOT > B.IOR > B.DIM
+  //   B.DATR > B.TEXT > B.IOT > B.IOR > B.DIM
   let k = decoded_block_contract_kind();
   match k {
     // VEC: SIMT vector blocks (VPAR/VSEQ/MPAR/MSEQ): require DIM + TEXT.
@@ -1605,10 +1717,10 @@ function bdesc_validate_header_end(src_pc_or_tpc : bits(64)) -> unit = {
         vec_init_p_for_group(ssr_lc1)
       }
     },
-    // TMA: TLOAD/TSTORE: require ARG + IOR + IOT; TEXT illegal.
+    // TMA: require DATR + IOR + IOT; TEXT illegal.
     0b0010 => {
       if bdesc_seen_text then bdesc_illegal_combo_or_trap(0x02, src_pc_or_tpc)
-      else if not_bool(bdesc_seen_arg) then trap_blockfmt(0x03, 0x00, src_pc_or_tpc)
+      else if not_bool(bdesc_seen_datr) then trap_blockfmt(0x03, 0x00, src_pc_or_tpc)
       else if not_bool(bdesc_seen_iot) then trap_blockfmt(0x05, 0x00, src_pc_or_tpc)
       else if not_bool(bdesc_seen_ior) then trap_blockfmt(0x04, 0x00, src_pc_or_tpc)
       else ()
@@ -1619,21 +1731,19 @@ function bdesc_validate_header_end(src_pc_or_tpc : bits(64)) -> unit = {
       else if not_bool(bdesc_seen_iot) then trap_blockfmt(0x05, 0x00, src_pc_or_tpc)
       else ()
     },
-    // CUBE: require DIM + IOT + ARG; TEXT illegal.
+    // CUBE: require DIM + IOT + DATR; TEXT illegal.
     0b0100 => {
       if bdesc_seen_text then bdesc_illegal_combo_or_trap(0x02, src_pc_or_tpc)
-      else if not_bool(bdesc_seen_arg) then trap_blockfmt(0x03, 0x00, src_pc_or_tpc)
+      else if not_bool(bdesc_seen_datr) then trap_blockfmt(0x03, 0x00, src_pc_or_tpc)
       else if not_bool(bdesc_seen_iot) then trap_blockfmt(0x05, 0x00, src_pc_or_tpc)
       else if not_bool(bdesc_seen_dim) then trap_blockfmt(0x01, 0x00, src_pc_or_tpc)
       else ()
     },
-    // ACCCVT: require DIM + IOT + ARG + IOR; TEXT illegal.
+    // ACCCVT: require DATR + destination IOT; shape is inherited from ACC.
     0b0101 => {
       if bdesc_seen_text then bdesc_illegal_combo_or_trap(0x02, src_pc_or_tpc)
-      else if not_bool(bdesc_seen_arg) then trap_blockfmt(0x03, 0x00, src_pc_or_tpc)
+      else if not_bool(bdesc_seen_datr) then trap_blockfmt(0x03, 0x00, src_pc_or_tpc)
       else if not_bool(bdesc_seen_iot) then trap_blockfmt(0x05, 0x00, src_pc_or_tpc)
-      else if not_bool(bdesc_seen_ior) then trap_blockfmt(0x04, 0x00, src_pc_or_tpc)
-      else if not_bool(bdesc_seen_dim) then trap_blockfmt(0x01, 0x00, src_pc_or_tpc)
       else ()
     },
     // HDRDRV: header-driven engine ops: TEXT illegal; mandatory families are op-specific.
diff --git a/isa/sail/semantics_policy.json b/isa/sail/semantics_policy.json
index d2d793bd..e622602f 100644
--- a/isa/sail/semantics_policy.json
+++ b/isa/sail/semantics_policy.json
@@ -1,22 +1,6 @@
 {
   "default_status": "executable-subset",
   "form_overrides": {
-    "bstart_mgather_32_c9defbf18276": "decode-only",
-    "bstart_mgather_cas_32_fd8c8a3b720a": "decode-only",
-    "bstart_mgather_mask_32_5573241cd944": "decode-only",
-    "bstart_mscatter_32_0f0ba08bd798": "decode-only",
-    "bstart_mscatter_mask_32_2a33eed646f7": "decode-only",
-    "bstart_tgemv_32_ae19f5b678f5": "decode-only",
-    "bstart_tgemv_acc_32_9a471b21913e": "decode-only",
-    "bstart_tgemv_bias_32_186ee96c0a8b": "decode-only",
-    "bstart_tgemvmx_32_ae5e005f6589": "decode-only",
-    "bstart_tgemvmx_acc_32_368647b04bb0": "decode-only",
-    "bstart_tgemvmx_bias_32_d23011f15171": "decode-only",
-    "bstart_tmatmul_bias_32_4d5a498d12f3": "decode-only",
-    "bstart_tmatmulmx_32_e26cb3874648": "decode-only",
-    "bstart_tmatmulmx_acc_32_70fa59b0ab4c": "decode-only",
-    "bstart_tmatmulmx_bias_32_098c7efa51b0": "decode-only",
-    "bstart_tprefetch_32_d5f83e5aadf6": "decode-only",
     "dma_32_a168aeca5fa5": "decode-only"
   },
   "schema_version": "linx-sail-policy-v0.57.0"
diff --git a/isa/sail/semantics_status.json b/isa/sail/semantics_status.json
index e3df326a..54442110 100644
--- a/isa/sail/semantics_status.json
+++ b/isa/sail/semantics_status.json
@@ -48,35 +48,11 @@
       "mnemonic": "ASSERT",
       "status": "executable-subset"
     },
-    "b_arg_32_374ec956affe": {
-      "mnemonic": "B.ARG",
-      "status": "executable-subset"
-    },
-    "b_arg_32_47e8ac50ac96": {
-      "mnemonic": "B.ARG",
-      "status": "executable-subset"
-    },
-    "b_arg_32_5c8bfa662370": {
-      "mnemonic": "B.ARG",
-      "status": "executable-subset"
-    },
-    "b_arg_32_95152c29a268": {
-      "mnemonic": "B.ARG",
-      "status": "executable-subset"
-    },
-    "b_arg_32_c6d5c49a4ad7": {
-      "mnemonic": "B.ARG",
-      "status": "executable-subset"
-    },
-    "b_arg_32_f19d18f2126b": {
-      "mnemonic": "B.ARG",
-      "status": "executable-subset"
-    },
-    "b_catr_32_e90bd52fa480": {
+    "b_catr_32_8f94bdb16d29": {
       "mnemonic": "B.CATR",
       "status": "executable-subset"
     },
-    "b_datr_32_c161a042ff38": {
+    "b_datr_32_840f4b8d579d": {
       "mnemonic": "B.DATR",
       "status": "executable-subset"
     },
@@ -116,23 +92,23 @@
       "mnemonic": "B.IOR",
       "status": "executable-subset"
     },
-    "b_iot_32_10db6db84f5d": {
+    "b_iot_32_0f23e46d6176": {
       "mnemonic": "B.IOT",
       "status": "executable-subset"
     },
-    "b_iot_32_2c07e7177fad": {
+    "b_iot_32_3a6945dec034": {
       "mnemonic": "B.IOT",
       "status": "executable-subset"
     },
-    "b_iot_32_8b8bce6bffe8": {
+    "b_iot_32_778f84340400": {
       "mnemonic": "B.IOT",
       "status": "executable-subset"
     },
-    "b_iot_32_c11eb189dd83": {
+    "b_iot_32_a06b9b6c1965": {
       "mnemonic": "B.IOT",
       "status": "executable-subset"
     },
-    "b_iot_32_efa0fe3fe49a": {
+    "b_iot_32_f1ca66bbcce1": {
       "mnemonic": "B.IOT",
       "status": "executable-subset"
     },
@@ -200,14 +176,6 @@
       "mnemonic": "BSTART CALL",
       "status": "executable-subset"
     },
-    "bstart_cube_32_bd3f337acb9d": {
-      "mnemonic": "BSTART.CUBE",
-      "status": "executable-subset"
-    },
-    "bstart_fixp_32_3b0ae11126a6": {
-      "mnemonic": "BSTART.FIXP",
-      "status": "executable-subset"
-    },
     "bstart_fp_32_0c671a644214": {
       "mnemonic": "BSTART.FP",
       "status": "executable-subset"
@@ -238,15 +206,15 @@
     },
     "bstart_mgather_32_c9defbf18276": {
       "mnemonic": "BSTART.MGATHER",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_mgather_cas_32_fd8c8a3b720a": {
       "mnemonic": "BSTART.MGATHER.CAS",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_mgather_mask_32_5573241cd944": {
       "mnemonic": "BSTART.MGATHER.MASK",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_mpar_32_2d163417c615": {
       "mnemonic": "BSTART.MPAR",
@@ -254,11 +222,11 @@
     },
     "bstart_mscatter_32_0f0ba08bd798": {
       "mnemonic": "BSTART.MSCATTER",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_mscatter_mask_32_2a33eed646f7": {
       "mnemonic": "BSTART.MSCATTER.MASK",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_mseq_32_39343a456ec5": {
       "mnemonic": "BSTART.MSEQ",
@@ -296,33 +264,33 @@
       "mnemonic": "BSTART.SYS",
       "status": "executable-subset"
     },
-    "bstart_tepl_32_d022db6dacb3": {
+    "bstart_tepl_32_bff5143d4fe3": {
       "mnemonic": "BSTART.TEPL",
       "status": "executable-subset"
     },
     "bstart_tgemv_32_ae19f5b678f5": {
       "mnemonic": "BSTART.TGEMV",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tgemv_acc_32_9a471b21913e": {
       "mnemonic": "BSTART.TGEMV.ACC",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tgemv_bias_32_186ee96c0a8b": {
       "mnemonic": "BSTART.TGEMV.BIAS",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tgemvmx_32_ae5e005f6589": {
       "mnemonic": "BSTART.TGEMVMX",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tgemvmx_acc_32_368647b04bb0": {
       "mnemonic": "BSTART.TGEMVMX.ACC",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tgemvmx_bias_32_d23011f15171": {
       "mnemonic": "BSTART.TGEMVMX.BIAS",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tload_32_d0c18bb0ab15": {
       "mnemonic": "BSTART.TLOAD",
@@ -338,19 +306,19 @@
     },
     "bstart_tmatmul_bias_32_4d5a498d12f3": {
       "mnemonic": "BSTART.TMATMUL.BIAS",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tmatmulmx_32_e26cb3874648": {
       "mnemonic": "BSTART.TMATMULMX",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tmatmulmx_acc_32_70fa59b0ab4c": {
       "mnemonic": "BSTART.TMATMULMX.ACC",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tmatmulmx_bias_32_098c7efa51b0": {
       "mnemonic": "BSTART.TMATMULMX.BIAS",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tmov_32_211446509efb": {
       "mnemonic": "BSTART.TMOV",
@@ -358,7 +326,7 @@
     },
     "bstart_tprefetch_32_d5f83e5aadf6": {
       "mnemonic": "BSTART.TPREFETCH",
-      "status": "decode-only"
+      "status": "executable-subset"
     },
     "bstart_tstore_32_4048b6e8b0f4": {
       "mnemonic": "BSTART.TSTORE",
@@ -3077,6 +3045,6 @@
       "status": "executable-subset"
     }
   },
-  "schema_version": "linx-sail-status-v0.57.0",
-  "spec_version": "0.57.0"
+  "schema_version": "linx-sail-status-v0.57.1",
+  "spec_version": "0.57.1"
 }
diff --git a/isa/sail/tests/directed.sail b/isa/sail/tests/directed.sail
index cbd6b65b..af41e0b5 100644
--- a/isa/sail/tests/directed.sail
+++ b/isa/sail/tests/directed.sail
@@ -30,6 +30,18 @@ function reset_fused_call_case(base_pc : bits(64), ra_seed : bits(64)) -> unit =
   bdesc_reset()
 }
 
+function reset_tile_effect_case() -> unit = {
+  tile_effect_reset_arch();
+  bdesc_reset();
+  bcatr_raw = sail_zeros(64);
+  bdatr_raw = sail_zeros(64);
+  ssr_lb0 = 0x0000_0000_0000_0002;
+  ssr_lb1 = 0x0000_0000_0000_0003;
+  ssr_lb2 = 0x0000_0000_0000_0041;
+  last_trapnum = sail_zeros(6);
+  block_marker_strict = false
+}
+
 function main() : unit -> unit = {
   // SrcRType arithmetic codes are 00=.sw, 01=.uw, 10=.neg, 11=none.
   assert(apply_srcrtype_arith64(0b00, 0x1234_5678_8000_0001) == 0xFFFF_FFFF_8000_0001);
@@ -124,15 +136,14 @@ function main() : unit -> unit = {
   exec_c_setret(0b00101);
   assert(read_reg5(0b01010) == 0x0000_0000_0000_100A);
 
-  // Retired B.IOD encoding space must trap as illegal; the old PAR spelling is
-  // not represented in Sail and its bit pattern decodes as canonical TEPL.
+  // Retired B.IOD and legacy BSTART.PAR encoding space must trap as illegal;
+  // neither spelling or bit pattern canonical-redecodes in PTO ISA 0.57.1.
   last_trapnum = sail_zeros(6);
   decode_execute32(0x0000_1013);
   assert(last_trapnum == trapnum_illegal_inst());
   last_trapnum = sail_zeros(6);
   decode_execute32(0x0200_1181);
-  assert(last_trapnum == sail_zeros(6));
-  assert(barg_block_type_cur == 0b1101);
+  assert(last_trapnum == trapnum_illegal_inst());
 
   // Trap records retain precise source state and the block-interrupted bit.
   trap_block_cfi(0x1, 0xCAFE_BABE_DEAD_BEEF);
@@ -155,5 +166,123 @@ function main() : unit -> unit = {
   assert(fp32_eq(0x0000_0000, 0x8000_0000));
   assert(fp32_class_mask(0x7F80_0000) == 0x0000_0080);
   assert(fp64_is_nan(0x7FF8_0000_0000_0001));
-  assert(fp64_eq(0x0000_0000_0000_0000, 0x8000_0000_0000_0000))
+  assert(fp64_eq(0x0000_0000_0000_0000, 0x8000_0000_0000_0000));
+
+  // PTO 0.57.1 differential operand maps match the frozen catalog/QEMU
+  // function identities, including implicit ACC and MX scale operands.
+  assert(tile_tma_required_sources(0b00100) == 0b00_0001);
+  assert(tile_tma_required_sources(0b00110) == 0b00_0010);
+  assert(tile_tma_required_sources(0b00101) == 0b00_0010);
+  assert(tile_tma_required_sources(0b00111) == 0b00_0011);
+  assert(tile_tma_required_sources(0b01000) == 0b00_0011);
+  assert(tile_cube_required_sources(0b10000) == 0b00_0010);
+  assert(tile_cube_required_sources(0b10001) == 0b00_0011);
+  assert(tile_cube_required_sources(0b10100) == 0b00_0100);
+  assert(tile_cube_required_sources(0b10101) == 0b00_0101);
+  assert(tile_cube_required_sources(0b10110) == 0b00_0100);
+  assert(tile_mask_lane_effect(false) == 0b0000);
+  assert(tile_mask_lane_effect(true) == 0b1111);
+
+  // Positive masked gather: one descriptor carries indices+mask and one
+  // destination.  Only a successful complete preflight publishes effects and
+  // last-use releases; false mask lanes are recorded as access-suppressing.
+  reset_tile_effect_case();
+  bdesc_mark_datr();
+  bdesc_mark_ior();
+  bdatr_raw = 0x0000_0000_0800_0000; // PadValue=01
+  decoded_tile_datatype_shadow = 0b00001;
+  tile_effect_begin(0b01, 0b00110);
+  tile_effect_append_iot(0x0000_0000_0819_C013);
+  assert(tile_effect_finalize());
+  assert(tile_effect_commit_seq == 0x0000_0000_0000_0001);
+  assert(tile_effect_memory_seq == 0x0000_0000_0000_0001);
+  assert(tile_effect_tile_seq == 0x0000_0000_0000_0001);
+  assert(tile_effect_lifetime_releases == 0x0000_0000_0000_0002);
+  assert(tile_effect_last_masked);
+  assert(tile_effect_last_mask_suppresses_access);
+  assert(tile_effect_last_pad == 0b01);
+
+  // Negative/retry path: a failed full access-set preflight reports the first
+  // original address and commits no memory, Tile, ACC, or lifetime effect.
+  reset_tile_effect_case();
+  bdesc_mark_datr();
+  bdesc_mark_ior();
+  decoded_tile_datatype_shadow = 0b00001;
+  tile_effect_begin(0b01, 0b00100);
+  tile_effect_append_iot(0x0000_0000_0019_D013); // one source + dst, size=3
+  tile_effect_access_set_valid = false;
+  tile_effect_fault_address = 0x0000_0000_DEAD_0040;
+  assert(not_bool(tile_effect_finalize()));
+  assert(tile_effect_pending);
+  assert(tile_effect_restart_pending);
+  assert(tile_effect_commit_seq == 0x0000_0000_0000_0000);
+  assert(tile_effect_memory_seq == 0x0000_0000_0000_0000);
+  assert(tile_effect_tile_seq == 0x0000_0000_0000_0000);
+  assert(tile_effect_lifetime_releases == 0x0000_0000_0000_0000);
+  assert(last_trapnum == trapnum_data_page_fault());
+  assert(last_traparg0 == 0x0000_0000_DEAD_0040);
+  tile_effect_access_set_valid = true;
+  assert(tile_effect_finalize());
+  assert(tile_effect_commit_seq == 0x0000_0000_0000_0001);
+  assert(tile_effect_memory_seq == 0x0000_0000_0000_0001);
+  assert(tile_effect_tile_seq == 0x0000_0000_0000_0001);
+
+  // TPREFETCH performs the same complete address/translation preflight but is
+  // destination-free and publishes no memory-data or Tile payload effect.
+  reset_tile_effect_case();
+  bdesc_mark_datr();
+  bdesc_mark_ior();
+  decoded_tile_datatype_shadow = 0b00001;
+  tile_effect_begin(0b01, 0b00011);
+  assert(tile_effect_finalize());
+  assert(tile_effect_preflight_seq == 0x0000_0000_0000_0001);
+  assert(tile_effect_memory_seq == 0x0000_0000_0000_0000);
+  assert(tile_effect_tile_seq == 0x0000_0000_0000_0000);
+
+  // MX+BIAS uses authored source order A,B,ScaleA,ScaleB,Bias.  E8M0 scales
+  // cover ceil(K/32)=3 groups for K=65 and ordinary/MX writes implicit ACC.
+  reset_tile_effect_case();
+  bdesc_mark_datr();
+  bdesc_mark_dim();
+  decoded_tile_datatype_shadow = 0b00001; // FP32 header/ACC for MX
+  tile_effect_begin(0b10, 0b10101);
+  tile_effect_append_iot(0x0000_0000_0810_4013);
+  tile_effect_append_iot(0x0000_0000_1030_4013);
+  tile_effect_append_iot(0x0000_0000_0058_5013);
+  assert(tile_effect_finalize());
+  assert(tile_acc_valid);
+  assert(tile_effect_acc_seq == 0x0000_0000_0000_0001);
+  assert(tile_effect_last_mx);
+  assert(tile_effect_last_bias);
+  assert(tile_effect_last_scale_a_rows == 0x0000_0000_0000_0002);
+  assert(tile_effect_last_scale_a_cols == 0x0000_0000_0000_0003);
+  assert(tile_effect_last_scale_b_rows == 0x0000_0000_0000_0003);
+  assert(tile_effect_last_scale_b_cols == 0x0000_0000_0000_0003);
+  assert(tile_effect_last_scale_a_source == 0b00_0010);
+  assert(tile_effect_last_scale_b_source == 0b00_0011);
+
+  // .ACC is implicit: it has no B.IOT pseudo-destination and must preserve the
+  // prior accumulator on descriptor/shape failure, then update it on success.
+  reset_tile_effect_case();
+  bdesc_mark_datr();
+  bdesc_mark_dim();
+  decoded_tile_datatype_shadow = 0b00001;
+  tile_effect_begin(0b10, 0b10010);
+  tile_effect_append_iot(0x0000_0000_0818_4013);
+  assert(not_bool(tile_effect_finalize()));
+  assert(tile_effect_acc_seq == 0x0000_0000_0000_0000);
+  assert(not_bool(tile_acc_valid));
+  tile_effect_pending = false;
+  tile_effect_restart_pending = false;
+  tile_effect_reset_descriptors();
+  tile_effect_begin(0b10, 0b10000);
+  tile_effect_append_iot(0x0000_0000_0818_4013);
+  assert(tile_effect_finalize());
+  assert(tile_acc_valid);
+  tile_effect_reset_descriptors();
+  tile_effect_begin(0b10, 0b10010);
+  tile_effect_append_iot(0x0000_0000_0818_4013);
+  assert(tile_effect_finalize());
+  assert(tile_effect_acc_seq == 0x0000_0000_0000_0002);
+  assert(tile_effect_last_accumulate)
 }
diff --git a/isa/v0.57/encoding/fields.json b/isa/v0.57/encoding/fields.json
index 227d10dd..cc52a7a5 100644
--- a/isa/v0.57/encoding/fields.json
+++ b/isa/v0.57/encoding/fields.json
@@ -7,7 +7,7 @@
     "CMode": {"widths": [3], "namespace": "selector", "reserved_values": []},
     "CROSS-BID": {"widths": [7], "namespace": "register-or-identifier"},
     "DR": {"widths": [1], "namespace": "operand"},
-    "DataLayout": {"widths": [5], "namespace": "selector", "reserved_values": []},
+    "Canonicalize": {"widths": [1], "namespace": "operand"},
     "DataType": {"widths": [5], "namespace": "selector", "reserved_values": []},
     "DstBegin": {"widths": [5], "namespace": "register-or-identifier"},
     "DstEnd": {"widths": [5], "namespace": "register-or-identifier"},
@@ -16,11 +16,12 @@
     "Function": {"widths": [5], "namespace": "selector", "reserved_values": []},
     "L": {"widths": [1], "namespace": "operand"},
     "L/UL": {"widths": [1], "namespace": "operand"},
+    "Layout": {"widths": [5], "namespace": "selector", "reserved_values": [2, 5, 7, 10, 11, 12, 13, 14, 15, 16, 19, 21, 22, 23, 24, 25, 26, 29, 31]},
     "LSR_ID": {"widths": [12], "namespace": "register-or-identifier"},
     "LoopNest": {"widths": [2, 3], "namespace": "selector", "reserved_values": []},
     "Mode": {"widths": [2], "namespace": "selector", "reserved_values": []},
     "PRED_IMM": {"widths": [4], "namespace": "immediate", "signed": false, "scale": 1},
-    "PadValue": {"widths": [5], "namespace": "operand"},
+    "PadValueOrByteId": {"widths": [2], "namespace": "operand"},
     "RMode": {"widths": [3], "namespace": "selector", "reserved_values": []},
     "RRA_Type": {"widths": [4], "namespace": "selector", "reserved_values": []},
     "RST_Type": {"widths": [4], "namespace": "selector", "reserved_values": []},
@@ -50,13 +51,11 @@
     "SrcTile1": {"widths": [6], "namespace": "register-or-identifier"},
     "SrcType": {"widths": [2, 5], "namespace": "selector", "reserved_values": []},
     "SrcZero": {"widths": [5], "namespace": "register-or-identifier"},
-    "TileOpcode": {"widths": [10], "namespace": "selector", "reserved_values": [], "reserved_ranges": [[73, 127], [140, 191], [201, 223], [228, 1023]], "description": "The v0.57 TEPL selector field remains 10 bits. Selectors 0x000-0x02A preserve established identities; 0x02B-0x048, 0x080-0x08B, 0x0C0-0x0C8, and 0x0E0-0x0E3 are allocated by the reviewed v0.57 TEPL map; all other values are reserved."},
     "V": {"widths": [1], "namespace": "operand"},
     "aq": {"widths": [1], "namespace": "operand"},
     "atom": {"widths": [1], "namespace": "operand"},
     "e": {"widths": [1], "namespace": "operand"},
     "far": {"widths": [1], "namespace": "operand"},
-    "format": {"widths": [5], "namespace": "selector", "reserved_values": []},
     "h": {"widths": [1], "namespace": "operand"},
     "i": {"widths": [1], "namespace": "operand"},
     "imm": {"widths": [7, 32], "namespace": "immediate", "signed": false, "scale": 1},
diff --git a/isa/v0.57/encoding/retired_encodings.json b/isa/v0.57/encoding/retired_encodings.json
index 8f184c1b..5d072b64 100644
--- a/isa/v0.57/encoding/retired_encodings.json
+++ b/isa/v0.57/encoding/retired_encodings.json
@@ -8,16 +8,31 @@
       "retired_mnemonic": "B.IOD"
     },
     {
-      "disposition": "canonical-redecode",
+      "disposition": "reserved",
       "length_bits": 32,
       "mask": "0x06007fff",
       "match": "0x02001181",
-      "replacement_mnemonic": "BSTART.TEPL",
       "retired_mnemonic": "BSTART.PAR"
     }
   ],
+  "deleted_tile_names": [
+    "TADDC",
+    "TADDSC",
+    "TFMA",
+    "TFMOD",
+    "TFMODS",
+    "TLRELU",
+    "TRANDOM",
+    "TSUBC",
+    "TSUBSC"
+  ],
+  "migration_only_source_aliases": {
+    "TSORT32": "TSORT",
+    "TTRANSPOSE": "TTRANS"
+  },
   "notes": [
     "Retired spellings are assembler errors.",
-    "B.IOD's bit pattern is reserved. The former BSTART.PAR bit pattern remains active only as BSTART.TEPL."
+    "B.IOD and the former BSTART.PAR/legacy-TEPL bit pattern are reserved and must not canonical-redecode.",
+    "Deleted tile operation selectors remain unallocated in the PTO ISA 0.57.1 TEPL Mode/Function map."
   ]
 }
diff --git a/isa/v0.57/linxisa-v0.57.json b/isa/v0.57/linxisa-v0.57.json
index 3110cb7c..1a1382a3 100644
--- a/isa/v0.57/linxisa-v0.57.json
+++ b/isa/v0.57/linxisa-v0.57.json
@@ -1 +1 @@
-{"field_definitions":{"fields":{"ACR-ID":{"namespace":"register-or-identifier","widths":[10]},"B/E":{"namespace":"operand","widths":[1]},"BrType":{"namespace":"selector","reserved_values":[],"widths":[3]},"C":{"namespace":"operand","widths":[1]},"CMode":{"namespace":"selector","reserved_values":[],"widths":[3]},"CROSS-BID":{"namespace":"register-or-identifier","widths":[7]},"DR":{"namespace":"operand","widths":[1]},"DataLayout":{"namespace":"selector","reserved_values":[],"widths":[5]},"DataType":{"namespace":"selector","reserved_values":[],"widths":[5]},"DstBegin":{"namespace":"register-or-identifier","widths":[5]},"DstEnd":{"namespace":"register-or-identifier","widths":[5]},"DstTile":{"namespace":"register-or-identifier","widths":[3]},"DstType":{"namespace":"selector","reserved_values":[],"widths":[5]},"Function":{"namespace":"selector","reserved_values":[],"widths":[5]},"L":{"namespace":"operand","widths":[1]},"L/UL":{"namespace":"operand","widths":[1]},"LSR_ID":{"namespace":"register-or-identifier","widths":[12]},"LoopNest":{"namespace":"selector","reserved_values":[],"widths":[2,3]},"Mode":{"namespace":"selector","reserved_values":[],"widths":[2]},"PRED_IMM":{"namespace":"immediate","scale":1,"signed":false,"widths":[4]},"PadValue":{"namespace":"operand","widths":[5]},"RMode":{"namespace":"selector","reserved_values":[],"widths":[3]},"RRA_Type":{"namespace":"selector","reserved_values":[],"widths":[4]},"RST_Type":{"namespace":"selector","reserved_values":[],"widths":[4]},"RegDst":{"namespace":"register-or-identifier","widths":[5]},"RegDst0":{"namespace":"register-or-identifier","widths":[5]},"RegDst1":{"namespace":"register-or-identifier","widths":[5]},"RegSrc":{"namespace":"register-or-identifier","widths":[5]},"RegSrc0":{"namespace":"register-or-identifier","widths":[5]},"RegSrc1":{"namespace":"register-or-identifier","widths":[5]},"RegSrc2":{"namespace":"register-or-identifier","widths":[5]},"S0R":{"namespace":"operand","widths":[1]},"S1R":{"namespace":"operand","widths":[1]},"SSRID":{"namespace":"register-or-identifier","widths":[5]},"SSR_ID":{"namespace":"register-or-identifier","widths":[12,24]},"SUCC_IMM":{"namespace":"immediate","scale":1,"signed":false,"widths":[4]},"Sat":{"namespace":"operand","widths":[1]},"SrcA":{"namespace":"register-or-identifier","widths":[5]},"SrcBegin":{"namespace":"register-or-identifier","widths":[5]},"SrcD":{"namespace":"register-or-identifier","widths":[5]},"SrcD1":{"namespace":"register-or-identifier","widths":[5]},"SrcEnd":{"namespace":"register-or-identifier","widths":[5]},"SrcL":{"namespace":"register-or-identifier","widths":[5]},"SrcP":{"namespace":"register-or-identifier","widths":[5]},"SrcR":{"namespace":"register-or-identifier","widths":[5]},"SrcRType":{"namespace":"selector","reserved_values":[],"widths":[2]},"SrcTile0":{"namespace":"register-or-identifier","widths":[6]},"SrcTile1":{"namespace":"register-or-identifier","widths":[6]},"SrcType":{"namespace":"selector","reserved_values":[],"widths":[2,5]},"SrcZero":{"namespace":"register-or-identifier","widths":[5]},"TileOpcode":{"description":"The v0.57 TEPL selector field remains 10 bits. Selectors 0x000-0x02A preserve established identities; 0x02B-0x048, 0x080-0x08B, 0x0C0-0x0C8, and 0x0E0-0x0E3 are allocated by the reviewed v0.57 TEPL map; all other values are reserved.","namespace":"selector","reserved_ranges":[[73,127],[140,191],[201,223],[228,1023]],"reserved_values":[],"widths":[10]},"V":{"namespace":"operand","widths":[1]},"aq":{"namespace":"operand","widths":[1]},"atom":{"namespace":"operand","widths":[1]},"e":{"namespace":"operand","widths":[1]},"far":{"namespace":"operand","widths":[1]},"format":{"namespace":"selector","reserved_values":[],"widths":[5]},"h":{"namespace":"operand","widths":[1]},"i":{"namespace":"operand","widths":[1]},"imm":{"namespace":"immediate","scale":1,"signed":false,"widths":[7,32]},"imm20":{"namespace":"immediate","scale":1,"signed":false,"widths":[20]},"imm32":{"namespace":"immediate","scale":1,"signed":false,"widths":[32]},"imm4":{"namespace":"immediate","scale":1,"signed":false,"widths":[4]},"imm5":{"namespace":"immediate","scale":1,"signed":false,"widths":[5]},"imm8":{"namespace":"immediate","scale":1,"signed":false,"widths":[8]},"imml":{"namespace":"immediate","scale":1,"signed":false,"widths":[6]},"immr":{"namespace":"immediate","scale":1,"signed":false,"widths":[6]},"imms":{"namespace":"immediate","scale":1,"signed":false,"widths":[6]},"model":{"namespace":"selector","reserved_values":[],"widths":[5]},"prefetch_size":{"namespace":"immediate","scale":1,"signed":false,"widths":[12]},"r":{"namespace":"operand","widths":[1]},"rd":{"namespace":"operand","widths":[1]},"reserve":{"allowed_values":[0],"description":"Legacy source notation for reserved bit ranges. Active opcode patterns encode these ranges as fixed zero constants.","documented_only":true,"namespace":"reserved","widths":[11,16,17]},"rl":{"namespace":"operand","widths":[1]},"s":{"namespace":"operand","widths":[1]},"shamt":{"namespace":"immediate","scale":1,"signed":false,"widths":[5,6,7]},"simm":{"namespace":"immediate","scale":1,"signed":true,"widths":[17,25,29]},"simm12":{"namespace":"immediate","scale":1,"signed":true,"widths":[12]},"simm17":{"namespace":"immediate","scale":1,"signed":true,"widths":[17]},"simm22":{"namespace":"immediate","scale":1,"signed":true,"widths":[22]},"simm24":{"namespace":"immediate","scale":1,"signed":true,"widths":[12,24]},"simm25":{"namespace":"immediate","scale":1,"signed":true,"widths":[25]},"simm32":{"namespace":"immediate","scale":1,"signed":true,"widths":[32]},"simm5":{"namespace":"immediate","scale":1,"signed":true,"widths":[5]},"temp":{"namespace":"selector","reserved_values":[],"widths":[2]},"trap":{"namespace":"operand","widths":[1]},"uimm":{"namespace":"immediate","scale":1,"signed":false,"widths":[12]},"uimm12":{"namespace":"immediate","scale":1,"signed":false,"widths":[12]},"uimm17":{"namespace":"immediate","scale":1,"signed":false,"widths":[17]},"uimm19":{"namespace":"immediate","scale":1,"signed":false,"widths":[19]},"uimm24":{"namespace":"immediate","scale":1,"signed":false,"widths":[24]},"uimm32":{"namespace":"immediate","scale":1,"signed":false,"widths":[32]},"uimm5":{"namespace":"immediate","scale":1,"signed":false,"widths":[5]}},"notes":["This checked-in table is the complete field contract for opcodes/*.opc; missing and unknown entries are errors. The documented-only reserve entry records legacy source widths after active patterns were hardened to fixed zero constants.","Widths are verified against encoded pieces. Immediate signedness and the default encoded-unit scale are explicit; instruction semantics may apply an additional form-specific scale such as the halfword PC-relative convention.","Selector reserved_values and reserved_ranges enumerate rejected selector codes when known. Reserved fields declare their canonical allowed_values; reserve accepts only zero."]},"instruction_count":769,"instructions":[{"asm":"acrc rst_type","encoding":{"length_bits":32,"parts":[{"fields":[{"name":"RST_Type","pieces":[{"insn_lsb":20,"insn_msb":23,"token":"RST_Type","width":4}],"signed":null}],"index":0,"mask":"0xff0fffff","match":"0x0000302b","pattern":"00000000....00000011000000101011","width_bits":32}]},"encoding_kind":"L32","group":"Execution Control","id":"acrc_32_a9c0e33f9904","length_bits":32,"mnemonic":"ACRC","parts":[{"segments":[{"const":{"value":0,"width":4},"lsb":28,"msb":31,"token":"4'b0000","width":4},{"const":{"value":0,"width":4},"lsb":24,"msb":27,"token":"4'b0000","width":4},{"lsb":20,"msb":23,"token":"RST_Type","width":4},{"const":{"value":0,"width":5},"lsb":15,"msb":19,"token":"5'b0_0000","width":5},{"const":{"value":3,"width":3},"lsb":12,"msb":14,"token":"3'b011","width":3},{"const":{"value":0,"width":5},"lsb":7,"msb":11,"token":"5'b0_0000","width":5},{"const":{"value":2,"width":3},"lsb":4,"msb":6,"token":"3'b010","width":3},{"const":{"value":5,"width":3},"lsb":1,"msb":3,"token":"3'b101","width":3},{"const":{"value":1,"width":1},"lsb":0,"msb":0,"token":"1","width":1}],"width_bits":32}],"source":{"file":"opcodes/lx_32.opc","line":11},"uid":"a9c0e33f9904","uop_big_kind":"SYS","uop_class":{"note":"User confirmed A","source":"group_rule","uop_kind":"SYS"},"uop_group":"SYS"},{"asm":"acre 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producer transaction bases, status, and AckID remain independent","producer_bases_coalesce":false,"stale_ack_rule":"wrong producer, sequence, operation/scope, match, directory, owner, or status-generation is rejected; identical terminal AckID retransmission is idempotent","status_rules":["each state transition increments status_generation","matching post-seal transactions independently record DEFERRED_ACTIVE","FINAL creates one RELEASED_AFTER_FINAL per pending match","fatal release creates one RELEASED_AFTER_ABORT per pending match","post-release admission performs a new lookup at new directory generation"],"terminal_kinds":["NO_MATCH","CANCELED_PRE_EVENT","RELEASED_AFTER_FINAL","RELEASED_AFTER_ABORT"],"terminal_rules":["NO_MATCH after lookup at the transaction directory generation for nonmatches","CANCELED_PRE_EVENT only after cancellation prevents stale event-zero seal","DEFERRED_ACTIVE recorded independently for each post-seal match and is nonterminal","RELEASED_AFTER_FINAL created atomically by FINAL per pending match","RELEASED_AFTER_ABORT created atomically by fatal release per pending match after quiescence","post-release admission performs a new lookup at the new directory generation and normally receives NO_MATCH"],"txn_base_fields":["producer_domain","producer_kind","producer_lxcpu_id","producer_context_generation","producer_pe_id","producer_stid_valid","producer_stid","producer_tid_valid","producer_engine_local_tid","producer_endpoint_id","transaction_sequence_value","transaction_sequence_wrap_or_generation","architectural_operation","exact_operation_scope"],"txn_id_fields":["complete InvalidationTxnBase","matched_LeaseID_or_explicit_NO_LEASE","lease_directory_generation_at_lookup","status_generation"]},"lease_id":["lease_generation","validation_generation","validation_token_hash","exact_vtgt_TemplateOwnerID","exact_vload_TemplateOwnerID_or_canonical_invalid","retained_target_mapping_visibility_share_domain_key"],"legality":{"fret_ra_target":"fixed pre-restore R10","fret_stk_stack_slot_zero":{"device_mmio_or_mixed_or_non_idempotent":"phase_zero E_DATA/MMU_PERM before any cache, fabric, device, or MMIO physical read","required_memory_type":"Normal","requires_idempotent":true},"fret_stk_target":"fixed R10 restored from slot zero","malformed_effects":"zero template effect","pre_effect_checks":["well_formed_endpoints","sufficient_F_pre_effect","FRET.STK_Begin_is_R10"]},"phase_fault_envelopes":{"phase_one_recoverable":{"acre_restore":"retry exactly saved event; do not reissue VLOAD, reacquire lease, or repeat earlier events","bi":1,"dirty":1,"prior_events":"remain_visible","redo_ok":0,"resume_ok":1,"step_index":"faulting_or_next_uncommitted_event"},"phase_zero":{"bi":0,"dirty":0,"phase":0,"redo_ok":1,"resume_ok":0,"step_index":0,"template_effect":"none"},"post_seal_fatal":{"argv":1,"bi":1,"cause":0,"dirty":1,"e":0,"redo_ok":0,"resume_ok":0,"reuse_boundary":"platform reset only","traparg0":"source template PC/TPC","trapnum":"ASSERT_FAIL (52)"}},"profile":"v0.57 range-mode frame templates","register_ring":{"allows_full_ring":true,"allows_singleton":true,"allows_wrap":true,"inclusive_range":[2,23]},"seal_and_recovery":{"after_seal_invalidation":"lease wins; producer completion waits through traps, ACRE, suspension, FINAL, or fatal release","before_seal_invalidation":"wins and cancels phase zero with no effect","ebstate_recoverable_retention":["exact TemplateOwnerID","phase and StepIndex cursors","sealed VLOAD state when applicable","validation token","retained lease","complete pending InvalidationTxnID/status set"],"ebstate_retention_forbidden":["renumber pending invalidation entries","merge pending invalidation entries","reacquire lease entries","restore a pre-template checkpoint"],"event_zero_seal_transaction":["recheck_all_identities_and_generations","acquire_complete_FRET_lease","retire_successful_validation_rows_with_distinct_traces","commit_event_zero","advance_StepIndex_0_to_1"],"final":"qualifies full token, performs boundary transfer/retirement, and releases lease atomically","final_identity":{"required_matches":["group","checkpoint","template","validation","lease","VTGT key","VLOAD key or canonical invalid","visibility/share-domain","FINAL RID/slot/generation","final ordinal"],"shortcut_authority_forbidden":["queue head","BID","RID value","PC","opcode","hash alone"]},"lease_directory_suspend_rule":"lease directory retains discoverability during suspension; a manager must resume through FINAL or choose fatal abandonment and cannot wait on its own deferred invalidation","rollback_after_seal":"forbidden for SP, GPR, memory, target, progress, and trace effects"},"source_contract":"R975 Template Fatal-State and Canonical Identity Contract","step_index":{"event_effect_and_cursor_advance":"atomic","meaning":"next_uncommitted_phase_one_event"},"target_proof":{"actual_current_marker_proof":"required before every FRET effect","coherent_marker_provenance_cache":"legal only when it proves the same target marker bytes, address-space state, code-visibility epoch, and invalidation scope as an actual current marker proof","deferred_demand_paging":"qualified only while every FRET effect remains withheld","fault_owner":"VTGT owns translation, execute-permission, marker, and CFI faults","metadata_only_continuation_or_fallthrough":"non-conforming compatibility; must be rejected"},"template_integrity_fail":{"acre_continuation_allowed":false,"cause":0,"fatal_reasons":{"0":"explicit abandonment","1":"dirty-template RRAT_DEFAULT","2":"sealed-VLOAD replay/withdrawal","3":"poisoned response/token","4":"exact-live ownership/generation/lease/FINAL contradiction","5":"suspended drain failure","6..255":"reserved"},"fatal_teardown_order":["stop source-context issue, commit, wakeup, redirect, FINAL transfer, and new lease acquisition","snapshot exact envelope, state, owner, token, and pending transactions","advance template, row, and load generations","cancel every uncommitted row and request","invalidate VLOAD data, VTGT proof, token, and queued transfer","obtain quiescence from every listed owner before releasing the lease","atomically release the lease and create one RELEASED_AFTER_ABORT per pending matching invalidation","publish the fatal record for managing-ring inspection"],"fixup_allowed":false,"maskable_by_ECONFIG3":false,"quiescence_owners":["ROB","LSU","target-validation","block-control","recovery","trace","redirect/transfer","lease-directory"],"release_ack":"one RELEASED_AFTER_ABORT per pending matching invalidation after quiescence","reset_only":true,"reset_reuse":{"global_quiescence_before_reset":true,"new_context_generation_required":true,"no_pre_reset_ack_after_new_context_generation":true,"platform_reset_only":true,"pre_template_state_restore":"forbidden"},"trapnum":"ASSERT_FAIL (52)"},"template_owner_id":{"equality":"all fields participate; mismatch is never alias","exact_live_post_seal_contradiction":"template_integrity_fail FatalReason=4","field_groups":{"group":["bid","bid_robid(valid,wrap,value)","gid","gid_robid(valid,wrap,value)","group_base_rid","group_base_rid_robid(valid,wrap,value)","group_base_rob_slot","group_row_count","checkpoint_id","template_generation","source_pc","source_raw","form_id","encoded_N"],"memory":["lsid_valid","lsid_value","lsid_wrap_or_generation","load_id_valid","load_id_value","load_id_generation","load_replay_generation","store_id_valid","store_id_value","store_id_generation"],"placement":["lxcpu_id","lxcpu_context_generation","pe_id","stid","engine_local_tid"],"row":["row_present","row_kind","child_ordinal","rid","rid_robid(valid,wrap,value)","rob_slot","row_generation"]},"late_mismatch":"reject without live mutation","reuse_rule":"advance applicable ROBID wrap or template/row/LSID/load/store generation before numeric reuse"},"vload":{"eligible_memory":"complete eight-byte Normal and explicitly idempotent","forbidden_memory_zero_read":["Device/MMIO","mixed_type","unspecified_non_idempotent"],"identity_fields":["owner_key","VA","translation_generation","permission_type_generation","LSID","load_id","older_store_forwarding_state","response_source","miss_refill_coherence_generation","load_generation","data"],"lifecycle":["EMPTY","ISSUED","RESPONDED","ORDER_QUALIFIED","TARGET_VALIDATED","EVENT0_SEALED"],"post_seal_replacement":"forbidden; enters template_integrity_fail FatalReason=2","pre_seal_replay_action":["advance_load_generation","discard_value_vtgt_proof_and_lease_candidate","reject_late_old_generation_responses","rerun_VTGT_even_if_data_bit_identical"],"sampling_point":"event_zero_seal"}},"immediate_materialization":{"description":"Constant materialization conventions.","hl_lis":{"imm_kind":"signed","rule":"Write(RegDst, SignExtend(imm32))"},"hl_liu":{"imm_kind":"unsigned","rule":"Write(RegDst, ZeroExtend(imm32))"},"hl_lui":{"imm_kind":"signed","note":"No <<12 in HL.LUI.","rule":"Write(RegDst, SignExtend(imm32))"},"lui":{"imm_kind":"signed","rule":"Write(RegDst, SignExtend(imm20) << 12)"}},"multiplication":{"description":"MUL family conventions (v0.57, retained by v0.57).","hl_madd":{"acc_rule":"acc = (signed_mul(SrcL, SrcR) + signed_add(SrcD))","description":"HL.MADD/HL.MADDW return a 128-bit accumulator split across two destinations.","dst0":"low64(acc)","dst1":"high64(acc)"},"hl_two_dest":{"description":"HL.MUL/HL.MULU return the full 128-bit product split across two destinations.","dst0":"low64(full_product)","dst1":"high64(full_product)","policy":"dst0_low64_dst1_high64"},"scalar":{"model":"low_part","note":"Scalar MUL/MULU return the low 64 bits of the full product."},"word_writeback":{"applies_to":["MULW","MULUW"],"description":"For *W variants, compute in 32-bit domain then sign-extend result to 64-bit.","policy":"sign_extend_all_w_results"}},"notes":["This file records staged bring-up semantics conventions that are consumed by the Sail formal model and referenced by the manual.","These conventions are normative for v0.57. Rules not changed by the reviewed v0.57 delta are retained by v0.57."],"pc_relative":{"addtpc":{"extend":"SignExtend","imm_kind":"signed","note":"ADDTPC uses a signed immediate (addtpc simm)."},"base":"current instruction PC (scalar blocks) or current instruction TPC (vec bodies); the instruction description says PC/TPC.","compressed":{"c.setret":"uses uimm5 with ZeroExtend, then <<1"},"description":"PC-relative immediate conventions (ADDTPC/SETRET and variants).","fused_bstart_call":{"atomic":true,"description":"The exact 32-bit and 48-bit BSTART.CALL forms embed a call transfer and C.SETRET. Their adjacent immediate fields remain independent operands.","forms":{"bstart_call_32_9404418d1ae5":{"call_relocation":"CBSTART12_PCREL","call_target":"P + (SignExtend(simm12) << 1)","return_relocation":"CSETRET5_PCREL","return_target":"(P + 2) + (ZeroExtend(uimm5) << 1)"},"hl_bstart_call_48_3c784c583c90":{"call_relocation":"B25_PCREL","call_target":"P + (SignExtend(simm25) << 1)","return_relocation":"CSETRET5_PCREL","return_target":"(P + 4) + (ZeroExtend(uimm5) << 1)"}},"operand_rule":"simm12/simm25 and uimm5 are independently relocatable PC-relative operands; they MUST NOT be concatenated into one target.","p_definition":"P is the address of the first byte of the fused form.","return_delta_range_bytes":[0,62],"target_alignment_bytes":2},"hl48":{"hl.addtpc":"uses imm32 with SignExtend, then <<1","hl.setret":"uses imm32 with ZeroExtend, then <<1"},"offset_unit_bytes":2,"rule":"target = base + (Extend(imm) << 1)","setret":{"extend":"ZeroExtend","imm_kind":"unsigned","note":"SETRET uses an unsigned immediate (setret uimm)."}},"prefetch":{"address_writeback":{"hl_prf_a":"Rd = EA","hl_prfi_ua":"Rd = EA"},"description":"Prefetch / cache hint instructions (PRF/PRFI and HL variants).","faults":"suppressed (non-faulting hint)","note":"Scalar PRF/PRFI prefetch provides a non-faulting performance hint in v0.57. This rule does not apply to BSTART.TPREFETCH, which is a destination-free TLOAD and retains TLOAD faults."},"regdst_writeback":{"clockhands":{"t_selector":{"behavior":"Push result into T-hand queue (t#1..t#4).","code":31},"u_selector":{"behavior":"Push result into U-hand queue (u#1..u#4).","code":30}},"description":"Destination selector semantics for RegDst-like fields that can target GPRs or ClockHands pushes.","gpr":{"behavior":"Write the selected GPR (R1..R23).","codes":[[1,23]]},"no_output":{"behavior":"No architectural output is produced (silent drop). No exception is raised.","codes":[0,[24,29]]}},"setc_immediates":{"assembly":"Assembly syntax elides shamt (prints a single immediate). Assembler/tooling may choose shamt to represent larger aligned constants when encodable.","description":"Immediate-compare conventions for SETC.*I forms with an encoded shamt field.","encoding":"SETC.*I encodes simm/uimm plus a 5-bit shamt (bits[11:7] in 32-bit forms, analogous position in HL forms).","semantics":{"signed":"imm = SignExtend(simm) << shamt","unsigned":"imm = ZeroExtend(uimm) << shamt"}},"shifts":{"description":"Shift amount masking conventions.","reg_shifts":{"word32":"mask shift amount to SrcR[4:0] (mod 32)","xlen64":"mask shift amount to SrcR[5:0] (mod 64)"}},"srcrtype":{"csel":{"description":"CSEL encodes an optional .neg on SrcR; other SrcRType values are treated as 00.","policy":"11_as_neg_else_00"},"description":"2-bit SrcRType mapping and evaluation order.","mapping":{"00":"none","01":"sw (sext32)","10":"uw (zext32)","11":"neg (arithmetic families) / not (logical families)"},"order":"Apply SrcRType first, then apply any explicit shift (e.g. <<<shamt or <<shamt in addressing).","restricted_forms":{"description":"For forms whose assembly syntax only allows {.sw,.uw} (e.g. CMP.{EQ,NE,LT,GE,LTU,GEU} and SETC.{EQ,NE,LT,GE,LTU,GEU}), SrcRType=11 is treated as 00 (no modifier) in v0.57, retained by v0.57.","policy":"11_as_00"},"word_ops":"For *W (32-bit) operations, apply modifiers at 32-bit width, compute a 32-bit result, then sign-extend to 64-bit."},"version":"v0.57"},"state":{"architectural_state":{"notes":["Architectural state is intentionally minimal here: this repo treats the compiled catalog as the primary machine-readable source.","v0.57 defines the complete architectural, shader-kernel, and rendering state.","Contradictory raw legacy fragments are archived history only and remain reserved or illegal in canonical v0.57.","v0.57 retains PRED with plen[1:0] plus p0..p3 mask bits retained by v0.57.","v0.57 retains the 64-logical-tile model with dynamic capacity descriptors retained by v0.57."],"state":{"block_control_predicate":{"consumer":["BSTART COND","BWE","BWI"],"domain":"block-control","name":"BARG.CARG","producer":["SETC.*","C.SETC.*"]},"kernel_exec_mask":{"consumer":["implicit vector predication","in-body B.Z/B.NZ control flow"],"inactive_lane_result_for_mask_producer":"inactive lanes clear their destination bit to 0","inactive_lane_rule":"inactive lanes follow the selected architectural merge/zero policy","lane_count":64,"lane_layout":{"p_bits":["p0","p1","p2","p3"],"plen_bits":[1,0]},"lane_mask_width_bits":6,"name":"p","packed_lane_rule":"packed convert/compare operations update plen and p0..p3 according to the number of logical elements carried in each lane","plen_encoding":{"0":"no mask bits valid","1":"p0 valid","2":"p0..p1 valid","3":"p0..p3 valid"},"producer":["V.CMP.* ->p"],"width_bits":64},"simt_group_model":{"compiler_1d_profile":{"group_count_field":"LB1","lane_count_field":"LB0","lane_counter_roles":{"lc0":"lane index within current group","lc1":"group index","lc2":"optional third-dimension group index"},"lb2_default":1},"group_execution_mode":{"MPAR":"groups/lanes may execute in parallel but must preserve architectural ordering guarantees","MSEQ":"groups/lanes retire in lexicographic LC order"},"grouping_rule":"group_count = ceil(total_lanes / lane_count)","scalar_uniform_lane":"each group has one scalar-uniform lane context; scalar body instructions execute once per group replay"},"vector_body_mixed_execution":{"applies_to_block_types":["MSEQ","MPAR","VSEQ","VPAR"],"operand_namespace":{"group_scalars":["lc0","lc1","lc2","lb0","lb1","lb2"],"scalar_imports":{"binding_rule":"allocated from repeated B.IOR descriptors in header order, then RegSrc0/RegSrc1/RegSrc2 within each descriptor","form":"ri0..ri11"},"special":["p","zero"],"tile_bases":{"input":["TA","TB","TC","TD"],"output":["TO"],"reserved_legacy":["TE","TF","TG","TH","TO1","TO2","TO3"],"scratch":["TS"]}},"replay":"body executes as a structured instruction stream with one scalar-uniform control context per group","scalar_instructions":{"allowed":true,"state_access":["GPR","t/u","p","scalar condition state"]},"vector_instruction_operand_contract":{"any_operand_rule":"if any operand names vt/vu/vm/vn the instruction executes as v.*; otherwise it executes as l.*","cross_domain_write_rule":"v.* may not write scalar/group-domain destinations except through explicitly defined reduction or mask-producing instructions","direct_scalar_gpr_names":"illegal","exception":"zero literal allowed where encoding permits","scalar_inputs":"must be imported via B.IOR and consumed as ri0..ri11 or other defined scalar/group operand classes","vector_broadcast_rule":"scalar/group-domain source operands broadcast to all active lanes when consumed by v.*"}},"vector_lane_predicate":{"consumer":["V.CSEL"],"producer":["V.CMP.*","V.FEQ","V.FNE","V.FLT","V.FGE","V.FEQS","V.FNES","V.FLTS","V.FGES"],"storage":"vector queue registers (vt/vu/vm/vn)","truth_rule":"lane_value != 0"},"vector_reduction_contract":{"compiler_staged_lowering":{"identity_requirement":"staged reduction lowering requires identity initializer for the selected reduction operation","liveout_bridge":"for strict bring-up, compiler may materialize reduction live-out through `V.RD*` followed by a bridged scratch store (`V.SW.BRG` via ri* binding)"},"destinations":{"group_local":"t/u and block-local scalar destinations","inter_group":"R0..R23 global scalar registers"},"mnemonics":["V.RDADD","V.RDAND","V.RDFADD","V.RDFMAX","V.RDFMIN","V.RDMAX","V.RDMIN","V.RDOR","V.RDXOR"],"mp_ar_compiler_rule":"compiler emits MPAR reduction only when dependence-safe (associative/commutative or explicit programmer parallel hint)","scope":"reduce lane values to a scalar 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producer transaction bases, status, and AckID remain independent","producer_bases_coalesce":false,"stale_ack_rule":"wrong producer, sequence, operation/scope, match, directory, owner, or status-generation is rejected; identical terminal AckID retransmission is idempotent","status_rules":["each state transition increments status_generation","matching post-seal transactions independently record DEFERRED_ACTIVE","FINAL creates one RELEASED_AFTER_FINAL per pending match","fatal release creates one RELEASED_AFTER_ABORT per pending match","post-release admission performs a new lookup at new directory generation"],"terminal_kinds":["NO_MATCH","CANCELED_PRE_EVENT","RELEASED_AFTER_FINAL","RELEASED_AFTER_ABORT"],"terminal_rules":["NO_MATCH after lookup at the transaction directory generation for nonmatches","CANCELED_PRE_EVENT only after cancellation prevents stale event-zero seal","DEFERRED_ACTIVE recorded independently for each post-seal match and is nonterminal","RELEASED_AFTER_FINAL created atomically by FINAL per pending match","RELEASED_AFTER_ABORT created atomically by fatal release per pending match after quiescence","post-release admission performs a new lookup at the new directory generation and normally receives NO_MATCH"],"txn_base_fields":["producer_domain","producer_kind","producer_lxcpu_id","producer_context_generation","producer_pe_id","producer_stid_valid","producer_stid","producer_tid_valid","producer_engine_local_tid","producer_endpoint_id","transaction_sequence_value","transaction_sequence_wrap_or_generation","architectural_operation","exact_operation_scope"],"txn_id_fields":["complete InvalidationTxnBase","matched_LeaseID_or_explicit_NO_LEASE","lease_directory_generation_at_lookup","status_generation"]},"lease_id":["lease_generation","validation_generation","validation_token_hash","exact_vtgt_TemplateOwnerID","exact_vload_TemplateOwnerID_or_canonical_invalid","retained_target_mapping_visibility_share_domain_key"],"legality":{"fret_ra_target":"fixed pre-restore R10","fret_stk_stack_slot_zero":{"device_mmio_or_mixed_or_non_idempotent":"phase_zero E_DATA/MMU_PERM before any cache, fabric, device, or MMIO physical read","required_memory_type":"Normal","requires_idempotent":true},"fret_stk_target":"fixed R10 restored from slot zero","malformed_effects":"zero template effect","pre_effect_checks":["well_formed_endpoints","sufficient_F_pre_effect","FRET.STK_Begin_is_R10"]},"phase_fault_envelopes":{"phase_one_recoverable":{"acre_restore":"retry exactly saved event; do not reissue VLOAD, reacquire lease, or repeat earlier events","bi":1,"dirty":1,"prior_events":"remain_visible","redo_ok":0,"resume_ok":1,"step_index":"faulting_or_next_uncommitted_event"},"phase_zero":{"bi":0,"dirty":0,"phase":0,"redo_ok":1,"resume_ok":0,"step_index":0,"template_effect":"none"},"post_seal_fatal":{"argv":1,"bi":1,"cause":0,"dirty":1,"e":0,"redo_ok":0,"resume_ok":0,"reuse_boundary":"platform reset only","traparg0":"source template PC/TPC","trapnum":"ASSERT_FAIL (52)"}},"profile":"v0.57 range-mode frame templates","register_ring":{"allows_full_ring":true,"allows_singleton":true,"allows_wrap":true,"inclusive_range":[2,23]},"seal_and_recovery":{"after_seal_invalidation":"lease wins; producer completion waits through traps, ACRE, suspension, FINAL, or fatal release","before_seal_invalidation":"wins and cancels phase zero with no effect","ebstate_recoverable_retention":["exact TemplateOwnerID","phase and StepIndex cursors","sealed VLOAD state when applicable","validation token","retained lease","complete pending InvalidationTxnID/status set"],"ebstate_retention_forbidden":["renumber pending invalidation entries","merge pending invalidation entries","reacquire lease entries","restore a pre-template checkpoint"],"event_zero_seal_transaction":["recheck_all_identities_and_generations","acquire_complete_FRET_lease","retire_successful_validation_rows_with_distinct_traces","commit_event_zero","advance_StepIndex_0_to_1"],"final":"qualifies full token, performs boundary transfer/retirement, and releases lease atomically","final_identity":{"required_matches":["group","checkpoint","template","validation","lease","VTGT key","VLOAD key or canonical invalid","visibility/share-domain","FINAL RID/slot/generation","final ordinal"],"shortcut_authority_forbidden":["queue head","BID","RID value","PC","opcode","hash alone"]},"lease_directory_suspend_rule":"lease directory retains discoverability during suspension; a manager must resume through FINAL or choose fatal abandonment and cannot wait on its own deferred invalidation","rollback_after_seal":"forbidden for SP, GPR, memory, target, progress, and trace effects"},"source_contract":"R975 Template Fatal-State and Canonical Identity Contract","step_index":{"event_effect_and_cursor_advance":"atomic","meaning":"next_uncommitted_phase_one_event"},"target_proof":{"actual_current_marker_proof":"required before every FRET effect","coherent_marker_provenance_cache":"legal only when it proves the same target marker bytes, address-space state, code-visibility epoch, and invalidation scope as an actual current marker proof","deferred_demand_paging":"qualified only while every FRET effect remains withheld","fault_owner":"VTGT owns translation, execute-permission, marker, and CFI faults","metadata_only_continuation_or_fallthrough":"non-conforming compatibility; must be rejected"},"template_integrity_fail":{"acre_continuation_allowed":false,"cause":0,"fatal_reasons":{"0":"explicit abandonment","1":"dirty-template RRAT_DEFAULT","2":"sealed-VLOAD replay/withdrawal","3":"poisoned response/token","4":"exact-live ownership/generation/lease/FINAL contradiction","5":"suspended drain failure","6..255":"reserved"},"fatal_teardown_order":["stop source-context issue, commit, wakeup, redirect, FINAL transfer, and new lease acquisition","snapshot exact envelope, state, owner, token, and pending transactions","advance template, row, and load generations","cancel every uncommitted row and request","invalidate VLOAD data, VTGT proof, token, and queued transfer","obtain quiescence from every listed owner before releasing the lease","atomically release the lease and create one RELEASED_AFTER_ABORT per pending matching invalidation","publish the fatal record for managing-ring inspection"],"fixup_allowed":false,"maskable_by_ECONFIG3":false,"quiescence_owners":["ROB","LSU","target-validation","block-control","recovery","trace","redirect/transfer","lease-directory"],"release_ack":"one RELEASED_AFTER_ABORT per pending matching invalidation after quiescence","reset_only":true,"reset_reuse":{"global_quiescence_before_reset":true,"new_context_generation_required":true,"no_pre_reset_ack_after_new_context_generation":true,"platform_reset_only":true,"pre_template_state_restore":"forbidden"},"trapnum":"ASSERT_FAIL (52)"},"template_owner_id":{"equality":"all fields participate; mismatch is never alias","exact_live_post_seal_contradiction":"template_integrity_fail FatalReason=4","field_groups":{"group":["bid","bid_robid(valid,wrap,value)","gid","gid_robid(valid,wrap,value)","group_base_rid","group_base_rid_robid(valid,wrap,value)","group_base_rob_slot","group_row_count","checkpoint_id","template_generation","source_pc","source_raw","form_id","encoded_N"],"memory":["lsid_valid","lsid_value","lsid_wrap_or_generation","load_id_valid","load_id_value","load_id_generation","load_replay_generation","store_id_valid","store_id_value","store_id_generation"],"placement":["lxcpu_id","lxcpu_context_generation","pe_id","stid","engine_local_tid"],"row":["row_present","row_kind","child_ordinal","rid","rid_robid(valid,wrap,value)","rob_slot","row_generation"]},"late_mismatch":"reject without live mutation","reuse_rule":"advance applicable ROBID wrap or template/row/LSID/load/store generation before numeric reuse"},"vload":{"eligible_memory":"complete eight-byte Normal and explicitly idempotent","forbidden_memory_zero_read":["Device/MMIO","mixed_type","unspecified_non_idempotent"],"identity_fields":["owner_key","VA","translation_generation","permission_type_generation","LSID","load_id","older_store_forwarding_state","response_source","miss_refill_coherence_generation","load_generation","data"],"lifecycle":["EMPTY","ISSUED","RESPONDED","ORDER_QUALIFIED","TARGET_VALIDATED","EVENT0_SEALED"],"post_seal_replacement":"forbidden; enters template_integrity_fail FatalReason=2","pre_seal_replay_action":["advance_load_generation","discard_value_vtgt_proof_and_lease_candidate","reject_late_old_generation_responses","rerun_VTGT_even_if_data_bit_identical"],"sampling_point":"event_zero_seal"}},"immediate_materialization":{"description":"Constant materialization conventions.","hl_lis":{"imm_kind":"signed","rule":"Write(RegDst, SignExtend(imm32))"},"hl_liu":{"imm_kind":"unsigned","rule":"Write(RegDst, ZeroExtend(imm32))"},"hl_lui":{"imm_kind":"signed","note":"No <<12 in HL.LUI.","rule":"Write(RegDst, SignExtend(imm32))"},"lui":{"imm_kind":"signed","rule":"Write(RegDst, SignExtend(imm20) << 12)"}},"multiplication":{"description":"MUL family conventions (v0.57, retained by v0.57).","hl_madd":{"acc_rule":"acc = (signed_mul(SrcL, SrcR) + signed_add(SrcD))","description":"HL.MADD/HL.MADDW return a 128-bit accumulator split across two destinations.","dst0":"low64(acc)","dst1":"high64(acc)"},"hl_two_dest":{"description":"HL.MUL/HL.MULU return the full 128-bit product split across two destinations.","dst0":"low64(full_product)","dst1":"high64(full_product)","policy":"dst0_low64_dst1_high64"},"scalar":{"model":"low_part","note":"Scalar MUL/MULU return the low 64 bits of the full product."},"word_writeback":{"applies_to":["MULW","MULUW"],"description":"For *W variants, compute in 32-bit domain then sign-extend result to 64-bit.","policy":"sign_extend_all_w_results"}},"notes":["This file records staged bring-up semantics conventions that are consumed by the Sail formal model and referenced by the manual.","These conventions are normative for v0.57. Rules not changed by the reviewed v0.57 delta are retained by v0.57."],"pc_relative":{"addtpc":{"extend":"SignExtend","imm_kind":"signed","note":"ADDTPC uses a signed immediate (addtpc simm)."},"base":"current instruction PC (scalar blocks) or current instruction TPC (vec bodies); the instruction description says PC/TPC.","compressed":{"c.setret":"uses uimm5 with ZeroExtend, then <<1"},"description":"PC-relative immediate conventions (ADDTPC/SETRET and variants).","fused_bstart_call":{"atomic":true,"description":"The exact 32-bit and 48-bit BSTART.CALL forms embed a call transfer and C.SETRET. Their adjacent immediate fields remain independent operands.","forms":{"bstart_call_32_9404418d1ae5":{"call_relocation":"CBSTART12_PCREL","call_target":"P + (SignExtend(simm12) << 1)","return_relocation":"CSETRET5_PCREL","return_target":"(P + 2) + (ZeroExtend(uimm5) << 1)"},"hl_bstart_call_48_3c784c583c90":{"call_relocation":"B25_PCREL","call_target":"P + (SignExtend(simm25) << 1)","return_relocation":"CSETRET5_PCREL","return_target":"(P + 4) + (ZeroExtend(uimm5) << 1)"}},"operand_rule":"simm12/simm25 and uimm5 are independently relocatable PC-relative operands; they MUST NOT be concatenated into one target.","p_definition":"P is the address of the first byte of the fused form.","return_delta_range_bytes":[0,62],"target_alignment_bytes":2},"hl48":{"hl.addtpc":"uses imm32 with SignExtend, then <<1","hl.setret":"uses imm32 with ZeroExtend, then <<1"},"offset_unit_bytes":2,"rule":"target = base + (Extend(imm) << 1)","setret":{"extend":"ZeroExtend","imm_kind":"unsigned","note":"SETRET uses an unsigned immediate (setret uimm)."}},"prefetch":{"address_writeback":{"hl_prf_a":"Rd = EA","hl_prfi_ua":"Rd = EA"},"description":"Prefetch / cache hint instructions (PRF/PRFI and HL variants).","faults":"suppressed (non-faulting hint)","note":"Scalar PRF/PRFI prefetch provides a non-faulting performance hint in v0.57. This rule does not apply to BSTART.TPREFETCH, which is a destination-free TLOAD and retains TLOAD faults."},"regdst_writeback":{"clockhands":{"t_selector":{"behavior":"Push result into T-hand queue (t#1..t#4).","code":31},"u_selector":{"behavior":"Push result into U-hand queue (u#1..u#4).","code":30}},"description":"Destination selector semantics for RegDst-like fields that can target GPRs or ClockHands pushes.","gpr":{"behavior":"Write the selected GPR (R1..R23).","codes":[[1,23]]},"no_output":{"behavior":"No architectural output is produced (silent drop). No exception is raised.","codes":[0,[24,29]]}},"setc_immediates":{"assembly":"Assembly syntax elides shamt (prints a single immediate). Assembler/tooling may choose shamt to represent larger aligned constants when encodable.","description":"Immediate-compare conventions for SETC.*I forms with an encoded shamt field.","encoding":"SETC.*I encodes simm/uimm plus a 5-bit shamt (bits[11:7] in 32-bit forms, analogous position in HL forms).","semantics":{"signed":"imm = SignExtend(simm) << shamt","unsigned":"imm = ZeroExtend(uimm) << shamt"}},"shifts":{"description":"Shift amount masking conventions.","reg_shifts":{"word32":"mask shift amount to SrcR[4:0] (mod 32)","xlen64":"mask shift amount to SrcR[5:0] (mod 64)"}},"srcrtype":{"csel":{"description":"CSEL encodes an optional .neg on SrcR; other SrcRType values are treated as 00.","policy":"11_as_neg_else_00"},"description":"2-bit SrcRType mapping and evaluation order.","mapping":{"00":"none","01":"sw (sext32)","10":"uw (zext32)","11":"neg (arithmetic families) / not (logical families)"},"order":"Apply SrcRType first, then apply any explicit shift (e.g. <<<shamt or <<shamt in addressing).","restricted_forms":{"description":"For forms whose assembly syntax only allows {.sw,.uw} (e.g. CMP.{EQ,NE,LT,GE,LTU,GEU} and SETC.{EQ,NE,LT,GE,LTU,GEU}), SrcRType=11 is treated as 00 (no modifier) in v0.57, retained by v0.57.","policy":"11_as_00"},"word_ops":"For *W (32-bit) operations, apply modifiers at 32-bit width, compute a 32-bit result, then sign-extend to 64-bit."},"version":"v0.57"},"state":{"architectural_state":{"notes":["Architectural state is intentionally minimal here: this repo treats the compiled catalog as the primary machine-readable source.","v0.57 defines the complete architectural, shader-kernel, and rendering state.","Contradictory raw legacy fragments are archived history only and remain reserved or illegal in canonical v0.57.","v0.57 retains PRED with plen[1:0] plus p0..p3 mask bits retained by v0.57.","v0.57 retains the 64-logical-tile model with dynamic capacity descriptors retained by v0.57."],"state":{"block_control_predicate":{"consumer":["BSTART COND","BWE","BWI"],"domain":"block-control","name":"BARG.CARG","producer":["SETC.*","C.SETC.*"]},"kernel_exec_mask":{"consumer":["implicit vector predication","in-body B.Z/B.NZ control flow"],"inactive_lane_result_for_mask_producer":"inactive lanes clear their destination bit to 0","inactive_lane_rule":"inactive lanes follow the selected architectural merge/zero policy","lane_count":64,"lane_layout":{"p_bits":["p0","p1","p2","p3"],"plen_bits":[1,0]},"lane_mask_width_bits":6,"name":"p","packed_lane_rule":"packed convert/compare operations update plen and p0..p3 according to the number of logical elements carried in each lane","plen_encoding":{"0":"no mask bits valid","1":"p0 valid","2":"p0..p1 valid","3":"p0..p3 valid"},"producer":["V.CMP.* ->p"],"width_bits":64},"simt_group_model":{"compiler_1d_profile":{"group_count_field":"LB1","lane_count_field":"LB0","lane_counter_roles":{"lc0":"lane index within current group","lc1":"group index","lc2":"optional third-dimension group index"},"lb2_default":1},"group_execution_mode":{"MPAR":"groups/lanes may execute in parallel but must preserve architectural ordering guarantees","MSEQ":"groups/lanes retire in lexicographic LC order"},"grouping_rule":"group_count = ceil(total_lanes / lane_count)","scalar_uniform_lane":"each group has one scalar-uniform lane context; scalar body instructions execute once per group replay"},"vector_body_mixed_execution":{"applies_to_block_types":["MSEQ","MPAR","VSEQ","VPAR"],"operand_namespace":{"group_scalars":["lc0","lc1","lc2","lb0","lb1","lb2"],"scalar_imports":{"binding_rule":"allocated from repeated B.IOR descriptors in header order, then RegSrc0/RegSrc1/RegSrc2 within each descriptor","form":"ri0..ri11"},"special":["p","zero"],"tile_bases":{"input":["TA","TB","TC","TD"],"output":["TO"],"reserved_legacy":["TE","TF","TG","TH","TO1","TO2","TO3"],"scratch":["TS"]}},"replay":"body executes as a structured instruction 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0/1 per element","fragment_tiles":["pos_x","pos_y","pos_z","pos_w","coverage","color_r","color_g","color_b","color_a"],"packed_output":"RGBA8_UNORM may be packed as one uint32_t per element","style":"SoA"},"notes":["This file carries the rendering-oriented profile into v0.57 retained by v0.57.","Tiles remain general-purpose intermediate-state storage; screen-space tiling is optional and not baked into the ISA."],"state_placement":{"descriptor_state":"small or rarely-changing values use B.DATR, B.DIM, and B.IOR","state_tiles":"large or hot rendering state uses dedicated StateTiles in the tile register file"},"tau_policy":{"fallback":"VEC MPAR kernels are the required functional fallback for rendering PTOs","memory_access":"TAU is tile-to-tile only"},"tile_profile":{"carrier_bytes":4096,"element_grid":"1024x1","layout":"RowMajor","role":"fragment-list and state-carrier storage"}},"system_registers":{"debug_ssr":{"base_idx":"0xF80","counts":{"addr_bp":4,"context_bp":1,"watchpoint":4},"description":"v0.2 bring-up debug SSRs (breakpoints/watchpoints with optional linking).","entries":[{"access":"RO","description":"Debug capability ID register (CPs/BPs/WPs).","idx":"0xF80","name":"DBGID_ACRn","width_bits":64},{"access":"RW","count":4,"description":"Address breakpoint control.","idx_base":"0xF90","name_fmt":"DBCR%d_ACRn","stride":2,"width_bits":64},{"access":"RW","count":4,"description":"Address breakpoint value (full address).","idx_base":"0xF91","name_fmt":"DBVR%d_ACRn","stride":2,"width_bits":64},{"access":"RW","count":1,"description":"Context breakpoint control.","idx_base":"0xFA0","name_fmt":"DCCR%d_ACRn","stride":2,"width_bits":64},{"access":"RW","count":1,"description":"Context breakpoint value (LC0/LC1/LC2).","idx_base":"0xFA1","name_fmt":"DCVR%d_ACRn","stride":2,"width_bits":64},{"access":"RW","count":4,"description":"Watchpoint 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EBARG words are ACR-scoped manager-family SSRs (0xnf40+).","entries":[{"access":"RW","description":"Packed control word: BlockType, GroupID, TYPE/TAKEN/TRAP, order attributes.","idx":"0xF40","name":"EBARG0_ACRn","width_bits":64},{"access":"RW","description":"Current block start PC (BPC.CUR).","idx":"0xF41","name":"EBARG_BPC_CUR_ACRn","width_bits":64},{"access":"RW","description":"Next block PC target (BPC.TGT).","idx":"0xF42","name":"EBARG_BPC_TGT_ACRn","width_bits":64},{"access":"RW","description":"Body resume PC (TPC). Valid when ECSTATE.BI=1.","idx":"0xF43","name":"EBARG_TPC_ACRn","width_bits":64},{"access":"RW","description":"Local return address (LRA) for split/decoupled blocks.","idx":"0xF44","name":"EBARG_LRA_ACRn","width_bits":64},{"access":"RW","description":"T-hand queue entry 0.","idx":"0xF45","name":"EBARG_TQ0_ACRn","width_bits":64},{"access":"RW","description":"T-hand queue entry 1.","idx":"0xF46","name":"EBARG_TQ1_ACRn","width_bits":64},{"access":"RW","description":"T-hand queue entry 2.","idx":"0xF47","name":"EBARG_TQ2_ACRn","width_bits":64},{"access":"RW","description":"T-hand queue entry 3.","idx":"0xF48","name":"EBARG_TQ3_ACRn","width_bits":64},{"access":"RW","description":"U-hand queue entry 0.","idx":"0xF49","name":"EBARG_UQ0_ACRn","width_bits":64},{"access":"RW","description":"U-hand queue entry 1.","idx":"0xF4A","name":"EBARG_UQ1_ACRn","width_bits":64},{"access":"RW","description":"U-hand queue entry 2.","idx":"0xF4B","name":"EBARG_UQ2_ACRn","width_bits":64},{"access":"RW","description":"U-hand queue entry 3.","idx":"0xF4C","name":"EBARG_UQ3_ACRn","width_bits":64},{"access":"RW","description":"Packed LB0..LB2 as 16-bit each (low bits).","idx":"0xF4D","name":"EBARG_LB_ACRn","width_bits":64},{"access":"RW","description":"Packed LC0..LC2 as 16-bit each (low bits).","idx":"0xF4E","name":"EBARG_LC_ACRn","width_bits":64},{"access":"RW","description":"Pointer to extended-context buffer for ESAVE/ERCOV.","idx":"0xF4F","name":"EBARG_EXTCTX_PTR_ACRn","width_bits":64},{"access":"RW","description":"Extended-context metadata (kind/version/length/checksum; profile-defined).","idx":"0xF50","name":"EBARG_EXTCTX_META_ACRn","width_bits":64},{"access":"RW","description":"Template replay flags: bit0 TPL_VALID, bit1 TPL_ID_PRESENT, bits11:2 TPL_ID, bits13:12 TPL_PHASE, bit14 TPL_DIRTY, bit15 TPL_REDO_OK, bit16 TPL_RESUME_OK; all higher bits reserved zero.","idx":"0xF51","name":"EBARG_TPLFLAGS_ACRn","width_bits":64}]},"notes":["v0.57 system registers (SSR) and trap envelope definitions, defined by v0.57 unless explicitly noted.","v0.57 preserves the v0.57 ACR/EBARG/TRAPNO contract while integrating the reviewed v0.57 extension semantics.","This file is the canonical source for SSR IDs, EBARG layout, and TRAPNO encoding used by the ISA manual, QEMU, Linux, and LLVM.","v0.57 assigns SSR 0x0050 to BLOCKNUM and 0x0051 to BLOCKID.","Prior LB/LC SSR IDs are not reused in this profile without an explicit assignment source."],"ssr":{"base":[{"access":"RW","description":"Thread pointer (TLS base).","id":"0x0000","name":"TP","width_bits":64},{"access":"RW","description":"Global pointer (global data base).","id":"0x0001","name":"GP","width_bits":64},{"access":"RO","clock":"monotonic","description":"Monotonic time counter in nanoseconds. Reads return elapsed monotonic time modulo 2^64 and are not affected by wall-clock adjustments.","id":"0x0010","name":"TIME","unit":"nanoseconds","width_bits":64},{"access":"RW","description":"Common state (privilege + execution state). Includes active ACR and interrupt mask.","id":"0x0020","name":"CSTATE","width_bits":64},{"access":"RO","description":"Linx logical core ID.","id":"0x0021","name":"LXLCID","width_bits":64},{"access":"RO","description":"Vendor ID.","id":"0x0022","name":"VENDOR","width_bits":64},{"access":"RO","description":"Core version.","id":"0x0023","name":"VERSION","width_bits":64},{"access":"RO","description":"Core feature description (includes LaneNum).","id":"0x0024","name":"LCFR","width_bits":64},{"access":"RW","description":"Core feature enable.","id":"0x0025","name":"LCFR_EN","width_bits":64},{"access":"RO","description":"Block Number. Configured by system controller before kernel launch; identifies total logical blocks participating in a parallel task.","id":"0x0050","name":"BLOCKNUM","width_bits":64},{"access":"RO","description":"Block ID. Configured by system controller before kernel launch; identifies the current logical block for debug, trace, and block-level parallel programming.","id":"0x0051","name":"BLOCKID","width_bits":64},{"access":"RO","description":"Cycle counter (bring-up may model as instruction count).","id":"0x0C00","name":"CYCLE","width_bits":64}],"manager_acr_family":{"description":"Manager-ACR (privileged) SSR family. Full SSR_ID is 16-bit where n is the manager ACR ID and low 12 bits select the index.","entries":[{"access":"RW","description":"Exception state. Mirrors key CSTATE fields. Includes BI and ACR target for ACRE.","idx":"0xF00","name":"ECSTATE_ACRn","width_bits":64},{"access":"RW","description":"Exception vector base.","idx":"0xF01","name":"EVBASE_ACRn","width_bits":64},{"access":"RW","description":"Trap number encoding (E/ARGV/CAUSE/TRAPNUM).","idx":"0xF02","name":"TRAPNO_ACRn","width_bits":64},{"access":"RW","description":"Trap argument 0 (valid when TRAPNO.ARGV=1).","idx":"0xF03","name":"TRAPARG0_ACRn","width_bits":64},{"access":"RW","description":"Exception temporary register.","idx":"0xF05","name":"ETEMP_ACRn","width_bits":64},{"access":"RW","description":"Exception temporary register 0 (v0.2 bring-up).","idx":"0xF06","name":"ETEMP0_ACRn","width_bits":64},{"access":"RW","description":"Exception/interrupt configuration.","idx":"0xF07","name":"ECONFIG_ACRn","width_bits":64},{"access":"RO","description":"Interrupt pending bitmap.","idx":"0xF08","name":"IPENDING_ACRn","width_bits":64},{"access":"RO","description":"Top pending interrupt ID.","idx":"0xF09","name":"TOPEI_ACRn","width_bits":64},{"access":"WO","description":"End-of-interrupt.","idx":"0xF0A","name":"EOIEI_ACRn","width_bits":64},{"access":"RW","description":"CPU MMU table base register 0 (ACR1).","idx":"0xF10","name":"TTBR0_ACR1","width_bits":64},{"access":"RW","description":"CPU MMU table base register 1 (ACR1).","idx":"0xF11","name":"TTBR1_ACR1","width_bits":64},{"access":"RW","description":"CPU MMU translation control (ACR1).","idx":"0xF12","name":"TCR_ACR1","width_bits":64},{"access":"RW","description":"CPU MMU memory attribute indirection register (ACR1).","idx":"0xF13","name":"MAIR_ACR1","width_bits":64},{"access":"RW","description":"IOMMU translation table base (ACR1).","idx":"0xF14","name":"IOTTBR_ACR1","width_bits":64},{"access":"RW","description":"IOMMU translation control (ACR1).","idx":"0xF15","name":"IOTCR_ACR1","width_bits":64},{"access":"RW","description":"IOMMU memory attribute indirection register (ACR1).","idx":"0xF16","name":"IOMAIR_ACR1","width_bits":64},{"access":"RO","description":"Timer register.","idx":"0xF20","name":"TIMER_TIME_ACRn","width_bits":64},{"access":"RW","description":"Timer compare register.","idx":"0xF21","name":"TIMER_TIMECMP_ACRn","width_bits":64},{"access":"RW","description":"Cross-block info register. Provides the CAC_TABLE base address for the selected ACR in the v0.57 profile.","idx":"0xF30","name":"XBINFO_ACRn","width_bits":64},{"access":"RW","description":"ACR parameter register. Bring-up uses the low bits to advertise EBSTATE capacity and related context limits.","idx":"0xF31","name":"ACR_PARAM_ACRn","width_bits":64}],"id_pattern":"0xnfxx"},"reserved_pending_assignment":[{"access":"RW","description":"Loop/lane boundary register 0 (bring-up).","id":"0x0050","name":"LB0","status":"reserved_pending_architectural_id_assignment; 0x0050/0x0051 are BLOCKNUM/BLOCKID in v0.57","width_bits":64},{"access":"RW","description":"Loop/lane boundary register 1 (bring-up).","id":"0x0051","name":"LB1","status":"reserved_pending_architectural_id_assignment; 0x0050/0x0051 are BLOCKNUM/BLOCKID in v0.57","width_bits":64},{"access":"RW","description":"Loop/lane boundary register 2 (bring-up).","id":"0x0052","name":"LB2","status":"reserved_pending_architectural_id_assignment; 0x0050/0x0051 are BLOCKNUM/BLOCKID in v0.57","width_bits":64},{"access":"RW","description":"Loop/lane counter register 0 (bring-up).","id":"0x0053","name":"LC0","status":"reserved_pending_architectural_id_assignment; 0x0050/0x0051 are BLOCKNUM/BLOCKID in v0.57","width_bits":64},{"access":"RW","description":"Loop/lane counter register 1 (bring-up).","id":"0x0054","name":"LC1","status":"reserved_pending_architectural_id_assignment; 0x0050/0x0051 are BLOCKNUM/BLOCKID in v0.57","width_bits":64},{"access":"RW","description":"Loop/lane counter register 2 (bring-up).","id":"0x0055","name":"LC2","status":"reserved_pending_architectural_id_assignment; 0x0050/0x0051 are BLOCKNUM/BLOCKID in v0.57","width_bits":64}]},"trapno_encoding":{"bringup_trapnums":[{"description":"Target Exec State Check (e.g. illegal ACRE target).","name":"EXEC_STATE_CHECK","trapnum":0},{"description":"Illegal instruction / illegal SSR / illegal encoding.","name":"ILLEGAL_INST","trapnum":4},{"description":"Block-level trap (format/legality violations).","name":"BLOCK_TRAP","trapnum":5},{"description":"System call (ACRC).","name":"SCALL","trapnum":6},{"description":"Instruction PC fault (alignment/canonicality).","name":"INST_PC_FAULT","trapnum":32},{"description":"Instruction page fault (IFSC in CAUSE).","name":"INST_PAGE_FAULT","trapnum":33},{"description":"Data alignment fault.","name":"DATA_ALIGN_FAULT","trapnum":34},{"description":"Data page fault (DFSC/LaneNum/WnR in CAUSE).","name":"DATA_PAGE_FAULT","trapnum":35},{"description":"Interrupt class (E=1, TRAPARG0=irq_id).","name":"INTERRUPT","trapnum":44},{"description":"Hardware breakpoint trap.","name":"HW_BREAKPOINT","trapnum":49},{"description":"Software breakpoint trap (EBREAK).","name":"SW_BREAKPOINT","trapnum":50},{"description":"Hardware watchpoint trap.","name":"HW_WATCHPOINT","trapnum":51},{"description":"ASSERT failure trap (bring-up / fixup-aware).","name":"ASSERT_FAIL","trapnum":52}],"fields":[{"description":"Asynchronous interrupt indicator (1=async interrupt, 0=sync fault/trap).","lsb":63,"msb":63,"name":"E"},{"description":"TRAPARG0 valid (1=valid).","lsb":62,"msb":62,"name":"ARGV"},{"description":"Sub-cause encoding (profile-defined per TRAPNUM).","lsb":24,"msb":47,"name":"CAUSE"},{"description":"Trap major class (6-bit).","lsb":0,"msb":5,"name":"TRAPNUM"}],"notes":["TRAPNO is shared for faults, traps, and interrupts.","E=1 indicates asynchronous interrupt; E=0 indicates synchronous fault/trap.","ARGV=1 indicates TRAPARG0 is valid."]},"xlen_bits":64}},"version":"0.57.1"}
diff --git a/isa/v0.57/meta.json b/isa/v0.57/meta.json
index 4ed69789..8bbcafac 100644
--- a/isa/v0.57/meta.json
+++ b/isa/v0.57/meta.json
@@ -7,13 +7,14 @@
   ],
   "isa": "LinxISA",
   "notes": [
-    "This directory is the authoritative staged golden ISA definition for v0.57.",
-    "v0.57 is the sole active LinxISA profile and incorporates the complete established ISA contract.",
-    "v0.57 adds reviewed TMA Function 3..8 aliases, named PTO selectors, source-only B.IOT forms, and scalar CASB/CASH/CASW/CASD and DMA encodings.",
-    "The normalized PTO 0.57 inventory classifies all 111 workbook rows into 97 TEPL, 6 TMA, and 8 CUBE dispositions; named CUBE aliases retain the inherited generic BSTART.CUBE form.",
-    "B.IOD remains a reserved encoding. BSTART.PAR remains a retired spelling whose former bit pattern decodes only as BSTART.TEPL.",
+    "This directory is the authoritative staged Linx ISA projection of PTO ISA 0.57.1.",
+    "PTO-ISA/pto-spec is the sole normative source for the 120 tile operations and 99 command forms; pto-spec.lock.json freezes its identity.",
+    "TEPL uses separate Mode and Function fields; the legacy TileOpcode and all legacy decode aliases are forbidden.",
+    "The exact tile inventory is 98 TEPL, 9 TMA, and 13 CUBE operations. Unlisted selectors and unassigned CUBE functions trap as illegal instructions.",
+    "TTRANSPOSE and TSORT32 are migration-only source aliases. Deleted D-class names have no architectural spelling or decode.",
+    "B.IOD remains reserved and old BSTART.PAR/TEPL encodings remain retired.",
     "BSTART.TMA remains an encoding-family name, not a legal textual instruction."
   ],
   "status": "stable",
-  "version": "0.57.0"
+  "version": "0.57.1"
 }
diff --git a/isa/v0.57/opcodes/lx_32.opc b/isa/v0.57/opcodes/lx_32.opc
index 69b38ca3..35651cbd 100644
--- a/isa/v0.57/opcodes/lx_32.opc
+++ b/isa/v0.57/opcodes/lx_32.opc
@@ -20,14 +20,8 @@ ANDI [{"asm":"andi SrcL, simm, ->{t, u, Rd}","group":"Arithmetic Operation 64bit
 ANDIW [{"asm":"andiw SrcL, simm, ->{t, u, Rd}","group":"Arithmetic Operation 32bit","length_bits":32}] : 31..20=simm12 19..15=SrcL 14..12=3'b010 11..7=RegDst 6..4=3'b011 3..1=3'b010 0=1 ; RegDst SrcL simm12 ; -
 ANDW [{"asm":"andw SrcL, SrcR<{.sw,.uw,.not}><<<shamt>, ->{t, u, Rd}","group":"Arithmetic Operation 32bit","length_bits":32}] : 31..27=shamt 26..25=SrcRType 24..20=SrcR 19..15=SrcL 14..12=3'b010 11..7=RegDst 6..4=3'b010 3..1=3'b010 0=1 ; RegDst SrcL SrcR SrcRType shamt ; -
 ASSERT [{"asm":"assert SrcL","group":"Execution Control","length_bits":32}] : 31..28=4'b0000 27..24=4'b0000 23..20=4'b0000 19..15=SrcL 14..12=3'b001 11..7=5'b0_0000 6..4=3'b010 3..1=3'b101 0=1 ; SrcL ; -
-B.CATR [{"asm":"B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}","group":"Block Control Attribute","length_bits":32,"note":"canonical split of legacy B.CATR/B.DATR control fields. Bits 25:15 are reserved zero."}] : 31=trap 30=atom 29=aq 28=rl 27=far 26=DR 25..15=11'b0_0000_0000_00 14..12=3'b000 11..7=5'b0_0000 6..4=3'b010 3..1=3'b001 0=1 ; DR aq atom far rl trap ; -
-B.DATR [{"asm":"B.DATR {layout.{canon, normal}, datatype, padvalue, cmode, rmode, sat}","group":"Block Data Attribute","length_bits":32,"note":"canonical split of legacy B.CATR/B.DATR data fields. CMode is 3 bits; RMode is 3 bits; Sat is bit 31."}] : 31=Sat 30..28=RMode 27..25=CMode 24..20=DataType 19..15=PadValue 14..12=3'b001 11..7=DataLayout 6..4=3'b010 3..1=3'b001 0=1 ; CMode DataLayout DataType PadValue RMode Sat ; -
-B.ARG [{"asm":"B.ARG format","group":"Block Argument","length_bits":32}] : 31..15=17'b0_0000_0000_0000_0000 14..12=3'b011 11..7=format 6..4=3'b100 3..1=3'b001 0=1 ; format ; -
-B.ARG [{"asm":"B.ARG ND2ZN.normal, FP16, Null","group":"Block Argument","length_bits":32}] : 31..20=12'h180 19..15=5'b0_0100 14..12=3'b010 11..7=5'b0_0011 6..4=3'b010 3..1=3'b001 0=1 ;  ; -
-B.ARG [{"asm":"B.ARG DN2NZ.normal, FP32, Null","group":"Block Argument","length_bits":32}] : 31..20=12'h180 19..15=5'b0_0001 14..12=3'b010 11..7=5'b0_1001 6..4=3'b010 3..1=3'b001 0=1 ;  ; -
-B.ARG [{"asm":"B.ARG DN2ZN.normal, FP16, Null","group":"Block Argument","length_bits":32}] : 31..20=12'h180 19..15=5'b0_0100 14..12=3'b010 11..7=5'b0_1000 6..4=3'b010 3..1=3'b001 0=1 ;  ; -
-B.ARG [{"asm":"B.ARG NZ2DN.canon","group":"Block Argument","length_bits":32}] : 31..20=12'h020 19..15=5'b1_1111 14..12=3'b010 11..7=5'b1_1100 6..4=3'b010 3..1=3'b001 0=1 ;  ; -
-B.ARG [{"asm":"B.ARG NORM.normal","group":"Block Argument","length_bits":32}] : 31..20=12'h000 19..15=5'b1_1111 14..12=3'b010 11..7=5'b0_0000 6..4=3'b010 3..1=3'b001 0=1 ;  ; -
+B.CATR [{"asm":"B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}","group":"Block Control Attribute","length_bits":32,"note":"PTO ISA 0.57.1 control attributes. Only DR[26], trap[19], far[18], atom[17], aq[16], and rl[15] are variable."}] : 31..27=5'b0_0000 26=DR 25..20=6'b00_0000 19=trap 18=far 17=atom 16=aq 15=rl 14..12=3'b000 11..7=5'b0_0000 6..4=3'b010 3..1=3'b001 0=1 ; DR aq atom far rl trap ; -
+B.DATR [{"asm":"B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}","group":"Block Data Attribute","length_bits":32,"note":"PTO ISA 0.57.1 data attributes. PadValueOrByteId is an opcode-defined two-bit union; bits 19:18 are reserved zero."}] : 31..29=CMode 28..27=PadValueOrByteId 26=Sat 25=Canonicalize 24..20=DataType 19..18=2'b00 17..15=RMode 14..12=3'b001 11..7=Layout 6..4=3'b010 3..1=3'b001 0=1 ; CMode Canonicalize DataType Layout PadValueOrByteId RMode Sat ; CMode!=6 CMode!=7 DataType!=15 DataType!=21 DataType!=22 DataType!=23 DataType!=29 DataType!=30 DataType!=31 Layout!=2 Layout!=5 Layout!=7 Layout!=10 Layout!=11 Layout!=12 Layout!=13 Layout!=14 Layout!=15 Layout!=16 Layout!=19 Layout!=21 Layout!=22 Layout!=23 Layout!=24 Layout!=25 Layout!=26 Layout!=29 Layout!=31
 B.DIM [{"asm":"B.DIM RegSrc, uimm, ->LB2","group":"Block Argument","length_bits":32}] : 31..20=uimm17[11:0] 19..15=RegSrc 14..12=3'b010 11..7=uimm17[16:12] 6..4=3'b100 3..1=3'b001 0=1 ; RegSrc uimm17 ; -
 B.DIM [{"asm":"B.DIM RegSrc, uimm, ->LB0","group":"Block Argument","length_bits":32}] : 31..20=uimm17[11:0] 19..15=RegSrc 14..12=3'b000 11..7=uimm17[16:12] 6..4=3'b100 3..1=3'b001 0=1 ; RegSrc uimm17 ; -
 B.DIM [{"asm":"B.DIM RegSrc, uimm, ->LB1","group":"Block Argument","length_bits":32}] : 31..20=uimm17[11:0] 19..15=RegSrc 14..12=3'b001 11..7=uimm17[16:12] 6..4=3'b100 3..1=3'b001 0=1 ; RegSrc uimm17 ; -
@@ -37,11 +31,11 @@ B.GEU [{"asm":"b.geu SrcL, SrcR, label","group":"Branch","length_bits":32}] : 31
 B.HINT [{"asm":"B.HINT {BR.{likely, unlikely}, TEMP.{hot, warm, cool, none}, PRFSIZE}","group":"Block Hint","length_bits":32}] : 31..20=prefetch_size 19=0 18..17=temp 16=L/UL 15=V 14..12=3'b000 11..7=5'b0_0000 6..4=3'b011 3..1=3'b001 0=1 ; L/UL V prefetch_size temp ; -
 B.HINT [{"asm":"B.HINT TRACE.{begin, end}","group":"Block Hint","length_bits":32,"note":"Bits 31:16 are reserved zero."}] : 31..16=16'b0 15=B/E 14..12=3'b001 11..7=5'b0_0000 6..4=3'b011 3..1=3'b001 0=1 ; B/E ; -
 B.IOR [{"asm":"B.IOR [RegSrc0, RegSrc1, RegSrc2],[RegDst]","group":"Block Input & Output","length_bits":32}] : 31..27=RegSrc2 26..25=2'b00 24..20=RegSrc1 19..15=RegSrc0 14..12=3'b000 11..7=RegDst 6..4=3'b001 3..1=3'b001 0=1 ; RegDst RegSrc0 RegSrc1 RegSrc2 ; -
-B.IOT [{"asm":"B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>","group":"Block Input & Output","length_bits":32,"note":"canonical two-input immediate-size tile descriptor. SrcTile0/1 are independent 6-bit fields; imm4 encodes 0B..512KB. v0.57 excludes DstTile=111 from this destination-producing form."}] : 31=S1R 30=S0R 29=L 28..25=imm4 24..22=DstTile 21..16=SrcTile1 15=SrcTile0[5:5] 14..12=3'b100 11..7=SrcTile0[4:0] 6..4=3'b001 3..1=3'b001 0=1 ; DstTile L S0R S1R SrcTile0 SrcTile1 imm4 ; DstTile!=7
-B.IOT [{"asm":"B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>","group":"Block Input & Output","length_bits":32,"note":"canonical one-input immediate-size tile descriptor; function=101 means only SrcTile0 is valid. v0.57 excludes DstTile=111 from this destination-producing form."}] : 31=1'b0 30=S0R 29=L 28..25=imm4 24..22=DstTile 21..16=6'b00_0000 15=SrcTile0[5:5] 14..12=3'b101 11..7=SrcTile0[4:0] 6..4=3'b001 3..1=3'b001 0=1 ; DstTile L S0R SrcTile0 imm4 ; DstTile!=7
-B.IOT [{"asm":"B.IOT <last>, ->DstTile<Size>","group":"Block Input & Output","length_bits":32,"note":"canonical no-input immediate-size tile descriptor; function=110 means only the destination allocation is valid."}] : 31=1'b0 30=1'b0 29=L 28..25=imm4 24..22=DstTile 21..16=6'b00_0000 15=1'b0 14..12=3'b110 11..7=5'b0_0000 6..4=3'b001 3..1=3'b001 0=1 ; DstTile L imm4 ; -
-B.IOT [{"asm":"B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>","group":"Block Input & Output","length_bits":32,"note":"v0.57 two-input source-only tile descriptor required by multi-descriptor PTO expansions. DstTile=111 denotes no output and the unused size field is canonically zero."}] : 31=S1R 30=S0R 29=L 28..25=4'b0000 24..22=3'b111 21..16=SrcTile1 15=SrcTile0[5:5] 14..12=3'b100 11..7=SrcTile0[4:0] 6..4=3'b001 3..1=3'b001 0=1 ; L S0R S1R SrcTile0 SrcTile1 ; -
-B.IOT [{"asm":"B.IOT SrcTile0<.reuse>, <last>","group":"Block Input & Output","length_bits":32,"note":"v0.57 one-input source-only tile descriptor required by multi-descriptor PTO expansions. DstTile=111 denotes no output and the unused size field is canonically zero."}] : 31=1'b0 30=S0R 29=L 28..25=4'b0000 24..22=3'b111 21..16=6'b00_0000 15=SrcTile0[5:5] 14..12=3'b101 11..7=SrcTile0[4:0] 6..4=3'b001 3..1=3'b001 0=1 ; L S0R SrcTile0 ; -
+B.IOT [{"asm":"B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>","group":"Block Input & Output","length_bits":32,"note":"PTO ISA 0.57.1 two-source descriptor. imm4 3..9 selects 128B..8KiB; ACC is never encoded as DstTile."}] : 31..26=SrcTile1 25..20=SrcTile0 19=L 18..15=imm4 14..12=3'b100 11=S1R 10=S0R 9..7=DstTile 6..4=3'b001 3..1=3'b001 0=1 ; DstTile L S0R S1R SrcTile0 SrcTile1 imm4 ; DstTile!=4 DstTile!=5 DstTile!=6 DstTile!=7 imm4!=0 imm4!=1 imm4!=2 imm4!=10 imm4!=11 imm4!=12 imm4!=13 imm4!=14 imm4!=15
+B.IOT [{"asm":"B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>","group":"Block Input & Output","length_bits":32,"note":"PTO ISA 0.57.1 one-source descriptor. Inactive source and reuse fields encode zero."}] : 31..26=6'b00_0000 25..20=SrcTile0 19=L 18..15=imm4 14..12=3'b101 11=1'b0 10=S0R 9..7=DstTile 6..4=3'b001 3..1=3'b001 0=1 ; DstTile L S0R SrcTile0 imm4 ; DstTile!=4 DstTile!=5 DstTile!=6 DstTile!=7 imm4!=0 imm4!=1 imm4!=2 imm4!=10 imm4!=11 imm4!=12 imm4!=13 imm4!=14 imm4!=15
+B.IOT [{"asm":"B.IOT <last>, ->DstTile<Size>","group":"Block Input & Output","length_bits":32,"note":"PTO ISA 0.57.1 zero-source destination descriptor. Inactive source and reuse fields encode zero."}] : 31..20=12'b0000_0000_0000 19=L 18..15=imm4 14..12=3'b110 11..10=2'b00 9..7=DstTile 6..4=3'b001 3..1=3'b001 0=1 ; DstTile L imm4 ; DstTile!=4 DstTile!=5 DstTile!=6 DstTile!=7 imm4!=0 imm4!=1 imm4!=2 imm4!=10 imm4!=11 imm4!=12 imm4!=13 imm4!=14 imm4!=15
+B.IOT [{"asm":"B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>","group":"Block Input & Output","length_bits":32,"note":"PTO ISA 0.57.1 two-source destination-free descriptor. DstTile and imm4 encode zero; zero does not name an output."}] : 31..26=SrcTile1 25..20=SrcTile0 19=L 18..15=4'b0000 14..12=3'b100 11=S1R 10=S0R 9..7=3'b000 6..4=3'b001 3..1=3'b001 0=1 ; L S0R S1R SrcTile0 SrcTile1 ; -
+B.IOT [{"asm":"B.IOT SrcTile0<.reuse>, <last>","group":"Block Input & Output","length_bits":32,"note":"PTO ISA 0.57.1 one-source destination-free descriptor. All inapplicable fields encode zero."}] : 31..26=6'b00_0000 25..20=SrcTile0 19=L 18..15=4'b0000 14..12=3'b101 11=1'b0 10=S0R 9..7=3'b000 6..4=3'b001 3..1=3'b001 0=1 ; L S0R SrcTile0 ; -
 B.LT [{"asm":"b.lt SrcL, SrcR, label","group":"Branch","length_bits":32}] : 31..25=simm12[6:0] 24..20=SrcR 19..15=SrcL 14..12=3'b010 11..7=simm12[11:7] 6..4=3'b010 3..1=3'b011 0=1 ; SrcL SrcR simm12 ; -
 B.LTU [{"asm":"b.ltu SrcL, SrcR, label","group":"Branch","length_bits":32}] : 31..25=simm12[6:0] 24..20=SrcR 19..15=SrcL 14..12=3'b100 11..7=simm12[11:7] 6..4=3'b010 3..1=3'b011 0=1 ; SrcL SrcR simm12 ; -
 B.NE [{"asm":"b.ne SrcL, SrcR, label","group":"Branch","length_bits":32}] : 31..25=simm12[6:0] 24..20=SrcR 19..15=SrcL 14..12=3'b001 11..7=simm12[11:7] 6..4=3'b010 3..1=3'b011 0=1 ; SrcL SrcR simm12 ; -
@@ -60,12 +54,10 @@ BSTART [{"asm":"BSTART COND, <label>","group":"Block Split","length_bits":32}] :
 # Strict-v0.57 typed tile header contract:
 # - Encoded selector families: TMA, CUBE, TEPL; TMA has only exact legal named forms.
 # - Explicit named forms cover assigned TMA/CUBE functions and every allocated TEPL selector.
-# - TLOAD/TSTORE require B.ARG(layout/pad) + B.IOR(stride/base) + B.IOT.
-# - CUBE matmul requires B.DIM LB0/LB1/LB2 bound as m/n/k; ACCCVT requires quant args via B.ARG + B.IOR.
+# - TLOAD/TSTORE use B.DATR(layout/pad) + B.IOR(stride/base) + B.IOT.
+# - CUBE matmul uses B.DIM LB0/LB1/LB2 as m/n/k; ACCCVT conversion controls come from B.DATR.
 # - VPAR/VSEQ are TVEC-equivalent SIMT headers with B.TEXT body; TMA/CUBE/TEPL tile ops are header-driven.
-BSTART.ACCCVT [{"asm":"BSTART.ACCCVT DataType","group":"Block Split","length_bits":32,"note":"Alias of BSTART.CUBE Function=8. ACCCVT requires quantization args via B.ARG+B.IOR (scale/zero-point required in strict profile)."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_1000 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
-BSTART.CUBE [{"asm":"BSTART.CUBE Function, DataType","group":"Block Split","length_bits":32,"note":"Generic CUBE selector form for unnamed functions. Functions 0/1/2/4/5/6/8/16/17/18/20/21/22 decode through their canonical named forms."}] : 31..27=DataType 26..25=2'b00 24..20=Function 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType Function ; Function!=0 Function!=1 Function!=2 Function!=4 Function!=5 Function!=6 Function!=8 Function!=16 Function!=17 Function!=18 Function!=20 Function!=21 Function!=22
-BSTART.FIXP [{"asm":"BSTART.FIXP TileOp, DataType","group":"Block Split","length_bits":32}] : 31..27=DataType 26..25=2'b00 24..20=Function 19..15=5'b0_0111 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType Function ; -
+BSTART.ACCCVT [{"asm":"BSTART.ACCCVT DataType","group":"Block Split","length_bits":32,"note":"Named CUBE-family Function=8. ACCCVT reads implicit ACC and uses B.DATR conversion controls before publishing an ordinary Tile."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_1000 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.FP [{"asm":"BSTART.FP RET","group":"Block Split","length_bits":32,"note":"Bits 31:15 are reserved zero."}] : 31..15=17'b0 14..12=3'b111 11..7=5'b0_0010 6..4=3'b000 3..1=3'b000 0=1 ; - ; -
 BSTART.FP [{"asm":"BSTART.FP IND","group":"Block Split","length_bits":32,"note":"Bits 31:15 are reserved zero."}] : 31..15=17'b0 14..12=3'b101 11..7=5'b0_0010 6..4=3'b000 3..1=3'b000 0=1 ; - ; -
 BSTART.FP [{"asm":"BSTART.FP COND, <label>","group":"Block Split","length_bits":32}] : 31..15=simm17 14..12=3'b011 11..7=5'b0_0010 6..4=3'b000 3..1=3'b000 0=1 ; simm17 ; -
@@ -83,17 +75,17 @@ BSTART.STD [{"asm":"BSTART.STD CALL, <label>","group":"Block Split","length_bits
 BSTART.STD [{"asm":"BSTART.STD IND","group":"Block Split","length_bits":32,"note":"Bits 31:15 are reserved zero."}] : 31..15=17'b0 14..12=3'b101 11..7=5'b0_0000 6..4=3'b000 3..1=3'b000 0=1 ; - ; -
 BSTART.STD [{"asm":"BSTART.STD DIRECT, <label>","group":"Block Split","length_bits":32}] : 31..15=simm17 14..12=3'b010 11..7=5'b0_0000 6..4=3'b000 3..1=3'b000 0=1 ; simm17 ; -
 BSTART.SYS [{"asm":"BSTART.SYS FALL<, fixup_label>","group":"Block Split","length_bits":32}] : 31..15=simm17 14..12=3'b001 11..7=5'b0_0001 6..4=3'b000 3..1=3'b000 0=1 ; simm17 ; -
-BSTART.TEPL [{"asm":"BSTART.TEPL TileOpcode, DataType","group":"Block Split","length_bits":32,"note":"Tile opcode selects PTO template ops. Canonical established assignments require TileOpcode[9:6]=0 and pack TileOpcode[5]=Mode with TileOpcode[4:0]=Function; unassigned values remain reserved for future template extension."}] : 31..27=DataType 26..25=2'b01 24..15=TileOpcode 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType TileOpcode ; -
-BSTART.TLOAD [{"asm":"BSTART.TLOAD DataType","group":"Block Split","length_bits":32,"note":"Alias of BSTART.TMA Function=0. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0000 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
+BSTART.TEPL [{"asm":"BSTART.TEPL Mode, Function, DataType","group":"Block Split","length_bits":32,"note":"PTO ISA 0.57.1 TEPL selector: logical_selector=(Mode<<5)|Function. There is no legacy 10-bit TileOpcode decode."}] : 31..27=DataType 26..25=Mode 24..20=Function 19..15=5'b0_0011 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType Function Mode ; -
+BSTART.TLOAD [{"asm":"BSTART.TLOAD DataType","group":"Block Split","length_bits":32,"note":"TMA Function=0. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0000 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 # TMA Function=9..31 are reserved encodings, not legal forms; see state/engine_ops.json.
-BSTART.MGATHER [{"asm":"BSTART.MGATHER DataType","group":"Block Split","length_bits":32,"note":"Named TMA-family Function=4. Memory gather uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0100 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
+BSTART.MGATHER [{"asm":"BSTART.MGATHER DataType","group":"Block Split","length_bits":32,"note":"TMA Function=4. Memory gather uses B.DATR/B.IOR/B.IOT descriptor state."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0100 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.MGATHER.CAS [{"asm":"BSTART.MGATHER.CAS DataType","group":"Block Split","length_bits":32,"note":"Named TMA-family Function=8. Per-element atomic compare-and-swap gather; detailed PTO selector manifest is defined out-of-band for v0.57."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_1000 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.MGATHER.MASK [{"asm":"BSTART.MGATHER.MASK DataType","group":"Block Split","length_bits":32,"note":"Named TMA-family Function=6. Masked memory gather; detailed PTO selector manifest is defined out-of-band for v0.57."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0110 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
-BSTART.MSCATTER [{"asm":"BSTART.MSCATTER DataType","group":"Block Split","length_bits":32,"note":"Named TMA-family Function=5. Memory scatter uses B.ARG/B.IOR/B.IOT descriptor state; detailed PTO selector manifest is defined out-of-band for v0.57."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0101 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
+BSTART.MSCATTER [{"asm":"BSTART.MSCATTER DataType","group":"Block Split","length_bits":32,"note":"TMA Function=5. Memory scatter uses B.DATR/B.IOR/B.IOT descriptor state."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0101 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.MSCATTER.MASK [{"asm":"BSTART.MSCATTER.MASK DataType","group":"Block Split","length_bits":32,"note":"Named TMA-family Function=7. Masked memory scatter; detailed PTO selector manifest is defined out-of-band for v0.57."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0111 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
-BSTART.TMATMUL [{"asm":"BSTART.TMATMUL DataType","group":"Block Split","length_bits":32,"note":"Alias of BSTART.CUBE Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0000 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
+BSTART.TMATMUL [{"asm":"BSTART.TMATMUL DataType","group":"Block Split","length_bits":32,"note":"Named CUBE-family Function=0. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0000 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.TMATMUL.BIAS [{"asm":"BSTART.TMATMUL.BIAS DataType","group":"Block Split","length_bits":32,"note":"Named CUBE-family Function=1. Matrix multiply with bias; requires B.DIM and CUBE tile bindings."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0001 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
-BSTART.TMATMUL.ACC [{"asm":"BSTART.TMATMUL.ACC DataType","group":"Block Split","length_bits":32,"note":"Alias of BSTART.CUBE Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0010 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
+BSTART.TMATMUL.ACC [{"asm":"BSTART.TMATMUL.ACC DataType","group":"Block Split","length_bits":32,"note":"Named CUBE-family Function=2. Requires B.DIM (LB0/LB1/LB2 as m,n,k) and tile bindings via B.IOT."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0010 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.TMATMULMX [{"asm":"BSTART.TMATMULMX DataType","group":"Block Split","length_bits":32,"note":"Named CUBE-family Function=4. Micro-scaled matrix multiply; requires B.DIM and CUBE tile bindings."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0100 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.TMATMULMX.BIAS [{"asm":"BSTART.TMATMULMX.BIAS DataType","group":"Block Split","length_bits":32,"note":"Named CUBE-family Function=5. Micro-scaled matrix multiply with bias; requires B.DIM and CUBE tile bindings."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0101 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.TMATMULMX.ACC [{"asm":"BSTART.TMATMULMX.ACC DataType","group":"Block Split","length_bits":32,"note":"Named CUBE-family Function=6. Micro-scaled matrix multiply-accumulate; requires B.DIM and CUBE tile bindings."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0110 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
@@ -105,7 +97,7 @@ BSTART.TGEMVMX.BIAS [{"asm":"BSTART.TGEMVMX.BIAS DataType","group":"Block Split"
 BSTART.TGEMVMX.ACC [{"asm":"BSTART.TGEMVMX.ACC DataType","group":"Block Split","length_bits":32,"note":"Named CUBE-family Function=22. Micro-scaled matrix-vector multiply-accumulate; requires B.DIM and CUBE tile bindings."}] : 31..27=DataType 26..25=2'b00 24..20=5'b1_0110 19..15=5'b0_0110 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.TMOV [{"asm":"BSTART.TMOV DataType","group":"Block Split","length_bits":32,"note":"Alias of BSTART.TMA Function=2. TMOV is tile-state only (no GM memory access) and destination allocation is queue-push only."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0010 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.TPREFETCH [{"asm":"BSTART.TPREFETCH DataType","group":"Block Split","length_bits":32,"note":"Named TMA-family Function=3. TPREFETCH has the same address, layout, memory, fault, ordering, and restart contract as TLOAD, with destination binding/allocation/writeback effects removed."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0011 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
-BSTART.TSTORE [{"asm":"BSTART.TSTORE DataType","group":"Block Split","length_bits":32,"note":"Alias of BSTART.TMA Function=1. Requires B.ARG layout/pad and B.IOR stride/base plus B.IOT tile binding."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0001 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
+BSTART.TSTORE [{"asm":"BSTART.TSTORE DataType","group":"Block Split","length_bits":32,"note":"TMA Function=1. Uses B.DATR layout/pad and B.IOR stride/base plus B.IOT tile binding."}] : 31..27=DataType 26..25=2'b00 24..20=5'b0_0001 19..15=5'b0_0010 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; DataType ; -
 BSTART.VPAR [{"asm":"BSTART.VPAR <VS8, VS16>","group":"Block Split","length_bits":32,"note":"TVEC-equivalent parallel SIMT header; requires B.TEXT body target in decoupled form."}] : 31..27=5'b0_0000 26..25=Mode 24..20=5'b0_0000 19..15=5'b0_0100 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; Mode ; -
 BSTART.VSEQ [{"asm":"BSTART.VSEQ <VS8, VS16>","group":"Block Split","length_bits":32,"note":"TVEC-equivalent sequential SIMT header; requires B.TEXT body target in decoupled form."}] : 31..27=5'b0_0000 26..25=Mode 24..20=5'b0_0000 19..15=5'b0_0101 14..12=3'b001 11..7=5'b0_0011 6..4=3'b000 3..1=3'b000 0=1 ; Mode ; -
 BSTOP [{"asm":"BSTOP","group":"Block Split","length_bits":32}] : 31..15=17'b0_0000_0000_0000_0000 14..12=3'b000 11..7=5'b0_0000 6..4=3'b000 3..1=3'b000 0=1 ;  ; -
diff --git a/isa/v0.57/pto-spec.lock.json b/isa/v0.57/pto-spec.lock.json
new file mode 100644
index 00000000..319547a3
--- /dev/null
+++ b/isa/v0.57/pto-spec.lock.json
@@ -0,0 +1,36 @@
+{
+  "$schema": "https://docs.openclaw.ai/schemas/linxisa/pto_spec_lock.v1.json",
+  "catalogs": {
+    "command_forms": {
+      "path": "spec/catalog/command-forms.json",
+      "sha256": "e5a98441098fdd88c0f5837bb3e1367d7b272ebc2ba506275e9e2be1b4c1978a",
+      "count": 99
+    },
+    "tile_operations": {
+      "path": "spec/catalog/tile-operations.json",
+      "sha256": "e77c762122dd776ea8b1b2113e6d095b2db0fe24b5b98d0c26012db9fb98e64e",
+      "count": 120
+    }
+  },
+  "content_sha256": "748c1c6ac1bd5482d219cd08b8f0a871c7eda2b8f8afb1e81d498ec742e8abe8",
+  "encoding_abi": "pto-isa-0.57.1-mode-function-v1",
+  "encoding_projection_sha256": "9705a984e2e48e0d4e856d3fbcfa07041c8578dd326d81f1c90279e826354c32",
+  "hardware_conformance_profile": {
+    "path": "spec/hardware-conformance-profile.json",
+    "profile_id": "pto-hardware-numeric-0.57.1-ieee-v1",
+    "sha256": "becfbefcc7a31408e5e5293802493f833f68a2fccebb3f9e8008d8b9f4e7658c"
+  },
+  "numeric_conformance_vectors": {
+    "path": "spec/evidence/pto-isa-0571-hardware-numeric-vectors.json",
+    "sha256": "b9f908deb9cfec412388e95f4532563cf4e462032b43d15996f0f7b4b93b4ec9"
+  },
+  "release": "0.57.1",
+  "release_manifest": {
+    "path": "spec/release-manifest.json",
+    "sha256": "d85ee1cfcd51b1b86184ba015e9fb24ee61371165cf4691a5794f79618f7e273"
+  },
+  "source": {
+    "commit": "2f3f605e289b09d56ef5a9ba39fc80b52948a5f5",
+    "repository": "https://github.com/PTO-ISA/pto-spec.git"
+  }
+}
diff --git a/isa/v0.57/release_manifest.json b/isa/v0.57/release_manifest.json
index bfda37dc..0646f4ce 100644
--- a/isa/v0.57/release_manifest.json
+++ b/isa/v0.57/release_manifest.json
@@ -1,469 +1,64 @@
 {
-  "$schema": "https://docs.openclaw.ai/schemas/linxisa/release_manifest.v0.json",
-  "added_instructions": [
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00311181",
-      "mnemonic": "BSTART.TPREFETCH",
-      "semantic_delta": "Same address, layout, memory, fault, ordering, and restart contract as BSTART.TLOAD, with destination binding, destination allocation, and destination writeback removed.",
-      "source": "user decision for v0.57 TMA Function=3"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00411181",
-      "mnemonic": "BSTART.MGATHER",
-      "source": "LinxISA/linx-isa#123"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00511181",
-      "mnemonic": "BSTART.MSCATTER",
-      "source": "LinxISA/linx-isa#123"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00611181",
-      "mnemonic": "BSTART.MGATHER.MASK",
-      "source": "LinxISA/linx-isa#123"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00711181",
-      "mnemonic": "BSTART.MSCATTER.MASK",
-      "source": "LinxISA/linx-isa#123"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00811181",
-      "mnemonic": "BSTART.MGATHER.CAS",
-      "source": "LinxISA/linx-isa#133"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00131181",
-      "mnemonic": "BSTART.TMATMUL.BIAS",
-      "source": "PTO-ISA-LinxISA 0.57 workbook and documented CUBE Function=1"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00431181",
-      "mnemonic": "BSTART.TMATMULMX",
-      "source": "PTO-ISA-LinxISA 0.57 workbook and documented CUBE Function=4"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00531181",
-      "mnemonic": "BSTART.TMATMULMX.BIAS",
-      "source": "documented CUBE Function=5"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x00631181",
-      "mnemonic": "BSTART.TMATMULMX.ACC",
-      "source": "documented CUBE Function=6"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x01031181",
-      "mnemonic": "BSTART.TGEMV",
-      "source": "PTO-ISA-LinxISA 0.57 workbook and documented CUBE Function=16"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x01131181",
-      "mnemonic": "BSTART.TGEMV.BIAS",
-      "source": "PTO-ISA-LinxISA 0.57 workbook and documented CUBE Function=17"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x01231181",
-      "mnemonic": "BSTART.TGEMV.ACC",
-      "source": "PTO-ISA-LinxISA 0.57 workbook and documented CUBE Function=18"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x01431181",
-      "mnemonic": "BSTART.TGEMVMX",
-      "source": "PTO-ISA-LinxISA 0.57 workbook and documented CUBE Function=20"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x01531181",
-      "mnemonic": "BSTART.TGEMVMX.BIAS",
-      "source": "documented CUBE Function=21"
-    },
-    {
-      "mask": "0x07ffffff",
-      "match": "0x01631181",
-      "mnemonic": "BSTART.TGEMVMX.ACC",
-      "source": "documented CUBE Function=22"
-    },
-    {
-      "mask": "0x0000707f",
-      "match": "0x0000001b",
-      "mnemonic": "CASB",
-      "source": "LinxISA/linx-isa#139"
-    },
-    {
-      "mask": "0x0000707f",
-      "match": "0x0000101b",
-      "mnemonic": "CASH",
-      "source": "LinxISA/linx-isa#139"
-    },
-    {
-      "mask": "0x0000707f",
-      "match": "0x0000201b",
-      "mnemonic": "CASW",
-      "source": "LinxISA/linx-isa#139"
-    },
-    {
-      "mask": "0x0000707f",
-      "match": "0x0000301b",
-      "mnemonic": "CASD",
-      "source": "LinxISA/linx-isa#139"
-    },
-    {
-      "mask": "0xfe007fff",
-      "match": "0x0000700b",
-      "mnemonic": "DMA",
-      "source": "LinxISA/linx-isa#139"
-    }
-  ],
-  "added_instruction_forms": [
-    {
-      "asm": "B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>",
-      "mask": "0x1fc0707f",
-      "match": "0x01c04013",
-      "mnemonic": "B.IOT",
-      "semantic_delta": "Bind two ordered source Tiles without allocating or writing a destination Tile; DstTile=111 is the architectural no-output value and the unused size field is fixed to zero.",
-      "source": "LinxISA/linx-isa#123 and LinxISA/linx-isa#133 multi-descriptor PTO expansions"
-    },
-    {
-      "asm": "B.IOT SrcTile0<.reuse>, <last>",
-      "mask": "0x9fff707f",
-      "match": "0x01c05013",
-      "mnemonic": "B.IOT",
-      "semantic_delta": "Bind one ordered source Tile without allocating or writing a destination Tile; DstTile=111 is the architectural no-output value and the unused size field is fixed to zero.",
-      "source": "LinxISA/linx-isa#123 and LinxISA/linx-isa#133 multi-descriptor PTO expansions"
-    }
-  ],
-  "changed_instructions": [
-    {
-      "uid": "bd3f337acb9d",
-      "mnemonic": "BSTART.CUBE",
-      "allowed_change": "Narrow the inherited generic selector constraints only at functions that receive canonical named v0.57 forms; all unnamed functions remain legal and the encoding, fields, operand roles, and semantics are unchanged.",
-      "excluded_named_functions": [
-        0,
-        1,
-        2,
-        4,
-        5,
-        6,
-        8,
-        16,
-        17,
-        18,
-        20,
-        21,
-        22
-      ]
-    },
-    {
-      "uid": "10db6db84f5d",
-      "mnemonic": "B.IOT",
-      "allowed_change": "Exclude DstTile=111 from the inherited one-input destination-producing form so the new source-only form has a disjoint canonical encoding.",
-      "added_constraints": [
-        {
-          "field": "DstTile",
-          "op": "!=",
-          "value": "7"
-        }
-      ]
-    },
-    {
-      "uid": "8b8bce6bffe8",
-      "mnemonic": "B.IOT",
-      "allowed_change": "Exclude DstTile=111 from the inherited two-input destination-producing form so the new source-only form has a disjoint canonical encoding.",
-      "added_constraints": [
-        {
-          "field": "DstTile",
-          "op": "!=",
-          "value": "7"
-        }
-      ]
-    }
-  ],
+  "$schema": "https://docs.openclaw.ai/schemas/linxisa/release_manifest.v1.json",
   "profile": "v0.57",
-  "version": "0.57.0",
+  "version": "0.57.1",
+  "source_lock": "isa/v0.57/pto-spec.lock.json",
   "policy": {
-    "standalone_release": true,
-    "legacy_aliases_allowed": false,
-    "new_pto_selector_manifest_in_scope": true,
-    "textual_family_mnemonics_allowed": false
+    "pto_spec_is_sole_source": true,
+    "legacy_decode_allowed": false,
+    "unlisted_selectors_reserved": true,
+    "migration_aliases_are_source_only": true
   },
-  "reserved_ranges": {
-    "tma_function_u5": [
-      [
-        9,
-        31
-      ]
-    ]
+  "cardinality": {
+    "tile_operations": 120,
+    "tile_families": {
+      "TEPL": 98,
+      "CUBE": 13,
+      "TMA": 9
+    },
+    "command_forms": 99,
+    "command_form_families": {
+      "BBD": 25,
+      "CMD": 74
+    },
+    "scalar_forms": 474
   },
-  "tepl_selector_delta": {
-    "manifest_files": [
-      "isa/v0.57/state/pto_ops.json",
-      "isa/v0.57/state/pto_encoding_map.json"
-    ],
-    "new_selector_ranges": [
-      [
-        "0x02B",
-        "0x048"
-      ],
-      [
-        "0x080",
-        "0x08B"
-      ],
-      [
-        "0x0C0",
-        "0x0C8"
-      ],
-      [
-        "0x0E0",
-        "0x0E3"
-      ]
-    ],
-    "new_selectors": [
-      {
-        "name": "TCMP",
-        "selector": "0x02B"
-      },
-      {
-        "name": "TSEL",
-        "selector": "0x02C"
-      },
-      {
-        "name": "TABS",
-        "selector": "0x02D"
-      },
-      {
-        "name": "TNOT",
-        "selector": "0x02E"
-      },
-      {
-        "name": "TNEG",
-        "selector": "0x02F"
-      },
-      {
-        "name": "TREM",
-        "selector": "0x030"
-      },
-      {
-        "name": "TAXPY",
-        "selector": "0x031"
-      },
-      {
-        "name": "TREMS",
-        "selector": "0x032"
-      },
-      {
-        "name": "TCMPS",
-        "selector": "0x033"
-      },
-      {
-        "name": "TSELS",
-        "selector": "0x034"
-      },
-      {
-        "name": "TROWPROD",
-        "selector": "0x035"
-      },
-      {
-        "name": "TROWARGMAX",
-        "selector": "0x036"
-      },
-      {
-        "name": "TROWARGMIN",
-        "selector": "0x037"
-      },
-      {
-        "name": "TCOLPROD",
-        "selector": "0x038"
-      },
-      {
-        "name": "TCOLARGMAX",
-        "selector": "0x039"
-      },
-      {
-        "name": "TCOLARGMIN",
-        "selector": "0x03A"
-      },
-      {
-        "name": "TROWEXPANDADD",
-        "selector": "0x03B"
-      },
-      {
-        "name": "TROWEXPANDSUB",
-        "selector": "0x03C"
-      },
-      {
-        "name": "TROWEXPANDMUL",
-        "selector": "0x03D"
-      },
-      {
-        "name": "TROWEXPANDDIV",
-        "selector": "0x03E"
-      },
-      {
-        "name": "TROWEXPANDMAX",
-        "selector": "0x03F"
-      },
-      {
-        "name": "TROWEXPANDMIN",
-        "selector": "0x040"
-      },
-      {
-        "name": "TROWEXPANDEXPDIF",
-        "selector": "0x041"
-      },
-      {
-        "name": "TCOLEXPANDADD",
-        "selector": "0x042"
-      },
-      {
-        "name": "TCOLEXPANDSUB",
-        "selector": "0x043"
-      },
-      {
-        "name": "TCOLEXPANDMUL",
-        "selector": "0x044"
-      },
-      {
-        "name": "TCOLEXPANDDIV",
-        "selector": "0x045"
-      },
-      {
-        "name": "TCOLEXPANDMAX",
-        "selector": "0x046"
-      },
-      {
-        "name": "TCOLEXPANDMIN",
-        "selector": "0x047"
-      },
-      {
-        "name": "TCOLEXPANDEXPDIF",
-        "selector": "0x048"
-      },
-      {
-        "name": "TCI",
-        "selector": "0x080"
-      },
-      {
-        "name": "TTRI",
-        "selector": "0x081"
-      },
-      {
-        "name": "TFILLPAD",
-        "selector": "0x082"
-      },
-      {
-        "name": "TQUANT",
-        "selector": "0x083"
-      },
-      {
-        "name": "TDEQUANT",
-        "selector": "0x084"
-      },
-      {
-        "name": "TEXTRACT",
-        "selector": "0x085"
-      },
-      {
-        "name": "TINSERT",
-        "selector": "0x086"
-      },
-      {
-        "name": "TCONCAT",
-        "selector": "0x087"
-      },
-      {
-        "name": "TIMG2COL",
-        "selector": "0x088"
-      },
-      {
-        "name": "TGATHERB",
-        "selector": "0x089"
-      },
-      {
-        "name": "TDEINTERLEAVE",
-        "selector": "0x08A"
-      },
-      {
-        "name": "TINTERLEAVE",
-        "selector": "0x08B"
-      },
-      {
-        "name": "TSORT",
-        "selector": "0x0C0"
-      },
-      {
-        "name": "TMRGSORT",
-        "selector": "0x0C1"
-      },
-      {
-        "name": "THISTOGRAM",
-        "selector": "0x0C2"
-      },
-      {
-        "name": "TPARTADD",
-        "selector": "0x0C3"
-      },
-      {
-        "name": "TPARTMUL",
-        "selector": "0x0C4"
-      },
-      {
-        "name": "TPARTMAX",
-        "selector": "0x0C5"
-      },
-      {
-        "name": "TPARTMIN",
-        "selector": "0x0C6"
-      },
-      {
-        "name": "TPARTARGMAX",
-        "selector": "0x0C7"
-      },
-      {
-        "name": "TPARTARGMIN",
-        "selector": "0x0C8"
-      },
-      {
-        "name": "TPUSH",
-        "selector": "0x0E0"
-      },
-      {
-        "name": "TPOP",
-        "selector": "0x0E1"
-      },
-      {
-        "name": "TALLOC",
-        "selector": "0x0E2"
-      },
-      {
-        "name": "TFREE",
-        "selector": "0x0E3"
-      }
-    ],
-    "established_selector_range": [
-      "0x000",
-      "0x02A"
-    ],
-    "review_only_names_rejected": [
-      "TFMOD",
-      "TPOW",
-      "TRANDOM",
-      "TEXRACT"
-    ]
+  "migration_aliases": {
+    "TTRANSPOSE": "TTRANS",
+    "TSORT32": "TSORT"
   },
-  "release_contract": "The v0.57 catalog is the sole active LinxISA catalog. It includes all established instructions and state rules plus the additions and reviewed constraint refinements recorded here."
+  "deleted_names": [
+    "TADDC",
+    "TADDSC",
+    "TFMA",
+    "TFMOD",
+    "TFMODS",
+    "TLRELU",
+    "TRANDOM",
+    "TSUBC",
+    "TSUBSC"
+  ],
+  "rejected_names": [
+    "TEXRACT",
+    "TFILL/TEXPANDS",
+    "TPOW",
+    "TPOWS"
+  ],
+  "elf_identity": {
+    "alignment_bytes": 4,
+    "descriptor_encoding": "UTF-8 JSON with lexicographically sorted keys and no insignificant whitespace",
+    "descriptor_fields": [
+      "release",
+      "encoding_abi",
+      "encoding_projection_sha256"
+    ],
+    "descriptor_nul_terminated": false,
+    "link_policy": "all input identities must be present and exactly equal",
+    "load_policy": "the image identity must exactly match the implementation identity",
+    "name_size_bytes": 4,
+    "note_name": "PTO",
+    "note_type": "PTO_NT_ISA_IDENTITY",
+    "note_type_value": 1,
+    "section": ".note.pto.isa"
+  }
 }
diff --git a/isa/v0.57/state/engine_ops.json b/isa/v0.57/state/engine_ops.json
index 019f0570..6ac2b5b8 100644
--- a/isa/v0.57/state/engine_ops.json
+++ b/isa/v0.57/state/engine_ops.json
@@ -93,144 +93,386 @@
       "7": "RHB"
     }
   },
-  "note": "Authoritative semantic catalog for accelerator engine ops in LinxISA v0.57. v0.57 is the sole active release.",
+  "note": "Linx scheduling metadata projected onto the normative PTO ISA 0.57.1 tile catalog.",
   "profile": "v0.57",
   "tma": {
+    "kind": "function_u5",
     "function_field_bits": [
       0,
       4
     ],
-    "kind": "function_u5",
     "legal_aliases": [
       {
+        "name": "TLOAD",
         "function": 0,
-        "mnemonic": "BSTART.TLOAD"
+        "mnemonic": "BSTART.TLOAD",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TLOAD",
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:address:base-address"
+        ]
       },
       {
+        "name": "TSTORE",
         "function": 1,
-        "mnemonic": "BSTART.TSTORE"
-      },
-      {
-        "function": 2,
-        "mnemonic": "BSTART.TMOV"
+        "mnemonic": "BSTART.TSTORE",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TSTORE",
+        "state_effects": [
+          "operand:address:base-address",
+          "operand:source0:source"
+        ]
       },
       {
+        "name": "TPREFETCH",
         "function": 3,
         "mnemonic": "BSTART.TPREFETCH",
-        "semantic_delta": "Same address, layout, memory, fault, ordering, and restart contract as BSTART.TLOAD, with destination binding, destination allocation, and destination writeback removed."
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TPREFETCH",
+        "state_effects": [
+          "operand:address:base-address",
+          "operand:byte_count:byte-count"
+        ]
       },
       {
+        "name": "MGATHER",
         "function": 4,
-        "mnemonic": "BSTART.MGATHER"
+        "mnemonic": "BSTART.MGATHER",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "MGATHER",
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:address:base-address",
+          "operand:source0:indices"
+        ]
       },
       {
+        "name": "MSCATTER",
         "function": 5,
-        "mnemonic": "BSTART.MSCATTER"
+        "mnemonic": "BSTART.MSCATTER",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "MSCATTER",
+        "state_effects": [
+          "operand:address:base-address",
+          "operand:source0:source",
+          "operand:source1:indices"
+        ]
       },
       {
+        "name": "MGATHER_MASK",
         "function": 6,
-        "mnemonic": "BSTART.MGATHER.MASK"
+        "mnemonic": "BSTART.MGATHER.MASK",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "MGATHER_MASK",
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:address:base-address",
+          "operand:source0:indices",
+          "operand:source1:mask"
+        ]
       },
       {
+        "name": "MSCATTER_MASK",
         "function": 7,
-        "mnemonic": "BSTART.MSCATTER.MASK"
+        "mnemonic": "BSTART.MSCATTER.MASK",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "MSCATTER_MASK",
+        "state_effects": [
+          "operand:address:base-address",
+          "operand:source0:source",
+          "operand:source1:indices",
+          "operand:source2:mask"
+        ]
       },
       {
+        "name": "MGATHER_CAS",
         "function": 8,
-        "mnemonic": "BSTART.MGATHER.CAS"
+        "mnemonic": "BSTART.MGATHER.CAS",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "MGATHER_CAS",
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:address:base-address",
+          "operand:source0:indices",
+          "operand:source1:expected",
+          "operand:source2:replacement"
+        ]
+      },
+      {
+        "name": "TMOV",
+        "function": 2,
+        "mnemonic": "BSTART.TMOV",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TMOV",
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       }
     ],
-    "reserved_behavior": "illegal_instruction",
     "reserved_function_range": [
       9,
       31
-    ]
+    ],
+    "reserved_behavior": "illegal_instruction"
   },
   "cube": {
+    "kind": "function_u5",
     "function_field_bits": [
       0,
       4
     ],
-    "kind": "function_u5",
     "legal_aliases": [
       {
+        "name": "TMATMUL",
         "function": 0,
-        "mnemonic": "BSTART.TMATMUL"
+        "mnemonic": "BSTART.TMATMUL",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TMATMUL",
+        "state_effects": [
+          "operand:source0:left",
+          "operand:source1:right",
+          "implicit:ACC:write-initialize"
+        ]
       },
       {
+        "name": "TMATMUL_BIAS",
         "function": 1,
-        "mnemonic": "BSTART.TMATMUL.BIAS"
+        "mnemonic": "BSTART.TMATMUL.BIAS",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TMATMUL_BIAS",
+        "state_effects": [
+          "operand:source0:left",
+          "operand:source1:right",
+          "operand:source2:bias",
+          "implicit:ACC:write-initialize"
+        ]
       },
       {
+        "name": "TMATMUL_ACC",
         "function": 2,
-        "mnemonic": "BSTART.TMATMUL.ACC"
+        "mnemonic": "BSTART.TMATMUL.ACC",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TMATMUL_ACC",
+        "state_effects": [
+          "operand:source0:left",
+          "operand:source1:right",
+          "implicit:ACC:read-write"
+        ]
       },
       {
+        "name": "TMATMUL_MX",
         "function": 4,
-        "mnemonic": "BSTART.TMATMULMX"
+        "mnemonic": "BSTART.TMATMULMX",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TMATMUL_MX",
+        "state_effects": [
+          "operand:source0:left",
+          "operand:source1:right",
+          "operand:source2:row-scale",
+          "operand:source3:column-scale",
+          "implicit:ACC:write-initialize"
+        ]
       },
       {
+        "name": "TMATMUL_MX_BIAS",
         "function": 5,
-        "mnemonic": "BSTART.TMATMULMX.BIAS"
+        "mnemonic": "BSTART.TMATMULMX.BIAS",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TMATMUL_MX_BIAS",
+        "state_effects": [
+          "operand:source0:left",
+          "operand:source1:right",
+          "operand:source2:row-scale",
+          "operand:source3:column-scale",
+          "operand:source4:bias",
+          "implicit:ACC:write-initialize"
+        ]
       },
       {
+        "name": "TMATMUL_MX_ACC",
         "function": 6,
-        "mnemonic": "BSTART.TMATMULMX.ACC"
+        "mnemonic": "BSTART.TMATMULMX.ACC",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TMATMUL_MX_ACC",
+        "state_effects": [
+          "operand:source0:left",
+          "operand:source1:right",
+          "operand:source2:row-scale",
+          "operand:source3:column-scale",
+          "implicit:ACC:read-write"
+        ]
       },
       {
+        "name": "ACCCVT",
         "function": 8,
-        "mnemonic": "BSTART.ACCCVT"
+        "mnemonic": "BSTART.ACCCVT",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ACCCVT",
+        "state_effects": [
+          "operand:destination0:destination",
+          "implicit:ACC:read-release-on-commit"
+        ]
       },
       {
+        "name": "TGEMV",
         "function": 16,
-        "mnemonic": "BSTART.TGEMV"
+        "mnemonic": "BSTART.TGEMV",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TGEMV",
+        "state_effects": [
+          "operand:source0:matrix",
+          "operand:source1:vector",
+          "implicit:ACC:write-initialize"
+        ]
       },
       {
+        "name": "TGEMV_BIAS",
         "function": 17,
-        "mnemonic": "BSTART.TGEMV.BIAS"
+        "mnemonic": "BSTART.TGEMV.BIAS",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TGEMV_BIAS",
+        "state_effects": [
+          "operand:source0:matrix",
+          "operand:source1:vector",
+          "operand:source2:bias",
+          "implicit:ACC:write-initialize"
+        ]
       },
       {
+        "name": "TGEMV_ACC",
         "function": 18,
-        "mnemonic": "BSTART.TGEMV.ACC"
+        "mnemonic": "BSTART.TGEMV.ACC",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TGEMV_ACC",
+        "state_effects": [
+          "operand:source0:matrix",
+          "operand:source1:vector",
+          "implicit:ACC:read-write"
+        ]
       },
       {
+        "name": "TGEMV_MX",
         "function": 20,
-        "mnemonic": "BSTART.TGEMVMX"
+        "mnemonic": "BSTART.TGEMVMX",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TGEMV_MX",
+        "state_effects": [
+          "operand:source0:matrix",
+          "operand:source1:vector",
+          "operand:source2:row-scale",
+          "operand:source3:column-scale",
+          "implicit:ACC:write-initialize"
+        ]
       },
       {
+        "name": "TGEMV_MX_BIAS",
         "function": 21,
-        "mnemonic": "BSTART.TGEMVMX.BIAS"
+        "mnemonic": "BSTART.TGEMVMX.BIAS",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TGEMV_MX_BIAS",
+        "state_effects": [
+          "operand:source0:matrix",
+          "operand:source1:vector",
+          "operand:source2:row-scale",
+          "operand:source3:column-scale",
+          "operand:source4:bias",
+          "implicit:ACC:write-initialize"
+        ]
       },
       {
+        "name": "TGEMV_MX_ACC",
         "function": 22,
-        "mnemonic": "BSTART.TGEMVMX.ACC"
+        "mnemonic": "BSTART.TGEMVMX.ACC",
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TGEMV_MX_ACC",
+        "state_effects": [
+          "operand:source0:matrix",
+          "operand:source1:vector",
+          "operand:source2:row-scale",
+          "operand:source3:column-scale",
+          "implicit:ACC:read-write"
+        ]
       }
     ],
-    "unassigned_alias_behavior": "inherit_generic_bstart_cube_decode_without_canonical_alias",
-    "unassigned_alias_functions": [
+    "unassigned_function_behavior": "illegal_instruction",
+    "reserved_functions": [
       3,
       7,
-      9,
-      10,
-      11,
-      12,
-      13,
-      14,
-      15,
+      [
+        9,
+        15
+      ],
       19,
-      23,
-      24,
-      25,
-      26,
-      27,
-      28,
-      29,
-      30,
-      31
+      [
+        23,
+        31
+      ]
     ]
   },
   "tepl": {
-    "kind": "TileOpcode",
+    "kind": "mode_function",
+    "selector_formula": "(mode << 5) | function",
+    "mode_field_bits": [
+      0,
+      1
+    ],
+    "function_field_bits": [
+      0,
+      4
+    ],
+    "accepted_selector_count": 98,
+    "reserved_selector_ranges": [
+      [
+        "0x005",
+        "0x005"
+      ],
+      [
+        "0x018",
+        "0x019"
+      ],
+      [
+        "0x01C",
+        "0x01F"
+      ],
+      [
+        "0x025",
+        "0x025"
+      ],
+      [
+        "0x02E",
+        "0x02E"
+      ],
+      [
+        "0x030",
+        "0x039"
+      ],
+      [
+        "0x03C",
+        "0x03F"
+      ],
+      [
+        "0x04E",
+        "0x04F"
+      ],
+      [
+        "0x05E",
+        "0x05F"
+      ],
+      [
+        "0x069",
+        "0x069"
+      ],
+      [
+        "0x07E",
+        "0x07F"
+      ]
+    ],
+    "migration_aliases": {
+      "TTRANSPOSE": "TTRANS",
+      "TSORT32": "TSORT"
+    },
     "ops": [
       {
         "dim_lb_defaults": {
@@ -251,7 +493,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 0
+        "mode": 0,
+        "function": 0,
+        "logical_selector": 0,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -272,7 +541,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 1
+        "mode": 0,
+        "function": 1,
+        "logical_selector": 1,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -293,40 +589,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 2
-      },
-      {
-        "dim_lb_defaults": {
-          "LB1": 1,
-          "LB2": 1
-        },
-        "dim_lb_required": [
-          "LB0"
-        ],
-        "dim_required": true,
-        "dirty_rule": "op-defined",
-        "div_by_zero_result": "0",
-        "div_overflow_result": "0",
-        "dst_tiles": 1,
-        "engineop_state_bytes_max": 0,
-        "engineop_state_version": 0,
-        "has_index_tile": false,
-        "name": "TDIV",
-        "optional_scalar_status": true,
-        "phase_model": "op-defined",
-        "redo_ok_after_start": false,
-        "requires_b_ior": true,
-        "requires_b_iot": true,
-        "resume_ok": false,
-        "scalar_status_flags": [
-          "DIV_BY_ZERO_SEEN",
-          "DIV_OVERFLOW_SEEN",
-          "NAN_SEEN"
+        "mode": 0,
+        "function": 2,
+        "logical_selector": 2,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
         ],
-        "scalar_status_reduce": "or",
-        "src_tiles": 2,
-        "status_absent_behavior": "flags_dropped",
-        "tile_opcode": 3
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -347,7 +637,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 4
+        "mode": 0,
+        "function": 11,
+        "logical_selector": 11,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -368,7 +685,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 5
+        "mode": 0,
+        "function": 12,
+        "logical_selector": 12,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -389,7 +733,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 6
+        "mode": 0,
+        "function": 6,
+        "logical_selector": 6,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -410,7 +781,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 7
+        "mode": 0,
+        "function": 7,
+        "logical_selector": 7,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -431,7 +829,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 8
+        "mode": 0,
+        "function": 8,
+        "logical_selector": 8,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -452,7 +877,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 9
+        "mode": 0,
+        "function": 9,
+        "logical_selector": 9,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -473,7 +925,194 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 10
+        "mode": 0,
+        "function": 10,
+        "logical_selector": 10,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
+      },
+      {
+        "name": "TCMP",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 0,
+        "function": 13,
+        "logical_selector": 13,
+        "semantic_handler": "ExecuteTileCompare",
+        "legality_handler": "TileOperandsLegal_ExecuteTileCompare",
+        "effect_contract": "ExecuteTileCompare",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          },
+          {
+            "field": "comparison",
+            "role": "comparison"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right",
+          "operand:comparison:comparison"
+        ]
+      },
+      {
+        "name": "TSEL",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 0,
+        "function": 26,
+        "logical_selector": 26,
+        "semantic_handler": "ExecuteTileSelect",
+        "legality_handler": "TileOperandsLegal_ExecuteTileSelect",
+        "effect_contract": "ExecuteTileSelect",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "mask"
+          },
+          {
+            "field": "source1",
+            "role": "source-true"
+          },
+          {
+            "field": "source2",
+            "role": "source-false"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:mask",
+          "operand:source1:source-true",
+          "operand:source2:source-false"
+        ]
+      },
+      {
+        "name": "TABS",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 0,
+        "function": 15,
+        "logical_selector": 15,
+        "semantic_handler": "ExecuteTileUnary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+        "effect_contract": "ExecuteTileUnary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
+      },
+      {
+        "name": "TNOT",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 0,
+        "function": 16,
+        "logical_selector": 16,
+        "semantic_handler": "ExecuteTileUnary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+        "effect_contract": "ExecuteTileUnary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
+      },
+      {
+        "name": "TNEG",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 0,
+        "function": 17,
+        "logical_selector": 17,
+        "semantic_handler": "ExecuteTileUnary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+        "effect_contract": "ExecuteTileUnary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -494,7 +1133,29 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 1,
-        "tile_opcode": 11
+        "mode": 0,
+        "function": 23,
+        "logical_selector": 23,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileUnary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+        "effect_contract": "ExecuteTileUnary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -515,7 +1176,34 @@
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 2,
-        "tile_opcode": 12
+        "mode": 0,
+        "function": 14,
+        "logical_selector": 14,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TPRELU",
+        "legality_handler": "TileOperandsLegal_TPRELU",
+        "effect_contract": "TPRELU",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "negative-slope"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:negative-slope"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -527,26 +1215,88 @@
         ],
         "dim_required": true,
         "dirty_rule": "op-defined",
+        "div_by_zero_result": "0",
+        "div_overflow_result": "0",
         "dst_tiles": 1,
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "missing_required_attr_desc_family": "B.CATR/B.DATR",
-        "missing_required_attr_detail": "0x00",
-        "missing_required_attr_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "missing_required_ior_desc_family": "B.IOR",
-        "missing_required_ior_detail": "0x00",
-        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TCVT",
+        "name": "TDIV",
+        "optional_scalar_status": true,
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
-        "requires_b_arg": true,
-        "requires_catr_or_datr": true,
         "requires_b_ior": true,
         "requires_b_iot": true,
         "resume_ok": false,
-        "src_tiles": 1,
-        "tile_opcode": 13
+        "scalar_status_flags": [
+          "DIV_BY_ZERO_SEEN",
+          "DIV_OVERFLOW_SEEN",
+          "NAN_SEEN"
+        ],
+        "scalar_status_reduce": "or",
+        "src_tiles": 2,
+        "status_absent_behavior": "flags_dropped",
+        "mode": 0,
+        "function": 3,
+        "logical_selector": 3,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
+      },
+      {
+        "name": "TREM",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 0,
+        "function": 4,
+        "logical_selector": 4,
+        "semantic_handler": "ExecuteTileBinary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+        "effect_contract": "ExecuteTileBinary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source-left",
+          "operand:source1:source-right"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -561,11 +1311,33 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TEXP",
+        "name": "TSQRT",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
         "resume_ok": false,
-        "tile_opcode": 14
+        "mode": 0,
+        "function": 21,
+        "logical_selector": 21,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileUnary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+        "effect_contract": "ExecuteTileUnary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -584,7 +1356,29 @@
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
         "resume_ok": false,
-        "tile_opcode": 15
+        "mode": 0,
+        "function": 19,
+        "logical_selector": 19,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileUnary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+        "effect_contract": "ExecuteTileUnary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -599,11 +1393,33 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TSQRT",
+        "name": "TRECIP",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
         "resume_ok": false,
-        "tile_opcode": 16
+        "mode": 0,
+        "function": 20,
+        "logical_selector": 20,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileUnary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+        "effect_contract": "ExecuteTileUnary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -618,11 +1434,33 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TRSQRT",
+        "name": "TEXP",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
         "resume_ok": false,
-        "tile_opcode": 17
+        "mode": 0,
+        "function": 18,
+        "logical_selector": 18,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileUnary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+        "effect_contract": "ExecuteTileUnary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -634,16 +1472,36 @@
         ],
         "dim_required": true,
         "dirty_rule": "op-defined",
-        "dst_tiles": 1,
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TROWMAX",
+        "name": "TRSQRT",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
         "resume_ok": false,
-        "src_tiles": 1,
-        "tile_opcode": 18
+        "mode": 0,
+        "function": 22,
+        "logical_selector": 22,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileUnary",
+        "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+        "effect_contract": "ExecuteTileUnary",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -659,12 +1517,81 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TROWMIN",
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TADDS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 19
+        "mode": 1,
+        "function": 0,
+        "logical_selector": 32,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
+      },
+      {
+        "name": "TAXPY",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 1,
+        "function": 15,
+        "logical_selector": 47,
+        "semantic_handler": "ExecuteTileAxpy",
+        "legality_handler": "TileOperandsLegal_ExecuteTileAxpy",
+        "effect_contract": "ExecuteTileAxpy",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -680,12 +1607,48 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TROWSUM",
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TSUBS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 20
+        "mode": 1,
+        "function": 1,
+        "logical_selector": 33,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -701,12 +1664,48 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TCOLMAX",
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TMULS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 21
+        "mode": 1,
+        "function": 2,
+        "logical_selector": 34,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -722,12 +1721,48 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TCOLMIN",
-        "phase_model": "op-defined",
-        "redo_ok_after_start": false,
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TDIVS",
+        "phase_model": "op-defined",
+        "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 22
+        "mode": 1,
+        "function": 3,
+        "logical_selector": 35,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -743,12 +1778,48 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TCOLSUM",
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TMINS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 23
+        "mode": 1,
+        "function": 12,
+        "logical_selector": 44,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -760,14 +1831,85 @@
         ],
         "dim_required": true,
         "dirty_rule": "op-defined",
+        "dst_tiles": 1,
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TRECIP",
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TMAXS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
-        "tile_opcode": 24
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
+        "src_tiles": 1,
+        "mode": 1,
+        "function": 11,
+        "logical_selector": 43,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
+      },
+      {
+        "name": "TREMS",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 1,
+        "function": 4,
+        "logical_selector": 36,
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -786,19 +1928,45 @@
         "missing_required_ior_desc_family": "B.IOR",
         "missing_required_ior_detail": "0x00",
         "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TEXPANDS",
+        "name": "TANDS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
         "requires_b_ior": true,
-        "requires_b_iot": true,
         "resume_ok": false,
         "scalar_rhs_broadcast": true,
         "scalar_rhs_extract": "truncate_low_bits",
         "scalar_rhs_mixed_signedness": false,
         "scalar_rhs_signedness": "match_tile_dtype",
         "scalar_rhs_type": "tile_element_dtype",
-        "src_tiles": 0,
-        "tile_opcode": 25
+        "src_tiles": 1,
+        "mode": 1,
+        "function": 6,
+        "logical_selector": 38,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -810,15 +1978,52 @@
         ],
         "dim_required": true,
         "dirty_rule": "op-defined",
+        "dst_tiles": 1,
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
-        "has_index_tile": true,
-        "index_range_rule": "unpredictable",
-        "name": "TGATHER",
+        "has_index_tile": false,
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TORS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
-        "tile_opcode": 26
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
+        "src_tiles": 1,
+        "mode": 1,
+        "function": 7,
+        "logical_selector": 39,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -830,15 +2035,128 @@
         ],
         "dim_required": true,
         "dirty_rule": "op-defined",
+        "dst_tiles": 1,
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
-        "has_index_tile": true,
-        "index_range_rule": "unpredictable",
-        "name": "TSCATTER",
+        "has_index_tile": false,
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TXORS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
-        "tile_opcode": 27
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
+        "src_tiles": 1,
+        "mode": 1,
+        "function": 8,
+        "logical_selector": 40,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
+      },
+      {
+        "name": "TCMPS",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 1,
+        "function": 13,
+        "logical_selector": 45,
+        "semantic_handler": "ExecuteTileCompareScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileCompareScalar",
+        "effect_contract": "ExecuteTileCompareScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          },
+          {
+            "field": "comparison",
+            "role": "comparison"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar",
+          "operand:comparison:comparison"
+        ]
+      },
+      {
+        "name": "TSELS",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 1,
+        "function": 26,
+        "logical_selector": 58,
+        "semantic_handler": "ExecuteTileSelectScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileSelectScalar",
+        "effect_contract": "ExecuteTileSelectScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "mask"
+          },
+          {
+            "field": "source1",
+            "role": "source-true"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar-false"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:mask",
+          "operand:source1:source-true",
+          "operand:scalar0:scalar-false"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -854,12 +2172,48 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TRESHAPE",
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TSHLS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 28
+        "mode": 1,
+        "function": 9,
+        "logical_selector": 41,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -875,12 +2229,48 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TTRANSPOSE",
+        "missing_required_ior_desc_family": "B.IOR",
+        "missing_required_ior_detail": "0x00",
+        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
+        "name": "TSHRS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_ior": true,
         "resume_ok": false,
+        "scalar_rhs_broadcast": true,
+        "scalar_rhs_extract": "truncate_low_bits",
+        "scalar_rhs_mixed_signedness": false,
+        "scalar_rhs_signedness": "match_tile_dtype",
+        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 29
+        "mode": 1,
+        "function": 10,
+        "logical_selector": 42,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+        "effect_contract": "ExecuteTileScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scalar"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -896,12 +2286,62 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TCOLEXPAND",
+        "name": "TROWSUM",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 1,
-        "tile_opcode": 30
+        "mode": 2,
+        "function": 0,
+        "logical_selector": 64,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
+      },
+      {
+        "name": "TROWPROD",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 3,
+        "logical_selector": 67,
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -917,12 +2357,34 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "name": "TROWEXPAND",
+        "name": "TROWMAX",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
         "resume_ok": false,
         "src_tiles": 1,
-        "tile_opcode": 31
+        "mode": 2,
+        "function": 1,
+        "logical_selector": 65,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -938,21 +2400,90 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "missing_required_ior_desc_family": "B.IOR",
-        "missing_required_ior_detail": "0x00",
-        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TADDS",
+        "name": "TROWMIN",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
-        "requires_b_ior": true,
         "resume_ok": false,
-        "scalar_rhs_broadcast": true,
-        "scalar_rhs_extract": "truncate_low_bits",
-        "scalar_rhs_mixed_signedness": false,
-        "scalar_rhs_signedness": "match_tile_dtype",
-        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 32
+        "mode": 2,
+        "function": 2,
+        "logical_selector": 66,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
+      },
+      {
+        "name": "TROWARGMAX",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 12,
+        "logical_selector": 76,
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
+      },
+      {
+        "name": "TROWARGMIN",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 13,
+        "logical_selector": 77,
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -968,21 +2499,62 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "missing_required_ior_desc_family": "B.IOR",
-        "missing_required_ior_detail": "0x00",
-        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TSUBS",
+        "name": "TCOLSUM",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
-        "requires_b_ior": true,
         "resume_ok": false,
-        "scalar_rhs_broadcast": true,
-        "scalar_rhs_extract": "truncate_low_bits",
-        "scalar_rhs_mixed_signedness": false,
-        "scalar_rhs_signedness": "match_tile_dtype",
-        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 33
+        "mode": 2,
+        "function": 16,
+        "logical_selector": 80,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
+      },
+      {
+        "name": "TCOLPROD",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 19,
+        "logical_selector": 83,
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -998,21 +2570,34 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "missing_required_ior_desc_family": "B.IOR",
-        "missing_required_ior_detail": "0x00",
-        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TMULS",
+        "name": "TCOLMAX",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
-        "requires_b_ior": true,
         "resume_ok": false,
-        "scalar_rhs_broadcast": true,
-        "scalar_rhs_extract": "truncate_low_bits",
-        "scalar_rhs_mixed_signedness": false,
-        "scalar_rhs_signedness": "match_tile_dtype",
-        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 34
+        "mode": 2,
+        "function": 17,
+        "logical_selector": 81,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -1028,21 +2613,90 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "missing_required_ior_desc_family": "B.IOR",
-        "missing_required_ior_detail": "0x00",
-        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TDIVS",
+        "name": "TCOLMIN",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
-        "requires_b_ior": true,
         "resume_ok": false,
-        "scalar_rhs_broadcast": true,
-        "scalar_rhs_extract": "truncate_low_bits",
-        "scalar_rhs_mixed_signedness": false,
-        "scalar_rhs_signedness": "match_tile_dtype",
-        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 35
+        "mode": 2,
+        "function": 18,
+        "logical_selector": 82,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
+      },
+      {
+        "name": "TCOLARGMAX",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 28,
+        "logical_selector": 92,
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
+      },
+      {
+        "name": "TCOLARGMIN",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 29,
+        "logical_selector": 93,
+        "semantic_handler": "ExecuteTileReduction",
+        "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+        "effect_contract": "ExecuteTileReduction",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -1058,29 +2712,278 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "missing_required_ior_desc_family": "B.IOR",
-        "missing_required_ior_detail": "0x00",
-        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TMAXS",
+        "name": "TROWEXPAND",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
-        "requires_b_ior": true,
         "resume_ok": false,
-        "scalar_rhs_broadcast": true,
-        "scalar_rhs_extract": "truncate_low_bits",
-        "scalar_rhs_mixed_signedness": false,
-        "scalar_rhs_signedness": "match_tile_dtype",
-        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 36
+        "mode": 2,
+        "function": 4,
+        "logical_selector": 68,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
       },
       {
-        "dim_lb_defaults": {
-          "LB1": 1,
-          "LB2": 1
-        },
-        "dim_lb_required": [
-          "LB0"
+        "name": "TROWEXPANDADD",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 5,
+        "logical_selector": 69,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TROWEXPANDSUB",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 6,
+        "logical_selector": 70,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TROWEXPANDMUL",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 7,
+        "logical_selector": 71,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TROWEXPANDDIV",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 8,
+        "logical_selector": 72,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TROWEXPANDMAX",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 9,
+        "logical_selector": 73,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TROWEXPANDMIN",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 10,
+        "logical_selector": 74,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TROWEXPANDEXPDIF",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 11,
+        "logical_selector": 75,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "dim_lb_defaults": {
+          "LB1": 1,
+          "LB2": 1
+        },
+        "dim_lb_required": [
+          "LB0"
         ],
         "dim_required": true,
         "dirty_rule": "op-defined",
@@ -1088,21 +2991,270 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
-        "missing_required_ior_desc_family": "B.IOR",
-        "missing_required_ior_detail": "0x00",
-        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TMINS",
+        "name": "TCOLEXPAND",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
-        "requires_b_ior": true,
         "resume_ok": false,
-        "scalar_rhs_broadcast": true,
-        "scalar_rhs_extract": "truncate_low_bits",
-        "scalar_rhs_mixed_signedness": false,
-        "scalar_rhs_signedness": "match_tile_dtype",
-        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 37
+        "mode": 2,
+        "function": 20,
+        "logical_selector": 84,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TCOLEXPANDADD",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 21,
+        "logical_selector": 85,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TCOLEXPANDSUB",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 22,
+        "logical_selector": 86,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TCOLEXPANDMUL",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 23,
+        "logical_selector": 87,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TCOLEXPANDDIV",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 24,
+        "logical_selector": 88,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TCOLEXPANDMAX",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 25,
+        "logical_selector": 89,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TCOLEXPANDMIN",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 26,
+        "logical_selector": 90,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
+      },
+      {
+        "name": "TCOLEXPANDEXPDIF",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 2,
+        "function": 27,
+        "logical_selector": 91,
+        "semantic_handler": "ExecuteTileExpand",
+        "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+        "effect_contract": "ExecuteTileExpand",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "source1",
+            "role": "broadcast-source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:source1:broadcast-source"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -1121,18 +3273,140 @@
         "missing_required_ior_desc_family": "B.IOR",
         "missing_required_ior_detail": "0x00",
         "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TANDS",
+        "name": "TEXPANDS",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
         "requires_b_ior": true,
+        "requires_b_iot": true,
         "resume_ok": false,
         "scalar_rhs_broadcast": true,
         "scalar_rhs_extract": "truncate_low_bits",
         "scalar_rhs_mixed_signedness": false,
         "scalar_rhs_signedness": "match_tile_dtype",
         "scalar_rhs_type": "tile_element_dtype",
-        "src_tiles": 1,
-        "tile_opcode": 38
+        "src_tiles": 0,
+        "mode": 1,
+        "function": 27,
+        "logical_selector": 59,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "ExecuteTileFillScalar",
+        "legality_handler": "TileOperandsLegal_ExecuteTileFillScalar",
+        "effect_contract": "ExecuteTileFillScalar",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "scalar0",
+            "role": "scalar"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:scalar0:scalar"
+        ]
+      },
+      {
+        "name": "TCI",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 3,
+        "function": 6,
+        "logical_selector": 102,
+        "semantic_handler": "TCI",
+        "legality_handler": "TileOperandsLegal_TCI",
+        "effect_contract": "TCI",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "scalar0",
+            "role": "start"
+          },
+          {
+            "field": "flag0",
+            "role": "descending"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:scalar0:start",
+          "operand:flag0:descending"
+        ]
+      },
+      {
+        "name": "TTRI",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 3,
+        "function": 7,
+        "logical_selector": 103,
+        "semantic_handler": "TTRI",
+        "legality_handler": "TileOperandsLegal_TTRI",
+        "effect_contract": "TTRI",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "flag0",
+            "role": "upper"
+          },
+          {
+            "field": "diagonal",
+            "role": "diagonal"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:flag0:upper",
+          "operand:diagonal:diagonal"
+        ]
+      },
+      {
+        "name": "TFILLPAD",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 3,
+        "function": 5,
+        "logical_selector": 101,
+        "semantic_handler": "TFILLPAD",
+        "legality_handler": "TileOperandsLegal_TFILLPAD",
+        "effect_contract": "TFILLPAD",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "padding"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:padding"
+        ]
       },
       {
         "dim_lb_defaults": {
@@ -1148,21 +3422,196 @@
         "engineop_state_bytes_max": 0,
         "engineop_state_version": 0,
         "has_index_tile": false,
+        "missing_required_attr_desc_family": "B.CATR/B.DATR",
+        "missing_required_attr_detail": "0x00",
+        "missing_required_attr_trap": "E_BLOCK(EC_BLOCKFMT)",
         "missing_required_ior_desc_family": "B.IOR",
         "missing_required_ior_detail": "0x00",
         "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TORS",
+        "name": "TCVT",
         "phase_model": "op-defined",
         "redo_ok_after_start": false,
+        "requires_b_arg": true,
+        "requires_catr_or_datr": true,
         "requires_b_ior": true,
+        "requires_b_iot": true,
         "resume_ok": false,
-        "scalar_rhs_broadcast": true,
-        "scalar_rhs_extract": "truncate_low_bits",
-        "scalar_rhs_mixed_signedness": false,
-        "scalar_rhs_signedness": "match_tile_dtype",
-        "scalar_rhs_type": "tile_element_dtype",
         "src_tiles": 1,
-        "tile_opcode": 39
+        "mode": 0,
+        "function": 27,
+        "logical_selector": 27,
+        "semantic_status": "reviewed-complete",
+        "semantic_handler": "TCVT",
+        "legality_handler": "TileOperandsLegal_TCVT",
+        "effect_contract": "TCVT",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source"
+        ]
+      },
+      {
+        "name": "TQUANT",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 3,
+        "function": 10,
+        "logical_selector": 106,
+        "semantic_handler": "TQUANT",
+        "legality_handler": "TileOperandsLegal_TQUANT",
+        "effect_contract": "TQUANT",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
+            "field": "scalar0",
+            "role": "scale"
+          },
+          {
+            "field": "scalar1",
+            "role": "zero-point"
+          }
+        ],
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:source0:source",
+          "operand:scalar0:scale",
+          "operand:scalar1:zero-point"
+        ]
+      },
+      {
+        "name": "TDEQUANT",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 3,
+        "function": 11,
+        "logical_selector": 107,
+        "semantic_handler": "TDEQUANT",
+        "legality_handler": "TileOperandsLegal_TDEQUANT",
+        "effect_contract": "TDEQUANT",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
+            "field": "source0",
+            "role": "source"
+          },
+          {
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+          "operand:natural1:column-offset"
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+        "semantic_handler": "TINSERT",
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+        "effect_contract": "TINSERT",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
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+          "operand:natural0:row-offset",
+          "operand:natural1:column-offset"
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@@ -1174,25 +3623,42 @@
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-        "name": "TXORS",
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+        "effect_contract": "TGATHER",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
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+          },
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+          {
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+          "operand:source0:source",
+          "operand:source1:indices"
+        ]
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@@ -1204,25 +3670,80 @@
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-        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
-        "name": "TSHLS",
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+        "semantic_status": "reviewed-complete",
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+        "effect_contract": "TSCATTER",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
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+          }
+        ],
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+          "operand:source0:source",
+          "operand:source1:indices"
+        ]
+      },
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+        "name": "TCONCAT",
+        "profile": "v0.57",
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
+        "mode": 3,
+        "function": 0,
+        "logical_selector": 96,
+        "semantic_handler": "TCONCAT",
+        "legality_handler": "TileOperandsLegal_TCONCAT",
+        "effect_contract": "TCONCAT",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+        "operands": [
+          {
+            "field": "destination0",
+            "role": "destination"
+          },
+          {
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+            "role": "source-left"
+          },
+          {
+            "field": "source1",
+            "role": "source-right"
+          },
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+          "operand:source0:source-left",
+          "operand:source1:source-right",
+          "operand:axis:axis"
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@@ -1238,540 +3759,730 @@
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-        "missing_required_ior_trap": "E_BLOCK(EC_BLOCKFMT)",
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         "phase_model": "op-defined",
         "redo_ok_after_start": false,
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+        "effect_contract": "TTRANS",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
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+          },
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+            "role": "pad-columns"
+          },
+          {
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+          }
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+          "operand:positive0:kernel-rows",
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+          "operand:natural0:pad-rows",
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-        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7"
+        "semantic_status": "reviewed-complete",
+        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7",
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+        "function": 1,
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+        "semantic_handler": "TGATHERB",
+        "legality_handler": "TileOperandsLegal_TGATHERB",
+        "effect_contract": "TGATHERB",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
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+          },
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+          },
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+            "role": "byte-offsets"
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-        "allocation_source": "isa-golden-v0.57-upgrade.md Section 3.7"
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+        "semantic_handler": "TDEINTERLEAVE",
+        "legality_handler": "TileOperandsLegal_TDEINTERLEAVE",
+        "effect_contract": "TDEINTERLEAVE",
+        "fault_contract": "ExecuteTileInstruction",
+        "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
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+            "role": "destination-even"
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+          },
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+          }
+        ],
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+          {
+            "field": "source1",
+            "role": "source-right"
+          },
+          {
+            "field": "source2",
+            "role": "left-indices"
+          },
+          {
+            "field": "source3",
+            "role": "right-indices"
+          }
         ],
-        [
-          228,
-          1023
+        "state_effects": [
+          "operand:destination0:destination",
+          "operand:destination1:destination-indices",
+          "operand:source0:source-left",
+          "operand:source1:source-right",
+          "operand:source2:left-indices",
+          "operand:source3:right-indices"
         ]
-      ],
-      "manifest_files": [
-        "isa/v0.57/state/pto_ops.json",
-        "isa/v0.57/state/pto_encoding_map.json"
-      ]
-    }
+      }
+    ]
   },
   "tile_capacity_model": {
+    "kind": "dynamic_per_descriptor",
+    "cell_bytes": 128,
+    "cells_per_pe": 2048,
+    "capacity_bytes_per_pe": 262144,
     "b_iot_size_imm4_bytes": [
-      0,
-      32,
-      64,
+      null,
+      null,
+      null,
       128,
       256,
       512,
@@ -1779,18 +4490,19 @@
       2048,
       4096,
       8192,
-      16384,
-      32768,
-      65536,
-      131072,
-      262144,
-      524288
+      null,
+      null,
+      null,
+      null,
+      null,
+      null
     ],
-    "empty_tile_bytes": 0,
-    "kind": "dynamic_per_descriptor",
-    "normal_tile_max_bytes": 262144,
-    "normal_tile_min_bytes": 256,
-    "physical_contiguity": "required",
-    "thread_total_active_bytes_max": 524288
-  }
+    "normal_tile_min_bytes": 128,
+    "normal_tile_max_bytes": 8192,
+    "resource_shortage": "precise_allocation_trap",
+    "eviction_or_spill": "forbidden",
+    "physical_contiguity": "required"
+  },
+  "version": "0.57.1",
+  "source_lock": "isa/v0.57/pto-spec.lock.json"
 }
diff --git a/isa/v0.57/state/pto_command_forms.json b/isa/v0.57/state/pto_command_forms.json
new file mode 100644
index 00000000..1827208e
--- /dev/null
+++ b/isa/v0.57/state/pto_command_forms.json
@@ -0,0 +1,5349 @@
+{
+  "form_count": 99,
+  "form_constraint_count": 35,
+  "forms": [
+    {
+      "asm": "B.CATR {trap, atomic, <aq, rl, aqrl>, far, dr}",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xfbf07fff",
+          "match": "0x00000023",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DR",
+          "pieces": [
+            {
+              "instruction_lsb": 26,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "trap",
+          "pieces": [
+            {
+              "instruction_lsb": 19,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "far",
+          "pieces": [
+            {
+              "instruction_lsb": 18,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "atom",
+          "pieces": [
+            {
+              "instruction_lsb": 17,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "aq",
+          "pieces": [
+            {
+              "instruction_lsb": 16,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "rl",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        }
+      ],
+      "form_id": "b_catr_32_e90bd52fa480",
+      "length_bits": 32,
+      "mnemonic": "B.CATR",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Control Attribute",
+      "semantic_handler": "SetBundleControlAttributes",
+      "semantic_summary": "Latches bundle control, trap, atomic, ordering, and address-class attributes.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.DATR {layout, datatype, padvalue_or_byteid, cmode, rmode, sat, canonicalize}",
+      "constraints": [
+        {
+          "field": "CMode",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5
+          ]
+        },
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        },
+        {
+          "field": "Layout",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            3,
+            4,
+            6,
+            8,
+            9,
+            17,
+            18,
+            20,
+            27,
+            28,
+            30
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x000c707f",
+          "match": "0x00001023",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "CMode",
+          "pieces": [
+            {
+              "instruction_lsb": 29,
+              "value_lsb": 0,
+              "width": 3
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 3
+        },
+        {
+          "name": "PadValueOrByteId",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 2
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 2
+        },
+        {
+          "name": "Sat",
+          "pieces": [
+            {
+              "instruction_lsb": 26,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "Canonicalize",
+          "pieces": [
+            {
+              "instruction_lsb": 25,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RMode",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 3
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 3
+        },
+        {
+          "name": "Layout",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "b_datr_32_c161a042ff38",
+      "length_bits": 32,
+      "mnemonic": "B.DATR",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Data Attribute",
+      "semantic_handler": "SetBundleDataAttributes",
+      "semantic_summary": "Latches tile layout, data type, padding, conversion, rounding, and saturation attributes.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.DIM RegSrc, uimm, ->LB2",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000707f",
+          "match": "0x00002043",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "RegSrc",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "uimm17",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 12
+            },
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 12,
+              "width": 5
+            }
+          ],
+          "signedness": "unsigned",
+          "width": 17
+        }
+      ],
+      "form_id": "b_dim_32_1caa1aa2944a",
+      "length_bits": 32,
+      "mnemonic": "B.DIM",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Argument",
+      "semantic_handler": "SetBundleDimension",
+      "semantic_summary": "Writes one of the three bundle-local dimension registers.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.DIM RegSrc, uimm, ->LB0",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000707f",
+          "match": "0x00000043",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "RegSrc",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "uimm17",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 12
+            },
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 12,
+              "width": 5
+            }
+          ],
+          "signedness": "unsigned",
+          "width": 17
+        }
+      ],
+      "form_id": "b_dim_32_27602ab68929",
+      "length_bits": 32,
+      "mnemonic": "B.DIM",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Argument",
+      "semantic_handler": "SetBundleDimension",
+      "semantic_summary": "Writes one of the three bundle-local dimension registers.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.DIM RegSrc, uimm, ->LB1",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000707f",
+          "match": "0x00001043",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "RegSrc",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "uimm17",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 12
+            },
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 12,
+              "width": 5
+            }
+          ],
+          "signedness": "unsigned",
+          "width": 17
+        }
+      ],
+      "form_id": "b_dim_32_4191099a5f4d",
+      "length_bits": 32,
+      "mnemonic": "B.DIM",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Argument",
+      "semantic_handler": "SetBundleDimension",
+      "semantic_summary": "Writes one of the three bundle-local dimension registers.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.HINT {BR.{likely, unlikely}, TEMP.{hot, warm, cool, none}, PRFSIZE}",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00087fff",
+          "match": "0x00000033",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "L/UL",
+          "pieces": [
+            {
+              "instruction_lsb": 16,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "V",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "prefetch_size",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 12
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 12
+        },
+        {
+          "name": "temp",
+          "pieces": [
+            {
+              "instruction_lsb": 17,
+              "value_lsb": 0,
+              "width": 2
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 2
+        }
+      ],
+      "form_id": "b_hint_32_69d942ff1583",
+      "length_bits": 32,
+      "mnemonic": "B.HINT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Hint",
+      "semantic_handler": "SetBundleHint",
+      "semantic_summary": "Records non-functional branch, temperature, prefetch-size, or trace guidance.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.HINT TRACE.{begin, end}",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffff7fff",
+          "match": "0x00001033",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "B/E",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        }
+      ],
+      "form_id": "b_hint_32_f7d01d734925",
+      "length_bits": 32,
+      "mnemonic": "B.HINT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Hint",
+      "semantic_handler": "SetBundleHint",
+      "semantic_summary": "Records non-functional branch, temperature, prefetch-size, or trace guidance.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.IOR [RegSrc0, RegSrc1, RegSrc2],[RegDst]",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0600707f",
+          "match": "0x00000013",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "RegDst",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc0",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc1",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc2",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "b_ior_32_c3ea71404eb3",
+      "length_bits": 32,
+      "mnemonic": "B.IOR",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Input & Output",
+      "semantic_handler": "BindBundleScalarIO",
+      "semantic_summary": "Binds encoded scalar inputs and outputs to the current bundle interface.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.IOT SrcTile0<.reuse>, <last>, ->DstTile<Size>",
+      "constraints": [
+        {
+          "field": "DstTile",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3
+          ]
+        },
+        {
+          "field": "imm4",
+          "operator": "one-of",
+          "values": [
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xfc00787f",
+          "match": "0x00005013",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "SrcTile0",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 6
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 6
+        },
+        {
+          "name": "L",
+          "pieces": [
+            {
+              "instruction_lsb": 19,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "imm4",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 4
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 4
+        },
+        {
+          "name": "S0R",
+          "pieces": [
+            {
+              "instruction_lsb": 10,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "DstTile",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 3
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 3
+        }
+      ],
+      "form_id": "b_iot_32_10db6db84f5d",
+      "length_bits": 32,
+      "mnemonic": "B.IOT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Input & Output",
+      "semantic_handler": "BindBundleTileIO",
+      "semantic_summary": "Binds encoded tile inputs and outputs, reuse, last-use, and allocation-size metadata.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0007f3ff",
+          "match": "0x00004013",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "SrcTile1",
+          "pieces": [
+            {
+              "instruction_lsb": 26,
+              "value_lsb": 0,
+              "width": 6
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 6
+        },
+        {
+          "name": "SrcTile0",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 6
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 6
+        },
+        {
+          "name": "L",
+          "pieces": [
+            {
+              "instruction_lsb": 19,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "S1R",
+          "pieces": [
+            {
+              "instruction_lsb": 11,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "S0R",
+          "pieces": [
+            {
+              "instruction_lsb": 10,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        }
+      ],
+      "form_id": "b_iot_32_2c07e7177fad",
+      "length_bits": 32,
+      "mnemonic": "B.IOT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Input & Output",
+      "semantic_handler": "BindBundleTileIO",
+      "semantic_summary": "Binds encoded tile inputs and outputs, reuse, last-use, and allocation-size metadata.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.IOT SrcTile0<.reuse>, SrcTile1<.reuse>, <last>, ->DstTile<Size>",
+      "constraints": [
+        {
+          "field": "DstTile",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3
+          ]
+        },
+        {
+          "field": "imm4",
+          "operator": "one-of",
+          "values": [
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000707f",
+          "match": "0x00004013",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "SrcTile1",
+          "pieces": [
+            {
+              "instruction_lsb": 26,
+              "value_lsb": 0,
+              "width": 6
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 6
+        },
+        {
+          "name": "SrcTile0",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 6
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 6
+        },
+        {
+          "name": "L",
+          "pieces": [
+            {
+              "instruction_lsb": 19,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "imm4",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 4
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 4
+        },
+        {
+          "name": "S1R",
+          "pieces": [
+            {
+              "instruction_lsb": 11,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "S0R",
+          "pieces": [
+            {
+              "instruction_lsb": 10,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "DstTile",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 3
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 3
+        }
+      ],
+      "form_id": "b_iot_32_8b8bce6bffe8",
+      "length_bits": 32,
+      "mnemonic": "B.IOT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Input & Output",
+      "semantic_handler": "BindBundleTileIO",
+      "semantic_summary": "Binds encoded tile inputs and outputs, reuse, last-use, and allocation-size metadata.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.IOT SrcTile0<.reuse>, <last>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xfc07fbff",
+          "match": "0x00005013",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "SrcTile0",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 6
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 6
+        },
+        {
+          "name": "L",
+          "pieces": [
+            {
+              "instruction_lsb": 19,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "S0R",
+          "pieces": [
+            {
+              "instruction_lsb": 10,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        }
+      ],
+      "form_id": "b_iot_32_c11eb189dd83",
+      "length_bits": 32,
+      "mnemonic": "B.IOT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Input & Output",
+      "semantic_handler": "BindBundleTileIO",
+      "semantic_summary": "Binds encoded tile inputs and outputs, reuse, last-use, and allocation-size metadata.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.IOT <last>, ->DstTile<Size>",
+      "constraints": [
+        {
+          "field": "DstTile",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3
+          ]
+        },
+        {
+          "field": "imm4",
+          "operator": "one-of",
+          "values": [
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xfff07c7f",
+          "match": "0x00006013",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "L",
+          "pieces": [
+            {
+              "instruction_lsb": 19,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "imm4",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 4
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 4
+        },
+        {
+          "name": "DstTile",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 3
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 3
+        }
+      ],
+      "form_id": "b_iot_32_efa0fe3fe49a",
+      "length_bits": 32,
+      "mnemonic": "B.IOT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Input & Output",
+      "semantic_handler": "BindBundleTileIO",
+      "semantic_summary": "Binds encoded tile inputs and outputs, reuse, last-use, and allocation-size metadata.",
+      "status": "accepted"
+    },
+    {
+      "asm": "B.TEXT <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x00000003",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm25",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            }
+          ],
+          "signedness": "signed",
+          "width": 25
+        }
+      ],
+      "form_id": "b_text_32_1ce09f50e5dd",
+      "length_bits": 32,
+      "mnemonic": "B.TEXT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Offset",
+      "semantic_handler": "SetBundleBodyAddress",
+      "semantic_summary": "Sets the out-of-line body entry address for a decoupled bundle.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART {DIRECT, CALL}, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x00000011",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm25",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            }
+          ],
+          "signedness": "signed",
+          "width": 25
+        }
+      ],
+      "form_id": "bstart_32_7eb93b649748",
+      "length_bits": 32,
+      "mnemonic": "BSTART",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART COND, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x00000021",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm25",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            }
+          ],
+          "signedness": "signed",
+          "width": 25
+        }
+      ],
+      "form_id": "bstart_32_e11e678a32ac",
+      "length_bits": 32,
+      "mnemonic": "BSTART",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.CALL <br_label>, <rt_label>, ->ra",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xf83f000f",
+          "match": "0x50160002",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm12",
+          "pieces": [
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 0,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 12
+        },
+        {
+          "name": "uimm5",
+          "pieces": [
+            {
+              "instruction_lsb": 22,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "unsigned",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_call_32_9404418d1ae5",
+      "length_bits": 32,
+      "mnemonic": "BSTART CALL",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.ACCCVT DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00831181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_acccvt_32_56c3ce3838c5",
+      "length_bits": 32,
+      "mnemonic": "BSTART.ACCCVT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.FP RET",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffffffff",
+          "match": "0x00007101",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [],
+      "form_id": "bstart_fp_32_0c671a644214",
+      "length_bits": 32,
+      "mnemonic": "BSTART.FP",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.FP ICALL",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffffffff",
+          "match": "0x00006101",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [],
+      "form_id": "bstart_fp_32_24db3966d6ba",
+      "length_bits": 32,
+      "mnemonic": "BSTART.FP",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.FP COND, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00003101",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm17",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 17
+        }
+      ],
+      "form_id": "bstart_fp_32_58ad7954fb49",
+      "length_bits": 32,
+      "mnemonic": "BSTART.FP",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.FP IND",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffffffff",
+          "match": "0x00005101",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [],
+      "form_id": "bstart_fp_32_7978795a29a1",
+      "length_bits": 32,
+      "mnemonic": "BSTART.FP",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.FP DIRECT, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00002101",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm17",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 17
+        }
+      ],
+      "form_id": "bstart_fp_32_d00a708a81f0",
+      "length_bits": 32,
+      "mnemonic": "BSTART.FP",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.FP CALL, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00004101",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm17",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 17
+        }
+      ],
+      "form_id": "bstart_fp_32_dd7bc8dd694c",
+      "length_bits": 32,
+      "mnemonic": "BSTART.FP",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.FP FALL<, fixup_label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00001101",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm17",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 17
+        }
+      ],
+      "form_id": "bstart_fp_32_face4f238d84",
+      "length_bits": 32,
+      "mnemonic": "BSTART.FP",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.MGATHER DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00411181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_mgather_32_c9defbf18276",
+      "length_bits": 32,
+      "mnemonic": "BSTART.MGATHER",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.MGATHER.CAS DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00811181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_mgather_cas_32_fd8c8a3b720a",
+      "length_bits": 32,
+      "mnemonic": "BSTART.MGATHER.CAS",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.MGATHER.MASK DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00611181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_mgather_mask_32_5573241cd944",
+      "length_bits": 32,
+      "mnemonic": "BSTART.MGATHER.MASK",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.MPAR <VS8, VS16>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xf9ffffff",
+          "match": "0x00001181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "Mode",
+          "pieces": [
+            {
+              "instruction_lsb": 25,
+              "value_lsb": 0,
+              "width": 2
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 2
+        }
+      ],
+      "form_id": "bstart_mpar_32_2d163417c615",
+      "length_bits": 32,
+      "mnemonic": "BSTART.MPAR",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.MSCATTER DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00511181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_mscatter_32_0f0ba08bd798",
+      "length_bits": 32,
+      "mnemonic": "BSTART.MSCATTER",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.MSCATTER.MASK DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00711181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_mscatter_mask_32_2a33eed646f7",
+      "length_bits": 32,
+      "mnemonic": "BSTART.MSCATTER.MASK",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.MSEQ <VS8, VS16>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xf9ffffff",
+          "match": "0x00009181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "Mode",
+          "pieces": [
+            {
+              "instruction_lsb": 25,
+              "value_lsb": 0,
+              "width": 2
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 2
+        }
+      ],
+      "form_id": "bstart_mseq_32_39343a456ec5",
+      "length_bits": 32,
+      "mnemonic": "BSTART.MSEQ",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.STD COND, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00003001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm17",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 17
+        }
+      ],
+      "form_id": "bstart_std_32_1ef99c4cedcb",
+      "length_bits": 32,
+      "mnemonic": "BSTART.STD",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.STD ICALL",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffffffff",
+          "match": "0x00006001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [],
+      "form_id": "bstart_std_32_3f6980d013f7",
+      "length_bits": 32,
+      "mnemonic": "BSTART.STD",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.STD FALL<, fixup_label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00001001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm17",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 17
+        }
+      ],
+      "form_id": "bstart_std_32_441ad677fffe",
+      "length_bits": 32,
+      "mnemonic": "BSTART.STD",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.STD RET",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffffffff",
+          "match": "0x00007001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [],
+      "form_id": "bstart_std_32_816dfa76cc4a",
+      "length_bits": 32,
+      "mnemonic": "BSTART.STD",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.STD IND",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffffffff",
+          "match": "0x00005001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [],
+      "form_id": "bstart_std_32_986b7ee2cf6a",
+      "length_bits": 32,
+      "mnemonic": "BSTART.STD",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.STD CALL, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00004001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm17",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 17
+        }
+      ],
+      "form_id": "bstart_std_32_b05390d367cf",
+      "length_bits": 32,
+      "mnemonic": "BSTART.STD",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.STD DIRECT, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00002001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm17",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 17
+        }
+      ],
+      "form_id": "bstart_std_32_c1de85e06878",
+      "length_bits": 32,
+      "mnemonic": "BSTART.STD",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.SYS FALL<, fixup_label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00001081",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "simm17",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 17
+        }
+      ],
+      "form_id": "bstart_sys_32_762d9d84a6d8",
+      "length_bits": 32,
+      "mnemonic": "BSTART.SYS",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TEPL Mode, Function, DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x000fffff",
+          "match": "0x00019181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "Mode",
+          "pieces": [
+            {
+              "instruction_lsb": 25,
+              "value_lsb": 0,
+              "width": 2
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 2
+        },
+        {
+          "name": "Function",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tepl_32_d022db6dacb3",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TEPL",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TGEMV DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x01031181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tgemv_32_ae19f5b678f5",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TGEMV",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TGEMV.ACC DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x01231181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tgemv_acc_32_9a471b21913e",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TGEMV.ACC",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TGEMV.BIAS DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x01131181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tgemv_bias_32_186ee96c0a8b",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TGEMV.BIAS",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TGEMVMX DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x01431181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tgemvmx_32_ae5e005f6589",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TGEMVMX",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TGEMVMX.ACC DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x01631181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tgemvmx_acc_32_368647b04bb0",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TGEMVMX.ACC",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TGEMVMX.BIAS DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x01531181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tgemvmx_bias_32_d23011f15171",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TGEMVMX.BIAS",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TLOAD DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00011181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tload_32_d0c18bb0ab15",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TLOAD",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TMATMUL DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00031181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tmatmul_32_f9da70e4e0ad",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TMATMUL",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TMATMUL.ACC DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00231181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tmatmul_acc_32_0c8c62e5f00a",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TMATMUL.ACC",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TMATMUL.BIAS DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00131181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tmatmul_bias_32_4d5a498d12f3",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TMATMUL.BIAS",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TMATMULMX DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00431181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tmatmulmx_32_e26cb3874648",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TMATMULMX",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TMATMULMX.ACC DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00631181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tmatmulmx_acc_32_70fa59b0ab4c",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TMATMULMX.ACC",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TMATMULMX.BIAS DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00531181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tmatmulmx_bias_32_098c7efa51b0",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TMATMULMX.BIAS",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TMOV DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00211181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tmov_32_211446509efb",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TMOV",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TPREFETCH DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00311181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tprefetch_32_d5f83e5aadf6",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TPREFETCH",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTART.TSTORE DataType",
+      "constraints": [
+        {
+          "field": "DataType",
+          "operator": "one-of",
+          "values": [
+            0,
+            1,
+            2,
+            3,
+            4,
+            5,
+            6,
+            7,
+            8,
+            9,
+            10,
+            11,
+            12,
+            13,
+            14,
+            16,
+            17,
+            18,
+            19,
+            20,
+            24,
+            25,
+            26,
+            27,
+            28
+          ]
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x07ffffff",
+          "match": "0x00111181",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DataType",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "bstart_tstore_32_4048b6e8b0f4",
+      "length_bits": 32,
+      "mnemonic": "BSTART.TSTORE",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "BSTOP",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffffffff",
+          "match": "0x00000001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [],
+      "form_id": "bstop_32_d25b09fdd59c",
+      "length_bits": 32,
+      "mnemonic": "BSTOP",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStop",
+      "semantic_summary": "Commits the current bundle and transfers to its selected continuation.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.B.DIM RegSrc, ->{LB0, LB1, LB2}",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xc03f",
+          "match": "0xc03c",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [
+        {
+          "name": "LoopNest",
+          "pieces": [
+            {
+              "instruction_lsb": 11,
+              "value_lsb": 0,
+              "width": 3
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 3
+        },
+        {
+          "name": "RegSrc",
+          "pieces": [
+            {
+              "instruction_lsb": 6,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "c_b_dim_16_14f1b8fba5e6",
+      "length_bits": 16,
+      "mnemonic": "C.B.DIM",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Dimension",
+      "semantic_handler": "SetBundleDimension",
+      "semantic_summary": "Writes one of the three bundle-local dimension registers.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.B.DIMI imm, ->{LB0, LB1, LB2}",
+      "constraints": [
+        {
+          "field": "LoopNest",
+          "operator": "not-equal",
+          "value": 3
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x003f",
+          "match": "0x003c",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [
+        {
+          "name": "LoopNest",
+          "pieces": [
+            {
+              "instruction_lsb": 14,
+              "value_lsb": 0,
+              "width": 2
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 2
+        },
+        {
+          "name": "imm8",
+          "pieces": [
+            {
+              "instruction_lsb": 6,
+              "value_lsb": 0,
+              "width": 8
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 8
+        }
+      ],
+      "form_id": "c_b_dimi_16_3f1b113c76ce",
+      "length_bits": 16,
+      "mnemonic": "C.B.DIMI",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Dimension",
+      "semantic_handler": "SetBundleDimension",
+      "semantic_summary": "Writes one of the three bundle-local dimension registers.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.BSTART COND,  label",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x000f",
+          "match": "0x0004",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [
+        {
+          "name": "simm12",
+          "pieces": [
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 0,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 12
+        }
+      ],
+      "form_id": "c_bstart_16_c4e238a9227a",
+      "length_bits": 16,
+      "mnemonic": "C.BSTART",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.BSTART DIRECT, label",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x000f",
+          "match": "0x0002",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [
+        {
+          "name": "simm12",
+          "pieces": [
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 0,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 12
+        }
+      ],
+      "form_id": "c_bstart_16_f833d2a4753c",
+      "length_bits": 16,
+      "mnemonic": "C.BSTART",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.BSTART.FP BrType",
+      "constraints": [
+        {
+          "field": "BrType",
+          "operator": "not-equal",
+          "value": 0
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xc7ff",
+          "match": "0x0080",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [
+        {
+          "name": "BrType",
+          "pieces": [
+            {
+              "instruction_lsb": 11,
+              "value_lsb": 0,
+              "width": 3
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 3
+        }
+      ],
+      "form_id": "c_bstart_fp_16_9dcef7e3a85b",
+      "length_bits": 16,
+      "mnemonic": "C.BSTART.FP",
+      "semantic_family": "BBD",
+      "semantic_group": "C.BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.BSTART.MPAR FALL",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffff",
+          "match": "0x08c0",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [],
+      "form_id": "c_bstart_mpar_16_66c3ef2226ec",
+      "length_bits": 16,
+      "mnemonic": "C.BSTART.MPAR",
+      "semantic_family": "BBD",
+      "semantic_group": "C.BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.BSTART.MSEQ FALL",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffff",
+          "match": "0x48c0",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [],
+      "form_id": "c_bstart_mseq_16_b5597e0e41c2",
+      "length_bits": 16,
+      "mnemonic": "C.BSTART.MSEQ",
+      "semantic_family": "BBD",
+      "semantic_group": "C.BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.BSTART.STD BrType",
+      "constraints": [
+        {
+          "field": "BrType",
+          "operator": "not-equal",
+          "value": 0
+        }
+      ],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xc7ff",
+          "match": "0x0000",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [
+        {
+          "name": "BrType",
+          "pieces": [
+            {
+              "instruction_lsb": 11,
+              "value_lsb": 0,
+              "width": 3
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 3
+        }
+      ],
+      "form_id": "c_bstart_std_16_8b40f078c14a",
+      "length_bits": 16,
+      "mnemonic": "C.BSTART.STD",
+      "semantic_family": "BBD",
+      "semantic_group": "C.BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.BSTART.SYS FALL",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffff",
+          "match": "0x0840",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [],
+      "form_id": "c_bstart_sys_16_ec213ce96eb7",
+      "length_bits": 16,
+      "mnemonic": "C.BSTART.SYS",
+      "semantic_family": "BBD",
+      "semantic_group": "C.BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "C.BSTOP",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xffff",
+          "match": "0x0000",
+          "width_bits": 16
+        }
+      ],
+      "encoding_kind": "C16",
+      "fields": [],
+      "form_id": "c_bstop_16_ca4743d8a95e",
+      "length_bits": 16,
+      "mnemonic": "C.BSTOP",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteBundleStop",
+      "semantic_summary": "Commits the current bundle and transfers to its selected continuation.",
+      "status": "accepted"
+    },
+    {
+      "asm": "ERCOV [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind]",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x06007fff",
+          "match": "0x00003031",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "RegSrc0",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc1",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc2",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "ercov_32_dc0be14a2d8b",
+      "length_bits": 32,
+      "mnemonic": "ERCOV",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "RecoverExecutionContext",
+      "semantic_summary": "Recovers the encoded execution-context range from memory.",
+      "status": "accepted"
+    },
+    {
+      "asm": "ESAVE [RegSrc0=BasePtr, RegSrc1=LenBytes, RegSrc2=Kind]",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x06007fff",
+          "match": "0x00002031",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "RegSrc0",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc1",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc2",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "esave_32_4c4f79fe3171",
+      "length_bits": 32,
+      "mnemonic": "ESAVE",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "SaveExecutionContext",
+      "semantic_summary": "Saves the encoded execution-context range to memory.",
+      "status": "accepted"
+    },
+    {
+      "asm": "FENTRY [RegSrc0 ~ RegSrcn], sp!, uimm",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000707f",
+          "match": "0x00000041",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "SrcBegin",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "SrcEnd",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "uimm",
+          "pieces": [
+            {
+              "instruction_lsb": 25,
+              "value_lsb": 3,
+              "width": 7
+            },
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 10,
+              "width": 5
+            }
+          ],
+          "signedness": "unsigned",
+          "width": 15
+        }
+      ],
+      "form_id": "fentry_32_a47584ec13b6",
+      "length_bits": 32,
+      "mnemonic": "FENTRY",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteFrameEntry",
+      "semantic_summary": "Atomically validates and creates a frame-template entry state.",
+      "status": "accepted"
+    },
+    {
+      "asm": "FEXIT [RegDst0 ~ RegDstn], sp!, uimm",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000707f",
+          "match": "0x00001041",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DstBegin",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "DstEnd",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "uimm",
+          "pieces": [
+            {
+              "instruction_lsb": 25,
+              "value_lsb": 3,
+              "width": 7
+            },
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 10,
+              "width": 5
+            }
+          ],
+          "signedness": "unsigned",
+          "width": 15
+        }
+      ],
+      "form_id": "fexit_32_37b663f2a34d",
+      "length_bits": 32,
+      "mnemonic": "FEXIT",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteFrameExit",
+      "semantic_summary": "Atomically validates and commits a frame-template exit state.",
+      "status": "accepted"
+    },
+    {
+      "asm": "FRET.RA [RegDst0 ~ RegDstn], sp!, uimm",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000707f",
+          "match": "0x00002041",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DstBegin",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "DstEnd",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "uimm",
+          "pieces": [
+            {
+              "instruction_lsb": 25,
+              "value_lsb": 3,
+              "width": 7
+            },
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 10,
+              "width": 5
+            }
+          ],
+          "signedness": "unsigned",
+          "width": 15
+        }
+      ],
+      "form_id": "fret_ra_32_659c886221c1",
+      "length_bits": 32,
+      "mnemonic": "FRET.RA",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteFrameReturnAddress",
+      "semantic_summary": "Restores a frame and returns through the retained return-address target.",
+      "status": "accepted"
+    },
+    {
+      "asm": "FRET.STK [RegDst0 ~ RegDstn], sp!, uimm",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000707f",
+          "match": "0x00003041",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "DstBegin",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "DstEnd",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "uimm",
+          "pieces": [
+            {
+              "instruction_lsb": 25,
+              "value_lsb": 3,
+              "width": 7
+            },
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 10,
+              "width": 5
+            }
+          ],
+          "signedness": "unsigned",
+          "width": 15
+        }
+      ],
+      "form_id": "fret_stk_32_4fe246bd8241",
+      "length_bits": 32,
+      "mnemonic": "FRET.STK",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteFrameReturnStack",
+      "semantic_summary": "Restores a frame and returns through the validated stack target.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.CALL <br_label>, <rt_label>, ->ra",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xf83f0000007f",
+          "match": "0x501600000011",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm25",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            }
+          ],
+          "signedness": "signed",
+          "width": 25
+        },
+        {
+          "name": "uimm5",
+          "pieces": [
+            {
+              "instruction_lsb": 38,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "unsigned",
+          "width": 5
+        }
+      ],
+      "form_id": "hl_bstart_call_48_3c784c583c90",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART CALL",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.FP COND, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff000f",
+          "match": "0x00003101000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 1,
+              "width": 17
+            },
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 18,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 30
+        }
+      ],
+      "form_id": "hl_bstart_fp_48_038e2e96cf64",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART.FP",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.FP FALL<, fixup_label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff000f",
+          "match": "0x00001101000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 1,
+              "width": 17
+            },
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 18,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 30
+        }
+      ],
+      "form_id": "hl_bstart_fp_48_43530d2ebfae",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART.FP",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.FP CALL, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff000f",
+          "match": "0x00004101000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 1,
+              "width": 17
+            },
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 18,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 30
+        }
+      ],
+      "form_id": "hl_bstart_fp_48_81b457553844",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART.FP",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.FP DIRECT, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff000f",
+          "match": "0x00002101000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 1,
+              "width": 17
+            },
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 18,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 30
+        }
+      ],
+      "form_id": "hl_bstart_fp_48_eb938e9200eb",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART.FP",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.STD CALL, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff000f",
+          "match": "0x00004001000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 1,
+              "width": 17
+            },
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 18,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 30
+        }
+      ],
+      "form_id": "hl_bstart_std_48_51f78942222e",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART.STD",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.STD FALL<, fixup_label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff000f",
+          "match": "0x00001001000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 1,
+              "width": 17
+            },
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 18,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 30
+        }
+      ],
+      "form_id": "hl_bstart_std_48_9ba705710872",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART.STD",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.STD COND, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff000f",
+          "match": "0x00003001000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 1,
+              "width": 17
+            },
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 18,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 30
+        }
+      ],
+      "form_id": "hl_bstart_std_48_b13f22c7c4a3",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART.STD",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.STD DIRECT, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff000f",
+          "match": "0x00002001000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 1,
+              "width": 17
+            },
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 18,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 30
+        }
+      ],
+      "form_id": "hl_bstart_std_48_d814d26508a4",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART.STD",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "HL.BSTART.SYS FALL<, fixup_label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff000f",
+          "match": "0x00001081000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 1,
+              "width": 17
+            },
+            {
+              "instruction_lsb": 4,
+              "value_lsb": 18,
+              "width": 12
+            }
+          ],
+          "signedness": "signed",
+          "width": 30
+        }
+      ],
+      "form_id": "hl_bstart_sys_48_5bf0381f7bf8",
+      "length_bits": 48,
+      "mnemonic": "HL.BSTART.SYS",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "hl.qmt.{i,e,s,r,ie,is,ir,es,er,ies,ier} SrcL, SrcR, ->{t, u}",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xe000707fffff",
+          "match": "0x0000007d000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "RegDst",
+          "pieces": [
+            {
+              "instruction_lsb": 23,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "SrcL",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "SrcR",
+          "pieces": [
+            {
+              "instruction_lsb": 36,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "e",
+          "pieces": [
+            {
+              "instruction_lsb": 41,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "i",
+          "pieces": [
+            {
+              "instruction_lsb": 44,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "r",
+          "pieces": [
+            {
+              "instruction_lsb": 42,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "s",
+          "pieces": [
+            {
+              "instruction_lsb": 43,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        }
+      ],
+      "form_id": "hl_qmt_48_eb9e41958045",
+      "length_bits": 48,
+      "mnemonic": "HL.QMT",
+      "semantic_family": "CMD",
+      "semantic_group": "General",
+      "semantic_handler": "ExecuteQueueMove",
+      "semantic_summary": "Moves values between scalar temporary queues according to encoded queue controls.",
+      "status": "accepted"
+    },
+    {
+      "asm": "hl.qpop.{e,r,er} SrcL, ->Dst0, Dst1",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xf800707f07ff",
+          "match": "0x0000207d000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "RegDst0",
+          "pieces": [
+            {
+              "instruction_lsb": 23,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegDst1",
+          "pieces": [
+            {
+              "instruction_lsb": 11,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "SrcL",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "SrcR",
+          "pieces": [
+            {
+              "instruction_lsb": 36,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "e",
+          "pieces": [
+            {
+              "instruction_lsb": 41,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "r",
+          "pieces": [
+            {
+              "instruction_lsb": 42,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        }
+      ],
+      "form_id": "hl_qpop_48_a2c57f5bc27b",
+      "length_bits": 48,
+      "mnemonic": "HL.QPOP",
+      "semantic_family": "CMD",
+      "semantic_group": "General",
+      "semantic_handler": "ExecuteQueuePop",
+      "semantic_summary": "Pops selected scalar queue values into encoded destinations.",
+      "status": "accepted"
+    },
+    {
+      "asm": "hl.qpush.{h,e,r,he,hr,er,her} SrcL, SrcR, ->{t, u}",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0xf000707fffff",
+          "match": "0x0000107d000e",
+          "width_bits": 48
+        }
+      ],
+      "encoding_kind": "HL48",
+      "fields": [
+        {
+          "name": "RegDst",
+          "pieces": [
+            {
+              "instruction_lsb": 23,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "SrcL",
+          "pieces": [
+            {
+              "instruction_lsb": 31,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "SrcR",
+          "pieces": [
+            {
+              "instruction_lsb": 36,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "e",
+          "pieces": [
+            {
+              "instruction_lsb": 41,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "h",
+          "pieces": [
+            {
+              "instruction_lsb": 43,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        },
+        {
+          "name": "r",
+          "pieces": [
+            {
+              "instruction_lsb": 42,
+              "value_lsb": 0,
+              "width": 1
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 1
+        }
+      ],
+      "form_id": "hl_qpush_48_3eab8e05d61a",
+      "length_bits": 48,
+      "mnemonic": "HL.QPUSH",
+      "semantic_family": "CMD",
+      "semantic_group": "General",
+      "semantic_handler": "ExecuteQueuePush",
+      "semantic_summary": "Pushes the encoded scalar values to the selected temporary queue.",
+      "status": "accepted"
+    },
+    {
+      "asm": "L.BSTART.FP COND, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x0000000f",
+          "width_bits": 32
+        },
+        {
+          "index": 1,
+          "mask": "0x00007fff",
+          "match": "0x00003081",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L64",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            },
+            {
+              "instruction_lsb": 47,
+              "value_lsb": 25,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 42
+        }
+      ],
+      "form_id": "l_bstart_fp_64_098e57019d7b",
+      "length_bits": 64,
+      "mnemonic": "L.BSTART.FP",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "L.BSTART.FP DIRECT, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x0000000f",
+          "width_bits": 32
+        },
+        {
+          "index": 1,
+          "mask": "0x00007fff",
+          "match": "0x00002081",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L64",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            },
+            {
+              "instruction_lsb": 47,
+              "value_lsb": 25,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 42
+        }
+      ],
+      "form_id": "l_bstart_fp_64_0cac9941f7d4",
+      "length_bits": 64,
+      "mnemonic": "L.BSTART.FP",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "L.BSTART.FP CALL, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x0000000f",
+          "width_bits": 32
+        },
+        {
+          "index": 1,
+          "mask": "0x00007fff",
+          "match": "0x00004081",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L64",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            },
+            {
+              "instruction_lsb": 47,
+              "value_lsb": 25,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 42
+        }
+      ],
+      "form_id": "l_bstart_fp_64_2067ad6667ed",
+      "length_bits": 64,
+      "mnemonic": "L.BSTART.FP",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "L.BSTART.FP FALL<, fixup_label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x0000000f",
+          "width_bits": 32
+        },
+        {
+          "index": 1,
+          "mask": "0x00007fff",
+          "match": "0x00001081",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L64",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            },
+            {
+              "instruction_lsb": 47,
+              "value_lsb": 25,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 42
+        }
+      ],
+      "form_id": "l_bstart_fp_64_8115c042ef26",
+      "length_bits": 64,
+      "mnemonic": "L.BSTART.FP",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "L.BSTART.STD DIRECT, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x0000000f",
+          "width_bits": 32
+        },
+        {
+          "index": 1,
+          "mask": "0x00007fff",
+          "match": "0x00002001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L64",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            },
+            {
+              "instruction_lsb": 47,
+              "value_lsb": 25,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 42
+        }
+      ],
+      "form_id": "l_bstart_std_64_37e84068ce61",
+      "length_bits": 64,
+      "mnemonic": "L.BSTART.STD",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "L.BSTART.STD CALL, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x0000000f",
+          "width_bits": 32
+        },
+        {
+          "index": 1,
+          "mask": "0x00007fff",
+          "match": "0x00004001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L64",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            },
+            {
+              "instruction_lsb": 47,
+              "value_lsb": 25,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 42
+        }
+      ],
+      "form_id": "l_bstart_std_64_463a1567da91",
+      "length_bits": 64,
+      "mnemonic": "L.BSTART.STD",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "L.BSTART.STD COND, <label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x0000000f",
+          "width_bits": 32
+        },
+        {
+          "index": 1,
+          "mask": "0x00007fff",
+          "match": "0x00003001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L64",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            },
+            {
+              "instruction_lsb": 47,
+              "value_lsb": 25,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 42
+        }
+      ],
+      "form_id": "l_bstart_std_64_72d502fcd30d",
+      "length_bits": 64,
+      "mnemonic": "L.BSTART.STD",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "L.BSTART.STD FALL<, fixup_label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x0000000f",
+          "width_bits": 32
+        },
+        {
+          "index": 1,
+          "mask": "0x00007fff",
+          "match": "0x00001001",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L64",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            },
+            {
+              "instruction_lsb": 47,
+              "value_lsb": 25,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 42
+        }
+      ],
+      "form_id": "l_bstart_std_64_899592f9c5bc",
+      "length_bits": 64,
+      "mnemonic": "L.BSTART.STD",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "L.BSTART.SYS FALL<, fixup_label>",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x0000007f",
+          "match": "0x0000000f",
+          "width_bits": 32
+        },
+        {
+          "index": 1,
+          "mask": "0x00007fff",
+          "match": "0x00001011",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L64",
+      "fields": [
+        {
+          "name": "simm",
+          "pieces": [
+            {
+              "instruction_lsb": 7,
+              "value_lsb": 0,
+              "width": 25
+            },
+            {
+              "instruction_lsb": 47,
+              "value_lsb": 25,
+              "width": 17
+            }
+          ],
+          "signedness": "signed",
+          "width": 42
+        }
+      ],
+      "form_id": "l_bstart_sys_64_919e576c79e4",
+      "length_bits": 64,
+      "mnemonic": "L.BSTART.SYS",
+      "semantic_family": "BBD",
+      "semantic_group": "BSTART",
+      "semantic_handler": "ExecuteBundleStart",
+      "semantic_summary": "Closes the current bundle, initializes the next bundle descriptor, and selects its transfer and execution kind.",
+      "status": "accepted"
+    },
+    {
+      "asm": "MCOPY [RegSrc0, RegSrc1, RegSrc2]",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x06007fff",
+          "match": "0x00000031",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "RegSrc0",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc1",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc2",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "mcopy_32_4fc4a803e995",
+      "length_bits": 32,
+      "mnemonic": "MCOPY",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteMemoryCopy",
+      "semantic_summary": "Copies an encoded memory range with instruction-atomic preflight and snapshot semantics.",
+      "status": "accepted"
+    },
+    {
+      "asm": "MSET [RegSrc0, RegSrc1, RegSrc2]",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x06007fff",
+          "match": "0x00001031",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "RegSrc0",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc1",
+          "pieces": [
+            {
+              "instruction_lsb": 20,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        },
+        {
+          "name": "RegSrc2",
+          "pieces": [
+            {
+              "instruction_lsb": 27,
+              "value_lsb": 0,
+              "width": 5
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 5
+        }
+      ],
+      "form_id": "mset_32_0b932f291932",
+      "length_bits": 32,
+      "mnemonic": "MSET",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteMemorySet",
+      "semantic_summary": "Fills an encoded memory range after complete access preflight.",
+      "status": "accepted"
+    },
+    {
+      "asm": "XB ACR-ID, C-ID",
+      "constraints": [],
+      "encoding": [
+        {
+          "index": 0,
+          "mask": "0x00007fff",
+          "match": "0x00006f81",
+          "width_bits": 32
+        }
+      ],
+      "encoding_kind": "L32",
+      "fields": [
+        {
+          "name": "ACR-ID",
+          "pieces": [
+            {
+              "instruction_lsb": 15,
+              "value_lsb": 0,
+              "width": 10
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 10
+        },
+        {
+          "name": "CROSS-BID",
+          "pieces": [
+            {
+              "instruction_lsb": 25,
+              "value_lsb": 0,
+              "width": 7
+            }
+          ],
+          "signedness": "encoding-defined",
+          "width": 7
+        }
+      ],
+      "form_id": "xb_32_40ad190a0a7f",
+      "length_bits": 32,
+      "mnemonic": "XB",
+      "semantic_family": "CMD",
+      "semantic_group": "Bundle Split",
+      "semantic_handler": "ExecuteCrossBlockTransfer",
+      "semantic_summary": "Transfers the named context value to a target virtual core block.",
+      "status": "accepted"
+    }
+  ],
+  "isa": "PTO Instruction Set Architecture",
+  "operand_field_count": 57,
+  "operand_piece_count": 190,
+  "reviewed_encoding_overlaps": [
+    {
+      "broad_form_id": "b_iot_32_10db6db84f5d",
+      "narrow_form_id": "b_iot_32_c11eb189dd83",
+      "reason": "destination-free form fixes DstTile and imm4 to zero; destination form requires DstTile 0..3 and imm4 3..9"
+    },
+    {
+      "broad_form_id": "b_iot_32_8b8bce6bffe8",
+      "narrow_form_id": "b_iot_32_2c07e7177fad",
+      "reason": "destination-free form fixes DstTile and imm4 to zero; destination form requires DstTile 0..3 and imm4 3..9"
+    },
+    {
+      "broad_form_id": "c_b_dimi_16_3f1b113c76ce",
+      "narrow_form_id": "c_b_dim_16_14f1b8fba5e6",
+      "reason": "register form fixes the immediate-form LoopNest projection to excluded value 3"
+    },
+    {
+      "broad_form_id": "c_bstart_std_16_8b40f078c14a",
+      "narrow_form_id": "c_bstop_16_ca4743d8a95e",
+      "reason": "C.BSTOP fixes the broad C.BSTART.STD BrType field to excluded value 0"
+    }
+  ],
+  "schema_version": 2,
+  "semantic_handler_count": 21,
+  "surface": "command-and-boundary",
+  "source_lock": "isa/v0.57/pto-spec.lock.json"
+}
diff --git a/isa/v0.57/state/pto_encoding_map.json b/isa/v0.57/state/pto_encoding_map.json
index 1e90f468..00576726 100644
--- a/isa/v0.57/state/pto_encoding_map.json
+++ b/isa/v0.57/state/pto_encoding_map.json
@@ -1,984 +1,1224 @@
 {
-  "$schema": "https://docs.openclaw.ai/schemas/linxisa/pto_encoding_map.v0.json",
+  "$schema": "https://docs.openclaw.ai/schemas/linxisa/pto_encoding_map.v1.json",
   "profile": "v0.57",
-  "version": "0.57.0",
-  "source": {
-    "title": "PTO-ISA-LinxISA 0.57",
-    "original_sha256": "0387b39f108599f2469c2e2374a46ea4b832a96fee7bf7aa5d7cc575fdc7864a",
-    "review_export_sha256": "4c75f961e8f2f63e35bce51dec21c97f75c50e2189a0f8c83f95577403984d21",
-    "sheet": "Sheet1",
-    "data_rows": 111
-  },
+  "version": "0.57.1",
+  "source_lock": "isa/v0.57/pto-spec.lock.json",
   "policy": {
-    "established_selectors_stable": true,
-    "spreadsheet_row_order_allocates_selectors": false,
-    "legacy_descriptor_spellings_allowed": false,
-    "unlisted_selectors_reserved": true
+    "catalog_order_allocates_encodings": false,
+    "unlisted_selectors_reserved": true,
+    "legacy_decode_allowed": false,
+    "source_aliases_are_migration_only": true
   },
-  "entry_count": 111,
+  "entry_count": 120,
   "family_counts": {
-    "TEPL": 97,
-    "TMA": 6,
-    "CUBE": 8
+    "CUBE": 13,
+    "TEPL": 98,
+    "TMA": 9
+  },
+  "migration_aliases": {
+    "TTRANSPOSE": "TTRANS",
+    "TSORT32": "TSORT"
   },
   "entries": [
     {
-      "pto_name": "TADD",
-      "canonical_name": "TADD",
-      "source_row": 2,
+      "name": "TADD",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x000",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 0,
+      "function": 0,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TSUB",
-      "canonical_name": "TSUB",
-      "source_row": 3,
+      "name": "TSUB",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x001",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 0,
+      "function": 1,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TMUL",
-      "canonical_name": "TMUL",
-      "source_row": 4,
+      "name": "TMUL",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x002",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 0,
+      "function": 2,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TMAX",
-      "canonical_name": "TMAX",
-      "source_row": 5,
+      "name": "TMAX",
       "family": "TEPL",
-      "selector": "0x004",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x00B",
+      "mode": 0,
+      "function": 11,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TMIN",
-      "canonical_name": "TMIN",
-      "source_row": 6,
+      "name": "TMIN",
       "family": "TEPL",
-      "selector": "0x005",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x00C",
+      "mode": 0,
+      "function": 12,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TAND",
-      "canonical_name": "TAND",
-      "source_row": 7,
+      "name": "TAND",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x006",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 0,
+      "function": 6,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TOR",
-      "canonical_name": "TOR",
-      "source_row": 8,
+      "name": "TOR",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x007",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 0,
+      "function": 7,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TXOR",
-      "canonical_name": "TXOR",
-      "source_row": 9,
+      "name": "TXOR",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x008",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 0,
+      "function": 8,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TSHL",
-      "canonical_name": "TSHL",
-      "source_row": 10,
+      "name": "TSHL",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x009",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 0,
+      "function": 9,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TSHR",
-      "canonical_name": "TSHR",
-      "source_row": 11,
+      "name": "TSHR",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x00A",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 0,
+      "function": 10,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TCMP",
-      "canonical_name": "TCMP",
-      "source_row": 12,
+      "name": "TCMP",
       "family": "TEPL",
-      "selector": "0x02B",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x00D",
+      "mode": 0,
+      "function": 13,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TSEL",
-      "canonical_name": "TSEL",
-      "source_row": 13,
+      "name": "TSEL",
       "family": "TEPL",
-      "selector": "0x02C",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x01A",
+      "mode": 0,
+      "function": 26,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TABS",
-      "canonical_name": "TABS",
-      "source_row": 14,
+      "name": "TABS",
       "family": "TEPL",
-      "selector": "0x02D",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x00F",
+      "mode": 0,
+      "function": 15,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TNOT",
-      "canonical_name": "TNOT",
-      "source_row": 15,
+      "name": "TNOT",
       "family": "TEPL",
-      "selector": "0x02E",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x010",
+      "mode": 0,
+      "function": 16,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TNEG",
-      "canonical_name": "TNEG",
-      "source_row": 16,
+      "name": "TNEG",
       "family": "TEPL",
-      "selector": "0x02F",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x011",
+      "mode": 0,
+      "function": 17,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TRELU",
-      "canonical_name": "TRELU",
-      "source_row": 17,
+      "name": "TRELU",
       "family": "TEPL",
-      "selector": "0x00B",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x017",
+      "mode": 0,
+      "function": 23,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
+    },
+    {
+      "name": "TPRELU",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x00E",
+      "mode": 0,
+      "function": 14,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TDIV",
-      "canonical_name": "TDIV",
-      "source_row": 18,
+      "name": "TDIV",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x003",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 0,
+      "function": 3,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TREM",
-      "canonical_name": "TREM",
-      "source_row": 19,
+      "name": "TREM",
       "family": "TEPL",
-      "selector": "0x030",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x004",
+      "mode": 0,
+      "function": 4,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TSQRT",
-      "canonical_name": "TSQRT",
-      "source_row": 20,
+      "name": "TSQRT",
       "family": "TEPL",
-      "selector": "0x010",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x015",
+      "mode": 0,
+      "function": 21,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TLOG",
-      "canonical_name": "TLOG",
-      "source_row": 21,
+      "name": "TLOG",
       "family": "TEPL",
-      "selector": "0x00F",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x013",
+      "mode": 0,
+      "function": 19,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TRECIP",
-      "canonical_name": "TRECIP",
-      "source_row": 22,
+      "name": "TRECIP",
       "family": "TEPL",
-      "selector": "0x018",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x014",
+      "mode": 0,
+      "function": 20,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TEXP",
-      "canonical_name": "TEXP",
-      "source_row": 23,
+      "name": "TEXP",
       "family": "TEPL",
-      "selector": "0x00E",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x012",
+      "mode": 0,
+      "function": 18,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TRSQRT",
-      "canonical_name": "TRSQRT",
-      "source_row": 24,
+      "name": "TRSQRT",
       "family": "TEPL",
-      "selector": "0x011",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x016",
+      "mode": 0,
+      "function": 22,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TADDS",
-      "canonical_name": "TADDS",
-      "source_row": 25,
+      "name": "TADDS",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x020",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 1,
+      "function": 0,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TAXPY",
-      "canonical_name": "TAXPY",
-      "source_row": 26,
+      "name": "TAXPY",
       "family": "TEPL",
-      "selector": "0x031",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x02F",
+      "mode": 1,
+      "function": 15,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TSUBS",
-      "canonical_name": "TSUBS",
-      "source_row": 27,
+      "name": "TSUBS",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x021",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 1,
+      "function": 1,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TMULS",
-      "canonical_name": "TMULS",
-      "source_row": 28,
+      "name": "TMULS",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x022",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 1,
+      "function": 2,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TDIVS",
-      "canonical_name": "TDIVS",
-      "source_row": 29,
+      "name": "TDIVS",
       "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "selector": "0x023",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "mode": 1,
+      "function": 3,
+      "disposition": "accepted-direct-operation",
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     },
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-      "canonical_name": "TMINS",
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       "family": "TEPL",
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-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TMAXS",
-      "canonical_name": "TMAXS",
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       "family": "TEPL",
-      "selector": "0x024",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TREMS",
-      "canonical_name": "TREMS",
-      "source_row": 32,
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       "family": "TEPL",
-      "selector": "0x032",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TANDS",
-      "canonical_name": "TANDS",
-      "source_row": 33,
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       "family": "TEPL",
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       "selector": "0x026",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TORS",
-      "canonical_name": "TORS",
-      "source_row": 34,
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       "family": "TEPL",
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       "selector": "0x027",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TXORS",
-      "canonical_name": "TXORS",
-      "source_row": 35,
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       "family": "TEPL",
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       "selector": "0x028",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCMPS",
-      "canonical_name": "TCMPS",
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       "family": "TEPL",
-      "selector": "0x033",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TSELS",
-      "canonical_name": "TSELS",
-      "source_row": 37,
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       "family": "TEPL",
-      "selector": "0x034",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TSHLS",
-      "canonical_name": "TSHLS",
-      "source_row": 38,
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       "family": "TEPL",
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       "selector": "0x029",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TSHRS",
-      "canonical_name": "TSHRS",
-      "source_row": 39,
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       "family": "TEPL",
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       "selector": "0x02A",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWSUM",
-      "canonical_name": "TROWSUM",
-      "source_row": 40,
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       "family": "TEPL",
-      "selector": "0x014",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWPROD",
-      "canonical_name": "TROWPROD",
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       "family": "TEPL",
-      "selector": "0x035",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWMAX",
-      "canonical_name": "TROWMAX",
-      "source_row": 42,
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       "family": "TEPL",
-      "selector": "0x012",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWMIN",
-      "canonical_name": "TROWMIN",
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       "family": "TEPL",
-      "selector": "0x013",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWARGMAX",
-      "canonical_name": "TROWARGMAX",
-      "source_row": 44,
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       "family": "TEPL",
-      "selector": "0x036",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWARGMIN",
-      "canonical_name": "TROWARGMIN",
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       "family": "TEPL",
-      "selector": "0x037",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLSUM",
-      "canonical_name": "TCOLSUM",
-      "source_row": 46,
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       "family": "TEPL",
-      "selector": "0x017",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLPROD",
-      "canonical_name": "TCOLPROD",
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       "family": "TEPL",
-      "selector": "0x038",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLMAX",
-      "canonical_name": "TCOLMAX",
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       "family": "TEPL",
-      "selector": "0x015",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLMIN",
-      "canonical_name": "TCOLMIN",
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       "family": "TEPL",
-      "selector": "0x016",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLARGMAX",
-      "canonical_name": "TCOLARGMAX",
-      "source_row": 50,
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       "family": "TEPL",
-      "selector": "0x039",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLARGMIN",
-      "canonical_name": "TCOLARGMIN",
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       "family": "TEPL",
-      "selector": "0x03A",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWEXPAND",
-      "canonical_name": "TROWEXPAND",
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       "family": "TEPL",
-      "selector": "0x01F",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWEXPANDADD",
-      "canonical_name": "TROWEXPANDADD",
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       "family": "TEPL",
-      "selector": "0x03B",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWEXPANDSUB",
-      "canonical_name": "TROWEXPANDSUB",
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       "family": "TEPL",
-      "selector": "0x03C",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWEXPANDMUL",
-      "canonical_name": "TROWEXPANDMUL",
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       "family": "TEPL",
-      "selector": "0x03D",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWEXPANDDIV",
-      "canonical_name": "TROWEXPANDDIV",
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       "family": "TEPL",
-      "selector": "0x03E",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWEXPANDMAX",
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       "family": "TEPL",
-      "selector": "0x03F",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWEXPANDMIN",
-      "canonical_name": "TROWEXPANDMIN",
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       "family": "TEPL",
-      "selector": "0x040",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TROWEXPANDEXPDIF",
-      "canonical_name": "TROWEXPANDEXPDIF",
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       "family": "TEPL",
-      "selector": "0x041",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLEXPAND",
-      "canonical_name": "TCOLEXPAND",
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       "family": "TEPL",
-      "selector": "0x01E",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLEXPANDADD",
-      "canonical_name": "TCOLEXPANDADD",
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       "family": "TEPL",
-      "selector": "0x042",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLEXPANDSUB",
-      "canonical_name": "TCOLEXPANDSUB",
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       "family": "TEPL",
-      "selector": "0x043",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLEXPANDMUL",
-      "canonical_name": "TCOLEXPANDMUL",
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       "family": "TEPL",
-      "selector": "0x044",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLEXPANDDIV",
-      "canonical_name": "TCOLEXPANDDIV",
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       "family": "TEPL",
-      "selector": "0x045",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLEXPANDMAX",
-      "canonical_name": "TCOLEXPANDMAX",
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       "family": "TEPL",
-      "selector": "0x046",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLEXPANDMIN",
-      "canonical_name": "TCOLEXPANDMIN",
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       "family": "TEPL",
-      "selector": "0x047",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TCOLEXPANDEXPDIF",
-      "canonical_name": "TCOLEXPANDEXPDIF",
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       "family": "TEPL",
-      "selector": "0x048",
-      "encoding_mnemonic": "BSTART.TEPL"
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     },
     {
-      "pto_name": "TMATMUL",
-      "canonical_name": "TMATMUL",
-      "source_row": 68,
+      "name": "TMATMUL",
       "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMUL",
+      "selector": null,
+      "mode": null,
       "function": 0,
-      "encoding_mnemonic": "BSTART.TMATMUL"
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     },
     {
-      "pto_name": "TMATMUL_BIAS",
-      "canonical_name": "TMATMUL_BIAS",
-      "source_row": 69,
+      "name": "TMATMUL_BIAS",
       "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMUL.BIAS",
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       "function": 1,
-      "encoding_mnemonic": "BSTART.TMATMUL.BIAS"
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     },
     {
-      "pto_name": "TMATMUL_ACC",
-      "canonical_name": "TMATMUL_ACC",
-      "source_row": 70,
+      "name": "TMATMUL_ACC",
       "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMUL.ACC",
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       "function": 2,
-      "encoding_mnemonic": "BSTART.TMATMUL.ACC"
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     },
     {
-      "pto_name": "TMATMUL_MX",
-      "canonical_name": "TMATMUL_MX",
-      "source_row": 71,
+      "name": "TMATMUL_MX",
       "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMULMX",
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       "function": 4,
-      "encoding_mnemonic": "BSTART.TMATMULMX"
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     },
     {
-      "pto_name": "TGEMV",
-      "canonical_name": "TGEMV",
-      "source_row": 72,
+      "name": "TMATMUL_MX_BIAS",
       "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMULMX.BIAS",
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+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
+    },
+    {
+      "name": "TMATMUL_MX_ACC",
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+      "command_mnemonic": "BSTART.TMATMULMX.ACC",
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+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
+    },
+    {
+      "name": "ACCCVT",
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+    },
+    {
+      "name": "TGEMV",
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       "function": 16,
-      "encoding_mnemonic": "BSTART.TGEMV"
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     },
     {
-      "pto_name": "TGEMV_BIAS",
-      "canonical_name": "TGEMV_BIAS",
-      "source_row": 73,
+      "name": "TGEMV_BIAS",
       "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMV.BIAS",
+      "selector": null,
+      "mode": null,
       "function": 17,
-      "encoding_mnemonic": "BSTART.TGEMV.BIAS"
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TGEMV_ACC",
-      "canonical_name": "TGEMV_ACC",
-      "source_row": 74,
+      "name": "TGEMV_ACC",
       "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMV.ACC",
+      "selector": null,
+      "mode": null,
       "function": 18,
-      "encoding_mnemonic": "BSTART.TGEMV.ACC"
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TGEMV_MX",
-      "canonical_name": "TGEMV_MX",
-      "source_row": 75,
+      "name": "TGEMV_MX",
       "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMVMX",
+      "selector": null,
+      "mode": null,
       "function": 20,
-      "encoding_mnemonic": "BSTART.TGEMVMX"
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TLOAD",
-      "canonical_name": "TLOAD",
-      "source_row": 76,
+      "name": "TGEMV_MX_BIAS",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMVMX.BIAS",
+      "selector": null,
+      "mode": null,
+      "function": 21,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
+    },
+    {
+      "name": "TGEMV_MX_ACC",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMVMX.ACC",
+      "selector": null,
+      "mode": null,
+      "function": 22,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
+    },
+    {
+      "name": "TLOAD",
       "family": "TMA",
+      "command_mnemonic": "BSTART.TLOAD",
+      "selector": null,
+      "mode": null,
       "function": 0,
-      "encoding_mnemonic": "BSTART.TLOAD"
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TSTORE",
-      "canonical_name": "TSTORE",
-      "source_row": 77,
+      "name": "TSTORE",
       "family": "TMA",
+      "command_mnemonic": "BSTART.TSTORE",
+      "selector": null,
+      "mode": null,
       "function": 1,
-      "encoding_mnemonic": "BSTART.TSTORE"
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TPREFETCH",
-      "canonical_name": "TPREFETCH",
-      "source_row": 78,
+      "name": "TPREFETCH",
       "family": "TMA",
+      "command_mnemonic": "BSTART.TPREFETCH",
+      "selector": null,
+      "mode": null,
       "function": 3,
-      "encoding_mnemonic": "BSTART.TPREFETCH"
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "MGATHER",
-      "canonical_name": "MGATHER",
-      "source_row": 79,
+      "name": "MGATHER",
       "family": "TMA",
+      "command_mnemonic": "BSTART.MGATHER",
+      "selector": null,
+      "mode": null,
       "function": 4,
-      "encoding_mnemonic": "BSTART.MGATHER"
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "MSCATTER",
-      "canonical_name": "MSCATTER",
-      "source_row": 80,
+      "name": "MSCATTER",
       "family": "TMA",
+      "command_mnemonic": "BSTART.MSCATTER",
+      "selector": null,
+      "mode": null,
       "function": 5,
-      "encoding_mnemonic": "BSTART.MSCATTER"
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
+    },
+    {
+      "name": "MGATHER_MASK",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.MGATHER.MASK",
+      "selector": null,
+      "mode": null,
+      "function": 6,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TEXPANDS",
-      "canonical_name": "TEXPANDS",
-      "source_row": 81,
+      "name": "MSCATTER_MASK",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.MSCATTER.MASK",
+      "selector": null,
+      "mode": null,
+      "function": 7,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
+    },
+    {
+      "name": "MGATHER_CAS",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.MGATHER.CAS",
+      "selector": null,
+      "mode": null,
+      "function": 8,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
+    },
+    {
+      "name": "TEXPANDS",
       "family": "TEPL",
-      "selector": "0x019",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x03B",
+      "mode": 1,
+      "function": 27,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TCI",
-      "canonical_name": "TCI",
-      "source_row": 82,
+      "name": "TCI",
       "family": "TEPL",
-      "selector": "0x080",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x066",
+      "mode": 3,
+      "function": 6,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TTRI",
-      "canonical_name": "TTRI",
-      "source_row": 83,
+      "name": "TTRI",
       "family": "TEPL",
-      "selector": "0x081",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x067",
+      "mode": 3,
+      "function": 7,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TFILLPAD",
-      "canonical_name": "TFILLPAD",
-      "source_row": 84,
+      "name": "TFILLPAD",
       "family": "TEPL",
-      "selector": "0x082",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x065",
+      "mode": 3,
+      "function": 5,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TCVT",
-      "canonical_name": "TCVT",
-      "source_row": 85,
+      "name": "TCVT",
       "family": "TEPL",
-      "selector": "0x00D",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x01B",
+      "mode": 0,
+      "function": 27,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TQUANT",
-      "canonical_name": "TQUANT",
-      "source_row": 86,
+      "name": "TQUANT",
       "family": "TEPL",
-      "selector": "0x083",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x06A",
+      "mode": 3,
+      "function": 10,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TDEQUANT",
-      "canonical_name": "TDEQUANT",
-      "source_row": 87,
+      "name": "TDEQUANT",
       "family": "TEPL",
-      "selector": "0x084",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x06B",
+      "mode": 3,
+      "function": 11,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TEXTRACT",
-      "canonical_name": "TEXTRACT",
-      "source_row": 88,
+      "name": "TEXTRACT",
       "family": "TEPL",
-      "selector": "0x085",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x062",
+      "mode": 3,
+      "function": 2,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TINSERT",
-      "canonical_name": "TINSERT",
-      "source_row": 89,
+      "name": "TINSERT",
       "family": "TEPL",
-      "selector": "0x086",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x063",
+      "mode": 3,
+      "function": 3,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TGATHER",
-      "canonical_name": "TGATHER",
-      "source_row": 90,
+      "name": "TGATHER",
       "family": "TEPL",
-      "selector": "0x01A",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x06F",
+      "mode": 3,
+      "function": 15,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TSCATTER",
-      "canonical_name": "TSCATTER",
-      "source_row": 91,
+      "name": "TSCATTER",
       "family": "TEPL",
-      "selector": "0x01B",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x070",
+      "mode": 3,
+      "function": 16,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TCONCAT",
-      "canonical_name": "TCONCAT",
-      "source_row": 92,
+      "name": "TCONCAT",
       "family": "TEPL",
-      "selector": "0x087",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x060",
+      "mode": 3,
+      "function": 0,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TTRANS",
-      "canonical_name": "TTRANSPOSE",
-      "source_row": 93,
+      "name": "TTRANS",
       "family": "TEPL",
-      "selector": "0x01D",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x06E",
+      "mode": 3,
+      "function": 14,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TIMG2COL",
-      "canonical_name": "TIMG2COL",
-      "source_row": 94,
+      "name": "TIMG2COL",
       "family": "TEPL",
-      "selector": "0x088",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x064",
+      "mode": 3,
+      "function": 4,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TMOV",
-      "canonical_name": "TMOV",
-      "source_row": 95,
+      "name": "TMOV",
       "family": "TMA",
+      "command_mnemonic": "BSTART.TMOV",
+      "selector": null,
+      "mode": null,
       "function": 2,
-      "encoding_mnemonic": "BSTART.TMOV"
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TGATHERB",
-      "canonical_name": "TGATHERB",
-      "source_row": 96,
+      "name": "TGATHERB",
       "family": "TEPL",
-      "selector": "0x089",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x061",
+      "mode": 3,
+      "function": 1,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TDEINTERLEAVE",
-      "canonical_name": "TDEINTERLEAVE",
-      "source_row": 97,
+      "name": "TDEINTERLEAVE",
       "family": "TEPL",
-      "selector": "0x08A",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x078",
+      "mode": 3,
+      "function": 24,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TINTERLEAVE",
-      "canonical_name": "TINTERLEAVE",
-      "source_row": 98,
+      "name": "TINTERLEAVE",
       "family": "TEPL",
-      "selector": "0x08B",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x079",
+      "mode": 3,
+      "function": 25,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TRESHAPE",
-      "canonical_name": "TRESHAPE",
-      "source_row": 99,
+      "name": "TRESHAPE",
       "family": "TEPL",
-      "selector": "0x01C",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x077",
+      "mode": 3,
+      "function": 23,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TSORT",
-      "canonical_name": "TSORT",
-      "source_row": 100,
+      "name": "TSORT",
       "family": "TEPL",
-      "selector": "0x0C0",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x06C",
+      "mode": 3,
+      "function": 12,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TMRGSORT",
-      "canonical_name": "TMRGSORT",
-      "source_row": 101,
+      "name": "TMRGSORT",
       "family": "TEPL",
-      "selector": "0x0C1",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x06D",
+      "mode": 3,
+      "function": 13,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "THISTOGRAM",
-      "canonical_name": "THISTOGRAM",
-      "source_row": 102,
+      "name": "THISTOGRAM",
       "family": "TEPL",
-      "selector": "0x0C2",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x068",
+      "mode": 3,
+      "function": 8,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TPARTADD",
-      "canonical_name": "TPARTADD",
-      "source_row": 103,
+      "name": "TPUSH",
       "family": "TEPL",
-      "selector": "0x0C3",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x07A",
+      "mode": 3,
+      "function": 26,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TPARTMUL",
-      "canonical_name": "TPARTMUL",
-      "source_row": 104,
+      "name": "TPOP",
       "family": "TEPL",
-      "selector": "0x0C4",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x07B",
+      "mode": 3,
+      "function": 27,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TPARTMAX",
-      "canonical_name": "TPARTMAX",
-      "source_row": 105,
+      "name": "TALLOC",
       "family": "TEPL",
-      "selector": "0x0C5",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x07C",
+      "mode": 3,
+      "function": 28,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TPARTMIN",
-      "canonical_name": "TPARTMIN",
-      "source_row": 106,
+      "name": "TFREE",
       "family": "TEPL",
-      "selector": "0x0C6",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x07D",
+      "mode": 3,
+      "function": 29,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TPARTARGMAX",
-      "canonical_name": "TPARTARGMAX",
-      "source_row": 107,
+      "name": "TPARTADD",
       "family": "TEPL",
-      "selector": "0x0C7",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x071",
+      "mode": 3,
+      "function": 17,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TPARTARGMIN",
-      "canonical_name": "TPARTARGMIN",
-      "source_row": 108,
+      "name": "TPARTMUL",
       "family": "TEPL",
-      "selector": "0x0C8",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x072",
+      "mode": 3,
+      "function": 18,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TPUSH",
-      "canonical_name": "TPUSH",
-      "source_row": 109,
+      "name": "TPARTMAX",
       "family": "TEPL",
-      "selector": "0x0E0",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x073",
+      "mode": 3,
+      "function": 19,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TPOP",
-      "canonical_name": "TPOP",
-      "source_row": 110,
+      "name": "TPARTMIN",
       "family": "TEPL",
-      "selector": "0x0E1",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x074",
+      "mode": 3,
+      "function": 20,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TALLOC",
-      "canonical_name": "TALLOC",
-      "source_row": 111,
+      "name": "TPARTARGMAX",
       "family": "TEPL",
-      "selector": "0x0E2",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x075",
+      "mode": 3,
+      "function": 21,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     },
     {
-      "pto_name": "TFREE",
-      "canonical_name": "TFREE",
-      "source_row": 112,
+      "name": "TPARTARGMIN",
       "family": "TEPL",
-      "selector": "0x0E3",
-      "encoding_mnemonic": "BSTART.TEPL"
+      "command_mnemonic": "BSTART.TEPL",
+      "selector": "0x076",
+      "mode": 3,
+      "function": 22,
+      "disposition": "accepted-direct-operation",
+      "contract_status": "reviewed-complete"
     }
-  ],
-  "supplemental_entries": [
-    {
-      "canonical_name": "BSTART.MGATHER.MASK",
-      "family": "TMA",
-      "function": 6,
-      "source": "LinxISA/linx-isa#123"
-    },
-    {
-      "canonical_name": "BSTART.MSCATTER.MASK",
-      "family": "TMA",
-      "function": 7,
-      "source": "LinxISA/linx-isa#123"
-    },
-    {
-      "canonical_name": "BSTART.MGATHER.CAS",
-      "family": "TMA",
-      "function": 8,
-      "source": "LinxISA/linx-isa#133"
-    }
-  ],
-  "reserved": {
-    "tma_functions": [
-      [
-        9,
-        31
-      ]
-    ],
-    "cube_functions_without_named_alias": [
-      3,
-      7,
-      [
-        9,
-        15
-      ],
-      19,
-      [
-        23,
-        31
-      ]
-    ],
-    "tepl_selector_ranges": [
-      [
-        "0x049",
-        "0x07F"
-      ],
-      [
-        "0x08C",
-        "0x0BF"
-      ],
-      [
-        "0x0C9",
-        "0x0DF"
-      ],
-      [
-        "0x0E4",
-        "0x3FF"
-      ]
-    ]
-  },
-  "rejected_review_only_names": [
-    "TEXRACT",
-    "TFILL/TEXPANDS",
-    "TFMOD",
-    "TFMODS",
-    "TLRELU？",
-    "TPOW",
-    "TPOWS",
-    "TPRELU？",
-    "TRANDOM"
   ]
 }
diff --git a/isa/v0.57/state/pto_ops.json b/isa/v0.57/state/pto_ops.json
index 43aa04b4..a970e52f 100644
--- a/isa/v0.57/state/pto_ops.json
+++ b/isa/v0.57/state/pto_ops.json
@@ -1,4224 +1,6339 @@
 {
-  "$schema": "https://docs.openclaw.ai/schemas/linxisa/pto_ops.v0.json",
+  "$schema": "https://docs.openclaw.ai/schemas/linxisa/pto_ops.v1.json",
   "profile": "v0.57",
-  "version": "0.57.0",
-  "source": {
-    "title": "PTO-ISA-LinxISA 0.57",
-    "original_sha256": "0387b39f108599f2469c2e2374a46ea4b832a96fee7bf7aa5d7cc575fdc7864a",
-    "review_export_sha256": "4c75f961e8f2f63e35bce51dec21c97f75c50e2189a0f8c83f95577403984d21",
-    "sheet": "Sheet1",
-    "data_rows": 111
+  "version": "0.57.1",
+  "source_lock": "isa/v0.57/pto-spec.lock.json",
+  "operation_count": 120,
+  "family_counts": {
+    "CUBE": 13,
+    "TEPL": 98,
+    "TMA": 9
   },
-  "normalization_rules": [
-    "Spreadsheet row order is evidence only and never determines an encoding.",
-    "TTRANS is the PTO spelling of canonical TEPL TTRANSPOSE.",
-    "PR-only MASK/CAS TMA functions are supplemental mappings, not invented workbook rows.",
-    "Retired descriptor references are translated to the active B.IOR/B.IOT descriptor contract."
+  "deleted_names": [
+    "TADDC",
+    "TADDSC",
+    "TFMA",
+    "TFMOD",
+    "TFMODS",
+    "TLRELU",
+    "TRANDOM",
+    "TSUBC",
+    "TSUBSC"
   ],
-  "operation_count": 111,
-  "family_counts": {
-    "TEPL": 97,
-    "TMA": 6,
-    "CUBE": 8
+  "rejected_names": [
+    "TEXRACT",
+    "TFILL/TEXPANDS",
+    "TPOW",
+    "TPOWS"
+  ],
+  "reserved": {
+    "cube_functions_without_named_alias": [
+      3,
+      7,
+      [
+        9,
+        15
+      ],
+      19,
+      [
+        23,
+        31
+      ]
+    ],
+    "tepl_selector_ranges": [
+      [
+        "0x005",
+        "0x005"
+      ],
+      [
+        "0x018",
+        "0x019"
+      ],
+      [
+        "0x01C",
+        "0x01F"
+      ],
+      [
+        "0x025",
+        "0x025"
+      ],
+      [
+        "0x02E",
+        "0x02E"
+      ],
+      [
+        "0x030",
+        "0x039"
+      ],
+      [
+        "0x03C",
+        "0x03F"
+      ],
+      [
+        "0x04E",
+        "0x04F"
+      ],
+      [
+        "0x05E",
+        "0x05F"
+      ],
+      [
+        "0x069",
+        "0x069"
+      ],
+      [
+        "0x07E",
+        "0x07F"
+      ]
+    ],
+    "tma_functions": [
+      [
+        9,
+        31
+      ]
+    ]
   },
   "operations": [
     {
-      "source_row": 2,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TADD",
-      "canonical_name": "TADD",
-      "category": "逐元素双目运算",
-      "subcategory": "算术运算",
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, U32, F32, S16, U16, F16, BF16, U8, S8",
-        "values": [
-          "S32",
-          "U32",
-          "F32",
-          "S16",
-          "U16",
-          "F16",
-          "BF16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "Elementwise add: dst[i,j] = src0[i,j] + src1[i,j].",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TAdd.hpp; pto/npu/a2a3/TAdd.hpp; pto/npu/a5/TAdd.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x000",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x000",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_ADD"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 0,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 3,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSUB",
-      "canonical_name": "TSUB",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8, F32, F16",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8",
-          "F32",
-          "F16"
-        ]
-      },
-      "description": "TSUB: Elementwise subtract of two tiles.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TSub.hpp; pto/npu/a2a3/TSub.hpp; pto/npu/a5/TSub.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x001",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x001",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_SUB"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 1,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 4,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TMUL",
-      "canonical_name": "TMUL",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, U32, F32, S16, U16, F16",
-        "values": [
-          "S32",
-          "U32",
-          "F32",
-          "S16",
-          "U16",
-          "F16"
-        ]
-      },
-      "description": "TMUL: Elementwise multiply of two tiles.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TMul.hpp; pto/npu/a2a3/TMul.hpp; pto/npu/a5/TMul.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x002",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x002",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_MUL"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 2,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 5,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TMAX",
-      "canonical_name": "TMAX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8, F32, F16",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8",
-          "F32",
-          "F16"
-        ]
-      },
-      "description": "Elementwise maximum of two tiles (tilebuf, DPS)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TMax.hpp; pto/npu/a2a3/TMax.hpp; pto/npu/a5/TMax.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x004",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x00B",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_MAX"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 11,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 6,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TMIN",
-      "canonical_name": "TMIN",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8, F32, F16",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8",
-          "F32",
-          "F16"
-        ]
-      },
-      "description": "Elementwise minimum of two tiles (tilebuf, DPS)",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/npu/a2a3/TMin.hpp; pto/npu/a5/TMin.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x005",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x00C",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_MIN"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 12,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 7,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TAND",
-      "canonical_name": "TAND",
-      "category": null,
-      "subcategory": "逻辑运算",
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "TAND(dst, src0, src1) bitwise-and on tiles",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/npu/a2a3/TAnd.hpp; pto/npu/a5/TAnd.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x006",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x006",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_AND"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 6,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 8,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TOR",
-      "canonical_name": "TOR",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "TOR: Elementwise bitwise OR of two tiles.",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/npu/a2a3/TOr.hpp; pto/npu/a5/TOr.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x007",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x007",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_OR"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 7,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 9,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TXOR",
-      "canonical_name": "TXOR",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile; PTOAS form also declares tmp tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "TXOR: Elementwise bitwise XOR of two tiles.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/ElementTileOp.h; pto/npu/a2a3/TXor.hpp; pto/npu/a5/TXor.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x008",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x008",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_XOR"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 8,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 10,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSHL",
-      "canonical_name": "TSHL",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "TSHL: Elementwise shift-left of two tiles.",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/npu/a2a3/TShl.hpp; pto/npu/a5/TShl.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x009",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x009",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_SHL"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 9,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 11,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSHR",
-      "canonical_name": "TSHR",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "TSHR: Elementwise shift-right of two tiles.",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/npu/a2a3/TShr.hpp; pto/npu/a5/TShr.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x00A",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x00A",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_SHR"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 10,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 12,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCMP",
-      "canonical_name": "TCMP",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst predicate/mask tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile + CmpMode attr",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Input: U32, S32, U16, S16, U8, S8, F32, F16; output mask: U32",
-        "values": [
-          "Input: U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8",
-          "F32",
-          "F16; output mask: U32"
-        ]
-      },
-      "description": "Compare two tiles and write a packed predicate mask",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/ElementTileOp.h; pto/npu/a2a3/TCmp.hpp; pto/npu/a5/TCmp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x02B",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x00D",
+      "semantic_handler": "ExecuteTileCompare",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        },
+        {
+          "field": "comparison",
+          "role": "comparison"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "comparison"
+        }
+      ],
+      "mode": 0,
+      "function": 13,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileCompare",
+      "effect_contract": "ExecuteTileCompare",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right",
+        "operand:comparison:comparison"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "CMode"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 13,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSEL",
-      "canonical_name": "TSEL",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst (output; TileData)",
-        "input_0": "selMask (arg; MaskTile)",
-        "input_1_or_attributes": "src0 (input; TileData)",
-        "input_2_or_extra_attributes": "src1 (input; TileData); tmp (tmp; TmpTile)"
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent; see public signature",
-        "values": [
-          "Template-dependent; see public signature"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TSEL(TileData &dst, MaskTile &selMask, TileData &src0, TileData &src1, TmpTile &tmp, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY (inserted missing API)",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TSel.hpp; pto/npu/a2a3/TSel.hpp; pto/npu/a5/TSel.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x02C",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x01A",
+      "semantic_handler": "ExecuteTileSelect",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "mask"
+        },
+        {
+          "field": "source1",
+          "role": "source-true"
+        },
+        {
+          "field": "source2",
+          "role": "source-false"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        }
+      ],
+      "mode": 0,
+      "function": 26,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileSelect",
+      "effect_contract": "ExecuteTileSelect",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:mask",
+        "operand:source1:source-true",
+        "operand:source2:source-false"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 14,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TABS",
-      "canonical_name": "TABS",
-      "category": "逐元素单目运算",
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F32, F16",
-        "values": [
-          "F32",
-          "F16"
-        ]
-      },
-      "description": "Elementwise absolute value of a tile",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TAbs.hpp; pto/npu/a2a3/TUnaryOp.hpp; pto/npu/a5/TUnaryOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x02D",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x00F",
+      "semantic_handler": "ExecuteTileUnary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileUnary_ABS"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 15,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+      "effect_contract": "ExecuteTileUnary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 15,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TNOT",
-      "canonical_name": "TNOT",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "TNOT: Elementwise bitwise NOT of a tile.",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/npu/a2a3/TUnaryOp.hpp; pto/npu/a5/TUnaryOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x02E",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x010",
+      "semantic_handler": "ExecuteTileUnary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileUnary_NOT"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 16,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+      "effect_contract": "ExecuteTileUnary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 16,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TNEG",
-      "canonical_name": "TNEG",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, S16, F32, F16, BF16",
-        "values": [
-          "S32",
-          "S16",
-          "F32",
-          "F16",
-          "BF16"
-        ]
-      },
-      "description": "TNEG: Elementwise negation of a tile.",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/npu/a2a3/TUnaryOp.hpp; pto/npu/a5/TUnaryOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x02F",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x011",
+      "semantic_handler": "ExecuteTileUnary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileUnary_NEG"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 17,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+      "effect_contract": "ExecuteTileUnary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 17,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TRELU",
-      "canonical_name": "TRELU",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32, S32",
-        "values": [
-          "F16",
-          "F32",
-          "S32"
-        ]
-      },
-      "description": "TRELU: Elementwise ReLU of a tile.",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/npu/a2a3/TUnaryOp.hpp; pto/npu/a5/TUnaryOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x00B",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x017",
+      "semantic_handler": "ExecuteTileUnary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileUnary_RELU"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 23,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+      "effect_contract": "ExecuteTileUnary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 18,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TPRELU",
+      "selector": "0x00E",
+      "semantic_handler": "TPRELU",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "negative-slope"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 0,
+      "function": 14,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TPRELU",
+      "effect_contract": "TPRELU",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:negative-slope"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
+      }
+    },
+    {
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TDIV",
-      "canonical_name": "TDIV",
-      "category": "逐元素超越函数",
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, U32, F32, S16, U16, F16",
-        "values": [
-          "S32",
-          "U32",
-          "F32",
-          "S16",
-          "U16",
-          "F16"
-        ]
-      },
-      "description": "Elementwise division of two tiles (tilebuf, DPS)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TDiv.hpp; pto/npu/a2a3/TDiv.hpp; pto/npu/a5/TDiv.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x003",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x003",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_DIV"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 3,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 19,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TREM",
-      "canonical_name": "TREM",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile; PTOAS form also declares tmp tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F32, S32, U32, F16, S16, U16",
-        "values": [
-          "F32",
-          "S32",
-          "U32",
-          "F16",
-          "S16",
-          "U16"
-        ]
-      },
-      "description": "TREM: Elementwise remainder of two tiles.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/ElementTileOp.h; pto/npu/a2a3/TRem.hpp; pto/npu/a5/TRem.hpp; pto/npu/kirin9030/TRem.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x030",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x004",
+      "semantic_handler": "ExecuteTileBinary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_REM"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 0,
+      "function": 4,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileBinary",
+      "effect_contract": "ExecuteTileBinary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 20,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSQRT",
-      "canonical_name": "TSQRT",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F32, F16",
-        "values": [
-          "F32",
-          "F16"
-        ]
-      },
-      "description": "TSQRT: Elementwise square root.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TSqrt.hpp; pto/npu/a2a3/TUnaryOp.hpp; pto/npu/a5/TUnaryOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x010",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x015",
+      "semantic_handler": "ExecuteTileUnary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileUnary_SQRT"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 21,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+      "effect_contract": "ExecuteTileUnary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 21,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TLOG",
-      "canonical_name": "TLOG",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F32, F16",
-        "values": [
-          "F32",
-          "F16"
-        ]
-      },
-      "description": "Elementwise natural logarithm (tilebuf, DPS)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/ElementTileOp.h; pto/npu/a2a3/TUnaryOp.hpp; pto/npu/a5/TUnaryOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x00F",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x013",
+      "semantic_handler": "ExecuteTileUnary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileUnary_LOG"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 19,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+      "effect_contract": "ExecuteTileUnary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 22,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TRECIP",
-      "canonical_name": "TRECIP",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F32, F16",
-        "values": [
-          "F32",
-          "F16"
-        ]
-      },
-      "description": "TRECIP: Elementwise reciprocal of a tile.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: A2A3, A5, Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/ElementTileOp.h",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x018",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x014",
+      "semantic_handler": "ExecuteTileUnary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileUnary_RECIP"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 20,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+      "effect_contract": "ExecuteTileUnary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 23,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TEXP",
-      "canonical_name": "TEXP",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F32, F16",
-        "values": [
-          "F32",
-          "F16"
-        ]
-      },
-      "description": "Elementwise exponential (tilebuf, DPS)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/ElementTileOp.h; pto/npu/a2a3/TUnaryOp.hpp; pto/npu/a5/TUnaryOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x00E",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x012",
+      "semantic_handler": "ExecuteTileUnary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileUnary_EXP"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 18,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+      "effect_contract": "ExecuteTileUnary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 24,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TRSQRT",
-      "canonical_name": "TRSQRT",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F32, F16",
-        "values": [
-          "F32",
-          "F16"
-        ]
-      },
-      "description": "TRSQRT: Elementwise reciprocal square root.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TRSqrt.hpp; pto/npu/a2a3/TUnaryOp.hpp; pto/npu/a5/TRsqrt.hpp; pto/npu/a5/TUnaryOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x011",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x016",
+      "semantic_handler": "ExecuteTileUnary",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileUnary_RSQRT"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 22,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileUnary",
+      "effect_contract": "ExecuteTileUnary",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 25,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TADDS",
-      "canonical_name": "TADDS",
-      "category": "逐元素与标量运算",
-      "subcategory": "算术运算",
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar GPR/immediate (via B.IOR)",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U8, S8, U16, S16, U32, S32, F16, F32, BF16",
-        "values": [
-          "U8",
-          "S8",
-          "U16",
-          "S16",
-          "U32",
-          "S32",
-          "F16",
-          "F32",
-          "BF16"
-        ]
-      },
-      "description": "Elementwise add scalar to tile over the destination valid region.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TAddS.hpp; pto/npu/a5/TAddS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x020",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x020",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_ADD"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 0,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 26,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TAXPY",
-      "canonical_name": "TAXPY",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst (output; TileDataDst)",
-        "input_0": "src0 (input; TileDataSrc)",
-        "input_1_or_attributes": "scalar (attr; typename TileDataSrc::DType)",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent; see public signature",
-        "values": [
-          "Template-dependent; see public signature"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TAXPY(TileDataDst &dst, TileDataSrc &src0, typename TileDataSrc::DType scalar, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY (inserted missing API)",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TAxpy.hpp; pto/npu/a5/TAxpy.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x031",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x02F",
+      "semantic_handler": "ExecuteTileAxpy",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 15,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileAxpy",
+      "effect_contract": "ExecuteTileAxpy",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 27,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSUBS",
-      "canonical_name": "TSUBS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, S16, F16, F32",
-        "values": [
-          "S32",
-          "S16",
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TSUBS: Elementwise subtract a scalar from a tile.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TSubS.hpp; pto/npu/a5/TSubS.hpp; pto/npu/kirin9030/TSubS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x021",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x021",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_SUB"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 1,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 28,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TMULS",
-      "canonical_name": "TMULS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U8, S8, U16, S16, U32, S32, F16, F32, BF16",
-        "values": [
-          "U8",
-          "S8",
-          "U16",
-          "S16",
-          "U32",
-          "S32",
-          "F16",
-          "F32",
-          "BF16"
-        ]
-      },
-      "description": "TMULS: Elementwise multiply a tile by a scalar.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TMulS.hpp; pto/npu/a5/TMulS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x022",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x022",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_MUL"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 2,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 29,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TDIVS",
-      "canonical_name": "TDIVS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U8, S8, U16, S16, U32, S32, F16, F32",
-        "values": [
-          "U8",
-          "S8",
-          "U16",
-          "S16",
-          "U32",
-          "S32",
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Elementwise division with a scalar (tilebuf, DPS)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TDivS.hpp; pto/npu/a5/TDivS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x023",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x023",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_DIV"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 3,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 30,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TMINS",
-      "canonical_name": "TMINS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U8, S8, U16, S16, U32, S32, F16, F32, BF16",
-        "values": [
-          "U8",
-          "S8",
-          "U16",
-          "S16",
-          "U32",
-          "S32",
-          "F16",
-          "F32",
-          "BF16"
-        ]
-      },
-      "description": "Elementwise minimum of a tile and a scalar (tilebuf, DPS)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TMins.hpp; pto/npu/a5/TMins.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x025",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x02C",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_MIN"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 12,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 31,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TMAXS",
-      "canonical_name": "TMAXS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, U32, F32, S16, U16, F16, BF16, U8, S8",
-        "values": [
-          "S32",
-          "U32",
-          "F32",
-          "S16",
-          "U16",
-          "F16",
-          "BF16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "Elementwise max of a tile and a scalar (tilebuf, DPS)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TMaxS.hpp; pto/npu/a5/TMaxs.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x024",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x02B",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_MAX"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 11,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 32,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TREMS",
-      "canonical_name": "TREMS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value; PTOAS form also declares tmp tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F32, S32, U32, F16, S16, U16",
-        "values": [
-          "F32",
-          "S32",
-          "U32",
-          "F16",
-          "S16",
-          "U16"
-        ]
-      },
-      "description": "TREMS: Elementwise remainder with a scalar",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TRemS.hpp; pto/npu/a5/TRemS.hpp; pto/npu/kirin9030/TRemS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x032",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x024",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_REM"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 4,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 33,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TANDS",
-      "canonical_name": "TANDS",
-      "category": null,
-      "subcategory": "逻辑运算",
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "TANDS(dst, src, scalar) bitwise-and tile with scalar",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TBitwiseSOp.hpp; pto/npu/a5/TAndS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x026",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x026",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_AND"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 6,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 34,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TORS",
-      "canonical_name": "TORS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "TORS: Elementwise bitwise OR of a tile and a scalar.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TBitwiseSOp.hpp; pto/npu/a5/TOrS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x027",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x027",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_OR"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 7,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 35,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TXORS",
-      "canonical_name": "TXORS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value; PTOAS form also declares tmp tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, U16, S16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "U16",
-          "S16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "TXORS: Elementwise bitwise XOR of a tile and a scalar.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TBitwiseSOp.hpp; pto/npu/a5/TXorS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x028",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x028",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_XOR"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 8,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 36,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCMPS",
-      "canonical_name": "TCMPS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst predicate/mask tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar + CmpMode attr",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Input: S32, F32, F16, U16, S16; output mask: U32",
-        "values": [
-          "Input: S32",
-          "F32",
-          "F16",
-          "U16",
-          "S16; output mask: U32"
-        ]
-      },
-      "description": "Compare scalar value against a tile and write a packed predicate mask",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TCmps.hpp; pto/npu/a2a3/TCmps.hpp; pto/npu/a5/TCmps.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x033",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x02D",
+      "semantic_handler": "ExecuteTileCompareScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        },
+        {
+          "field": "comparison",
+          "role": "comparison"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        },
+        {
+          "operand": "comparison"
+        }
+      ],
+      "mode": 1,
+      "function": 13,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileCompareScalar",
+      "effect_contract": "ExecuteTileCompareScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar",
+        "operand:comparison:comparison"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "CMode"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 37,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSELS",
-      "canonical_name": "TSELS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst (output; TileDataDst)",
-        "input_0": "mask (arg; TileDataMask)",
-        "input_1_or_attributes": "src (input; TileDataSrc)",
-        "input_2_or_extra_attributes": "tmp (tmp; TileDataTmp); scalar (attr; typename TileDataSrc::DType)"
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent; see public signature",
-        "values": [
-          "Template-dependent; see public signature"
-        ]
-      },
-      "description": "s",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY (inserted missing API)",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TSelS.hpp; pto/npu/a2a3/TSels.hpp; pto/npu/a5/TSels.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x034",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x03A",
+      "semantic_handler": "ExecuteTileSelectScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "mask"
+        },
+        {
+          "field": "source1",
+          "role": "source-true"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar-false"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 26,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileSelectScalar",
+      "effect_contract": "ExecuteTileSelectScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:mask",
+        "operand:source1:source-true",
+        "operand:scalar0:scalar-false"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 38,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSHLS",
-      "canonical_name": "TSHLS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, S16, S8, U32, U16, U8",
-        "values": [
-          "S32",
-          "S16",
-          "S8",
-          "U32",
-          "U16",
-          "U8"
-        ]
-      },
-      "description": "TSHLS: Elementwise shift-left of a tile by a scalar (shift count).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TBitwiseSOp.hpp; pto/npu/a5/TShlS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x029",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x029",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_SHL"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 9,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 39,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSHRS",
-      "canonical_name": "TSHRS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scalar value",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, S16, S8, U32, U16, U8",
-        "values": [
-          "S32",
-          "S16",
-          "S8",
-          "U32",
-          "U16",
-          "U8"
-        ]
-      },
-      "description": "TSHRS: Elementwise shift-right of a tile by a scalar (shift count).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TBinSOps.hpp; pto/npu/a2a3/TBitwiseSOp.hpp; pto/npu/a5/TShrS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x02A",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x02A",
+      "semantic_handler": "ExecuteTileScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileBinary_SHR"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 10,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileScalar",
+      "effect_contract": "ExecuteTileScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 40,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWSUM",
-      "canonical_name": "TROWSUM",
-      "category": "归约运算",
-      "subcategory": "归约为一列",
-      "operands": {
-        "outputs": "dst 1D tile, one value per row",
-        "input_0": "src 2D tile",
-        "input_1_or_attributes": null,
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Reduce each source row by summing across columns.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TRowSum.hpp; pto/npu/a2a3/TRowReduceOps.hpp; pto/npu/a2a3/TRowSum.hpp; pto/npu/a5/TRowReduce.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x014",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x040",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_SUM"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 0,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 41,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWPROD",
-      "canonical_name": "TROWPROD",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst column/vector tile, one value per row",
-        "input_0": "src 2D tile",
-        "input_1_or_attributes": "tmp tile for accumulation/index tracking",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32, S32, S16",
-        "values": [
-          "F16",
-          "F32",
-          "S32",
-          "S16"
-        ]
-      },
-      "description": "TROWPROD: Reduce each row by multiplying across columns.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TRowProd.hpp; pto/npu/a2a3/TRowProd.hpp; pto/npu/a2a3/TRowReduceOps.hpp; pto/npu/a5/TRowProd.hpp; pto/npu/a5/TRowReduce.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x035",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x043",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_PRODUCT"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 3,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 42,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWMAX",
-      "canonical_name": "TROWMAX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst column/vector tile, one value per row",
-        "input_0": "src 2D tile",
-        "input_1_or_attributes": "tmp tile for accumulation/index tracking",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TROWMAX: Reduce each row by taking the maximum across columns.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TRowMax.hpp; pto/npu/a2a3/TRowMax.hpp; pto/npu/a2a3/TRowReduceOps.hpp; pto/npu/a5/TRowReduce.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x012",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x041",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_MAX"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 1,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 43,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWMIN",
-      "canonical_name": "TROWMIN",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst column/vector tile, one value per row",
-        "input_0": "src 2D tile",
-        "input_1_or_attributes": "tmp tile for accumulation/index tracking",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TROWMIN: Reduce each row by taking the minimum across columns.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TRowMin.hpp; pto/npu/a2a3/TRowMin.hpp; pto/npu/a2a3/TRowReduceOps.hpp; pto/npu/a5/TRowReduce.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x013",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x042",
+      "semantic_handler": "ExecuteTileReduction",
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+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_MIN"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 2,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 44,
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       "name": "TROWARGMAX",
-      "canonical_name": "TROWARGMAX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst column-index vector tile",
-        "input_0": "src 2D tile",
-        "input_1_or_attributes": "tmp tile for accumulation/index tracking",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "src: F16, F32; dst index: U32, S32",
-        "values": [
-          "src: F16",
-          "F32; dst index: U32",
-          "S32"
-        ]
-      },
-      "description": "TROWARGMAX: Reduce each row to the column index of the maximum element.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
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-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x036",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x04C",
+      "semantic_handler": "ExecuteTileReduction",
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+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_ARGMAX"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
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+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 45,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWARGMIN",
-      "canonical_name": "TROWARGMIN",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst column-index vector tile",
-        "input_0": "src 2D tile",
-        "input_1_or_attributes": "tmp tile for accumulation/index tracking",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "src: F16, F32; dst index: U32, S32",
-        "values": [
-          "src: F16",
-          "F32; dst index: U32",
-          "S32"
-        ]
-      },
-      "description": "TROWARGMIN: Reduce each row to the column index of the minimum element.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
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-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x037",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x04D",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_ARGMIN"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 13,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 46,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLSUM",
-      "canonical_name": "TCOLSUM",
-      "category": null,
-      "subcategory": "归约为一行",
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-        "outputs": "dst row/vector tile, one value per column",
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-        "input_2_or_extra_attributes": null
-      },
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-          "F16",
-          "F32",
-          "S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "BF16"
-        ]
-      },
-      "description": "Reduce each column by summing across rows (tilebuf-based, explicit tmp)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TColSum.hpp; pto/npu/a2a3/TColReduceOps.hpp; pto/npu/a2a3/TColSum.hpp; pto/npu/a5/TColReduceOps.hpp; pto/npu/a5/TColSum.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x017",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x050",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_SUM"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 16,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 47,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLPROD",
-      "canonical_name": "TCOLPROD",
-      "category": null,
-      "subcategory": null,
-      "operands": {
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-      },
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-          "F16",
-          "F32",
-          "BF16",
-          "S16",
-          "U16",
-          "S32",
-          "U32"
-        ]
-      },
-      "description": "Reduce each column by multiplying across rows",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColProd.hpp; pto/npu/a2a3/TColProd.hpp; pto/npu/a2a3/TColReduceOps.hpp; pto/npu/a5/TColProd.hpp; pto/npu/a5/TColReduceOps.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x038",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x053",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_PRODUCT"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
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+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 48,
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+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLMAX",
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-      "subcategory": null,
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-      },
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-          "F16",
-          "F32",
-          "S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "BF16"
-        ]
-      },
-      "description": "Reduce each column by taking the maximum across rows",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColMax.hpp; pto/npu/a2a3/TColMax.hpp; pto/npu/a2a3/TColReduceOps.hpp; pto/npu/a5/TColMax.hpp; pto/npu/a5/TColReduceOps.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x015",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x051",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_MAX"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 17,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 49,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLMIN",
-      "canonical_name": "TCOLMIN",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst row/vector tile, one value per column",
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-        "input_1_or_attributes": "optional tmp/dependency attrs",
-        "input_2_or_extra_attributes": null
-      },
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-        "values": [
-          "F16",
-          "F32",
-          "S8",
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-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "BF16"
-        ]
-      },
-      "description": "Reduce each column by taking the minimum across rows",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
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-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x016",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x052",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_MIN"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 18,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 50,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLARGMAX",
-      "canonical_name": "TCOLARGMAX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst row-index vector tile",
-        "input_0": "src 2D tile",
-        "input_1_or_attributes": "tmp tile for accumulation/index tracking",
-        "input_2_or_extra_attributes": null
-      },
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-        "values": [
-          "src: S8",
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-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "F16",
-          "F32; dst index: U32",
-          "S32"
-        ]
-      },
-      "description": "Reduce each column to the row index of the maximum element",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TReduceIdx.hpp; pto/npu/a2a3/TColReduceIdx.hpp; pto/npu/a5/TColReduceIdx.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x039",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x05C",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_ARGMAX"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 28,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 51,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLARGMIN",
-      "canonical_name": "TCOLARGMIN",
-      "category": null,
-      "subcategory": null,
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-        "input_0": "src 2D tile",
-        "input_1_or_attributes": "tmp tile for accumulation/index tracking",
-        "input_2_or_extra_attributes": null
-      },
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-          "src: S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "F16",
-          "F32; dst index: U32",
-          "S32"
-        ]
-      },
-      "description": "Reduce each column to the row index of the minimum element",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TReduceIdx.hpp; pto/npu/a2a3/TColReduceIdx.hpp; pto/npu/a5/TColReduceIdx.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x03A",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x05D",
+      "semantic_handler": "ExecuteTileReduction",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileReduction_ARGMIN"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 2,
+      "function": 29,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileReduction",
+      "effect_contract": "ExecuteTileReduction",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 52,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWEXPAND",
-      "canonical_name": "TROWEXPAND",
-      "category": "广播运算",
-      "subcategory": "按行广播",
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "row vector/source tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S8, U8, S16, U16, S32, U32, F16, BF16, F32",
-        "values": [
-          "S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "F16",
-          "BF16",
-          "F32"
-        ]
-      },
-      "description": "TROWEXPAND: Broadcast the first element of each source row across the destination row.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TRowExpand.hpp; pto/npu/a2a3/TRowExpand.hpp; pto/npu/a5/TRowExpand.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x01F",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x044",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_COPY"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 4,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 53,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWEXPANDADD",
-      "canonical_name": "TROWEXPANDADD",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "row vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TROWEXPANDADD: Row-wise broadcast add: add a per-row scalar vector src1 to each row of src0.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TRowExpandOp.hpp; pto/npu/a2a3/TRowExpandAdd.hpp; pto/npu/a2a3/TRowExpandBinOp.hpp; pto/npu/a5/TRowExpandAdd.hpp; pto/npu/a5/TRowExpandBinOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x03B",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x045",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_ADD"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 5,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 54,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWEXPANDSUB",
-      "canonical_name": "TROWEXPANDSUB",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "row vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TROWEXPANDSUB: Row-wise broadcast subtract: subtract a per-row scalar vector src1 from each row of src0.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TRowExpandOp.hpp; pto/npu/a2a3/TRowExpandBinOp.hpp; pto/npu/a2a3/TRowExpandSub.hpp; pto/npu/a5/TRowExpandBinOp.hpp; pto/npu/a5/TRowExpandSub.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x03C",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x046",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_SUB"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 6,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 55,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWEXPANDMUL",
-      "canonical_name": "TROWEXPANDMUL",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "row vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TROWEXPANDMUL: Row-wise broadcast multiply with per-row scalar vector.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TRowExpandOp.hpp; pto/npu/a2a3/TRowExpandBinOp.hpp; pto/npu/a2a3/TRowExpandMul.hpp; pto/npu/a5/TRowExpandBinOp.hpp; pto/npu/a5/TRowExpandMul.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x03D",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x047",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_MUL"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 7,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 56,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWEXPANDDIV",
-      "canonical_name": "TROWEXPANDDIV",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "row vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TROWEXPANDDIV: Row-wise broadcast divide: divide each row of src0 by a per-row scalar vector src1.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TRowExpandOp.hpp; pto/npu/a2a3/TRowExpandBinOp.hpp; pto/npu/a2a3/TRowExpandDiv.hpp; pto/npu/a5/TRowExpandBinOp.hpp; pto/npu/a5/TRowExpandDiv.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x03E",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x048",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_DIV"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 8,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 57,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWEXPANDMAX",
-      "canonical_name": "TROWEXPANDMAX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "row vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TROWEXPANDMAX: Row-wise broadcast max with per-row scalar vector.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TRowExpandOp.hpp; pto/npu/a2a3/TRowExpandBinOp.hpp; pto/npu/a2a3/TRowExpandMax.hpp; pto/npu/a5/TRowExpandBinOp.hpp; pto/npu/a5/TRowExpandMax.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x03F",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x049",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_MAX"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 9,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 58,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWEXPANDMIN",
-      "canonical_name": "TROWEXPANDMIN",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "row vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TROWEXPANDMIN: Row-wise broadcast min with per-row scalar vector.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TRowExpandOp.hpp; pto/npu/a2a3/TRowExpandBinOp.hpp; pto/npu/a2a3/TRowExpandMin.hpp; pto/npu/a5/TRowExpandBinOp.hpp; pto/npu/a5/TRowExpandMin.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x040",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x04A",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_MIN"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 10,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 59,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TROWEXPANDEXPDIF",
-      "canonical_name": "TROWEXPANDEXPDIF",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "row vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "TROWEXPANDEXPDIF: Row-wise broadcast expdif with per-row scalar vector.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TRowExpandOp.hpp; pto/npu/a2a3/TRowExpandBinOp.hpp; pto/npu/a2a3/TRowExpandExpdif.hpp; pto/npu/a5/TRowExpandBinOp.hpp; pto/npu/a5/TRowExpandExpdif.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x041",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x04B",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_EXPDIF"
+        },
+        {
+          "constant": "TileAxis_Row"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 11,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 60,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLEXPAND",
-      "canonical_name": "TCOLEXPAND",
-      "category": null,
-      "subcategory": "按列广播",
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "column vector/source tile",
-        "input_1_or_attributes": "-",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S8, U8, S16, U16, S32, U32, F16, BF16, F32",
-        "values": [
-          "S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "F16",
-          "BF16",
-          "F32"
-        ]
-      },
-      "description": "Broadcast src(0, j) to all rows in column j",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColExpand.hpp; pto/npu/a2a3/TColExpand.hpp; pto/npu/a5/TColExpand.hpp; pto/npu/a5/TColExpandBinOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x01E",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x054",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_COPY"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 20,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 61,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLEXPANDADD",
-      "canonical_name": "TCOLEXPANDADD",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "column vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Column-wise broadcast add: add a per-column scalar vector src1 to src0",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColExpandOp.hpp; pto/npu/a2a3/TColExpandAdd.hpp; pto/npu/a2a3/TColExpandBinOp.hpp; pto/npu/a5/TColExpandAdd.hpp; pto/npu/a5/TColExpandBinOp.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x042",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x055",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_ADD"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 21,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 62,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLEXPANDSUB",
-      "canonical_name": "TCOLEXPANDSUB",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "column vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Column-wise broadcast subtract: subtract a per-column scalar vector src1 from src0",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColExpandOp.hpp; pto/npu/a2a3/TColExpandBinOp.hpp; pto/npu/a2a3/TColExpandSub.hpp; pto/npu/a5/TColExpandBinOp.hpp; pto/npu/a5/TColExpandSub.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x043",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x056",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_SUB"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 22,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 63,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLEXPANDMUL",
-      "canonical_name": "TCOLEXPANDMUL",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "column vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Column-wise broadcast multiply: multiply each element of src0 by a per-column scalar vector src1",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColExpandOp.hpp; pto/npu/a2a3/TColExpandBinOp.hpp; pto/npu/a2a3/TColExpandMul.hpp; pto/npu/a5/TColExpandBinOp.hpp; pto/npu/a5/TColExpandMul.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x044",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x057",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_MUL"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 23,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 64,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLEXPANDDIV",
-      "canonical_name": "TCOLEXPANDDIV",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "column vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Column-wise broadcast divide: divide each element of src0 by a per-column scalar vector src1",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColExpandOp.hpp; pto/npu/a2a3/TColExpandBinOp.hpp; pto/npu/a2a3/TColExpandDiv.hpp; pto/npu/a5/TColExpandBinOp.hpp; pto/npu/a5/TColExpandDiv.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x045",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x058",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_DIV"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 24,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 65,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLEXPANDMAX",
-      "canonical_name": "TCOLEXPANDMAX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "column vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Column-wise broadcast max: take max(src0, src1) using a per-column scalar vector src1",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColExpandOp.hpp; pto/npu/a2a3/TColExpandBinOp.hpp; pto/npu/a2a3/TColExpandMax.hpp; pto/npu/a5/TColExpandBinOp.hpp; pto/npu/a5/TColExpandMax.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x046",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x059",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_MAX"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 25,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 66,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLEXPANDMIN",
-      "canonical_name": "TCOLEXPANDMIN",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "column vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Column-wise broadcast min: take min(src0, src1) using a per-column scalar vector src1",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColExpandOp.hpp; pto/npu/a2a3/TColExpandBinOp.hpp; pto/npu/a2a3/TColExpandMin.hpp; pto/npu/a5/TColExpandBinOp.hpp; pto/npu/a5/TColExpandMin.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x047",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x05A",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_MIN"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 26,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 67,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCOLEXPANDEXPDIF",
-      "canonical_name": "TCOLEXPANDEXPDIF",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "column vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Column-wise broadcast expdif: compute exp(src0 - src1) using a per-column scalar vector src1",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TColExpandOp.hpp; pto/npu/a2a3/TColExpandBinOp.hpp; pto/npu/a2a3/TColExpandExpdif.hpp; pto/npu/a5/TColExpandBinOp.hpp; pto/npu/a5/TColExpandExpdif.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x048",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x05B",
+      "semantic_handler": "ExecuteTileExpand",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "broadcast-source"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TileExpand_EXPDIF"
+        },
+        {
+          "constant": "TileAxis_Column"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 2,
+      "function": 27,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileExpand",
+      "effect_contract": "ExecuteTileExpand",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:broadcast-source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 68,
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMUL",
+      "function": 0,
       "name": "TMATMUL",
-      "canonical_name": "TMATMUL",
-      "category": "矩阵运算",
-      "subcategory": "矩阵乘矩阵",
-      "operands": {
-        "outputs": "ACC destination",
-        "input_0": "A matrix tile",
-        "input_1_or_attributes": "B matrix tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "ACC S32 = S8xS8; ACC F32 = F16/BF16/F32 and selected FP8 pairs",
-        "values": [
-          "ACC S32 = S8xS8; ACC F32 = F16/BF16/F32 and selected FP8 pairs"
-        ]
-      },
-      "description": "PE-local CUBE matrix multiply: C[i,j] = sum_k(A[i,k] * B[k,j]).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TMatmul.hpp; pto/npu/a2a3/TMatmul.hpp; pto/npu/a5/TMatmul.hpp; pto/npu/kirin9030/TMatmul.hpp",
-      "disposition": {
-        "family": "CUBE",
-        "function": 0,
-        "encoding_mnemonic": "BSTART.TMATMUL"
+      "semantic_handler": "TMATMUL",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "left"
+        },
+        {
+          "field": "source1",
+          "role": "right"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "constant": "FALSE"
+        }
+      ],
+      "acc_effect": "write-initialize",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TMATMUL",
+      "effect_contract": "TMATMUL",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:left",
+        "operand:source1:right",
+        "implicit:ACC:write-initialize"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 69,
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMUL.BIAS",
+      "function": 1,
       "name": "TMATMUL_BIAS",
-      "canonical_name": "TMATMUL_BIAS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst C/acc tile",
-        "input_0": "A/lhs tile",
-        "input_1_or_attributes": "B/rhs tile + bias tile",
-        "input_2_or_extra_attributes": "optional ExtraTile (input ACC/bias/scale per opcode profile)"
-      },
-      "supported_dtype_format": {
-        "raw": "Same as TMATMUL; bias dtype matches ACC/result dtype",
-        "values": [
-          "Same as TMATMUL; bias dtype matches ACC/result dtype"
-        ]
-      },
-      "description": "Matmul with bias add (tile world, ins/outs).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TMatmul.hpp; pto/npu/a2a3/TMatmul.hpp; pto/npu/a5/TMatmul.hpp; pto/npu/kirin9030/TMatmul.hpp",
-      "disposition": {
-        "family": "CUBE",
-        "function": 1,
-        "encoding_mnemonic": "BSTART.TMATMUL.BIAS"
+      "semantic_handler": "TMATMUL_BIAS",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "left"
+        },
+        {
+          "field": "source1",
+          "role": "right"
+        },
+        {
+          "field": "source2",
+          "role": "bias"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        }
+      ],
+      "acc_effect": "write-initialize",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TMATMUL_BIAS",
+      "effect_contract": "TMATMUL_BIAS",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:left",
+        "operand:source1:right",
+        "operand:source2:bias",
+        "implicit:ACC:write-initialize"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 70,
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMUL.ACC",
+      "function": 2,
       "name": "TMATMUL_ACC",
-      "canonical_name": "TMATMUL_ACC",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "ACC destination",
-        "input_0": "A/source tile",
-        "input_1_or_attributes": "B/source tile",
-        "input_2_or_extra_attributes": "optional ExtraTile (input ACC/bias/scale per opcode profile)"
-      },
-      "supported_dtype_format": {
-        "raw": "Same as TMATMUL; input/output ACC dtype follows CUBE profile",
-        "values": [
-          "Same as TMATMUL; input/output ACC dtype follows CUBE profile"
-        ]
-      },
-      "description": "PE-local CUBE matrix multiply accumulate; variant operands are profile-specific.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TMatmul.hpp; pto/npu/a2a3/TMatmul.hpp; pto/npu/a5/TMatmul.hpp; pto/npu/kirin9030/TMatmul.hpp",
-      "disposition": {
-        "family": "CUBE",
-        "function": 2,
-        "encoding_mnemonic": "BSTART.TMATMUL.ACC"
+      "semantic_handler": "TMATMUL_ACC",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "left"
+        },
+        {
+          "field": "source1",
+          "role": "right"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "acc_effect": "read-write",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TMATMUL_ACC",
+      "effect_contract": "TMATMUL_ACC",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:left",
+        "operand:source1:right",
+        "implicit:ACC:read-write"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 71,
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMULMX",
+      "function": 4,
       "name": "TMATMUL_MX",
-      "canonical_name": "TMATMUL_MX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst C/acc tile",
-        "input_0": "A/lhs tile",
-        "input_1_or_attributes": "A scale tile + B/rhs tile + B scale tile",
-        "input_2_or_extra_attributes": "optional ExtraTile (input ACC/bias/scale per opcode profile)"
-      },
-      "supported_dtype_format": {
-        "raw": "MX profile-defined: source F16/BF16/F32 or FP8/FP4; scale/bias/ACC follow MX profile",
-        "values": [
-          "MX profile-defined: source F16/BF16/F32 or FP8/FP4; scale/bias/ACC follow MX profile"
-        ]
-      },
-      "description": "Matmul mx (tile world, ins/outs).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "MISSING",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: A2A3",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 3 | impl: pto/cpu/TMatmul.hpp; pto/npu/a5/TMatmul.hpp; pto/npu/kirin9030/TMatmul.hpp",
-      "disposition": {
-        "family": "CUBE",
-        "function": 4,
-        "encoding_mnemonic": "BSTART.TMATMULMX"
+      "semantic_handler": "TMATMUL_MX",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "left"
+        },
+        {
+          "field": "source1",
+          "role": "right"
+        },
+        {
+          "field": "source2",
+          "role": "row-scale"
+        },
+        {
+          "field": "source3",
+          "role": "column-scale"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        },
+        {
+          "operand": "source3"
+        }
+      ],
+      "acc_effect": "write-initialize",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TMATMUL_MX",
+      "effect_contract": "TMATMUL_MX",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:left",
+        "operand:source1:right",
+        "operand:source2:row-scale",
+        "operand:source3:column-scale",
+        "implicit:ACC:write-initialize"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 72,
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMULMX.BIAS",
+      "function": 5,
+      "name": "TMATMUL_MX_BIAS",
+      "semantic_handler": "TMATMUL_MX_BIAS",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "left"
+        },
+        {
+          "field": "source1",
+          "role": "right"
+        },
+        {
+          "field": "source2",
+          "role": "row-scale"
+        },
+        {
+          "field": "source3",
+          "role": "column-scale"
+        },
+        {
+          "field": "source4",
+          "role": "bias"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        },
+        {
+          "operand": "source3"
+        },
+        {
+          "operand": "source4"
+        }
+      ],
+      "acc_effect": "write-initialize",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TMATMUL_MX_BIAS",
+      "effect_contract": "TMATMUL_MX_BIAS",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:left",
+        "operand:source1:right",
+        "operand:source2:row-scale",
+        "operand:source3:column-scale",
+        "operand:source4:bias",
+        "implicit:ACC:write-initialize"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
+      }
+    },
+    {
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TMATMULMX.ACC",
+      "function": 6,
+      "name": "TMATMUL_MX_ACC",
+      "semantic_handler": "TMATMUL_MX_ACC",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "left"
+        },
+        {
+          "field": "source1",
+          "role": "right"
+        },
+        {
+          "field": "source2",
+          "role": "row-scale"
+        },
+        {
+          "field": "source3",
+          "role": "column-scale"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        },
+        {
+          "operand": "source3"
+        }
+      ],
+      "acc_effect": "read-write",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TMATMUL_MX_ACC",
+      "effect_contract": "TMATMUL_MX_ACC",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:left",
+        "operand:source1:right",
+        "operand:source2:row-scale",
+        "operand:source3:column-scale",
+        "implicit:ACC:read-write"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
+      }
+    },
+    {
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.ACCCVT",
+      "function": 8,
+      "name": "ACCCVT",
+      "semantic_handler": "ACCCVT",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        }
+      ],
+      "acc_effect": "read-release-on-commit",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ACCCVT",
+      "effect_contract": "ACCCVT",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "implicit:ACC:read-release-on-commit"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Sat",
+          "Canonicalize",
+          "DataType",
+          "RMode",
+          "Layout"
+        ],
+        "pad_union": "must-zero"
+      }
+    },
+    {
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMV",
+      "function": 16,
       "name": "TGEMV",
-      "canonical_name": "TGEMV",
-      "category": null,
-      "subcategory": "矩阵乘向量",
-      "operands": {
-        "outputs": "dst C/acc tile",
-        "input_0": "A/lhs tile",
-        "input_1_or_attributes": "B/rhs tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "ACC S32 = S8xS8; ACC F32 = F16/BF16/F32 and selected FP8 pairs",
-        "values": [
-          "ACC S32 = S8xS8; ACC F32 = F16/BF16/F32 and selected FP8 pairs"
-        ]
-      },
-      "description": "PTO matrix-vector multiplication operation (optional bias), destination-style (DPS) in tile world.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TMatmul.hpp; pto/npu/a2a3/TMatmul.hpp; pto/npu/a5/TMatmul.hpp; pto/npu/kirin9030/TMatmul.hpp",
-      "disposition": {
-        "family": "CUBE",
-        "function": 16,
-        "encoding_mnemonic": "BSTART.TGEMV"
+      "semantic_handler": "TGEMV",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "matrix"
+        },
+        {
+          "field": "source1",
+          "role": "vector"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "acc_effect": "write-initialize",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TGEMV",
+      "effect_contract": "TGEMV",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:matrix",
+        "operand:source1:vector",
+        "implicit:ACC:write-initialize"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 73,
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMV.BIAS",
+      "function": 17,
       "name": "TGEMV_BIAS",
-      "canonical_name": "TGEMV_BIAS",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst C/acc tile",
-        "input_0": "A/lhs tile",
-        "input_1_or_attributes": "B/rhs tile + bias tile",
-        "input_2_or_extra_attributes": "optional ExtraTile (input ACC/bias/scale per opcode profile)"
-      },
-      "supported_dtype_format": {
-        "raw": "Same as TGEMV; bias dtype matches ACC/result dtype",
-        "values": [
-          "Same as TGEMV; bias dtype matches ACC/result dtype"
-        ]
-      },
-      "description": "GEMV with bias add (tile world, ins/outs).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TMatmul.hpp; pto/npu/a2a3/TMatmul.hpp; pto/npu/a5/TMatmul.hpp; pto/npu/kirin9030/TMatmul.hpp",
-      "disposition": {
-        "family": "CUBE",
-        "function": 17,
-        "encoding_mnemonic": "BSTART.TGEMV.BIAS"
+      "semantic_handler": "TGEMV_BIAS",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "matrix"
+        },
+        {
+          "field": "source1",
+          "role": "vector"
+        },
+        {
+          "field": "source2",
+          "role": "bias"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        }
+      ],
+      "acc_effect": "write-initialize",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TGEMV_BIAS",
+      "effect_contract": "TGEMV_BIAS",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:matrix",
+        "operand:source1:vector",
+        "operand:source2:bias",
+        "implicit:ACC:write-initialize"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 74,
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMV.ACC",
+      "function": 18,
       "name": "TGEMV_ACC",
-      "canonical_name": "TGEMV_ACC",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst C/acc tile",
-        "input_0": "acc_in tile + A/lhs tile",
-        "input_1_or_attributes": "B/rhs tile",
-        "input_2_or_extra_attributes": "optional ExtraTile (input ACC/bias/scale per opcode profile)"
-      },
-      "supported_dtype_format": {
-        "raw": "Same as TGEMV; input/output ACC dtype follows CUBE profile",
-        "values": [
-          "Same as TGEMV; input/output ACC dtype follows CUBE profile"
-        ]
-      },
-      "description": "PTO matrix-vector multiplication accumulate operation, destination-style (DPS, no bias).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TMatmul.hpp; pto/npu/a2a3/TMatmul.hpp; pto/npu/a5/TMatmul.hpp; pto/npu/kirin9030/TMatmul.hpp",
-      "disposition": {
-        "family": "CUBE",
-        "function": 18,
-        "encoding_mnemonic": "BSTART.TGEMV.ACC"
+      "semantic_handler": "TGEMV_ACC",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "matrix"
+        },
+        {
+          "field": "source1",
+          "role": "vector"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "acc_effect": "read-write",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TGEMV_ACC",
+      "effect_contract": "TGEMV_ACC",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:matrix",
+        "operand:source1:vector",
+        "implicit:ACC:read-write"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 75,
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMVMX",
+      "function": 20,
       "name": "TGEMV_MX",
-      "canonical_name": "TGEMV_MX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst C/acc tile",
-        "input_0": "A/lhs tile",
-        "input_1_or_attributes": "A scale tile + B/rhs tile + B scale tile",
-        "input_2_or_extra_attributes": "optional ExtraTile (input ACC/bias/scale per opcode profile)"
-      },
-      "supported_dtype_format": {
-        "raw": "MX profile-defined: source F16/BF16/F32 or FP8/FP4; scale/bias/ACC follow MX profile",
-        "values": [
-          "MX profile-defined: source F16/BF16/F32 or FP8/FP4; scale/bias/ACC follow MX profile"
-        ]
-      },
-      "description": "Mixed-precision GEMV with scale tiles (tile world, ins/outs).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "MISSING",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: A2A3, Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 3 | impl: pto/cpu/TMatmul.hpp; pto/npu/a5/TMatmul.hpp",
-      "disposition": {
-        "family": "CUBE",
-        "function": 20,
-        "encoding_mnemonic": "BSTART.TGEMVMX"
+      "semantic_handler": "TGEMV_MX",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "matrix"
+        },
+        {
+          "field": "source1",
+          "role": "vector"
+        },
+        {
+          "field": "source2",
+          "role": "row-scale"
+        },
+        {
+          "field": "source3",
+          "role": "column-scale"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        },
+        {
+          "operand": "source3"
+        }
+      ],
+      "acc_effect": "write-initialize",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TGEMV_MX",
+      "effect_contract": "TGEMV_MX",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:matrix",
+        "operand:source1:vector",
+        "operand:source2:row-scale",
+        "operand:source3:column-scale",
+        "implicit:ACC:write-initialize"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
+      }
+    },
+    {
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMVMX.BIAS",
+      "function": 21,
+      "name": "TGEMV_MX_BIAS",
+      "semantic_handler": "TGEMV_MX_BIAS",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "matrix"
+        },
+        {
+          "field": "source1",
+          "role": "vector"
+        },
+        {
+          "field": "source2",
+          "role": "row-scale"
+        },
+        {
+          "field": "source3",
+          "role": "column-scale"
+        },
+        {
+          "field": "source4",
+          "role": "bias"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        },
+        {
+          "operand": "source3"
+        },
+        {
+          "operand": "source4"
+        }
+      ],
+      "acc_effect": "write-initialize",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TGEMV_MX_BIAS",
+      "effect_contract": "TGEMV_MX_BIAS",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:matrix",
+        "operand:source1:vector",
+        "operand:source2:row-scale",
+        "operand:source3:column-scale",
+        "operand:source4:bias",
+        "implicit:ACC:write-initialize"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
+      }
+    },
+    {
+      "disposition": "accepted-direct-operation",
+      "family": "CUBE",
+      "command_mnemonic": "BSTART.TGEMVMX.ACC",
+      "function": 22,
+      "name": "TGEMV_MX_ACC",
+      "semantic_handler": "TGEMV_MX_ACC",
+      "operands": [
+        {
+          "field": "source0",
+          "role": "matrix"
+        },
+        {
+          "field": "source1",
+          "role": "vector"
+        },
+        {
+          "field": "source2",
+          "role": "row-scale"
+        },
+        {
+          "field": "source3",
+          "role": "column-scale"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        },
+        {
+          "operand": "source3"
+        }
+      ],
+      "acc_effect": "read-write",
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TGEMV_MX_ACC",
+      "effect_contract": "TGEMV_MX_ACC",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:source0:matrix",
+        "operand:source1:vector",
+        "operand:source2:row-scale",
+        "operand:source3:column-scale",
+        "implicit:ACC:read-write"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 76,
+      "disposition": "accepted-direct-operation",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.TLOAD",
+      "function": 0,
       "name": "TLOAD",
-      "canonical_name": "TLOAD",
-      "category": "数据搬运与访存",
-      "subcategory": "规则访存",
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "global/partition-view src",
-        "input_1_or_attributes": "base, stride, pad mode/value, init attrs",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S8, U8, S16, U16, S32, U32, S64, U64, F16, BF16, F32; selected FP8/FP4/e8m0 layout profiles",
-        "values": [
-          "S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "S64",
-          "U64",
-          "F16",
-          "BF16",
-          "F32; selected FP8/FP4/e8m0 layout profiles"
-        ]
-      },
-      "description": "PTO data load operation (Dimension Collapse: PartitionView -> TileBuf).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TLoad.hpp; pto/npu/a2a3/TLoad.hpp; pto/npu/a5/TLoad.hpp; pto/npu/kirin9030/TLoad.hpp; pto/npu/kirinX90/TLoad.hpp",
-      "disposition": {
-        "family": "TMA",
-        "function": 0,
-        "encoding_mnemonic": "BSTART.TLOAD"
+      "semantic_handler": "TLOAD",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "address",
+          "role": "base-address"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "address"
+        }
+      ],
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TLOAD",
+      "effect_contract": "TLOAD",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:address:base-address"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 77,
+      "disposition": "accepted-direct-operation",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.TSTORE",
+      "function": 1,
       "name": "TSTORE",
-      "canonical_name": "TSTORE",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "global/partition-view dst",
-        "input_0": "src tile",
-        "input_1_or_attributes": "base, stride, optional preQuant scalar",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S8, U8, S16, U16, S32, U32, S64, U64, F16, BF16, F32; selected FP8/FP4/HiF8 layout profiles",
-        "values": [
-          "S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "S64",
-          "U64",
-          "F16",
-          "BF16",
-          "F32; selected FP8/FP4/HiF8 layout profiles"
-        ]
-      },
-      "description": "PTO data store operation (TileBuf -> PartitionView).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TStore.hpp; pto/npu/a2a3/TStore.hpp; pto/npu/a5/TStore.hpp; pto/npu/kirin9030/TStore.hpp; pto/npu/kirinX90/TStore.hpp",
-      "disposition": {
-        "family": "TMA",
-        "function": 1,
-        "encoding_mnemonic": "BSTART.TSTORE"
+      "semantic_handler": "TSTORE",
+      "operands": [
+        {
+          "field": "address",
+          "role": "base-address"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "address"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TSTORE",
+      "effect_contract": "TSTORE",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:address:base-address",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 78,
+      "disposition": "accepted-direct-operation",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.TPREFETCH",
+      "function": 3,
       "name": "TPREFETCH",
-      "canonical_name": "TPREFETCH",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile/cache target",
-        "input_0": "GM source address",
-        "input_1_or_attributes": "address/layout attrs",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Same element dtype set as TLOAD profile; src/dst element size must match",
-        "values": [
-          "Same element dtype set as TLOAD profile; src/dst element size must match"
-        ]
-      },
-      "description": "Prefetch GM data into a tile-local cache/buffer for a later load/use.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TPrefetch.hpp; pto/npu/a2a3/TPrefetch.hpp; pto/npu/a5/TPrefetch.hpp",
-      "disposition": {
-        "family": "TMA",
-        "function": 3,
-        "encoding_mnemonic": "BSTART.TPREFETCH"
+      "semantic_handler": "TPREFETCH",
+      "operands": [
+        {
+          "field": "address",
+          "role": "base-address"
+        },
+        {
+          "field": "byte_count",
+          "role": "byte-count"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "address"
+        },
+        {
+          "operand": "byte_count"
+        }
+      ],
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TPREFETCH",
+      "effect_contract": "TPREFETCH",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:address:base-address",
+        "operand:byte_count:byte-count"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 79,
+      "disposition": "accepted-direct-operation",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.MGATHER",
+      "function": 4,
       "name": "MGATHER",
-      "canonical_name": "MGATHER",
-      "category": null,
-      "subcategory": "不规则访存",
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "global memory/partition-view src",
-        "input_1_or_attributes": "indexes tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "data: U8, S8, U16, S16, U32, S32, F16, BF16, F32; index: S32, U32",
-        "values": [
-          "data: U8",
-          "S8",
-          "U16",
-          "S16",
-          "U32",
-          "S32",
-          "F16",
-          "BF16",
-          "F32; index: S32",
-          "U32"
-        ]
-      },
-      "description": "Gather-load elements from memory into a tile using per-element indices (tile world, ins/outs).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/MGather.hpp; pto/npu/a2a3/MGather.hpp; pto/npu/a5/MGather.hpp",
-      "disposition": {
-        "family": "TMA",
-        "function": 4,
-        "encoding_mnemonic": "BSTART.MGATHER"
+      "semantic_handler": "MGATHER",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "address",
+          "role": "base-address"
+        },
+        {
+          "field": "source0",
+          "role": "indices"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "address"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_MGATHER",
+      "effect_contract": "MGATHER",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:address:base-address",
+        "operand:source0:indices"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 80,
+      "disposition": "accepted-direct-operation",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.MSCATTER",
+      "function": 5,
       "name": "MSCATTER",
-      "canonical_name": "MSCATTER",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "global memory/partition-view dst",
-        "input_0": "src tile",
-        "input_1_or_attributes": "indexes tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "data: S8, U8, S16, U16, S32, U32, F16, BF16, F32; index: S32, U32",
-        "values": [
-          "data: S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "F16",
-          "BF16",
-          "F32; index: S32",
-          "U32"
-        ]
-      },
-      "description": "Scatter-store elements from a tile into memory using per-element indices (tile world, ins/outs).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/MScatter.hpp; pto/npu/a2a3/MScatter.hpp; pto/npu/a5/MScatter.hpp",
-      "disposition": {
-        "family": "TMA",
-        "function": 5,
-        "encoding_mnemonic": "BSTART.MSCATTER"
+      "semantic_handler": "MSCATTER",
+      "operands": [
+        {
+          "field": "address",
+          "role": "base-address"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "indices"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "address"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_MSCATTER",
+      "effect_contract": "MSCATTER",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:address:base-address",
+        "operand:source0:source",
+        "operand:source1:indices"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
+      }
+    },
+    {
+      "disposition": "accepted-direct-operation",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.MGATHER.MASK",
+      "function": 6,
+      "name": "MGATHER_MASK",
+      "semantic_handler": "MGATHER_MASK",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "address",
+          "role": "base-address"
+        },
+        {
+          "field": "source0",
+          "role": "indices"
+        },
+        {
+          "field": "source1",
+          "role": "mask"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "address"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "runtime": "CurrentBundlePadValue"
+        }
+      ],
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_MGATHER_MASK",
+      "effect_contract": "MGATHER_MASK",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:address:base-address",
+        "operand:source0:indices",
+        "operand:source1:mask"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "PadValueOrByteId",
+          "Layout"
+        ],
+        "pad_union": "pad-value"
+      }
+    },
+    {
+      "disposition": "accepted-direct-operation",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.MSCATTER.MASK",
+      "function": 7,
+      "name": "MSCATTER_MASK",
+      "semantic_handler": "MSCATTER_MASK",
+      "operands": [
+        {
+          "field": "address",
+          "role": "base-address"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "indices"
+        },
+        {
+          "field": "source2",
+          "role": "mask"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "address"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        }
+      ],
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_MSCATTER_MASK",
+      "effect_contract": "MSCATTER_MASK",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:address:base-address",
+        "operand:source0:source",
+        "operand:source1:indices",
+        "operand:source2:mask"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 81,
+      "disposition": "accepted-direct-operation",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.MGATHER.CAS",
+      "function": 8,
+      "name": "MGATHER_CAS",
+      "semantic_handler": "MGATHER_CAS",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "address",
+          "role": "base-address"
+        },
+        {
+          "field": "source0",
+          "role": "indices"
+        },
+        {
+          "field": "source1",
+          "role": "expected"
+        },
+        {
+          "field": "source2",
+          "role": "replacement"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "address"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        }
+      ],
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_MGATHER_CAS",
+      "effect_contract": "MGATHER_CAS",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:address:base-address",
+        "operand:source0:indices",
+        "operand:source1:expected",
+        "operand:source2:replacement"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
+      }
+    },
+    {
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TEXPANDS",
-      "canonical_name": "TEXPANDS",
-      "category": "复杂变换计算",
-      "subcategory": "初始化",
-      "operands": {
-        "outputs": "dst 2D tile",
-        "input_0": "src0 2D tile",
-        "input_1_or_attributes": "column vector src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U8, S8, U16, S16, U32, S32, F16, BF16, F32",
-        "values": [
-          "U8",
-          "S8",
-          "U16",
-          "S16",
-          "U32",
-          "S32",
-          "F16",
-          "BF16",
-          "F32"
-        ]
-      },
-      "description": "Broadcast scalar into dst (tilebuf, DPS)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TExpands.hpp; pto/npu/a2a3/TExpandS.hpp; pto/npu/a5/TExpandS.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x019",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x03B",
+      "semantic_handler": "ExecuteTileFillScalar",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "scalar0",
+          "role": "scalar"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 1,
+      "function": 27,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTileFillScalar",
+      "effect_contract": "ExecuteTileFillScalar",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:scalar0:scalar"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 82,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCI",
-      "canonical_name": "TCI",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst sequence tile",
-        "input_0": "start scalar via B.IOR",
-        "input_1_or_attributes": "descending attr",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, U32, S16, U16",
-        "values": [
-          "S32",
-          "U32",
-          "S16",
-          "U16"
-        ]
-      },
-      "description": "Generate a contiguous ascending or descending integer sequence into dst.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TCI.hpp; pto/npu/a2a3/TCI.hpp; pto/npu/a5/Tci.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x080",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x066",
+      "semantic_handler": "TCI",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "scalar0",
+          "role": "start"
+        },
+        {
+          "field": "flag0",
+          "role": "descending"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "scalar0"
+        },
+        {
+          "operand": "flag0"
+        }
+      ],
+      "mode": 3,
+      "function": 6,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TCI",
+      "effect_contract": "TCI",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:scalar0:start",
+        "operand:flag0:descending"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 83,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TTRI",
-      "canonical_name": "TTRI",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst triangular mask tile",
-        "input_0": "diagonal scalar via B.IOR",
-        "input_1_or_attributes": "upper/lower attr",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, U32, S16, U16, S8, U8, F16, BF16, F32",
-        "values": [
-          "S32",
-          "U32",
-          "S16",
-          "U16",
-          "S8",
-          "U8",
-          "F16",
-          "BF16",
-          "F32"
-        ]
-      },
-      "description": "Generate a lower or upper triangular 0/1 mask tile.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TTRI.hpp; pto/npu/a2a3/TTri.hpp; pto/npu/a5/TTri.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x081",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x067",
+      "semantic_handler": "TTRI",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "flag0",
+          "role": "upper"
+        },
+        {
+          "field": "diagonal",
+          "role": "diagonal"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "flag0"
+        },
+        {
+          "operand": "diagonal"
+        }
+      ],
+      "mode": 3,
+      "function": 7,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TTRI",
+      "effect_contract": "TTRI",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:flag0:upper",
+        "operand:diagonal:diagonal"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 84,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TFILLPAD",
-      "canonical_name": "TFILLPAD",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst padded tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "PadValue attr via B.DATR",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "1/2/4-byte element types; src/dst same size (S/U8, S/U16, F16/BF16, S/U32/F32)",
-        "values": [
-          "1/2/4-byte element types; src/dst same size (S/U8",
-          "S/U16",
-          "F16/BF16",
-          "S/U32/F32)"
-        ]
-      },
-      "description": "Copy valid source elements and fill the destination padding region with PadValue.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TFillPad.hpp; pto/npu/a2a3/TFillPad.hpp; pto/npu/a5/TFillPad.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x082",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x065",
+      "semantic_handler": "TFILLPAD",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "padding"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 3,
+      "function": 5,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TFILLPAD",
+      "effect_contract": "TFILLPAD",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:padding"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "PadValueOrByteId",
+          "Layout"
+        ],
+        "pad_union": "pad-value"
       }
     },
     {
-      "source_row": 85,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCVT",
-      "canonical_name": "TCVT",
-      "category": null,
-      "subcategory": "数据类型转换",
-      "operands": {
-        "outputs": "dst tile (converted dtype)",
-        "input_0": "src tile",
-        "input_1_or_attributes": "round/sat attrs via B.DATR",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "A5 src->dst pairs over S8/U8/S16/U16/S32/U32/S64, F16/BF16/F32, FP8/FP4/e8m0; exact pair depends on RoundMode/SaturationMode",
-        "values": [
-          "A5 src->dst pairs over S8/U8/S16/U16/S32/U32/S64",
-          "F16/BF16/F32",
-          "FP8/FP4/e8m0; exact pair depends on RoundMode/SaturationMode"
-        ]
-      },
-      "description": "Elementwise tile data-format conversion over the destination valid region.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 4 | impl: pto/cpu/TCvt.hpp; pto/npu/a2a3/TCvt.hpp; pto/npu/a5/TCvt.hpp; pto/npu/kirin9030/TCvt.hpp; pto/npu/kirinX90/TCvt.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x00D",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x01B",
+      "semantic_handler": "TCVT",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 0,
+      "function": 27,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TCVT",
+      "effect_contract": "TCVT",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Sat",
+          "Canonicalize",
+          "DataType",
+          "RMode",
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 86,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TQUANT",
-      "canonical_name": "TQUANT",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst quantized tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "scale/exp/max metadata tile(s)",
-        "input_2_or_extra_attributes": "optional offset/scaling/index tile per quant profile"
-      },
-      "supported_dtype_format": {
-        "raw": "INT8: F32 -> S8/U8; MXFP8: F32/BF16/F16 -> FP8(e4m3); MXFP4: BF16/F16 -> FP4(e2m1x2)",
-        "values": [
-          "INT8: F32 -> S8/U8; MXFP8: F32/BF16/F16 -> FP8(e4m3); MXFP4: BF16/F16 -> FP4(e2m1x2)"
-        ]
-      },
-      "description": "Quantize a source tile into a lower-precision destination and optional metadata tiles.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 4 | impl: pto/cpu/TQuant.hpp; pto/npu/a2a3/TQuant.hpp; pto/npu/a5/TQuant.hpp; pto/npu/kirin9030/TQuant.hpp; pto/npu/kirinX90/TQuant.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x083",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x06A",
+      "semantic_handler": "TQUANT",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scale"
+        },
+        {
+          "field": "scalar1",
+          "role": "zero-point"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        },
+        {
+          "operand": "scalar1"
+        }
+      ],
+      "mode": 3,
+      "function": 10,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TQUANT",
+      "effect_contract": "TQUANT",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scale",
+        "operand:scalar1:zero-point"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Sat",
+          "Canonicalize",
+          "DataType",
+          "RMode",
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 87,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TDEQUANT",
-      "canonical_name": "TDEQUANT",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst dequantized tile",
-        "input_0": "src quantized tile",
-        "input_1_or_attributes": "scale tile",
-        "input_2_or_extra_attributes": "offset tile"
-      },
-      "supported_dtype_format": {
-        "raw": "src: S8 or S16; dst/scale/offset: F32",
-        "values": [
-          "src: S8 or S16; dst/scale/offset: F32"
-        ]
-      },
-      "description": "Dequantize a quantized source tile using scale and offset tiles.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TDeQuant.hpp; pto/npu/a2a3/TDequant.hpp; pto/npu/a5/TDeQuant.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x084",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x06B",
+      "semantic_handler": "TDEQUANT",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "scalar0",
+          "role": "scale"
+        },
+        {
+          "field": "scalar1",
+          "role": "zero-point"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "scalar0"
+        },
+        {
+          "operand": "scalar1"
+        }
+      ],
+      "mode": 3,
+      "function": 11,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TDEQUANT",
+      "effect_contract": "TDEQUANT",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:scalar0:scale",
+        "operand:scalar1:zero-point"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Sat",
+          "Canonicalize",
+          "DataType",
+          "RMode",
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 88,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TEXTRACT",
-      "canonical_name": "TEXTRACT",
-      "category": null,
-      "subcategory": "布局变换",
-      "operands": {
-        "outputs": "dst sub-tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "indexRow/indexCol attrs via B.IOR",
-        "input_2_or_extra_attributes": null
-      },
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-          "HiF8",
-          "FP8(e5m2/e4m3/e8m0)",
-          "F16",
-          "BF16",
-          "F32",
-          "FP4(e2m1x2/e1m2x2)"
-        ]
-      },
-      "description": "Extract a sub-tile window from a source tile at indexRow/indexCol.",
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-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 4 | impl: pto/cpu/TExtract.hpp; pto/npu/a2a3/TExtract.hpp; pto/npu/a5/TExtract.hpp; pto/npu/kirin9030/TExtract.hpp; pto/npu/kirinX90/TExtract.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x085",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x062",
+      "semantic_handler": "TEXTRACT",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "natural0",
+          "role": "row-offset"
+        },
+        {
+          "field": "natural1",
+          "role": "column-offset"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "natural0"
+        },
+        {
+          "operand": "natural1"
+        }
+      ],
+      "mode": 3,
+      "function": 2,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TEXTRACT",
+      "effect_contract": "TEXTRACT",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:natural0:row-offset",
+        "operand:natural1:column-offset"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 89,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TINSERT",
-      "canonical_name": "TINSERT",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src sub-tile",
-        "input_1_or_attributes": "indexRow/indexCol attrs via B.IOR",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
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-          "src/dst same dtype: S8",
-          "HiF8",
-          "FP8(e5m2/e4m3/e8m0)",
-          "F16",
-          "BF16",
-          "F32",
-          "S32",
-          "FP4(e2m1x2/e1m2x2)"
-        ]
-      },
-      "description": "Insert a source sub-tile into a destination tile at indexRow/indexCol.",
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-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 4 | impl: pto/cpu/TInsert.hpp; pto/npu/a2a3/TInsert.hpp; pto/npu/a5/TInsert.hpp; pto/npu/kirin9030/TInsert.hpp; pto/npu/kirinX90/TInsert.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x086",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x063",
+      "semantic_handler": "TINSERT",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "natural0",
+          "role": "row-offset"
+        },
+        {
+          "field": "natural1",
+          "role": "column-offset"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "natural0"
+        },
+        {
+          "operand": "natural1"
+        }
+      ],
+      "mode": 3,
+      "function": 3,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TINSERT",
+      "effect_contract": "TINSERT",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:natural0:row-offset",
+        "operand:natural1:column-offset"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 90,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TGATHER",
-      "canonical_name": "TGATHER",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst gathered tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "index/mask tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
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-          "index gather data: S16",
-          "U16",
-          "S32",
-          "U32",
-          "F16",
-          "F32; index: S16",
-          "U16",
-          "S32",
-          "U32; mask gather also S8",
-          "U8",
-          "BF16",
-          "FP8(e4m3/e5m2)",
-          "HiF8"
-        ]
-      },
-      "description": "Gather elements from a source tile according to an index or mask profile.",
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-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp, include/pto/comm/pto_comm_inst.hpp | overloads: 5 | impl: pto/comm/a2a3/TGather.hpp; pto/comm/a5/TGather.hpp; pto/cpu/TGather.hpp; pto/cpu/comm/TGather.hpp; pto/npu/a2a3/TGather.hpp; pto/npu/a5/TGather.hpp; pto/npu/kirin9030/TGather.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x01A",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x06F",
+      "semantic_handler": "TGATHER",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "indices"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 3,
+      "function": 15,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TGATHER",
+      "effect_contract": "TGATHER",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:indices"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 91,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSCATTER",
-      "canonical_name": "TSCATTER",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst scattered tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "index tile",
-        "input_2_or_extra_attributes": null
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-      "supported_dtype_format": {
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-        "values": [
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-          "S16",
-          "S8",
-          "F16",
-          "F32",
-          "U32",
-          "U16",
-          "U8",
-          "BF16; index: S16",
-          "S32",
-          "U16",
-          "U32"
-        ]
-      },
-      "description": "Scatter source elements into destination positions selected by an index tile.",
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-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp, include/pto/comm/pto_comm_inst.hpp | overloads: 4 | impl: pto/comm/a2a3/TScatter.hpp; pto/comm/a5/TScatter.hpp; pto/cpu/TScatter.hpp; pto/cpu/comm/TScatter.hpp; pto/npu/a2a3/TScatter.hpp; pto/npu/a5/TScatter.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x01B",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x070",
+      "semantic_handler": "TSCATTER",
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+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "indices"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 3,
+      "function": 16,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TSCATTER",
+      "effect_contract": "TSCATTER",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:indices"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 92,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TCONCAT",
-      "canonical_name": "TCONCAT",
-      "category": null,
-      "subcategory": null,
-      "operands": {
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-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile; concat axis attrs",
-        "input_2_or_extra_attributes": null
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-      "supported_dtype_format": {
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-        "values": [
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-          "U32",
-          "F32",
-          "S16",
-          "U16",
-          "F16",
-          "BF16",
-          "U8",
-          "S8; index variant idx: S/U8",
-          "S/U16",
-          "S/U32"
-        ]
-      },
-      "description": "Concatenate two tiles, currently documented as column-dimension concat in PTOAS summary.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 3 | impl: pto/cpu/TConcat.hpp; pto/npu/a2a3/TConcat.hpp; pto/npu/a5/TConcat.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x087",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x060",
+      "semantic_handler": "TCONCAT",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        },
+        {
+          "field": "axis",
+          "role": "axis"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "axis"
+        }
+      ],
+      "mode": 3,
+      "function": 0,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TCONCAT",
+      "effect_contract": "TCONCAT",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right",
+        "operand:axis:axis"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 93,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TTRANS",
-      "canonical_name": "TTRANSPOSE",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst transposed tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": "tmp tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U32, S32, F32, U16, S16, F16, BF16, U8, S8",
-        "values": [
-          "U32",
-          "S32",
-          "F32",
-          "U16",
-          "S16",
-          "F16",
-          "BF16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "Transpose or layout-transform a source tile into dst.",
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-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TTrans.hpp; pto/npu/a2a3/TTrans.hpp; pto/npu/a5/TTrans.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x01D",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x06E",
+      "semantic_handler": "TTRANS",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 3,
+      "function": 14,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TTRANS",
+      "effect_contract": "TTRANS",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 94,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TIMG2COL",
-      "canonical_name": "TIMG2COL",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst im2col/Left tile",
-        "input_0": "src ConvTile/feature tile",
-        "input_1_or_attributes": "posM/posK attrs via B.IOR",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S8, U8, S16, U16, S32, U32, F16, BF16, F32",
-        "values": [
-          "S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "F16",
-          "BF16",
-          "F32"
-        ]
-      },
-      "description": "Transform convolution feature-map data into an im2col-style matrix tile.",
-      "targets": {
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-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TImg2col.hpp; pto/npu/a2a3/TImg2col.hpp; pto/npu/a5/TImg2col.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x088",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x064",
+      "semantic_handler": "TIMG2COL",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "positive0",
+          "role": "kernel-rows"
+        },
+        {
+          "field": "positive1",
+          "role": "kernel-columns"
+        },
+        {
+          "field": "positive2",
+          "role": "stride-rows"
+        },
+        {
+          "field": "positive3",
+          "role": "stride-columns"
+        },
+        {
+          "field": "natural0",
+          "role": "pad-rows"
+        },
+        {
+          "field": "natural1",
+          "role": "pad-columns"
+        },
+        {
+          "field": "scalar0",
+          "role": "padding"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "positive0"
+        },
+        {
+          "operand": "positive1"
+        },
+        {
+          "operand": "positive2"
+        },
+        {
+          "operand": "positive3"
+        },
+        {
+          "operand": "natural0"
+        },
+        {
+          "operand": "natural1"
+        },
+        {
+          "operand": "scalar0"
+        }
+      ],
+      "mode": 3,
+      "function": 4,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TIMG2COL",
+      "effect_contract": "TIMG2COL",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:positive0:kernel-rows",
+        "operand:positive1:kernel-columns",
+        "operand:positive2:stride-rows",
+        "operand:positive3:stride-columns",
+        "operand:natural0:pad-rows",
+        "operand:natural1:pad-columns",
+        "operand:scalar0:padding"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 95,
+      "disposition": "accepted-direct-operation",
+      "family": "TMA",
+      "command_mnemonic": "BSTART.TMOV",
+      "function": 2,
       "name": "TMOV",
-      "canonical_name": "TMOV",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst (output; DstTileData)",
-        "input_0": "src (input; SrcTileData)",
-        "input_1_or_attributes": null,
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent; see public signature",
-        "values": [
-          "Template-dependent; see public signature"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TMOV(DstTileData &dst, SrcTileData &src, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY (inserted missing API)",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 4 | impl: pto/cpu/TMov.hpp; pto/npu/a2a3/TMov.hpp; pto/npu/a5/TMov.hpp; pto/npu/kirin9030/TMov.hpp; pto/npu/kirinX90/TMov.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TMA",
-        "function": 2,
-        "encoding_mnemonic": "BSTART.TMOV"
+      "semantic_handler": "TMOV",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TMOV",
+      "effect_contract": "TMOV",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 96,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TGATHERB",
-      "canonical_name": "TGATHERB",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst (output; TileDataDst)",
-        "input_0": "src (input; TileDataSrc)",
-        "input_1_or_attributes": "offset (attr; TileDataOffset)",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent; see public signature",
-        "values": [
-          "Template-dependent; see public signature"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TGATHERB(TileDataDst &dst, TileDataSrc &src, TileDataOffset &offset, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY (inserted missing API)",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TGatherB.hpp; pto/npu/a2a3/TGatherB.hpp; pto/npu/a5/TGatherB.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x089",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x061",
+      "semantic_handler": "TGATHERB",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "byte-offsets"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 3,
+      "function": 1,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TGATHERB",
+      "effect_contract": "TGATHERB",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:byte-offsets"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 97,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TDEINTERLEAVE",
-      "canonical_name": "TDEINTERLEAVE",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst1, dst0 tiles",
-        "input_0": "src1 tile (two-src) / src tile (single-src)",
-        "input_1_or_attributes": "src0 tile (two-src form; None single-src)",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "DType ∈ {int32,uint32,float,int16,uint16,half,bfloat16_t,uint8,int8}; all tiles same DType; row-major; validCols even",
-        "values": [
-          "DType ∈ {int32",
-          "uint32",
-          "float",
-          "int16",
-          "uint16",
-          "half",
-          "bfloat16_t",
-          "uint8",
-          "int8}; all tiles same DType; row-major; validCols even"
-        ]
-      },
-      "description": "De-interleave source tile(s) into dst0 (even positions) / dst1 (odd positions); two-source & single-source forms; inverse of TInterleave.",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "MISSING",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM, A2A3, Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/npu/a5/TDeInterleave.hpp (A5-only)",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x08A",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x078",
+      "semantic_handler": "TDEINTERLEAVE",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination-even"
+        },
+        {
+          "field": "destination1",
+          "role": "destination-odd"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "destination1"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 3,
+      "function": 24,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TDEINTERLEAVE",
+      "effect_contract": "TDEINTERLEAVE",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination-even",
+        "operand:destination1:destination-odd",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 98,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TINTERLEAVE",
-      "canonical_name": "TINTERLEAVE",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst1, dst0 tiles",
-        "input_0": "src1 tile",
-        "input_1_or_attributes": "src0 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "src0/src1/dst0/dst1 same DType; row-major; validCols even",
-        "values": [
-          "src0/src1/dst0/dst1 same DType; row-major; validCols even"
-        ]
-      },
-      "description": "Interleave two source tiles into two destination tiles (alternating even/odd split at midpoint); inverse of TDeInterleave.",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "MISSING",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM, A2A3, Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/npu/a5/TInterleave.hpp (A5-only)",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x08B",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x079",
+      "semantic_handler": "TINTERLEAVE",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 3,
+      "function": 25,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TINTERLEAVE",
+      "effect_contract": "TINTERLEAVE",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 99,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TRESHAPE",
-      "canonical_name": "TRESHAPE",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src tile",
-        "input_1_or_attributes": null,
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "bitwise reinterpret (any dtype): sizeof(InElem)·InNumel == sizeof(OutElem)·OutNumel; Loc must match; no NoneBox<->boxed",
-        "values": [
-          "bitwise reinterpret (any dtype): sizeof(InElem)·InNumel == sizeof(OutElem)·OutNumel; Loc must match; no NoneBox<->boxed"
-        ]
-      },
-      "description": "Reinterpret a tile as another tile type/shape while preserving underlying bytes (bitwise reshape; values unchanged).",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TReshape.hpp; pto/npu/a2a3/TReshape.hpp; pto/npu/a5/TReshape.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x01C",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x077",
+      "semantic_handler": "TRESHAPE",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 3,
+      "function": 23,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TRESHAPE",
+      "effect_contract": "TRESHAPE",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "Layout"
+        ],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 100,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TSORT",
-      "canonical_name": "TSORT",
-      "category": null,
-      "subcategory": "排序",
-      "operands": {
-        "outputs": "dst sorted value/index pairs",
-        "input_0": "src value tile",
-        "input_1_or_attributes": "idx tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "values: F16, F32; idx: U32",
-        "values": [
-          "values: F16",
-          "F32; idx: U32"
-        ]
-      },
-      "description": "Sort each 32-element block and carry indices along with values.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TSort32.hpp; pto/npu/a2a3/TSort32.hpp; pto/npu/a5/TSort32.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0C0",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x06C",
+      "semantic_handler": "TSORT",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "destination1",
+          "role": "original-indices-u32"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "flag0",
+          "role": "descending"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "destination1"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "flag0"
+        }
+      ],
+      "mode": 3,
+      "function": 12,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TSORT",
+      "effect_contract": "TSORT",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:destination1:original-indices-u32",
+        "operand:source0:source",
+        "operand:flag0:descending"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 101,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "TMRGSORT",
-      "canonical_name": "TMRGSORT",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst merged sorted list",
-        "input_0": "src list tile(s)",
-        "input_1_or_attributes": "blockLen or executed-count attrs",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "F16, F32",
-        "values": [
-          "F16",
-          "F32"
-        ]
-      },
-      "description": "Merge sorted list tiles into a destination sorted list.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 4 | impl: pto/cpu/TMrgSort.hpp; pto/npu/a2a3/TMrgSort.hpp; pto/npu/a5/TMrgSort.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0C1",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x06D",
+      "semantic_handler": "TMRGSORT",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        },
+        {
+          "field": "flag0",
+          "role": "descending"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "flag0"
+        }
+      ],
+      "mode": 3,
+      "function": 13,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TMRGSORT",
+      "effect_contract": "TMRGSORT",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right",
+        "operand:flag0:descending"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 102,
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
       "name": "THISTOGRAM",
-      "canonical_name": "THISTOGRAM",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst histogram tile (uint32, R×256, 256 bins/row)",
-        "input_0": "src tile",
-        "input_1_or_attributes": "idx tile (uint8 cascaded filter)",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "src ∈ {uint16,uint32}; dst=uint32 (256 bins/row); idx=uint8; byte=k∈{0,1,2,3} (uint16 only 0/1)",
-        "values": [
-          "src ∈ {uint16",
-          "uint32}; dst=uint32 (256 bins/row); idx=uint8; byte=k∈{0",
-          "1",
-          "2",
-          "3} (uint16 only 0/1)"
-        ]
-      },
-      "description": "Per-byte histogram (256 bins) over a selected byte of each source element, with optional cascaded upper-byte filtering; radix-sort bucket-count primitive. A5/Kirin9030/CPU-sim only.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "MISSING",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "TARGET_GAPS: A2A3",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/THistogram.hpp; pto/npu/a5/THistogram.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0C2",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "selector": "0x068",
+      "semantic_handler": "THISTOGRAM",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        },
+        {
+          "field": "source1",
+          "role": "indices"
+        },
+        {
+          "field": "selected_byte",
+          "role": "selected-byte"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "selected_byte"
+        }
+      ],
+      "mode": 3,
+      "function": 8,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_THISTOGRAM",
+      "effect_contract": "THISTOGRAM",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source",
+        "operand:source1:indices",
+        "operand:selected_byte:selected-byte"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [
+          "PadValueOrByteId",
+          "DataType"
+        ],
+        "pad_union": "histogram-byte-id"
       }
     },
     {
-      "source_row": 103,
-      "name": "TPARTADD",
-      "canonical_name": "TPARTADD",
-      "category": null,
-      "subcategory": "Union计算",
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "U8, S8, U16, S16, U32, S32, F16, F32, BF16",
-        "values": [
-          "U8",
-          "S8",
-          "U16",
-          "S16",
-          "U32",
-          "S32",
-          "F16",
-          "F32",
-          "BF16"
-        ]
-      },
-      "description": "Partial/valid-region elementwise add.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TPartAdd.hpp; pto/cpu/TPartOp.hpp; pto/npu/a2a3/TPartAdd.hpp; pto/npu/a2a3/TPartOp.hpp; pto/npu/a5/TPartAdd.hpp; pto/npu/a5/TPartBinOps.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0C3",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TPUSH",
+      "selector": "0x07A",
+      "semantic_handler": "TPUSH",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 3,
+      "function": 26,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TPUSH",
+      "effect_contract": "TPUSH",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 104,
-      "name": "TPARTMUL",
-      "canonical_name": "TPARTMUL",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S32, U32, F32, S16, U16, F16, BF16, U8, S8",
-        "values": [
-          "S32",
-          "U32",
-          "F32",
-          "S16",
-          "U16",
-          "F16",
-          "BF16",
-          "U8",
-          "S8"
-        ]
-      },
-      "description": "Partial/valid-region elementwise multiply.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TPartMul.hpp; pto/cpu/TPartOp.hpp; pto/npu/a2a3/TPartMul.hpp; pto/npu/a2a3/TPartOp.hpp; pto/npu/a5/TPartBinOps.hpp; pto/npu/a5/TPartMul.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0C4",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TPOP",
+      "selector": "0x07B",
+      "semantic_handler": "TPOP",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        }
+      ],
+      "mode": 3,
+      "function": 27,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TPOP",
+      "effect_contract": "TPOP",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 105,
-      "name": "TPARTMAX",
-      "canonical_name": "TPARTMAX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S8, U8, S16, U16, S32, U32, F16, BF16, F32",
-        "values": [
-          "S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "F16",
-          "BF16",
-          "F32"
-        ]
-      },
-      "description": "Partial/valid-region elementwise maximum.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TPartMax.hpp; pto/cpu/TPartOp.hpp; pto/npu/a2a3/TPartMax.hpp; pto/npu/a2a3/TPartOp.hpp; pto/npu/a5/TPartBinOps.hpp; pto/npu/a5/TPartMax.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0C5",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TALLOC",
+      "selector": "0x07C",
+      "semantic_handler": "TALLOC",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "byte_count",
+          "role": "capacity-bytes"
+        },
+        {
+          "field": "positive0",
+          "role": "rows"
+        },
+        {
+          "field": "positive1",
+          "role": "columns"
+        },
+        {
+          "field": "natural0",
+          "role": "valid-rows"
+        },
+        {
+          "field": "natural1",
+          "role": "valid-columns"
+        },
+        {
+          "field": "scalar0",
+          "role": "data-type-code"
+        },
+        {
+          "field": "flag0",
+          "role": "implementation-defined-layout"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "byte_count"
+        },
+        {
+          "operand": "positive0"
+        },
+        {
+          "operand": "positive1"
+        },
+        {
+          "operand": "natural0"
+        },
+        {
+          "operand": "natural1"
+        },
+        {
+          "operand": "scalar0"
+        },
+        {
+          "operand": "flag0"
+        }
+      ],
+      "mode": 3,
+      "function": 28,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TALLOC",
+      "effect_contract": "TALLOC",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:byte_count:capacity-bytes",
+        "operand:positive0:rows",
+        "operand:positive1:columns",
+        "operand:natural0:valid-rows",
+        "operand:natural1:valid-columns",
+        "operand:scalar0:data-type-code",
+        "operand:flag0:implementation-defined-layout"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 106,
-      "name": "TPARTMIN",
-      "canonical_name": "TPARTMIN",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst tile",
-        "input_0": "src0 tile",
-        "input_1_or_attributes": "src1 tile",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "S8, U8, S16, U16, S32, U32, F16, BF16, F32",
-        "values": [
-          "S8",
-          "U8",
-          "S16",
-          "U16",
-          "S32",
-          "U32",
-          "F16",
-          "BF16",
-          "F32"
-        ]
-      },
-      "description": "Partial/valid-region elementwise minimum.",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TPartMin.hpp; pto/cpu/TPartOp.hpp; pto/npu/a2a3/TPartMin.hpp; pto/npu/a2a3/TPartOp.hpp; pto/npu/a5/TPartBinOps.hpp; pto/npu/a5/TPartMin.hpp",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0C6",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TFREE",
+      "selector": "0x07D",
+      "semantic_handler": "TFREE",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        }
+      ],
+      "arguments": [
+        {
+          "operand": "destination0"
+        }
+      ],
+      "mode": 3,
+      "function": 29,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_TFREE",
+      "effect_contract": "TFREE",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 107,
-      "name": "TPARTARGMAX",
-      "canonical_name": "TPARTARGMAX",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst (output; TileDataDst); dstIdx (output; TileDataDstIdx)",
-        "input_0": "src0 (input; TileDataSrc0)",
-        "input_1_or_attributes": "src1 (input; TileDataSrc1)",
-        "input_2_or_extra_attributes": "src0Idx (input; TileDataSrc0Idx); src1Idx (input; TileDataSrc1Idx)"
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent; see public signature",
-        "values": [
-          "Template-dependent; see public signature"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TPARTARGMAX(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataDstIdx &dstIdx, TileDataSrc0Idx &src0Idx, TileDataSrc1Idx &src1Idx, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY (inserted missing API)",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TPartArgMax.hpp; pto/npu/a2a3/TPartArgOp.hpp; pto/npu/a5/TPartArgBinOps.hpp; pto/npu/a5/TPartArgMax.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0C7",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TPARTADD",
+      "selector": "0x071",
+      "semantic_handler": "ExecuteTilePartial",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TilePartial_ADD"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 3,
+      "function": 17,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTilePartial",
+      "effect_contract": "ExecuteTilePartial",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 108,
-      "name": "TPARTARGMIN",
-      "canonical_name": "TPARTARGMIN",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "dst (output; TileDataDst); dstIdx (output; TileDataDstIdx)",
-        "input_0": "src0 (input; TileDataSrc0)",
-        "input_1_or_attributes": "src1 (input; TileDataSrc1)",
-        "input_2_or_extra_attributes": "src0Idx (input; TileDataSrc0Idx); src1Idx (input; TileDataSrc1Idx)"
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent; see public signature",
-        "values": [
-          "Template-dependent; see public signature"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TPARTARGMIN(TileDataDst &dst, TileDataSrc0 &src0, TileDataSrc1 &src1, TileDataDstIdx &dstIdx, TileDataSrc0Idx &src0Idx, TileDataSrc1Idx &src1Idx, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "SUPPORTED",
-        "kirinx90": "SUPPORTED"
-      },
-      "review_status": "OK_INCLUDE_ONLY (inserted missing API)",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/cpu/TPartArgMin.hpp; pto/npu/a2a3/TPartArgOp.hpp; pto/npu/a5/TPartArgBinOps.hpp; pto/npu/a5/TPartArgMin.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0C8",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TPARTMUL",
+      "selector": "0x072",
+      "semantic_handler": "ExecuteTilePartial",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TilePartial_MUL"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 3,
+      "function": 18,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTilePartial",
+      "effect_contract": "ExecuteTilePartial",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 109,
-      "name": "TPUSH",
-      "canonical_name": "TPUSH",
-      "category": "系统与控制",
-      "subcategory": "核间通信",
-      "operands": {
-        "outputs": "pipe enqueue side effect",
-        "input_0": "pipe (handle; Pipe)",
-        "input_1_or_attributes": "tile/gmTensor (input object)",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent control/interface API",
-        "values": [
-          "Template-dependent control/interface API"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TPUSH(Pipe &pipe, TileProd &tile, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 4 | impl: pto/cpu/TPush.hpp; pto/npu/a2a3/TPush.hpp; pto/npu/a5/TPush.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0E0",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TPARTMAX",
+      "selector": "0x073",
+      "semantic_handler": "ExecuteTilePartial",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TilePartial_MAX"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 3,
+      "function": 19,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTilePartial",
+      "effect_contract": "ExecuteTilePartial",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 110,
-      "name": "TPOP",
-      "canonical_name": "TPOP",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "tile/gmTensor output from pipe",
-        "input_0": "pipe (handle; Pipe)",
-        "input_1_or_attributes": "tile/gmTensor (output object)",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent control/interface API",
-        "values": [
-          "Template-dependent control/interface API"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TPOP(Pipe &pipe, TileCons &tile, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 4 | impl: pto/cpu/TPop.hpp; pto/npu/a2a3/TPop.hpp; pto/npu/a5/TPop.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0E1",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TPARTMIN",
+      "selector": "0x074",
+      "semantic_handler": "ExecuteTilePartial",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TilePartial_MIN"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        }
+      ],
+      "mode": 3,
+      "function": 20,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTilePartial",
+      "effect_contract": "ExecuteTilePartial",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:source0:source-left",
+        "operand:source1:source-right"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 111,
-      "name": "TALLOC",
-      "canonical_name": "TALLOC",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "pipe allocation side effect",
-        "input_0": "pipe (handle; Pipe)",
-        "input_1_or_attributes": "gmTensor (backing storage; GlobalData)",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent control/interface API",
-        "values": [
-          "Template-dependent control/interface API"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TALLOC(Pipe &pipe, GlobalData &gmTensor, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "MISSING",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: CPU-SIM, Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 1 | impl: pto/npu/a2a3/TAlloc.hpp; pto/npu/a5/TAlloc.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0E2",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TPARTARGMAX",
+      "selector": "0x075",
+      "semantic_handler": "ExecuteTilePartialArg",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "destination1",
+          "role": "destination-indices"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        },
+        {
+          "field": "source2",
+          "role": "left-indices"
+        },
+        {
+          "field": "source3",
+          "role": "right-indices"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "TRUE"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "destination1"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        },
+        {
+          "operand": "source3"
+        }
+      ],
+      "mode": 3,
+      "function": 21,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTilePartialArg",
+      "effect_contract": "ExecuteTilePartialArg",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:destination1:destination-indices",
+        "operand:source0:source-left",
+        "operand:source1:source-right",
+        "operand:source2:left-indices",
+        "operand:source3:right-indices"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     },
     {
-      "source_row": 112,
-      "name": "TFREE",
-      "canonical_name": "TFREE",
-      "category": null,
-      "subcategory": null,
-      "operands": {
-        "outputs": "pipe free side effect",
-        "input_0": "pipe (handle; Pipe)",
-        "input_1_or_attributes": "gmTensor optional backing storage",
-        "input_2_or_extra_attributes": null
-      },
-      "supported_dtype_format": {
-        "raw": "Template-dependent control/interface API",
-        "values": [
-          "Template-dependent control/interface API"
-        ]
-      },
-      "description": "Public PTO ISA API wrapper from include/pto: PTO_INST RecordEvent TFREE(Pipe &pipe, WaitEvents &...events)",
-      "targets": {
-        "cpu_sim": "SUPPORTED",
-        "a2a3": "SUPPORTED",
-        "a5": "SUPPORTED",
-        "kirin9030": "MISSING",
-        "kirinx90": "MISSING"
-      },
-      "review_status": "TARGET_GAPS: Kirin9030, KirinX90",
-      "evidence": "public: include/pto/common/pto_instr.hpp | overloads: 2 | impl: pto/cpu/TPop.hpp; pto/npu/a2a3/TFree.hpp; pto/npu/a5/TFree.hpp | inserted from include/pto public API scan",
-      "disposition": {
-        "family": "TEPL",
-        "selector": "0x0E3",
-        "encoding_mnemonic": "BSTART.TEPL"
+      "disposition": "accepted-direct-operation",
+      "family": "TEPL",
+      "command_mnemonic": "BSTART.TEPL",
+      "name": "TPARTARGMIN",
+      "selector": "0x076",
+      "semantic_handler": "ExecuteTilePartialArg",
+      "operands": [
+        {
+          "field": "destination0",
+          "role": "destination"
+        },
+        {
+          "field": "destination1",
+          "role": "destination-indices"
+        },
+        {
+          "field": "source0",
+          "role": "source-left"
+        },
+        {
+          "field": "source1",
+          "role": "source-right"
+        },
+        {
+          "field": "source2",
+          "role": "left-indices"
+        },
+        {
+          "field": "source3",
+          "role": "right-indices"
+        }
+      ],
+      "arguments": [
+        {
+          "constant": "FALSE"
+        },
+        {
+          "operand": "destination0"
+        },
+        {
+          "operand": "destination1"
+        },
+        {
+          "operand": "source0"
+        },
+        {
+          "operand": "source1"
+        },
+        {
+          "operand": "source2"
+        },
+        {
+          "operand": "source3"
+        }
+      ],
+      "mode": 3,
+      "function": 22,
+      "contract_status": "reviewed-complete",
+      "legality_handler": "TileOperandsLegal_ExecuteTilePartialArg",
+      "effect_contract": "ExecuteTilePartialArg",
+      "fault_contract": "ExecuteTileInstruction",
+      "restart_contract": "CompleteBundleAtWithAcceptedApplicabilityRules",
+      "state_effects": [
+        "operand:destination0:destination",
+        "operand:destination1:destination-indices",
+        "operand:source0:source-left",
+        "operand:source1:source-right",
+        "operand:source2:left-indices",
+        "operand:source3:right-indices"
+      ],
+      "datr_contract": {
+        "allowed_nonzero_fields": [],
+        "pad_union": "must-zero"
       }
     }
   ]
diff --git a/isa/v0.57/state/rendering_profile.json b/isa/v0.57/state/rendering_profile.json
index ea66b953..be665b71 100644
--- a/isa/v0.57/state/rendering_profile.json
+++ b/isa/v0.57/state/rendering_profile.json
@@ -26,7 +26,7 @@
     "packed_output": "RGBA8_UNORM may be packed as one uint32_t per element"
   },
   "state_placement": {
-    "descriptor_state": "small or rarely-changing values use B.ARG and B.IOR",
+    "descriptor_state": "small or rarely-changing values use B.DATR, B.DIM, and B.IOR",
     "state_tiles": "large or hot rendering state uses dedicated StateTiles in the tile register file"
   },
   "tau_policy": {
diff --git a/isa/v0.57/state/system_registers.json b/isa/v0.57/state/system_registers.json
index 1c2af2d2..2e28f3fd 100644
--- a/isa/v0.57/state/system_registers.json
+++ b/isa/v0.57/state/system_registers.json
@@ -352,14 +352,14 @@
           "width_bits": 64
         },
         {
-          "access": "RW",
+          "access": "RO",
           "description": "Interrupt pending bitmap.",
           "idx": "0xF08",
           "name": "IPENDING_ACRn",
           "width_bits": 64
         },
         {
-          "access": "RW",
+          "access": "RO",
           "description": "Top pending interrupt ID.",
           "idx": "0xF09",
           "name": "TOPEI_ACRn",
diff --git a/isa/v0.57/uop_classification_v0.57/CMD/BLOCK_ARGUMENT.json b/isa/v0.57/uop_classification_v0.57/CMD/BLOCK_ARGUMENT.json
index 060deea9..5de5ff19 100644
--- a/isa/v0.57/uop_classification_v0.57/CMD/BLOCK_ARGUMENT.json
+++ b/isa/v0.57/uop_classification_v0.57/CMD/BLOCK_ARGUMENT.json
@@ -1,20 +1,7 @@
 {
   "big_kind": "CMD",
-  "count": 2,
+  "count": 1,
   "instructions": [
-    {
-      "class": {
-        "cmd_kind": "BLOCK_ARGUMENT",
-        "note": "User confirmed A",
-        "source": "group_rule",
-        "uop_kind": "CMD"
-      },
-      "group": "Block Argument",
-      "length_bits": [
-        32
-      ],
-      "mnemonic": "B.ARG"
-    },
     {
       "class": {
         "cmd_kind": "BLOCK_ARGUMENT",
diff --git a/isa/v0.57/uop_classification_v0.57/CMD/BLOCK_SPLIT.json b/isa/v0.57/uop_classification_v0.57/CMD/BLOCK_SPLIT.json
index 644db2cc..9a8de630 100644
--- a/isa/v0.57/uop_classification_v0.57/CMD/BLOCK_SPLIT.json
+++ b/isa/v0.57/uop_classification_v0.57/CMD/BLOCK_SPLIT.json
@@ -1,6 +1,6 @@
 {
   "big_kind": "CMD",
-  "count": 45,
+  "count": 43,
   "instructions": [
     {
       "class": {
@@ -28,32 +28,6 @@
       ],
       "mnemonic": "BSTART.ACCCVT"
     },
-    {
-      "class": {
-        "cmd_kind": "BLOCK_SPLIT",
-        "note": "User corrected to A",
-        "source": "group_rule",
-        "uop_kind": "CMD"
-      },
-      "group": "Block Split",
-      "length_bits": [
-        32
-      ],
-      "mnemonic": "BSTART.CUBE"
-    },
-    {
-      "class": {
-        "cmd_kind": "BLOCK_SPLIT",
-        "note": "User corrected to A",
-        "source": "group_rule",
-        "uop_kind": "CMD"
-      },
-      "group": "Block Split",
-      "length_bits": [
-        32
-      ],
-      "mnemonic": "BSTART.FIXP"
-    },
     {
       "class": {
         "cmd_kind": "BLOCK_SPLIT",
diff --git a/kernel/linux b/kernel/linux
index a65ec362..def640ea 160000
--- a/kernel/linux
+++ b/kernel/linux
@@ -1 +1 @@
-Subproject commit a65ec3620d275a2bb53bd6087cd6b737c53da7a0
+Subproject commit def640ea4169a32c759e00e4c6af35043fe880df
diff --git a/lib/glibc b/lib/glibc
index 6dd1cee3..d5ca74ac 160000
--- a/lib/glibc
+++ b/lib/glibc
@@ -1 +1 @@
-Subproject commit 6dd1cee38fef1e9cf2caf71554cb68975e7e9f90
+Subproject commit d5ca74ac57c19d2f89e66991da5e6f043f64e684
diff --git a/lib/musl b/lib/musl
index a16cd1b5..7098648f 160000
--- a/lib/musl
+++ b/lib/musl
@@ -1 +1 @@
-Subproject commit a16cd1b589382141452dbf5408448a51e9b90273
+Subproject commit 7098648ff8330ae1e0bae82fc91f017287d2054b
diff --git a/mkdocs.zh.yml b/mkdocs.zh.yml
index 60f3d991..7dd75102 100644
--- a/mkdocs.zh.yml
+++ b/mkdocs.zh.yml
@@ -1105,7 +1105,6 @@ nav:
             - TMUL: isa/header/tileblock/TMUL.md
             - TDIV: isa/header/tileblock/TDIV.md
             - TREM: isa/header/tileblock/TREM.md
-            - TFMOD: isa/header/tileblock/TFMOD.md
             - TAND: isa/header/tileblock/TAND.md
             - TOR: isa/header/tileblock/TOR.md
             - TXOR: isa/header/tileblock/TXOR.md
@@ -1124,8 +1123,6 @@ nav:
             - TSQRT: isa/header/tileblock/TSQRT.md
             - TRSQRT: isa/header/tileblock/TRSQRT.md
             - TRELU: isa/header/tileblock/TRELU.md
-            - TADDC: isa/header/tileblock/TADDC.md
-            - TSUBC: isa/header/tileblock/TSUBC.md
             - TSEL: isa/header/tileblock/TSEL.md
             - TCVT: isa/header/tileblock/TCVT.md
         - 逐元素和标量操作:
@@ -1134,7 +1131,6 @@ nav:
             - TMULS: isa/header/tileblock/TMULS.md
             - TDIVS: isa/header/tileblock/TDIVS.md
             - TREMS: isa/header/tileblock/TREMS.md
-            - TFMODS: isa/header/tileblock/TFMODS.md
             - TANDS: isa/header/tileblock/TANDS.md
             - TORS: isa/header/tileblock/TORS.md
             - TXORS: isa/header/tileblock/TXORS.md
@@ -1143,9 +1139,6 @@ nav:
             - TMAXS: isa/header/tileblock/TMAXS.md
             - TMINS: isa/header/tileblock/TMINS.md
             - TCMPS: isa/header/tileblock/TCMPS.md
-            - TLRELU: isa/header/tileblock/TLRELU.md
-            - TADDSC: isa/header/tileblock/TADDSC.md
-            - TSUBSC: isa/header/tileblock/TSUBSC.md
             - TSELS: isa/header/tileblock/TSELS.md
             - TEXPANDS: isa/header/tileblock/TEXPANDS.md
         - 按轴逐元素操作:
diff --git a/rtl/LinxCore b/rtl/LinxCore
index 294542ff..2f2ccacf 160000
--- a/rtl/LinxCore
+++ b/rtl/LinxCore
@@ -1 +1 @@
-Subproject commit 294542ffb5c9a65915af34fa38abc32e2eec134f
+Subproject commit 2f2ccacfc0e2dca5b3c3933820c23e2ddd257791
diff --git a/skills/linx-skills b/skills/linx-skills
index 6b0b6fe9..558a56ff 160000
--- a/skills/linx-skills
+++ b/skills/linx-skills
@@ -1 +1 @@
-Subproject commit 6b0b6fe9fd6f3ef219ce4090928d6c0388ddbd0f
+Subproject commit 558a56ff4295a82c09ae0752404beead241a2f14
diff --git a/tools/LinxCoreModel b/tools/LinxCoreModel
index 31555f49..ba366564 160000
--- a/tools/LinxCoreModel
+++ b/tools/LinxCoreModel
@@ -1 +1 @@
-Subproject commit 31555f49dbb020c8eb9f26f7df98310a7415b69d
+Subproject commit ba366564783aee18f0a2162d9a20f74bc07effde
diff --git a/tools/bringup/check_sail_model.py b/tools/bringup/check_sail_model.py
index ae3df0f3..fff8f6c7 100644
--- a/tools/bringup/check_sail_model.py
+++ b/tools/bringup/check_sail_model.py
@@ -209,8 +209,15 @@ def main(argv: list[str]) -> int:
     instructions = spec.get("instructions")
     if not isinstance(instructions, list):
         raise SystemExit(f"error: malformed spec file: {args.spec}")
-    if str(status.get("schema_version", "")).strip() != "linx-sail-status-v0.57.0":
-        raise SystemExit("error: semantics_status.schema_version must be 'linx-sail-status-v0.57.0'")
+    release = str(spec.get("version") or "").strip()
+    if not re.fullmatch(r"[0-9]+(?:\.[0-9]+)+", release):
+        raise SystemExit(f"error: malformed ISA release in {args.spec}")
+    expected_status_schema = f"linx-sail-status-v{release}"
+    if str(status.get("schema_version", "")).strip() != expected_status_schema:
+        raise SystemExit(
+            "error: semantics_status.schema_version must be "
+            f"{expected_status_schema!r}"
+        )
     form_statuses = status.get("forms")
     if not isinstance(form_statuses, dict):
         raise SystemExit("error: semantics_status.forms must be an object")
diff --git a/tools/bringup/report_qemu_isa_coverage.py b/tools/bringup/report_qemu_isa_coverage.py
index e6a629ec..352e00a4 100644
--- a/tools/bringup/report_qemu_isa_coverage.py
+++ b/tools/bringup/report_qemu_isa_coverage.py
@@ -161,7 +161,6 @@ def _validate_executable_evidence(
     "bstart_fp_icall": "BSTART.FP",
     "bstart_fp_ret": "BSTART.FP",
     "bstart_sys": "BSTART.SYS",
-    "bstart_fixp": "BSTART.FIXP",
     "hl_bstart_fp_fall": "HL.BSTART.FP",
     "hl_bstart_fp_direct": "HL.BSTART.FP",
     "hl_bstart_fp_cond": "HL.BSTART.FP",
@@ -590,10 +589,7 @@ def _canonicalize_scalar_mnemonic(stem: str) -> str | list[str] | None:
             "BSTART.SYS",
             "HL.BSTART.FP",
             "HL.BSTART.SYS",
-            "BSTART.FIXP",
-            "BSTART.CUBE",
             "BSTART.TEPL",
-            "BSTART.TMA",
             "BSTART.VPAR",
             "BSTART.VSEQ",
             "BSTART.MPAR",
@@ -612,10 +608,7 @@ def _canonicalize_scalar_mnemonic(stem: str) -> str | list[str] | None:
             "BSTART.SYS",
             "HL.BSTART.FP",
             "HL.BSTART.SYS",
-            "BSTART.FIXP",
-            "BSTART.CUBE",
             "BSTART.TEPL",
-            "BSTART.TMA",
             "BSTART.VPAR",
             "BSTART.VSEQ",
             "BSTART.MPAR",
@@ -634,10 +627,7 @@ def _canonicalize_scalar_mnemonic(stem: str) -> str | list[str] | None:
             "BSTART.SYS",
             "HL.BSTART.FP",
             "HL.BSTART.SYS",
-            "BSTART.FIXP",
-            "BSTART.CUBE",
             "BSTART.TEPL",
-            "BSTART.TMA",
             "BSTART.VPAR",
             "BSTART.VSEQ",
             "BSTART.MPAR",
@@ -739,8 +729,6 @@ def _canonicalize_scalar_mnemonic(stem: str) -> str | list[str] | None:
     }
     if stem in header_map:
         return header_map[stem]
-    if stem.startswith("b_arg_"):
-        return "B.ARG"
     if stem.startswith(("bdim_", "b_dim_")):
         return "B.DIM"
 
diff --git a/tools/bringup/report_qemu_translation_coverage.py b/tools/bringup/report_qemu_translation_coverage.py
index 7b809447..67d84198 100644
--- a/tools/bringup/report_qemu_translation_coverage.py
+++ b/tools/bringup/report_qemu_translation_coverage.py
@@ -76,8 +76,6 @@ def canonicalize_mnemonic(mnemonic: str) -> str:
 
 def derived_selector_mnemonics(mnemonic: str, operands: list[str]) -> set[str]:
     selector = canonicalize_mnemonic(mnemonic)
-    if selector == "B.DATR":
-        return {"B.ARG"}
     if not operands:
         return set()
 
@@ -85,14 +83,6 @@ def derived_selector_mnemonics(mnemonic: str, operands: list[str]) -> set[str]:
     aliases = {
         ("BSTART.STD", "CALL"): "BSTART CALL",
         ("HL.BSTART.STD", "CALL"): "HL.BSTART CALL",
-        ("BSTART.CUBE", "ACCCVT"): "BSTART.ACCCVT",
-        ("BSTART.CUBE", "TMATMUL"): "BSTART.TMATMUL",
-        ("BSTART.CUBE", "TMATMUL.ACC"): "BSTART.TMATMUL.ACC",
-        ("BSTART.TEPL", "TLOAD"): "BSTART.TLOAD",
-        ("BSTART.TEPL", "TSTORE"): "BSTART.TSTORE",
-        ("BSTART.TEPL", "TMOV"): "BSTART.TMOV",
-        ("BSTART.TEPL", "TMATMUL"): "BSTART.TMATMUL",
-        ("BSTART.TEPL", "TMATMUL.ACC"): "BSTART.TMATMUL.ACC",
         ("BSTART.TEPL", "ACCCVT"): "BSTART.ACCCVT",
         ("BSTART.TMA", "TLOAD"): "BSTART.TLOAD",
         ("BSTART.TMA", "TSTORE"): "BSTART.TSTORE",
diff --git a/tools/bringup/test_check_sail_model.py b/tools/bringup/test_check_sail_model.py
index 6e50c34c..054344fe 100644
--- a/tools/bringup/test_check_sail_model.py
+++ b/tools/bringup/test_check_sail_model.py
@@ -68,9 +68,12 @@ def test_parser_and_backend_failures_keep_their_classification(self) -> None:
             spec = root / "spec.json"
             status = root / "status.json"
             toolchain = root / "toolchain.json"
-            spec.write_text('{"instructions": [{"id": "addi", "mnemonic": "ADDI"}]}', encoding="utf-8")
+            spec.write_text(
+                '{"version": "0.57.1", "instructions": [{"id": "addi", "mnemonic": "ADDI"}]}',
+                encoding="utf-8",
+            )
             status.write_text(
-                '{"schema_version": "linx-sail-status-v0.57.0", '
+                '{"schema_version": "linx-sail-status-v0.57.1", '
                 '"forms": {"addi": {"mnemonic": "ADDI", "status": "architecturally-complete"}}}',
                 encoding="utf-8",
             )
diff --git a/tools/ci/check_linx_callret_crossstack.sh b/tools/ci/check_linx_callret_crossstack.sh
index 2b7b0588..4659e78c 100755
--- a/tools/ci/check_linx_callret_crossstack.sh
+++ b/tools/ci/check_linx_callret_crossstack.sh
@@ -5,11 +5,24 @@ SCRIPT_DIR="$(cd "$(dirname "${BASH_SOURCE[0]}")" && pwd)"
 REPO_ROOT="$(cd "$SCRIPT_DIR/../.." && pwd)"
 
 LINUX_ROOT="${1:-${LINUX_ROOT:-$REPO_ROOT/kernel/linux}}"
+LINUX_BUILD_ROOT="${LINUX_BUILD_DIR:-${LINUX_VMLINUX_OUT_DIR:-}}"
+
+BUILD_ROOTS=()
+if [[ -n "$LINUX_BUILD_ROOT" ]]; then
+  BUILD_ROOTS+=("$LINUX_BUILD_ROOT")
+fi
+BUILD_ROOTS+=(
+  "$LINUX_ROOT/build-linx-fixed"
+  "$LINUX_ROOT/build-linx"
+)
+
 VMLINUX=""
-for cand in \
-  "$LINUX_ROOT/build-linx-fixed/vmlinux" \
-  "$LINUX_ROOT/build-linx/vmlinux" \
-  "$LINUX_ROOT/vmlinux"; do
+VMLINUX_CANDIDATES=()
+for build_root in "${BUILD_ROOTS[@]}"; do
+  VMLINUX_CANDIDATES+=("$build_root/vmlinux")
+done
+VMLINUX_CANDIDATES+=("$LINUX_ROOT/vmlinux")
+for cand in "${VMLINUX_CANDIDATES[@]}"; do
   if [[ -f "$cand" ]]; then
     VMLINUX="$cand"
     break
@@ -26,17 +39,23 @@ pick_first_exists() {
   return 1
 }
 
-SWITCH_O="$(pick_first_exists \
-  "$LINUX_ROOT/build-linx-fixed/arch/linx/kernel/switch_to.o" \
-  "$LINUX_ROOT/build-linx/arch/linx/kernel/switch_to.o" \
-  "$LINUX_ROOT/arch/linx/kernel/switch_to.o" \
-  "$LINUX_ROOT/build-linx-fixed/arch/linx/kernel/entry.o" \
-  "$LINUX_ROOT/build-linx/arch/linx/kernel/entry.o" \
-  "$LINUX_ROOT/arch/linx/kernel/entry.o" || true)"
-ENTRY_O="$(pick_first_exists \
-  "$LINUX_ROOT/build-linx-fixed/arch/linx/kernel/entry.o" \
-  "$LINUX_ROOT/build-linx/arch/linx/kernel/entry.o" \
-  "$LINUX_ROOT/arch/linx/kernel/entry.o" || true)"
+SWITCH_CANDIDATES=()
+ENTRY_CANDIDATES=()
+for build_root in "${BUILD_ROOTS[@]}"; do
+  SWITCH_CANDIDATES+=(
+    "$build_root/arch/linx/kernel/switch_to.o"
+    "$build_root/arch/linx/kernel/entry.o"
+  )
+  ENTRY_CANDIDATES+=("$build_root/arch/linx/kernel/entry.o")
+done
+SWITCH_CANDIDATES+=(
+  "$LINUX_ROOT/arch/linx/kernel/switch_to.o"
+  "$LINUX_ROOT/arch/linx/kernel/entry.o"
+)
+ENTRY_CANDIDATES+=("$LINUX_ROOT/arch/linx/kernel/entry.o")
+
+SWITCH_O="$(pick_first_exists "${SWITCH_CANDIDATES[@]}" || true)"
+ENTRY_O="$(pick_first_exists "${ENTRY_CANDIDATES[@]}" || true)"
 
 if [[ -n "${LLVM_OBJDUMP:-}" ]]; then
   OBJDUMP="$LLVM_OBJDUMP"
@@ -81,14 +100,14 @@ trap 'rm -rf "$tmpdir"' EXIT
 
 audit_objs=("$ENTRY_O")
 SELECTED_BUILD_ROOT=""
-case "$ENTRY_O" in
-  "$LINUX_ROOT/build-linx-fixed/"*)
-    SELECTED_BUILD_ROOT="$LINUX_ROOT/build-linx-fixed"
-    ;;
-  "$LINUX_ROOT/build-linx/"*)
-    SELECTED_BUILD_ROOT="$LINUX_ROOT/build-linx"
-    ;;
-esac
+for build_root in "${BUILD_ROOTS[@]}"; do
+  case "$ENTRY_O" in
+    "$build_root/"*)
+      SELECTED_BUILD_ROOT="$build_root"
+      break
+      ;;
+  esac
+done
 if [[ -n "$SELECTED_BUILD_ROOT" && -f "$SELECTED_BUILD_ROOT/kernel/printk/printk.o" ]]; then
   audit_objs+=("$SELECTED_BUILD_ROOT/kernel/printk/printk.o")
 fi
diff --git a/tools/isa/build_golden.py b/tools/isa/build_golden.py
index 65b2733a..8c87a927 100644
--- a/tools/isa/build_golden.py
+++ b/tools/isa/build_golden.py
@@ -504,6 +504,68 @@ def _assign_stable_ids(instructions: List[Dict[str, Any]]) -> None:
         inst["id"] = f"{_slug(str(inst.get('mnemonic','inst')))}_{inst.get('length_bits',0)}_{uid}"
 
 
+def _attach_pto_source_form_ids(in_dir: Path, instructions: List[Dict[str, Any]]) -> None:
+    """Attach the sole-source PTO form identity without replacing Linx stable IDs."""
+    source_path = in_dir / "state" / "pto_command_forms.json"
+    if not source_path.is_file():
+        return
+    source = _read_json(source_path)
+    if source.get("form_count") != 99:
+        raise ValueError(f"{source_path}: expected exactly 99 PTO command forms")
+
+    def source_key(form: Dict[str, Any]) -> Tuple[Any, ...]:
+        encoding = tuple(
+            (int(part["mask"], 0), int(part["match"], 0), int(part["width_bits"]))
+            for part in form.get("encoding", [])
+        )
+        return (form.get("mnemonic"), form.get("asm"), int(form.get("length_bits", 0)), encoding)
+
+    def instruction_key(inst: Dict[str, Any]) -> Tuple[Any, ...]:
+        encoding = tuple(
+            (int(part["mask"], 0), int(part["match"], 0), int(part["width_bits"]))
+            for part in inst.get("encoding", {}).get("parts", [])
+        )
+        return (inst.get("mnemonic"), inst.get("asm"), int(inst.get("length_bits", 0)), encoding)
+
+    by_key: Dict[Tuple[Any, ...], List[Dict[str, Any]]] = {}
+    for inst in instructions:
+        by_key.setdefault(instruction_key(inst), []).append(inst)
+    attached = set()
+    for form in source.get("forms", []):
+        key = source_key(form)
+        matches = by_key.get(key, [])
+        if len(matches) != 1:
+            raise ValueError(
+                f"{source_path}: PTO form {form.get('form_id')} has {len(matches)} exact Linx encoding matches"
+            )
+        form_id = str(form["form_id"])
+        matched = matches[0]
+        matched["pto_source_form_id"] = form_id
+        for part in matched.get("encoding", {}).get("parts", []):
+            part.pop("constraints", None)
+        widths = {str(field["name"]): int(field["width"]) for field in form.get("fields", [])}
+        compiled_constraints = []
+        for constraint in form.get("constraints", []):
+            field = str(constraint["field"])
+            if constraint["operator"] == "one-of":
+                allowed = {int(value) for value in constraint["values"]}
+                rejected = sorted(set(range(1 << widths[field])) - allowed)
+            elif constraint["operator"] == "not-equal":
+                rejected = [int(constraint["value"])]
+            else:
+                raise ValueError(
+                    f"{source_path}: unsupported constraint operator {constraint['operator']!r}"
+                )
+            compiled_constraints.extend(
+                {"field": field, "op": "!=", "value": str(value)} for value in rejected
+            )
+        if compiled_constraints:
+            matched["encoding"]["parts"][0]["constraints"] = compiled_constraints
+        attached.add(form_id)
+    if len(attached) != 99:
+        raise ValueError(f"{source_path}: PTO source form identities are not unique")
+
+
 @dataclass(frozen=True)
 class _OpcodeLine:
     mnemonic: str
@@ -801,6 +863,7 @@ def build(in_dir: Path) -> Dict[str, Any]:
 
     _augment_with_encoding(instructions)
     _assign_stable_ids(instructions)
+    _attach_pto_source_form_ids(in_dir, instructions)
 
     # Attach uop classification + compression kind (documentation + downstream decoders).
     _augment_with_uop_classification(in_dir, instructions)
diff --git a/tools/isa/check_canonical_v057.py b/tools/isa/check_canonical_v057.py
index d447fe1b..e9779048 100644
--- a/tools/isa/check_canonical_v057.py
+++ b/tools/isa/check_canonical_v057.py
@@ -91,8 +91,8 @@ def validate(root: Path) -> list[str]:
     if not spec_path.is_file():
         return [f"missing v0.57 compiled spec: {spec_path}"]
     spec = _load_spec(root)
-    if spec.get("version") != "0.57.0":
-        errors.append(f"{spec_path}: expected version 0.57.0, got {spec.get('version')!r}")
+    if spec.get("version") != "0.57.1":
+        errors.append(f"{spec_path}: expected version 0.57.1, got {spec.get('version')!r}")
 
     mnemonics = {str(inst.get("mnemonic") or "") for inst in spec.get("instructions", [])}
     required = {
@@ -132,10 +132,10 @@ def validate(root: Path) -> list[str]:
         errors.append(f"missing v0.57 release manifest: {release_manifest}")
     else:
         manifest = json.loads(release_manifest.read_text(encoding="utf-8"))
-        if manifest.get("profile") != "v0.57" or manifest.get("version") != "0.57.0":
-            errors.append(f"{release_manifest}: expected standalone v0.57.0 release identity")
-        if not manifest.get("policy", {}).get("standalone_release"):
-            errors.append(f"{release_manifest}: standalone_release policy is required")
+        if manifest.get("profile") != "v0.57" or manifest.get("version") != "0.57.1":
+            errors.append(f"{release_manifest}: expected standalone v0.57.1 release identity")
+        if not manifest.get("policy", {}).get("pto_spec_is_sole_source"):
+            errors.append(f"{release_manifest}: pto_spec_is_sole_source policy is required")
 
     retired_profile = root / "isa/v0.56"
     if retired_profile.exists():
diff --git a/tools/isa/check_pto_v057_manifest.py b/tools/isa/check_pto_v057_manifest.py
index 6ef142ac..f4193fa9 100644
--- a/tools/isa/check_pto_v057_manifest.py
+++ b/tools/isa/check_pto_v057_manifest.py
@@ -1,210 +1,237 @@
 #!/usr/bin/env python3
-"""Validate the normalized PTO 0.57 inventory and its Linx encoding map."""
+"""Validate the locked PTO ISA 0.57.1 projections and compiled command ABI."""
 
 from __future__ import annotations
 
 import argparse
 import json
+import re
 import sys
+from collections import Counter
 from pathlib import Path
 from typing import Any
 
 
 ROOT = Path(__file__).resolve().parents[2]
-SOURCE_SHA256 = "0387b39f108599f2469c2e2374a46ea4b832a96fee7bf7aa5d7cc575fdc7864a"
-EXPORT_SHA256 = "4c75f961e8f2f63e35bce51dec21c97f75c50e2189a0f8c83f95577403984d21"
-EXPECTED_NAMES = """
-TADD TSUB TMUL TMAX TMIN TAND TOR TXOR TSHL TSHR TCMP TSEL TABS TNOT TNEG TRELU
-TDIV TREM TSQRT TLOG TRECIP TEXP TRSQRT TADDS TAXPY TSUBS TMULS TDIVS TMINS TMAXS
-TREMS TANDS TORS TXORS TCMPS TSELS TSHLS TSHRS TROWSUM TROWPROD TROWMAX TROWMIN
-TROWARGMAX TROWARGMIN TCOLSUM TCOLPROD TCOLMAX TCOLMIN TCOLARGMAX TCOLARGMIN
-TROWEXPAND TROWEXPANDADD TROWEXPANDSUB TROWEXPANDMUL TROWEXPANDDIV TROWEXPANDMAX
-TROWEXPANDMIN TROWEXPANDEXPDIF TCOLEXPAND TCOLEXPANDADD TCOLEXPANDSUB TCOLEXPANDMUL
-TCOLEXPANDDIV TCOLEXPANDMAX TCOLEXPANDMIN TCOLEXPANDEXPDIF TMATMUL TMATMUL_BIAS
-TMATMUL_ACC TMATMUL_MX TGEMV TGEMV_BIAS TGEMV_ACC TGEMV_MX TLOAD TSTORE TPREFETCH
-MGATHER MSCATTER TEXPANDS TCI TTRI TFILLPAD TCVT TQUANT TDEQUANT TEXTRACT TINSERT
-TGATHER TSCATTER TCONCAT TTRANS TIMG2COL TMOV TGATHERB TDEINTERLEAVE TINTERLEAVE
-TRESHAPE TSORT TMRGSORT THISTOGRAM TPARTADD TPARTMUL TPARTMAX TPARTMIN TPARTARGMAX
-TPARTARGMIN TPUSH TPOP TALLOC TFREE
-""".split()
-
-EXPECTED_TMA = {
-    "TLOAD": ("BSTART.TLOAD", 0),
-    "TSTORE": ("BSTART.TSTORE", 1),
-    "TMOV": ("BSTART.TMOV", 2),
-    "TPREFETCH": ("BSTART.TPREFETCH", 3),
-    "MGATHER": ("BSTART.MGATHER", 4),
-    "MSCATTER": ("BSTART.MSCATTER", 5),
-}
-EXPECTED_CUBE = {
-    "TMATMUL": ("BSTART.TMATMUL", 0),
-    "TMATMUL_BIAS": ("BSTART.TMATMUL.BIAS", 1),
-    "TMATMUL_ACC": ("BSTART.TMATMUL.ACC", 2),
-    "TMATMUL_MX": ("BSTART.TMATMULMX", 4),
-    "TGEMV": ("BSTART.TGEMV", 16),
-    "TGEMV_BIAS": ("BSTART.TGEMV.BIAS", 17),
-    "TGEMV_ACC": ("BSTART.TGEMV.ACC", 18),
-    "TGEMV_MX": ("BSTART.TGEMVMX", 20),
-}
-EXPECTED_SUPPLEMENTAL = {
-    ("BSTART.MGATHER.MASK", "TMA", 6),
-    ("BSTART.MSCATTER.MASK", "TMA", 7),
-    ("BSTART.MGATHER.CAS", "TMA", 8),
-}
-REJECTED_NAMES = {
-    "TEXRACT",
-    "TFILL/TEXPANDS",
-    "TFMOD",
-    "TFMODS",
-    "TLRELU？",
-    "TPOW",
-    "TPOWS",
-    "TPRELU？",
-    "TRANDOM",
-}
+RELEASE = "0.57.1"
+ABI = "pto-isa-0.57.1-mode-function-v1"
+LOCK_REF = "isa/v0.57/pto-spec.lock.json"
+HASH = re.compile(r"^[0-9a-f]{64}$")
+ALIASES = {"TTRANSPOSE": "TTRANS", "TSORT32": "TSORT"}
+RETIRED_COMMAND_MNEMONICS = {"B.ARG", "BSTART.CUBE", "BSTART.FIXP"}
 
 
 def _load(path: Path) -> Any:
-    with path.open("r", encoding="utf-8") as stream:
-        return json.load(stream)
+    return json.loads(path.read_text(encoding="utf-8"))
+
+
+def _piece_signature(fields: list[dict[str, Any]], compiled: bool) -> dict[str, tuple[tuple[int, int], ...]]:
+    grouped: dict[str, list[tuple[int, int]]] = {}
+    for field in fields:
+        pieces = field.get("pieces", [])
+        if compiled:
+            value = [(int(piece["insn_lsb"]), int(piece["width"])) for piece in pieces]
+        else:
+            value = [(int(piece["instruction_lsb"]), int(piece["width"])) for piece in pieces]
+        grouped.setdefault(str(field["name"]), []).extend(value)
+    return {name: tuple(sorted(pieces)) for name, pieces in grouped.items()}
+
+
+def _constraints_match(form: dict[str, Any], item: dict[str, Any]) -> bool:
+    widths = {str(field["name"]): int(field["width"]) for field in form.get("fields", [])}
+    expected: dict[str, set[int]] = {}
+    for constraint in form.get("constraints", []):
+        field = str(constraint["field"])
+        domain = set(range(1 << widths[field]))
+        if constraint["operator"] == "one-of":
+            allowed = {int(value) for value in constraint["values"]}
+        elif constraint["operator"] == "not-equal":
+            allowed = domain - {int(constraint["value"])}
+        else:
+            raise ValueError(f"unsupported PTO constraint operator {constraint['operator']!r}")
+        expected[field] = expected.get(field, domain) & allowed
+
+    actual: dict[str, set[int]] = {}
+    for part in item.get("encoding", {}).get("parts", []):
+        for constraint in part.get("constraints", []) or []:
+            field = str(constraint["field"])
+            if field not in widths or constraint.get("op") != "!=":
+                raise ValueError(f"unsupported compiled constraint for {form['form_id']}: {constraint!r}")
+            domain = set(range(1 << widths[field]))
+            actual.setdefault(field, domain).discard(int(str(constraint["value"]), 0))
+    normalized_expected = {name: tuple(sorted(values)) for name, values in expected.items()}
+    normalized_actual = {name: tuple(sorted(values)) for name, values in actual.items()}
+    return normalized_actual == normalized_expected
+
+
+def _validate_compiled_forms(root: Path, source: dict[str, Any], errors: list[str]) -> None:
+    spec_path = root / "isa/v0.57/linxisa-v0.57.json"
+    if not spec_path.is_file():
+        errors.append(f"missing compiled spec: {spec_path}")
+        return
+    spec = _load(spec_path)
+    compiled = {
+        str(item["pto_source_form_id"]): item
+        for item in spec.get("instructions", [])
+        if item.get("pto_source_form_id")
+    }
+    for form in source["forms"]:
+        form_id = str(form["form_id"])
+        item = compiled.get(form_id)
+        if item is None:
+            errors.append(f"compiled command form missing source identity {form_id}")
+            continue
+        if item.get("mnemonic") != form.get("mnemonic") or item.get("length_bits") != form.get("length_bits"):
+            errors.append(f"{form_id}: mnemonic/length differs from PTO source")
+        actual_encoding = [
+            (int(part["mask"], 0), int(part["match"], 0), int(part["width_bits"]))
+            for part in item.get("encoding", {}).get("parts", [])
+        ]
+        expected_encoding = [
+            (int(part["mask"], 0), int(part["match"], 0), int(part["width_bits"]))
+            for part in form.get("encoding", [])
+        ]
+        if actual_encoding != expected_encoding:
+            errors.append(f"{form_id}: mask/match differs from PTO source")
+        actual_fields = []
+        instruction_offset = 0
+        for part in item.get("encoding", {}).get("parts", []):
+            for field in part.get("fields", []):
+                actual_fields.append({
+                    "name": field["name"],
+                    "pieces": [
+                        {**piece, "insn_lsb": int(piece["insn_lsb"]) + instruction_offset}
+                        for piece in field.get("pieces", [])
+                    ],
+                })
+            instruction_offset += int(part["width_bits"])
+        if _piece_signature(actual_fields, True) != _piece_signature(form.get("fields", []), False):
+            errors.append(f"{form_id}: field layout differs from PTO source")
+        if not _constraints_match(form, item):
+            errors.append(f"{form_id}: legality constraints differ from PTO source")
 
 
 def validate(root: Path) -> list[str]:
     errors: list[str] = []
-    ops_path = root / "isa/v0.57/state/pto_ops.json"
-    map_path = root / "isa/v0.57/state/pto_encoding_map.json"
-    engine_path = root / "isa/v0.57/state/engine_ops.json"
-    for path in (ops_path, map_path, engine_path):
-        if not path.is_file():
-            errors.append(f"missing required v0.57 PTO state file: {path}")
-    if errors:
+    profile = root / "isa/v0.57"
+    paths = {
+        "lock": profile / "pto-spec.lock.json",
+        "operations": profile / "state/pto_ops.json",
+        "encoding": profile / "state/pto_encoding_map.json",
+        "commands": profile / "state/pto_command_forms.json",
+        "engine": profile / "state/engine_ops.json",
+        "release": profile / "release_manifest.json",
+    }
+    missing = [str(path) for path in paths.values() if not path.is_file()]
+    if missing:
+        return [f"missing PTO 0.57.1 projection: {path}" for path in missing]
+    documents = {name: _load(path) for name, path in paths.items()}
+    lock = documents["lock"]
+    if lock.get("release") != RELEASE or lock.get("encoding_abi") != ABI:
+        errors.append("pto-spec lock has the wrong release or encoding ABI")
+    for label, value in (
+        ("content_sha256", lock.get("content_sha256")),
+        ("encoding_projection_sha256", lock.get("encoding_projection_sha256")),
+        ("hardware profile hash", lock.get("hardware_conformance_profile", {}).get("sha256")),
+        ("numeric vectors hash", lock.get("numeric_conformance_vectors", {}).get("sha256")),
+        ("release manifest hash", lock.get("release_manifest", {}).get("sha256")),
+        ("tile catalog hash", lock.get("catalogs", {}).get("tile_operations", {}).get("sha256")),
+        ("command catalog hash", lock.get("catalogs", {}).get("command_forms", {}).get("sha256")),
+    ):
+        if not isinstance(value, str) or HASH.fullmatch(value) is None:
+            errors.append(f"pto-spec lock {label} is not a SHA-256")
+    if lock.get("catalogs", {}).get("tile_operations", {}).get("count") != 120:
+        errors.append("pto-spec lock must freeze exactly 120 tile operations")
+    if lock.get("catalogs", {}).get("command_forms", {}).get("count") != 99:
+        errors.append("pto-spec lock must freeze exactly 99 command forms")
+    if (
+        lock.get("hardware_conformance_profile", {}).get("path")
+        != "spec/hardware-conformance-profile.json"
+    ):
+        errors.append("pto-spec lock must freeze the hardware conformance profile")
+    if (
+        lock.get("hardware_conformance_profile", {}).get("profile_id")
+        != "pto-hardware-numeric-0.57.1-ieee-v1"
+    ):
+        errors.append("pto-spec lock has the wrong hardware conformance profile identity")
+    if (
+        lock.get("numeric_conformance_vectors", {}).get("path")
+        != "spec/evidence/pto-isa-0571-hardware-numeric-vectors.json"
+    ):
+        errors.append("pto-spec lock must freeze the hardware numeric conformance vectors")
+
+    for name in ("operations", "encoding", "commands", "engine", "release"):
+        document = documents[name]
+        if name != "commands" and document.get("version") != RELEASE:
+            errors.append(f"{name}: version must be {RELEASE}")
+        if document.get("source_lock") != LOCK_REF:
+            errors.append(f"{name}: source_lock must be {LOCK_REF}")
+
+    operations = documents["operations"].get("operations", [])
+    entries = documents["encoding"].get("entries", [])
+    engine = documents["engine"]
+    if len(operations) != 120 or len(entries) != 120:
+        errors.append("PTO tile projections must contain exactly 120 entries")
         return errors
-
-    inventory = _load(ops_path)
-    encoding_map = _load(map_path)
-    engine = _load(engine_path)
-    for label, document in (("inventory", inventory), ("encoding map", encoding_map)):
-        if document.get("profile") != "v0.57":
-            errors.append(f"{label}: profile must be v0.57")
-        if document.get("version") != "0.57.0":
-            errors.append(f"{label}: version must be 0.57.0")
-        source = document.get("source", {})
-        if source.get("original_sha256") != SOURCE_SHA256:
-            errors.append(f"{label}: original workbook SHA-256 mismatch")
-        if source.get("review_export_sha256") != EXPORT_SHA256:
-            errors.append(f"{label}: review export SHA-256 mismatch")
-
-    operations = inventory.get("operations")
-    entries = encoding_map.get("entries")
-    if not isinstance(operations, list) or not isinstance(entries, list):
-        return errors + ["PTO operations and encoding entries must be lists"]
-    names = [str(operation.get("name") or "") for operation in operations]
-    if names != EXPECTED_NAMES:
-        errors.append("PTO inventory names/order do not match the frozen 111-row workbook")
+    counts = Counter(str(item.get("family")) for item in operations)
+    if counts != Counter({"TEPL": 98, "TMA": 9, "CUBE": 13}):
+        errors.append(f"tile family counts differ from 98/9/13: {dict(counts)}")
+    names = [str(item.get("name")) for item in operations]
     if len(names) != len(set(names)):
-        errors.append("PTO inventory contains duplicate names")
-    if [operation.get("source_row") for operation in operations] != list(range(2, 113)):
-        errors.append("PTO inventory source rows must be exactly 2..112")
-    if inventory.get("operation_count") != 111 or encoding_map.get("entry_count") != 111:
-        errors.append("PTO inventory and encoding map must each contain 111 workbook rows")
-
-    by_name = {operation["name"]: operation for operation in operations}
-    map_by_name = {entry["pto_name"]: entry for entry in entries}
-    if set(map_by_name) != set(by_name) or len(map_by_name) != len(entries):
-        errors.append("PTO encoding map must contain each inventory operation exactly once")
-
-    tepl_by_name = {
-        str(operation["name"]): int(operation["tile_opcode"])
-        for operation in engine.get("tepl", {}).get("ops", [])
-    }
-    tma_state = {
-        (entry["mnemonic"], int(entry["function"]))
-        for entry in engine.get("tma", {}).get("legal_aliases", [])
-    }
-    cube_state = {
-        (entry["mnemonic"], int(entry["function"]))
-        for entry in engine.get("cube", {}).get("legal_aliases", [])
-    }
-    seen_tepl: dict[int, str] = {}
-    family_counts = {"TEPL": 0, "TMA": 0, "CUBE": 0}
-    for name in names:
-        operation = by_name[name]
-        entry = map_by_name.get(name, {})
-        disposition = operation.get("disposition", {})
-        family = disposition.get("family")
-        if family not in family_counts:
-            errors.append(f"{name}: invalid disposition family {family!r}")
-            continue
-        family_counts[family] += 1
-        if entry.get("canonical_name") != operation.get("canonical_name"):
-            errors.append(f"{name}: encoding map disagrees with canonical_name")
-        for key in ("canonical_name", "family", "encoding_mnemonic", "selector", "function"):
-            if key in disposition and entry.get(key) != disposition.get(key):
-                errors.append(f"{name}: encoding map disagrees with inventory field {key}")
-
-        if name in EXPECTED_TMA:
-            mnemonic, function = EXPECTED_TMA[name]
-            if disposition != {
-                "family": "TMA",
-                "function": function,
-                "encoding_mnemonic": mnemonic,
-            }:
-                errors.append(f"{name}: incorrect TMA disposition")
-            if (mnemonic, function) not in tma_state:
-                errors.append(f"{name}: TMA disposition missing from engine state")
-        elif name in EXPECTED_CUBE:
-            mnemonic, function = EXPECTED_CUBE[name]
-            if disposition != {
-                "family": "CUBE",
-                "function": function,
-                "encoding_mnemonic": mnemonic,
-            }:
-                errors.append(f"{name}: incorrect CUBE disposition")
-            if (mnemonic, function) not in cube_state:
-                errors.append(f"{name}: CUBE disposition missing from engine state")
-        else:
-            canonical = "TTRANSPOSE" if name == "TTRANS" else name
-            selector = tepl_by_name.get(canonical)
-            rendered = None if selector is None else f"0x{selector:03X}"
-            if disposition != {
-                "family": "TEPL",
-                "selector": rendered,
-                "encoding_mnemonic": "BSTART.TEPL",
-            }:
-                errors.append(f"{name}: incorrect TEPL disposition")
-            if selector is not None:
-                previous = seen_tepl.get(selector)
-                if previous is not None and previous != canonical:
-                    errors.append(
-                        f"TEPL selector 0x{selector:03X} is shared by {previous} and {canonical}"
-                    )
-                seen_tepl[selector] = canonical
-
-    expected_counts = {"TEPL": 97, "TMA": 6, "CUBE": 8}
-    if family_counts != expected_counts:
-        errors.append(f"PTO family counts mismatch: {family_counts}")
-    if inventory.get("family_counts") != expected_counts:
-        errors.append("PTO inventory family_counts field is stale")
-    if encoding_map.get("family_counts") != expected_counts:
-        errors.append("PTO encoding map family_counts field is stale")
-
-    supplemental = {
-        (
-            entry.get("canonical_name"),
-            entry.get("family"),
-            entry.get("function"),
-        )
-        for entry in encoding_map.get("supplemental_entries", [])
+        errors.append("PTO tile operation names are not unique")
+    if any(item.get("contract_status") != "reviewed-complete" for item in operations):
+        errors.append("all 120 tile contracts must be reviewed-complete")
+    deleted = set(documents["operations"].get("deleted_names", []))
+    rejected = set(documents["operations"].get("rejected_names", []))
+    leaked = sorted((deleted | rejected | set(ALIASES)) & set(names))
+    if leaked:
+        errors.append(f"deleted/rejected/migration-only names leaked into tile operations: {leaked}")
+    if documents["encoding"].get("migration_aliases") != ALIASES:
+        errors.append("encoding migration aliases must be exactly TTRANSPOSE/TTRANS and TSORT32/TSORT")
+    if documents["encoding"].get("policy", {}).get("legacy_decode_allowed") is not False:
+        errors.append("legacy PTO decodes must be disabled")
+
+    tepl = [item for item in operations if item.get("family") == "TEPL"]
+    selectors = []
+    for item in tepl:
+        expected = (int(item["mode"]) << 5) | int(item["function"])
+        if int(str(item["selector"]), 0) != expected:
+            errors.append(f"{item.get('name')}: selector is not (Mode<<5)|Function")
+        selectors.append(expected)
+    if len(set(selectors)) != 98:
+        errors.append("TEPL Mode/Function assignments are not 98 unique selectors")
+    engine_tepl = {
+        item["name"]: (item.get("mode"), item.get("function"), item.get("logical_selector"))
+        for item in engine.get("tepl", {}).get("ops", [])
     }
-    if supplemental != EXPECTED_SUPPLEMENTAL:
-        errors.append("supplemental PR #123/#133 TMA mappings are incomplete")
-
-    all_names = set(names) | {
-        str(entry.get("canonical_name") or "") for entry in entries
+    expected_tepl = {
+        item["name"]: (item["mode"], item["function"], int(str(item["selector"]), 0))
+        for item in tepl
     }
-    leaked = sorted(REJECTED_NAMES & all_names)
-    if leaked:
-        errors.append(f"review-only or typo PTO names leaked into v0.57: {leaked}")
+    if engine.get("tepl", {}).get("kind") != "mode_function" or engine_tepl != expected_tepl:
+        errors.append("engine TEPL projection differs from the 98-operation source map")
+    tma_functions = {int(item["function"]) for item in operations if item.get("family") == "TMA"}
+    cube_functions = {int(item["function"]) for item in operations if item.get("family") == "CUBE"}
+    if tma_functions != set(range(9)):
+        errors.append("TMA functions must be exactly 0..8")
+    if cube_functions != {0, 1, 2, 4, 5, 6, 8, 16, 17, 18, 20, 21, 22}:
+        errors.append("CUBE functions differ from the 13 named source operations")
+    if engine.get("cube", {}).get("unassigned_function_behavior") != "illegal_instruction":
+        errors.append("unassigned CUBE functions must trap as illegal instructions")
+
+    commands = documents["commands"]
+    forms = commands.get("forms", [])
+    if commands.get("form_count") != 99 or len(forms) != 99:
+        errors.append("PTO command source must contain exactly 99 forms")
+    families = Counter(str(item.get("semantic_family")) for item in forms)
+    if families != Counter({"CMD": 74, "BBD": 25}):
+        errors.append(f"command source families differ from 74 CMD / 25 BBD: {dict(families)}")
+    _validate_compiled_forms(root, commands, errors)
+    compiled_mnemonics = {str(item.get("mnemonic")) for item in _load(
+        root / "isa/v0.57/linxisa-v0.57.json").get("instructions", [])}
+    retired_leaks = sorted(RETIRED_COMMAND_MNEMONICS & compiled_mnemonics)
+    if retired_leaks:
+        errors.append(f"retired PTO command forms remain executable: {retired_leaks}")
     return errors
 
 
diff --git a/tools/isa/gen_instruction_fragments.py b/tools/isa/gen_instruction_fragments.py
index 8f6a972a..80ecdf7e 100644
--- a/tools/isa/gen_instruction_fragments.py
+++ b/tools/isa/gen_instruction_fragments.py
@@ -505,8 +505,6 @@ def _inst_description(inst: Dict[str, Any]) -> str:
             return "Tile input/output descriptor: binds tile operands and allocation metadata to a block."
         if base.startswith("B.IOR"):
             return "GPR input/output descriptor: binds scalar registers to a block argument slot."
-        if base.startswith("B.ARG"):
-            return "Block argument descriptor: carries layout format and pad policy for TMA operations."
         if base.startswith("B.DIM"):
             return "Block dimension descriptor: sets LB0/LB1/LB2 loop-bound registers."
         if base.startswith("B.TEXT"):
@@ -697,7 +695,10 @@ def main() -> int:
         print("OK")
         return 0
 
-    _emit_all(spec_path, uop_root, out_dir, args.enc_rel_dir)
+    expected_names = _emit_all(spec_path, uop_root, out_dir, args.enc_rel_dir)
+    for path in out_dir.glob("*.adoc"):
+        if path.name not in expected_names:
+            path.unlink()
 
     return 0
 
diff --git a/tools/isa/gen_sail_decode.py b/tools/isa/gen_sail_decode.py
index bef6c845..9b2bd132 100644
--- a/tools/isa/gen_sail_decode.py
+++ b/tools/isa/gen_sail_decode.py
@@ -146,7 +146,6 @@ def norm_exec_name(mnemonic: str) -> str:
     "BSTART.TMOV": "0b1010",
     "BSTART.CUBE": "0b1011",
     "BSTART.TEPL": "0b1101",
-    "BSTART.FIXP": "0b1110",
     "BSTART.TMATMUL": "0b1111",
     "BSTART.TMATMUL.ACC": "0b1111",
     "BSTART.TMATMUL.BIAS": "0b1111",
@@ -173,7 +172,9 @@ def norm_exec_name(mnemonic: str) -> str:
     "C.BSTART.MPAR": "0b0001",
     "C.BSTART.MSEQ": "0b0001",
     "BSTART.TLOAD": "0b0010",
-    "BSTART.TPREFETCH": "0b0010",
+    # TPREFETCH is scalar-address/byte-count driven and has no Tile IO.
+    # Its exact DATR+IOR contract is enforced by the tile transaction envelope.
+    "BSTART.TPREFETCH": "0b0110",
     "BSTART.MGATHER": "0b0010",
     "BSTART.MGATHER.CAS": "0b0010",
     "BSTART.MGATHER.MASK": "0b0010",
@@ -195,7 +196,6 @@ def norm_exec_name(mnemonic: str) -> str:
     "BSTART.TGEMVMX.BIAS": "0b0100",
     "BSTART.ACCCVT": "0b0101",
     "BSTART.TEPL": "0b0110",
-    "BSTART.FIXP": "0b0110",
     "BSTART.CUBE": "0b0110",
 }
 
@@ -349,6 +349,31 @@ def canonical_redecode_entries(retired_metadata: dict[str, Any] | None) -> list[
     return canonical
 
 
+def reserved_encoding_entries(
+    retired_metadata: dict[str, Any] | None,
+    width: int,
+) -> list[dict[str, Any]]:
+    if retired_metadata is None:
+        return []
+    entries = retired_metadata.get("entries")
+    if not isinstance(entries, list):
+        raise ValueError("retired encoding metadata must contain an entries list")
+
+    reserved = []
+    for idx, entry in enumerate(entries):
+        if entry.get("disposition") != "reserved" or entry.get("length_bits") != width:
+            continue
+        missing = [key for key in ("mask", "match", "retired_mnemonic") if key not in entry]
+        if missing:
+            raise ValueError(f"reserved entry {idx} is missing required field(s): {', '.join(missing)}")
+        mask = parse_hexish(entry["mask"])
+        match = parse_hexish(entry["match"])
+        if match & ~mask:
+            raise ValueError(f"reserved entry {idx} has match bits outside mask")
+        reserved.append({"mask": mask, "match": match, "retired_mnemonic": entry["retired_mnemonic"]})
+    return reserved
+
+
 def one_part_pattern(inst: dict[str, Any]) -> tuple[int, int] | None:
     parts = inst["encoding"]["parts"]
     if len(parts) != 1:
@@ -531,7 +556,17 @@ def branch_condition(inst: dict) -> str:
             conditions.append(
                 constraint_expr(inst, constraint["field"], constraint["op"], constraint["value"])
             )
-    return " & ".join(conditions)
+    while len(conditions) > 1:
+        combined: list[str] = []
+        for idx in range(0, len(conditions), 2):
+            if idx + 1 == len(conditions):
+                combined.append(conditions[idx])
+            else:
+                combined.append(
+                    f"and_bool_no_flow({conditions[idx]}, {conditions[idx + 1]})"
+                )
+        conditions = combined
+    return conditions[0]
 
 
 def decode_vector_type_expr(raw_name: str, mnemonic: str) -> str:
@@ -688,6 +723,9 @@ def prelude_lines(inst: dict, raw_fields: dict[str, tuple[str, int]], width: int
             f"{raw_fields['RegDst'][0]});"
         )
 
+    elif mnemonic == "B.IOT":
+        lines.append("decoded_biot_raw_shadow = sail_zero_extend(inst, 64);")
+
     if (
         mnemonic.startswith("BSTART")
         or mnemonic.startswith("C.BSTART")
@@ -700,6 +738,8 @@ def prelude_lines(inst: dict, raw_fields: dict[str, tuple[str, int]], width: int
         lines.append(f"decoded_block_type_shadow = {block_type};")
         lines.append(f"decoded_block_xfer_kind_shadow = {block_xfer_expr(inst, raw_fields)};")
         lines.append(f"decoded_block_contract_kind_shadow = {contract_kind};")
+        if "DataType" in raw_fields:
+            lines.append(f"decoded_tile_datatype_shadow = {raw_fields['DataType'][0]};")
 
     if mnemonic.startswith(VECTOR_ALL_MNEMONICS_PREFIX):
         srcl_t = "decoded_vec_srcl_type_shadow"
@@ -794,17 +834,36 @@ def render_decode_function(
     retired_metadata: dict[str, Any] | None = None,
 ) -> list[str]:
     func_name = WIDTH_FUNCS[width]
-    lines = [f"function {func_name}(inst : bits({width})) -> unit = {{"]  # noqa: E231
+    ordered = order_decode_entries(entries, retired_metadata)
+    reserved = reserved_encoding_entries(retired_metadata, width)
+    if width == 32:
+        return render_decode32_partitioned(func_name, ordered, exec_params, reserved)
+
+    lines: list[str] = []
+    for idx, inst in enumerate(ordered):
+        lines.extend(render_decode_match_predicate(func_name, idx, width, inst))
+    lines.append(f"function {func_name}(inst : bits({width})) -> unit = {{")  # noqa: E231
     if width == 64:
         lines.append("  let part0 : bits(32) = inst[63..32];")
         lines.append("  let part1 : bits(32) = inst[31..0];")
-    ordered = order_decode_entries(entries, retired_metadata)
+    branch_index = 0
+    for rule in reserved:
+        prefix = "if" if branch_index == 0 else "else if"
+        lines.append(
+            f"  {prefix} (inst & {hex_const(rule['mask'], width)}) == "
+            f"{hex_const(rule['match'], width)} then {{"
+        )
+        lines.append(f"    // Reserved retired encoding: {rule['retired_mnemonic']}")
+        lines.append("    trap_illegal_inst(read_pc_or_tpc())")
+        lines.append("  }")
+        branch_index += 1
     for idx, inst in enumerate(ordered):
-        prefix = "if" if idx == 0 else "else if"
-        lines.append(f"  {prefix} {branch_condition(inst)} then {{")
+        prefix = "if" if branch_index == 0 else "else if"
+        lines.append(f"  {prefix} {func_name}_match_{idx}(inst) then {{")
         for stmt in branch_body(inst, exec_params):
             lines.append(f"    {stmt}")
         lines.append("  }")
+        branch_index += 1
     lines.append("  else {")
     lines.append("    trap_illegal_inst(read_pc_or_tpc())")
     lines.append("  }")
@@ -812,6 +871,194 @@ def render_decode_function(
     return lines
 
 
+def render_decode_match_predicate(
+    func_name: str,
+    idx: int,
+    width: int,
+    inst: dict,
+) -> list[str]:
+    """Hide encoding refinements behind a bool-valued function boundary."""
+
+    lines = [f"function {func_name}_match_{idx}(inst : bits({width})) -> bool = {{"]
+    if width == 64:
+        lines.append("  let part0 : bits(32) = inst[63..32];")
+        lines.append("  let part1 : bits(32) = inst[31..0];")
+    lines.append(f"  {branch_condition(inst)}")
+    lines.append("}")
+    lines.append("")
+    return lines
+
+
+def render_decode32_partitioned(
+    func_name: str,
+    ordered: list[dict],
+    exec_params: dict[str, list[str]],
+    reserved: list[dict[str, Any]],
+) -> list[str]:
+    """Render the 32-bit catalog behind an exact low-opcode dispatcher.
+
+    A single 329-arm else-if chain makes Sail retain every prior singleton
+    negation as a flow fact and causes type checking to grow beyond CI-scale
+    time. All but the BSTART.CALL form fix inst[6..0], so route those disjoint
+    sets first and keep only genuinely broad encodings in the outer chain.
+    """
+
+    exact_groups: dict[int, list[dict]] = defaultdict(list)
+    broad: list[dict] = []
+    for inst in ordered:
+        part = inst["encoding"]["parts"][0]
+        mask = parse_hexish(part["mask"])
+        match = parse_hexish(part["match"])
+        if (mask & 0x7F) == 0x7F:
+            exact_groups[match & 0x7F].append(inst)
+        else:
+            broad.append(inst)
+
+    for broad_inst in broad:
+        broad_part = broad_inst["encoding"]["parts"][0]
+        broad_pattern = (parse_hexish(broad_part["mask"]), parse_hexish(broad_part["match"]))
+        for group in exact_groups.values():
+            for exact_inst in group:
+                exact_part = exact_inst["encoding"]["parts"][0]
+                exact_pattern = (parse_hexish(exact_part["mask"]), parse_hexish(exact_part["match"]))
+                if encoding_patterns_overlap(*broad_pattern, *exact_pattern):
+                    raise ValueError(
+                        "cannot partition overlapping 32-bit broad/exact encodings: "
+                        f"{broad_inst['mnemonic']} and {exact_inst['mnemonic']}"
+                    )
+
+    lines: list[str] = []
+    for opcode, group in sorted(exact_groups.items()):
+        lines.extend(render_decode32_opcode_group(func_name, opcode, group, exec_params))
+
+    lines.append(f"function {func_name}(inst : bits(32)) -> unit = {{")
+    branch_index = 0
+    for rule in reserved:
+        prefix = "if" if branch_index == 0 else "else if"
+        lines.append(
+            f"  {prefix} (inst & {hex_const(rule['mask'], 32)}) == "
+            f"{hex_const(rule['match'], 32)} then {{"
+        )
+        lines.append(f"    // Reserved retired encoding: {rule['retired_mnemonic']}")
+        lines.append("    trap_illegal_inst(read_pc_or_tpc())")
+        lines.append("  }")
+        branch_index += 1
+    for inst in broad:
+        prefix = "if" if branch_index == 0 else "else if"
+        lines.append(f"  {prefix} {branch_condition(inst)} then {{")
+        for stmt in branch_body(inst, exec_params):
+            lines.append(f"    {stmt}")
+        lines.append("  }")
+        branch_index += 1
+    if branch_index:
+        lines.append("  else {")
+        indent = "    "
+    else:
+        indent = "  "
+    lines.append(f"{indent}match inst[6..0] {{")
+    arms = [
+        f"{indent}  {bit_const(7, opcode)} => {func_name}_opcode_{bit_const(7, opcode)}(inst)"
+        for opcode in sorted(exact_groups)
+    ]
+    arms.append(f"{indent}  _ => trap_illegal_inst(read_pc_or_tpc())")
+    lines.append(",\n".join(arms))
+    lines.append(f"{indent}}}")
+    if branch_index:
+        lines.append("  }")
+    lines.append("}")
+    return lines
+
+
+def append_decode32_chain(
+    lines: list[str],
+    helper: str,
+    entries: list[dict],
+    exec_params: dict[str, list[str]],
+    fallback: str,
+) -> None:
+    for idx, inst in enumerate(entries):
+        lines.extend(render_decode_match_predicate(helper, idx, 32, inst))
+    lines.append(f"function {helper}(inst : bits(32)) -> unit = {{")
+    for idx, inst in enumerate(entries):
+        prefix = "if" if idx == 0 else "else if"
+        lines.append(f"  {prefix} {helper}_match_{idx}(inst) then {{")
+        for stmt in branch_body(inst, exec_params):
+            lines.append(f"    {stmt}")
+        lines.append("  }")
+    lines.append("  else {")
+    lines.append(f"    {fallback}")
+    lines.append("  }")
+    lines.append("}")
+    lines.append("")
+
+
+def render_decode32_opcode_group(
+    func_name: str,
+    opcode: int,
+    ordered: list[dict],
+    exec_params: dict[str, list[str]],
+) -> list[str]:
+    """Partition one exact opcode group again by the fixed funct3 field."""
+
+    helper = f"{func_name}_opcode_{bit_const(7, opcode)}"
+    exact_groups: dict[int, list[dict]] = defaultdict(list)
+    broad: list[dict] = []
+    positions = {id(inst): idx for idx, inst in enumerate(ordered)}
+    for inst in ordered:
+        part = inst["encoding"]["parts"][0]
+        mask = parse_hexish(part["mask"])
+        match = parse_hexish(part["match"])
+        if (mask & 0x7000) == 0x7000:
+            exact_groups[(match >> 12) & 0x7].append(inst)
+        else:
+            broad.append(inst)
+
+    for broad_inst in broad:
+        broad_part = broad_inst["encoding"]["parts"][0]
+        broad_pattern = (parse_hexish(broad_part["mask"]), parse_hexish(broad_part["match"]))
+        for group in exact_groups.values():
+            for exact_inst in group:
+                exact_part = exact_inst["encoding"]["parts"][0]
+                exact_pattern = (parse_hexish(exact_part["mask"]), parse_hexish(exact_part["match"]))
+                if (
+                    encoding_patterns_overlap(*broad_pattern, *exact_pattern)
+                    and positions[id(broad_inst)] < positions[id(exact_inst)]
+                ):
+                    raise ValueError(
+                        "cannot preserve 32-bit funct3 precedence while partitioning: "
+                        f"{broad_inst['mnemonic']} precedes {exact_inst['mnemonic']}"
+                    )
+
+    lines: list[str] = []
+    broad_helper = f"{helper}_fallback"
+    if broad:
+        append_decode32_chain(
+            lines,
+            broad_helper,
+            broad,
+            exec_params,
+            "trap_illegal_inst(read_pc_or_tpc())",
+        )
+
+    fallback = f"{broad_helper}(inst)" if broad else "trap_illegal_inst(read_pc_or_tpc())"
+    for funct3, group in sorted(exact_groups.items()):
+        funct3_helper = f"{helper}_funct3_{bit_const(3, funct3)}"
+        append_decode32_chain(lines, funct3_helper, group, exec_params, fallback)
+
+    lines.append(f"function {helper}(inst : bits(32)) -> unit = {{")
+    lines.append("  match inst[14..12] {")
+    arms = [
+        f"    {bit_const(3, funct3)} => {helper}_funct3_{bit_const(3, funct3)}(inst)"
+        for funct3 in sorted(exact_groups)
+    ]
+    arms.append(f"    _ => {fallback}")
+    lines.append(",\n".join(arms))
+    lines.append("  }")
+    lines.append("}")
+    lines.append("")
+    return lines
+
+
 def render(
     spec: dict,
     exec_text: str,
diff --git a/tools/isa/gen_sail_status.py b/tools/isa/gen_sail_status.py
index 0406173d..c7b84257 100644
--- a/tools/isa/gen_sail_status.py
+++ b/tools/isa/gen_sail_status.py
@@ -50,7 +50,7 @@ def build(spec_path: Path, policy_path: Path) -> dict[str, Any]:
         }
 
     return {
-        "schema_version": "linx-sail-status-v0.57.0",
+        "schema_version": "linx-sail-status-v0.57.1",
         "spec_version": str(spec.get("version") or ""),
         "forms": forms,
     }
diff --git a/tools/isa/import_pto_v0571.py b/tools/isa/import_pto_v0571.py
new file mode 100644
index 00000000..8c6cee56
--- /dev/null
+++ b/tools/isa/import_pto_v0571.py
@@ -0,0 +1,368 @@
+#!/usr/bin/env python3
+"""Import the canonical PTO ISA 0.57.1 release into the Linx v0.57 profile.
+
+The lock file is the only checked-in location that repeats the upstream commit
+and release hashes.  The three state files produced here are deterministic
+projections of the locked upstream catalogs; they name the lock instead of
+copying its identity fields.
+"""
+
+from __future__ import annotations
+
+import argparse
+import hashlib
+import json
+import subprocess
+import sys
+from collections import Counter
+from pathlib import Path
+from typing import Any
+
+
+ROOT = Path(__file__).resolve().parents[2]
+PROFILE = ROOT / "isa" / "v0.57"
+LOCK_PATH = PROFILE / "pto-spec.lock.json"
+RELEASE = "0.57.1"
+EXPECTED_ABI = "pto-isa-0.57.1-mode-function-v1"
+
+
+def load_json(path: Path) -> dict[str, Any]:
+    return json.loads(path.read_text(encoding="utf-8"))
+
+
+def sha256(path: Path) -> str:
+    digest = hashlib.sha256()
+    with path.open("rb") as stream:
+        for chunk in iter(lambda: stream.read(1024 * 1024), b""):
+            digest.update(chunk)
+    return digest.hexdigest()
+
+
+def pretty(document: Any) -> str:
+    return json.dumps(document, indent=2, ensure_ascii=False) + "\n"
+
+
+def source_paths(source_root: Path) -> tuple[Path, Path, Path, Path, Path]:
+    return (
+        source_root / "spec" / "release-manifest.json",
+        source_root / "spec" / "catalog" / "tile-operations.json",
+        source_root / "spec" / "catalog" / "command-forms.json",
+        source_root / "spec" / "hardware-conformance-profile.json",
+        source_root / "spec" / "evidence" / "pto-isa-0571-hardware-numeric-vectors.json",
+    )
+
+
+def validate_source(source_root: Path) -> tuple[dict[str, Any], dict[str, Any], dict[str, Any]]:
+    manifest_path, tile_path, command_path, hardware_path, vectors_path = source_paths(source_root)
+    for path in (manifest_path, tile_path, command_path, hardware_path, vectors_path):
+        if not path.is_file():
+            raise ValueError(f"missing upstream PTO source: {path}")
+
+    manifest = load_json(manifest_path)
+    tiles = load_json(tile_path)
+    commands = load_json(command_path)
+    hardware = load_json(hardware_path)
+    vectors = load_json(vectors_path)
+    if manifest.get("release") != RELEASE:
+        raise ValueError(f"upstream release must be {RELEASE}")
+    if manifest.get("encoding_abi") != EXPECTED_ABI:
+        raise ValueError(f"unexpected encoding ABI: {manifest.get('encoding_abi')!r}")
+    counts = manifest.get("catalog_counts") or {}
+    if counts.get("tile_operations_total") != 120 or counts.get("command_forms") != 99:
+        raise ValueError("upstream manifest must publish 120 tile operations and 99 command forms")
+    if tiles.get("operation_count") != 120 or len(tiles.get("operations") or []) != 120:
+        raise ValueError("upstream tile catalog is not the exact 120-operation release")
+    if commands.get("form_count") != 99 or len(commands.get("forms") or []) != 99:
+        raise ValueError("upstream command catalog is not the exact 99-form release")
+
+    canonical = {entry["path"]: entry["sha256"] for entry in manifest["canonical_inputs"]}
+    for path, rel in ((tile_path, "spec/catalog/tile-operations.json"),
+                      (command_path, "spec/catalog/command-forms.json")):
+        actual = sha256(path)
+        if canonical.get(rel) != actual:
+            raise ValueError(f"{rel} does not match the release manifest: {actual}")
+
+    hardware_manifest = manifest.get("hardware_conformance_profile") or {}
+    if hardware_manifest.get("path") != "spec/hardware-conformance-profile.json":
+        raise ValueError("release manifest names the wrong hardware conformance profile")
+    if hardware_manifest.get("evidence") != "spec/evidence/pto-isa-0571-hardware-numeric-vectors.json":
+        raise ValueError("release manifest names the wrong hardware numeric evidence")
+    if hardware_manifest.get("sha256") != sha256(hardware_path):
+        raise ValueError("hardware conformance profile does not match the release manifest")
+    if hardware.get("profile_id") != hardware_manifest.get("profile_id"):
+        raise ValueError("hardware profile identity differs from the release manifest")
+    if vectors.get("hardware_profile_id") != hardware.get("profile_id"):
+        raise ValueError("numeric vectors target a different hardware profile")
+    if vectors.get("hardware_profile_sha256") != sha256(hardware_path):
+        raise ValueError("numeric vectors target a different hardware profile hash")
+    return manifest, tiles, commands
+
+
+def build_lock(source_root: Path, manifest: dict[str, Any]) -> dict[str, Any]:
+    manifest_path, tile_path, command_path, hardware_path, vectors_path = source_paths(source_root)
+    try:
+        commit = subprocess.check_output(
+            ["git", "rev-parse", "HEAD"], cwd=source_root, text=True
+        ).strip()
+    except (OSError, subprocess.CalledProcessError) as exc:
+        raise ValueError(f"cannot resolve upstream git commit: {exc}") from exc
+    return {
+        "$schema": "https://docs.openclaw.ai/schemas/linxisa/pto_spec_lock.v1.json",
+        "catalogs": {
+            "command_forms": {
+                "path": "spec/catalog/command-forms.json",
+                "sha256": sha256(command_path),
+                "count": 99,
+            },
+            "tile_operations": {
+                "path": "spec/catalog/tile-operations.json",
+                "sha256": sha256(tile_path),
+                "count": 120,
+            },
+        },
+        "content_sha256": manifest["content_sha256"],
+        "encoding_abi": manifest["encoding_abi"],
+        "encoding_projection_sha256": manifest["encoding_projection_sha256"],
+        "hardware_conformance_profile": {
+            "path": "spec/hardware-conformance-profile.json",
+            "profile_id": manifest["hardware_conformance_profile"]["profile_id"],
+            "sha256": sha256(hardware_path),
+        },
+        "numeric_conformance_vectors": {
+            "path": "spec/evidence/pto-isa-0571-hardware-numeric-vectors.json",
+            "sha256": sha256(vectors_path),
+        },
+        "release": manifest["release"],
+        "release_manifest": {
+            "path": "spec/release-manifest.json",
+            "sha256": sha256(manifest_path),
+        },
+        "source": {
+            "commit": commit,
+            "repository": "https://github.com/PTO-ISA/pto-spec.git",
+        },
+    }
+
+
+def project_pto_ops(tiles: dict[str, Any]) -> dict[str, Any]:
+    counts = Counter(operation["family"] for operation in tiles["operations"])
+    return {
+        "$schema": "https://docs.openclaw.ai/schemas/linxisa/pto_ops.v1.json",
+        "profile": "v0.57",
+        "version": RELEASE,
+        "source_lock": "isa/v0.57/pto-spec.lock.json",
+        "operation_count": len(tiles["operations"]),
+        "family_counts": dict(sorted(counts.items())),
+        "deleted_names": tiles["deleted_names"],
+        "rejected_names": tiles["rejected_names"],
+        "reserved": tiles["reserved"],
+        "operations": tiles["operations"],
+    }
+
+
+def project_encoding_map(tiles: dict[str, Any]) -> dict[str, Any]:
+    entries = []
+    for operation in tiles["operations"]:
+        entries.append({
+            "name": operation["name"],
+            "family": operation["family"],
+            "command_mnemonic": operation["command_mnemonic"],
+            "selector": operation.get("selector"),
+            "mode": operation.get("mode"),
+            "function": operation.get("function"),
+            "disposition": operation["disposition"],
+            "contract_status": operation["contract_status"],
+        })
+    counts = Counter(entry["family"] for entry in entries)
+    return {
+        "$schema": "https://docs.openclaw.ai/schemas/linxisa/pto_encoding_map.v1.json",
+        "profile": "v0.57",
+        "version": RELEASE,
+        "source_lock": "isa/v0.57/pto-spec.lock.json",
+        "policy": {
+            "catalog_order_allocates_encodings": False,
+            "unlisted_selectors_reserved": True,
+            "legacy_decode_allowed": False,
+            "source_aliases_are_migration_only": True,
+        },
+        "entry_count": len(entries),
+        "family_counts": dict(sorted(counts.items())),
+        "migration_aliases": {"TTRANSPOSE": "TTRANS", "TSORT32": "TSORT"},
+        "entries": entries,
+    }
+
+
+def project_command_forms(commands: dict[str, Any]) -> dict[str, Any]:
+    result = dict(commands)
+    result["source_lock"] = "isa/v0.57/pto-spec.lock.json"
+    return result
+
+
+def project_release_manifest(
+    manifest: dict[str, Any], tiles: dict[str, Any], commands: dict[str, Any]
+) -> dict[str, Any]:
+    return {
+        "$schema": "https://docs.openclaw.ai/schemas/linxisa/release_manifest.v1.json",
+        "profile": "v0.57",
+        "version": RELEASE,
+        "source_lock": "isa/v0.57/pto-spec.lock.json",
+        "policy": {
+            "pto_spec_is_sole_source": True,
+            "legacy_decode_allowed": False,
+            "unlisted_selectors_reserved": True,
+            "migration_aliases_are_source_only": True,
+        },
+        "cardinality": {
+            "tile_operations": len(tiles["operations"]),
+            "tile_families": dict(Counter(item["family"] for item in tiles["operations"])),
+            "command_forms": len(commands["forms"]),
+            "command_form_families": manifest["catalog_counts"]["command_form_families"],
+            "scalar_forms": manifest["catalog_counts"]["scalar_forms"],
+        },
+        "migration_aliases": {"TTRANSPOSE": "TTRANS", "TSORT32": "TSORT"},
+        "deleted_names": tiles["deleted_names"],
+        "rejected_names": tiles["rejected_names"],
+        "elf_identity": manifest["elf_identity"],
+    }
+
+
+def project_engine_ops(tiles: dict[str, Any]) -> dict[str, Any]:
+    current = load_json(PROFILE / "state" / "engine_ops.json")
+    old_tepl = {entry["name"]: entry for entry in current["tepl"]["ops"]}
+    if "TTRANSPOSE" in old_tepl and "TTRANS" not in old_tepl:
+        old_tepl["TTRANS"] = old_tepl["TTRANSPOSE"]
+
+    tepl_ops = []
+    for operation in (item for item in tiles["operations"] if item["family"] == "TEPL"):
+        entry = dict(old_tepl.get(operation["name"], {}))
+        entry.pop("tile_opcode", None)
+        entry.update({
+            "name": operation["name"],
+            "mode": operation["mode"],
+            "function": operation["function"],
+            "logical_selector": int(operation["selector"], 16),
+            "semantic_status": operation["contract_status"],
+            "semantic_handler": operation["semantic_handler"],
+            "legality_handler": operation["legality_handler"],
+            "effect_contract": operation["effect_contract"],
+            "fault_contract": operation["fault_contract"],
+            "restart_contract": operation["restart_contract"],
+            "operands": operation["operands"],
+            "state_effects": operation["state_effects"],
+        })
+        tepl_ops.append(entry)
+
+    def aliases(family: str) -> list[dict[str, Any]]:
+        result = []
+        for operation in tiles["operations"]:
+            if operation["family"] != family:
+                continue
+            result.append({
+                "name": operation["name"],
+                "function": operation["function"],
+                "mnemonic": operation["command_mnemonic"],
+                "semantic_status": operation["contract_status"],
+                "semantic_handler": operation["semantic_handler"],
+                "state_effects": operation["state_effects"],
+            })
+        return result
+
+    current.update({
+        "profile": "v0.57",
+        "version": RELEASE,
+        "source_lock": "isa/v0.57/pto-spec.lock.json",
+        "note": "Linx scheduling metadata projected onto the normative PTO ISA 0.57.1 tile catalog.",
+    })
+    current["tma"] = {
+        "kind": "function_u5",
+        "function_field_bits": [0, 4],
+        "legal_aliases": aliases("TMA"),
+        "reserved_function_range": [9, 31],
+        "reserved_behavior": "illegal_instruction",
+    }
+    current["cube"] = {
+        "kind": "function_u5",
+        "function_field_bits": [0, 4],
+        "legal_aliases": aliases("CUBE"),
+        "unassigned_function_behavior": "illegal_instruction",
+        "reserved_functions": tiles["reserved"]["cube_functions_without_named_alias"],
+    }
+    current["tepl"] = {
+        "kind": "mode_function",
+        "selector_formula": "(mode << 5) | function",
+        "mode_field_bits": [0, 1],
+        "function_field_bits": [0, 4],
+        "accepted_selector_count": 98,
+        "reserved_selector_ranges": tiles["reserved"]["tepl_selector_ranges"],
+        "migration_aliases": {"TTRANSPOSE": "TTRANS", "TSORT32": "TSORT"},
+        "ops": tepl_ops,
+    }
+    current["tile_capacity_model"] = {
+        "kind": "dynamic_per_descriptor",
+        "cell_bytes": 128,
+        "cells_per_pe": 2048,
+        "capacity_bytes_per_pe": 262144,
+        "b_iot_size_imm4_bytes": [None, None, None, 128, 256, 512, 1024, 2048, 4096, 8192,
+                                      None, None, None, None, None, None],
+        "normal_tile_min_bytes": 128,
+        "normal_tile_max_bytes": 8192,
+        "resource_shortage": "precise_allocation_trap",
+        "eviction_or_spill": "forbidden",
+        "physical_contiguity": "required",
+    }
+    return current
+
+
+def projections(
+    manifest: dict[str, Any], tiles: dict[str, Any], commands: dict[str, Any]
+) -> dict[Path, dict[str, Any]]:
+    state = PROFILE / "state"
+    return {
+        state / "pto_ops.json": project_pto_ops(tiles),
+        state / "pto_encoding_map.json": project_encoding_map(tiles),
+        state / "pto_command_forms.json": project_command_forms(commands),
+        state / "engine_ops.json": project_engine_ops(tiles),
+        PROFILE / "release_manifest.json": project_release_manifest(manifest, tiles, commands),
+    }
+
+
+def compare_or_write(expected: dict[Path, dict[str, Any]], check: bool) -> list[str]:
+    errors = []
+    for path, document in expected.items():
+        rendered = pretty(document)
+        if check:
+            if not path.is_file() or path.read_text(encoding="utf-8") != rendered:
+                errors.append(f"out-of-date PTO projection: {path.relative_to(ROOT)}")
+        else:
+            path.write_text(rendered, encoding="utf-8")
+    return errors
+
+
+def main() -> int:
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--source-root", type=Path, required=True)
+    parser.add_argument("--check", action="store_true")
+    parser.add_argument("--update-lock", action="store_true")
+    args = parser.parse_args()
+    try:
+        manifest, tiles, commands = validate_source(args.source_root)
+        upstream_lock = build_lock(args.source_root, manifest)
+        if args.update_lock:
+            LOCK_PATH.write_text(pretty(upstream_lock), encoding="utf-8")
+        elif load_json(LOCK_PATH) != upstream_lock:
+            raise ValueError("checked-in pto-spec.lock.json does not match the upstream release")
+        errors = compare_or_write(projections(manifest, tiles, commands), args.check)
+    except (KeyError, TypeError, ValueError, json.JSONDecodeError) as exc:
+        print(f"error: {exc}", file=sys.stderr)
+        return 1
+    if errors:
+        for error in errors:
+            print(f"error: {error}", file=sys.stderr)
+        return 1
+    action = "verified" if args.check else "updated"
+    print(f"{action} PTO ISA {RELEASE} lock and Linx projections")
+    return 0
+
+
+if __name__ == "__main__":
+    raise SystemExit(main())
diff --git a/tools/isa/test_gen_sail_decode.py b/tools/isa/test_gen_sail_decode.py
index 575eeff3..0d954191 100644
--- a/tools/isa/test_gen_sail_decode.py
+++ b/tools/isa/test_gen_sail_decode.py
@@ -36,19 +36,15 @@ def _bstart_entries(spec: dict) -> list[dict]:
     ]
 
 
-def test_tepl_canonical_redecode_precedes_broad_overlaps() -> None:
+def test_tepl_mode_function_decode_precedes_broad_overlaps() -> None:
     spec = _load_spec()
     retired = _load_retired()
     ordered = gen_sail_decode.order_decode_entries(_bstart_entries(spec), retired)
-    by_name = {inst["mnemonic"]: idx for idx, inst in enumerate(ordered)}
-
     tepl = next(inst for inst in ordered if inst["mnemonic"] == "BSTART.TEPL")
-    assert _one_part(tepl) == (0x06007FFF, 0x02001181)
-    for mnemonic in ("BSTART.MPAR", "BSTART.MSEQ", "BSTART.VPAR", "BSTART.VSEQ"):
-        assert by_name["BSTART.TEPL"] < by_name[mnemonic], mnemonic
+    assert _one_part(tepl) == (0x000FFFFF, 0x00019181)
 
 
-def test_tepl_canonical_redecode_is_deterministic() -> None:
+def test_tepl_mode_function_decode_is_deterministic() -> None:
     spec = _load_spec()
     retired = _load_retired()
     entries = _bstart_entries(spec)
@@ -57,21 +53,39 @@ def test_tepl_canonical_redecode_is_deterministic() -> None:
     assert first == second
 
 
-def test_tepl_canonical_redecode_render_selects_tepl_first() -> None:
+def test_tepl_mode_function_decode_render_selects_tepl_first() -> None:
     spec = _load_spec()
     retired = _load_retired()
     execute_text = (ROOT / "isa/sail/model/execute/execute.sail").read_text(encoding="utf-8")
     rendered = gen_sail_decode.render(spec, execute_text, "isa/v0.57/linxisa-v0.57.json", retired)
 
     tepl_pos = rendered.index("// BSTART.TEPL |")
-    assert tepl_pos < rendered.index("// BSTART.MPAR |")
-    assert tepl_pos < rendered.index("// BSTART.MSEQ |")
-    assert tepl_pos < rendered.index("// BSTART.VPAR |")
-    assert tepl_pos < rendered.index("// BSTART.VSEQ |")
     tepl_body = rendered[tepl_pos : rendered.index("  }", tepl_pos)]
     assert "decoded_block_type_shadow = 0b1101;" in tepl_body
 
 
+def test_decode32_dispatch_is_partitioned_by_exact_opcode() -> None:
+    spec = _load_spec()
+    retired = _load_retired()
+    execute_text = (ROOT / "isa/sail/model/execute/execute.sail").read_text(encoding="utf-8")
+    rendered = gen_sail_decode.render(spec, execute_text, "isa/v0.57/linxisa-v0.57.json", retired)
+
+    assert "function decode_execute32_opcode_0b0001011" in rendered
+    assert "function decode_execute32_opcode_0b0001011_funct3_0b010" in rendered
+    assert "function decode_execute32_opcode_0b0001011_funct3_0b010_match_0" in rendered
+    assert "match inst[6..0]" in rendered
+    assert "match inst[14..12]" in rendered
+    assert "0b0001011 => decode_execute32_opcode_0b0001011(inst)" in rendered
+
+    assert "and_bool_no_flow" in rendered
+
+    dispatcher = rendered[rendered.index("function decode_execute32(inst") :]
+    reserved_pos = dispatcher.index("(inst & 0x06007fff) == 0x02001181")
+    wildcard_pos = dispatcher.index("// BSTART CALL |")
+    match_pos = dispatcher.index("match inst[6..0]")
+    assert reserved_pos < wildcard_pos < match_pos
+
+
 def test_malformed_canonical_redecode_metadata_fails_closed() -> None:
     bad = {"entries": [{"disposition": "canonical-redecode", "length_bits": 32}]}
     try:
@@ -135,9 +149,10 @@ def test_ambiguous_canonical_redecode_metadata_fails_closed() -> None:
 
 def main() -> int:
     tests = [
-        test_tepl_canonical_redecode_precedes_broad_overlaps,
-        test_tepl_canonical_redecode_is_deterministic,
-        test_tepl_canonical_redecode_render_selects_tepl_first,
+        test_tepl_mode_function_decode_precedes_broad_overlaps,
+        test_tepl_mode_function_decode_is_deterministic,
+        test_tepl_mode_function_decode_render_selects_tepl_first,
+        test_decode32_dispatch_is_partitioned_by_exact_opcode,
         test_malformed_canonical_redecode_metadata_fails_closed,
         test_unresolved_canonical_redecode_metadata_fails_closed,
         test_ambiguous_canonical_redecode_metadata_fails_closed,
diff --git a/tools/isa/test_golden_contract.py b/tools/isa/test_golden_contract.py
index d4e1b1f8..ff7946fd 100644
--- a/tools/isa/test_golden_contract.py
+++ b/tools/isa/test_golden_contract.py
@@ -63,7 +63,7 @@ def main() -> int:
     spec = json.loads((ROOT / "isa/v0.57/linxisa-v0.57.json").read_text(encoding="utf-8"))
     instructions = spec["instructions"]
     mnemonics = {str(inst["mnemonic"]) for inst in instructions}
-    assert spec["version"] == "0.57.0"
+    assert spec["version"] == "0.57.1"
     assert "B.IOD" not in mnemonics
     assert "BSTART.PAR" not in mnemonics
     assert {
@@ -84,7 +84,8 @@ def main() -> int:
 
     retired = {entry["retired_mnemonic"]: entry for entry in spec["retired_encodings"]["entries"]}
     assert retired["B.IOD"]["disposition"] == "reserved"
-    assert retired["BSTART.PAR"]["replacement_mnemonic"] == "BSTART.TEPL"
+    assert retired["BSTART.PAR"]["disposition"] == "reserved"
+    assert "replacement_mnemonic" not in retired["BSTART.PAR"]
 
     exact_calls = [
         inst
@@ -133,12 +134,9 @@ def main() -> int:
             assert isinstance(definition["reserved_values"], list), name
     assert field_source["fields"]["reserve"]["allowed_values"] == [0]
     assert field_source["fields"]["reserve"]["documented_only"] is True
-    assert field_source["fields"]["TileOpcode"]["reserved_ranges"] == [
-        [73, 127],
-        [140, 191],
-        [201, 223],
-        [228, 1023],
-    ]
+    assert "TileOpcode" not in field_source["fields"]
+    assert field_source["fields"]["Mode"]["widths"] == [2]
+    assert field_source["fields"]["Function"]["widths"] == [5]
 
     tma = spec["state"]["engine_ops"]["tma"]
     assert tma["function_field_bits"] == [0, 4]
@@ -188,7 +186,10 @@ def main() -> int:
     }
     assert "reserve" not in observed_fields
     b_catr = next(inst for inst in instructions if inst["mnemonic"] == "B.CATR")
-    assert int(b_catr["encoding"]["parts"][0]["mask"], 0) == 0x03FFFFFF
+    assert (
+        int(b_catr["encoding"]["parts"][0]["mask"], 0),
+        int(b_catr["encoding"]["parts"][0]["match"], 0),
+    ) == (0xFBF07FFF, 0x00000023)
     trace_hint = next(inst for inst in instructions if inst["asm"] == "B.HINT TRACE.{begin, end}")
     assert int(trace_hint["encoding"]["parts"][0]["mask"], 0) == 0xFFFF7FFF
 
diff --git a/tools/isa/test_v057_profile.py b/tools/isa/test_v057_profile.py
index 80dc4a19..5b1dcfd8 100644
--- a/tools/isa/test_v057_profile.py
+++ b/tools/isa/test_v057_profile.py
@@ -125,74 +125,23 @@ def main() -> int:
             word = (dtype << 27) | (function << 20) | cube_base
             matches = sorted(name for name, mask, match in one_part_32 if word & mask == match)
             if function in expected_cube:
-                assert matches == sorted(["BSTART.CUBE", expected_cube[function]]), (dtype, function, matches)
+                assert matches == [expected_cube[function]], (dtype, function, matches)
             else:
-                assert matches == ["BSTART.CUBE"], (dtype, function, matches)
+                assert matches == [], (dtype, function, matches)
 
+    tepl_ops = v057["state"]["engine_ops"]["tepl"]["ops"]
     v057_tepl = {
-        op["name"]: int(op["tile_opcode"])
-        for op in v057["state"]["engine_ops"]["tepl"]["ops"]
-    }
-    expected_new_tepl = {
-        "TCMP": 0x02B,
-        "TSEL": 0x02C,
-        "TABS": 0x02D,
-        "TNOT": 0x02E,
-        "TNEG": 0x02F,
-        "TREM": 0x030,
-        "TAXPY": 0x031,
-        "TREMS": 0x032,
-        "TCMPS": 0x033,
-        "TSELS": 0x034,
-        "TROWPROD": 0x035,
-        "TROWARGMAX": 0x036,
-        "TROWARGMIN": 0x037,
-        "TCOLPROD": 0x038,
-        "TCOLARGMAX": 0x039,
-        "TCOLARGMIN": 0x03A,
-        "TROWEXPANDADD": 0x03B,
-        "TROWEXPANDSUB": 0x03C,
-        "TROWEXPANDMUL": 0x03D,
-        "TROWEXPANDDIV": 0x03E,
-        "TROWEXPANDMAX": 0x03F,
-        "TROWEXPANDMIN": 0x040,
-        "TROWEXPANDEXPDIF": 0x041,
-        "TCOLEXPANDADD": 0x042,
-        "TCOLEXPANDSUB": 0x043,
-        "TCOLEXPANDMUL": 0x044,
-        "TCOLEXPANDDIV": 0x045,
-        "TCOLEXPANDMAX": 0x046,
-        "TCOLEXPANDMIN": 0x047,
-        "TCOLEXPANDEXPDIF": 0x048,
-        "TCI": 0x080,
-        "TTRI": 0x081,
-        "TFILLPAD": 0x082,
-        "TQUANT": 0x083,
-        "TDEQUANT": 0x084,
-        "TEXTRACT": 0x085,
-        "TINSERT": 0x086,
-        "TCONCAT": 0x087,
-        "TIMG2COL": 0x088,
-        "TGATHERB": 0x089,
-        "TDEINTERLEAVE": 0x08A,
-        "TINTERLEAVE": 0x08B,
-        "TSORT": 0x0C0,
-        "TMRGSORT": 0x0C1,
-        "THISTOGRAM": 0x0C2,
-        "TPARTADD": 0x0C3,
-        "TPARTMUL": 0x0C4,
-        "TPARTMAX": 0x0C5,
-        "TPARTMIN": 0x0C6,
-        "TPARTARGMAX": 0x0C7,
-        "TPARTARGMIN": 0x0C8,
-        "TPUSH": 0x0E0,
-        "TPOP": 0x0E1,
-        "TALLOC": 0x0E2,
-        "TFREE": 0x0E3,
+        op["name"]: (op["mode"], op["function"], op["logical_selector"])
+        for op in tepl_ops
     }
-    for name, selector in expected_new_tepl.items():
-        assert v057_tepl[name] == selector
-    assert {"TFMOD", "TPOW", "TRANDOM", "TEXRACT"} & set(v057_tepl) == set()
+    assert len(v057_tepl) == 98
+    assert len({selector for _, _, selector in v057_tepl.values()}) == 98
+    for mode, function, selector in v057_tepl.values():
+        assert selector == (mode << 5) | function
+    assert {
+        "TADDC", "TADDSC", "TFMA", "TFMOD", "TFMODS", "TLRELU",
+        "TRANDOM", "TSUBC", "TSUBSC", "TTRANSPOSE", "TSORT32",
+    } & set(v057_tepl) == set()
 
     frame = v057["semantics_conventions"]["frame_templates_r975"]
     assert frame["step_index"]["meaning"] == "next_uncommitted_phase_one_event"
diff --git a/tools/isa/validate_spec.py b/tools/isa/validate_spec.py
index f7424cd7..e7e280c9 100755
--- a/tools/isa/validate_spec.py
+++ b/tools/isa/validate_spec.py
@@ -233,6 +233,61 @@ def _validate_v057_tepl_extensions(tepl: Dict[str, Any], selector_by_name: Dict[
         errors.append("state.engine_ops.tepl.extension_policy_v057.reserved_selector_ranges do not match the frozen v0.57 map")
 
 
+def _validate_engine_ops_v0571(spec: Dict[str, Any], engine_ops: Dict[str, Any], errors: List[str]) -> None:
+    """Validate the PTO 0.57.1 projection without retaining pre-0.57.1 ABI rules."""
+    tepl = engine_ops.get("tepl", {})
+    ops = tepl.get("ops", []) if isinstance(tepl, dict) else []
+    if tepl.get("kind") != "mode_function":
+        errors.append("state.engine_ops.tepl.kind must be mode_function")
+    if tepl.get("selector_formula") != "(mode << 5) | function":
+        errors.append("state.engine_ops.tepl.selector_formula must be (mode << 5) | function")
+    if tepl.get("accepted_selector_count") != 98 or len(ops) != 98:
+        errors.append("state.engine_ops.tepl must contain exactly 98 accepted operations")
+    selectors: Dict[int, str] = {}
+    forbidden = {"TADDC", "TADDSC", "TFMA", "TFMOD", "TFMODS", "TLRELU", "TRANDOM", "TSUBC", "TSUBSC", "TTRANSPOSE", "TSORT32"}
+    for idx, op in enumerate(ops):
+        name = str(op.get("name") or "")
+        mode, function = op.get("mode"), op.get("function")
+        if not isinstance(mode, int) or not 0 <= mode <= 3 or not isinstance(function, int) or not 0 <= function <= 31:
+            errors.append(f"state.engine_ops.tepl.ops[{idx}] has invalid Mode/Function")
+            continue
+        selector = (mode << 5) | function
+        if op.get("logical_selector") != selector:
+            errors.append(f"state.engine_ops.tepl.ops[{idx}] logical_selector does not match Mode/Function")
+        if selector in selectors:
+            errors.append(f"state.engine_ops.tepl selector {selector:#04x} is shared by {selectors[selector]} and {name}")
+        selectors[selector] = name
+        if op.get("semantic_status") != "reviewed-complete":
+            errors.append(f"state.engine_ops.tepl.ops[{idx}] is not reviewed-complete")
+    leaked = sorted(forbidden & {str(op.get("name")) for op in ops})
+    if leaked:
+        errors.append(f"deleted or migration-only TEPL names leaked: {leaked}")
+
+    expected = {
+        "tma": set(range(9)),
+        "cube": {0, 1, 2, 4, 5, 6, 8, 16, 17, 18, 20, 21, 22},
+    }
+    for family, functions in expected.items():
+        state = engine_ops.get(family, {})
+        actual = {int(item["function"]) for item in state.get("legal_aliases", [])}
+        if actual != functions:
+            errors.append(f"state.engine_ops.{family} functions differ from PTO ISA 0.57.1")
+    if engine_ops.get("cube", {}).get("unassigned_function_behavior") != "illegal_instruction":
+        errors.append("state.engine_ops.cube unassigned functions must be illegal_instruction")
+
+    instructions = spec.get("instructions", [])
+    mnemonics = {str(item.get("mnemonic") or "") for item in instructions}
+    if "BSTART.CUBE" in mnemonics:
+        errors.append("generic BSTART.CUBE must not be a legal decode in PTO ISA 0.57.1")
+    tepl_forms = [item for item in instructions if item.get("mnemonic") == "BSTART.TEPL"]
+    if len(tepl_forms) != 1:
+        errors.append("PTO ISA 0.57.1 requires exactly one BSTART.TEPL form")
+    else:
+        part = tepl_forms[0].get("encoding", {}).get("parts", [{}])[0]
+        if (int(part.get("mask", "0"), 0), int(part.get("match", "0"), 0)) != (0x000FFFFF, 0x00019181):
+            errors.append("BSTART.TEPL must use the PTO ISA 0.57.1 Mode/Function encoding")
+
+
 def _validate_engine_ops(spec: Dict[str, Any], errors: List[str]) -> None:
     state = spec.get("state")
     if not isinstance(state, dict):
@@ -245,6 +300,10 @@ def _validate_engine_ops(spec: Dict[str, Any], errors: List[str]) -> None:
         errors.append("state.engine_ops must be a mapping")
         return
 
+    if str(spec.get("version") or "") == "0.57.1":
+        _validate_engine_ops_v0571(spec, engine_ops, errors)
+        return
+
     tma = engine_ops.get("tma")
     version = str(spec.get("version") or "")
     is_v057 = version.startswith("0.57")
diff --git a/tools/model b/tools/model
index 3ca25e05..f6e75480 160000
--- a/tools/model
+++ b/tools/model
@@ -1 +1 @@
-Subproject commit 3ca25e05d2a2571ab9f54eab7c9891a3c214c5de
+Subproject commit f6e7548082732c274a3936e5cf0db282171866e5
diff --git a/tools/pyCircuit b/tools/pyCircuit
index cc020392..84b40281 160000
--- a/tools/pyCircuit
+++ b/tools/pyCircuit
@@ -1 +1 @@
-Subproject commit cc0203928b0c078468f2549a2477f891a17552e0
+Subproject commit 84b40281c60ad208a5d2f1b4d03f50ad52a6262c
diff --git a/tools/spec2017/run_int_rate_qemu.py b/tools/spec2017/run_int_rate_qemu.py
index 0e542d64..8db5056c 100755
--- a/tools/spec2017/run_int_rate_qemu.py
+++ b/tools/spec2017/run_int_rate_qemu.py
@@ -1256,8 +1256,9 @@ def _qemu_fentry_trace_from_args(args: argparse.Namespace) -> dict[str, str]:
     return trace
 
 
-def _find_gen_init_cpio(linux_root: Path, out_dir: Path) -> Path:
+def _find_gen_init_cpio(linux_root: Path, out_dir: Path, kernel: Path | None = None) -> Path:
     cands = [
+        *(([kernel.parent / "usr" / "gen_init_cpio"]) if kernel is not None else []),
         linux_root / "build-linx-fixed" / "usr" / "gen_init_cpio",
         linux_root / "usr" / "gen_init_cpio",
     ]
@@ -6242,7 +6243,7 @@ def main(argv: list[str]) -> int:
     started_at_utc = _utc_now()
     start_wall = time.monotonic()
 
-    gen_init_cpio = _find_gen_init_cpio(linux_root, out_dir)
+    gen_init_cpio = _find_gen_init_cpio(linux_root, out_dir, kernel)
     if args.stage == "a":
         benches = args.bench if args.bench else STAGE_A_BENCHES
     else:
diff --git a/tools/spec2017/test_run_int_rate_qemu.py b/tools/spec2017/test_run_int_rate_qemu.py
index 5e1a6e72..b333d736 100644
--- a/tools/spec2017/test_run_int_rate_qemu.py
+++ b/tools/spec2017/test_run_int_rate_qemu.py
@@ -62,6 +62,24 @@ def test_default_qemu_honors_qemu_env_override(self) -> None:
                 str((Path(td) / "custom-qemu").resolve()),
             )
 
+    def test_gen_init_cpio_prefers_kernel_build_output(self) -> None:
+        with tempfile.TemporaryDirectory() as td:
+            root = Path(td)
+            linux_root = root / "linux"
+            out_dir = root / "spec-out"
+            kernel = root / "linux-build" / "vmlinux"
+            external_tool = kernel.parent / "usr" / "gen_init_cpio"
+            in_tree_tool = linux_root / "build-linx-fixed" / "usr" / "gen_init_cpio"
+            external_tool.parent.mkdir(parents=True)
+            in_tree_tool.parent.mkdir(parents=True)
+            external_tool.touch()
+            in_tree_tool.touch()
+
+            self.assertEqual(
+                runner._find_gen_init_cpio(linux_root, out_dir, kernel),
+                external_tool,
+            )
+
     def test_child_exit_failure_evidence_includes_wait_status(self) -> None:
         result = runner._classify_qemu_result(
             text=(
diff --git a/workloads/SuperNPUBench b/workloads/SuperNPUBench
index f259866f..fbad00f1 160000
--- a/workloads/SuperNPUBench
+++ b/workloads/SuperNPUBench
@@ -1 +1 @@
-Subproject commit f259866ff9f463eddb7dc41a39fdaaeb04eacbcf
+Subproject commit fbad00f1f66fc4290d33372bb83b149ee944834a
diff --git a/workloads/pto_kernels b/workloads/pto_kernels
index 0eb72cb2..13d55d91 160000
--- a/workloads/pto_kernels
+++ b/workloads/pto_kernels
@@ -1 +1 @@
-Subproject commit 0eb72cb20b0de99326d984a9a27ddb815e6e4c24
+Subproject commit 13d55d9106f6cdb97ce4e5e5c3ccf376f0e7b34d