diff --git a/.codespellrc b/.codespellrc new file mode 100644 index 00000000000..2ea390ce8b9 --- /dev/null +++ b/.codespellrc @@ -0,0 +1,3 @@ +[codespell] +exclude-file = .codespellx +ignore-words-list = "FPT,FTP,fpt,ftp" diff --git a/.codespellx b/.codespellx new file mode 100644 index 00000000000..e69de29bb2d diff --git a/.conform.yaml b/.conform.yaml new file mode 100644 index 00000000000..f96e4e09406 --- /dev/null +++ b/.conform.yaml @@ -0,0 +1,16 @@ +--- +policies: + - type: commit + spec: + header: + length: 80 + imperative: false + invalidLastCharacters: . + body: + required: false + dco: true + gpg: + required: true + spellcheck: + locale: US + maximumOfOneCommit: false diff --git a/.github/scripts/capsule-lint.sh b/.github/scripts/capsule-lint.sh new file mode 100755 index 00000000000..4e1aef0351b --- /dev/null +++ b/.github/scripts/capsule-lint.sh @@ -0,0 +1,87 @@ +#!/bin/bash + +function get_str() { + local cfg=$1 + local name=$2 + sed -n 's/^'"$name"'="\(.*\)"$/\1/p' "$cfg" +} + +function get_hex() { + local cfg=$1 + local name=$2 + sed -n 's/^'"$name"'=\(.*\)$/\1/p' "$cfg" +} + +function hex_to_ver_str() { + local hex=$1 + + local major=${hex:2:2} + local minor=${hex:4:2} + local bugfix=${hex:6:2} + local rc=${hex:8:2} + + local ver="v$((0x$major)).$((0x$minor)).$((0x$bugfix))" + if [ "$((0x$rc))" -lt 128 ]; then + ver="$ver-rc$((rc))" + fi + echo "$ver" +} + +if [ ! -d configs ]; then + echo "error: $(basename "$0") should be run from the root of coreboot's tree" + exit 1 +fi + +declare -A guids +fail=0 + +mapfile -t configs < <(grep -l 'EFI_UPDATE_CAPSULE' configs/config.*) +for c in "${configs[@]}"; do + local_ver=$(get_str "$c" 'CONFIG_LOCALVERSION') + + guid=$(get_str "$c" 'CONFIG_DRIVERS_EFI_MAIN_FW_GUID') + ver=$(get_hex "$c" 'CONFIG_DRIVERS_EFI_MAIN_FW_VERSION') + lsv=$(get_hex "$c" 'CONFIG_DRIVERS_EFI_MAIN_FW_LSV') + + # convert to lower case as normalization + guid=${guid,,*} + # remove common prefix to shorten error messages + c=${c##*/} + + if [ -z "$guid" ]; then + echo "$c: missing CONFIG_DRIVERS_EFI_MAIN_FW_GUID" + fail=1 + elif [ -n "${guids["$guid"]}" ]; then + echo "$c: duplicated CONFIG_DRIVERS_EFI_MAIN_FW_GUID value ($guid)" + echo "${c//?/ } also appears in ${guids["$guid"]}" + fail=1 + else + guids["$guid"]=$c + fi + + if [ -z "$ver" ]; then + echo "$c: missing CONFIG_DRIVERS_EFI_MAIN_FW_VERSION" + fail=1 + fi + if [ -z "$lsv" ]; then + echo "$c: missing CONFIG_DRIVERS_EFI_MAIN_FW_LSV" + fail=1 + fi + + if [ -n "$ver" ] && [ -n "$lsv" ] && [ $(( ver < lsv )) -eq 1 ]; then + echo "$c: CONFIG_DRIVERS_EFI_MAIN_FW_VERSION < CONFIG_DRIVERS_EFI_MAIN_FW_LSV" + echo "${c//?/ } $ver < $lsv" + fail=1 + fi + + if [ -n "$ver" ]; then + str_ver=$(hex_to_ver_str "$ver") + if [ "$str_ver" != "$local_ver" ]; then + echo "$c: CONFIG_LOCALVERSION doesn't match CONFIG_DRIVERS_EFI_MAIN_FW_VERSION" + echo "${c//?/ } $local_ver != $str_ver ($ver)" + fail=1 + fi + fi +done + +exit "$fail" diff --git a/.github/workflows/build.yml b/.github/workflows/build.yml new file mode 100644 index 00000000000..416ffc50974 --- /dev/null +++ b/.github/workflows/build.yml @@ -0,0 +1,460 @@ +name: Dasharo +on: + pull_request: + branches: + - dasharo + push: + branches: + - dasharo-24.12 + tags: + - '*' + +jobs: + build_novacustom_ec: + runs-on: ubuntu-22.04 + strategy: + matrix: + vendor: [ novacustom ] + model: [ nv4x_adl, ns5x_adl, nv4x_tgl, ns5x_tgl, v540tu, v560tu, v540tnx, v560tnx ] + steps: + - name: Checkout EC + uses: actions/checkout@v4 + with: + repository: Dasharo/ec + - name: Build EC + run: EC_BOARD_VENDOR=${{ matrix.vendor }} EC_BOARD_MODEL=${{ matrix.model }} ./build.sh + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-ec" + path: | + ${{ matrix.vendor }}_${{ matrix.model }}_ec.rom + retention-days: 30 + build_novacustom: + runs-on: ubuntu-22.04 + needs: build_novacustom_ec + container: + image: coreboot/coreboot-sdk:2023-11-24_2731fa619b + options: --user 1001 + strategy: + matrix: + vendor: [ novacustom ] + model: [ nv4x_adl, ns5x_adl, nv4x_tgl, ns5x_tgl, v540tu, v560tu, v540tnx, v560tnx ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Obtain EC + uses: actions/download-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-ec" + - name: Obtain blobs + uses: actions/checkout@v4 + with: + repository: Dasharo/novacustom-blobs + ref: 480afdc3d15bb9ec5b72b100581badea11e779f8 + path: 3rdparty/blobs/mainboard + token: ${{ secrets.NCM_BLOBS_TOKEN }} + - name: Build Dasharo + run: | + mv ${{ matrix.vendor }}_${{ matrix.model }}_ec.rom ec.rom + cp configs/config.${{ matrix.vendor }}_${{ matrix.model }} .config + make olddefconfig + make + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + retention-days: 30 + build_optiplex: + runs-on: ubuntu-22.04 + container: + image: coreboot/coreboot-sdk:2023-11-24_2731fa619b + options: --user 1001 + strategy: + matrix: + vendor: [ dell ] + model: [ optiplex_9010_sff, optiplex_9010_sff_uefi ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + cp configs/config.${{ matrix.vendor }}_${{ matrix.model }}_txt .config + make olddefconfig + make + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + retention-days: 30 + build_msi: + runs-on: ubuntu-22.04 + container: + image: coreboot/coreboot-sdk:2023-11-24_2731fa619b + options: --user 1001 + strategy: + matrix: + vendor: [ msi ] + model: [ ms7d25_ddr4, ms7d25_ddr5, ms7e06_ddr4, ms7e06_ddr5 ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + cp configs/config.${{ matrix.vendor }}_${{ matrix.model }} .config + make olddefconfig + make + pkcs7sign=payloads/external/edk2/workspace/Dasharo/BaseTools/Source/Python/Pkcs7Sign + ./capsule.sh make -t "$pkcs7sign"/TestRoot.pub.pem \ + -o "$pkcs7sign"/TestSub.pub.pem \ + -s "$pkcs7sign"/TestCert.pem + mv *.cap build/coreboot.cap + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + build/coreboot.cap + retention-days: 30 + build_protectli: + runs-on: ubuntu-22.04 + strategy: + matrix: + vendor: [ protectli ] + model: [ vp66xx, vp46xx, vp32xx, vp2430, vp2420, vp2410, V1210, V1211, V1410, V1610 ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + ./build.sh ${{ matrix.model }} + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + retention-days: 30 + build_pcengines: + runs-on: ubuntu-22.04 + container: + image: coreboot/coreboot-sdk:2023-11-24_2731fa619b + options: --user 1001 + strategy: + matrix: + vendor: [ pcengines ] + model: [ apu2, apu3, apu4, apu6 ] + payload: [ uefi ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + cp configs/config.${{ matrix.vendor }}_${{ matrix.payload }}_${{ matrix.model }} .config + make olddefconfig + make + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.payload }}" + path: | + build/coreboot.rom + retention-days: 30 + build_q35: + runs-on: ubuntu-22.04 + container: + image: coreboot/coreboot-sdk:2023-11-24_2731fa619b + options: --user 1001 + strategy: + matrix: + vendor: [ emulation_qemu ] + model: [ x86_q35 ] + payload: [ uefi, uefi_all_menus ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Build Dasharo + run: | + cp configs/config.${{ matrix.vendor }}_${{ matrix.model }}_${{ matrix.payload }} .config + make olddefconfig + make + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.payload }}" + path: | + build/coreboot.rom + retention-days: 30 + build_hardkernel_odroid_h4: + runs-on: ubuntu-22.04 + container: + image: coreboot/coreboot-sdk:2024-02-18_732134932b + options: --user 1001 + strategy: + matrix: + vendor: [ hardkernel ] + model: [ odroid_h4 ] + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Fetch complete history + fetch-depth: 0 + - name: Checkout all submodules + run: git submodule update --init --recursive --checkout + - name: Build Dasharo + run: | + cp configs/config.${{ matrix.vendor }}_${{ matrix.model }} .config + make olddefconfig + make + - name: Save artifacts + uses: actions/upload-artifact@v4 + with: + name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + path: | + build/coreboot.rom + retention-days: 30 + + deploy_protectli_adl: + if: startsWith(github.ref, 'refs/tags/protectli_vault_adl_') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp66xx ] + deploy_protectli_adl_n: + if: startsWith(github.ref, 'refs/tags/protectli_vault_adln_') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp32xx ] + deploy_protectli_vp2430: + if: startsWith(github.ref, 'refs/tags/protectli_vp2430_') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp2430 ] + deploy_protectli_jsl: + if: startsWith(github.ref, 'refs/tags/protectli_vault_jsl') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ V1210, V1211, V1410, V1610 ] + deploy_protectli_glk: + if: startsWith(github.ref, 'refs/tags/protectli_vault_glk') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp2410 ] + deploy_protectli_ehl: + if: startsWith(github.ref, 'refs/tags/protectli_vault_ehl') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp2420 ] + deploy_protectli_cml: + if: startsWith(github.ref, 'refs/tags/protectli_vault_cml') + needs: build_protectli + uses: ./.github/workflows/deploy-template.yml + with: + platform: protectli + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ protectli ] + model: [ vp46xx ] + deploy_novacustom_adl: + if: startsWith(github.ref, 'refs/tags/novacustom') && contains(github.ref, 'adl') + needs: build_novacustom + uses: ./.github/workflows/deploy-template.yml + with: + platform: novacustom + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ novacustom ] + model: [ nv4x_adl, ns5x_adl ] + deploy_novacustom_tgl: + if: startsWith(github.ref, 'refs/tags/novacustom') && contains(github.ref, 'tgl') + needs: build_novacustom + uses: ./.github/workflows/deploy-template.yml + with: + platform: novacustom + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + secrets: inherit + strategy: + matrix: + vendor: [ novacustom ] + model: [ nv4x_tgl, ns5x_tgl ] + deploy_pcengines: + if: startsWith(github.ref, 'refs/tags/pcengines') + needs: build_pcengines + uses: ./.github/workflows/deploy-template.yml + with: + platform: pcengines + vendor: ${{ matrix.vendor }} + model: ${{ matrix.model }} + payload: ${{ matrix.payload }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}-${{ matrix.payload }}" + secrets: inherit + strategy: + matrix: + vendor: [ pcengines ] + model: [ apu2, apu3, apu4, apu6 ] + payload: [ uefi ] + deploy_msi_ms7d25: + if: startsWith(github.ref, 'refs/tags/msi_ms7d25') + needs: build_msi + uses: ./.github/workflows/deploy-template.yml + with: + platform: msi + vendor: ${{ matrix.vendor }} + model: "ms7d25" + type: ${{ matrix.type }} + artifact_name: "dasharo-${{ matrix.vendor }}-ms7d25_${{ matrix.type }}" + released_by_3mdeb: true + secrets: inherit + strategy: + matrix: + vendor: [ msi ] + type: [ ddr4, ddr5 ] + deploy_msi_ms7e06: + if: startsWith(github.ref, 'refs/tags/msi_ms7e06') + needs: build_msi + uses: ./.github/workflows/deploy-template.yml + with: + platform: msi + vendor: ${{ matrix.vendor }} + model: "ms7e06" + type: ${{ matrix.type }} + artifact_name: "dasharo-${{ matrix.vendor }}-ms7e06_${{ matrix.type }}" + released_by_3mdeb: true + secrets: inherit + strategy: + matrix: + vendor: [ msi ] + type: [ ddr4, ddr5 ] + deploy_hardkernel_odroid: + if: startsWith(github.ref, 'refs/tags/hardkernel_odroid_h4') + needs: build_hardkernel_odroid_h4 + uses: ./.github/workflows/deploy-template.yml + with: + platform: hardkernel + model: ${{ matrix.model }} + vendor: ${{ matrix.model }} + artifact_name: "dasharo-${{ matrix.vendor }}-${{ matrix.model }}" + released_by_3mdeb: true + secrets: inherit + strategy: + matrix: + vendor: [ hardkernel ] + model: [ odroid_h4 ] diff --git a/.github/workflows/code-checks.yml b/.github/workflows/code-checks.yml new file mode 100644 index 00000000000..464f92d4c33 --- /dev/null +++ b/.github/workflows/code-checks.yml @@ -0,0 +1,49 @@ +name: Dasharo Checks +on: + push: + +jobs: + lint: + runs-on: ubuntu-22.04 + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Top commit is enough + fetch-depth: 1 + - name: Standard lint tests + run: util/lint/lint lint-stable + - name: Extended lint tests + run: util/lint/lint lint-extended + check-defconfigs: + runs-on: ubuntu-22.04 + steps: + - name: Checkout repository + uses: actions/checkout@v4 + with: + # Checkout pull request HEAD commit instead of merge commit + # See: https://github.com/actions/checkout#checkout-pull-request-head-commit-instead-of-merge-commit + ref: ${{ github.event.pull_request.head.sha }} + # Top commit is enough + fetch-depth: 1 + - name: Verify defconfigs are up-to-date + run: | + # Start with the list of Dasharo boards that use EDK + boards=( $(grep -l 'Dasharo/edk2\(\.git\)\?"' configs/config.*) ) + # Add non-EDK boards + boards+=( configs/config.dell_optiplex_9010_sff_txt ) + boards+=( configs/config.protectli_vp46xx_txt_seabios ) + + # Update all of them before reporting anything + for c in $(printf "%s\n" "${boards[@]}" | sort); do + make savedefconfig DOTCONFIG="$c" + mv defconfig "$c" + done + + # Print all the differences at once and fail or do nothing + git diff --exit-code + - name: Verify update capsules support in defconfigs + run: .github/scripts/capsule-lint.sh diff --git a/.github/workflows/deploy-template.yml b/.github/workflows/deploy-template.yml new file mode 100644 index 00000000000..0c940bfd42f --- /dev/null +++ b/.github/workflows/deploy-template.yml @@ -0,0 +1,96 @@ +name: Reusable Deploy workflow +on: + workflow_call: + inputs: + platform: + type: string + vendor: + type: string + required: false + model: + type: string + required: false + payload: + type: string + required: false + type: + type: string + required: false + artifact_name: + type: string + # Set to true for DPP/community releases by 3mdeb + released_by_3mdeb: + type: boolean + +jobs: + deploy: + runs-on: ubuntu-22.04 + steps: + - name: Checkout repository + uses: actions/checkout@v4 + + - name: Set up tag name + id: tag_name + run: echo "tag=${GITHUB_REF#refs/tags/}" >> "$GITHUB_OUTPUT" + + - name: Parse directories + id: parse_directories + run: | + + tag=${{ steps.tag_name.outputs.tag }} + # Extract platform model string (everything before the last underscore in the tag) + model=$(echo "$tag" | awk -F'_' '{OFS="_"; $(NF)=""; print $0}' | sed 's/_$//') + # Extract version string (everything after the last underscore in the tag) + release=$(echo "$tag" | awk -F'_' '{print $NF}') + + # Use 3mdeb directory for community / DPP releases + if ${{ inputs.released_by_3mdeb }} ; then + base_dir="3mdeb" + else + # by default, use platform vendor name as a directory + base_dir="${{ inputs.platform }}" + fi + + echo "base_dir=$base_dir" >> "$GITHUB_OUTPUT" + echo "model=$model" >> "$GITHUB_OUTPUT" + echo "release=$release" >> "$GITHUB_OUTPUT" + + - name: Download workflow artifact + uses: actions/download-artifact@v4 + with: + name: ${{ inputs.artifact_name }} + path: "./artifacts" + + - name: Upload to Nextcloud + run: | + BASE_URL="https://cloud.3mdeb.com/public.php/webdav" + url_part=$(echo "${{ secrets.CLOUD_URL }}" | cut -d'/' -f6) + base_dir="${{ steps.parse_directories.outputs.base_dir }}" + model="${{ steps.parse_directories.outputs.model }}" + release="${{ steps.parse_directories.outputs.release }}" + CURL_CMD="curl -u $url_part:${{ secrets.CLOUD_PASSWORD }}" + + if [ "${{ inputs.platform }}" == "pcengines" ]; then + new_name="pcengines_${{ inputs.model }}_${release}.rom" + else + new_name="${{ inputs.model }}_${release}.rom" + if [ ! -z "${{ inputs.vendor }}" ]; then + new_name="${{ inputs.vendor }}_${new_name}" + fi + if [ ! -z "${{ inputs.payload }}" ]; then + new_name=$(echo "$new_name" | awk -F'_' '{OFS="_"; $NF="${{ inputs.payload }}_"$NF; print}') + fi + if [ ! -z "${{ inputs.type }}" ]; then + new_name=$(echo "${new_name%.rom}_${{ inputs.type }}.rom") + fi + fi + + # Create release directory if it doesn't exist + $CURL_CMD -X MKCOL "$BASE_URL/$base_dir" + $CURL_CMD -X MKCOL "$BASE_URL/$base_dir/$model" + $CURL_CMD -X MKCOL "$BASE_URL/$base_dir/$model/$release" + + # upload firmware and hash files + $CURL_CMD -X PUT -T "artifacts/coreboot.rom" "$BASE_URL/$base_dir/$model/$release/$new_name" + sha256sum artifacts/coreboot.rom > ${new_name}.sha256 + $CURL_CMD -X PUT -T "${new_name}.sha256" "$BASE_URL/$base_dir/$model/$release/" diff --git a/.gitignore b/.gitignore index e813493526f..5cd280c8d7b 100644 --- a/.gitignore +++ b/.gitignore @@ -26,6 +26,7 @@ site-local *.pyc *.sw[po] /*.rom +*.rom.sha256 .test .dependencies diff --git a/.gitmodules b/.gitmodules index c1d7849a9e9..300e11a6457 100644 --- a/.gitmodules +++ b/.gitmodules @@ -68,3 +68,6 @@ [submodule "3rdparty/open-power-signing-utils"] path = 3rdparty/open-power-signing-utils url = https://review.coreboot.org/open-power-signing-utils.git +[submodule "3rdparty/dasharo-blobs"] + path = 3rdparty/dasharo-blobs + url = https://github.com/Dasharo/dasharo-blobs.git diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml new file mode 100644 index 00000000000..f0464484cb6 --- /dev/null +++ b/.pre-commit-config.yaml @@ -0,0 +1,46 @@ +--- +default_stages: [pre-commit] + +default_install_hook_types: [pre-commit, commit-msg] + +ci: + autoupdate_commit_msg: 'pre-commit: autoupdate hooks' + autofix_prs: false + +repos: + - repo: https://github.com/pre-commit/pre-commit-hooks + rev: v4.4.0 + hooks: + - id: check-added-large-files + - id: check-merge-conflict + - id: check-symlinks + - id: detect-private-key + # Consider re-enabling (a lot of coreboot code is affected, but with + # vendorcode excluded is much less) + # - id: end-of-file-fixer + # exclude: "src/vendorcode" + # - id: trailing-whitespace + # exclude: "src/vendorcode" + - id: mixed-line-ending + + - repo: https://github.com/talos-systems/conform + rev: v0.1.0-alpha.27 + hooks: + - id: conform + stages: + - commit-msg + + # Consider re-enabling (a lot of coreboot code is affected, but with + # vendorcode excluded it is much less) + # - repo: https://github.com/codespell-project/codespell + # rev: v2.2.5 + # hooks: + # - id: codespell + + - repo: local + hooks: + - id: coreboot_lint + name: Runs coreboot lint-stable linter checks + entry: util/lint/lint lint-stable + language: script + types: [file] diff --git a/3rdparty/dasharo-blobs b/3rdparty/dasharo-blobs new file mode 160000 index 00000000000..a337f0e9400 --- /dev/null +++ b/3rdparty/dasharo-blobs @@ -0,0 +1 @@ +Subproject commit a337f0e94003d9d721d14a694273a3512667b565 diff --git a/3rdparty/fsp b/3rdparty/fsp index 851f7105d80..86c9111639d 160000 --- a/3rdparty/fsp +++ b/3rdparty/fsp @@ -1 +1 @@ -Subproject commit 851f7105d803672e17202bc2f598a5a4dbf659d3 +Subproject commit 86c9111639d357e0f369c14248097b119112a71c diff --git a/3rdparty/intel-microcode b/3rdparty/intel-microcode index 8ac9378a848..8a62de41c01 160000 --- a/3rdparty/intel-microcode +++ b/3rdparty/intel-microcode @@ -1 +1 @@ -Subproject commit 8ac9378a84879e81c503e09f344560b3dd7f72df +Subproject commit 8a62de41c011615d749f8e72bb906dddc72e56a8 diff --git a/Documentation/drivers/cfr.md b/Documentation/drivers/cfr.md index ade6d2b14a3..0405f5c58c7 100644 --- a/Documentation/drivers/cfr.md +++ b/Documentation/drivers/cfr.md @@ -26,7 +26,7 @@ visible name, a help text, a default value and status flags. All strings are in ASCII. The boot options are grouped into forms, where each form hold -one ore more options. Boot options that are not used in the current +one or more options. Boot options that are not used in the current boot flow, and are never reachable should be marked as hidden. Dependecies between options can be defined in the code and should be evaluated by the CFR parser/UI. @@ -66,7 +66,7 @@ The public API can be found in ## Implementation design ### Tags Tags identify the structure defined in `src/commonlib/include/commonlib/cfr.h`. -Every struct might be immideatly followed by additional structs (so called +Every struct might be immediately followed by additional structs (so called sub nodes), having their own tag and size field. The sum of all sub nodes size fields plus the size of the struct itself equals the size field. @@ -208,7 +208,7 @@ effect on the non-volatile variable. Prevents writes to the variable. -* `CFR_OPTFLAG_GRAYOUT` +* `CFR_OPTFLAG_INACTIVE` Implies `READONLY`. The option is visible, but cannot be modified because one of the dependencies are not given. However there's a diff --git a/Documentation/drivers/cfr_internal.md b/Documentation/drivers/cfr_internal.md index 95fef66eee5..b2355d7b62b 100644 --- a/Documentation/drivers/cfr_internal.md +++ b/Documentation/drivers/cfr_internal.md @@ -50,8 +50,9 @@ static const struct sm_object serial_number = SM_DECLARE_VARCHAR({ The CFR options can have a dependency that must be evaluated at runtime by the OS/payload that parses the CFR record and displays the UI. -By using the `WITH_DEP()` macro you can specify another numberic option that -is checked to hide the current option. +By using the `WITH_DEP()` macro you can specify another numeric option that +is checked to hide the current option. The `WITH_DEP_VALUES()` macro allows +specifying one or more values that cause the dependent option to be displayed. **Example:** Declares a dependency from `sata_disable_port0` to `sata_enable`. The option `sata_disable_port0` will be hidden as long as "sata_enable" is 0. @@ -76,6 +77,37 @@ static struct sm_object sata_disable_port0 = SM_DECLARE_BOOL({ }, WITH_DEP(&sata_enable)); ``` +**Example:** Declares a dependency from `com1_termination` to `com1_mode`. +The option `com1_termination` will only be shown if `com1_mode` is set to RS-485. + +``` +#define COM_MODE_DISABLED 3 +#define COM_MODE_RS232 0 +#define COM_MODE_RS485 1 + +static struct sm_object com1_mode = SM_DECLARE_ENUM({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "com1_mode", + .ui_name = "COM1 Mode", + .ui_helptext = NULL, + .default_value = 1, + .values = (const struct sm_enum_value[]) { + { "Disabled", COM_MODE_DISABLED }, + { "RS-232", COM_MODE_RS232 }, + { "RS-485", COM_MODE_RS485 }, + SM_ENUM_VALUE_END }, +}); + +static struct sm_object com1_termination = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "com1_termination", + .ui_name = "Enable COM1 termination resistors", + .ui_helptext = NULL, + .default_value = false, +}, WITH_DEP_VALUES(&com1_mode, COM_MODE_RS485)); + +``` + ### Providing mainboard custom options A mainboard that uses CFR can provide a list of custom options diff --git a/Documentation/drivers/smmstorev2.md b/Documentation/drivers/smmstorev2.md index 6956cd49e1a..816f917dc14 100644 --- a/Documentation/drivers/smmstorev2.md +++ b/Documentation/drivers/smmstorev2.md @@ -197,6 +197,31 @@ coreboot tables, there's no risk that a malicious application capable of issuing SMIs could extract arbitrary data or modify the currently running kernel. +## Capsule update API + +To allow updating full flash content (except if locked at hardware +level), few new calls were added. They reuse communication buffer, SMI +command, return values and calling arguments of SMMSTORE commands listed +above, with the exception of subcommand passed via `%ah`. If the +subcommand is to operate on full flash size, it has the highest bit set, +e.g. it is `0x85` for `SMMSTORE_CMD_RAW_READ` and `0x86` for +`SMMSTORE_CMD_RAW_WRITE`. Every `block_id` describes block relative to +beginning of a flash, maximum value depends on its size. + +In addition, there is one new subcommand that must be called before any +other subcommands with highest bit set can be used. + +#### - SMMSTORE_CMD_USE_FULL_FLASH = 0x80 + +This command can only be executed once and is done by the firmware. +Calling this function at runtime has no effect. It takes one additional +parameter that, contrary to other commands, isn't a pointer. Instead, +`%ebx` indicates requested state of full flash access. If it equals 0, +commands for accessing full flash are permanently disabled, otherwise +they are permanently enabled until next boot. It is expected that the +payload won't allow regular OS to boot if the handler is enabled without +rebooting first. + ## External links * [A Tour Beyond BIOS Implementing UEFI Authenticated Variables in SMM with EDKI](https://software.intel.com/sites/default/files/managed/cf/ea/a_tour_beyond_bios_implementing_uefi_authenticated_variables_in_smm_with_edkii.pdf) diff --git a/FUNDING.yml b/FUNDING.yml new file mode 100644 index 00000000000..4e77cf822a0 --- /dev/null +++ b/FUNDING.yml @@ -0,0 +1,2 @@ + +open_collective: 3mdeb_com diff --git a/Makefile.mk b/Makefile.mk index ca79d053ad4..10f707b9d1d 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -115,8 +115,8 @@ subdirs-y += $(filter-out src/superio/common,$(wildcard src/superio/*)) $(wildca subdirs-y += $(wildcard src/drivers/*) $(wildcard src/drivers/*/*) $(wildcard src/drivers/*/*/*) subdirs-y += src/cpu src/vendorcode subdirs-y += util/cbfstool util/sconfig util/nvramtool util/pgtblgen util/amdfwtool -subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu -subdirs-y += util/ifdtool +subdirs-y += util/futility util/marvell util/bincfg util/supermicro util/qemu util/msi +subdirs-y += util/ifdtool util/txesbmantool subdirs-y += $(wildcard src/arch/*) subdirs-y += src/mainboard/$(MAINBOARDDIR) subdirs-y += src/security @@ -235,9 +235,7 @@ ifeq ($(CONFIG_USE_BLOBS),y) # until expressly requested and enabled with --checkout forgetthis:=$(shell git submodule update --init --checkout 3rdparty/blobs $(quiet_errors)) forgetthis:=$(shell git submodule update --init --checkout 3rdparty/intel-microcode $(quiet_errors)) -ifeq ($(CONFIG_FSP_USE_REPO),y) forgetthis:=$(shell git submodule update --init --checkout 3rdparty/fsp $(quiet_errors)) -endif ifeq ($(CONFIG_USE_AMD_BLOBS),y) forgetthis:=$(shell git submodule update --init --checkout 3rdparty/amd_blobs $(quiet_errors)) endif @@ -477,9 +475,20 @@ ifeq ($(CONFIG_COMPRESS_PRERAM_STAGES),y) CBFS_PRERAM_COMPRESS_FLAG:=LZ4 endif +strip_version = $(strip $(subst v,,$(subst ., ,$(1)))) + ifneq ($(CONFIG_LOCALVERSION),"") COREBOOT_EXTRA_VERSION := -$(call strip_quotes,$(CONFIG_LOCALVERSION)) +DASHARO_VERSION := $(call strip_quotes,$(CONFIG_LOCALVERSION)) +DASHARO_MAJOR_VERSION := $(word 1,$(call strip_version,$(DASHARO_VERSION))) +DASHARO_MINOR_VERSION := $(word 2,$(call strip_version,$(DASHARO_VERSION))) +DASHARO_PATCH_VERSION := $(word 3,$(call strip_version,$(DASHARO_VERSION))) + COREBOOT_EXPORTS += COREBOOT_EXTRA_VERSION +COREBOOT_EXPORTS += DASHARO_VERSION +COREBOOT_EXPORTS += DASHARO_MAJOR_VERSION +COREBOOT_EXPORTS += DASHARO_MINOR_VERSION +COREBOOT_EXPORTS += DASHARO_PATCH_VERSION endif CPPFLAGS_common := -Isrc @@ -648,7 +657,9 @@ build_h := $(obj)/build.h # when we call it through the `$(shell)` function. This is fragile # but as variables newly added to `genbuild_h.sh` would just not # work, we'd notice that instantly at least. -build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION +build_h_exports := BUILD_TIMELESS KERNELVERSION COREBOOT_EXTRA_VERSION \ + DASHARO_VERSION DASHARO_MAJOR_VERSION DASHARO_MINOR_VERSION \ + DASHARO_PATCH_VERSION # Report new `build.ht` as dependency if `build.h` differs. build_h_check := \ @@ -680,6 +691,12 @@ CSE_SERGER:=$(objutil)/cbfstool/cse_serger ECCTOOL:=$(objutil)/ffs/ecc/ecc CREATE_CONTAINER:=$(objutil)/open-power-signing-utils/create-container +ifeq ($(CONFIG_TXE_SECURE_BOOT),y) +TXESBMANTOOL:=$(objutil)/txesbmantool/txesbmantool +else +TXESBMANTOOL:= +endif + $(obj)/cbfstool: $(CBFSTOOL) cp $< $@ @@ -846,7 +863,7 @@ install-git-commit-clangfmt: include util/crossgcc/Makefile.mk .PHONY: tools -tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD) $(ECCTOOL) $(CREATE_CONTAINER) +tools: $(objutil)/kconfig/conf $(objutil)/kconfig/toada $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(AMDCOMPRESS) $(FUTILITY) $(BINCFG) $(IFITTOOL) $(objutil)/supermicro/smcbiosinfo $(objutil)/msi/romholetool $(CSE_FPT) $(CSE_SERGER) $(AMDFWREAD) $(ECCTOOL) $(CREATE_CONTAINER) $(TXESBMANTOOL) ########################################################################### # Common recipes for all stages @@ -1061,9 +1078,12 @@ placed-files-in-region = $(foreach file,$(call all-files-in-region,$(1)), \ # $(call sort-files,subset of $(cbfs-files)) # reorders the files in the given set to list files at fixed positions first, -# followed by aligned files and finally those with no constraints. +# followed by a payload (which might be big, best to place it first when there +# are few files in CBFS), followed by aligned files, and finally those with +# no constraints. sort-files = \ $(eval _tmp_fixed:=) \ + $(eval _tmp_payload:=) \ $(eval _tmp_aligned:=) \ $(eval _tmp_regular:=) \ $(foreach file,$(1), \ @@ -1071,8 +1091,10 @@ sort-files = \ $(eval _tmp_fixed += $(file)), \ $(if $(call extract_nth,6,$(file)), \ $(eval _tmp_aligned += $(file)), \ - $(eval _tmp_regular += $(file))))) \ - $(_tmp_fixed) $(_tmp_aligned) $(_tmp_regular) + $(if $(filter payload,$(call extract_nth,3,$(file))), \ + $(eval _tmp_payload += $(file)), \ + $(eval _tmp_regular += $(file)))))) \ + $(_tmp_fixed) $(_tmp_payload) $(_tmp_aligned) $(_tmp_regular) # command list to add files to CBFS prebuild-files = $(foreach region,$(all-regions), \ diff --git a/build.sh b/build.sh new file mode 100755 index 00000000000..6397232076c --- /dev/null +++ b/build.sh @@ -0,0 +1,480 @@ +#!/bin/bash + +set -euo pipefail + +usage() { + echo "${0} CMD" + echo "Available CMDs:" + echo -e "\tz690a_ddr4 - build Dasharo image compatible with MSI PRO Z690-A (WIFI) DDR4" + echo -e "\tz690a_ddr5 - build Dasharo image compatible with MSI PRO Z690-A (WIFI)" + echo -e "\tz790p_ddr4 - build Dasharo image compatible with MSI PRO Z790-P (WIFI) DDR4" + echo -e "\tz790p_ddr5 - build Dasharo image compatible with MSI PRO Z790-P (WIFI)" + echo -e "\tvp66xx - build Dasharo for Protectli VP66xx" + echo -e "\tvp46xx - build Dasharo for Protectli VP46xx" + echo -e "\tvp32xx - build Dasharo for Protectli VP32xx" + echo -e "\tvp2430 - build Dasharo for Protectli VP2430" + echo -e "\tvp2420 - build Dasharo for Protectli VP2420" + echo -e "\tvp2410 - build Dasharo for Protectli VP2410" + echo -e "\tV1210 - build Dasharo for Protectli V1210" + echo -e "\tV1410 - build Dasharo for Protectli V1410" + echo -e "\tV1610 - build Dasharo for Protectli V1610" + echo -e "\tns5x_adl - build Dasharo for Novacustom NS5x_ADL" + echo -e "\tns5x_tgl - build Dasharo for Novacustom NS5x_TGL" + echo -e "\tnv4x_adl - build Dasharo for Novacustom NV4x_ADL" + echo -e "\tnv4x_tgl - build Dasharo for Novacustom NV4x_TGL" + echo -e "\tv540tnx - build Dasharo for Novacustom V540TNx" + echo -e "\tv540tu - build Dasharo for Novacustom V540TU" + echo -e "\tv560tnx - build Dasharo for Novacustom V560TNx" + echo -e "\tv560tu - build Dasharo for Novacustom V560TU" + echo -e "\tapu2 - build Dasharo for PC Engines APU2" + echo -e "\tapu3 - build Dasharo for PC Engines APU3" + echo -e "\tapu4 - build Dasharo for PC Engines APU4" + echo -e "\tapu6 - build Dasharo for PC Engines APU6" + echo -e "\toptiplex_9010_uefi - build Dasharo compatible with Dell OptiPlex 7010/9010 (UEFI)" + echo -e "\toptiplex_9010_seabios - build Dasharo compatible with Dell OptiPlex 7010/9010 (SeaBIOS)" + echo -e "\tqemu - build Dasharo for QEMU Q35" + echo -e "\tqemu_full - build Dasharo for QEMU Q35 with all menus available" + echo -e "\todroid_h4 - build Dasharo compatible with Hardkernel ODROID H4" +} + +SDKVER="2024-02-18_732134932b" + + +function build_optiplex_9010 { + DEFCONFIG=$1 + # Determine FW flavor first (uefi or seabios) + if [[ ${DEFCONFIG} == *"uefi"* ]]; then + FW_FLAVOR="uefi" + else + FW_FLAVOR="seabios" + fi + + # Get FW version + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + # Combine FW flavor with version + FW_VERSION="${FW_FLAVOR}_${FW_VERSION}" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make distclean" + + cp "${DEFCONFIG}" .config + + git submodule update --init --checkout + + echo "Building Dasharo compatible with Dell OptiPlex 7010/9010 (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + cp build/coreboot.rom ${BOARD}_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/${BOARD}_${FW_VERSION}.rom" + sha256sum ${BOARD}_${FW_VERSION}.rom > ${BOARD}_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_msi { + DEFCONFIG="configs/config.${BOARD}_$1" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make distclean" + + cp "${DEFCONFIG}" .config + + git submodule update --init --checkout + + echo "Building Dasharo compatible with MSI PRO $2(WIFI) (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + cp build/coreboot.rom ${BOARD}_${FW_VERSION}_$1.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/${BOARD}_${FW_VERSION}_$1.rom" + sha256sum ${BOARD}_${FW_VERSION}_$1.rom > ${BOARD}_${FW_VERSION}_$1.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_protectli_vault { + DEFCONFIG="configs/config.protectli_${BOARD}" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + if [ ! -d 3rdparty/dasharo-blobs/protectli ]; then + git submodule update --init --checkout + fi + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:2021-09-23_b0d87f753c \ + /bin/bash -c "make distclean" + + cp $DEFCONFIG .config + + echo "Building Dasharo for Protectli $BOARD (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + cp build/coreboot.rom protectli_${BOARD}_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/protectli_${BOARD}_${FW_VERSION}.rom" + sha256sum protectli_${BOARD}_${FW_VERSION}.rom > protectli_${BOARD}_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_v1x10 { + DEFCONFIG="configs/config.protectli_vault_jsl_$1" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + if [ ! -d 3rdparty/dasharo-blobs/protectli ]; then + git submodule update --init --checkout + fi + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make distclean" + + cp $DEFCONFIG .config + + echo "Building Dasharo for Protectli $1 (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + cp build/coreboot.rom protectli_$1_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/protectli_$1_${FW_VERSION}.rom" + sha256sum protectli_$1_${FW_VERSION}.rom > protectli_$1_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_novacustom { + DEFCONFIG="configs/config.novacustom_$1" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + if [ ! -d 3rdparty/dasharo-blobs/novacustom ]; then + git submodule update --init --checkout + fi + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make distclean" + + cp $DEFCONFIG .config + + echo "Building Dasharo for Novacustom $1 (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + # Obtain LAN ROM blob from release binary + wget -O UEFIExtract_NE_A68_x64_linux.zip https://github.com/LongSoft/UEFITool/releases/download/A68/UEFIExtract_NE_A68_x64_linux.zip + unzip -o UEFIExtract_NE_A68_x64_linux.zip + wget -O novacustom_v54x_mtl_v0.9.0.rom https://dl.3mdeb.com/open-source-firmware/Dasharo/novacustom_v54x_mtl/v0.9.0/novacustom_v54x_mtl_v0.9.0.rom + cp build/coreboot.rom novacustom_$1_${FW_VERSION}.rom + + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/novacustom_$1_${FW_VERSION}.rom" + sha256sum novacustom_$1_${FW_VERSION}.rom > novacustom_$1_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + + +function build_novacustom_v5x0tu { + DEFCONFIG="configs/config.novacustom_$1" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + if [ ! -d 3rdparty/dasharo-blobs/novacustom ]; then + git submodule update --init --checkout + fi + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make distclean" + + cp $DEFCONFIG .config + + echo "Building Dasharo for Novacustom $1 (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + # Obtain LAN ROM blob from release binary + wget -O UEFIExtract_NE_A68_x64_linux.zip https://github.com/LongSoft/UEFITool/releases/download/A68/UEFIExtract_NE_A68_x64_linux.zip + unzip -o UEFIExtract_NE_A68_x64_linux.zip + wget -O novacustom_v54x_mtl_v0.9.0.rom https://dl.3mdeb.com/open-source-firmware/Dasharo/novacustom_v54x_mtl/v0.9.0/novacustom_v54x_mtl_v0.9.0.rom + cp build/coreboot.rom novacustom_$1_${FW_VERSION}.rom + + # Extract and transfer LAN ROM blob + make -C util/cbfstool + util/cbfstool/cbfstool novacustom_v54x_mtl_v0.9.0.rom extract -r COREBOOT -f payload -n fallback/payload -m x86 + ./uefiextract payload DEB917C0-C56A-4860-A05B-BF2F22EBB717 + cp payload.dump/2\ 8C8CE578-8A3D-4F1C-9935-896185C32DD3/82\ DEB917C0-C56A-4860-A05B-BF2F22EBB717/1\ PE32\ image\ section/body.bin 3rdparty/blobs/mainboard/clevo/mtl-h/LanRom.efi + + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/novacustom_$1_${FW_VERSION}.rom" + sha256sum novacustom_$1_${FW_VERSION}.rom > novacustom_$1_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_pcengines { + VARIANT=$1 + DEFCONFIG="configs/config.pcengines_uefi_${VARIANT}" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + # checkout several submodules needed by these boards (some others are checked + # out by coreboot's Makefile) + git submodule update --init --force --checkout \ + 3rdparty/dasharo-blobs \ + 3rdparty/vboot + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make distclean" + + cp $DEFCONFIG .config + + echo "Building Dasharo for PC Engines ${VARIANT^^*} (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + cp build/coreboot.rom pcengines_${VARIANT}_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/pcengines_${VARIANT}_${FW_VERSION}.rom" + sha256sum pcengines_${VARIANT}_${FW_VERSION}.rom > pcengines_${VARIANT}_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_qemu { + DEFCONFIG="configs/config.emulation_qemu_x86_q35_uefi${1:-}" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + # checkout several submodules needed by these boards (some others are checked + # out by coreboot's Makefile) + git submodule update --init --force --checkout \ + 3rdparty/dasharo-blobs + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make distclean" + + cp $DEFCONFIG .config + + echo "Building Dasharo for QEMU Q35 (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + cp build/coreboot.rom qemu_q35_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/qemu_q35_${FW_VERSION}.rom" + sha256sum qemu_q35_${FW_VERSION}.rom > qemu_q35_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +function build_odroid_h4 { + DEFCONFIG="configs/config.hardkernel_odroid_h4" + FW_VERSION=$(cat ${DEFCONFIG} | grep CONFIG_LOCALVERSION | cut -d '=' -f 2 | tr -d '"') + + # checkout several submodules needed by these boards (some others are checked + # out by coreboot's Makefile) + git submodule update --init --force --checkout \ + 3rdparty/dasharo-blobs + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make distclean" + + cp $DEFCONFIG .config + + echo "Building Dasharo compatbile with Hardkernel ODROID H4 (version $FW_VERSION)" + + docker run --rm -t -u $UID -v $PWD:/home/coreboot/coreboot \ + -v $HOME/.ssh:/home/coreboot/.ssh \ + -w /home/coreboot/coreboot coreboot/coreboot-sdk:$SDKVER \ + /bin/bash -c "make olddefconfig && make -j$(nproc)" + + cp build/coreboot.rom hardkernel_odroid_h4_${FW_VERSION}.rom + if [ $? -eq 0 ]; then + echo "Result binary placed in $PWD/hardkernel_odroid_h4_${FW_VERSION}.rom" + sha256sum hardkernel_odroid_h4_${FW_VERSION}.rom > hardkernel_odroid_h4_${FW_VERSION}.rom.sha256 + else + echo "Build failed!" + exit 1 + fi +} + +CMD="$1" + +case "$CMD" in + "ddr4" | "z690a_ddr4") + BOARD="msi_ms7d25" + build_msi ddr4 "Z690-A DDR4 " + ;; + "ddr5" | "z690a_ddr5") + BOARD="msi_ms7d25" + build_msi ddr5 "Z690-A DDR5 " + ;; + "z790p_ddr4") + BOARD="msi_ms7e06" + build_msi ddr4 "Z790-P DDR4 " + ;; + "z790p_ddr5") + BOARD="msi_ms7e06" + build_msi ddr5 "Z790-P DDR5 " + ;; + "vp66xx" | "VP66XX") + BOARD="vp66xx" + build_protectli_vault + ;; + "vp46xx" | "VP46XX") + BOARD="vp46xx" + build_protectli_vault + ;; + "vp32xx" | "VP32XX") + BOARD="vp32xx" + build_protectli_vault + ;; + "vp2410" | "VP2410") + BOARD="vp2410" + build_protectli_vault + ;; + "vp2420" | "VP2420") + BOARD="vp2420" + build_protectli_vault + ;; + "vp2430" | "VP2430") + BOARD="vp2430" + build_protectli_vault + ;; + "v1210" | "V1210" ) + build_v1x10 "v1210" + ;; + "v1211" | "V1211" ) + build_v1x10 "v1211" + ;; + "v1410" | "V1410" ) + build_v1x10 "v1410" + ;; + "v1610" | "V1610" ) + build_v1x10 "v1610" + ;; + "v540tnx" | "V540TNx" | "V540TNX" ) + BOARD="v540tnx" + build_novacustom "v540tnx" + ;; + "v560tnx" | "V560TNx" | "V560TNX" ) + BOARD="v560tnx" + build_novacustom "v560tnx" + ;; + "nv4x_adl" | "NV4x_ADL" | "NV4X_ADL" ) + BOARD="nv4x_adl" + build_novacustom "nv4x_adl" + ;; + "nv4x_tgl" | "NV4x_tgl" | "NV4X_TGL" ) + BOARD="nv4x_tgl" + build_novacustom "nv4x_tgl" + ;; + "ns5x_adl" | "NS5x_ADL" | "NS5X_ADL" ) + BOARD="ns5x_adl" + build_novacustom "ns5x_adl" + ;; + "ns5x_tgl" | "NS5x_TGL" | "NS5X_TGL" ) + BOARD="ns5x_tgl" + build_novacustom "ns5x_tgl" + ;; + "v560tu" | "V560TU" ) + BOARD="v560tu" + build_novacustom_v5x0tu "v560tu" + ;; + "v540tu " | "V540TU " ) + BOARD="v540tu" + build_novacustom_v5x0tu "v540tu " + ;; + "apu2" | "APU2" ) + build_pcengines "apu2" + ;; + "apu3" | "APU3" ) + build_pcengines "apu3" + ;; + "apu4" | "APU4" ) + build_pcengines "apu4" + ;; + "apu6" | "APU6" ) + build_pcengines "apu6" + ;; + "optiplex_9010_uefi") + BOARD="optiplex_9010" + build_optiplex_9010 "configs/config.dell_optiplex_9010_sff_uefi_txt" + ;; + "optiplex_9010_seabios") + BOARD="optiplex_9010" + build_optiplex_9010 "configs/config.dell_optiplex_9010_sff_txt" + ;; + "qemu" | "QEMU" | "q35" | "Q35" ) + build_qemu + ;; + "qemu_full" | "QEMU_full" | "q35_full" | "Q35_full" ) + build_qemu "_all_menus" + ;; + "odroid_h4" | "odroid_H4" | "ODROID_H4" ) + build_odroid_h4 + ;; + *) + echo "Invalid command: \"$CMD\"" + usage + ;; +esac diff --git a/capsule.sh b/capsule.sh new file mode 100755 index 00000000000..fc0de48b97e --- /dev/null +++ b/capsule.sh @@ -0,0 +1,294 @@ +#!/bin/bash + +set -e + +edk_workspace=payloads/external/edk2/workspace +edk_tools=${edk_workspace}/Dasharo/BaseTools/BinWrappers/PosixLike +edk_scripts=${edk_workspace}/Dasharo/BaseTools/Scripts + +function die() { + echo error: "$@" 1>&2 + exit 1 +} + +function confirm() { + local msg=$1 + read -r -n1 -p "$msg [y/N] " + echo + if [ "$REPLY" != y ]; then + die "operation cancelled by the user" + fi +} + +function print_banner() { + local msg=$1 + + echo + echo ========== "${msg^^*}" ========== + echo +} + +function print_usage() { + echo "Usage: $(basename "$0") subcommand [subcommand-args...]" + echo + echo 'Subcommands:' + echo ' help print this message' + echo ' keygen use OpenSSL to auto-generate test keys suitable for signing' + echo ' positional argument: directory-path' + echo ' make build a capsule, options:' + echo ' -t root-certificate-file' + echo ' -o subroot-certificate-file' + echo ' -s signing-certificate-file' +} + +function help_subcommand() { + print_usage +} + +function keygen_subcommand() { + local dir=$1 + + if [ $# -ne 1 ]; then + echo "Usage: $(basename "$0") keygen keys-dir" + exit 1 + fi + + if [ -e "$dir" ]; then + confirm "OK to remove '$dir'?" + rm -r "$dir" + fi + + mkdir "$dir" + cd "$dir" + + # this is needed to make `openssl req` work non-interactively + cat > "openssl.cnf" << 'EOF' +.include /etc/ssl/openssl.cnf + +[ CA_default ] +dir = ./test-ca +certs = $dir/certs +crl_dir = $dir/crl +database = $dir/index.txt +new_certs_dir = $dir/newcerts +certificate = $dir/cacert.pem +serial = $dir/serial +crlnumber = $dir/crlnumber +crl = $dir/crl.pem +private_key = $dir/private/cakey.pem + +[ req_root ] +prompt = no +distinguished_name = req_root_dn +x509_extensions = v3_ca +string_mask = utf8only +[ req_root_dn ] +countryName = XX +stateOrProvinceName = Province +organizationName = Org +commonName = root + +[ req_sub ] +prompt = no +distinguished_name = req_sub_dn +x509_extensions = v3_ca +string_mask = utf8only +[ req_sub_dn ] +countryName = XX +stateOrProvinceName = Province +organizationName = Org +commonName = sub + +[ req_sign ] +prompt = no +distinguished_name = req_sign_dn +x509_extensions = v3_ca +string_mask = utf8only +[ req_sign_dn ] +countryName = XX +stateOrProvinceName = Province +organizationName = Org +commonName = sign +EOF + + print_banner 'Making root certificate' + + # make root certificate + openssl genrsa -out root.p8e 2048 + openssl req -config openssl.cnf -section req_root -new -x509 -days 3650 -key root.p8e -out root.pub.pem + + # dump certificate information like `openssl ca` does for completeness + openssl x509 -in root.pub.pem -text -certopt no_sigdump,no_pubkey -nocert + + # create a CA + mkdir -p test-ca/newcerts + touch test-ca/index.txt + echo 01 > test-ca/serial + + openssl x509 -in root.pub.pem -out root.cer -outform DER + python "${OLDPWD}/${edk_scripts}/BinToPcd.py" \ + -p gFmpDevicePkgTokenSpaceGuid.PcdFmpDevicePkcs7CertBufferXdr \ + -i root.cer -x -o CapsuleRootKey.inc + + print_banner 'Making subroot certificate' + + # make subroot certificate + openssl genrsa -out sub.p8e 2048 + openssl req -config openssl.cnf -section req_sub -new -key sub.p8e -out sub.csr + yes | openssl ca -config openssl.cnf -extensions v3_ca -in sub.csr -days 3650 -cert root.pub.pem -keyfile root.p8e -notext -out sub.pub.pem + + print_banner 'Making signing certificate' + + # make signing certificate + openssl genrsa -out sign.p8e 2048 + openssl req -config openssl.cnf -section req_sign -new -key sign.p8e -out sign.csr + yes | openssl ca -config openssl.cnf -in sign.csr -days 3650 -cert sub.pub.pem -keyfile sub.p8e -notext -out sign.crt + + # create binary PKCS12 (certificate + private key) from signing certificate + openssl pkcs12 -export -passout pass: -inkey sign.p8e -in sign.crt -out sign.pfx + # now convert binary PKCS12 into PEM PKCS12 with no password + openssl pkcs12 -in sign.pfx -passin pass: -nodes -out sign.p12 + + print_banner 'Usage examples' + + echo "Installing root certificate (before build):" + echo " cp $dir/CapsuleRootKey.inc ${edk_workspace}/Dasharo/DasharoPayloadPkg/" + echo + echo "Signing a capsule (after build):" + echo " $0 make -t $dir/root.pub.pem -o $dir/sub.pub.pem -s $dir/sign.p12" +} + +function check_cert() { + local name=$1 + local path=$2 + + if [ -z "$path" ]; then + die "$name certificate wasn't provided" + fi + + if [ ! -f "$path" ]; then + die "can't read $name certificate at '$path'" + fi +} + +function make_subcommand() { + if [ ! -f .config ]; then + die "no '.config' file in current directory" + fi + if [ ! -f build/coreboot.rom ]; then + die "no 'build/coreboot.rom'; the firmware wasn't built?" + fi + if [ ! build/coreboot.rom -nt .config ]; then + die "'build/coreboot.rom' is not newer than .config'; need a re-build?" + fi + if [ ! -x "${edk_tools}/GenerateCapsule" ]; then + die "'${edk_tools}/GenerateCapsule' can't be executed" + fi + + # import coreboot's config file replacing $(...) with ${...} + while read -r line; do + if ! eval "$line"; then + die "failed to source '.config'" + fi + done <<< "$(sed 's/\$(\([^)]\+\))/${\1}/g' .config)" + + if [ "$CONFIG_DRIVERS_EFI_UPDATE_CAPSULES" != y ]; then + die "current board configuration lacks support of update capsules" + fi + + # Option names match terminology of GenerateCapsule which conveniently start + # with different letters: + # * t - trusted + # * o - other + # * s - signer + local root_cert sub_cert sign_cert + while getopts "t:o:s:" OPTION; do + case $OPTION in + t) root_cert="$OPTARG" ;; + o) sub_cert="$OPTARG" ;; + s) sign_cert="$OPTARG" ;; + *) exit 1 ;; + esac + done + + check_cert root "$root_cert" + check_cert sub "$sub_cert" + check_cert sign "$sign_cert" + + local cap_file=${CONFIG_MAINBOARD_DIR/\//-} + if [[ ${CONFIG_MAINBOARD_PART_NUMBER} =~ DDR4 ]]; then + cap_file+=-ddr4 + fi + cap_file+=-${CONFIG_LOCALVERSION} + cap_file+=.cap + + if [ -e "$cap_file" ]; then + confirm "Overwrite already existing '$cap_file'?" + fi + + local build_type + if [ "$CONFIG_EDK2_RELEASE" = y ]; then + build_type=RELEASE + else + build_type=DEBUG + fi + + local json_file + json_file=$(mktemp --tmpdir --suffix -cap.json XXXXXXXX) + trap "$(printf 'rm -f %q' "$json_file")" EXIT + + cat > "$json_file" << EOF +{ + "EmbeddedDrivers": [ + { + "Driver": "${edk_workspace}/Build/DasharoPayloadPkgX64/${build_type}_COREBOOT/X64/CapsuleSplashDxe.efi" + }, + { + "Driver": "${edk_workspace}/Build/DasharoPayloadPkgX64/${build_type}_COREBOOT/X64/FmpDxe.efi" + } + ], + "Payloads": [ + { + "Payload": "build/coreboot.rom", + "Guid": "${CONFIG_DRIVERS_EFI_MAIN_FW_GUID}", + "FwVersion": "${CONFIG_DRIVERS_EFI_MAIN_FW_VERSION}", + "LowestSupportedVersion": "${CONFIG_DRIVERS_EFI_MAIN_FW_LSV}", + + "OpenSslSignerPrivateCertFile": "${sign_cert}", + "OpenSslOtherPublicCertFile": "${sub_cert}", + "OpenSslTrustedPublicCertFile": "${root_cert}" + } + ] +} +EOF + + # Linux doesn't support InitiateReset flag, omitting it to rely on manual + # warm reset + if ! "${edk_tools}/GenerateCapsule" --encode \ + --capflag PersistAcrossReset \ + --json-file "$json_file" \ + --output "$cap_file"; then + die "GenerateCapsule failed" + fi + + echo "Created the capsule at '$cap_file'" +} + +if [ $# -eq 0 ]; then + print_usage + exit 1 +fi + +subcommand=$1 +shift + +case "$subcommand" in + help|keygen|make) + "$subcommand"_subcommand "$@" ;; + + *) + echo "Unexpected subcommand: $subcommand" + echo + print_usage + exit 1 ;; +esac diff --git a/configs/config.dell_optiplex_9010_sff b/configs/config.dell_optiplex_9010_sff index b0ef91b09eb..b45182a67ad 100644 --- a/configs/config.dell_optiplex_9010_sff +++ b/configs/config.dell_optiplex_9010_sff @@ -1,10 +1,21 @@ -CONFIG_USE_OPTION_TABLE=y -CONFIG_USE_BLOBS=y +CONFIG_LOCALVERSION="v0.1.0-rc3" CONFIG_VENDOR_DELL=y -CONFIG_BOARD_DELL_OPTIPLEX_9010=y CONFIG_ONBOARD_VGA_IS_PRIMARY=y -# CONFIG_DRIVERS_UART_8250IO is not set -CONFIG_PCIEXP_CLK_PM=y CONFIG_SEABIOS_PS2_TIMEOUT=3000 -CONFIG_POST_DEVICE_LPC=y -CONFIG_HAVE_EM100_SUPPORT=y +CONFIG_PXE_ROM_ID="8086,1502" +CONFIG_BOARD_DELL_OPTIPLEX_9010=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_PCIEXP_CLK_PM=y +CONFIG_TPM_MEASURED_BOOT=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_SEABIOS_USB_SIGATT_TIME=3000 +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_SEABIOS_DEBUG_LEVEL=0 +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" diff --git a/configs/config.dell_optiplex_9010_sff_txt b/configs/config.dell_optiplex_9010_sff_txt new file mode 100644 index 00000000000..14d03f04d8f --- /dev/null +++ b/configs/config.dell_optiplex_9010_sff_txt @@ -0,0 +1,24 @@ +CONFIG_LOCALVERSION="v0.1.0-rc3" +CONFIG_VENDOR_DELL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_SEABIOS_PS2_TIMEOUT=3000 +CONFIG_PXE_ROM_ID="8086,1502" +CONFIG_BOARD_DELL_OPTIPLEX_9010=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_TPM_MEASURED_BOOT=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BDR_VERSION=4 +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_SEABIOS_USB_SIGATT_TIME=3000 +CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y +CONFIG_SEABIOS_DEBUG_LEVEL=0 +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" diff --git a/configs/config.dell_optiplex_9010_sff_uefi b/configs/config.dell_optiplex_9010_sff_uefi new file mode 100644 index 00000000000..6bcb8613530 --- /dev/null +++ b/configs/config.dell_optiplex_9010_sff_uefi @@ -0,0 +1,49 @@ +CONFIG_LOCALVERSION="v0.1.1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_DELL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_BOARD_DELL_OPTIPLEX_9010=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SD_MMC_TIMEOUT=1000 +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.dell_optiplex_9010_sff_uefi_txt b/configs/config.dell_optiplex_9010_sff_uefi_txt new file mode 100644 index 00000000000..9f9513aed30 --- /dev/null +++ b/configs/config.dell_optiplex_9010_sff_uefi_txt @@ -0,0 +1,52 @@ +CONFIG_LOCALVERSION="v0.1.1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_DELL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_BOARD_DELL_OPTIPLEX_9010=y +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +# CONFIG_USE_PC_CMOS_ALTCENTURY is not set +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BDR_VERSION=4 +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SD_MMC_TIMEOUT=1000 +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="12345678" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.emulation_qemu_x86_q35_uefi b/configs/config.emulation_qemu_x86_q35_uefi new file mode 100644 index 00000000000..2bfa5c582dc --- /dev/null +++ b/configs/config.emulation_qemu_x86_q35_uefi @@ -0,0 +1,44 @@ +CONFIG_LOCALVERSION="v0.2.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_CPU_QEMU_X86_TSEG_SMM=y +CONFIG_UDK_202005_BINDING=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="20651b14-8653-4d9b-a75a-67fa76e0ada5" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00020080 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00020080 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_TPM1=y +CONFIG_TPM2=y +CONFIG_TPM_HASH_SHA256=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0017 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.emulation_qemu_x86_q35_uefi_all_menus b/configs/config.emulation_qemu_x86_q35_uefi_all_menus new file mode 100644 index 00000000000..edb9a5a6ec5 --- /dev/null +++ b/configs/config.emulation_qemu_x86_q35_uefi_all_menus @@ -0,0 +1,53 @@ +CONFIG_LOCALVERSION="v0.2.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_BOARD_EMULATION_QEMU_X86_Q35=y +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_CPU_QEMU_X86_TSEG_SMM=y +CONFIG_UDK_202005_BINDING=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM1=y +CONFIG_TPM2=y +CONFIG_TPM_HASH_SHA256=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0017 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.hardkernel_odroid_h4 b/configs/config.hardkernel_odroid_h4 new file mode 100644 index 00000000000..39ab3427690 --- /dev/null +++ b/configs/config.hardkernel_odroid_h4 @@ -0,0 +1,59 @@ +CONFIG_LOCALVERSION="v0.9.0-rc3" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_HARDKERNEL=y +CONFIG_VBOOT=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT=10 +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +# CONFIG_DRIVERS_MTK_WIFI is not set +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_DISPLAY_FSP_CALLS_AND_STATUS=y +CONFIG_DISPLAY_FSP_HEADER=y diff --git a/configs/config.intel_minnowmax b/configs/config.intel_minnowmax new file mode 100644 index 00000000000..c515c738c48 --- /dev/null +++ b/configs/config.intel_minnowmax @@ -0,0 +1,45 @@ +CONFIG_VENDOR_INTEL=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_VGA_BIOS is not set +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_IFD_BIN_PATH="IFWI_HEADER.bin" +CONFIG_ME_BIN_PATH="VLV_SEC_REGION.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_BOARD_INTEL_MINNOWMAX=y +CONFIG_HAVE_IFD_BIN=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_HAVE_MRC=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="IntelBYTGopDriver.efi" +CONFIG_EDK2_DISABLE_TPM=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.lenovo_m900_tiny b/configs/config.lenovo_m900_tiny new file mode 100644 index 00000000000..5bc8609d66a --- /dev/null +++ b/configs/config.lenovo_m900_tiny @@ -0,0 +1,49 @@ +CONFIG_CCACHE=y +CONFIG_VENDOR_LENOVO=y +CONFIG_VBOOT=y +CONFIG_VBOOT_SLOTS_RW_A=y +CONFIG_VBOOT_NO_BOARD_SUPPORT=y +CONFIG_BOARD_LENOVO_THINKCENTRE_M900_TINY=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_INTEL_ME_DISABLED_HECI=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_OPTION_CFR=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_VBOOT_MOCK_SECDATA=y +CONFIG_VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE=y +CONFIG_TPM2=y +CONFIG_TPM_HASH_SHA256=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="origin/cfr_ng" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowMenu=FALSE" +CONFIG_BUILD_IPXE=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.msi_ms7d25_ddr4 b/configs/config.msi_ms7d25_ddr4 index fde405193c2..f1141039fc8 100644 --- a/configs/config.msi_ms7d25_ddr4 +++ b/configs/config.msi_ms7d25_ddr4 @@ -1,23 +1,77 @@ +CONFIG_LOCALVERSION="v1.1.4" CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR4=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_TPM_MEASURED_BOOT=y CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INCLUDE_HSPHY_IN_FMAP=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y CONFIG_PCIEXP_HOTPLUG=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y CONFIG_DRIVERS_EFI_VARIABLE_STORE=y CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="0f3e8ba6-19d3-461b-bbbc-8b5689fe8097" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01010480 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01010400 CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y -CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y -CONFIG_DRIVERS_GENERIC_CBFS_UUID=y CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set CONFIG_POST_DEVICE_PCI_PCIE=y CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" -CONFIG_EDK2_TAG_OR_REV="origin/dasharo" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y -CONFIG_EDK2_SD_MMC_TIMEOUT=1000 +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.msi_ms7d25_ddr5 b/configs/config.msi_ms7d25_ddr5 index e26e99e8178..20c168a8a25 100644 --- a/configs/config.msi_ms7d25_ddr5 +++ b/configs/config.msi_ms7d25_ddr5 @@ -1,21 +1,74 @@ +CONFIG_LOCALVERSION="v1.1.4" +CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y -CONFIG_CBFS_SIZE=0x1000000 -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_MSI_Z690_A_PRO_WIFI_DDR5=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y -CONFIG_PCIEXP_HOTPLUG=y -CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_INCLUDE_HSPHY_IN_FMAP=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="119059ec-1a5e-4844-b2e6-6f573b257570" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x01010480 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x01010400 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y -CONFIG_POST_DEVICE_PCI_PCIE=y -CONFIG_POST_IO_PORT=0x80 +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set CONFIG_PAYLOAD_EDK2=y CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" -CONFIG_EDK2_TAG_OR_REV="origin/dasharo" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y -CONFIG_EDK2_SD_MMC_TIMEOUT=1000 -CONFIG_TPM2=y -CONFIG_TPM_MEASURED_BOOT=y -CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y -CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.msi_ms7e06_ddr4 b/configs/config.msi_ms7e06_ddr4 index a6080b93a9a..4fef3b65fe4 100644 --- a/configs/config.msi_ms7e06_ddr4 +++ b/configs/config.msi_ms7e06_ddr4 @@ -1,11 +1,74 @@ +CONFIG_LOCALVERSION="v0.9.2" +CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VBOOT=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR4=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_TPM_MEASURED_BOOT=y CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INCLUDE_HSPHY_IN_FMAP=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="91e6522e-25e1-4543-9b38-02e2aeafc9ed" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00090280 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00090200 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.msi_ms7e06_ddr5 b/configs/config.msi_ms7e06_ddr5 index f48435f159e..1d70f9b7b42 100644 --- a/configs/config.msi_ms7e06_ddr5 +++ b/configs/config.msi_ms7e06_ddr5 @@ -1,11 +1,74 @@ +CONFIG_LOCALVERSION="v0.9.2" +CONFIG_OPTION_BACKEND_NONE=y CONFIG_VENDOR_MSI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y CONFIG_VBOOT=y -CONFIG_BOARD_MSI_Z790_P_PRO_WIFI=y +# CONFIG_PCIEXP_ASPM is not set +# CONFIG_PCIEXP_L1_SUB_STATE is not set +# CONFIG_PCIEXP_CLK_PM is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=37 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_MSI_Z790_P_PRO_WIFI_DDR5=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" CONFIG_TPM_MEASURED_BOOT=y CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INCLUDE_HSPHY_IN_FMAP=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_HAVE_ME_BIN=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_EFI_FW_INFO=y +CONFIG_DRIVERS_EFI_MAIN_FW_GUID="58301b3d-5b6d-4562-9ec1-fbce40f15253" +CONFIG_DRIVERS_EFI_MAIN_FW_VERSION=0x00090280 +CONFIG_DRIVERS_EFI_MAIN_FW_LSV=0x00090200 +CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=y CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_DASHARO_PCI_CONFIG=y +CONFIG_EDK2_DASHARO_MEMORY_CONFIG=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.novacustom_ns5x_adl b/configs/config.novacustom_ns5x_adl new file mode 100644 index 00000000000..c83c47a4c1d --- /dev/null +++ b/configs/config.novacustom_ns5x_adl @@ -0,0 +1,73 @@ +CONFIG_LOCALVERSION="v2.0.0-rc3" +CONFIG_CCACHE=y +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_MAINBOARD_VERSION="v2.1" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/ns5x_adl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/ns5x_adl/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/ns5x_adl/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdS3SupportExperimental=TRUE" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SYSTEM76_EC_LOGGING=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_ns5x_tgl b/configs/config.novacustom_ns5x_tgl new file mode 100644 index 00000000000..2014ed2e01e --- /dev/null +++ b/configs/config.novacustom_ns5x_tgl @@ -0,0 +1,73 @@ +CONFIG_LOCALVERSION="v2.0.0-rc3" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_FMDFILE="src/mainboard/clevo/tgl-u/vboot-rwa.fmd" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/ns5x_tgl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/ns5x_tgl/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_NS5X_TGLU=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INTEL_TME=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/ns5x_tgl/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdS3SupportExperimental=TRUE" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SYSTEM76_EC_LOGGING=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_nv4x_adl b/configs/config.novacustom_nv4x_adl new file mode 100644 index 00000000000..554b8b5da9d --- /dev/null +++ b/configs/config.novacustom_nv4x_adl @@ -0,0 +1,73 @@ +CONFIG_LOCALVERSION="v2.0.0-rc3" +CONFIG_CCACHE=y +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_MAINBOARD_VERSION="v2.1" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_adl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_adl/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_NV4X_ADLP=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/nv4x_adl/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SYSTEM76_EC_LOGGING=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_nv4x_tgl b/configs/config.novacustom_nv4x_tgl new file mode 100644 index 00000000000..aed314e5472 --- /dev/null +++ b/configs/config.novacustom_nv4x_tgl @@ -0,0 +1,73 @@ +CONFIG_LOCALVERSION="v2.0.0-rc3" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_FMDFILE="src/mainboard/clevo/tgl-u/vboot-rwa.fmd" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_tgl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_tgl/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_NV4X_TGLU=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INTEL_TME=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="055ef012e63dad2ca03d49e6bc31cb79dd11ddc7" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/nv4x_tgl/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdS3SupportExperimental=TRUE" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SYSTEM76_EC_LOGGING=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_nv4x_tgl_dgpu b/configs/config.novacustom_nv4x_tgl_dgpu new file mode 100644 index 00000000000..665b14be21a --- /dev/null +++ b/configs/config.novacustom_nv4x_tgl_dgpu @@ -0,0 +1,72 @@ +CONFIG_LOCALVERSION="v2.0.0-rc3" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_FMDFILE="src/mainboard/clevo/tgl-u/vboot-rwa.fmd" +# CONFIG_CONSOLE_SERIAL is not set +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_tgl/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/nv4x_tgl/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_NV4X_TGLU=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_INTEL_TME=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_EC_DASHARO_EC_UPDATE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_PCIEXP_HOTPLUG_IO=0x2000 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="055ef012e63dad2ca03d49e6bc31cb79dd11ddc7" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/nv4x_tgl/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="-D VARIABLE_SUPPORT=SMMSTORE --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdS3SupportExperimental=TRUE" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SYSTEM76_EC_LOGGING=y +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_SLEEP_TYPE_OPTION=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_DGPU_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.novacustom_v540tnx b/configs/config.novacustom_v540tnx new file mode 100644 index 00000000000..86ab2b8d10e --- /dev/null +++ b/configs/config.novacustom_v540tnx @@ -0,0 +1,81 @@ +CONFIG_LOCALVERSION="v0.9.1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_MAINBOARD_PART_NUMBER="V54x_6x_TU" +CONFIG_FMDFILE="src/mainboard/novacustom/mtl-h/vboot-rwab.fmd" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +# CONFIG_CONSOLE_POST is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tnx/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tnx/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_V540TNX=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x1558 +CONFIG_SUBSYSTEM_DEVICE_ID=0xa741 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="055ef012e63dad2ca03d49e6bc31cb79dd11ddc7" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/v5x0tu/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution=1920 --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution=1080" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_DGPU_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_v540tu b/configs/config.novacustom_v540tu new file mode 100644 index 00000000000..20f088bf0b8 --- /dev/null +++ b/configs/config.novacustom_v540tu @@ -0,0 +1,81 @@ +CONFIG_LOCALVERSION="v0.9.0-rc6" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_FMDFILE="src/mainboard/novacustom/mtl-h/vboot-rwab.fmd" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +# CONFIG_CONSOLE_POST is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/me.bin" +CONFIG_GBE_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/gbe.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_V540TU=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_GBE_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_BUILDING_WITH_DEBUG_FSP=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/v5x0tu/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_LAN_ROM_DRIVER="3rdparty/blobs/mainboard/novacustom/mtl-h/LanRom.efi" +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_v560tnx b/configs/config.novacustom_v560tnx new file mode 100644 index 00000000000..e89bfbda430 --- /dev/null +++ b/configs/config.novacustom_v560tnx @@ -0,0 +1,81 @@ +CONFIG_LOCALVERSION="v0.9.1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_MAINBOARD_PART_NUMBER="V54x_6x_TU" +CONFIG_FMDFILE="src/mainboard/novacustom/mtl-h/vboot-rwab.fmd" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +# CONFIG_CONSOLE_POST is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tnx/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tnx/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_V560TNX=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_HAVE_ME_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_SUBSYSTEM_VENDOR_ID=0x1558 +CONFIG_SUBSYSTEM_DEVICE_ID=0xa741 +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="055ef012e63dad2ca03d49e6bc31cb79dd11ddc7" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/v5x0tu/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_EDK2_CUSTOM_BUILD_PARAMS="--pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution=1920 --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution=1080" +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_DGPU_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.novacustom_v560tu b/configs/config.novacustom_v560tu new file mode 100644 index 00000000000..e8a62f16205 --- /dev/null +++ b/configs/config.novacustom_v560tu @@ -0,0 +1,81 @@ +CONFIG_LOCALVERSION="v0.9.0-rc6" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_NOVACUSTOM=y +CONFIG_FMDFILE="src/mainboard/novacustom/mtl-h/vboot-rwab.fmd" +# CONFIG_CONSOLE_SERIAL is not set +# CONFIG_POST_IO is not set +CONFIG_VBOOT=y +# CONFIG_CONSOLE_POST is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/me.bin" +CONFIG_GBE_BIN_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/gbe.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x200000 +CONFIG_PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS=36 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_NOVACUSTOM_V560TU=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/novacustom/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Include/" +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/novacustom/v5x0tu/MeteorLakeFspBinPkg/Fsp.fd" +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_ENABLE_EARLY_DMA_PROTECTION=y +CONFIG_HAVE_ME_BIN=y +CONFIG_HAVE_GBE_BIN=y +CONFIG_NO_GFX_INIT=y +CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS=y +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_PCIEXP_HOTPLUG_PREFETCH_MEM_BELOW_4G=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_BUILDING_WITH_DEBUG_FSP=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_EDK2_GOP_FILE="3rdparty/dasharo-blobs/novacustom/v5x0tu/IntelGopDriver.efi" +CONFIG_EDK2_USE_LAPTOP_LID_LIB=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_SKIP_PS2_DETECT=y +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_SHOW_CAMERA_OPTION=y +CONFIG_EDK2_SHOW_WIFI_BT_OPTION=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_BATTERY_CONFIG_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_USB_PORT_POWER_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0011 +CONFIG_EDK2_SETUP_MENU_KEY=0x000C +CONFIG_EDK2_ENABLE_BATTERY_CHECK=y +CONFIG_EDK2_PRINT_SOL_STRINGS=y +CONFIG_EDK2_LAN_ROM_DRIVER="3rdparty/blobs/mainboard/novacustom/mtl-h/LanRom.efi" +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=y +CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=y diff --git a/configs/config.pcengines_apu1 b/configs/config.pcengines_apu1 index a3e34b8df04..7ca69636a16 100644 --- a/configs/config.pcengines_apu1 +++ b/configs/config.pcengines_apu1 @@ -6,5 +6,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="10ec,8168" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu2 b/configs/config.pcengines_apu2 index fe0a9d7ba43..8e2d0548db9 100644 --- a/configs/config.pcengines_apu2 +++ b/configs/config.pcengines_apu2 @@ -8,5 +8,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,157b" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu3 b/configs/config.pcengines_apu3 index bf377158dfe..166a1f31e31 100644 --- a/configs/config.pcengines_apu3 +++ b/configs/config.pcengines_apu3 @@ -8,5 +8,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,1539" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu4 b/configs/config.pcengines_apu4 index 17db794bcf9..8085a046859 100644 --- a/configs/config.pcengines_apu4 +++ b/configs/config.pcengines_apu4 @@ -8,5 +8,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,1539" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu5 b/configs/config.pcengines_apu5 index b004e89c910..9e31e65e063 100644 --- a/configs/config.pcengines_apu5 +++ b/configs/config.pcengines_apu5 @@ -8,5 +8,4 @@ CONFIG_SEABIOS_ADD_SERCON_PORT_FILE=y CONFIG_PXE=y CONFIG_BUILD_IPXE=y CONFIG_PXE_ROM_ID="8086,1539" -# CONFIG_IPXE_SERIAL_CONSOLE is not set CONFIG_MEMTEST_SECONDARY_PAYLOAD=y diff --git a/configs/config.pcengines_apu6 b/configs/config.pcengines_apu6 new file mode 100644 index 00000000000..0e5ef7d866f --- /dev/null +++ b/configs/config.pcengines_apu6 @@ -0,0 +1,41 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_EDK2_BOOT_TIMEOUT=3 +CONFIG_BOARD_PCENGINES_APU6=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_RAM_DISK_ENABLE=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.pcengines_uefi_apu2 b/configs/config.pcengines_uefi_apu2 new file mode 100644 index 00000000000..1c9c2ab8ac9 --- /dev/null +++ b/configs/config.pcengines_uefi_apu2 @@ -0,0 +1,50 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_VBOOT=y +CONFIG_PXE_ROM_ID="8086,157b" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CHIP=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SPI_LOCK_PIN=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0014 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.pcengines_uefi_apu3 b/configs/config.pcengines_uefi_apu3 new file mode 100644 index 00000000000..c9e90f6609c --- /dev/null +++ b/configs/config.pcengines_uefi_apu3 @@ -0,0 +1,51 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_VBOOT=y +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_BOARD_PCENGINES_APU3=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CHIP=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SPI_LOCK_PIN=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0014 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.pcengines_uefi_apu4 b/configs/config.pcengines_uefi_apu4 new file mode 100644 index 00000000000..f41c834abc0 --- /dev/null +++ b/configs/config.pcengines_uefi_apu4 @@ -0,0 +1,51 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_VBOOT=y +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_BOARD_PCENGINES_APU4=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CHIP=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SPI_LOCK_PIN=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0014 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.pcengines_uefi_apu6 b/configs/config.pcengines_uefi_apu6 new file mode 100644 index 00000000000..52d10d9a172 --- /dev/null +++ b/configs/config.pcengines_uefi_apu6 @@ -0,0 +1,51 @@ +CONFIG_LOCALVERSION="v0.9.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PCENGINES=y +CONFIG_VBOOT=y +CONFIG_PXE_ROM_ID="8086,1539" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_BOARD_PCENGINES_APU6=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/dasharo/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_UDK_202005_BINDING=y +CONFIG_NO_GFX_INIT=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CHIP=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SPI_LOCK_PIN=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_1=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2.git" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SATA_PASSWORD=y +CONFIG_EDK2_OPAL_PASSWORD=y +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0014 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_cml_vp46xx b/configs/config.protectli_cml_vp46xx deleted file mode 100644 index 11642325dbb..00000000000 --- a/configs/config.protectli_cml_vp46xx +++ /dev/null @@ -1,13 +0,0 @@ -CONFIG_VENDOR_PROTECTLI=y -CONFIG_BOARD_PROTECTLI_VP46XX=y -CONFIG_TPM_MEASURED_BOOT=y -CONFIG_SMMSTORE_SIZE=0x40000 -CONFIG_TPM2=y -CONFIG_POST_IO_PORT=0x80 -CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y -CONFIG_EDK2_BOOT_TIMEOUT=6 -CONFIG_EDK2_FOLLOW_BGRT_SPEC=y -# CONFIG_EDK2_FULL_SCREEN_SETUP is not set -CONFIG_EDK2_SD_MMC_TIMEOUT=10 -CONFIG_EDK2_SERIAL_SUPPORT=y diff --git a/configs/config.protectli_vault_jsl_v1210 b/configs/config.protectli_vault_jsl_v1210 new file mode 100644 index 00000000000..e910ed6d8cc --- /dev/null +++ b/configs/config.protectli_vault_jsl_v1210 @@ -0,0 +1,52 @@ +CONFIG_LOCALVERSION="v0.9.2" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1210/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1210/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_V1210=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/Include" +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/FSP.fd" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vault_jsl_v1211 b/configs/config.protectli_vault_jsl_v1211 new file mode 100644 index 00000000000..4cbdf222fe0 --- /dev/null +++ b/configs/config.protectli_vault_jsl_v1211 @@ -0,0 +1,52 @@ +CONFIG_LOCALVERSION="v0.9.0-rc1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1210/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1210/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_V1211=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/Include" +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/FSP.fd" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vault_jsl_v1410 b/configs/config.protectli_vault_jsl_v1410 new file mode 100644 index 00000000000..b1940170ff5 --- /dev/null +++ b/configs/config.protectli_vault_jsl_v1410 @@ -0,0 +1,52 @@ +CONFIG_LOCALVERSION="v0.9.2" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1410/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1410/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_V1410=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/Include" +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/FSP.fd" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vault_jsl_v1610 b/configs/config.protectli_vault_jsl_v1610 new file mode 100644 index 00000000000..f39aeb7f2bd --- /dev/null +++ b/configs/config.protectli_vault_jsl_v1610 @@ -0,0 +1,52 @@ +CONFIG_LOCALVERSION="v0.9.2" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1610/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/V1610/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_V1610=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/Include" +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/JasperLakeFspBinPkg/FSP.fd" +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp2410 b/configs/config.protectli_vp2410 new file mode 100644 index 00000000000..64a8ede47d3 --- /dev/null +++ b/configs/config.protectli_vp2410 @@ -0,0 +1,63 @@ +CONFIG_LOCALVERSION="v1.1.1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +# CONFIG_DISABLE_HECI1_AT_PRE_BOOT is not set +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_IFWI_FILE_NAME="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/ifwi.bin" +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_VP2410=y +CONFIG_DRIVERS_UART_8250IO=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_FSP_HEADER_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/GeminilakeFspBinPkg/Include" +CONFIG_FSP_FD_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/GeminilakeFspBinPkg/Fsp.fd" +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_ADD_FSP_BINARIES=y +CONFIG_FSP_FULL_FD=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_POST_DEVICE_LPC=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y +CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI=y diff --git a/configs/config.protectli_vp2420 b/configs/config.protectli_vp2420 index 899a9560d60..1adf1f22f67 100644 --- a/configs/config.protectli_vp2420 +++ b/configs/config.protectli_vp2420 @@ -1,13 +1,65 @@ +CONFIG_LOCALVERSION="v1.2.1-rc8" CONFIG_VENDOR_PROTECTLI=y -CONFIG_CBFS_SIZE=0x900000 CONFIG_ONBOARD_VGA_IS_PRIMARY=y -CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x20000 +CONFIG_VBOOT=y +CONFIG_DISABLE_HECI1_AT_PRE_BOOT=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y CONFIG_BOARD_PROTECTLI_VP2420=y -CONFIG_SMMSTORE_SIZE=0x40000 +CONFIG_SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_INTEL_ME_DISABLED_HECI=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_SPI_FLASH_NO_FAST_READ=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_CBFS_VERIFICATION=y +CONFIG_CBFS_ALLOW_UNVERIFIED_DECOMPRESSION=y +CONFIG_VBOOT_CBFS_INTEGRATION=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +CONFIG_POST_DEVICE_LPC=y CONFIG_PAYLOAD_EDK2=y -CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y CONFIG_EDK2_FOLLOW_BGRT_SPEC=y -CONFIG_EDK2_SD_MMC_TIMEOUT=10 +# CONFIG_EDK2_PS2_SUPPORT is not set CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp2430 b/configs/config.protectli_vp2430 new file mode 100644 index 00000000000..c28417b194c --- /dev/null +++ b/configs/config.protectli_vp2430 @@ -0,0 +1,61 @@ +CONFIG_LOCALVERSION="v0.9.0-rc5" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp2430/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp2430/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_VP2430=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_INTEL_ME_DISABLED_HECI=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp32xx b/configs/config.protectli_vp32xx new file mode 100644 index 00000000000..c0008a5cae8 --- /dev/null +++ b/configs/config.protectli_vp32xx @@ -0,0 +1,62 @@ +CONFIG_LOCALVERSION="v0.9.0-rc10" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_VBOOT=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp32xx/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/vp32xx/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_EDK2_BOOTSPLASH_FILE="3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_HAVE_ME_BIN=y +CONFIG_INTEL_ME_DISABLED_HECI=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_FAN_OFF_CURVE_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp46xx b/configs/config.protectli_vp46xx new file mode 100644 index 00000000000..563783d8105 --- /dev/null +++ b/configs/config.protectli_vp46xx @@ -0,0 +1,65 @@ +CONFIG_LOCALVERSION="v1.2.0" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_VP46XX=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_INTEL_ME_DISABLED_HECI=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_RUN_FSP_GOP=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_BOOT_MANAGER_ESCAPE=y +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_FULL_SCREEN_SETUP is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=y +CONFIG_EDK2_DASHARO_OC_WDT_SHOW=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp46xx_txt b/configs/config.protectli_vp46xx_txt new file mode 100644 index 00000000000..6a94cdc8281 --- /dev/null +++ b/configs/config.protectli_vp46xx_txt @@ -0,0 +1,60 @@ +CONFIG_LOCALVERSION="v1.2.0-rc2" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_VBOOT=y +CONFIG_USE_LEGACY_8254_TIMER=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_VP46XX=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_RUN_FSP_GOP=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/biosac.bin" +CONFIG_INTEL_TXT_SINITACM_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/sinitac.bin" +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/configs/config.protectli_vp46xx_txt_seabios b/configs/config.protectli_vp46xx_txt_seabios new file mode 100644 index 00000000000..3345e94255e --- /dev/null +++ b/configs/config.protectli_vp46xx_txt_seabios @@ -0,0 +1,35 @@ +CONFIG_LOCALVERSION="v0.9.0-rc1" +CONFIG_VENDOR_PROTECTLI=y +CONFIG_FMDFILE="" +CONFIG_ONBOARD_VGA_IS_PRIMARY=y +CONFIG_PXE_ROM_ID="8086,15f3" +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_VP46XX=y +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_USE_INTEL_FSP_MP_INIT=y +CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_RUN_FSP_GOP=y +# CONFIG_RESOURCE_ALLOCATION_TOP_DOWN is not set +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_INTEL_TXT=y +CONFIG_INTEL_TXT_BIOSACM_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/biosac.bin" +CONFIG_INTEL_TXT_SINITACM_FILE="3rdparty/blobs/mainboard/$(MAINBOARDDIR)/sinitac.bin" +CONFIG_INTEL_TXT_LOGGING=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_SEABIOS_USB_SIGATT_TIME=500 +CONFIG_SEABIOS_DEBUG_LEVEL=0 +CONFIG_PXE=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_NO_PROMPT=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/dasharo.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" diff --git a/configs/config.protectli_vp66xx b/configs/config.protectli_vp66xx new file mode 100644 index 00000000000..5ba2424ac6b --- /dev/null +++ b/configs/config.protectli_vp66xx @@ -0,0 +1,72 @@ +CONFIG_LOCALVERSION="v0.9.1" +CONFIG_OPTION_BACKEND_NONE=y +CONFIG_VENDOR_PROTECTLI=y +CONFIG_VBOOT=y +CONFIG_PCIEXP_L1_SUB_STATE=y +CONFIG_PCIEXP_CLK_PM=y +CONFIG_IFD_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/descriptor.bin" +CONFIG_ME_BIN_PATH="3rdparty/dasharo-blobs/$(MAINBOARDDIR)/me.bin" +CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0x100000 +CONFIG_EDK2_BOOT_TIMEOUT=6 +CONFIG_HAVE_IFD_BIN=y +CONFIG_BOARD_PROTECTLI_VP66XX=y +CONFIG_EDK2_BOOTSPLASH_FILE="$(top)/3rdparty/dasharo-blobs/protectli/bootsplash.bmp" +CONFIG_TPM_MEASURED_BOOT=y +CONFIG_POWER_STATE_OFF_AFTER_FAILURE=y +CONFIG_SOFTWARE_CONNECTION_MANAGER=y +CONFIG_IFDTOOL_DISABLE_ME=y +CONFIG_HAVE_ME_BIN=y +CONFIG_ME_REGION_ALLOW_CPU_READ_ACCESS=y +CONFIG_INTEL_ME_DISABLED_HAP=y +CONFIG_DASHARO_PREFER_S3_SLEEP=y +# CONFIG_DASHARO_FIRMWARE_UPDATE_MODE is not set +CONFIG_PCIEXP_LANE_ERR_STAT_CLEAR=y +CONFIG_DRIVERS_EFI_VARIABLE_STORE=y +CONFIG_DRIVERS_GENERIC_CBFS_SERIAL=y +CONFIG_DRIVERS_GENERIC_CBFS_UUID=y +CONFIG_TPM2=y +CONFIG_BOOTMEDIA_LOCK_CONTROLLER=y +CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO=y +CONFIG_BOOTMEDIA_LOCK_IN_VERSTAGE=y +CONFIG_BOOTMEDIA_SMM_BWP=y +CONFIG_DEFAULT_CONSOLE_LOGLEVEL_0=y +# CONFIG_CONSOLE_USE_LOGLEVEL_PREFIX is not set +# CONFIG_CONSOLE_USE_ANSI_ESCAPES is not set +CONFIG_POST_DEVICE_LPC=y +CONFIG_PAYLOAD_EDK2=y +CONFIG_EDK2_REPOSITORY="https://github.com/Dasharo/edk2" +CONFIG_EDK2_TAG_OR_REV="78b13d68604f0afde31080ca49e8c53bb43eaece" +CONFIG_EDK2_USE_EDK2_PLATFORMS=y +CONFIG_EDK2_PLATFORMS_REPOSITORY="https://github.com/Dasharo/edk2-platforms" +CONFIG_EDK2_PLATFORMS_TAG_OR_REV="3323ed481d35096fb6a7eae7b49f35eff00f86cf" +CONFIG_EDK2_CBMEM_LOGGING=y +CONFIG_EDK2_FOLLOW_BGRT_SPEC=y +# CONFIG_EDK2_PRIORITIZE_INTERNAL is not set +# CONFIG_EDK2_PS2_SUPPORT is not set +CONFIG_EDK2_SERIAL_SUPPORT=y +CONFIG_BUILD_IPXE=y +CONFIG_IPXE_ADD_SCRIPT=y +CONFIG_IPXE_SCRIPT="3rdparty/dasharo-blobs/dasharo/protectli.ipxe" +CONFIG_IPXE_CUSTOM_BUILD_ID="0123456789" +CONFIG_EDK2_ENABLE_IPXE=y +CONFIG_EDK2_IPXE_OPTION_NAME="Network Boot and Utilities" +# CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE is not set +CONFIG_EDK2_SETUP_PASSWORD=y +CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=y +CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=y +CONFIG_EDK2_DASHARO_USB_CONFIG=y +CONFIG_EDK2_DASHARO_POWER_CONFIG=y +CONFIG_EDK2_FAN_CURVE_OPTION=y +CONFIG_EDK2_FAN_OFF_CURVE_OPTION=y +CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=y +CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=y +CONFIG_EDK2_HAVE_2ND_UART=y +CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=y +CONFIG_EDK2_DASHARO_CPU_CONFIG=y +CONFIG_EDK2_CORE_DISABLE_OPTION=y +CONFIG_EDK2_HYPERTHREADING_OPTION=y +CONFIG_EDK2_BOOT_MENU_KEY=0x0015 +CONFIG_EDK2_SETUP_MENU_KEY=0x0008 +CONFIG_EDK2_DISABLE_OPTION_ROMS=y +CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=y diff --git a/payloads/Kconfig b/payloads/Kconfig index 49486246c6b..fe9b79bf5b7 100644 --- a/payloads/Kconfig +++ b/payloads/Kconfig @@ -57,6 +57,10 @@ endchoice source "payloads/external/*/Kconfig" +menu "Dasharo specific payload options" +source "payloads/external/*/Kconfig.dasharo" +endmenu + config PAYLOAD_FILE string "Payload path and filename" depends on PAYLOAD_ELF || PAYLOAD_FIT || PAYLOAD_FLAT_BINARY diff --git a/payloads/external/Makefile.mk b/payloads/external/Makefile.mk index 299f1eee0b9..952047a15f7 100644 --- a/payloads/external/Makefile.mk +++ b/payloads/external/Makefile.mk @@ -121,6 +121,15 @@ $(call add_intermediate, seabios_sercon, $(CBFSTOOL)) $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port endif +ifneq ($(CONFIG_SEABIOS_USB_SIGATT_TIME),) +ifneq ($(CONFIG_SEABIOS_USB_SIGATT_TIME),0) +$(call add_intermediate, seabios_usb_sigatt_time, $(CBFSTOOL)) + @printf " SeaBIOS Add sercon-port file\n" + $(if $(CONFIG_UPDATE_IMAGE),-$(CBFSTOOL) $< remove -n etc/usb-time-sigatt 2>/dev/null) + $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_USB_SIGATT_TIME) -n etc/usb-time-sigatt +endif +endif + ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) $(call add_intermediate, seabios_thread_optionroms, $(CBFSTOOL)) @printf " SeaBIOS Thread optionroms\n" @@ -156,8 +165,12 @@ payloads/external/depthcharge/depthcharge/build/depthcharge.elf depthcharge: $(D # edk2 -$(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) - $(MAKE) -C payloads/external/edk2 UefiPayloadPkg \ +ifeq ($(CONFIG_EDK2_ENABLE_IPXE),y) +IPXE_EFI := payloads/external/iPXE/ipxe/ipxe.rom +endif + +$(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) $(IPXE_EFI) + $(MAKE) -C payloads/external/edk2 DasharoPayloadPkg \ HOSTCC="$(HOSTCC)" \ CC="$(HOSTCC)" \ CONFIG_EDK2_REPOSITORY=$(CONFIG_EDK2_REPOSITORY) \ @@ -206,7 +219,76 @@ $(obj)/UEFIPAYLOAD.fd: $(DOTCONFIG) OBJCOPY_x86_64=$(OBJCOPY_x86_64) \ OBJCOPY_arm=$(OBJCOPY_arm) \ OBJCOPY_arm64=$(OBJCOPY_arm64) \ - MFLAGS= MAKEFLAGS= + MFLAGS= MAKEFLAGS= \ + CONFIG_EDK2_ABOVE_4G_MEMORY=$(CONFIG_EDK2_ABOVE_4G_MEMORY) \ + CONFIG_EDK2_BATTERY_CONFIG_OPTION=$(CONFIG_EDK2_BATTERY_CONFIG_OPTION) \ + CONFIG_EDK2_BOOT_MENU_KEY=$(CONFIG_EDK2_BOOT_MENU_KEY) \ + CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS=$(CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS) \ + CONFIG_EDK2_DASHARO_CHIPSET_CONFIG=$(CONFIG_EDK2_DASHARO_CHIPSET_CONFIG) \ + CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS=$(CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS) \ + CONFIG_EDK2_DASHARO_MEMORY_CONFIG=$(CONFIG_EDK2_DASHARO_MEMORY_CONFIG) \ + CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE=$(CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE) \ + CONFIG_EDK2_DASHARO_NETWORK_CONFIG=$(CONFIG_EDK2_DASHARO_NETWORK_CONFIG) \ + CONFIG_EDK2_DASHARO_OC_WDT_ENABLE=$(CONFIG_SOC_INTEL_COMMON_OC_WDT_ENABLE) \ + CONFIG_EDK2_DASHARO_OC_WDT_TIMEOUT=$(CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS) \ + CONFIG_EDK2_DASHARO_PCI_CONFIG=$(CONFIG_EDK2_DASHARO_PCI_CONFIG) \ + CONFIG_EDK2_DASHARO_POWER_CONFIG=$(CONFIG_EDK2_DASHARO_POWER_CONFIG) \ + CONFIG_EDK2_DASHARO_SECURITY_OPTIONS=$(CONFIG_EDK2_DASHARO_SECURITY_OPTIONS) \ + CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE=$(CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE) \ + CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE=$(CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE) \ + CONFIG_EDK2_DASHARO_SYSTEM_FEATURES=$(CONFIG_EDK2_DASHARO_SYSTEM_FEATURES) \ + CONFIG_EDK2_DASHARO_USB_CONFIG=$(CONFIG_EDK2_DASHARO_USB_CONFIG) \ + CONFIG_EDK2_DISABLE_MTRR_PROGRAMMING=$(CONFIG_EDK2_DISABLE_MTRR_PROGRAMMING) \ + CONFIG_EDK2_DISABLE_OPTION_ROMS=$(CONFIG_EDK2_DISABLE_OPTION_ROMS) \ + CONFIG_EDK2_ENABLE_BATTERY_CHECK=$(CONFIG_EDK2_ENABLE_BATTERY_CHECK) \ + CONFIG_EDK2_ENABLE_BIOS_LOCK=$(CONFIG_BOOTMEDIA_LOCK_WPRO_VBOOT_RO) \ + CONFIG_EDK2_ENABLE_FUM=$(CONFIG_DASHARO_FIRMWARE_UPDATE_MODE) \ + CONFIG_EDK2_ENABLE_SMM_BWP=$(CONFIG_BOOTMEDIA_SMM_BWP) \ + CONFIG_EDK2_FAN_CURVE_OPTION=$(CONFIG_EDK2_FAN_CURVE_OPTION) \ + CONFIG_EDK2_FAN_OFF_CURVE_OPTION=$(CONFIG_EDK2_FAN_OFF_CURVE_OPTION) \ + CONFIG_EDK2_HAVE_2ND_UART=$(CONFIG_EDK2_HAVE_2ND_UART) \ + CONFIG_EDK2_IPXE=$(CONFIG_EDK2_ENABLE_IPXE) \ + CONFIG_EDK2_IPXE_OPTION_NAME=$(CONFIG_EDK2_IPXE_OPTION_NAME) \ + CONFIG_EDK2_LAN_ROM_DRIVER=$(CONFIG_EDK2_LAN_ROM_DRIVER) \ + CONFIG_EDK2_OPAL_PASSWORD=$(CONFIG_EDK2_OPAL_PASSWORD) \ + CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE=$(CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE) \ + CONFIG_EDK2_PRINT_SOL_STRINGS=$(CONFIG_EDK2_PRINT_SOL_STRINGS) \ + CONFIG_EDK2_RAM_DISK_ENABLE=$(CONFIG_EDK2_RAM_DISK_ENABLE) \ + CONFIG_EDK2_S3_SLEEP_DEFAULT=$(CONFIG_DASHARO_PREFER_S3_SLEEP) \ + CONFIG_EDK2_SATA_PASSWORD=$(CONFIG_EDK2_SATA_PASSWORD) \ + CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE=$(CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE) \ + CONFIG_EDK2_SERIAL_ON_SUPERIO=$(CONFIG_DRIVERS_UART_8250IO) \ + CONFIG_EDK2_SETUP_MENU_KEY=$(CONFIG_EDK2_SETUP_MENU_KEY) \ + CONFIG_EDK2_SETUP_PASSWORD=$(CONFIG_EDK2_SETUP_PASSWORD) \ + CONFIG_EDK2_SHOW_CAMERA_OPTION=$(CONFIG_EDK2_SHOW_CAMERA_OPTION) \ + CONFIG_EDK2_SHOW_WIFI_BT_OPTION=$(CONFIG_EDK2_SHOW_WIFI_BT_OPTION) \ + CONFIG_EDK2_SKIP_PS2_DETECT=$(CONFIG_EDK2_SKIP_PS2_DETECT) \ + CONFIG_EDK2_SLEEP_TYPE_OPTION=$(CONFIG_EDK2_SLEEP_TYPE_OPTION) \ + CONFIG_EDK2_SYSTEM76_EC_LOGGING=$(CONFIG_EDK2_SYSTEM76_EC_LOGGING) \ + CONFIG_EDK2_VERBOSE_BUILD=$(CONFIG_EDK2_VERBOSE_BUILD) \ + CONFIG_HAVE_INTEL_ME_HAP=$(CONFIG_HAVE_INTEL_ME_HAP) \ + CONFIG_HAVE_POWER_STATE_AFTER_FAILURE=$(CONFIG_HAVE_POWER_STATE_AFTER_FAILURE) \ + CONFIG_INTEL_ME_DEFAULT_STATE=$(CONFIG_INTEL_ME_DEFAULT_STATE) \ + CONFIG_IOMMU_ENABLE=$(CONFIG_ENABLE_EARLY_DMA_PROTECTION) \ + CONFIG_MAINBOARD_POWER_FAILURE_STATE=$(CONFIG_MAINBOARD_POWER_FAILURE_STATE) \ + CONFIG_VENDOR_PCENGINES=$(CONFIG_VENDOR_PCENGINES) \ + CONFIG_EDK2_DASHARO_OC_WDT_SHOW=$(CONFIG_EDK2_DASHARO_OC_WDT_SHOW) \ + CONFIG_EDK2_DASHARO_CPU_CONFIG=$(CONFIG_EDK2_DASHARO_CPU_CONFIG) \ + CONFIG_EDK2_CORE_DISABLE_OPTION=$(CONFIG_EDK2_CORE_DISABLE_OPTION) \ + CONFIG_EDK2_HYPERTHREADING_OPTION=$(CONFIG_EDK2_HYPERTHREADING_OPTION) \ + CONFIG_EDK2_HYPERTHREADING_DEFAULT_STATE=$(CONFIG_FSP_HYPERTHREADING) \ + CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION=$(CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION) \ + CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT=$(CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT) \ + CONFIG_CPU_MAX_TEMPERATURE=$(CONFIG_CPU_MAX_TEMPERATURE) \ + CONFIG_EDK2_USE_LAPTOP_LID_LIB=$(CONFIG_EDK2_USE_LAPTOP_LID_LIB) \ + CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI=$(CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI) \ + CONFIG_DRIVERS_EFI_UPDATE_CAPSULES=$(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES) \ + CONFIG_DRIVERS_EFI_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID) \ + CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE=$(CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE) \ + CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE=$(CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE) \ + CONFIG_EDK2_USB_PORT_POWER_OPTION=$(CONFIG_EDK2_USB_PORT_POWER_OPTION) \ + CONFIG_EDK2_DGPU_POWER_OPTION=$(CONFIG_EDK2_DGPU_POWER_OPTION) + $(obj)/ShimmedUniversalPayload.elf: $(DOTCONFIG) $(MAKE) -C payloads/external/edk2 UniversalPayload \ @@ -364,13 +446,18 @@ else IPXE_SERIAL_CONSOLE = n endif +ifneq ($(CONFIG_EDK2_ENABLE_IPXE),y) cbfs-files-$(CONFIG_PXE_ROM)$(CONFIG_BUILD_IPXE) += pci$(CONFIG_PXE_ROM_ID).rom pci$(CONFIG_PXE_ROM_ID).rom-file := $(PXE_ROM_FILE) pci$(CONFIG_PXE_ROM_ID).rom-type := raw +IPXE_CROSS_COMPILE:="$(CROSS_COMPILE_$(ARCH-ramstage-y))" +else +IPXE_CROSS_COMPILE:=$(CROSS_COMPILE_x86_64) +endif payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT) $(MAKE) -C payloads/external/iPXE all \ - CROSS_COMPILE="$(CROSS_COMPILE_$(ARCH-ramstage-y))" \ + CROSS_COMPILE=$(IPXE_CROSS_COMPILE) \ PXE_ROM_PCI_ID=$(PXE_ROM_PCI_ID) \ CONFIG_IPXE_MASTER=$(CONFIG_IPXE_MASTER) \ CONFIG_IPXE_STABLE=$(CONFIG_IPXE_STABLE) \ @@ -381,7 +468,10 @@ payloads/external/iPXE/ipxe/ipxe.rom ipxe: $(DOTCONFIG) $(IPXE_CONFIG_SCRIPT) CONFIG_HAS_SCRIPT=$(CONFIG_IPXE_ADD_SCRIPT) \ CONFIG_IPXE_NO_PROMPT=$(CONFIG_IPXE_NO_PROMPT) \ CONFIG_IPXE_HAS_HTTPS=$(CONFIG_IPXE_HAS_HTTPS) \ - CONFIG_IPXE_TRUST_CMD=$(CONFIG_IPXE_TRUST_CMD) + CONFIG_IPXE_TRUST_CMD=$(CONFIG_IPXE_TRUST_CMD) \ + CONFIG_IPXE_CUSTOM_BUILD_ID=$(CONFIG_IPXE_CUSTOM_BUILD_ID) \ + CFLAGS_x86_64="$(CFLAGS_x86_64)" \ + CONFIG_IPXE_BUILD_EFI=$(CONFIG_EDK2_ENABLE_IPXE) # LinuxBoot LINUXBOOT_CROSS_COMPILE_ARCH-$(CONFIG_LINUXBOOT_X86) = x86_32 diff --git a/payloads/external/SeaBIOS/Kconfig b/payloads/external/SeaBIOS/Kconfig index b12af46a14a..5131fe3f121 100644 --- a/payloads/external/SeaBIOS/Kconfig +++ b/payloads/external/SeaBIOS/Kconfig @@ -52,6 +52,20 @@ config SEABIOS_PS2_TIMEOUT after powering on. This specifies how long SeaBIOS will wait for the keyboard controller to become ready before giving up. +config SEABIOS_USB_SIGATT_TIME + prompt "USB device attachment timeout (milliseconds)" + default 0 + int + help + The USB2 specification requires devices to signal that they are + attached within 100ms of the USB port being powered on. Some USB + devices are known to require more time. Prior to receiving an + attachment signal there is no way to know if a USB port is empty or + if it has a device attached. One may specify an amount of time here + (in milliseconds, default 100) to wait for a USB device attachment + signal. Increasing this value will also increase the overall machine + bootup time. + config SEABIOS_THREAD_OPTIONROMS prompt "Hardware init during option ROM execution" default n diff --git a/payloads/external/edk2/Kconfig b/payloads/external/edk2/Kconfig index 291da7a1f6d..f7a617a0b0b 100644 --- a/payloads/external/edk2/Kconfig +++ b/payloads/external/edk2/Kconfig @@ -229,7 +229,7 @@ config EDK2_FULL_SCREEN_SETUP config EDK2_HAVE_EFI_SHELL bool "Include EFI Shell" - default y + default n help Include the EFI shell Binary @@ -283,6 +283,14 @@ config EDK2_GOP_FILE help The name of the GOP driver file passed to edk2. +config EDK2_USE_LAPTOP_LID_LIB + bool "Use platform-specific GOP policy library" + depends on EDK2_GOP_DRIVER + default n + help + Select this option to have edk2 use a platform-specific library to get lid state. + If not selected, the lid is always assumed to be open. + config EDK2_DISABLE_TPM bool "Disable TPM support in edk2" default y if EDK2_REPO_MRCHROMEBOX && TPM_GOOGLE_CR50 && SOC_AMD_COMMON diff --git a/payloads/external/edk2/Kconfig.dasharo b/payloads/external/edk2/Kconfig.dasharo new file mode 100644 index 00000000000..e1fbad03a9c --- /dev/null +++ b/payloads/external/edk2/Kconfig.dasharo @@ -0,0 +1,394 @@ +if PAYLOAD_EDK2 + +config EDK2_SYSTEM76_EC_LOGGING + bool "Enable edk2 logging to System76 EC" + default n + depends on EC_SYSTEM76_EC || EC_DASHARO_EC + help + Select this option if you want to enable edk2 logging to S76 EC. + +config EDK2_SKIP_PS2_DETECT + bool "Skip PS/2 keyboard detection check" + depends on EDK2_PS2_SUPPORT + default n + help + Skips checking for the PS/2 keyboard presence and assumes the PS/2 + keyboard is connected. Useful for laptops, where PS/2 keyboard is + always connected, to save a precious second or two of boot time. + +config EDK2_ENABLE_IPXE + bool "Include iPXE in edk2 payload" + default n + select PXE + help + Instructs coreboot build system to build iPXE EFI target and include + it in the EDK2 payload. + +config EDK2_IPXE_OPTION_NAME + string "iPXE option name" + depends on EDK2_ENABLE_IPXE + default "iPXE Network Boot" + help + Configures how the iPXE boot option should be displayed in boot menu + of EDK2 Payload. This name will be passed as PCD to the EDK2 build + system. + +config EDK2_SECURE_BOOT_DEFAULT_ENABLE + bool "Set Secure Boot state to enabled by default" + default y + depends on EDK2_SECURE_BOOT_SUPPORT + help + Sets the UEFI Secure Boot state to enabled by default. + +config EDK2_SATA_PASSWORD + bool "Enable TianoCore SATA disk password" + default n + help + Enable SATA disk password suupport in the TianoCore payload. + +config EDK2_OPAL_PASSWORD + bool "Enable TianoCore TCG OPAL password" + default n + help + Enables TCG OPAL disk password in the TianoCore Payload. + +config EDK2_SETUP_PASSWORD + bool "Enable Setup Menu password" + default n + help + Enables setup menu password in the TianoCore Payload. + +config EDK2_PERFORMANCE_MEASUREMENT_ENABLE + bool "Enable firmware performance measurement" + default n + help + Enables firmware performance measurement in the TianoCore Payload. + The measurements will be exposed to OS via FPDT ACPI table. Should be + used in conjunction with EDK2_CPU_TIMER_LIB to match the coreboot + measurement made with TSC. If EDK2_CPU_TIMER_LIB cannot be enabled on + the platform, the counters wil be mismatched and the performance will + not be properly reported by OS. + +# DasharoModulePkg specific options + +config EDK2_DASHARO_SYSTEM_FEATURES + bool "Enable Dasharo System Features menu in EDK2" + default n + help + Enables Dasharo System Features submenu in the EDK2 setup menu. + +if EDK2_DASHARO_SYSTEM_FEATURES + +config EDK2_DASHARO_SECURITY_OPTIONS + bool "Enable EDK2 Dasharo Security Options Menu" + default n + help + Enables the security configuration submenu in Dasharo System Features. + +config EDK2_SHOW_CAMERA_OPTION + bool "Show Camera option in Dasharo Security Options Menu" + depends on EDK2_DASHARO_SECURITY_OPTIONS + help + Shows the Camera option in Dasharo Security Options submenu in + Dasharo System Features menu. + +config EDK2_SHOW_WIFI_BT_OPTION + bool "Show WiFi/BT option in Dasharo Security Options Menu" + depends on EDK2_DASHARO_SECURITY_OPTIONS + help + Shows the WiFi/BT option in Dasharo Security Options submenu in + Dasharo System Features menu. + +config EDK2_DASHARO_INTEL_ME_OPTIONS + bool "Enable EDK2 Dasharo ME Configuration Menu" + default n + help + Enables the Intel ME configuration submenu in Dasharo System Features. + +config EDK2_DASHARO_USB_CONFIG + bool "Enable EDK2 Dasharo USB Configuration Menu" + default n + help + Enables the EDK2 USB stack configuration submenu in Dasharo System Features. + +config EDK2_DASHARO_NETWORK_CONFIG + bool "Enable EDK2 Dasharo Network Stack Configuration Menu" + default n + help + Enables the EDK2 network stack configuration submenu in Dasharo System Features. + +config EDK2_DASHARO_CHIPSET_CONFIG + bool "Enable EDK2 Dasharo Chipset Configuration Menu" + default n + help + Enables the EDK2 chipset configuration submenu in Dasharo System Features menu. + +config EDK2_DASHARO_OC_WDT_SHOW + bool "Enable watchdog configuration options" + depends on EDK2_DASHARO_CHIPSET_CONFIG + default y if SOC_INTEL_COMMON_OC_WDT_ENABLE + default n + help + Enable watchdog-related options in the Dasharo Chipset Configuration + submenu. + +config EDK2_DASHARO_POWER_CONFIG + bool "Enable EDK2 Dasharo Power Configuration Menu" + default n + help + Enables the EDK2 power configuration submenu in Dasharo System Features menu. + +config EDK2_SLEEP_TYPE_OPTION + bool "Show Sleep Type option in Dasharo Power Configuration Menu" + default n + depends on EDK2_DASHARO_POWER_CONFIG + help + Shows the Sleep Type option in EDK2 power configuration submenu in + Dasharo System Features menu. + +config EDK2_FAN_CURVE_OPTION + bool "Show Fan Curve option in Dasharo Power Configuration Menu" + depends on EDK2_DASHARO_POWER_CONFIG + default n + help + Shows the Fan Curve option in EDK2 power configuration submenu in + Dasharo System Features menu. + +config EDK2_FAN_OFF_CURVE_OPTION + bool "Show Fan Off option in the Fan Curve option list" + depends on EDK2_FAN_CURVE_OPTION + default n + help + Shows the Fan Off option when selecting Fan Curve in EDK2 power + configuration submenu in Dasharo System Features menu. + +config EDK2_BATTERY_CONFIG_OPTION + bool "Show Battery Threshold options in Dasharo Power Configuration Menu" + default n + depends on EDK2_DASHARO_POWER_CONFIG + help + Enables battery threshold options in the EDK2 power management + configuration submenu. + +config EDK2_CPU_THROTTLING_THRESHOLD_OPTION + bool "Display CPU throttling threshold option" + default n + depends on EDK2_DASHARO_POWER_CONFIG + help + Enables setting a custom CPU throttling threshold temperature + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + int "CPU throttling threshold default value" + depends on EDK2_CPU_THROTTLING_THRESHOLD_OPTION + default 20 + range 0 63 + help + Board-specific CPU throttling threshold temperature default value + +config EDK2_USB_PORT_POWER_OPTION + bool "Show USB Port Power option in Dasharo Power Configuration Menu" + default n + depends on EDK2_DASHARO_POWER_CONFIG + help + Shows the USB Port Power option in EDK2 power configuration submenu in + Dasharo System Features menu. + +config EDK2_DGPU_POWER_OPTION + bool "Show DGPU power option in Dasharo Power Configuration Menu" + default n + depends on EDK2_DASHARO_POWER_CONFIG + help + Shows the DGPU power option in EDK2 power configuration submenu in + Dasharo System Features menu. + +config EDK2_DASHARO_PCI_CONFIG + bool "Enable EDK2 Dasharo PCI/PCIe Configuration Menu" + default n + help + Enables the EDK2 PCI/PCIe configuration submenu in Dasharo System Features menu. + +config EDK2_DASHARO_MEMORY_CONFIG + bool "Enable EDK2 Dasharo Memory Configuration Menu" + default n + help + Enables the EDK2 Memory configuration submenu in Dasharo System Features menu. + +config EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE + bool "Enable EDK2 network boot option by default" + default n + help + Enables the network boot option in EDK2 by default. + +config EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE + bool "Enable serial console redirection by default" + depends on EDK2_SERIAL_SUPPORT + default n + help + Enable serial port output in edk2 by default. Serial output limits + the performance of edk2's FrontPage. + +config EDK2_HAVE_2ND_UART + bool "Have second serial port for console redirection" + depends on EDK2_SERIAL_SUPPORT + depends on DRIVERS_UART_8250IO + default n + help + Enable support for two serial ports in edk2. + +config EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE + bool "Enable second serial port console redirection by default" + depends on EDK2_SERIAL_SUPPORT + depends on EDK2_HAVE_2ND_UART + default n + help + Enable serial port output on second UART in edk2 by default. Serial + output limits the performance of edk2's FrontPage. + +config EDK2_DASHARO_CPU_CONFIG + bool "Enable EDK2 Dasharo CPU Configuration Menu" + default n + help + Enables the EDK2 CPU configuration submenu in Dasharo System Features menu. + +config EDK2_CORE_DISABLE_OPTION + bool "Show CPU core disabling option in Dasharo CPU Configuration Menu" + depends on EDK2_DASHARO_CPU_CONFIG + help + Shows the CPU core disabling option in EDK2 CPU configuration submenu in + Dasharo System Features menu. + +config EDK2_HYPERTHREADING_OPTION + bool "Show CPU Hyper-Threading option in Dasharo CPU Configuration Menu" + depends on EDK2_DASHARO_CPU_CONFIG + default n + help + Shows the CPU Hyper-Threading option in EDK2 CPU configuration submenu in + Dasharo System Features menu. + +endif + +config EDK2_BOOT_MENU_KEY + hex "TianoCore boot menu key" + default 0x0016 + help + Select the TianoCore payload boot menu key: + UP 0x0001 + DOWN 0x0002 + RIGHT 0x0003 + LEFT 0x0004 + HOME 0x0005 + END 0x0006 + INSERT 0x0007 + DELETE 0x0008 + F1 0x000B + F2 0x000C + F3 0x000D + F4 0x000E + F5 0x000F + F6 0x0010 + F7 0x0011 + F8 0x0012 + F9 0x0013 + F10 0x0014 + F11 0x0015 + F12 0x0016 + ESC 0x0017 + +config EDK2_SETUP_MENU_KEY + hex "TianoCore setup menu key" + default 0x0017 + help + Select the TianoCore payload setup menu key: + UP 0x0001 + DOWN 0x0002 + RIGHT 0x0003 + LEFT 0x0004 + HOME 0x0005 + END 0x0006 + INSERT 0x0007 + DELETE 0x0008 + F1 0x000B + F2 0x000C + F3 0x000D + F4 0x000E + F5 0x000F + F6 0x0010 + F7 0x0011 + F8 0x0012 + F9 0x0013 + F10 0x0014 + F11 0x0015 + F12 0x0016 + ESC 0x0017 + +config EDK2_DISABLE_MTRR_PROGRAMMING + bool "Disable MTRR programming in EDK2 Payload" + default y + help + Disables MTRRs programming in the TianoCore Payload. + +config EDK2_ENABLE_BATTERY_CHECK + bool "Enable battery level check" + default n + help + Enables the battery level check in the UEFI Payload. If the battery + level is too low, a pop up will appear with appropriate warning and + prevent booting, which could cause disk data corruption. + +config EDK2_DISABLE_OPTION_ROMS + bool "Disable OptionROM loading by default" + default n + help + Disables OptionROM loading and execution in UEFI Payload. By default + all PCI OptionROMs are loaded and executed. + +config EDK2_PRINT_SOL_STRINGS + bool "Print Sign Of Life string on boot" + default n + help + Prints the BIOS and, if available, the EC version on the screen + during boot prompt in UEFI Payload. + +config EDK2_RAM_DISK_ENABLE + bool "Enable RAM Disk support" + default n + help + Enable support for RAM Disks in EDK2 UEFIPayload. + +config EDK2_LAN_ROM_DRIVER + string "Optional LAN ROM driver file" + help + Integrates LAN ROM driver in TianoCore Payload. Takes an EFI driver + as input. + +config EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS + bool "Create boot entries for pre-installed OSes" + default n + help + Tell UEFIPaylaod to scan available EFI System Partitions and create + boot options from the bootloader binaries found on the disks. + +config EDK2_USE_UEFIVAR_BACKED_TPM_PPI + bool "Use UEFI variable-backed TPM PPI" + default n + depends on !EDK2_DISABLE_TPM + help + Tell UEFIPayload to use TPM PPI buffer in UEFI variables. Workaround + for platform-specific issues causing the RAM to not be preserved + across reboots. + + If unsure, say N. + +config EDK2_ENABLE_FAST_BOOT_FEATURE + bool "Enable fast boot feature in EDK2 Payload" + default n + help + Enables fast boot option in the TianoCore Payload. + +config EDK2_ENABLE_QUIET_BOOT_FEATURE + bool "Enable quiet boot feature in EDK2 Payload" + default n + help + Enables quiet boot option in the TianoCore Payload. + +endif diff --git a/payloads/external/edk2/Makefile b/payloads/external/edk2/Makefile index 6464e9f8514..71302213ec3 100644 --- a/payloads/external/edk2/Makefile +++ b/payloads/external/edk2/Makefile @@ -8,6 +8,7 @@ export WORKSPACE := $(CURDIR)/workspace export EDK2_PATH := $(WORKSPACE)/$(word 3,$(subst /, ,$(CONFIG_EDK2_REPOSITORY))) ifeq ($(CONFIG_EDK2_USE_EDK2_PLATFORMS),y) +BUILD_STR += -D USE_EDK2_PLATFORMS=TRUE export EDK2_PLATFORMS_PATH := $(WORKSPACE)/edk2-platforms export PACKAGES_PATH := $(EDK2_PATH):\ $(EDK2_PLATFORMS_PATH)/Platform/Intel:\ @@ -25,8 +26,10 @@ endif OBJCOPY = $(GCC_PREFIX)objcopy +PAYLOAD_NAME=DasharoPayloadPkg + ifeq ($(CONFIG_EDK2_UEFIPAYLOAD),y) -BUILD_STR = -p UefiPayloadPkg/UefiPayloadPkg.dsc +BUILD_STR += -p $(PAYLOAD_NAME)/$(PAYLOAD_NAME).dsc endif BUILD_STR += -t COREBOOT BUILD_STR += -D BOOTLOADER=COREBOOT @@ -112,8 +115,14 @@ ifeq ($(CONFIG_EDK2_SECURE_BOOT_SUPPORT), y) BUILD_STR += -D SECURE_BOOT_ENABLE=TRUE endif # PCIEXP_SUPPORT_RESIZABLE_BARS = FALSE -ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y) -BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE +#ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS), y) +#BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdPcieResizableBarSupport=TRUE +#endif +# CAPSULE_SUPPORT = FALSE +# CAPSULE_MAIN_FW_GUID = +ifneq ($(CONFIG_DRIVERS_EFI_UPDATE_CAPSULES),) +BUILD_STR += -D CAPSULE_SUPPORT=TRUE +BUILD_STR += -D CAPSULE_MAIN_FW_GUID=$(CONFIG_DRIVERS_EFI_MAIN_FW_GUID) endif # @@ -128,6 +137,10 @@ endif # GOP_DRIVER = FALSE ifeq ($(CONFIG_EDK2_GOP_DRIVER), y) BUILD_STR += -D USE_PLATFORM_GOP=TRUE +# USE_LAPTOP_LID_LIB = FALSE +ifeq ($(CONFIG_EDK2_USE_LAPTOP_LID_LIB), y) +BUILD_STR += -D USE_LAPTOP_LID_LIB=TRUE +endif endif # PRIORITIZE_INTERNAL = FALSE ifeq ($(CONFIG_EDK2_PRIORITIZE_INTERNAL),y) @@ -150,6 +163,262 @@ ifeq ($(CONFIG_EDK2_USE_LAPIC_TIMER),y) BUILD_STR += -D TIMER_SUPPORT=LAPIC endif +# +# The Dasharo repository has the following additional options: +# +ifneq ($(CONFIG_EDK2_DISABLE_TPM),y) +ifeq ($(CONFIG_EDK2_USE_UEFIVAR_BACKED_TPM_PPI),y) +BUILD_STR += -D USE_UEFIVAR_BACKED_TPM_PPI=TRUE +endif +endif +# ABOVE_4G_MEMORY = TRUE +ifneq ($(CONFIG_EDK2_ABOVE_4G_MEMORY),y) +BUILD_STR += -D ABOVE_4G_MEMORY=FALSE +endif +# PcdSerialRedirectionDefaultState = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION_DEFAULT_ENABLE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSerialRedirectionDefaultState=TRUE +endif +# SERIAL_TERMINAL = FALSE +ifeq ($(CONFIG_EDK2_SERIAL_SUPPORT),y) +BUILD_STR += -D DISABLE_SERIAL_TERMINAL=FALSE +BUILD_STR += -D SERIAL_TERMINAL=TRUE +ifeq ($(CONFIG_EDK2_HAVE_2ND_UART),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdHave2ndUart=TRUE +ifeq ($(CONFIG_EDK2_DASHARO_SERIAL_REDIRECTION2_DEFAULT_ENABLE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSerialRedirection2DefaultState=TRUE +endif +endif # CONFIG_EDK2_HAVE_2ND_UART +endif # SERIAL_TERMINAL +# PS2_KEYBOARD_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_PS2_SUPPORT),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowPs2Option=TRUE +# SKIP_PS2_DETECT = FALSE +ifeq ($(CONFIG_EDK2_SKIP_PS2_DETECT),y) +BUILD_STR += --pcd g$(PAYLOAD_NAME)TokenSpaceGuid.PcdSkipPs2Detect=TRUE +endif # SKIP_PS2_DETECT +else +BUILD_STR += --pcd g$(PAYLOAD_NAME)TokenSpaceGuid.PcdSkipPs2Detect=TRUE +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowPs2Option=FALSE +endif # PS2_KEYBOARD_ENABLE +# SYSTEM76_EC_LOGGING = FALSE +ifeq ($(CONFIG_EDK2_SYSTEM76_EC_LOGGING),y) +BUILD_STR += -D SYSTEM76_EC_LOGGING=TRUE +endif +# NETWORK_IPXE = FALSE +ifeq ($(CONFIG_EDK2_IPXE),y) +BUILD_STR += -D NETWORK_IPXE=TRUE +BUILD_STR += --pcd g$(PAYLOAD_NAME)TokenSpaceGuid.PcdiPXEOptionName=L"$(CONFIG_EDK2_IPXE_OPTION_NAME)" +endif +# SECURE_BOOT_DEFAULT_ENABLE = TRUE +ifneq ($(CONFIG_EDK2_SECURE_BOOT_DEFAULT_ENABLE),y) +BUILD_STR += -D SECURE_BOOT_DEFAULT_ENABLE=FALSE +endif +# SATA_PASSWORD_ENABLE = TRUE +ifeq ($(CONFIG_EDK2_SATA_PASSWORD),y) +BUILD_STR += -D SATA_PASSWORD_ENABLE=TRUE +endif +# OPAL_PASSWORD_ENABLE = TRUE +ifeq ($(CONFIG_EDK2_OPAL_PASSWORD),y) +BUILD_STR += -D OPAL_PASSWORD_ENABLE=TRUE +endif +# SETUP_PASSWORD_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_SETUP_PASSWORD),y) +BUILD_STR += -D SETUP_PASSWORD_ENABLE=TRUE +endif +# NETWORK_LAN_ROM = FALSE +ifneq ($(CONFIG_EDK2_LAN_ROM_DRIVER),) +BUILD_STR += -D NETWORK_LAN_ROM=TRUE +endif +# DISABLE_MTRR_PROGRAMMING = TRUE +ifneq ($(CONFIG_EDK2_DISABLE_MTRR_PROGRAMMING),y) +BUILD_STR += -D DISABLE_MTRR_PROGRAMMING=FALSE +endif +# IOMMU_ENABLE = FALSE +ifeq ($(CONFIG_IOMMU_ENABLE),y) +BUILD_STR += -D IOMMU_ENABLE=TRUE +endif +# DASHARO_SYSTEM_FEATURES = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_SYSTEM_FEATURES),y) +BUILD_STR += -D DASHARO_SYSTEM_FEATURES_ENABLE=TRUE +endif +# DASHARO_SECURITY_OPTIONS = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_SECURITY_OPTIONS),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowSecurityMenu=TRUE +endif +# DASHARO_INTEL_ME_OPTIONS = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_INTEL_ME_OPTIONS),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowIntelMeMenu=TRUE +endif +# DASHARO_NETWORK_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_NETWORK_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowNetworkMenu=TRUE +endif +# DASHARO_USB_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_USB_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowUsbMenu=TRUE +endif +# DASHARO_CHIPSET_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_CHIPSET_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowChipsetMenu=TRUE +endif +# Always set the default power failure state to some value +ifeq ($(CONFIG_HAVE_POWER_STATE_AFTER_FAILURE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdDefaultPowerFailureState=$(CONFIG_MAINBOARD_POWER_FAILURE_STATE) +else +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdDefaultPowerFailureState=0 +endif +# DASHARO_POWER_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_POWER_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowPowerMenu=TRUE + +ifneq ($(CONFIG_EDK2_SLEEP_TYPE_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowSleepType=FALSE +endif # CONFIG_EDK2_SLEEP_TYPE_OPTION + +ifeq ($(CONFIG_EDK2_FAN_CURVE_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowFanCurve=TRUE +ifeq ($(CONFIG_EDK2_FAN_OFF_CURVE_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowFanCurveOffOption=TRUE +endif # CONFIG_EDK2_FAN_OFF_CURVE_OPTION +endif # CONFIG_EDK2_FAN_CURVE_OPTION + +ifeq ($(CONFIG_EDK2_BATTERY_CONFIG_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowBatteryThresholds=TRUE +endif + +ifeq ($(CONFIG_EDK2_USB_PORT_POWER_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowUsbPowerOption=TRUE +endif + +ifeq ($(CONFIG_EDK2_DGPU_POWER_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPowerMenuShowDGPUPowerOption=TRUE +endif + +endif # CONFIG_EDK2_DASHARO_POWER_CONFIG +# DASHARO_PCI_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_PCI_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowPciMenu=TRUE +endif +# DASHARO_MEMORY_CONFIG = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_MEMORY_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowMemoryMenu=TRUE +endif +# DASHARO_NETWORK_BOOT_DEFAULT_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdDefaultNetworkBootEnable=TRUE +endif +ifeq ($(CONFIG_EDK2_DASHARO_OC_WDT_SHOW),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdOcWdtEnableDefault=TRUE +endif +ifeq ($(CONFIG_EDK2_DASHARO_OC_WDT_SHOW),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowOcWdtOptions=TRUE +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdOcWdtTimeoutDefault=$(CONFIG_EDK2_DASHARO_OC_WDT_TIMEOUT) +endif +# PCIEXP_SUPPORT_RESIZABLE_BARS = FALSE +ifeq ($(CONFIG_PCIEXP_SUPPORT_RESIZABLE_BARS),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdPciMenuShowResizeableBars=TRUE +endif +# BATTERY_CHECK = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_BATTERY_CHECK),y) +BUILD_STR += -D BATTERY_CHECK=TRUE +endif +# LOAD_OPTION_ROMS = TRUE +ifeq ($(CONFIG_EDK2_DISABLE_OPTION_ROMS),y) +BUILD_STR += -D LOAD_OPTION_ROMS=FALSE +endif +# PRINT_SOL_STRINGS = FALSE +ifeq ($(CONFIG_EDK2_PRINT_SOL_STRINGS),y) +BUILD_STR += --pcd g$(PAYLOAD_NAME)TokenSpaceGuid.PcdPrintSolStrings=TRUE +endif +# CREATE_PREINSTALLED_BOOT_OPTIONS = FALSE +ifeq ($(CONFIG_EDK2_CREATE_PREINSTALLED_BOOT_OPTIONS),y) +BUILD_STR += --pcd gEfiMdeModulePkgTokenSpaceGuid.PcdCreatePreInstalledBootOptions=TRUE +endif +# SHOW_CAMERA_OPTION = FALSE +ifeq ($(CONFIG_EDK2_SHOW_CAMERA_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSecurityShowCameraOption=TRUE +endif +# SHOW_WIFI_BT_OPTION = FALSE +ifeq ($(CONFIG_EDK2_SHOW_WIFI_BT_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSecurityShowWiFiBtOption=TRUE +endif +# PERFORMANCE_MEASUREMENT_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_PERFORMANCE_MEASUREMENT_ENABLE),y) +BUILD_STR += -D PERFORMANCE_MEASUREMENT_ENABLE=TRUE +endif +ifneq ($(CONFIG_HAVE_INTEL_ME_HAP),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdIntelMeHapAvailable=FALSE +endif +ifneq ($(CONFIG_INTEL_ME_DEFAULT_STATE),) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdIntelMeDefaultState=$(CONFIG_INTEL_ME_DEFAULT_STATE) +endif +# RAM_DISK_ENABLE = FALSE +ifeq ($(CONFIG_EDK2_RAM_DISK_ENABLE),y) +BUILD_STR += -D RAM_DISK_ENABLE=TRUE +endif +# APU_CONFIG_ENABLE = FALSE +ifeq ($(CONFIG_VENDOR_PCENGINES),y) +BUILD_STR += -D APU_CONFIG_ENABLE=TRUE +endif + +BUILD_STR += -D BOOT_MENU_KEY=$(CONFIG_EDK2_BOOT_MENU_KEY) +BUILD_STR += -D SETUP_MENU_KEY=$(CONFIG_EDK2_SETUP_MENU_KEY) + +# PcdShowLockBios = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_BIOS_LOCK),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowLockBios=TRUE +endif +# PcdShowSmmBwp = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_SMM_BWP),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowSmmBwp=TRUE +endif +# PcdSleepTypeDefaultS3 = FALSE +ifeq ($(CONFIG_EDK2_S3_SLEEP_DEFAULT),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdSleepTypeDefaultS3=TRUE +endif +# PcdShowFum = TRUE +ifneq ($(CONFIG_EDK2_ENABLE_FUM),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowFum=FALSE +endif +# UART_ON_SUPERIO = FALSE +ifeq ($(CONFIG_EDK2_SERIAL_ON_SUPERIO),y) +BUILD_STR += -D UART_ON_SUPERIO=TRUE +endif +# PcdShowCpuMenu = FALSE +ifeq ($(CONFIG_EDK2_DASHARO_CPU_CONFIG),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowCpuMenu=TRUE +endif +# PcdShowCpuCoreDisable = FALSE +ifeq ($(CONFIG_EDK2_CORE_DISABLE_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowCpuCoreDisable=TRUE +endif +# PcdShowCpuHyperThreading = FALSE +ifeq ($(CONFIG_EDK2_HYPERTHREADING_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowCpuHyperThreading=TRUE +endif +# PcdCpuHyperThreadingDefault = TRUE +ifneq ($(CONFIG_EDK2_HYPERTHREADING_DEFAULT_STATE),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdCpuHyperThreadingDefault=FALSE +endif +# PcdShowCpuThrottlingThreshold = FALSE +ifeq ($(CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_OPTION),y) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdShowCpuThrottlingThreshold=TRUE +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdCpuThrottlingOffsetDefault=$(CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT) +# PcdCpuMaxTemperature = 100 +ifneq ($(CONFIG_CPU_MAX_TEMPERATURE),) +BUILD_STR += --pcd gDasharoSystemFeaturesTokenSpaceGuid.PcdCpuMaxTemperature=$(CONFIG_CPU_MAX_TEMPERATURE) +endif +endif +# PcdFastBootFeatureEnabled = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_FAST_BOOT_FEATURE),y) +BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdFastBootFeatureEnabled=TRUE +endif +# PcdQuietBootFeatureEnabled = FALSE +ifeq ($(CONFIG_EDK2_ENABLE_QUIET_BOOT_FEATURE),y) +BUILD_STR += --pcd gEfiMdePkgTokenSpaceGuid.PcdQuietBootFeatureEnabled=TRUE +endif + endif # @@ -169,7 +438,7 @@ ifneq ($(CONFIG_EDK2_CUSTOM_BUILD_PARAMS),) BUILD_STR += $(CONFIG_EDK2_CUSTOM_BUILD_PARAMS) endif -all: UefiPayloadPkg +all: $(PAYLOAD_NAME) $(WORKSPACE): mkdir $(WORKSPACE) @@ -193,12 +462,12 @@ $(EDK2_PLATFORMS_PATH): $(WORKSPACE) $(EDK2_PATH): $(WORKSPACE) if [ ! -d "$(EDK2_PATH)" ]; then \ - git clone --recurse-submodules $(CONFIG_EDK2_REPOSITORY) $(EDK2_PATH) -j5; \ + git clone $(CONFIG_EDK2_REPOSITORY) $(EDK2_PATH) -j5; \ fi cd $(EDK2_PATH); \ - git checkout MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true; \ - if [ -e UefiPayloadPkg/ShimLayer/UniversalPayload.o ]; then \ - rm UefiPayloadPkg/ShimLayer/UniversalPayload.o; \ + git checkout -- MdeModulePkg/Logo/Logo.bmp > /dev/null 2>&1 || true; \ + if [ -e $(PAYLOAD_NAME)/ShimLayer/UniversalPayload.o ]; then \ + rm $(PAYLOAD_NAME)/ShimLayer/UniversalPayload.o; \ fi; \ echo " Fetching new commits from $(CONFIG_EDK2_REPOSITORY)"; \ git fetch origin 2>/dev/null; \ @@ -227,10 +496,29 @@ logo: $(EDK2_PATH) gop_driver: $(EDK2_PATH) if [ -n "$(CONFIG_EDK2_GOP_DRIVER)" ]; then \ echo "Using GOP driver $(CONFIG_EDK2_GOP_FILE)"; \ - cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/UefiPayloadPkg/IntelGopDriver.efi; \ - cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/UefiPayloadPkg/vbt.bin; \ + cp $(top)/$(CONFIG_EDK2_GOP_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/IntelGopDriver.efi; \ + cp $(top)/$(CONFIG_INTEL_GMA_VBT_FILE) $(EDK2_PATH)/$(PAYLOAD_NAME)/vbt.bin; \ fi; \ +lan_rom: $(EDK2_PATH) + case "$(CONFIG_EDK2_LAN_ROM_DRIVER)" in \ + "") ;; \ + /*) mkdir -p $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/; \ + cp $(CONFIG_EDK2_LAN_ROM_DRIVER) \ + $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/LanRom.efi;; \ + *) mkdir -p $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/; \ + cp $(top)/$(CONFIG_EDK2_LAN_ROM_DRIVER) \ + $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/LanRom.efi;; \ + esac \ + +ipxe_rom: $(EDK2_PATH) + if [ "$(CONFIG_EDK2_IPXE)" == "y" ]; then \ + echo " Including externally built iPXE"; \ + mkdir -p $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/; \ + cp $(top)/payloads/external/iPXE/ipxe/ipxe.rom \ + $(EDK2_PATH)/$(PAYLOAD_NAME)/NetworkDrivers/ipxe.efi; \ + fi \ + checktools: echo -n "EDK2: Checking uuid-dev:" echo "#include " > libtest.c @@ -268,7 +556,7 @@ print: -e 's/s /Build: Silent/' \ -e 's/t /Toolchain: /' -prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver +prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver lan_rom ipxe_rom cd $(WORKSPACE); \ source $(EDK2_PATH)/edksetup.sh; \ unset CC; $(MAKE) -C $(EDK2_PATH)/BaseTools 2>&1; \ @@ -277,49 +565,49 @@ prep: $(EDK2_PATH) $(EDK2_PLATFORMS_PATH) clean checktools logo gop_driver cat ../tools_def.txt >> $(EDK2_PATH)/Conf/tools_def.txt; \ fi; \ -$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd: \ +$(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd: \ prep print cd $(WORKSPACE); \ source $(EDK2_PATH)/edksetup.sh; \ echo -n "EDK2: Building... "; \ build -a IA32 -a X64 -b $(RELEASE_STR) $(BUILD_STR) \ - -y $(WORKSPACE)/Build/UefiPayloadPkgX64/UEFIPAYLOAD.txt; \ + -y $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/UEFIPAYLOAD.txt; \ if [ ! -f $@ ]; then \ echo "Failed!"; \ exit 1; \ fi echo "Success!"; \ -$(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf: \ +$(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/UniversalPayload.elf: \ prep print cd $(WORKSPACE); \ source $(EDK2_PATH)/edksetup.sh; \ echo -n "EDK2: Building... "; \ - $(EDK2_PATH)/UefiPayloadPkg/UniversalPayloadBuild.sh -a IA32 -b $(RELEASE_STR) $(BUILD_STR) + $(EDK2_PATH)/$(PAYLOAD_NAME)/UniversalPayloadBuild.sh -a IA32 -b $(RELEASE_STR) $(BUILD_STR) if [ ! -f $@ ]; then \ echo "Failed!"; \ exit 1; \ fi echo "Success!"; \ -$(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll: \ - $(WORKSPACE)/Build/UefiPayloadPkgX64/UniversalPayload.elf prep - cd $(WORKSPACE)/Build/UefiPayloadPkgX64 && \ +$(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/IA32/$(PAYLOAD_NAME)/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll: \ + $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/UniversalPayload.elf prep + cd $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64 && \ $(OBJCOPY) -I binary UniversalPayload.elf -O elf32-i386 -B i386 \ - $(EDK2_PATH)/UefiPayloadPkg/ShimLayer/UniversalPayload.o; \ + $(EDK2_PATH)/$(PAYLOAD_NAME)/ShimLayer/UniversalPayload.o; \ cd $(WORKSPACE) && \ source $(EDK2_PATH)/edksetup.sh; \ - build -p UefiPayloadPkg/UefiPayloadPkg.dsc -b $(RELEASE_STR) -a IA32 -a X64 \ - -m UefiPayloadPkg/ShimLayer/ShimLayer.inf \ + build -p $(PAYLOAD_NAME)/$(PAYLOAD_NAME).dsc -b $(RELEASE_STR) -a IA32 -a X64 \ + -m $(PAYLOAD_NAME)/ShimLayer/ShimLayer.inf \ -t COREBOOT -D BOOTLOADER=COREBOOT -D SHIMLAYER=TRUE \ - -y $(WORKSPACE)/Build/UefiPayloadPkgX64/ShimLayer.txt + -y $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/ShimLayer.txt -UefiPayloadPkg: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd - mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd \ +$(PAYLOAD_NAME): $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd + mv $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/FV/UEFIPAYLOAD.fd \ ../../../build/UEFIPAYLOAD.fd -UniversalPayload: $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll - mv $(WORKSPACE)/Build/UefiPayloadPkgX64/$(RELEASE_STR)_COREBOOT/IA32/UefiPayloadPkg/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll \ +UniversalPayload: $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/IA32/$(PAYLOAD_NAME)/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll + mv $(WORKSPACE)/Build/$(PAYLOAD_NAME)X64/$(RELEASE_STR)_COREBOOT/IA32/$(PAYLOAD_NAME)/ShimLayer/ShimLayer/DEBUG/ShimLayer.dll \ ../../../build/ShimmedUniversalPayload.elf clean: @@ -328,4 +616,4 @@ clean: distclean: rm -rf $(WORKSPACE) -.PHONY: $(EDK2_PATH) checktools logo UefiPayloadPkg UniversalPayload clean distclean +.PHONY: $(EDK2_PATH) checktools logo $(PAYLOAD_NAME) UniversalPayload clean distclean diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index ff25d81957f..b90b8f8a433 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -54,12 +54,12 @@ choice default IPXE_STABLE config IPXE_STABLE - bool "2022.1" + bool "2023.8" help iPXE uses a rolling release with no stable version, for reproducibility, use the last commit of a given month as the 'stable' version. - This is iPXE from the end of January, 2022. + This is iPXE from the end of August, 2023. config IPXE_MASTER bool "master" @@ -70,7 +70,9 @@ endchoice config IPXE_SERIAL_CONSOLE bool "Enable iPXE serial console" - def_bool y + default n if PAYLOAD_EDK2 && EDK2_ENABLE_IPXE + default n if PAYLOAD_SEABIOS && SEABIOS_ADD_SERCON_PORT_FILE + default y help Enable/disable iPXE serial console. Since SeaBIOS supports serial console this option might be helpful to avoid duplicated output. @@ -116,6 +118,13 @@ config IPXE_TRUST_CMD digital signature of file prior loading it, and restrict to loading trusted files only. +config IPXE_CUSTOM_BUILD_ID + string "iPXE custom build_id variable" + default "" + help + This option allows user to customize build_id for reproducible builds. + It is 32-bit hexadecimal number without "0x" prefix. + endif # BUILD_IPXE endmenu diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 7ec8126c977..05b4a6e7953 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -1,15 +1,36 @@ ## SPDX-License-Identifier: GPL-2.0-only -# 2022.1 - Last commit of January 2022 +# 2023.8 - Last commit of August 2023 # When updating, change the name both here and in payloads/external/iPXE/Kconfig -STABLE_COMMIT_ID=6ba671acd922ee046b257c5119b8a0f64d275473 + +# Temporarily Dasharo fork is used until i225/i226 native support is merged. +STABLE_COMMIT_ID=63ed3e352f2e65b26b15a847961440cb4dad0318 TAG-$(CONFIG_IPXE_MASTER)=origin/master TAG-$(CONFIG_IPXE_STABLE)=$(STABLE_COMMIT_ID) project_name=iPXE project_dir=ipxe -project_git_repo=https://git.ipxe.org/ipxe.git +project_git_repo=https://github.com/Dasharo/ipxe.git + +unexport KCONFIG_AUTOHEADER +unexport KCONFIG_AUTOCONFIG +unexport KCONFIG_DEPENDENCIES +unexport KCONFIG_SPLITCONFIG +unexport KCONFIG_TRISTATE +unexport KCONFIG_NEGATIVES + +ifneq ($(CONFIG_IPXE_CUSTOM_BUILD_ID),) +PXE_MAKE_OPTS := BUILD_ID_CMD="echo 0x$(CONFIG_IPXE_CUSTOM_BUILD_ID)" +endif + +ifeq ($(CONFIG_IPXE_BUILD_EFI),y) +IPXE_BUILD_TARGET := bin-x86_64-efi-sb/ipxe.efi +# Workaround problems with unrecognized ipxe/util/elf2efi relocations +PXE_MAKE_OPTS += EXTRA_CFLAGS="$(CFLAGS_x86_64) -fno-pic" +else +IPXE_BUILD_TARGET := bin/$(PXE_ROM_PCI_ID).rom +endif all: build @@ -28,6 +49,7 @@ fetch: $(project_dir) checkout: fetch echo " Checking out $(project_name) revision $(TAG-y)" cd $(project_dir); \ + git checkout -- src/config/general.h; \ git checkout master; \ git branch -D coreboot 2>/dev/null; \ git checkout -b coreboot $(TAG-y) @@ -59,12 +81,12 @@ endif build: config $(CONFIG_SCRIPT) ifeq ($(CONFIG_HAS_SCRIPT),y) echo " MAKE $(project_name) $(TAG-y) EMBED=$(CONFIG_SCRIPT)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom EMBED=$(CONFIG_SCRIPT) + $(MAKE) -C $(project_dir)/src $(IPXE_BUILD_TARGET) EMBED=$(CONFIG_SCRIPT) $(PXE_MAKE_OPTS) else echo " MAKE $(project_name) $(TAG-y)" - $(MAKE) -C $(project_dir)/src bin/$(PXE_ROM_PCI_ID).rom + $(MAKE) -C $(project_dir)/src $(IPXE_BUILD_TARGET) $(PXE_MAKE_OPTS) endif - cp $(project_dir)/src/bin/$(PXE_ROM_PCI_ID).rom $(project_dir)/ipxe.rom + cp $(project_dir)/src/$(IPXE_BUILD_TARGET) $(project_dir)/ipxe.rom ifeq ($(CONSOLE_SERIAL),yy) cp "$(project_dir)/src/config/console.h.cb" "$(project_dir)/src/config/console.h" cp "$(project_dir)/src/config/serial.h.cb" "$(project_dir)/src/config/serial.h" diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 06aa038caac..3bcda36f69d 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -304,7 +304,7 @@ static void acpi_ssdt_write_cbtable(void) acpigen_write_device("CTBL"); acpigen_write_coreboot_hid(COREBOOT_ACPI_ID_CBTABLE); acpigen_write_name_integer("_UID", 0); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_resource_consumer_mmio(base, base + size - 1, @@ -1231,6 +1231,11 @@ static void acpi_create_iort(acpi_header_t *header, void *unused) header->length = current - (unsigned long)iort; } +__weak unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) +{ + return 0; +} + static void acpi_create_wdat(acpi_header_t *header, void *unused) { if (!CONFIG(ACPI_WDAT_WDT)) diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index f682522bc86..9db849e611e 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -839,12 +839,9 @@ void acpigen_write_thermal_zone(const char *name) void acpigen_write_STA(uint8_t status) { /* - * Method (_STA, 0, NotSerialized) { Return (status) } + * Name (_STA, status) */ - acpigen_write_method("_STA", 0); - acpigen_emit_byte(RETURN_OP); - acpigen_write_byte(status); - acpigen_pop_len(); + acpigen_write_name_integer("_STA", status); } void acpigen_write_STA_ext(const char *namestring) diff --git a/src/arch/x86/bootblock.ld b/src/arch/x86/bootblock.ld index 1f44d6abef6..73ef8de9d67 100644 --- a/src/arch/x86/bootblock.ld +++ b/src/arch/x86/bootblock.ld @@ -33,8 +33,8 @@ SECTIONS { BOOTBLOCK_TOP = .; .init (.) : { *(.init._start); - *(.init); - *(.init.*); + KEEP(*(.init)); + KEEP(*(.init.*)); } /* diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index 97d5f242567..a35e9a229d4 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -39,6 +39,8 @@ static int smbios_processor_name(u8 *start) } tmp[12] = 0; str = (const char *)tmp; + /* Skip leading spaces. */ + while (*str == ' ') str++; } } return smbios_add_string(start, str); @@ -162,7 +164,8 @@ int smbios_write_type4(unsigned long *current, int handle) t->serial_number = smbios_add_string(t->eos, smbios_processor_serial_number()); t->status = SMBIOS_PROCESSOR_STATUS_CPU_ENABLED | SMBIOS_PROCESSOR_STATUS_POPULATED; t->processor_upgrade = get_socket_type(); - if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16) { + if (cpu_have_cpuid() && cpuid_get_max_func() >= 0x16 && + cpuid_eax(0x16) != 0 && cpuid_ecx(0x16) != 0) { t->current_speed = cpuid_eax(0x16); /* base frequency */ t->external_clock = cpuid_ecx(0x16); } else { diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h index b88a0831b95..4eb8097a19e 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h @@ -90,6 +90,7 @@ #define CBMEM_ID_CSE_INFO 0x4553435F #define CBMEM_ID_CSE_BP_INFO 0x42455343 #define CBMEM_ID_AMD_OPENSIL 0x4153494C +#define CBMEM_ID_TIANOCORE_LOGO 0x42475254 #define CBMEM_ID_TO_NAME_TABLE \ { CBMEM_ID_ACPI, "ACPI " }, \ @@ -172,5 +173,7 @@ { CBMEM_ID_AMD_MP2, "AMD MP2 BUFFER"},\ { CBMEM_ID_CSE_INFO, "CSE SPECIFIC INFO"},\ { CBMEM_ID_CSE_BP_INFO, "CSE BP INFO"}, \ - { CBMEM_ID_AMD_OPENSIL, "OPENSIL DATA"} + { CBMEM_ID_AMD_OPENSIL, "OPENSIL DATA"}, \ + { CBMEM_ID_TIANOCORE_LOGO, "UEFI LOGO "} + #endif /* _CBMEM_ID_H_ */ diff --git a/src/commonlib/include/commonlib/cfr.h b/src/commonlib/include/commonlib/cfr.h index 22058e96f91..af68269e297 100644 --- a/src/commonlib/include/commonlib/cfr.h +++ b/src/commonlib/include/commonlib/cfr.h @@ -49,6 +49,8 @@ * */ +#define CFR_VERSION 0x00000000 + enum cfr_tags { CFR_TAG_OPTION_FORM = 1, CFR_TAG_ENUM_VALUE = 2, @@ -61,6 +63,7 @@ enum cfr_tags { CFR_TAG_VARCHAR_UI_HELPTEXT = 9, CFR_TAG_VARCHAR_DEF_VALUE = 10, CFR_TAG_OPTION_COMMENT = 11, + CFR_TAG_DEP_VALUES = 12, }; /* @@ -68,7 +71,7 @@ enum cfr_tags { * effect on the non-volatile variable. * CFR_OPTFLAG_READONLY: * Prevents writes to the variable. - * CFR_OPTFLAG_GRAYOUT: + * CFR_OPTFLAG_INACTIVE: * Implies READONLY. The option is visible, but cannot be modified * because one of the dependencies are not given. However there's a * possibility to enable the option by changing runtime configuration. @@ -93,7 +96,7 @@ enum cfr_tags { */ enum cfr_option_flags { CFR_OPTFLAG_READONLY = 1 << 0, - CFR_OPTFLAG_GRAYOUT = 1 << 1, + CFR_OPTFLAG_INACTIVE = 1 << 1, CFR_OPTFLAG_SUPPRESS = 1 << 2, CFR_OPTFLAG_VOLATILE = 1 << 3, CFR_OPTFLAG_RUNTIME = 1 << 4, @@ -102,7 +105,8 @@ enum cfr_option_flags { struct __packed lb_cfr_varbinary { uint32_t tag; /* * CFR_TAG_VARCHAR_OPT_NAME, CFR_TAG_VARCHAR_UI_NAME, - * CFR_TAG_VARCHAR_UI_HELPTEXT or CFR_TAG_VARCHAR_DEF_VALUE + * CFR_TAG_VARCHAR_UI_HELPTEXT, CFR_TAG_VARCHAR_DEF_VALUE + * or CFR_TAG_DEP_VALUES */ uint32_t size; /* Length of the entire structure */ uint32_t data_length; /* Length of data, including NULL terminator for strings */ @@ -117,6 +121,15 @@ struct __packed lb_cfr_enum_value { */ }; +/* + * The optional flags describe how a numeric option is to be displayed. + * CFR_NUM_OPT_DISPFLAG_HEX: + * Displays a NUMBER option in hexadecimal instead of decimal notation. + */ +enum cfr_numeric_option_display_flags { + CFR_NUM_OPT_DISPFLAG_HEX = 1 << 0, +}; + /* Supports multiple option types: ENUM, NUMBER, BOOL */ struct __packed lb_cfr_numeric_option { uint32_t tag; /* @@ -130,10 +143,16 @@ struct __packed lb_cfr_numeric_option { */ uint32_t flags; /* enum cfr_option_flags */ uint32_t default_value; + uint32_t min; + uint32_t max; + uint32_t step; + uint32_t display_flags; /* enum cfr_numeric_option_display_flags */ + /* * struct lb_cfr_varbinary opt_name * struct lb_cfr_varbinary ui_name * struct lb_cfr_varbinary ui_helptext (Optional) + * struct lb_cfr_varbinary dependency_values (Optional) * struct lb_cfr_enum_value enum_values[] */ }; @@ -151,6 +170,7 @@ struct __packed lb_cfr_varchar_option { * struct lb_cfr_varbinary opt_name * struct lb_cfr_varbinary ui_name * struct lb_cfr_varbinary ui_helptext (Optional) + * struct lb_cfr_varbinary dependency_values (Optional) */ }; @@ -170,6 +190,7 @@ struct __packed lb_cfr_option_comment { /* * struct lb_cfr_varbinary ui_name * struct lb_cfr_varbinary ui_helptext (Optional) + * struct lb_cfr_varbinary dependency_values (Optional) */ }; @@ -184,6 +205,7 @@ struct __packed lb_cfr_option_form { uint32_t flags; /* enum cfr_option_flags */ /* * struct lb_cfr_varbinary ui_name + * struct lb_cfr_varbinary dependency_values (Optional) * struct lb_cfr_varchar_option options[] */ }; diff --git a/src/commonlib/include/commonlib/coreboot_tables.h b/src/commonlib/include/commonlib/coreboot_tables.h index def48b77979..0d42b50783d 100644 --- a/src/commonlib/include/commonlib/coreboot_tables.h +++ b/src/commonlib/include/commonlib/coreboot_tables.h @@ -90,6 +90,7 @@ enum { LB_TAG_EFI_FW_INFO = 0x0045, LB_TAG_CAPSULE = 0x0046, LB_TAG_CFR_ROOT = 0x0047, + LB_TAG_LOGO = 0x00a0, /* The following options are CMOS-related */ LB_TAG_CMOS_OPTION_TABLE = 0x00c8, LB_TAG_OPTION = 0x00c9, @@ -602,8 +603,17 @@ struct lb_efi_fw_info { struct lb_cfr { uint32_t tag; uint32_t size; + uint32_t version; uint32_t checksum; /* Checksum of the variable payload. */ /* struct lb_cfr_option_form forms[] */ }; +/* + * Bootlogo header for TianoCore boot logo + * * size Contains the size of the BMP file + */ +struct bootlogo_header { + uint64_t size; +} __packed; + #endif diff --git a/src/cpu/Kconfig b/src/cpu/Kconfig index 2770f648b49..ab4a472a7df 100644 --- a/src/cpu/Kconfig +++ b/src/cpu/Kconfig @@ -194,3 +194,9 @@ config CPU_UCODE_BINARIES microcode binary files to include, separated by spaces. If unsure, leave this blank. + +config CPU_MAX_TEMPERATURE + int + default 100 + help + The maximum CPU temperature, aka TjMax. Processor-specific. diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index d7c23daf105..984bd0ff2cc 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -43,8 +43,9 @@ static void model_16_init(struct device *dev) msr.hi &= ~(1 << (46 - 32)); wrmsr(NB_CFG_MSR, msr); - /* Write protect SMM space with SMMLOCK. */ - lock_smm(); + /* Write protect SMM space with SMMLOCK, or let SMI handler do it if any. */ + if (!CONFIG(HAVE_SMI_HANDLER)) + lock_smm(); amd_update_microcode_from_cbfs(); diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index 2336d68f968..17d2526e90b 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -10,7 +10,11 @@ config CPU_AMD_PI select UDELAY_LAPIC select LAPIC_MONOTONIC_TIMER select SPI_FLASH if HAVE_ACPI_RESUME - select NO_SMM + select SMM_TSEG + select PARALLEL_MP_AP_WORK + select SOC_AMD_COMMON_BLOCK_SMM + select SOC_AMD_COMMON_BLOCK_SMI + select SOC_AMD_COMMON_BLOCK_ACPI select SSE2 if CPU_AMD_PI @@ -31,10 +35,20 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x4000 +config SMM_MODULE_STACK_SIZE + default 0x800 + +config SMM_TSEG_SIZE + default 0x100000 if HAVE_SMI_HANDLER + default 0x0 + endif # CPU_AMD_PI source "src/cpu/amd/pi/00730F01/Kconfig" diff --git a/src/cpu/intel/fit/Makefile.mk b/src/cpu/intel/fit/Makefile.mk index f405c577445..0661984f155 100644 --- a/src/cpu/intel/fit/Makefile.mk +++ b/src/cpu/intel/fit/Makefile.mk @@ -13,6 +13,10 @@ intel_fit-file := fit_table.c:struct intel_fit-type := intel_fit intel_fit-align := 16 +ifneq ($(CONFIG_INTEL_FIT_LOC),) +intel_fit-COREBOOT-position := $(CONFIG_INTEL_FIT_LOC) +endif + $(call add_intermediate, set_fit_ptr, $(IFITTOOL)) @printf " UPDATE-FIT set FIT pointer to table\n" $(IFITTOOL) -f $< -F -n intel_fit -r COREBOOT -c diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index 86dcbea1772..a08cc9a9eed 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -451,13 +452,16 @@ static void configure_thermal_target(struct device *dev) /* Make sure your devicetree has the cpu_cluster below chip cpu/intel/haswell! */ struct cpu_intel_haswell_config *conf = dev->upstream->dev->chip_info; msr_t msr; + uint32_t tcc_offset; + + tcc_offset = get_cpu_throttling_offset(conf->tcc_offset); /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; + msr.lo |= (tcc_offset & 0xf) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } } diff --git a/src/cpu/intel/microcode/microcode_asm.S b/src/cpu/intel/microcode/microcode_asm.S index 28705230a2a..7e05a4cc1a3 100644 --- a/src/cpu/intel/microcode/microcode_asm.S +++ b/src/cpu/intel/microcode/microcode_asm.S @@ -48,6 +48,11 @@ .global update_bsp_microcode update_bsp_microcode: +#if CONFIG_CPU_MICROCODE_CBFS_LOC != 0 && CONFIG_CPU_MICROCODE_CBFS_LEN != 0 + movl $(CONFIG_CPU_MICROCODE_CBFS_LOC), %esi + movl $(CONFIG_CPU_MICROCODE_CBFS_LEN), %edi + addl %esi, %edi +#else /* Keep return address */ movl %esp, %edx /* find microcodes in cbfs */ @@ -69,6 +74,7 @@ update_bsp_microcode: movl CBFS_FILE_LEN(%eax), %edi bswap %edi addl %esi, %edi +#endif /* * Microcode revision -> %ebx diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index cb748543468..cf76b33851d 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -24,13 +25,16 @@ static void configure_thermal_target(struct device *dev) { struct cpu_intel_model_2065x_config *conf = dev->upstream->dev->chip_info; msr_t msr; + uint32_t tcc_offset; + + tcc_offset = get_cpu_throttling_offset(conf->tcc_offset); /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; + msr.lo |= (tcc_offset & 0xf) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } } diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 23310a303b4..ef9d752b5e6 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -331,6 +332,9 @@ static void configure_thermal_target(struct device *dev) { struct cpu_intel_model_206ax_config *conf = dev->upstream->dev->chip_info; msr_t msr; + uint32_t tcc_offset; + + tcc_offset = get_cpu_throttling_offset(conf->tcc_offset); if (boot_cpu()) { /* @@ -340,10 +344,10 @@ static void configure_thermal_target(struct device *dev) /* Set TCC activation offset if supported */ msr = rdmsr(MSR_PLATFORM_INFO); - if ((msr.lo & (1 << 30)) && conf->tcc_offset) { + if ((msr.lo & (1 << 30)) && tcc_offset) { msr = rdmsr(MSR_TEMPERATURE_TARGET); msr.lo &= ~(0xf << 24); /* Bits 27:24 */ - msr.lo |= (conf->tcc_offset & 0xf) << 24; + msr.lo |= (tcc_offset & 0xf) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } } diff --git a/src/cpu/x86/lapic/Makefile.mk b/src/cpu/x86/lapic/Makefile.mk index dd484ee6f66..24865c317b7 100644 --- a/src/cpu/x86/lapic/Makefile.mk +++ b/src/cpu/x86/lapic/Makefile.mk @@ -6,6 +6,8 @@ bootblock-$(CONFIG_UDELAY_LAPIC) += apic_timer.c romstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c postcar-$(CONFIG_UDELAY_LAPIC) += apic_timer.c +# Use TSC for SMM, should be safer than LAPIC after OS takes over +smm-$(CONFIG_UDELAY_LAPIC) += ../tsc/delay_tsc.c all_x86-y += boot_cpu.c all_x86-y += lapic.c diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index 47b3a9ef848..68015e2f117 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -1177,3 +1177,46 @@ enum cb_err mp_init_with_smm(struct bus *cpu_bus, const struct mp_ops *mp_ops) return ret; } + + +/* AP restart code */ + +static struct mp_flight_record ap_restart_steps[] = { + /* Wait for APs to finish then optionally start looking for work. */ + MP_FR_BLOCK_APS(ap_wait_for_instruction, NULL), +}; + +enum cb_err restart_aps(void) +{ + struct mp_params mp_params; + atomic_t *ap_count; + + if (!CONFIG(PARALLEL_MP_AP_WORK)) + return CB_ERR_NOT_IMPLEMENTED; + + mp_params.num_cpus = mp_state.cpu_count; + mp_params.num_records = ARRAY_SIZE(ap_restart_steps); + mp_params.flight_plan = &ap_restart_steps[0]; + + mp_info.num_records = ARRAY_SIZE(ap_restart_steps); + mp_info.records = &ap_restart_steps[0]; + + /* Load the SIPI vector. */ + ap_count = load_sipi_vector(&mp_params); + if (ap_count == NULL) + return CB_ERR; + + /* Make sure SIPI data hits RAM so the APs that come up will see + * the startup code even if the caches are disabled. */ + wbinvd(); + + if (start_aps(NULL, global_num_aps, ap_count) != CB_SUCCESS) { + mdelay(1000); + printk(BIOS_DEBUG, "%d/%d eventually checked in?\n", + atomic_read(ap_count), global_num_aps); + return CB_ERR; + } + + /* Walk the flight plan for the BSP. */ + return bsp_do_flight_plan(&mp_params); +} diff --git a/src/cpu/x86/topology.c b/src/cpu/x86/topology.c index b2fd202ed52..70bdf47c4a3 100644 --- a/src/cpu/x86/topology.c +++ b/src/cpu/x86/topology.c @@ -110,12 +110,14 @@ void set_cpu_topology(struct device *cpu) static struct bitfield_descriptor topology[LEVEL_TYPE_MAX]; static enum cb_err ret; static bool done; + unsigned int core_id_within_package; struct { unsigned int level; unsigned int *field; } apic_fields[] = { { LEVEL_TYPE_SMT, &cpu->path.apic.thread_id }, { LEVEL_TYPE_CORE, &cpu->path.apic.core_id }, + { LEVEL_TYPE_MODULE, &cpu->path.apic.module_id }, { LEVEL_TYPE_PACKAGE, &cpu->path.apic.package_id }, { LEVEL_TYPE_PACKAGE, &cpu->path.apic.node_id } }; @@ -150,4 +152,8 @@ void set_cpu_topology(struct device *cpu) *apic_fields[i].field = value; } } + + core_id_within_package = apicid & ((1 << topology[LEVEL_TYPE_PACKAGE].first_bit) - 1); + core_id_within_package >>= topology[LEVEL_TYPE_CORE].first_bit; + cpu->path.apic.core_id_within_package = core_id_within_package; } diff --git a/src/cpu/x86/tsc/delay_tsc.c b/src/cpu/x86/tsc/delay_tsc.c index 4253b18dab2..746e7876e52 100644 --- a/src/cpu/x86/tsc/delay_tsc.c +++ b/src/cpu/x86/tsc/delay_tsc.c @@ -30,7 +30,7 @@ void udelay(unsigned int us) } } -#if CONFIG(TSC_MONOTONIC_TIMER) +#if CONFIG(TSC_MONOTONIC_TIMER) || (CONFIG(LAPIC_MONOTONIC_TIMER) && ENV_SMM) #include static struct monotonic_counter { diff --git a/src/device/pci_device.c b/src/device/pci_device.c index d03d88df399..5b0531d7050 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -372,14 +373,15 @@ static uint64_t get_rebar_sizes_mask(const struct device *dev, static void pci_store_rebar_size(const struct device *dev, const struct resource *resource) { - const unsigned int num_bits = __fls64(resource->size); + /* The ReBAR size value in the register is in MiB */ + const unsigned int num_bits = __fls64(resource->size / MiB); const uint32_t offset = get_rebar_offset(dev, resource->index); if (!offset) return; pci_update_config32(dev, offset + PCI_REBAR_CTRL_OFFSET, - ~PCI_REBAR_CTRL_SIZE_MASK, - num_bits << PCI_REBAR_CTRL_SIZE_SHIFT); + PCI_REBAR_CTRL_BAR_SIZE_MASK, + num_bits << PCI_REBAR_CTRL_BAR_SIZE_SHIFT); } static void configure_adjustable_base(const struct device *dev, @@ -455,7 +457,7 @@ static void pci_read_bases(struct device *dev, unsigned int howmany) resource = pci_get_resource(dev, index); const bool is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE) != 0; - if (CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS) && is_pcie) + if (is_pcie && dasharo_resizeable_bars_enabled()) configure_adjustable_base(dev, index, resource); index += (resource->flags & IORESOURCE_PCI64) ? 8 : 4; @@ -698,7 +700,8 @@ static void pci_set_resource(struct device *dev, struct resource *resource) if (!(resource->flags & IORESOURCE_PCI_BRIDGE)) { if (CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS) && - (resource->flags & IORESOURCE_PCIE_RESIZABLE_BAR)) + (resource->flags & IORESOURCE_PCIE_RESIZABLE_BAR) && + dasharo_resizeable_bars_enabled()) pci_store_rebar_size(dev, resource); pci_store_resource(dev, resource); diff --git a/src/device/pciexp_device.c b/src/device/pciexp_device.c index 8686e38a868..6b9010fb9c8 100644 --- a/src/device/pciexp_device.c +++ b/src/device/pciexp_device.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -718,21 +719,24 @@ static void pciexp_tune_dev(struct device *dev) if (!root_cap) return; - /* Check for and enable Common Clock */ - if (CONFIG(PCIEXP_COMMON_CLOCK)) - pciexp_enable_common_clock(root, root_cap, dev, cap); + if (!CONFIG(VENDOR_PCENGINES) || CONFIG(BOARD_PCENGINES_APU5) || + dasharo_apu_pcie_pm_enabled()) { + /* Check for and enable Common Clock */ + if (CONFIG(PCIEXP_COMMON_CLOCK)) + pciexp_enable_common_clock(root, root_cap, dev, cap); - /* Check if per port CLK req is supported by endpoint*/ - if (CONFIG(PCIEXP_CLK_PM)) - pciexp_enable_clock_power_pm(dev, cap); + /* Check if per port CLK req is supported by endpoint*/ + if (CONFIG(PCIEXP_CLK_PM)) + pciexp_enable_clock_power_pm(dev, cap); - /* Enable L1 Sub-State when both root port and endpoint support */ - if (CONFIG(PCIEXP_L1_SUB_STATE)) - pciexp_config_L1_sub_state(root, dev); + /* Enable L1 Sub-State when both root port and endpoint support */ + if (CONFIG(PCIEXP_L1_SUB_STATE)) + pciexp_config_L1_sub_state(root, dev); - /* Check for and enable ASPM */ - if (CONFIG(PCIEXP_ASPM)) - pciexp_enable_aspm(root, root_cap, dev, cap); + /* Check for and enable ASPM */ + if (CONFIG(PCIEXP_ASPM)) + pciexp_enable_aspm(root, root_cap, dev, cap); + } /* Clear PCIe Lane Error Status */ if (CONFIG(PCIEXP_LANE_ERR_STAT_CLEAR)) diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c index 44782d87a1e..626a613ca16 100644 --- a/src/device/resource_allocator_v4.c +++ b/src/device/resource_allocator_v4.c @@ -91,6 +91,10 @@ static resource_t effective_limit(const struct resource *const res) if (res->flags & IORESOURCE_BRIDGE) return res->limit; + /* If the resource is bigger than 4G or resource 64bit, force 64bit limit */ + if (res->size > UINT32_MAX || res->flags & IORESOURCE_PCI64) + return UINT64_MAX; + const resource_t quirk_4g_limit = res->flags & IORESOURCE_ABOVE_4G ? UINT64_MAX : UINT32_MAX; return MIN(res->limit, quirk_4g_limit); diff --git a/src/drivers/efi/Kconfig b/src/drivers/efi/Kconfig index 07e5f146a61..8916281c76e 100644 --- a/src/drivers/efi/Kconfig +++ b/src/drivers/efi/Kconfig @@ -42,6 +42,7 @@ config DRIVERS_EFI_MAIN_FW_LSV config DRIVERS_EFI_UPDATE_CAPSULES bool "Include EFI update capsules driver" depends on DRIVERS_EFI_VARIABLE_STORE && SMMSTORE_V2 && DRIVERS_EFI_FW_INFO + select EXT_BIOS_FILL_UP if SOC_INTEL_COMMON_BLOCK help Adds a driver that is able to parse CapsuleUpdateData* EFI variables to discover firmware updates and expose them for tianocore thorough diff --git a/src/drivers/efi/capsules.c b/src/drivers/efi/capsules.c index e674e33228c..bb63de908ff 100644 --- a/src/drivers/efi/capsules.c +++ b/src/drivers/efi/capsules.c @@ -10,9 +10,10 @@ #include #include #include +#include +#include #include #include -#include #include #include @@ -344,7 +345,15 @@ static struct block_descr check_capsule_block(struct block_descr first_block, goto error; } - data_size += ALIGN_UP(capsule_hdr->CapsuleImageSize, CAPSULE_ALIGNMENT); + uint64_t capsule_size = + ALIGN_UP((uint64_t)capsule_hdr->CapsuleImageSize, CAPSULE_ALIGNMENT); + if (data_size + capsule_size < data_size) { /* overflow detection */ + printk(BIOS_ERR, + "capsules: capsules block size is too large (%#llx + %#llx) for uint64.\n", + data_size, capsule_size); + goto error; + } + data_size += capsule_size; uint32_t size_left = capsule_hdr->CapsuleImageSize; while (size_left != 0) { @@ -384,6 +393,12 @@ static struct block_descr check_capsule_block(struct block_descr first_block, } /* Increase the size only on successful parsing of the capsule block. */ + if (*total_data_size + data_size < *total_data_size) { /* overflow detection */ + printk(BIOS_ERR, + "capsules: total capsule's size is too large (%#llx + %#llx) for uint64.\n", + *total_data_size, data_size); + goto error; + } *total_data_size += data_size; return block; @@ -582,6 +597,7 @@ static void coalesce_capsules(struct block_descr block_chain, uint8_t *target) { struct block_descr block = block_chain; uint8_t *capsule_start = NULL; + uint32_t capsule_size = 0; uint32_t size_left = 0; /* No safety checks in this function, as all of them were done earlier. */ @@ -596,8 +612,10 @@ static void coalesce_capsules(struct block_descr block_chain, uint8_t *target) if (size_left == 0) { const EFI_CAPSULE_HEADER *capsule_hdr = map_range(block.addr, sizeof(*capsule_hdr)); - size_left = capsule_hdr->CapsuleImageSize; + capsule_size = capsule_hdr->CapsuleImageSize; capsule_start = target; + + size_left = capsule_size; } uint64_t addr = block.addr; @@ -627,13 +645,14 @@ static void coalesce_capsules(struct block_descr block_chain, uint8_t *target) } uefi_capsules[uefi_capsule_count].base = (uintptr_t)capsule_start; - uefi_capsules[uefi_capsule_count].len = block.len; + uefi_capsules[uefi_capsule_count].len = capsule_size; uefi_capsule_count++; /* This is to align start of the next capsule (assumes that initial value of target was suitably aligned). */ - if (!IS_ALIGNED(block.len, CAPSULE_ALIGNMENT)) - target += ALIGN_UP(block.len, CAPSULE_ALIGNMENT) - block.len; + if (!IS_ALIGNED(capsule_size, CAPSULE_ALIGNMENT)) + target += ALIGN_UP(capsule_size, CAPSULE_ALIGNMENT) - + capsule_size; } } @@ -768,3 +787,16 @@ static void parse_capsules(void *unused) BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, parse_capsules, NULL); #endif + +static void enable_capsule_smi(void *unused) +{ + uint32_t ret; + + ret = call_smm(APM_CNT_SMMSTORE, SMMSTORE_CMD_USE_FULL_FLASH, + (void*)(uintptr_t)uefi_capsule_count); + + printk(BIOS_INFO, "%sabled capsule update SMI handler\n", + ret == SMMSTORE_RET_SUCCESS ? "En" : "Dis"); +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, enable_capsule_smi, NULL); diff --git a/src/drivers/efi/efivars.c b/src/drivers/efi/efivars.c index 2591eab7307..56b517ada7f 100644 --- a/src/drivers/efi/efivars.c +++ b/src/drivers/efi/efivars.c @@ -3,14 +3,13 @@ #include #include #include +#include #include #include #include #include -#include "efivars.h" - #define PREFIX "EFIVARS: " static const EFI_GUID EfiVariableGuid = { @@ -408,12 +407,13 @@ enum cb_err efi_fv_print_options(struct region_device *rdev) { enum cb_err ret; bool auth_format; + struct region_device store_rdev = *rdev; - ret = efi_fv_init(rdev, &auth_format); + ret = efi_fv_init(&store_rdev, &auth_format); if (ret != CB_SUCCESS) return ret; - return walk_variables(rdev, auth_format, print_var, NULL); + return walk_variables(&store_rdev, auth_format, print_var, NULL); } /* @@ -431,8 +431,9 @@ enum cb_err efi_fv_get_option(struct region_device *rdev, struct efi_find_args args; bool auth_format; enum cb_err ret; + struct region_device store_rdev = *rdev; - ret = efi_fv_init(rdev, &auth_format); + ret = efi_fv_init(&store_rdev, &auth_format); if (ret != CB_SUCCESS) return ret; @@ -441,7 +442,7 @@ enum cb_err efi_fv_get_option(struct region_device *rdev, args.size = size; args.data = dest; - return walk_variables(rdev, auth_format, find_and_copy, &args); + return walk_variables(&store_rdev, auth_format, find_and_copy, &args); } static enum cb_err write_auth_hdr(struct region_device *rdev, const EFI_GUID *guid, @@ -584,13 +585,14 @@ enum cb_err efi_fv_set_option(struct region_device *rdev, uint32_t size) { struct region_device rdev_old; + struct region_device store_rdev = *rdev; struct efi_find_compare_args args; bool found_existing; VARIABLE_HEADER hdr; bool auth_format; enum cb_err ret; - ret = efi_fv_init(rdev, &auth_format); + ret = efi_fv_init(&store_rdev, &auth_format); if (ret != CB_SUCCESS) return ret; @@ -601,7 +603,7 @@ enum cb_err efi_fv_set_option(struct region_device *rdev, args.match = false; args.data = data; - ret = walk_variables(rdev, auth_format, find_and_compare, &args); + ret = walk_variables(&store_rdev, auth_format, find_and_compare, &args); found_existing = ret == CB_SUCCESS; if (found_existing) { @@ -610,17 +612,17 @@ enum cb_err efi_fv_set_option(struct region_device *rdev, if (args.match) return CB_SUCCESS; - rdev_old = *rdev; + rdev_old = store_rdev; /* Mark as to be deleted */ hdr.State = VAR_IN_DELETED_TRANSITION; - if (rdev_writeat(rdev, &hdr.State, offsetof(VARIABLE_HEADER, State), + if (rdev_writeat(&store_rdev, &hdr.State, offsetof(VARIABLE_HEADER, State), sizeof(hdr.State)) != sizeof(hdr.State)) return CB_EFI_ACCESS_ERROR; } /* Walk to end of variable store */ - ret = walk_variables(rdev, auth_format, noop, NULL); + ret = walk_variables(&store_rdev, auth_format, noop, NULL); if (ret != CB_EFI_OPTION_NOT_FOUND) return ret; @@ -632,9 +634,9 @@ enum cb_err efi_fv_set_option(struct region_device *rdev, */ if (auth_format) - ret = write_auth_hdr(rdev, guid, name, data, size); + ret = write_auth_hdr(&store_rdev, guid, name, data, size); else - ret = write_hdr(rdev, guid, name, data, size); + ret = write_hdr(&store_rdev, guid, name, data, size); if (ret != CB_SUCCESS) return ret; diff --git a/src/drivers/efi/efivars.h b/src/drivers/efi/efivars.h index b3443b33b35..a7932d1dc1b 100644 --- a/src/drivers/efi/efivars.h +++ b/src/drivers/efi/efivars.h @@ -6,6 +6,12 @@ #include #include +/* + * efi/efi_datatype.h must be included before other EFI headers because it + * provides entities that EDK's headers define when they are absent, leading to + * conflicting definitions for some orderings of includes. + */ +#include #include /** diff --git a/src/drivers/efi/option.c b/src/drivers/efi/option.c index d634c963545..cc147d26697 100644 --- a/src/drivers/efi/option.c +++ b/src/drivers/efi/option.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include -#include - #include "efivars.h" static const EFI_GUID EficorebootNvDataGuid = { diff --git a/src/drivers/generic/bayhub_lv2/lv2.h b/src/drivers/generic/bayhub_lv2/lv2.h index 9eef4b3fc39..cb2ddb83e64 100644 --- a/src/drivers/generic/bayhub_lv2/lv2.h +++ b/src/drivers/generic/bayhub_lv2/lv2.h @@ -22,7 +22,7 @@ enum { LV2_PCR_HEX_234 = 0x234, LV2_MAX_LATENCY_SETTING = 0x10011001, LV2_PCR_HEX_3F4 = 0x3F4, - LV2_L1_SUBSTATE_OPTIMISE = 0x0000000A, + LV2_L1_SUBSTATE_OPTIMISE = 0x0000000F, LV2_L1_SUBSTATE_OPTIMISE_MASK = 0xFFFFFFF0, LV2_PCR_HEX_300 = 0x300, LV2_TUNING_WINDOW = 0x00006055, diff --git a/src/drivers/generic/cbfs-serial/cbfs-serial.c b/src/drivers/generic/cbfs-serial/cbfs-serial.c index 6ff010cb413..3b6e9ce63a4 100644 --- a/src/drivers/generic/cbfs-serial/cbfs-serial.c +++ b/src/drivers/generic/cbfs-serial/cbfs-serial.c @@ -2,6 +2,7 @@ #include #include +#include #include #include @@ -20,6 +21,9 @@ const char *smbios_mainboard_serial_number(void) return serial_number; } + if (get_serial_number_from_efivar(serial_number)) + return serial_number; + strncpy(serial_number, CONFIG_MAINBOARD_SERIAL_NUMBER, MAX_SERIAL_LENGTH); diff --git a/src/drivers/generic/cbfs-uuid/cbfs-uuid.c b/src/drivers/generic/cbfs-uuid/cbfs-uuid.c index e657bdd922b..e438aa4015c 100644 --- a/src/drivers/generic/cbfs-uuid/cbfs-uuid.c +++ b/src/drivers/generic/cbfs-uuid/cbfs-uuid.c @@ -1,7 +1,10 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include +#include #include #include #include @@ -17,7 +20,12 @@ void smbios_system_set_uuid(u8 *uuid) if (uuid_len >= UUID_STRLEN && uuid_len <= UUID_STRLEN + 3) { /* Cut off any trailing whitespace like CR or LF */ uuid_str[UUID_STRLEN] = '\0'; - if (!parse_uuid(system_uuid, uuid_str)) + if (!parse_uuid(system_uuid, uuid_str)) { memcpy(uuid, system_uuid, UUID_LEN); + return; + } } + + if (get_uuid_from_efivar(system_uuid)) + memcpy(uuid, system_uuid, UUID_LEN); } diff --git a/src/drivers/gfx/nvidia/optimus/Kconfig b/src/drivers/gfx/nvidia/optimus/Kconfig new file mode 100644 index 00000000000..5b520f67dd8 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/Kconfig @@ -0,0 +1,8 @@ +config DRIVER_NVIDIA_OPTIMUS + bool + default n + depends on HAVE_ACPI_TABLES + select PMC_IPC_ACPI_INTERFACE + help + NVIDIA Optimus driver for ULT platforms with a PMC IPC ACPI interface. + and graphics cards supporting Runtime D3 power management diff --git a/src/drivers/gfx/nvidia/optimus/Makefile.mk b/src/drivers/gfx/nvidia/optimus/Makefile.mk new file mode 100644 index 00000000000..f29943943d7 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/Makefile.mk @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-only + +ramstage-$(CONFIG_DRIVER_NVIDIA_OPTIMUS) += optimus.c diff --git a/src/drivers/gfx/nvidia/optimus/chip.h b/src/drivers/gfx/nvidia/optimus/chip.h new file mode 100644 index 00000000000..b0eb4c6f189 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/chip.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_GFX_NVIDIA_OPTIMUS_CHIP_H__ +#define __DRIVERS_GFX_NVIDIA_OPTIMUS_CHIP_H__ + +#include + +/* Device support at least one of enable/reset GPIO. */ +struct drivers_gfx_nvidia_optimus_config { + const char *desc; + + /* GPIO used to enable device. */ + struct acpi_gpio enable_gpio; + /* Delay to be inserted after device is enabled. */ + unsigned int enable_delay_ms; + /* Delay to be inserted after device is disabled. */ + unsigned int enable_off_delay_ms; + + /* GPIO used to take device out of reset or to put it into reset. */ + struct acpi_gpio reset_gpio; + /* Delay to be inserted after device is taken out of reset. */ + unsigned int reset_delay_ms; + /* Delay to be inserted after device is put into reset. */ + unsigned int reset_off_delay_ms; + + /* + * SRCCLK assigned to this root port which will be turned off via PMC IPC. + * If set to -1 then the clock will not be disabled in D3. + */ + int srcclk_pin; + + /* + * Disable the ACPI-driven L23 Ready-to-Detect transition for the root port. + * maybe unneeded for optimus? + */ + bool disable_l23; + + /* + * EC method to call on dGPU power state change + */ + const char *ec_notify_method; +}; + +#endif diff --git a/src/drivers/gfx/nvidia/optimus/optimus.c b/src/drivers/gfx/nvidia/optimus/optimus.c new file mode 100644 index 00000000000..cc7b4da85c9 --- /dev/null +++ b/src/drivers/gfx/nvidia/optimus/optimus.c @@ -0,0 +1,299 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +/* PCIe Root Port registers for link status and L23 control. */ +#define PCH_PCIE_CFG_SSID 0x40 /* Subsystem ID */ +#define PCH_PCIE_CFG_LSTS 0x52 /* Link Status Register */ +#define PCH_PCIE_CFG_SPR 0xe0 /* Scratchpad */ +#define PCH_PCIE_CFG_RPPGEN 0xe2 /* Root Port Power Gating Enable */ +#define PCH_PCIE_CFG_LCAP_PN 0x4f /* Root Port Number */ + +/* ACPI register names corresponding to PCIe root port registers. */ +#define ACPI_REG_PCI_LINK_ACTIVE "LASX" /* Link active status */ +#define ACPI_REG_PCI_L23_RDY_ENTRY "L23E" /* L23_Rdy Entry Request */ +#define ACPI_REG_PCI_L23_RDY_DETECT "L23R" /* L23_Rdy Detect Transition */ +#define ACPI_REG_PCI_L23_SAVE_STATE "NCB7" /* Scratch bit to save L23 state */ + +/* ACPI register names corresponding to GPU port registers */ +#define ACPI_REG_PCI_SUBSYSTEM_ID "DVID" /* Subsystem DID+VID */ + +/* Called from _ON to get PCIe link back to active state. */ +static void nvidia_optimus_acpi_l23_exit(void) +{ + /* Skip if port is not in L2/L3. */ + acpigen_write_if_lequal_namestr_int(ACPI_REG_PCI_L23_SAVE_STATE, 1); + + /* Initiate L2/L3 Ready To Detect transition. */ + acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_DETECT); + + /* Wait for transition to detect. */ + acpigen_write_delay_until_namestr_int(320, ACPI_REG_PCI_L23_RDY_DETECT, 0); + + acpigen_write_store_int_to_namestr(0, ACPI_REG_PCI_L23_SAVE_STATE); + + /* Once in detect, wait for link active. */ + acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_LINK_ACTIVE, 1); + + acpigen_pop_len(); /* If */ +} + +/* Called from _OFF to put PCIe link into L2/L3 state. */ +static void nvidia_optimus_acpi_l23_entry(void) +{ + /* Initiate L2/L3 Entry request. */ + acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_RDY_ENTRY); + + /* Wait for L2/L3 Entry request to clear. */ + acpigen_write_delay_until_namestr_int(128, ACPI_REG_PCI_L23_RDY_ENTRY, 0); + + acpigen_write_store_int_to_namestr(1, ACPI_REG_PCI_L23_SAVE_STATE); +} + +/* Restore the subsystem ID after _ON to ensure the windows driver works */ +static void nvidia_optimus_acpi_subsystem_id_restore(const struct device *dev) +{ + uint32_t did, vid, dvid; + + if (CONFIG_SUBSYSTEM_VENDOR_ID) + vid = CONFIG_SUBSYSTEM_VENDOR_ID; + else if (dev->subsystem_vendor) + vid = dev->subsystem_vendor; + else + vid = 0x0000; + + if (CONFIG_SUBSYSTEM_DEVICE_ID) + did = CONFIG_SUBSYSTEM_DEVICE_ID; + else if (dev->subsystem_device) + did = dev->subsystem_device; + else + did = 0x0000; + + dvid = did << 16 | vid; + acpigen_write_store_int_to_namestr(dvid, ACPI_REG_PCI_SUBSYSTEM_ID); +} + +static void +nvidia_optimus_acpi_method_on(unsigned int pcie_rp, + const struct device *dev) +{ + const struct drivers_gfx_nvidia_optimus_config *config = config_of(dev); + acpigen_write_method_serialized("_ON", 0); + acpigen_write_if_lequal_namestr_int("_STA", 0x5); + + /* Assert enable GPIO to turn on device power. */ + if (config->enable_gpio.pin_count) { + acpigen_enable_tx_gpio(&config->enable_gpio); + if (config->enable_delay_ms) + acpigen_write_sleep(config->enable_delay_ms); + } + + /* Enable SRCCLK for root port if pin is defined. */ + if (config->srcclk_pin >= 0) + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, true); + + /* De-assert reset GPIO to bring device out of reset. */ + if (config->reset_gpio.pin_count) { + acpigen_disable_tx_gpio(&config->reset_gpio); + if (config->reset_delay_ms) + acpigen_write_sleep(config->reset_delay_ms); + } + + /* Trigger L23 ready exit flow unless disabled by config. */ + if (!config->disable_l23) + nvidia_optimus_acpi_l23_exit(); + + /* Notify EC to start polling the dGPU */ + if (config->ec_notify_method) { + acpigen_emit_namestring(config->ec_notify_method); + acpigen_write_integer(1); + } + + acpigen_pop_len(); /* If */ + + nvidia_optimus_acpi_subsystem_id_restore(dev); + acpigen_write_store_int_to_namestr(0xF, "_STA"); + acpigen_pop_len(); /* Method */ +} + +static void +nvidia_optimus_acpi_method_off(unsigned int pcie_rp, + const struct device *dev) +{ + const struct drivers_gfx_nvidia_optimus_config *config = config_of(dev); + acpigen_write_method_serialized("_OFF", 0); + acpigen_write_if_lequal_namestr_int("_STA", 0xF); + + /* Notify EC to stop polling the dGPU */ + if (config->ec_notify_method) { + acpigen_emit_namestring(config->ec_notify_method); + acpigen_write_integer(0); + } + + /* Trigger L23 ready entry flow unless disabled by config. */ + if (!config->disable_l23) + nvidia_optimus_acpi_l23_entry(); + + /* Assert reset GPIO to place device into reset. */ + if (config->reset_gpio.pin_count) { + acpigen_enable_tx_gpio(&config->reset_gpio); + if (config->reset_off_delay_ms) + acpigen_write_sleep(config->reset_off_delay_ms); + } + + /* Disable SRCCLK for this root port if pin is defined. */ + if (config->srcclk_pin >= 0) + pmc_ipc_acpi_set_pci_clock(pcie_rp, config->srcclk_pin, false); + + /* De-assert enable GPIO to turn off device power. */ + if (config->enable_gpio.pin_count) { + acpigen_disable_tx_gpio(&config->enable_gpio); + if (config->enable_off_delay_ms) + acpigen_write_sleep(config->enable_off_delay_ms); + } + + acpigen_pop_len(); /* If */ + + acpigen_write_store_int_to_namestr(0x5, "_STA"); + acpigen_pop_len(); /* Method */ +} + +static void nvidia_optimus_acpi_fill_ssdt(const struct device *dev) +{ + const struct drivers_gfx_nvidia_optimus_config *config = config_of(dev); + static const char *const power_res_states[] = {"_PR0", "_PR2", "_PR3"}; + const struct device *parent = dev->upstream->dev; + const char *scope = acpi_device_path(parent); + + /* PCH RP PCIe configuration space */ + const struct opregion rp_pci_config = OPREGION("PXCS", SYSTEMMEMORY, CONFIG_ECAM_MMCONF_BASE_ADDRESS | (parent->path.pci.devfn << 12), 0x1000); + const struct fieldlist rp_fieldlist[] = { + FIELDLIST_OFFSET(PCH_PCIE_CFG_LSTS), + FIELDLIST_RESERVED(13), + FIELDLIST_NAMESTR(ACPI_REG_PCI_LINK_ACTIVE, 1), + FIELDLIST_OFFSET(PCH_PCIE_CFG_SPR), + FIELDLIST_RESERVED(7), + FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_SAVE_STATE, 1), + FIELDLIST_OFFSET(PCH_PCIE_CFG_RPPGEN), + FIELDLIST_RESERVED(2), + FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_ENTRY, 1), + FIELDLIST_NAMESTR(ACPI_REG_PCI_L23_RDY_DETECT, 1), + }; + uint8_t pcie_rp; + + /* dGPU PCIe configuration space */ + const struct opregion gpu_pci_config = OPREGION("PCIC", PCI_CONFIG, 0, 0x50); + const struct fieldlist gpu_fieldlist[] = { + FIELDLIST_OFFSET(PCH_PCIE_CFG_SSID), + FIELDLIST_NAMESTR(ACPI_REG_PCI_SUBSYSTEM_ID, 32), + }; + + if (!is_dev_enabled(parent)) { + printk(BIOS_ERR, "%s: root port not enabled\n", __func__); + return; + } + if (!scope) { + printk(BIOS_ERR, "%s: root port scope not found\n", __func__); + return; + } + if (!config->enable_gpio.pin_count && !config->reset_gpio.pin_count) { + printk(BIOS_ERR, "%s: Enable and/or Reset GPIO required for %s.\n", + __func__, scope); + return; + } + if (config->srcclk_pin > CONFIG_MAX_PCIE_CLOCK_SRC) { + printk(BIOS_ERR, "%s: Invalid clock pin %u for %s.\n", __func__, + config->srcclk_pin, scope); + return; + } + + /* Read port number of root port that this device is attached to. */ + pcie_rp = pci_read_config8(parent, PCH_PCIE_CFG_LCAP_PN); + if (pcie_rp == 0 || pcie_rp > CONFIG_MAX_ROOT_PORTS) { + printk(BIOS_ERR, "%s: Invalid root port number: %u\n", __func__, pcie_rp); + return; + } + /* Port number is 1-based, PMC IPC method expects 0-based. */ + pcie_rp--; + + printk(BIOS_INFO, "%s: Enable RTD3 for %s (%s)\n", scope, dev_path(parent), + config->desc ?: dev->chip_ops->name); + + /* The RTD3 power resource is added to the root port, not the device. */ + acpigen_write_scope(scope); + + if (config->desc) + acpigen_write_name_string("_DDN", config->desc); + + acpigen_write_power_res("PWRR", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + acpigen_write_name_integer("_STA", 1); + + acpigen_write_method_serialized("_ON", 0); + acpigen_write_store_int_to_namestr(1, "_STA"); + acpigen_pop_len(); /* Method */ + + acpigen_write_method_serialized("_OFF", 0); + acpigen_write_store_int_to_namestr(0, "_STA"); + acpigen_pop_len(); /* Method */ + + acpigen_pop_len(); /* PowerResource */ + + + /* GPU scope */ + acpigen_write_device("DEV0"); + acpigen_write_name_integer("_ADR", 0x0); + acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); + + acpigen_write_opregion(&rp_pci_config); + acpigen_write_field("PXCS", rp_fieldlist, ARRAY_SIZE(rp_fieldlist), + FIELD_ANYACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_write_opregion(&gpu_pci_config); + acpigen_write_field("PCIC", gpu_fieldlist, ARRAY_SIZE(gpu_fieldlist), + FIELD_DWORDACC | FIELD_NOLOCK | FIELD_PRESERVE); + + acpigen_write_power_res("PWRR", 0, 0, power_res_states, ARRAY_SIZE(power_res_states)); + + acpigen_write_name_integer("_STA", 0xF); + + nvidia_optimus_acpi_method_on(pcie_rp, dev); + nvidia_optimus_acpi_method_off(pcie_rp, dev); + + acpigen_pop_len(); /* PowerResource */ + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ +} + +static const char *nvidia_optimus_acpi_name(const struct device *dev) +{ + /* Attached device name must be "PXSX" for the Linux Kernel to recognize it. */ + return "PXSX"; +} + +static struct device_operations nvidia_optimus_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_fill_ssdt = nvidia_optimus_acpi_fill_ssdt, + .acpi_name = nvidia_optimus_acpi_name, + .ops_pci = &pci_dev_ops_pci, +}; + +static void nvidia_optimus_acpi_enable(struct device *dev) +{ + dev->ops = &nvidia_optimus_ops; +} + +struct chip_operations drivers_gfx_nvidia_optimus_ops = { + .name = "NVIDIA Optimus Hybrid Graphics", + .enable_dev = nvidia_optimus_acpi_enable +}; diff --git a/src/drivers/intel/fsp2_0/Makefile.mk b/src/drivers/intel/fsp2_0/Makefile.mk index 4cb24ffb56d..f13b1d42289 100644 --- a/src/drivers/intel/fsp2_0/Makefile.mk +++ b/src/drivers/intel/fsp2_0/Makefile.mk @@ -122,7 +122,7 @@ ifeq ($(CONFIG_PLATFORM_USES_SECOND_FSP)$(CONFIG_FSP_FULL_FD),yy) $(obj)/Fsp_2_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH_2)) $(DOTCONFIG) python 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH_2) -o "$(obj)" -n "Fsp_2.fd" -$(obj)/Fsp_2_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH_2)) $(obj)/Fsp_M.fd +$(obj)/Fsp_2_S.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH_2)) $(obj)/Fsp_2_M.fd true endif diff --git a/src/drivers/intel/fsp2_0/fsp_mpinit.c b/src/drivers/intel/fsp2_0/fsp_mpinit.c index cda9269cb8a..79fe006a733 100644 --- a/src/drivers/intel/fsp2_0/fsp_mpinit.c +++ b/src/drivers/intel/fsp2_0/fsp_mpinit.c @@ -1,7 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include -#include /* * As per FSP integration guide: @@ -10,5 +11,8 @@ */ void do_mpinit_after_fsp(void) { - init_cpus(); + struct device *dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); + assert(dev != NULL); + + mp_cpu_bus_init(dev); } diff --git a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c index 41fccd6a523..b697ccbf21f 100644 --- a/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c +++ b/src/drivers/intel/fsp2_0/ppi/mp_service_ppi.c @@ -61,7 +61,7 @@ efi_return_status_t mp_get_processor_info(efi_uintn_t processor_number, processor_info_buffer->ProcessorId = dev->path.apic.apic_id; processor_info_buffer->Location.Package = dev->path.apic.package_id; - processor_info_buffer->Location.Core = dev->path.apic.core_id; + processor_info_buffer->Location.Core = dev->path.apic.core_id_within_package; processor_info_buffer->Location.Thread = dev->path.apic.thread_id; return FSP_SUCCESS; diff --git a/src/drivers/intel/ptt/Makefile.mk b/src/drivers/intel/ptt/Makefile.mk index bab1789fd93..432035d4c70 100644 --- a/src/drivers/intel/ptt/Makefile.mk +++ b/src/drivers/intel/ptt/Makefile.mk @@ -1,5 +1,6 @@ ## SPDX-License-Identifier: GPL-2.0-only +bootblock-$(CONFIG_HAVE_INTEL_PTT) += ptt.c romstage-$(CONFIG_HAVE_INTEL_PTT) += ptt.c ramstage-$(CONFIG_HAVE_INTEL_PTT) += ptt.c postcar-$(CONFIG_HAVE_INTEL_PTT) += ptt.c diff --git a/src/drivers/option/cfr.c b/src/drivers/option/cfr.c index b323b4318a7..26bdd55f4d2 100644 --- a/src/drivers/option/cfr.c +++ b/src/drivers/option/cfr.c @@ -29,9 +29,6 @@ static uint32_t cfr_record_size(const char *startp, const char *endp) static uint32_t write_cfr_varchar(char *current, const char *string, uint32_t tag) { - uint8_t *data; - size_t padding; - ASSERT(string); if (!string) return 0; @@ -72,6 +69,25 @@ static uint32_t sm_write_ui_helptext(char *current, const char *string) return write_cfr_varchar(current, string, CFR_TAG_VARCHAR_UI_HELPTEXT); } +static uint32_t sm_write_dep_values(char *current, + const uint32_t *dep_values, const uint32_t num_dep_values) +{ + /* Dependency values are optional */ + if (!dep_values || !num_dep_values) + return 0; + + struct lb_cfr_varbinary *cfr_values = (struct lb_cfr_varbinary *)current; + cfr_values->tag = CFR_TAG_DEP_VALUES; + cfr_values->data_length = sizeof(*dep_values) * num_dep_values; + char *data = current + sizeof(*cfr_values); + memcpy(data, dep_values, cfr_values->data_length); + + /* Make sure that every TAG/SIZE field is always aligned to LB_ENTRY_ALIGN */ + cfr_values->size = ALIGN_UP(sizeof(*cfr_values) + cfr_values->data_length, LB_ENTRY_ALIGN); + + return cfr_values->size; +} + static uint32_t sm_write_enum_value(char *current, const struct sm_enum_value *e) { struct lb_cfr_enum_value *enum_val = (struct lb_cfr_enum_value *)current; @@ -88,8 +104,9 @@ static uint32_t sm_write_enum_value(char *current, const struct sm_enum_value *e static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t object_id, const char *opt_name, const char *ui_name, const char *ui_helptext, - uint32_t flags, uint32_t default_value, const struct sm_enum_value *values, - const uint64_t dep_id) + uint32_t flags, uint32_t default_value, uint32_t min, uint32_t max, uint32_t step, + uint32_t display_flags, const struct sm_enum_value *values, const uint64_t dep_id, + const uint32_t *dep_values, const uint32_t num_dep_values) { struct lb_cfr_numeric_option *option = (struct lb_cfr_numeric_option *)current; size_t len; @@ -98,9 +115,13 @@ static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t option->object_id = object_id; option->dependency_id = dep_id; option->flags = flags; - if (option->flags & (CFR_OPTFLAG_GRAYOUT | CFR_OPTFLAG_VOLATILE)) + if (option->flags & (CFR_OPTFLAG_INACTIVE | CFR_OPTFLAG_VOLATILE)) option->flags |= CFR_OPTFLAG_READONLY; option->default_value = default_value; + option->min = (min <= max) ? min : 0; + option->max = (min == 0 && max == 0) ? UINT32_MAX : max; + option->step = step; + option->display_flags = display_flags; option->size = sizeof(*option); current += option->size; @@ -113,6 +134,7 @@ static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t return 0; current += len; current += sm_write_ui_helptext(current, ui_helptext); + current += sm_write_dep_values(current, dep_values, num_dep_values); if (option->tag == CFR_TAG_OPTION_ENUM && values) { for (const struct sm_enum_value *e = values; e->ui_name; e++) { @@ -125,35 +147,42 @@ static uint32_t write_numeric_option(char *current, uint32_t tag, const uint64_t } static uint32_t sm_write_opt_enum(char *current, const struct sm_obj_enum *sm_enum, - const uint64_t object_id, const uint64_t dep_id) + const uint64_t object_id, const uint64_t dep_id, + const uint32_t *dep_values, const uint32_t num_dep_values) { return write_numeric_option(current, CFR_TAG_OPTION_ENUM, object_id, sm_enum->opt_name, sm_enum->ui_name, sm_enum->ui_helptext, - sm_enum->flags, sm_enum->default_value, sm_enum->values, - dep_id); + sm_enum->flags, sm_enum->default_value, 0, 0, 0, 0, sm_enum->values, + dep_id, dep_values, num_dep_values); } static uint32_t sm_write_opt_number(char *current, const struct sm_obj_number *sm_number, - const uint64_t object_id, const uint64_t dep_id) + const uint64_t object_id, const uint64_t dep_id, + const uint32_t *dep_values, const uint32_t num_dep_values) { return write_numeric_option(current, CFR_TAG_OPTION_NUMBER, object_id, sm_number->opt_name, sm_number->ui_name, sm_number->ui_helptext, - sm_number->flags, sm_number->default_value, NULL, dep_id); + sm_number->flags, sm_number->default_value, sm_number->min, sm_number->max, + sm_number->step, sm_number->display_flags, NULL, dep_id, dep_values, + num_dep_values); } static uint32_t sm_write_opt_bool(char *current, const struct sm_obj_bool *sm_bool, - const uint64_t object_id, const uint64_t dep_id) + const uint64_t object_id, const uint64_t dep_id, + const uint32_t *dep_values, const uint32_t num_dep_values) { return write_numeric_option(current, CFR_TAG_OPTION_BOOL, object_id, sm_bool->opt_name, sm_bool->ui_name, sm_bool->ui_helptext, - sm_bool->flags, sm_bool->default_value, NULL, dep_id); + sm_bool->flags, sm_bool->default_value, 0, 0, 0, 0, NULL, dep_id, + dep_values, num_dep_values); } static uint32_t sm_write_opt_varchar(char *current, const struct sm_obj_varchar *sm_varchar, - const uint64_t object_id, const uint64_t dep_id) + const uint64_t object_id, const uint64_t dep_id, + const uint32_t *dep_values, const uint32_t num_dep_values) { struct lb_cfr_varchar_option *option = (struct lb_cfr_varchar_option *)current; @@ -163,7 +192,7 @@ static uint32_t sm_write_opt_varchar(char *current, const struct sm_obj_varchar option->object_id = object_id; option->dependency_id = dep_id; option->flags = sm_varchar->flags; - if (option->flags & (CFR_OPTFLAG_GRAYOUT | CFR_OPTFLAG_VOLATILE)) + if (option->flags & (CFR_OPTFLAG_INACTIVE | CFR_OPTFLAG_VOLATILE)) option->flags |= CFR_OPTFLAG_READONLY; option->size = sizeof(*option); @@ -178,13 +207,15 @@ static uint32_t sm_write_opt_varchar(char *current, const struct sm_obj_varchar return 0; current += len; current += sm_write_ui_helptext(current, sm_varchar->ui_helptext); + current += sm_write_dep_values(current, dep_values, num_dep_values); option->size = cfr_record_size((char *)option, current); return option->size; } static uint32_t sm_write_opt_comment(char *current, const struct sm_obj_comment *sm_comment, - const uint32_t object_id, const uint32_t dep_id) + const uint32_t object_id, const uint32_t dep_id, + const uint32_t *dep_values, const uint32_t num_dep_values) { struct lb_cfr_option_comment *comment = (struct lb_cfr_option_comment *)current; size_t len; @@ -193,7 +224,7 @@ static uint32_t sm_write_opt_comment(char *current, const struct sm_obj_comment comment->object_id = object_id; comment->dependency_id = dep_id; comment->flags = sm_comment->flags; - if (comment->flags & (CFR_OPTFLAG_GRAYOUT | CFR_OPTFLAG_VOLATILE)) + if (comment->flags & (CFR_OPTFLAG_INACTIVE | CFR_OPTFLAG_VOLATILE)) comment->flags |= CFR_OPTFLAG_READONLY; comment->size = sizeof(*comment); @@ -203,6 +234,7 @@ static uint32_t sm_write_opt_comment(char *current, const struct sm_obj_comment return 0; current += len; current += sm_write_ui_helptext(current, sm_comment->ui_helptext); + current += sm_write_dep_values(current, dep_values, num_dep_values); comment->size = cfr_record_size((char *)comment, current); return comment->size; @@ -218,7 +250,8 @@ static uint64_t sm_gen_obj_id(void *ptr) static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj); static uint32_t sm_write_form(char *current, struct sm_obj_form *sm_form, - const uint64_t object_id, const uint64_t dep_id) + const uint64_t object_id, const uint64_t dep_id, + const uint32_t *dep_values, const uint32_t num_dep_values) { struct lb_cfr_option_form *form = (struct lb_cfr_option_form *)current; size_t len; @@ -228,7 +261,7 @@ static uint32_t sm_write_form(char *current, struct sm_obj_form *sm_form, form->object_id = object_id; form->dependency_id = dep_id; form->flags = sm_form->flags; - if (form->flags & (CFR_OPTFLAG_GRAYOUT | CFR_OPTFLAG_VOLATILE)) + if (form->flags & (CFR_OPTFLAG_INACTIVE | CFR_OPTFLAG_VOLATILE)) form->flags |= CFR_OPTFLAG_READONLY; form->size = sizeof(*form); @@ -237,6 +270,7 @@ static uint32_t sm_write_form(char *current, struct sm_obj_form *sm_form, if (!len) return 0; current += len; + current += sm_write_dep_values(current, dep_values, num_dep_values); while (sm_form->obj_list[i]) current += sm_write_object(current, sm_form->obj_list[i++]); @@ -248,6 +282,8 @@ static uint32_t sm_write_form(char *current, struct sm_obj_form *sm_form, static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj) { uint64_t dep_id, obj_id; + const uint32_t *dep_values; + uint32_t num_dep_values; struct sm_object sm_obj_copy; assert(sm_obj); @@ -256,10 +292,14 @@ static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj) /* Set dependency ID */ dep_id = 0; + dep_values = NULL; + num_dep_values = 0; if (sm_obj->dep) { - assert(sm_obj->dep->kind == SM_OBJ_BOOL); - if (sm_obj->dep->kind == SM_OBJ_BOOL) + if (sm_obj->dep->kind == SM_OBJ_BOOL || sm_obj->dep->kind == SM_OBJ_ENUM) { dep_id = sm_gen_obj_id((void *)sm_obj->dep); + dep_values = sm_obj->dep_values; + num_dep_values = sm_obj->num_dep_values; + } } /* Invoke callback to update fields */ @@ -276,21 +316,22 @@ static uint32_t sm_write_object(char *current, const struct sm_object *sm_obj) return 0; case SM_OBJ_ENUM: return sm_write_opt_enum(current, &sm_obj->sm_enum, obj_id, - dep_id); + dep_id, dep_values, num_dep_values); case SM_OBJ_NUMBER: return sm_write_opt_number(current, &sm_obj->sm_number, obj_id, - dep_id); + dep_id, dep_values, num_dep_values); case SM_OBJ_BOOL: return sm_write_opt_bool(current, &sm_obj->sm_bool, obj_id, - dep_id); + dep_id, dep_values, num_dep_values); case SM_OBJ_VARCHAR: return sm_write_opt_varchar(current, &sm_obj->sm_varchar, obj_id, - dep_id); + dep_id, dep_values, num_dep_values); case SM_OBJ_COMMENT: return sm_write_opt_comment(current, &sm_obj->sm_comment, obj_id, - dep_id); + dep_id, dep_values, num_dep_values); case SM_OBJ_FORM: - return sm_write_form(current, (struct sm_obj_form *)&sm_obj->sm_form, obj_id, dep_id); + return sm_write_form(current, (struct sm_obj_form *)&sm_obj->sm_form, obj_id, + dep_id, dep_values, num_dep_values); default: BUG(); printk(BIOS_ERR, "Unknown setup menu object kind %u, ignoring\n", sm_obj->kind); @@ -310,16 +351,17 @@ void cfr_write_setup_menu(struct lb_cfr *cfr_root, struct sm_obj_form *sm_root[] cfr_root->tag = LB_TAG_CFR_ROOT; cfr_root->size = sizeof(*cfr_root); + cfr_root->version = CFR_VERSION; current += cfr_root->size; while (sm_root && sm_root[i]) - current += sm_write_form(current, sm_root[i++], 0, 0); + current += sm_write_form(current, sm_root[i++], 0, 0, NULL, 0); /* * Add generic forms. */ for (obj = &_cfr_forms[0]; obj != &_ecfr_forms[0]; obj++) - current += sm_write_form(current, obj, 0, 0); + current += sm_write_form(current, obj, 0, 0, NULL, 0); cfr_root->size = cfr_record_size((char *)cfr_root, current); diff --git a/src/drivers/option/cfr_frontend.h b/src/drivers/option/cfr_frontend.h index 2161853f010..17332bdca44 100644 --- a/src/drivers/option/cfr_frontend.h +++ b/src/drivers/option/cfr_frontend.h @@ -30,6 +30,10 @@ struct sm_obj_number { const char *ui_name; const char *ui_helptext; uint32_t default_value; + uint32_t min; + uint32_t max; + uint32_t step; + uint32_t display_flags; /* enum cfr_numeric_option_display_flags */ }; struct sm_obj_bool { @@ -75,6 +79,8 @@ enum sm_object_kind { struct sm_object { enum sm_object_kind kind; const struct sm_object *dep; + const uint32_t *dep_values; + const uint32_t num_dep_values; void (*ctor)(const struct sm_object *obj, struct sm_object *new); /* Called on object creation */ union { struct sm_obj_enum sm_enum; @@ -87,21 +93,31 @@ struct sm_object { }; /* sm_object helpers with type checking */ -#define SM_DECLARE_ENUM(...) { .kind = SM_OBJ_ENUM, .dep = NULL, \ +#define SM_DECLARE_ENUM(...) { .kind = SM_OBJ_ENUM, .dep = NULL, \ + .dep_values = NULL, .num_dep_values = 0, \ .ctor = NULL, .sm_enum = __VA_ARGS__ } -#define SM_DECLARE_NUMBER(...) { .kind = SM_OBJ_NUMBER, .dep = NULL, \ +#define SM_DECLARE_NUMBER(...) { .kind = SM_OBJ_NUMBER, .dep = NULL, \ + .dep_values = NULL, .num_dep_values = 0, \ .ctor = NULL, .sm_number = __VA_ARGS__ } -#define SM_DECLARE_BOOL(...) { .kind = SM_OBJ_BOOL, .dep = NULL, \ +#define SM_DECLARE_BOOL(...) { .kind = SM_OBJ_BOOL, .dep = NULL, \ + .dep_values = NULL, .num_dep_values = 0, \ .ctor = NULL, .sm_bool = __VA_ARGS__ } -#define SM_DECLARE_VARCHAR(...) { .kind = SM_OBJ_VARCHAR, .dep = NULL, \ +#define SM_DECLARE_VARCHAR(...) { .kind = SM_OBJ_VARCHAR, .dep = NULL, \ + .dep_values = NULL, .num_dep_values = 0, \ .ctor = NULL, .sm_varchar = __VA_ARGS__ } -#define SM_DECLARE_COMMENT(...) { .kind = SM_OBJ_COMMENT, .dep = NULL, \ +#define SM_DECLARE_COMMENT(...) { .kind = SM_OBJ_COMMENT, .dep = NULL, \ + .dep_values = NULL, .num_dep_values = 0, \ .ctor = NULL, .sm_comment = __VA_ARGS__ } -#define SM_DECLARE_FORM(...) { .kind = SM_OBJ_FORM, .dep = NULL, \ +#define SM_DECLARE_FORM(...) { .kind = SM_OBJ_FORM, .dep = NULL, \ + .dep_values = NULL, .num_dep_values = 0, \ .ctor = NULL, .sm_form = __VA_ARGS__ } #define WITH_CALLBACK(c) .ctor = (c) #define WITH_DEP(d) .dep = (d) +#define WITH_DEP_VALUES(d, ...) \ + .dep = (d), \ + .dep_values = ((const uint32_t[]) { __VA_ARGS__ }), \ + .num_dep_values = sizeof((uint32_t[]) { __VA_ARGS__ }) / sizeof(uint32_t) void cfr_write_setup_menu(struct lb_cfr *cfr_root, struct sm_obj_form *sm_root[]); diff --git a/src/drivers/smmstore/smi.c b/src/drivers/smmstore/smi.c index 4f7b4bdac0a..3ac52dc3458 100644 --- a/src/drivers/smmstore/smi.c +++ b/src/drivers/smmstore/smi.c @@ -138,6 +138,9 @@ static uint32_t smmstorev2_exec(uint8_t command, void *param) uint32_t smmstore_exec(uint8_t command, void *param) { + if (smmstore_preprocess_cmd(&command, param)) + return SMMSTORE_RET_SUCCESS; + if (command != SMMSTORE_CMD_CLEAR && !param) return SMMSTORE_RET_FAILURE; diff --git a/src/drivers/smmstore/store.c b/src/drivers/smmstore/store.c index f1e07e41dd7..2fca79f180f 100644 --- a/src/drivers/smmstore/store.c +++ b/src/drivers/smmstore/store.c @@ -12,10 +12,17 @@ #define SMMSTORE_REGION "SMMSTORE" - +#if !CONFIG(SOC_INTEL_APOLLOLAKE) _Static_assert(IS_ALIGNED(FMAP_SECTION_SMMSTORE_START, SMM_BLOCK_SIZE), "SMMSTORE FMAP region not aligned to 64K"); - +#else +/* + * On APL and GLK the addresses in FMAP are off by 4KiB due to architectural + * changes in flash mapping to host memory space + */ +_Static_assert(IS_ALIGNED(FMAP_SECTION_SMMSTORE_START + 0x1000, SMM_BLOCK_SIZE), + "SMMSTORE FMAP region not aligned to 64K"); +#endif _Static_assert(SMM_BLOCK_SIZE <= FMAP_SECTION_SMMSTORE_SIZE, "SMMSTORE FMAP region must be at least 64K"); @@ -41,8 +48,43 @@ _Static_assert(SMM_BLOCK_SIZE <= FMAP_SECTION_SMMSTORE_SIZE, * crash/reboot could clear out all variables. */ +static int use_full_flash; +static int has_capsules = -1; + +int smmstore_preprocess_cmd(uint8_t *cmd, void *param) +{ + if (CONFIG(DRIVERS_EFI_UPDATE_CAPSULES)) { + if (has_capsules == -1 && *cmd == SMMSTORE_CMD_USE_FULL_FLASH) { + has_capsules = !!(uintptr_t)param; + /* + * If we have capsules, return success, otherwise let smmstore_exec() + * fail on !param check, which will be 0 in that case. This informs + * the caller whether capsule handling was enabled or not. + */ + return has_capsules; + } else if (has_capsules == 1 && *cmd & SMMSTORE_CMD_USE_FULL_FLASH) { + use_full_flash = 1; + *cmd &= ~SMMSTORE_CMD_USE_FULL_FLASH; + } else { + use_full_flash = 0; + } + } + + return 0; +} + static enum cb_err lookup_store_region(struct region *region) { + if (CONFIG(DRIVERS_EFI_UPDATE_CAPSULES) && use_full_flash) { + const struct region_device *rdev = boot_device_rw(); + + if (rdev == NULL) + return CB_ERR; + + *region = *region_device_region(rdev); + return CB_SUCCESS; + } + if (fmap_locate_area(SMMSTORE_REGION, region)) { printk(BIOS_WARNING, "smm store: Unable to find SMM store FMAP region '%s'\n", diff --git a/src/drivers/tpm/Kconfig b/src/drivers/tpm/Kconfig index 1bcc79c8e9b..42630ff44f7 100644 --- a/src/drivers/tpm/Kconfig +++ b/src/drivers/tpm/Kconfig @@ -3,8 +3,8 @@ config TPM_INIT_RAMSTAGE bool default y if TPM - depends on !VBOOT && !VENDORCODE_ELTAN_VBOOT && !VENDORCODE_ELTAN_MBOOT \ - && !TPM_MEASURED_BOOT_INIT_BOOTBLOCK + depends on (!VBOOT || VBOOT_NO_TPM) && !VENDORCODE_ELTAN_VBOOT \ + && !VENDORCODE_ELTAN_MBOOT && !TPM_MEASURED_BOOT_INIT_BOOTBLOCK help This driver automatically initializes the TPM if vboot is not used. The TPM driver init is done during the ramstage chip init phase. diff --git a/src/ec/dasharo/ec/Makefile.mk b/src/ec/dasharo/ec/Makefile.mk index d71a2fd9981..998941f98b9 100644 --- a/src/ec/dasharo/ec/Makefile.mk +++ b/src/ec/dasharo/ec/Makefile.mk @@ -6,4 +6,9 @@ all-y += dasharo_ec.c all-y += buttons.c smm-$(CONFIG_DEBUG_SMI) += dasharo_ec.c +cbfs-files-$(CONFIG_EC_DASHARO_EC_UPDATE) += ec.rom +ec.rom-file := $(call strip_quotes,$(CONFIG_EC_DASHARO_EC_UPDATE_FILE)) +ec.rom-compression := $(CBFS_COMPRESS_FLAG) +ec.rom-type := raw + endif diff --git a/src/ec/dasharo/ec/acpi/battery.asl b/src/ec/dasharo/ec/acpi/battery.asl index 106f3d1be01..b4d98300a3d 100644 --- a/src/ec/dasharo/ec/acpi/battery.asl +++ b/src/ec/dasharo/ec/acpi/battery.asl @@ -193,22 +193,8 @@ Device (BAT0) { If (^^PCI0.LPCB.EC0.BAT0) { - Local0 = 0 - Local1 = 0 - If (^^AC.ACFG) - { - If (((^^PCI0.LPCB.EC0.BST0 & 0x02) == 0x02)) - { - Local0 |= 0x02 - Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) - } - } - Else - { - Local0 |= 1 - Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) - } - + Local0 = ^^PCI0.LPCB.EC0.BST0 + Local1 = (^^PCI0.LPCB.EC0.BPR0 & 0xFFFF) Local7 = (Local1 & 0x8000) If ((Local7 == 0x8000)) { diff --git a/src/ec/dasharo/ec/acpi/dtt.asl b/src/ec/dasharo/ec/acpi/dtt.asl new file mode 100644 index 00000000000..1dd85c58963 --- /dev/null +++ b/src/ec/dasharo/ec/acpi/dtt.asl @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Device (TPWR) +{ + Name (_HID, DPTF_TPWR_DEVICE) + Name (_UID, "TPWR") + Name (_STR, Unicode("Intel DTT Power Participant")) + + Method (_STA, 0, NotSerialized) + { + Return (0x0F) + } + + Name (PTYP, 0x11) // Device is a platform power device + + Method (PSRC, 0) // Power source + { + Return (^^AC.ACFG) + } + + Method (ARTG, 0) // Adapter rating + { + If (^^PCI0.LPCB.EC0.ECOK) + { + Return (^^PCI0.LPCB.EC0.APWR) + } + Else + { + Return (0) + } + } + + Method (PBOK, 1) // Power Boss OK + { + // Notify EC to de-assert PROCHOT# + // Required by DTT, but N/A on this hardware, PROCHOT# + // is de-asserted by board logic upon AC plug-in + } +} + +Device (TBAT) +{ + Name (_HID, DPTF_BAT1_DEVICE) + Name (_STR, Unicode("Intel DTT Battery Participant")) + + Method (_STA, 0, NotSerialized) + { + Return (^^BAT0._STA) + } + + Name (PTYP, 0x0c) // Device is a platform battery device + Name (CTYP, 0x02) // Hybrid Power Boost architecture +} diff --git a/src/ec/dasharo/ec/acpi/ec.asl b/src/ec/dasharo/ec/acpi/ec.asl index e13c52dc390..c58b6bb9dab 100644 --- a/src/ec/dasharo/ec/acpi/ec.asl +++ b/src/ec/dasharo/ec/acpi/ec.asl @@ -7,6 +7,7 @@ Scope (\_SB) { #include "hid.asl" #include "lid.asl" #include "dasharo.asl" + #include "dtt.asl" } Device (\_SB.PCI0.LPCB.EC0) @@ -107,6 +108,7 @@ Device (\_SB.PCI0.LPCB.EC0) Method (_Q0A, 0, NotSerialized) // Touchpad Toggle { Printf ("EC: Touchpad Toggle") + TPTG () } Method (_Q0B, 0, NotSerialized) // Screen Toggle @@ -175,6 +177,7 @@ Device (\_SB.PCI0.LPCB.EC0) Printf ("EC: AC Detect") ^^^^AC.ACFG = ADP Notify (AC, 0x80) // Status Change + Notify (TPWR, 0x81) // Power State Change If (BAT0) { Notify (^^^^BAT0, 0x81) // Information Change diff --git a/src/ec/dasharo/ec/acpi/ec_ram.asl b/src/ec/dasharo/ec/acpi/ec_ram.asl index 008737785bd..8cd565cbd46 100644 --- a/src/ec/dasharo/ec/acpi/ec_ram.asl +++ b/src/ec/dasharo/ec/acpi/ec_ram.asl @@ -42,6 +42,9 @@ Field (ERAM, ByteAcc, Lock, Preserve) DUT2, 8, // Fan 2 duty RPM1, 16, // Fan 1 RPM RPM2, 16, // Fan 2 RPM + Offset (0xD4), + GPUD, 8, // GPU D-notify level + APWR, 32, // AC adapter power Offset (0xD9), AIRP, 8, // Airplane mode LED WINF, 8, // Enable ACPI brightness controls diff --git a/src/ec/dasharo/ec/commands.h b/src/ec/dasharo/ec/commands.h index 0fe7db40989..e5de0dcc515 100644 --- a/src/ec/dasharo/ec/commands.h +++ b/src/ec/dasharo/ec/commands.h @@ -79,6 +79,12 @@ // Persistent option definitions enum { OPT_POWER_ON_AC = 0, + OPT_KBLED_LEVEL_I, + OPT_KBLED_COLOR_I, + OPT_BAT_THRESHOLD_START, + OPT_BAT_THRESHOLD_STOP, + OPT_ALLOW_BAT_BOOST, + OPT_ALWAYS_ON_USB, NUM_OPTIONS }; diff --git a/src/ec/dasharo/ec/dasharo_ec.c b/src/ec/dasharo/ec/dasharo_ec.c index 571c6a06d01..ea311f6a437 100644 --- a/src/ec/dasharo/ec/dasharo_ec.c +++ b/src/ec/dasharo/ec/dasharo_ec.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -25,6 +26,33 @@ // When command register is 0, command is complete #define CMD_FINISHED 0 +#define SPI_WREN 0x06 /* Write Enable */ +#define SPI_WRDI 0x04 /* Write Disable */ +#define SPI_RDSR 0x05 /* Read Status Register */ +#define SPI_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define SPI_AAI_WP 0xad /* Auto Address Increment Word Program */ +#define SPI_BE 0xd7 /* 1K Block Erase */ + +#define SPI_SR_WIP (1 << 0) /* Write-in-Progress */ +#define SPI_SR_WEL (1 << 1) /* Write enable */ + +#define SPI_TIMEOUT_10MS 10000 + +#define SPI_ACCESS_SIZE 252 + +#define MAX_WRITE_RETRY 3 + +enum ec_update_error { + /* AC adapter is not connected. */ + EC_UPDATE_ERR_NO_AC, + /* EC did not jump to scratch ROM */ + EC_UPDATE_ERR_SCRATCH, + /* EC erase failed */ + EC_UPDATE_ERR_ERASE, + /* Programming EC failed */ + EC_UPDATE_ERR_PROGRAM, +}; + static inline uint8_t dasharo_ec_read(uint8_t addr) { return inb(DASHARO_EC_BASE + (uint16_t)addr); @@ -39,12 +67,14 @@ uint8_t dasharo_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data) { int i; - if (len > DASHARO_EC_SIZE - REG_DATA) + if (len > DASHARO_EC_SIZE - REG_DATA) { + printk(BIOS_ERR, "dasharo_ec: Invalid command length\n"); return -1; + } // Wait for previous command completion, for up to 10 milliseconds, with a // test period of 1 microsecond - wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); // Write data first for (i = 0; i < len; ++i) @@ -55,7 +85,7 @@ uint8_t dasharo_ec_smfi_cmd(uint8_t cmd, uint8_t len, uint8_t *data) // Wait for previous command completion, for up to 10 milliseconds, with a // test period of 1 microsecond - wait_us(10000, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); return dasharo_ec_read(REG_RESULT); } @@ -91,3 +121,845 @@ void dasharo_ec_set_bat_threshold(enum bat_threshold_type type, uint8_t value) break; } } + +uint8_t dasharo_ec_read_version(uint8_t *data) +{ + int i; + uint8_t result; + + if (!data) + return -1; + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + // Write command register, which starts command + dasharo_ec_write(REG_CMD, CMD_VERSION); + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + result = dasharo_ec_read(REG_RESULT); + + if (result != 0) + return result; + + // Read data bytes, index should be valid due to length test above + for (i = 0; i < (DASHARO_EC_SIZE - REG_DATA); i++) { + data[i] = dasharo_ec_read(REG_DATA + i); + if (data[i] == '\0') + break; + } + + return result; +} + +uint8_t dasharo_ec_read_board(uint8_t *data) +{ + int i; + uint8_t result; + + if (!data) + return -1; + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + // Write command register, which starts command + dasharo_ec_write(REG_CMD, CMD_BOARD); + + // Wait for previous command completion, for up to 10 milliseconds, with a + // test period of 1 microsecond + wait_us(SPI_TIMEOUT_10MS, dasharo_ec_read(REG_CMD) == CMD_FINISHED); + + result = dasharo_ec_read(REG_RESULT); + + if (result != 0) + return result; + + // Read data bytes, index should be valid due to length test above + for (i = 0; i < (DASHARO_EC_SIZE - REG_DATA); i++) { + data[i] = dasharo_ec_read(REG_DATA + i); + if (data[i] == '\0') + break; + } + + return result; +} + +/* Ported from system76_ectool */ +static int firmware_str(char *data, int data_len, const char *key, char *dest, int dest_len) +{ + int data_i, key_i, ret_i; + int key_len = strlen(key); + + data_i = key_i = ret_i = 0; + + /* Locate the key */ + while (data_i < data_len && key_i < key_len) { + if (data[data_i] == key[key_i]) + key_i += 1; + else + key_i = 0; + data_i += 1; + } + + if (key_i < key_len) + return 0; + + while (data_i < data_len && ret_i < dest_len - 1 && data[data_i] != 0) + dest[ret_i++] = data[data_i++]; + + dest[ret_i] = '\0'; + + return ret_i; +} + +/* Reset the EC SPI bus */ +static uint8_t ec_spi_reset(void) +{ + uint8_t reset_cmd = CMD_SPI_FLAG_DISABLE | CMD_SPI_FLAG_SCRATCH; + + return dasharo_ec_smfi_cmd(CMD_SPI, sizeof(reset_cmd), &reset_cmd); +} + +/* + * Read len bytes from EC SPI bus into dest. + * Returns 0 on success, <0 on error + */ +static int ec_spi_bus_read(uint8_t *dest, uint32_t len) +{ + uint32_t addr, i, rv; + + uint8_t read_cmd[2] = { + [0] = CMD_SPI_FLAG_READ | CMD_SPI_FLAG_SCRATCH, + [1] = 0, + }; + + for (addr = 0; addr + SPI_ACCESS_SIZE < len; addr += SPI_ACCESS_SIZE) { + read_cmd[1] = SPI_ACCESS_SIZE; + + if ((rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(read_cmd), read_cmd))) { + printk(BIOS_ERR, "dasharo_ec: Failed to send read SPI bus command\n"); + return -rv; + } + + if (dasharo_ec_read(REG_DATA + 1) != read_cmd[1]) { + printk(BIOS_ERR, "dasharo_ec: SPI bus read insufficient bytes\n"); + return -1; + } + + for (i = 0; i < read_cmd[1]; i++) + dest[addr + i] = dasharo_ec_read(REG_DATA + 2 + i); + } + + if (addr == len) + return 0; + + read_cmd[1] = len % SPI_ACCESS_SIZE; + + if ((rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(read_cmd), read_cmd))) { + printk(BIOS_ERR, "dasharo_ec: Failed to send read SPI bus command (remainder)\n"); + return -rv; + } + + if (dasharo_ec_read(REG_DATA + 1) != read_cmd[1]) { + printk(BIOS_ERR, "dasharo_ec: SPI bus read remainder insufficient bytes\n"); + return -1; + } + + for (i = 0; i < read_cmd[1]; i++) + dest[addr + i] = dasharo_ec_read(REG_DATA + 2 + i); + + return 0; +} + +/* + * Write len bytes from data to EC SPI bus with flags. + * Returns 0 on success, <0 on error + */ +static int ec_spi_bus_write_with_flags(uint8_t *data, uint8_t len, uint8_t flags) +{ + uint32_t addr, i, rv; + uint8_t write_cmd[2] = { + [0] = CMD_SPI_FLAG_SCRATCH | flags, + [1] = len, + }; + + for (addr = 0; addr + SPI_ACCESS_SIZE < len; addr += SPI_ACCESS_SIZE) { + write_cmd[1] = SPI_ACCESS_SIZE; + + for (i = 0; i < write_cmd[1]; ++i) + dasharo_ec_write(REG_DATA + ARRAY_SIZE(write_cmd) + i, data[addr + i]); + + rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(write_cmd), write_cmd); + if (rv) { + printk(BIOS_ERR, "dasharo_ec: Failed to send write SPI bus command\n"); + return -rv; + } + + if (dasharo_ec_read(REG_DATA + 1) != write_cmd[1]) { + printk(BIOS_ERR, "dasharo_ec: SPI bus write insufficient bytes\n"); + return -1; + } + } + + if (addr == len) + return 0; + + write_cmd[1] = len % SPI_ACCESS_SIZE; + + for (i = 0; i < write_cmd[1]; i++) + dasharo_ec_write(REG_DATA + ARRAY_SIZE(write_cmd) + i, data[addr + i]); + + rv = dasharo_ec_smfi_cmd(CMD_SPI, ARRAY_SIZE(write_cmd), write_cmd); + if (rv) { + printk(BIOS_ERR, "dasharo_ec: Failed to send write SPI bus command (remainder)\n"); + return -rv; + } + + if (dasharo_ec_read(REG_DATA + 1) != write_cmd[1]) { + printk(BIOS_ERR, "dasharo_ec: SPI bus write remainder insufficient bytes\n"); + return -1; + } + + return 0; +} + +/* + * Write len bytes from data to EC SPI bus + * Returns 0 on success, <0 on error + */ +static int ec_spi_bus_write(uint8_t *data, uint8_t len) +{ + return ec_spi_bus_write_with_flags(data, len, 0); +} + +static int ec_spi_wait_status(uint8_t mask, uint8_t value, const char *func, + const unsigned int line) +{ + struct stopwatch sw; + uint8_t status; + int rv; + uint8_t cmd = SPI_RDSR; + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + rv = ec_spi_bus_write(&cmd, sizeof(cmd)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + stopwatch_init_usecs_expire(&sw, SPI_TIMEOUT_10MS); + + rv = ec_spi_bus_read(&status, sizeof(status)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_read failed\n", __func__); + return rv; + } + + while ((status & mask) != value) { + if (stopwatch_expired(&sw)) { + printk(BIOS_ERR, "%s: Timeout at %s:%u\n", __func__, func, line); + ec_spi_reset(); + return -1; + } + + /* + * Status Register can be constantly read from SPI bus. + * No need to start new RDSR command. + */ + rv = ec_spi_bus_read(&status, sizeof(status)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_read failed\n", __func__); + ec_spi_reset(); + return rv; + } + } + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + return 0; +} + +static int ec_spi_cmd_write_enable(void) +{ + int rv; + uint8_t cmd = SPI_WREN;; + + rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + if (rv) { + printk(BIOS_ERR, "%s: flash not ready\n", __func__); + return rv; + } + + rv = ec_spi_bus_write(&cmd, sizeof(cmd)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + return ec_spi_wait_status(SPI_SR_WIP | SPI_SR_WEL, SPI_SR_WEL, __func__, __LINE__); +} + +static int ec_spi_cmd_write_disable(void) +{ + int rv; + uint8_t cmd = SPI_WRDI; + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + rv = ec_spi_bus_write(&cmd, sizeof(cmd)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + return ec_spi_wait_status(SPI_SR_WIP | SPI_SR_WEL, 0, __func__, __LINE__); +} + +/* Erase a sector at addr. Returns 0 on success <0 on error. */ +static int ec_spi_erase_sector(uint32_t addr) +{ + int rv; + uint8_t buf[4] = { + [0] = SPI_BE, + [1] = (addr >> 16) & 0xFF, + [2] = (addr >> 8) & 0xFF, + [3] = addr & 0xFF, + }; + + rv = ec_spi_cmd_write_enable(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_cmd_write_enable failed\n", __func__); + return rv; + } + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + rv = ec_spi_bus_write(buf, ARRAY_SIZE(buf)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + if (rv) + return rv; + + rv = ec_spi_cmd_write_disable(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_cmd_write_disable failed\n", __func__); + return rv; + } + + return 0; +} + +/* Read a sector into dest. Returns 0 on success and <0 on error. */ +static int ec_spi_read_sector(uint8_t *dest, uint32_t addr) +{ + int rv; + uint8_t buf[5] = { + [0] = SPI_FAST_READ, + [1] = (addr >> 16) & 0xFF, + [2] = (addr >> 8) & 0xFF, + [3] = addr & 0xFF, + [4] = 0, + }; + + rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + if (rv) + return rv; + + rv = ec_spi_bus_write(buf, ARRAY_SIZE(buf)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + rv = ec_spi_bus_read(dest, SPI_SECTOR_SIZE); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_read failed\n", __func__); + return rv; + } + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + return 0; +} + +/* Read a sector and verify if it has been erased. Returns 0 on success and <0 on error. */ +static int ec_spi_verify_erased_sector(uint32_t addr) +{ + int rv, i; + uint8_t buf[5] = { + [0] = SPI_FAST_READ, /* SPI Read */ + [1] = (addr >> 16) & 0xFF, + [2] = (addr >> 8) & 0xFF, + [3] = addr & 0xFF, + [4] = 0, + }; + uint8_t data; + + rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + if (rv) + return rv; + + rv = ec_spi_bus_write(buf, ARRAY_SIZE(buf)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed\n", __func__); + return rv; + } + + for (i = 0; i < SPI_SECTOR_SIZE; i++) { + /* Read the sector byte after byte and compare. */ + rv = ec_spi_bus_read(&data, sizeof(data)); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_read failed\n", __func__); + return rv; + } + + if (data != 0xff) { + printk(BIOS_ERR, "%s: sector at %x is not erased\n", __func__, addr); + return -1; + } + } + + rv = ec_spi_reset(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_reset failed\n", __func__); + return rv; + } + + return 0; +} + +/* + * Program a chip with a given image at given address and size of data. + * Returns written byte count on success and <0 on error. + */ +static int ec_spi_write_at(uint32_t start, uint8_t *image, size_t size) +{ + int rv; + uint32_t addr; + uint8_t buf[6] = {0}; + + buf[0] = SPI_AAI_WP; + buf[1] = (start >> 16) & 0xff; + buf[2] = (start >> 8) & 0xff; + buf[3] = start & 0xff; + + rv = ec_spi_cmd_write_enable(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_cmd_write_enable failed\n", __func__); + return rv; + } + + for (addr = start; addr < start + size; addr += 2) { + + /* + * ec_spi_cmd_write_enable ends with ec_spi_wait_status which always calls + * ec_spi_reset. No need to do it here again. We also reset the SPI + * (make the CS# go high) after AAI WP command* by passing the + * CMD_SPI_FLAG_DISABLE to ec_spi_bus_write_with_flags. + */ + + if (addr == start) { + /* 1st cmd bytes 1,2,3 are the address */ + buf[4] = image[addr]; + buf[5] = image[addr + 1]; + + rv = ec_spi_bus_write_with_flags(buf, 6, CMD_SPI_FLAG_DISABLE); + } else { + buf[1] = image[addr]; + buf[2] = image[addr + 1]; + + rv = ec_spi_bus_write_with_flags(buf, 3, CMD_SPI_FLAG_DISABLE); + } + + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_bus_write failed, addr 0x%06x\n", + __func__, addr); + return rv; + } + + /* + * From the experiments it looked like the busy bit is never set. + * It is still dangerous to not probe the bit, however, AAI programming + * is quite picky and stops after first 2 bytes if we interrupt the + * process with different command than AAI word program. + * + * rv = ec_spi_wait_status(SPI_SR_WIP, 0, __func__, __LINE__); + * if (rv) return rv; + */ + } + + rv = ec_spi_cmd_write_disable(); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_cmd_write_disable failed\n", __func__); + return rv; + } + + return addr - start; +} + +/* + * Program an entire chip with a given image. + * Returns written byte count on success and <0 on error. + */ +static int ec_spi_image_write(uint8_t *image, size_t size) +{ + uint8_t *sector; + uint32_t addr; + uint32_t erase_addr = CONFIG_EC_DASHARO_EC_FLASH_SIZE; + size_t length; + int rv; + + sector = malloc(SPI_SECTOR_SIZE); + if (!sector) + return -1; + + rv = 0; + addr = 0; + + while ((addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE) && + ((addr + SPI_SECTOR_SIZE) < size)) { + rv = ec_spi_read_sector(sector, addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_read_sector failed, addr 0x%06x\n", + __func__, addr); + goto cleanup; + } + + if (!memcmp(sector, image + addr, SPI_SECTOR_SIZE)) { + printk(BIOS_SPEW, "%s: Skipping identical sector, addr 0x%06x\n", + __func__, addr); + addr += SPI_SECTOR_SIZE; + continue; + } + + rv = ec_spi_erase_sector(addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_erase_sector failed, addr 0x%06x\n", + __func__, addr); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_ERASE); + goto cleanup; + } + + rv = ec_spi_verify_erased_sector(addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_verify_erased_sector failed, addr 0x%06x\n", + __func__, addr); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_ERASE); + goto cleanup; + } + + rv = ec_spi_write_at(addr, image, SPI_SECTOR_SIZE); + if (rv < 0) { + printk(BIOS_ERR, "%s: ec_spi_write_at failed, addr 0x%06x (%d)\n", + __func__, addr, rv); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_PROGRAM); + goto cleanup; + } + + addr += SPI_SECTOR_SIZE; + } + + /* Update any remainder bytes */ + rv = ec_spi_read_sector(sector, addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_read_sector failed, last addr 0x%06x\n", + __func__, addr); + goto cleanup; + } + + erase_addr = addr + SPI_SECTOR_SIZE; + + if (size % SPI_SECTOR_SIZE == 0 && addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE) + length = SPI_SECTOR_SIZE; + else + length = size % SPI_SECTOR_SIZE; + + if (memcmp(sector, image + addr, length)) { + rv = ec_spi_erase_sector(addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_erase_sector failed, addr 0x%06x\n", + __func__, addr); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_ERASE); + goto cleanup; + } + + rv = ec_spi_write_at(addr, image, length); + if (rv < 0) { + printk(BIOS_ERR, "%s: ec_spi_write_at failed, addr 0x%06x (%d)\n", + __func__, addr, rv); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_PROGRAM); + goto cleanup; + } + + addr += length; + } else { + printk(BIOS_SPEW, "%s: Skipping identical sector, addr 0x%06x\n", + __func__, addr); + addr += length; + } + + /* Erase remaining sectors if any */ + while (erase_addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE) { + rv = ec_spi_erase_sector(erase_addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_erase_sector failed, addr 0x%06x\n", + __func__, erase_addr); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_ERASE); + goto cleanup; + } + erase_addr += SPI_SECTOR_SIZE; + } + +cleanup: + free(sector); + + return rv ? rv : addr; +} + +/* Verify an image sector by sector. Returns 0 on success and <0 on error. */ +static int ec_spi_image_verify(uint8_t *image, ssize_t image_sz) +{ + uint8_t *sector; + uint32_t addr; + int rv; + int error = 0; + + sector = malloc(SPI_SECTOR_SIZE); + if (!sector) + return -1; + + rv = 0; + addr = 0; + + while ((addr < CONFIG_EC_DASHARO_EC_FLASH_SIZE) && + ((addr + SPI_SECTOR_SIZE) < image_sz)) { + rv = ec_spi_read_sector(sector, addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_read_sector failed, addr 0x%06x\n", + __func__, addr); + return rv; + } + + rv = memcmp(sector, image + addr, SPI_SECTOR_SIZE) ? -1 : 0; + if (rv) { + printk(BIOS_ERR, "%s: failed to verify sector, addr 0x%06x\n", + __func__, addr); + error = rv; + } + + addr += SPI_SECTOR_SIZE; + } + + if (addr == image_sz) + goto exit; + + rv = ec_spi_read_sector(sector, addr); + if (rv) { + printk(BIOS_ERR, "%s: ec_spi_read_sector failed, last addr 0x%06x\n", + __func__, addr); + goto exit; + } + + rv = memcmp(sector, image + addr, image_sz % SPI_SECTOR_SIZE) ? -1 : 0; + if (rv) { + printk(BIOS_ERR, "%s: failed to verify last sector, addr 0x%06x size 0x%lx\n", + __func__, addr, image_sz % SPI_SECTOR_SIZE); + goto exit; + } + +exit: + free(sector); + + if (error) + return error; + + return rv; +} + +/* Sync the EC firmware with an image contained in CBFS. */ +static void dasharo_ec_fw_sync(void *unused) +{ + size_t image_sz; + char *image; + char img_board_str[64]; + char img_version_str[64]; + char cur_board_str[64]; + char cur_version_str[64]; + uint8_t smfi_cmd; + int rv; + + if (!CONFIG(EC_DASHARO_EC_UPDATE)) + return; + + if (vboot_recovery_mode_enabled()) { + printk(BIOS_INFO, "EC: skipping update in recovery mode.\n"); + return; + } + + image = malloc(CONFIG_EC_DASHARO_EC_FLASH_SIZE); + if (image == NULL) { + printk(BIOS_ERR, "EC: failed to allocate memory for update."); + return; + } + + image_sz = cbfs_load("ec.rom", image, CONFIG_EC_DASHARO_EC_FLASH_SIZE); + if (!image_sz) { + printk(BIOS_ERR, "EC: failed to load update from CBFS."); + goto cleanup; + } + + printk(BIOS_INFO, "EC: update found (%ld bytes)\n", image_sz); + + /* Sanity checks */ + if (image_sz % 2 || image_sz > CONFIG_EC_DASHARO_EC_FLASH_SIZE) { + printk(BIOS_ERR, "EC: incorrect update size.\n"); + goto cleanup; + } + + if (!firmware_str(image, image_sz, "76EC_BOARD=", img_board_str, + ARRAY_SIZE(img_board_str))) { + printk(BIOS_ERR, "EC: could not determine update target board.\n"); + goto cleanup; + } + + if (!firmware_str(image, image_sz, "76EC_VERSION=", img_version_str, + ARRAY_SIZE(img_version_str))) { + printk(BIOS_ERR, "EC: could not determine update version.\n"); + goto cleanup; + } + + printk(BIOS_INFO, "EC: update target: %s\n", img_board_str); + printk(BIOS_INFO, "EC: update version: %s\n", img_version_str); + + dasharo_ec_read_board((uint8_t *)cur_board_str); + dasharo_ec_read_version((uint8_t *)cur_version_str); + + if (strcmp(img_board_str, cur_board_str)) { + printk(BIOS_ERR, "EC: update target mismatch detected! Found %s, expected %s\n", + img_board_str, cur_board_str); + goto cleanup; + } + + printk(BIOS_INFO, "EC: current version: %s\n", cur_version_str); + if (!strcmp(img_version_str, cur_version_str)) { + printk(BIOS_INFO, "EC: update not needed.\n"); + goto cleanup; + } else { + printk(BIOS_INFO, "EC: update required!\n"); + } + + if ((ec_read(0x10) & 0x01) != 0x01) { + printk(BIOS_WARNING, "EC: AC adapter not connected, skipping update.\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_NO_AC); + goto cleanup; + } + + /* Jump to Scratch ROM */ + smfi_cmd = CMD_SPI_FLAG_SCRATCH; + if (dasharo_ec_smfi_cmd(CMD_SPI, sizeof(smfi_cmd), &smfi_cmd)) { + /* If we failed to jump to scratch ROM, then we can probably continue booting. */ + printk(BIOS_ERR, "EC: failed to jump to scratch ROM!\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_SCRATCH); + goto cleanup; + } + + for (int i = 0; i < MAX_WRITE_RETRY; i++) { + rv = ec_spi_image_write((uint8_t *)image, image_sz); + if (rv < 0) { + /* EC is now in an unknown state. It may still boot from backup. */ + printk(BIOS_ALERT, "EC: update failed!\n"); + } else { + printk(BIOS_INFO, "EC: wrote %x bytes\n", rv); + } + + rv = ec_spi_image_verify((uint8_t *)image, image_sz); + if (rv < 0) { + printk(BIOS_ALERT, "EC: update verification failed! (try: %d)\n", + i + 1); + } else { + printk(BIOS_INFO, "EC: update verified.\n"); + rv = 0; + break; + } + } + + if (rv < 0) { + /* EC is now in an unknown state. It may still boot from backup. */ + printk(BIOS_ALERT, "EC: update failed!\n"); + if (CONFIG(VBOOT)) + vboot_fail_and_reboot(vboot_get_context(), + VB2_RECOVERY_EC_SOFTWARE_SYNC, + EC_UPDATE_ERR_PROGRAM); + goto cleanup; + } + + smfi_cmd = CMD_SPI_FLAG_DISABLE; + if (dasharo_ec_smfi_cmd(CMD_SPI, sizeof(smfi_cmd), &smfi_cmd)) { + printk(BIOS_ERR, "EC: failed to disable SPI bus!\n"); + goto cleanup; + } + + smfi_cmd = 0; + if (dasharo_ec_smfi_cmd(CMD_RESET, sizeof(smfi_cmd), &smfi_cmd)) + printk(BIOS_ERR, "EC: failed to trigger reset!\n"); + +cleanup: + free(image); + return; +} + +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, dasharo_ec_fw_sync, NULL); diff --git a/src/include/cpu/x86/mp.h b/src/include/cpu/x86/mp.h index dd86dce2c54..f80d309bbb8 100644 --- a/src/include/cpu/x86/mp.h +++ b/src/include/cpu/x86/mp.h @@ -135,6 +135,13 @@ enum cb_err mp_run_on_all_cpus_synchronously(void (*func)(void *), void *arg); */ enum cb_err mp_park_aps(void); +/* + * Restart APs after they have been parked. Used by Intel TXT, which requires + * parking APs before running ACM , to restart APs and let coreboot program + * MTRRs on APs. For use only after mp_init. + */ +enum cb_err restart_aps(void); + /* * SMM helpers to use with initializing CPUs. */ diff --git a/src/include/device/path.h b/src/include/device/path.h index 8e9ec3bdd50..03aa909d889 100644 --- a/src/include/device/path.h +++ b/src/include/device/path.h @@ -81,6 +81,12 @@ struct apic_path { unsigned int node_id; unsigned int core_id; unsigned int thread_id; + unsigned int module_id; + /* + * Core identifier within the package, including the die group, die, tile, module, and + * specific core. + */ + unsigned int core_id_within_package; unsigned char core_type; }; diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 6748b356b73..a824dd55db8 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -574,7 +574,8 @@ #define PCI_REBAR_CTRL_NBARS_SHIFT 5 #define PCI_REBAR_CTRL_IDX_MASK 0x07 #define PCI_REBAR_CTRL_SIZE_MASK 0xffff0000 -#define PCI_REBAR_CTRL_SIZE_SHIFT 16 +#define PCI_REBAR_CTRL_BAR_SIZE_MASK 0xffff00ff +#define PCI_REBAR_CTRL_BAR_SIZE_SHIFT 8 /* Root Complex Event Collector Endpoint Association */ #define PCI_RCECEA_BITMAP 4 diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 60ed807f31e..604dd6dcfaa 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3535,6 +3535,7 @@ #define PCI_DID_INTEL_ADL_P_PCIE_RP1 0x464d #define PCI_DID_INTEL_ADL_P_PCIE_RP2 0x460d #define PCI_DID_INTEL_ADL_P_PCIE_RP3 0x463d +#define PCI_DID_INTEL_ADL_P_PCIE_RP4 0x462d #define PCI_DID_INTEL_ADP_P_PCIE_RP1 0x51b8 #define PCI_DID_INTEL_ADP_P_PCIE_RP2 0x51b9 @@ -4276,6 +4277,8 @@ #define PCI_DID_INTEL_ADL_N_GT1 0x46D0 #define PCI_DID_INTEL_ADL_N_GT2 0x46D1 #define PCI_DID_INTEL_ADL_N_GT3 0x46D2 +#define PCI_DID_INTEL_ADL_N_GT4 0x46D3 +#define PCI_DID_INTEL_ADL_N_GT5 0x46D4 #define PCI_DID_INTEL_MTL_M_GT2 0x7d40 #define PCI_DID_INTEL_MTL_P_GT2_1 0x7d45 #define PCI_DID_INTEL_MTL_P_GT2_2 0x7d50 @@ -4290,6 +4293,8 @@ #define PCI_DID_INTEL_RPL_S_GT1_1 0xa780 #define PCI_DID_INTEL_RPL_S_GT1_2 0xa782 #define PCI_DID_INTEL_RPL_S_GT1_3 0xa783 +#define PCI_DID_INTEL_RPL_S_GT1_4 0xa792 +#define PCI_DID_INTEL_RPL_S_GT1_5 0xa793 #define PCI_DID_INTEL_RPL_P_GT1 0xa720 #define PCI_DID_INTEL_RPL_P_GT2 0xa7a8 #define PCI_DID_INTEL_RPL_P_GT3 0xa7a0 @@ -4444,6 +4449,7 @@ #define PCI_DID_INTEL_RPL_S_ID_3 0xa703 #define PCI_DID_INTEL_RPL_S_ID_4 0xa704 #define PCI_DID_INTEL_RPL_S_ID_5 0xa705 +#define PCI_DID_INTEL_RPL_S_ID_6 0xa740 #define PCI_DID_INTEL_RPL_P_ID_1 0xa706 #define PCI_DID_INTEL_RPL_P_ID_2 0xa707 #define PCI_DID_INTEL_RPL_P_ID_3 0xa708 diff --git a/src/include/efi/efi_datatype.h b/src/include/efi/efi_datatype.h index a5e8ec3014b..76ab55378a4 100644 --- a/src/include/efi/efi_datatype.h +++ b/src/include/efi/efi_datatype.h @@ -4,6 +4,12 @@ #ifndef __EFI_DATATYPE_H__ #define __EFI_DATATYPE_H__ +/* + * Make sure NULL is defined before including EDK2 headers. Otherwise, Base.h + * defines it causing to fail on redefinition. + */ +#include + /* * EDK2 EFIAPI macro definition relies on compiler flags such as __GNUC__ which * is not working well when included by coreboot. While it has no side-effect on diff --git a/src/include/smbios.h b/src/include/smbios.h index fd44e098d4e..894fe35ccf7 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -122,7 +122,9 @@ int smbios_write_type8(unsigned long *current, int *handle, #define BIOS_CHARACTERISTICS_BIOS_SOCKETED (1 << 17) #define BIOS_EXT1_CHARACTERISTICS_ACPI (1 << 0) +#define BIOS_EXT2_CHARACTERISTICS_BIOS_BOOT (1 << 1) #define BIOS_EXT2_CHARACTERISTICS_TARGET (1 << 2) +#define BIOS_EXT2_CHARACTERISTICS_UEFI (1 << 3) #define BIOS_MEMORY_ECC_SINGLE_BIT_CORRECTING (1 << 3) #define BIOS_MEMORY_ECC_DOUBLE_BIT_CORRECTING (1 << 4) diff --git a/src/include/smmstore.h b/src/include/smmstore.h index 6805cbc0696..202e681ab9f 100644 --- a/src/include/smmstore.h +++ b/src/include/smmstore.h @@ -21,6 +21,9 @@ #define SMMSTORE_CMD_RAW_WRITE 6 #define SMMSTORE_CMD_RAW_CLEAR 7 +/* Used by capsule updates as a standalone command or modifier to v2 commands */ +#define SMMSTORE_CMD_USE_FULL_FLASH 0x80 + /* Version 1 */ struct smmstore_params_read { void *buf; @@ -117,6 +120,8 @@ int smmstore_get_info(struct smmstore_params_info *info); #endif struct region_device; int smmstore_lookup_region(struct region_device *rstore); +/* Returns 0 if normal parsing should continue, 1 otherwise */ +int smmstore_preprocess_cmd(uint8_t *cmd, void *param); /* Advertise SMMSTORE v2 support */ struct lb_header; diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index 434d674755a..d9fffe89c38 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -9,6 +9,7 @@ #define SPD_PAGE_LEN 256 #define SPD_PAGE_LEN_DDR4 512 +#define SPD_LEN_DDR5 1024 #define SPD_PAGE_0 (0x6C >> 1) #define SPD_PAGE_1 (0x6E >> 1) #define SPD_DRAM_TYPE 2 @@ -36,6 +37,18 @@ #define DDR4_SPD_PART_OFF 329 #define DDR4_SPD_PART_LEN 20 #define DDR4_SPD_SN_OFF 325 +#define MAX_SPD_PAGE_SIZE_SPD5 128 +#define MAX_SPD_SIZE (SPD_PAGE_LEN * 4) +#define SPD_HUB_MEMREG(addr) ((u8)(0x80 | (addr))) +#define SPD5_MR11 0x0B +#define SPD5_MR0 0x00 +#define SPD5_MEMREG_REG(addr) ((u8)((~0x80) & (addr))) +#define SPD5_MR0_SPD5_HUB_DEV 0x51 + +struct spd_offset_table { + u16 start; /* Offset 0 */ + u16 end; /* Offset 2 */ +}; struct spd_block { u8 addr_map[CONFIG_DIMM_MAX]; /* 7 bit I2C addresses */ diff --git a/src/include/version.h b/src/include/version.h index 926756a5345..1698e371b38 100644 --- a/src/include/version.h +++ b/src/include/version.h @@ -3,6 +3,12 @@ #ifndef VERSION_H #define VERSION_H +/* Dasharo version */ +extern const char dasharo_version[]; +extern const unsigned int dasharo_major_revision; +extern const unsigned int dasharo_minor_revision; +extern const unsigned int dasharo_patch_revision; + /* coreboot Version */ extern const char coreboot_version[]; extern const char coreboot_extra_version[]; diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 03624bf2d7b..cbb6b316001 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -481,6 +481,7 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, struct region_device rdev; bool preload_successful = false; union cbfs_mdata mdata; + bool skip_verification = false; DEBUG("%s(name='%s', alloc=%p(%p), force_ro=%s, type=%d)\n", __func__, name, allocator, arg, force_ro ? "true" : "false", type ? *type : -1); @@ -503,7 +504,14 @@ void *_cbfs_alloc(const char *name, cbfs_allocator_t allocator, void *arg, if (!force_ro && get_preload_rdev(&rdev, name) == CB_SUCCESS) preload_successful = true; - void *ret = do_alloc(&mdata, &rdev, allocator, arg, size_out, false); + /* + * Bootblock will never have its hash due to how CBFS_VERIFICATION works. + * Skip its verification to let CRTM initialization pass. + */ + if (type && *type == CBFS_TYPE_BOOTBLOCK) + skip_verification = true; + + void *ret = do_alloc(&mdata, &rdev, allocator, arg, size_out, skip_verification); /* When using cbfs_preload we need to free the preload buffer after populating the * destination buffer. We know we must have a mem_rdev here, so extra mmap is fine. */ diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 3902c88eff5..1c126a7a7fe 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -274,6 +274,7 @@ static void add_cbmem_pointers(struct lb_header *header) {CBMEM_ID_FMAP, LB_TAG_FMAP}, {CBMEM_ID_VBOOT_WORKBUF, LB_TAG_VBOOT_WORKBUF}, {CBMEM_ID_TYPE_C_INFO, LB_TAG_TYPE_C_INFO}, + {CBMEM_ID_TIANOCORE_LOGO, LB_TAG_LOGO}, }; int i; @@ -422,6 +423,37 @@ void __weak lb_board(struct lb_header *header) { /* NOOP */ } */ void __weak lb_spi_flash(struct lb_header *header) { /* NOOP */ } + +/* + * Allocator for bootlogo that prepends a header to the logo CBMEM entry + */ +static void *logo_cbmem_allocator(void *arg, size_t size, const union cbfs_mdata *unused) +{ + struct bootlogo_header header; + void *logo_loc; + + header.size = size; + logo_loc = cbmem_entry_start(cbmem_entry_add((uintptr_t)arg, size + sizeof(header))); + memcpy(logo_loc, &header, sizeof(header)); + return logo_loc + sizeof(header); +} + +/* + * Loads the logo bitmap file from the BOOTSPLASH fmap region into CBMEM + */ +static void tianocore_logo_load(int ignored) +{ + size_t logo_size; + + cbfs_unverified_area_alloc("BOOTSPLASH", + "logo.bmp", + logo_cbmem_allocator, + (void *)CBMEM_ID_TIANOCORE_LOGO, + &logo_size); +} + +CBMEM_READY_HOOK(tianocore_logo_load); + static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header) { diff --git a/src/lib/smbios.c b/src/lib/smbios.c index 9cee637b695..66e64e23679 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -391,8 +391,8 @@ static int smbios_write_type0(unsigned long *current, int handle) else t->extended_bios_rom_size = DIV_ROUND_UP(CONFIG_ROM_SIZE, MiB); - t->system_bios_major_release = coreboot_major_revision; - t->system_bios_minor_release = coreboot_minor_revision; + t->system_bios_major_release = dasharo_major_revision; + t->system_bios_minor_release = dasharo_minor_revision; smbios_ec_revision(&t->ec_major_release, &t->ec_minor_release); @@ -408,6 +408,13 @@ static int smbios_write_type0(unsigned long *current, int handle) t->bios_characteristics_ext1 = BIOS_EXT1_CHARACTERISTICS_ACPI; t->bios_characteristics_ext2 = BIOS_EXT2_CHARACTERISTICS_TARGET; + + if (CONFIG(PAYLOAD_SEABIOS)) + t->bios_characteristics_ext2 |= BIOS_EXT2_CHARACTERISTICS_BIOS_BOOT; + + if (CONFIG(PAYLOAD_EDK2)) + t->bios_characteristics_ext2 |= BIOS_EXT2_CHARACTERISTICS_UEFI; + const int len = smbios_full_table_len(&t->header, t->eos); *current += len; return len; diff --git a/src/lib/spd_cache.c b/src/lib/spd_cache.c index dff6ede8609..1398da6fb78 100644 --- a/src/lib/spd_cache.c +++ b/src/lib/spd_cache.c @@ -209,7 +209,9 @@ enum cb_err spd_fill_from_cache(uint8_t *spd_cache, struct spd_block *blk) dram_type = *(spd_cache + SC_SPD_OFFSET(i) + SPD_DRAM_TYPE); - if (dram_type == SPD_DRAM_DDR4) + if (dram_type == SPD_DRAM_DDR5) + blk->len = SPD_LEN_DDR5; + else if (dram_type == SPD_DRAM_DDR4) blk->len = SPD_PAGE_LEN_DDR4; else blk->len = SPD_PAGE_LEN; diff --git a/src/lib/version.c b/src/lib/version.c index 43d6a458212..49e6647c1e2 100644 --- a/src/lib/version.c +++ b/src/lib/version.c @@ -18,6 +18,22 @@ #define COREBOOT_EXTRA_VERSION "" #endif +#ifndef DASHARO_VERSION +#define DASHARO_VERSION "*INVALID*" +#endif + +#ifndef DASHARO_MAJOR_VERSION +#define DASHARO_MAJOR_VERSION 0 +#endif + +#ifndef DASHARO_MINOR_VERSION +#define DASHARO_MINOR_VERSION 0 +#endif + +#ifndef DASHARO_PATCH_VERSION +#define DASHARO_PATCH_VERSION 0 +#endif + const char coreboot_version[] = COREBOOT_VERSION; const char coreboot_extra_version[] = COREBOOT_EXTRA_VERSION; const char coreboot_build[] = COREBOOT_BUILD; @@ -25,6 +41,11 @@ const unsigned int coreboot_version_timestamp = COREBOOT_VERSION_TIMESTAMP; const unsigned int coreboot_major_revision = COREBOOT_MAJOR_VERSION; const unsigned int coreboot_minor_revision = COREBOOT_MINOR_VERSION; +const char dasharo_version[] = DASHARO_VERSION; +const unsigned int dasharo_major_revision = DASHARO_MAJOR_VERSION; +const unsigned int dasharo_minor_revision = DASHARO_MINOR_VERSION; +const unsigned int dasharo_patch_revision = DASHARO_PATCH_VERSION; + const char coreboot_compile_time[] = COREBOOT_COMPILE_TIME; const char coreboot_dmi_date[] = COREBOOT_DMI_DATE; diff --git a/src/mainboard/clevo/adl-p/Kconfig b/src/mainboard/clevo/adl-p/Kconfig new file mode 100644 index 00000000000..7c5ba6bfcef --- /dev/null +++ b/src/mainboard/clevo/adl-p/Kconfig @@ -0,0 +1,133 @@ +config BOARD_CLEVO_ADLP_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select EC_DASHARO_EC + select EC_ACPI + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select SOC_INTEL_ALDERLAKE_PCH_P + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config BOARD_CLEVO_NS50PU_BASE + bool + select BOARD_CLEVO_ADLP_COMMON + select DRIVERS_GENERIC_BAYHUB_LV2 + +config BOARD_CLEVO_NS50PU + bool + select BOARD_CLEVO_NS50PU_BASE + +config BOARD_CLEVO_NV40PZ_BASE + bool + select BOARD_CLEVO_ADLP_COMMON + select EC_DASHARO_EC_DGPU + select DRIVERS_GENERIC_BAYHUB_LV2 + +config BOARD_CLEVO_NV40PZ + bool + select BOARD_CLEVO_NV40PZ_BASE + +if BOARD_CLEVO_ADLP_COMMON + +config MAINBOARD_DIR + default "clevo/adl-p" + +config VARIANT_DIR + default "ns50pu" if BOARD_CLEVO_NS50PU_BASE + default "nv40pz" if BOARD_CLEVO_NV40PZ_BASE + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_PART_NUMBER + default "ns50pu" if BOARD_CLEVO_NS50PU_BASE + default "nv40pz" if BOARD_CLEVO_NV40PZ_BASE + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "NS5x_NS7xPU" if BOARD_CLEVO_NS50PU_BASE + default "NV4xPZ" if BOARD_CLEVO_NV40PZ_BASE + +config MAINBOARD_SMBIOS_MANUFACTURER + default "Notebook" + +config MAINBOARD_VERSION + default "ns50pu" if BOARD_CLEVO_NS50PU_BASE + default "nv40pz" if BOARD_CLEVO_NV40PZ_BASE + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match stock firmware + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config DIMM_SPD_SIZE + default 512 + +config ONBOARD_VGA_IS_PRIMARY + default y + +config POST_DEVICE + default n + +config UART_FOR_CONSOLE + default 0 + +# PM Timer Disabled, saves power +config USE_PM_ACPI_TIMER + default n + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config VBOOT_VBNV_OFFSET + default 0x28 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + +config TPM_PIRQ + default 0x27 # GPP_E1 + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config VBOOT_FWID_VERSION + default "\$(CONFIG_LOCALVERSION)" + +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 20 + +endif + +endif diff --git a/src/mainboard/clevo/adl-p/Kconfig.name b/src/mainboard/clevo/adl-p/Kconfig.name new file mode 100644 index 00000000000..fa3a0fd11a8 --- /dev/null +++ b/src/mainboard/clevo/adl-p/Kconfig.name @@ -0,0 +1,7 @@ +comment "Alder Lake P" + +config BOARD_CLEVO_NS50PU + bool "NS5xPU / NS7xPU" + +config BOARD_CLEVO_NV40PZ + bool "NV4xPZ" diff --git a/src/mainboard/clevo/adl-p/Makefile.mk b/src/mainboard/clevo/adl-p/Makefile.mk new file mode 100644 index 00000000000..771d702af51 --- /dev/null +++ b/src/mainboard/clevo/adl-p/Makefile.mk @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +romstage-y += variants/$(VARIANT_DIR)/romstage.c + +ramstage-y += ramstage.c +ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c + +SPD_SOURCES = samsung-P4AAF165WA-BCWDE diff --git a/src/mainboard/clevo/adl-p/acpi/backlight.asl b/src/mainboard/clevo/adl-p/acpi/backlight.asl new file mode 100644 index 00000000000..01fa83ea610 --- /dev/null +++ b/src/mainboard/clevo/adl-p/acpi/backlight.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (GFX0) +{ + Name (BRIG, Package (23) { + 40, /* default AC */ + 40, /* default Battery */ + 0, + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/clevo/adl-p/acpi/mainboard.asl b/src/mainboard/clevo/adl-p/acpi/mainboard.asl new file mode 100644 index 00000000000..da2a78c694a --- /dev/null +++ b/src/mainboard/clevo/adl-p/acpi/mainboard.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#define CPU_CRIT_TEMP 100 +#define GPU_CRIT_TEMP 105 +#include + +Scope (\_SB) { + #include "sleep.asl" + Scope (PCI0) { + #include "backlight.asl" + } +} + +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +If (S0IX == 0) { + Name(\_S3, Package(){0x5,0x0,0x0,0x0}) +} Else { + Name(\_S1, Package(){0x1,0x0,0x0,0x0}) +} +#if !CONFIG(DISABLE_ACPI_HIBERNATE) +Name(\_S4, Package(){0x6,0x0,0x0,0x0}) +#endif +Name(\_S5, Package(){0x7,0x0,0x0,0x0}) diff --git a/src/mainboard/clevo/adl-p/acpi/sleep.asl b/src/mainboard/clevo/adl-p/acpi/sleep.asl new file mode 100644 index 00000000000..4e7d79798dd --- /dev/null +++ b/src/mainboard/clevo/adl-p/acpi/sleep.asl @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + + /* Bring system out of TC cold before enter Sx */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* HACK: Inform EC to apply PMC hack for S0ix issue */ + \_SB.PCI0.LPCB.EC0.PTS (0) + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + /* Bring system out of TC cold */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () + } +} diff --git a/src/mainboard/clevo/adl-p/acpi/touchpad.asl b/src/mainboard/clevo/adl-p/acpi/touchpad.asl new file mode 100644 index 00000000000..0ac407185f4 --- /dev/null +++ b/src/mainboard/clevo/adl-p/acpi/touchpad.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External (\_SB.PCI0.I2C0.H038, DeviceObj) +External (\_SB.PCI0.I2C0.H038._STA, IntObj) + +External (\_SB.PCI0.I2C0.H015, DeviceObj) +External (\_SB.PCI0.I2C0.H015._STA, IntObj) + +Method (TPTG, 0, Serialized) +{ + If (CondRefOf (\_SB.PCI0.I2C0.H038)) { + If (\_SB.PCI0.I2C0.H038._STA == Zero) { + \_SB.PCI0.I2C0.H038._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H038._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H038, One) + } + + If (CondRefOf (\_SB.PCI0.I2C0.H015)) { + If (\_SB.PCI0.I2C0.H015._STA == Zero) { + \_SB.PCI0.I2C0.H015._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H015._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H015, One) + } +} diff --git a/src/mainboard/clevo/adl-p/board_info.txt b/src/mainboard/clevo/adl-p/board_info.txt new file mode 100644 index 00000000000..5220e452c84 --- /dev/null +++ b/src/mainboard/clevo/adl-p/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Clevo +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/clevo/adl-p/bootblock.c b/src/mainboard/clevo/adl-p/bootblock.c new file mode 100644 index 00000000000..8d06adc9d7f --- /dev/null +++ b/src/mainboard/clevo/adl-p/bootblock.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void bootblock_mainboard_early_init(void) +{ + mainboard_configure_early_gpios(); +} diff --git a/src/mainboard/clevo/adl-p/cmos.default b/src/mainboard/clevo/adl-p/cmos.default new file mode 100644 index 00000000000..972deace70b --- /dev/null +++ b/src/mainboard/clevo/adl-p/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable +kbl_brightness=0xff +kbl_color=0x00ffffff diff --git a/src/mainboard/clevo/adl-p/cmos.layout b/src/mainboard/clevo/adl-p/cmos.layout new file mode 100644 index 00000000000..fa2067eb9f0 --- /dev/null +++ b/src/mainboard/clevo/adl-p/cmos.layout @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 304 r 0 reserved_memory + +# coreboot config options: ramtop +304 80 h 0 ramtop + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# Vboot non-volatile data +432 128 r 0 vbnv + +984 16 h 0 check_sum + +# embedded controller settings +1024 8 h 0 kbl_brightness +1032 32 h 0 kbl_color + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 431 984 diff --git a/src/mainboard/clevo/adl-p/devicetree.cb b/src/mainboard/clevo/adl-p/devicetree.cb new file mode 100644 index 00000000000..2420dd51a62 --- /dev/null +++ b/src/mainboard/clevo/adl-p/devicetree.cb @@ -0,0 +1,127 @@ +chip soc/intel/alderlake + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable S0ix / Modern Standby + register "s0ix_enable" = "1" + + # Enable C6 DRAM + register "enable_c6dram" = "1" + + # Thermal + register "tcc_offset" = "20" # TCC of 80C + + # Noise mitigation + register "acoustic_noise_mitigation" = "1" + register "slow_slew_rate[VR_DOMAIN_IA]" = "SLEW_FAST_8" + register "slow_slew_rate[VR_DOMAIN_GT]" = "SLEW_FAST_8" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_IA]" = "1" + register "fast_pkg_c_ramp_disable[VR_DOMAIN_GT]" = "1" + register "PreWake" = "150" + + # VR configuration + # +-----------+-------+-------+---------+-------------+----------+ + # | Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time | + # | |(mOhms)|(mOhms)| (A) | (A) | (msec) | + # +-----------+-------+-------+---------+-------------+----------+ + # | IA | 2.3 | 2.3 | 109 | 63 | 28000 | + # +-----------+-------+-------+---------+-------------+----------+ + # | GT | 3.1 | 3.1 | 50 | 30 | 28000 | + # +-----------+-------+-------+---------+-------------+----------+ + register "domain_vr_config[VR_DOMAIN_IA]" = "{ + .vr_config_enable = 1, + .ac_loadline = 230, + .dc_loadline = 230, + .icc_max = VR_CFG_AMP(109), + .tdc_timewindow = 28000, + .tdc_currentlimit = VR_CFG_TDC_AMP(63), + }" + + register "domain_vr_config[VR_DOMAIN_GT]" = "{ + .vr_config_enable = 1, + .ac_loadline = 310, + .dc_loadline = 310, + .icc_max = VR_CFG_AMP(50), + .tdc_timewindow = 28000, + .tdc_currentlimit = VR_CFG_TDC_AMP(30), + }" + + device cpu_cluster 0 on end + device domain 0 on + device ref system_agent on end + device ref igpu on + # DDIA is eDP, DDIB is HDMI + register "ddi_portA_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + }" + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref tbt_pcie_rp0 on end + device ref shared_sram on end + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref uart0 on # BIOS Debug Port + register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoPci" + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E12)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + + device ref heci1 on end + device ref pch_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0e01" # AP/EC command + register "gen3_dec" = "0x00fc0f01" # AP/EC debug + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref hda on + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/clevo/adl-p/dsdt.asl b/src/mainboard/clevo/adl-p/dsdt.asl new file mode 100644 index 00000000000..f911aae34a2 --- /dev/null +++ b/src/mainboard/clevo/adl-p/dsdt.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + } + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" + #include "acpi/touchpad.asl" +} diff --git a/src/mainboard/clevo/adl-p/fadt.c b/src/mainboard/clevo/adl-p/fadt.c new file mode 100644 index 00000000000..0967bc9a95b --- /dev/null +++ b/src/mainboard/clevo/adl-p/fadt.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + /* Control method power button (EC) */ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/clevo/adl-p/include/mainboard/gpio.h b/src/mainboard/clevo/adl-p/include/mainboard/gpio.h new file mode 100644 index 00000000000..57924a615fa --- /dev/null +++ b/src/mainboard/clevo/adl-p/include/mainboard/gpio.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/clevo/adl-p/ramstage.c b/src/mainboard/clevo/adl-p/ramstage.c new file mode 100644 index 00000000000..ba3f2c30262 --- /dev/null +++ b/src/mainboard/clevo/adl-p/ramstage.c @@ -0,0 +1,283 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct smfi_cmd_set_fan_curve { + uint8_t fan; + struct fan_curve curve; +} __packed; + +struct fan_curve fan_curve_silent = { + { .temp = 0, .duty = 20 }, + { .temp = 65, .duty = 25 }, + { .temp = 75, .duty = 35 }, + { .temp = 85, .duty = 100 } +}; + +struct fan_curve fan_curve_performance = { + { .temp = 0, .duty = 25 }, + { .temp = 55, .duty = 35 }, + { .temp = 75, .duty = 60 }, + { .temp = 85, .duty = 100} +}; + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +static void set_fan_curve(void) +{ + int i; + uint8_t selection = get_fan_curve_option(); + struct smfi_cmd_set_fan_curve cmd; + + switch (selection) { + case FAN_CURVE_OPTION_SILENT: + cmd.curve = fan_curve_silent; + break; + case FAN_CURVE_OPTION_PERFORMANCE: + cmd.curve = fan_curve_performance; + break; + default: + cmd.curve = fan_curve_silent; + break; + } + + for (i = 0; i < (CONFIG(EC_DASHARO_EC_DGPU) ? 2 : 1); ++i) { + cmd.fan = i; + dasharo_ec_smfi_cmd(CMD_FAN_CURVE_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); + } +} + +static void set_camera_enablement(void) +{ + bool enabled = get_camera_option(); + + dasharo_ec_smfi_cmd(CMD_CAMERA_ENABLEMENT_SET, sizeof(enabled) / sizeof(uint8_t), (uint8_t *)&enabled); +} + +static void set_battery_thresholds(void) +{ + struct battery_config bat_cfg; + + get_battery_config(&bat_cfg); + + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_START, bat_cfg.start_threshold); + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_STOP, bat_cfg.stop_threshold); +} + +static void set_power_on_ac(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_POWER_ON_AC, + 0 + }; + + cmd.value = dasharo_get_power_on_after_fail(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); +} + +static void set_usb_charge_port(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_ALWAYS_ON_USB, + 0 + }; + + cmd.value = dasharo_get_usb_port_power(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); +} + +static void mainboard_init(void *chip_info) +{ + config_t *cfg = config_of_soc(); + struct device *wlan_dev = pcidev_on_root(0x1c, 4); + struct device *cnvi_dev = pcidev_on_root(0x14, 3); + bool radio_enable = get_wireless_option(); + + printk(BIOS_DEBUG, "Wireless is %sabled\n", radio_enable ? "en" : "dis"); + + wlan_dev->enabled = radio_enable; + cnvi_dev->enabled = radio_enable; + cfg->cnvi_bt_core = radio_enable; + cfg->cnvi_bt_audio_offload = radio_enable; + cfg->usb2_ports[9].enable = radio_enable; + + dasharo_ec_smfi_cmd(CMD_WIFI_BT_ENABLEMENT_SET, 1, (uint8_t *)&radio_enable); + + mainboard_configure_gpios(); + set_fan_curve(); + set_camera_enablement(); + set_battery_thresholds(); + set_power_on_ac(); + set_usb_charge_port(); +} + +#if CONFIG(GENERATE_SMBIOS_TABLES) +static uint8_t read_proprietary_ec_version(uint8_t *data) +{ + int i, result; + char ec_version[16]; + + if (!data) + return -1; + + if (send_ec_command(0x93)) + return -1; + + for (i = 0; i < 16 - 1; i++) { + + result = recv_ec_data(); + if (result != -1) + ec_version[i] = result & 0xff; + + if (ec_version[i] == '$') { + ec_version[i] = '\0'; + break; + } + } + ec_version[15] = '\0'; + + data[0] = '1'; + data[1] = '.'; + + strcpy((char *)&data[2], ec_version); + + return 0; +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + char ec_version[256]; + uint8_t result; + + result = dasharo_ec_read_version((uint8_t *)ec_version); + + /* If the command fails it mean we are running proprietary EC most likely */ + if (result != 0) { + printk(BIOS_ERR, "Failed to read open EC firmware version\n"); + result = read_proprietary_ec_version((uint8_t *)ec_version); + if (result == 0) + t->count = smbios_add_string(t->eos, "EC: proprietary"); + else + t->count = smbios_add_string(t->eos, "EC: unknown"); + } else { + t->count = smbios_add_string(t->eos, "EC: open-source"); + } + + if (result == 0) { + printk(BIOS_DEBUG, "EC firmware version: %s\n", ec_version); + t->count = smbios_add_string(t->eos, strconcat("EC firmware version: ", + ec_version)); + } else { + printk(BIOS_ERR, "Unable to probe EC firmware version\n"); + t->count = smbios_add_string(t->eos, "EC firmware version: unknown"); + } + +} +#endif + + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_strings = mainboard_smbios_strings; +#endif +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .init = mainboard_init, +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->CnviRfResetPinMux = 0x194CE404; // GPP_F4 + params->CnviClkreqPinMux = 0x394CE605; // GPP_F5 + + params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6 + params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7 + + // DEVSLP doesn't work due to broken board design (crossed wiring) + params->SataPortDevSlpPinMux[0] = 0x59673e0c; // GPP_H12 + params->SataPortDevSlpPinMux[1] = 0x5967400d; // GPP_H13 + + params->SataPortsSolidStateDrive[1] = 1; + + params->PcieRpEnableCpm[4] = 1; + params->PcieRpEnableCpm[5] = 1; + params->PcieRpEnableCpm[7] = 1; + params->PcieRpEnableCpm[8] = 1; + params->PcieRpEnableCpm[9] = 1; + + params->PcieRpAcsEnabled[4] = 1; + params->PcieRpAcsEnabled[5] = 1; + params->PcieRpAcsEnabled[7] = 1; + params->PcieRpAcsEnabled[8] = 1; + params->PcieRpAcsEnabled[9] = 1; + + params->PcieRpMaxPayload[4] = 1; + params->PcieRpMaxPayload[5] = 1; + params->PcieRpMaxPayload[7] = 1; + params->PcieRpMaxPayload[8] = 1; + params->PcieRpMaxPayload[9] = 1; + + params->PcieRpPmSci[4] = 1; + params->PcieRpPmSci[5] = 1; + params->PcieRpPmSci[7] = 1; + params->PcieRpPmSci[8] = 1; + params->PcieRpPmSci[9] = 1; + + params->CpuPcieRpPmSci[0] = 1; + params->CpuPcieRpEnableCpm[0] = 1; + params->CpuPcieClockGating[0] = 1; + params->CpuPciePowerGating[0] = 1; + params->CpuPcieRpMultiVcEnabled[0] = 1; + params->CpuPcieRpPeerToPeerMode[0] = 1; + params->CpuPcieRpMaxPayload[0] = 2; // 512B + params->CpuPcieRpAcsEnabled[0] = 1; + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; + + params->LidStatus = dasharo_ec_get_lid_state(); +} + +void mainboard_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S3) + config->s0ix_enable = 0; + else + config->s0ix_enable = 1; +} diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/board_info.txt b/src/mainboard/clevo/adl-p/variants/ns50pu/board_info.txt new file mode 100644 index 00000000000..119a5d914cf --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/board_info.txt @@ -0,0 +1,2 @@ +Board name: NS5x_NS7xPU +Release year: 2022 diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/data.vbt b/src/mainboard/clevo/adl-p/variants/ns50pu/data.vbt new file mode 100644 index 00000000000..93dc627011d Binary files /dev/null and b/src/mainboard/clevo/adl-p/variants/ns50pu/data.vbt differ diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/gpio.c b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio.c new file mode 100644 index 00000000000..ed1b050cf58 --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio.c @@ -0,0 +1,1334 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, NONE, DEEP, OFF, ACPI), + + /* GPP_B3 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, ACPI), + + /* GPP_B4 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), + + /* GPP_B5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B5, NONE, DEEP, OFF, ACPI), + + /* GPP_B6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B6, NONE, DEEP, OFF, ACPI), + + /* GPP_B7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B7, NONE, DEEP, OFF, ACPI), + + /* GPP_B8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B8, NONE, DEEP, OFF, ACPI), + + /* GPP_B9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B9, NONE, DEEP, OFF, ACPI), + + /* GPP_B10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B10, NONE, DEEP, OFF, ACPI), + + /* GPP_B11 - PMCALERT# */ + /* DW0: 0x04000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + + /* GPP_B15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), + + /* GPP_B16 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + + /* GPP_B17 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B17, 1, PLTRST), + + /* GPP_B18 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, ACPI), + + /* GPP_B19 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B19, NONE, DEEP, OFF, ACPI), + + /* GPP_B20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B20, NONE, DEEP, OFF, ACPI), + + /* GPP_B21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B21, NONE, DEEP, OFF, ACPI), + + /* GPP_B22 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B22, NONE, DEEP, OFF, ACPI), + + /* GPP_B23 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, DEEP, OFF, ACPI), + + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_T ------- */ + + /* GPP_T0 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T0, NONE), + + /* GPP_T1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T1, NONE), + + /* GPP_T2 - Reserved */ + /* DW0: 0x44000b00, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_T2, DN_20K, DEEP, NF2), + + /* GPP_T3 - Reserved */ + /* DW0: 0x44000b00, DW1: 0x00001000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_T3, DN_20K, DEEP, NF2), + + /* GPP_T4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T4, NONE), + + /* GPP_T5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T5, NONE), + + /* GPP_T6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T6, NONE), + + /* GPP_T7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T7, NONE), + + /* GPP_T8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T8, NONE), + + /* GPP_T9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T9, NONE), + + /* GPP_T10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T10, NONE), + + /* GPP_T11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T11, NONE), + + /* GPP_T12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T12, NONE), + + /* GPP_T13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T13, NONE), + + /* GPP_T14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T14, NONE), + + /* GPP_T15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + /* DW0: 0x44000702, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS0# */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_ALERT0# */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + + /* GPP_A6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A6, UP_20K, DEEP, OFF, ACPI), + + /* GPP_A7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A7, NONE, DEEP, OFF, ACPI), + + /* GPP_A8 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A8, 1, PLTRST), + + /* GPP_A9 - ESPI_CLK */ + /* DW0: 0x44000700, DW1: 0x0003d000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - ESPI_RESET# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* GPP_A11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A11, NONE, DEEP, OFF, ACPI), + + /* GPP_A12 - SATAXPCIE1 */ + /* DW0: 0x44000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + + /* GPP_A13 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, NONE, DEEP, OFF, ACPI), + + /* GPP_A15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, ACPI), + + /* GPP_A16 - USB_OC3# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPP_A17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A17, NONE, DEEP, OFF, ACPI), + + /* GPP_A18 - DDSP_HPDB */ + /* DW0: 0x44000500, DW1: 0x00024000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A19, NONE, DEEP, OFF, ACPI), + + /* GPP_A20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A20, NONE, DEEP, OFF, ACPI), + + /* GPP_A21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A21, NONE, DEEP, OFF, ACPI), + + /* GPP_A22 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_A22, NONE, DEEP, OFF, ACPI), + + /* GPP_A23 - ESPI_CS1# */ + /* DW0: 0x44000700, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), + + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S0, NONE, DEEP, OFF, ACPI), + + /* GPP_S1 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S1, NONE, DEEP, OFF, ACPI), + + /* GPP_S2 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S2, NONE, DEEP, OFF, ACPI), + + /* GPP_S3 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S3, NONE, DEEP, OFF, ACPI), + + /* GPP_S4 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S4, NONE, DEEP, OFF, ACPI), + + /* GPP_S5 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S5, NONE, DEEP, OFF, ACPI), + + /* GPP_S6 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S6, NONE, DEEP, OFF, ACPI), + + /* GPP_S7 - GPIO */ + /* DW0: 0x44000100, DW1: 0x01800000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_S7, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + + /* GPP_H1 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H1, 1, PLTRST), + + /* GPP_H2 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H2, 1, PLTRST), + + /* GPP_H3 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, ACPI), + + /* GPP_H4 - I2C0_SDA */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* GPP_H5 - I2C0_SCL */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* GPP_H6 - I2C1_SDA */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + + /* GPP_H7 - I2C1_SCL */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* GPP_H8 - CNV_MFUART2_RXD */ + /* DW0: 0x44000902, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + + /* GPP_H9 - CNV_MFUART2_TXD */ + /* DW0: 0x44000900, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + + /* GPP_H10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H10, NONE, DEEP, OFF, ACPI), */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0_RXD */ + + /* GPP_H11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_H11, NONE, DEEP, OFF, ACPI), */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0_TXD */ + + /* GPP_H12 - DEVSLP0B */ + /* DW0: 0x44001500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_H12, NONE, DEEP, NF5), + + /* GPP_H13 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H13, NONE, DEEP, OFF, ACPI), + + /* GPP_H14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H14, NONE, DEEP, OFF, ACPI), + + /* GPP_H15 - DDPB_CTRLCLK */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + + /* GPP_H16 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H16, NONE, DEEP, OFF, ACPI), + + /* GPP_H17 - DDPB_CTRLDATA */ + /* DW0: 0x44000502, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - PROC_C10_GATE# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - SRCCLKREQ4# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + + /* GPP_H20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, ACPI), + + /* GPP_H21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H21, NONE, DEEP, OFF, ACPI), + + /* GPP_H22 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_H22, NONE, DEEP, OFF, ACPI), + + /* GPP_H23 - SRCCLKREQ5# */ + /* DW0: 0x44000b02, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + + /* GPP_D1 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, DEEP, OFF, ACPI), + + /* GPP_D2 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D2, 1, PLTRST), + + /* GPP_D3 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D3, 1, PLTRST), + + /* GPP_D4 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D4, 1, PLTRST), + + /* GPP_D5 - SRCCLKREQ0# */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D6, 1, DEEP), + + /* GPP_D7 - SRCCLKREQ2# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* GPP_D8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D8, NONE, DEEP, OFF, ACPI), + + /* GPP_D9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D9, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D12 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D13 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, ACPI), + + /* GPP_D14 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D15, 1, DEEP), + + /* GPP_D16 - GPIO */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D16, 1, PLTRST), + + /* GPP_D17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D17, NONE, DEEP, OFF, ACPI), + + /* GPP_D18 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D18, NONE, DEEP, OFF, ACPI), + + /* GPP_D19 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_D19, NONE, DEEP, OFF, ACPI), + + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group RESERVED ------- */ + + /* GPP_CPU_RSVD_1 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_1, NONE), + + /* GPP_CPU_RSVD_2 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_2, NONE), + + /* GPP_CPU_RSVD_3 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_3, NONE), + + /* GPP_CPU_RSVD_4 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_4, NONE), + + /* GPP_CPU_RSVD_5 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_5, NONE), + + /* GPP_CPU_RSVD_6 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_6, NONE), + + /* GPP_CPU_RSVD_7 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_7, NONE), + + /* GPP_CPU_RSVD_8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_8, NONE), + + /* GPP_CPU_RSVD_9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_9, NONE), + + /* GPP_CPU_RSVD_10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_10, NONE), + + /* GPP_CPU_RSVD_11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_11, NONE), + + /* GPP_CPU_RSVD_12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_12, NONE), + + /* GPP_CPU_RSVD_13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_13, NONE), + + /* GPP_CPU_RSVD_14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_14, NONE), + + /* GPP_CPU_RSVD_15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_15, NONE), + + /* GPP_CPU_RSVD_16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_16, NONE), + + /* GPP_CPU_RSVD_17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_17, NONE), + + /* GPP_CPU_RSVD_18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_18, NONE), + + /* GPP_CPU_RSVD_19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_19, NONE), + + /* GPP_CPU_RSVD_20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_CPU_RSVD_20, NONE), + + /* GPP_CPU_RSVD_21 - GPP_CPU_RSVD_21 */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_CPU_RSVD_21, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_22 - GPP_CPU_RSVD_22 */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_CPU_RSVD_22, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_23 - GPP_CPU_RSVD_23 */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_CPU_RSVD_23, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_24 - GPP_CPU_RSVD_24 */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_CPU_RSVD_24, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + /* DW0: 0x40000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + + /* GPP_VGPIO_4 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO_5 - GPIO */ + /* DW0: 0x40000003, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + /* DW0: 0x04000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - GPIO */ + /* DW0: 0x04000702, DW1: 0x00003c00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_GPI_SCI(GPD2, NONE, DEEP, LEVEL, INVERT), + + /* GPD3 - PWRBTN# */ + /* DW0: 0x04000702, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + + /* GPD7 - GPIO */ + /* DW0: 0x04000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PWROK, OFF, ACPI), + + /* GPD8 - SUSCLK */ + /* DW0: 0x04000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - GPIO */ + /* DW0: 0x04000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPD9, 0, PWROK), + + /* GPD10 - SLP_S5# */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + + /* GPD11 - LANPHYPC */ + /* DW0: 0x04000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + + /* GPD_SLP_LANB - GPD_SLP_LANB */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + + /* GPD_WAKEB - GPD_WAKEB */ + /* DW0: 0x00000702, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + /* DW0: 0x00000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + /* DW0: 0x44000502, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + /* DW0: 0x44000502, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C2, 1, PLTRST), + + /* GPP_C3 - SML0CLK */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_C5, NONE, DEEP, OFF, ACPI), + + /* GPP_C6 - SML1CLK */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + + /* GPP_C7 - SML1DATA */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + + /* GPP_C8 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C14, NONE), + + /* GPP_C15 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C16, NONE), + + /* GPP_C17 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C17, NONE), + + /* GPP_C18 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C18, NONE), + + /* GPP_C19 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C19, NONE), + + /* GPP_C20 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C22, NONE), + + /* GPP_C23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - CNV_BRI_DT */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + + /* GPP_F1 - CNV_BRI_RSP */ + /* DW0: 0x44000502, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + + /* GPP_F2 - CNV_RGI_DT */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + /* DW0: 0x44000502, DW1: 0x00003000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - CNV_RF_RESET# */ + /* DW0: 0x44000500, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* GPP_F5 - CRF_XTAL_CLKREQ */ + /* DW0: 0x44000d00, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + + /* GPP_F6 - CNV_PA_BLANKING */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + + /* GPP_F7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F7, NONE, DEEP, OFF, ACPI), + + /* GPP_F8 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F8, NONE, DEEP, OFF, ACPI), + + /* GPP_F9 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F9, NONE, DEEP, OFF, ACPI), + + /* GPP_F10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F10, NONE, DEEP, OFF, ACPI), + + /* GPP_F11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), + + /* GPP_F12 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, ACPI), + + /* GPP_F13 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), + + /* GPP_F14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), + + /* GPP_F15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), + + /* GPP_F16 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), + + /* GPP_F17 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + + /* GPP_F18 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), + + /* GPP_F19 - SRCCLKREQ6# */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* GPP_F20 - GPIO */ + /* DW0: 0x84000201, DW1: 0x0003c000 */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + + /* GPP_F21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x0003c000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_F21, NONE, DEEP, OFF, ACPI), + + /* GPP_F22 - VNN_CTRL */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1), + + /* GPP_F23 - V1P05_CTRL */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* GPP_F_CLK_LOOPBK - GPIO */ + /* DW0: 0x40000300, DW1: 0x00000000 */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), + + /* GPP_L_BKLTCTL - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), + + /* GPP_L_VDDEN - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), + + /* GPP_SYS_PWROK - n/a */ + /* DW0: 0x40000702, DW1: 0x0003c000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + + /* GPP_SYS_RESETB - n/a */ + /* DW0: 0x40000702, DW1: 0x0003c000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + + /* GPP_MLK_RSTB - n/a */ + /* DW0: 0x40000700, DW1: 0x00000000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, DEEP, OFF, ACPI), + + /* GPP_E1 - GPIO */ + /* DW0: 0x40100102, DW1: 0x00003000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_APIC(GPP_E1, UP_20K, DEEP, LEVEL, NONE), + + /* GPP_E2 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E2, NONE, DEEP, OFF, ACPI), + + /* GPP_E3 - GPIO */ + /* DW0: 0x84000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E3, 1, PLTRST), + + /* GPP_E4 - GPIO */ + /* DW0: 0x84000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + + /* GPP_E5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E5, NONE, DEEP, OFF, ACPI), + + /* GPP_E6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, ACPI), + + /* GPP_E7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), + + /* GPP_E8 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E8, NONE, DEEP, OFF, ACPI), + + /* GPP_E9 - USB_OC0# */ + /* DW0: 0x44000502, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1) - IGNORED */ + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), + + + /* GPP_E10 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, ACPI), + + + /* GPP_E11 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), + + /* GPP_E12 - GPIO INT */ + /* DW0: 0x40100102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), + + /* GPP_E13 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, DEEP, OFF, ACPI), + + /* GPP_E14 - DDSP_HPDA */ + /* DW0: 0x44000700, DW1: 0x00024000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E15, NONE, DEEP, OFF, ACPI), + + /* GPP_E16 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E16, NONE, DEEP, OFF, ACPI), + + /* GPP_E17 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), + + /* GPP_E18 - TBT_LSX0_TXD */ + /* DW0: 0x44000300, DW1: 0x00003c00 */ + //PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + + /* GPP_E19 - TBT_LSX0_RXD */ + /* DW0: 0x44000300, DW1: 0x00003c00 */ + //PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + + /* GPP_E20 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E20, NATIVE, DEEP, OFF, ACPI), + + /* GPP_E21 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00003c00 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E21, NATIVE, DEEP, OFF, ACPI), + + /* GPP_E22 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00001000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E22, DN_20K, DEEP, OFF, ACPI), + + /* GPP_E23 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_E23, NONE, DEEP, OFF, ACPI), + + /* GPP_E_CLK_LOOPBK - GPIO */ + /* DW0: 0x40000300, DW1: 0x00000000 */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + + /* GPP_R1 - HDA_SYNC */ + /* DW0: 0x44000500, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + + /* GPP_R2 - HDA_SDO */ + /* DW0: 0x44000500, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - HDA_SDI0 */ + /* DW0: 0x44000500, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + + /* GPP_R4 - HDA_RST# */ + /* DW0: 0x44000500, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* GPP_R5 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, DEEP, OFF, ACPI), + + /* GPP_R6 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, DEEP, OFF, ACPI), + + /* GPP_R7 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, DEEP, OFF, ACPI), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/gpio_early.c b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio_early.c new file mode 100644 index 00000000000..616d17da2b8 --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/gpio_early.c @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), // UART0_RX + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), // UART0_TX +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/hda_verb.c b/src/mainboard/clevo/adl-p/variants/ns50pu/hda_verb.c new file mode 100644 index 00000000000..4abb6736026 --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/hda_verb.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x15587717, /* Subsystem ID */ + 18, /* Number of entries */ + 0x0205001a, + 0x02048003, + 0x0205001a, + 0x0204c003, + AZALIA_SUBVENDOR(0, 0x15587717), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), + 0x02050038, + 0x02047901, + 0x02050007, + 0x02040202, + 0x02050008, + 0x02046a0e, + 0x0205001b, + 0x02040a4b, + 0x0205003c, + 0x02040354, + 0x0205003c, + 0x02040314, + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409a2, + 0x02050036, + 0x02045050, + 0x02050036, + 0x02045050, + + /* Intel Alderlake-P HDMI */ + 0x8086281c, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 7, /* Number of entries */ + 0x20278111, + 0x20278111, + 0x20278111, + 0x20278111, + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x20278100, + 0x20278100, + 0x20278100, + 0x20278100 +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/overridetree.cb b/src/mainboard/clevo/adl-p/variants/ns50pu/overridetree.cb new file mode 100644 index 00000000000..f475d67aa8f --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/overridetree.cb @@ -0,0 +1,200 @@ +chip soc/intel/alderlake + # Default values at boot, to be adjusted by EC at runtime according + # to available wall brick capabilities. + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ + .tdp_pl1_override = 20, + .tdp_pl2_override = 56, + .tdp_psyspl2 = 90, + .tdp_psyspl3 = 92, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + device domain 0 on + subsystemid 0x1558 0x7716 inherit + + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD2) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST# + register "srcclk_pin" = "0" # SSD2_CLKREQ# + device generic 0 on end + end + end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Motherboard + register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Multi Board + register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 (USB 3.2 Gen 2) + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 (Thunderbolt) + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A Motherboard + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_TYPEC1 CH2 + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 UJ_USB1"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1 CH0"" + register "type" = "UPC_TYPE_A" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1 CH1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port3 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref pcie_rp5 on + # PCIe RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end + device ref pcie_rp6 on + # PCIe RP#6 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, + }" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F17)" # GPIO_SDCARD_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D2)" # GPP_D2_SDCARD_RST# + register "srcclk_pin" = "5" # CARD_CLKREQ5# + device generic 0 on end + end + end + device ref pcie_rp8 on + # PCIe RP#8 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_BUILT_IN, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D3)" # LAN_PLT_RST# + register "srcclk_pin" = "6" # GLAN_CLKREQ6# + device generic 0 on end + end + end + device ref pcie_rp9 on + # PCIe RP#9 x4, Clock 4 (SSD1) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 4, + .clk_req = 4, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D16)" # SSD1_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B16)" # M2_SSD1_RST# + register "srcclk_pin" = "4" # SSD1_CLKREQ# + device generic 0 on end + end + end + device ref sata on + register "sata_salp_support" = "1" + register "sata_ports_enable[1]" = "1" # SSD1 + register "sata_ports_dev_slp[1]" = "1" # GPP_H12 (SATA1_DEVSLP1) + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC2 + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + end +end diff --git a/src/mainboard/clevo/adl-p/variants/ns50pu/romstage.c b/src/mainboard/clevo/adl-p/variants/ns50pu/romstage.c new file mode 100644 index 00000000000..8f714f1b81f --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/ns50pu/romstage.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + .rcomp = { .resistor = 100, }, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + mupd->FspmConfig.PchHdaSdiEnable[0] = 1; + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.DmiAspm = 2; // ASPM L1 + mupd->FspmConfig.DmiAspmCtrl = 2; // ASPM L1 + mupd->FspmConfig.GpioOverride = 0; + + mupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 1; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/board_info.txt b/src/mainboard/clevo/adl-p/variants/nv40pz/board_info.txt new file mode 100644 index 00000000000..6eb5949ebde --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/board_info.txt @@ -0,0 +1,2 @@ +Board name: NV4xPZ +Release year: 2022 diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/data.vbt b/src/mainboard/clevo/adl-p/variants/nv40pz/data.vbt new file mode 100644 index 00000000000..d58825f3265 Binary files /dev/null and b/src/mainboard/clevo/adl-p/variants/nv40pz/data.vbt differ diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/gpio.c b/src/mainboard/clevo/adl-p/variants/nv40pz/gpio.c new file mode 100644 index 00000000000..d88cc33f601 --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/gpio.c @@ -0,0 +1,881 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - GPIO */ + PAD_CFG_GPO(GPP_B2, 0, DEEP), + + /* GPP_B3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B3, NONE, DEEP, OFF, ACPI), + + /* GPP_B4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B4, NONE, DEEP, OFF, ACPI), + + /* GPP_B5 - I2C2_SDA */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF2), + + /* GPP_B6 - I2C2_SCL */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF2), + + /* GPP_B7 - GPIO */ + PAD_CFG_GPO(GPP_B7, 0, DEEP), + + /* GPP_B8 - GPIO */ + PAD_NC(GPP_B8, NONE), + + /* GPP_B9 - GPIO */ + PAD_CFG_GPO(GPP_B9, 0, DEEP), + + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + + /* GPP_B15 - GPIO */ + PAD_CFG_GPO(GPP_B15, 0, DEEP), + + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), + + /* GPP_B17 - GPIO */ + PAD_NC(GPP_B17, NONE), + + /* GPP_B18 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B18, NONE, DEEP, OFF, ACPI), + + /* GPP_B19 - GPIO */ + PAD_CFG_GPO(GPP_B19, 0, DEEP), + + /* GPP_B20 - GPIO */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), + + /* GPP_B21 - GPIO */ + PAD_CFG_GPO(GPP_B21, 0, DEEP), + + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + + /* GPP_B23 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B23, NONE, DEEP, OFF, ACPI), + + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_T ------- */ + + /* GPP_T0 - GPIO */ + PAD_NC(GPP_T0, NONE), + + /* GPP_T1 - GPIO */ + PAD_NC(GPP_T1, NONE), + + /* GPP_T2 - GPIO */ + PAD_CFG_GPO(GPP_T2, 0, DEEP), + + /* GPP_T3 - GPIO */ + PAD_NC(GPP_T3, NONE), + + /* GPP_T4 - GPIO */ + PAD_NC(GPP_T4, NONE), + + /* GPP_T5 - GPIO */ + PAD_NC(GPP_T5, NONE), + + /* GPP_T6 - GPIO */ + PAD_NC(GPP_T6, NONE), + + /* GPP_T7 - GPIO */ + PAD_NC(GPP_T7, NONE), + + /* GPP_T8 - GPIO */ + PAD_NC(GPP_T8, NONE), + + /* GPP_T9 - GPIO */ + PAD_NC(GPP_T9, NONE), + + /* GPP_T10 - GPIO */ + PAD_NC(GPP_T10, NONE), + + /* GPP_T11 - GPIO */ + PAD_NC(GPP_T11, NONE), + + /* GPP_T12 - GPIO */ + PAD_NC(GPP_T12, NONE), + + /* GPP_T13 - GPIO */ + PAD_NC(GPP_T13, NONE), + + /* GPP_T14 - GPIO */ + PAD_NC(GPP_T14, NONE), + + /* GPP_T15 - GPIO */ + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + + /* GPP_A6 - GPIO */ + PAD_CFG_GPO(GPP_A6, 0, DEEP), + + /* GPP_A7 - GPIO */ + PAD_CFG_GPO(GPP_A7, 0, DEEP), + + /* GPP_A8 - GPIO */ + PAD_NC(GPP_A8, NONE), + + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + + /* GPP_A12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), + + /* GPP_A13 - GPIO */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - GPIO */ + PAD_CFG_GPO(GPP_A14, 1, DEEP), + + /* GPP_A15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A15, NONE, DEEP, OFF, ACPI), + + /* GPP_A16 - USB_OC3# */ + PAD_NC(GPP_A16, NONE), + + /* GPP_A17 - GPIO */ + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), + + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_A19, NONE, DEEP, OFF, ACPI), + + /* GPP_A20 - GPIO */ + PAD_NC(GPP_A20, NONE), + + /* GPP_A21 - GPIO */ + PAD_NC(GPP_A21, NONE), + + /* GPP_A22 - GPIO */ + PAD_CFG_GPO(GPP_A22, 1, PLTRST), + + /* GPP_A23 - GPIO */ + PAD_NC(GPP_A23, NONE), + + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_CFG_GPO(GPP_S0, 0, DEEP), + + /* GPP_S1 - GPIO */ + PAD_CFG_GPO(GPP_S1, 0, DEEP), + + /* GPP_S2 - GPIO */ + PAD_CFG_GPO(GPP_S2, 0, DEEP), + + /* GPP_S3 - GPIO */ + PAD_CFG_GPO(GPP_S3, 0, DEEP), + + /* GPP_S4 - GPIO */ + PAD_CFG_GPO(GPP_S4, 0, DEEP), + + /* GPP_S5 - GPIO */ + PAD_CFG_GPO(GPP_S5, 0, DEEP), + + /* GPP_S6 - GPIO */ + PAD_CFG_GPO(GPP_S6, 0, DEEP), + + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + + /* GPP_H1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H1, NONE, DEEP, OFF, ACPI), + + /* GPP_H2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H2, NONE, DEEP, OFF, ACPI), + + /* GPP_H3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, NONE, DEEP, OFF, ACPI), + + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* GPP_H6 - I2C1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + + /* GPP_H7 - I2C1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + + /* GPP_H8 - CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF2), + + /* GPP_H9 - CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF2), + + /* GPP_H10 - UART0_RXD */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + + /* GPP_H11 - UART0_TXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + + /* GPP_H12 - GPIO */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + + /* GPP_H16 - GPIO */ + PAD_NC(GPP_H16, NONE), + + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - GPIO */ + PAD_NC(GPP_H19, NONE), + + /* GPP_H20 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H20, NONE, DEEP, OFF, ACPI), + + /* GPP_H21 - GPIO */ + PAD_CFG_GPO(GPP_H21, 0, DEEP), + + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + + /* GPP_H23 - SRCCLKREQ5# */ + PAD_CFG_NF(GPP_H23, NONE, DEEP, NF2), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + + /* GPP_D1 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D1, NONE, DEEP, OFF, ACPI), + + /* GPP_D2 - GPIO */ + PAD_CFG_GPO(GPP_D2, 1, DEEP), + + /* GPP_D3 - GPIO */ + PAD_CFG_GPO(GPP_D3, 0, DEEP), + + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - GPIO */ + PAD_NC(GPP_D6, NONE), + + /* GPP_D7 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* GPP_D8 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D9, NONE), + + /* GPP_D10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D10, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D11 - GPIO */ + PAD_NC(GPP_D11, NONE), + + /* GPP_D12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, NATIVE, DEEP, OFF, ACPI), + + /* GPP_D13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D13, NONE, DEEP, OFF, ACPI), + + /* GPP_D14 - GPIO */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + + /* GPP_D17 - GPIO */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group RESERVED ------- */ + + /* GPP_CPU_RSVD_1 - GPIO */ + PAD_NC(GPP_CPU_RSVD_1, NONE), + + /* GPP_CPU_RSVD_2 - GPIO */ + PAD_NC(GPP_CPU_RSVD_2, NONE), + + /* GPP_CPU_RSVD_3 - GPIO */ + PAD_NC(GPP_CPU_RSVD_3, NONE), + + /* GPP_CPU_RSVD_4 - GPIO */ + PAD_NC(GPP_CPU_RSVD_4, NONE), + + /* GPP_CPU_RSVD_5 - GPIO */ + PAD_NC(GPP_CPU_RSVD_5, NONE), + + /* GPP_CPU_RSVD_6 - GPIO */ + PAD_NC(GPP_CPU_RSVD_6, NONE), + + /* GPP_CPU_RSVD_7 - GPIO */ + PAD_NC(GPP_CPU_RSVD_7, NONE), + + /* GPP_CPU_RSVD_8 - GPIO */ + PAD_NC(GPP_CPU_RSVD_8, NONE), + + /* GPP_CPU_RSVD_9 - GPIO */ + PAD_NC(GPP_CPU_RSVD_9, NONE), + + /* GPP_CPU_RSVD_10 - GPIO */ + PAD_NC(GPP_CPU_RSVD_10, NONE), + + /* GPP_CPU_RSVD_11 - GPIO */ + PAD_NC(GPP_CPU_RSVD_11, NONE), + + /* GPP_CPU_RSVD_12 - GPIO */ + PAD_NC(GPP_CPU_RSVD_12, NONE), + + /* GPP_CPU_RSVD_13 - GPIO */ + PAD_NC(GPP_CPU_RSVD_13, NONE), + + /* GPP_CPU_RSVD_14 - GPIO */ + PAD_NC(GPP_CPU_RSVD_14, NONE), + + /* GPP_CPU_RSVD_15 - GPIO */ + PAD_NC(GPP_CPU_RSVD_15, NONE), + + /* GPP_CPU_RSVD_16 - GPIO */ + PAD_NC(GPP_CPU_RSVD_16, NONE), + + /* GPP_CPU_RSVD_17 - GPIO */ + PAD_NC(GPP_CPU_RSVD_17, NONE), + + /* GPP_CPU_RSVD_18 - GPIO */ + PAD_NC(GPP_CPU_RSVD_18, NONE), + + /* GPP_CPU_RSVD_19 - GPIO */ + PAD_NC(GPP_CPU_RSVD_19, NONE), + + /* GPP_CPU_RSVD_20 - GPIO */ + PAD_NC(GPP_CPU_RSVD_20, NONE), + + /* GPP_CPU_RSVD_21 - GPP_CPU_RSVD_21 */ + PAD_CFG_NF(GPP_CPU_RSVD_21, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_22 - GPP_CPU_RSVD_22 */ + PAD_CFG_NF(GPP_CPU_RSVD_22, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_23 - GPP_CPU_RSVD_23 */ + PAD_CFG_NF(GPP_CPU_RSVD_23, NONE, DEEP, NF1), + + /* GPP_CPU_RSVD_24 - GPP_CPU_RSVD_24 */ + PAD_CFG_NF(GPP_CPU_RSVD_24, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD2, NATIVE, PWROK, OFF, ACPI), + + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + + /* GPD7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD7, NONE, PWROK, OFF, ACPI), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + + /* GPD11 - LANPHYPC */ + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), + + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Group PCIe vGPIO ------- */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C2, NONE, DEEP, OFF, ACPI), + + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + PAD_CFG_GPO(GPP_C5, 1, PLTRST), + + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + PAD_NC(GPP_C14, NONE), + + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - GPIO */ + PAD_NC(GPP_C16, NONE), + + /* GPP_C17 - GPIO */ + PAD_NC(GPP_C17, NONE), + + /* GPP_C18 - GPIO */ + PAD_NC(GPP_C18, NONE), + + /* GPP_C19 - GPIO */ + PAD_NC(GPP_C19, NONE), + + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + PAD_NC(GPP_C22, NONE), + + /* GPP_C23 - GPIO */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + /* GPP_F1 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + /* GPP_F2 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* GPP_F5 - CRF_XTAL_CLKREQ */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), + + /* GPP_F6 - CNV_PA_BLANKING */ + PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), + + /* GPP_F7 - GPIO */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 1, PLTRST), + + /* GPP_F11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), + + /* GPP_F12 - GPIO */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + + /* GPP_F13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, PLTRST, OFF, ACPI), + + /* GPP_F14 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), + + /* GPP_F15 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), + + /* GPP_F16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), + + /* GPP_F17 - GPIO */ + PAD_CFG_GPO(GPP_F17, 1, PLTRST), + + /* GPP_F18 - GPIO */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), + + /* GPP_F19 - SRCCLKREQ6# */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + + /* GPP_F20 - GPIO */ + PAD_CFG_GPO(GPP_F20, 1, PLTRST), + + /* GPP_F21 - GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + + /* GPP_F22 - GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), + + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + + /* GPP_F_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), + + /* GPP_L_BKLTCTL - n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), + + /* GPP_L_VDDEN - n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), + + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E0, NONE, DEEP, OFF, ACPI), + + /* GPP_E1 - GPIO */ + PAD_CFG_GPI_APIC(GPP_E1, UP_20K, DEEP, LEVEL, NONE), + + /* GPP_E2 - GPIO */ + PAD_NC(GPP_E2, NONE), + + /* GPP_E3 - GPIO */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + + /* GPP_E4 - GPIO */ + PAD_CFG_GPO(GPP_E4, 0, PLTRST), + + /* GPP_E5 - GPIO */ + PAD_NC(GPP_E5, NONE), + + /* GPP_E6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E6, NONE, DEEP, OFF, ACPI), + + /* GPP_E7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E7, NONE, DEEP, OFF, ACPI), + + /* GPP_E8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E8, NONE, DEEP, OFF, ACPI), + + /* GPP_E9 - USB_OC0# */ + PAD_NC(GPP_E9, NONE), + + /* GPP_E10 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E10, NONE, DEEP, OFF, ACPI), + + /* GPP_E11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), + + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E13, NONE, DEEP, OFF, ACPI), + + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), + + /* GPP_E16 - GPIO */ + PAD_NC(GPP_E16, NONE), + + /* GPP_E17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), + + /* GPP_E18 - TBT_LSX0_TXD */ + //PAD_NC(GPP_E18, NATIVE), + + /* GPP_E19 - TBT_LSX0_RXD */ + //PAD_NC(GPP_E19, NATIVE), + + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NONE), + + /* GPP_E21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E21, NATIVE, DEEP, OFF, ACPI), + + /* GPP_E22 - GPIO */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), + + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* GPP_R5 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R5, NONE, DEEP, OFF, ACPI), + + /* GPP_R6 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R6, NONE, DEEP, OFF, ACPI), + + /* GPP_R7 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_R7, NONE, DEEP, OFF, ACPI), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/gpio_early.c b/src/mainboard/clevo/adl-p/variants/nv40pz/gpio_early.c new file mode 100644 index 00000000000..8503bb7925d --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/gpio_early.c @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN + PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_PCH + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), // UART0_RXD + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), // UART0_TXD +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/hda_verb.c b/src/mainboard/clevo/adl-p/variants/nv40pz/hda_verb.c new file mode 100644 index 00000000000..614576f06cb --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/hda_verb.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC256 */ + 0x10ec0256, /* Vendor ID */ + 0x15584041, /* Subsystem ID */ + 18, /* Number of entries */ + 0x0205001a, + 0x02048003, + 0x0205001a, + 0x0204c003, + AZALIA_SUBVENDOR(0, 0x15584041), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41700001), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x02211020), + 0x02050038, + 0x02047901, + 0x02050007, + 0x02040202, + 0x02050008, + 0x02046a0e, + 0x0205001b, + 0x02040a4b, + 0x0205003c, + 0x02040354, + 0x0205003c, + 0x02040314, + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409a2, + 0x02050036, + 0x02045050, + 0x02050036, + 0x02045050, + + /* Intel Alderlake-P HDMI */ + 0x8086281c, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 7, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + 0x20278111, + 0x20278111, + 0x20278111, + 0x20278111, + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x20278100, + 0x20278100, + 0x20278100, + 0x20278100 +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/overridetree.cb b/src/mainboard/clevo/adl-p/variants/nv40pz/overridetree.cb new file mode 100644 index 00000000000..12cb8561f7e --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/overridetree.cb @@ -0,0 +1,201 @@ +chip soc/intel/alderlake + # Default values at boot, to be adjusted by EC at runtime according + # to available wall brick capabilities. + register "power_limits_config[ADL_P_282_442_482_28W_CORE]" = "{ + .tdp_pl1_override = 28, + .tdp_pl2_override = 60, + .tdp_psyspl2 = 90, + .tdp_psyspl3 = 92, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + # GPE configuration + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + device domain 0 on + subsystemid 0x1558 0x4041 inherit + + device ref pcie4_0 on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_src = 0, + .clk_req = 0, + .flags = PCIE_RP_LTR, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD1_RST# + register "srcclk_pin" = "0" # SSD1_CLKREQ# + device generic 0 on end + end + end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + device ref xhci on + # USB2 + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_2 + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC1 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB3_1 + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # J_TYPEC2 + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth + # USB3 + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-C + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_2"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC1"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 J_TYPEC2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_2"" + register "type" = "UPC_TYPE_A" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_USB3_1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 J_TYPEC1"" + register "type" = "UPC_TYPE_A" + device ref usb3_port4 on end + end + end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref pcie_rp5 on + # PCIe RP#5 x1, Clock 2 (WLAN) + register "pch_pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end + device ref pcie_rp9 on + # PCIe RP#9 x1, Clock 5 (CARD) + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_BUILT_IN, + }" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F17)" # GPIO_CARD_PWR + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F10)" # GPP_D2_SDCARD_RST# + register "srcclk_pin" = "5" # CARD_CLKREQ5# + device generic 0 on end + end + end + device ref pcie_rp10 on + # PCIe RP#10 x1, Clock 6 (GLAN) + register "pch_pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_BUILT_IN, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A22)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F7)" # LAN_PLT_RST# + register "srcclk_pin" = "6" # LAN_CLKREQ# + device generic 0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # J_TYPEC2 + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + end +end diff --git a/src/mainboard/clevo/adl-p/variants/nv40pz/romstage.c b/src/mainboard/clevo/adl-p/variants/nv40pz/romstage.c new file mode 100644 index 00000000000..3d6a5fb993a --- /dev/null +++ b/src/mainboard/clevo/adl-p/variants/nv40pz/romstage.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; + mupd->FspmConfig.DmiMaxLinkSpeed = 4; + mupd->FspmConfig.GpioOverride = 0; + + memcfg_init(mupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/clevo/adl-p/vboot-rwa.fmd b/src/mainboard/clevo/adl-p/vboot-rwa.fmd new file mode 100644 index 00000000000..93cd54a8b78 --- /dev/null +++ b/src/mainboard/clevo/adl-p/vboot-rwa.fmd @@ -0,0 +1,41 @@ +FLASH 32M { + SI_ALL 5M { + SI_DESC 4K + SI_ME + } + + UNUSED 11M + + RW_MISC 424K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_SHARED 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_NVRAM(PRESERVE) 24K + } + + CONSOLE 128K + BOOTSPLASH(CBFS) 1M + + RW_SECTION_A { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + + WP_RO 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } +} diff --git a/src/mainboard/clevo/cml-u/Kconfig b/src/mainboard/clevo/cml-u/Kconfig index 5961b68cb47..15d4fc7d1d4 100644 --- a/src/mainboard/clevo/cml-u/Kconfig +++ b/src/mainboard/clevo/cml-u/Kconfig @@ -22,7 +22,7 @@ config BOARD_CLEVO_CMLU_COMMON config BOARD_CLEVO_L140CU_BASE bool select BOARD_CLEVO_CMLU_COMMON - select EC_CLEVO_IT5570E + select EC_DASHARO_EC select HAVE_SPD_IN_CBFS config BOARD_CLEVO_L140CU @@ -77,7 +77,7 @@ config SEABIOS_PS2_TIMEOUT depends on PAYLOAD_SEABIOS default 500 -config EC_CLEVO_IT5570E_MEM_BASE - default 0xfe700000 +config EC_DASHARO_EC_BAT_THRESHOLDS + default n if BOARD_CLEVO_L140CU_BASE endif diff --git a/src/mainboard/clevo/cml-u/Makefile.mk b/src/mainboard/clevo/cml-u/Makefile.mk index babadf538a3..6404f801342 100644 --- a/src/mainboard/clevo/cml-u/Makefile.mk +++ b/src/mainboard/clevo/cml-u/Makefile.mk @@ -1,7 +1,6 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/acpi bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c @@ -12,9 +11,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c ramstage-y += ramstage.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c -ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads -smm-$(CONFIG_EC_CLEVO_IT5570E) += smihandler.c - subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/cml-u/acpi/gpe.asl b/src/mainboard/clevo/cml-u/acpi/gpe.asl new file mode 100644 index 00000000000..c1bc04dc9a3 --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/gpe.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +// GPP_D9 SCI +Method (_L29, 0, Serialized) { + Debug = Concatenate("GPE _L29: ", ToHexString(\_SB.PCI0.LPCB.EC0.WFNO)) + If (\_SB.PCI0.LPCB.EC0.ECOK) { + If (\_SB.PCI0.LPCB.EC0.WFNO == One) { + Notify(\_SB.LID0, 0x80) + } + } +} diff --git a/src/mainboard/clevo/cml-u/acpi/mainboard.asl b/src/mainboard/clevo/cml-u/acpi/mainboard.asl new file mode 100644 index 00000000000..ba84732f35f --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x50 /* GPP_E16 */ +#define EC_GPE_SWI 0x29 /* GPP_D9 */ +#include + +Scope (\_SB) { + #include "sleep.asl" +} + +Scope (\_GPE) { + #include "gpe.asl" +} diff --git a/src/mainboard/clevo/cml-u/acpi/sleep.asl b/src/mainboard/clevo/cml-u/acpi/sleep.asl new file mode 100644 index 00000000000..48c50e075e3 --- /dev/null +++ b/src/mainboard/clevo/cml-u/acpi/sleep.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Method called from _PTS prior to enter sleep state */ +Method (MPTS, 1) { + \_SB.PCI0.LPCB.EC0.PTS (Arg0) +} + +/* Method called from _WAK prior to wakeup */ +Method (MWAK, 1) { + \_SB.PCI0.LPCB.EC0.WAK (Arg0) +} diff --git a/src/mainboard/clevo/cml-u/bootblock.c b/src/mainboard/clevo/cml-u/bootblock.c index ee6c0b31ce6..b351fbd8ef6 100644 --- a/src/mainboard/clevo/cml-u/bootblock.c +++ b/src/mainboard/clevo/cml-u/bootblock.c @@ -1,21 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include void bootblock_mainboard_early_init(void) { variant_configure_early_gpios(); - - /* Open LGMR window for EC */ - if (CONFIG(EC_CLEVO_IT5570E)) - lpc_open_mmio_window(CONFIG_EC_CLEVO_IT5570E_MEM_BASE, 64 * KiB); -} - -void bootblock_mainboard_init(void) -{ - if (CONFIG(EC_CLEVO_IT5570E)) - ec_configure_kbled_booteffect(); } diff --git a/src/mainboard/clevo/cml-u/cmos.default b/src/mainboard/clevo/cml-u/cmos.default index aaf4c6ea4a4..79961f43d82 100644 --- a/src/mainboard/clevo/cml-u/cmos.default +++ b/src/mainboard/clevo/cml-u/cmos.default @@ -2,16 +2,4 @@ boot_option=Fallback debug_level=Debug -hyper_threading=Enable power_on_after_fail=Disable - -# EC options -ac_fan_always_on=Disable -camera_boot_state=Keep -fn_win_swap=Disable -tp_toggle_mode=CtrlAltF9 -flexicharger_on=Disable -flexicharger_start=95 -flexicharger_stop=100 -kbled_booteffect=Disable -kbled_timeout=15 diff --git a/src/mainboard/clevo/cml-u/cmos.layout b/src/mainboard/clevo/cml-u/cmos.layout index 8350704ff06..b527f81b083 100644 --- a/src/mainboard/clevo/cml-u/cmos.layout +++ b/src/mainboard/clevo/cml-u/cmos.layout @@ -17,26 +17,12 @@ entries # ----------------------------------------------------------------- # coreboot config options: cpu -400 1 e 1 hyper_threading +400 1 e 2 hyper_threading # ----------------------------------------------------------------- # coreboot config options: southbridge 410 2 e 7 power_on_after_fail -# ----------------------------------------------------------------- -# EC options -500 1 e 1 ac_fan_always_on -502 2 e 7 camera_boot_state -504 1 e 1 fn_win_swap -505 1 e 8 tp_toggle_mode - -519 1 e 1 flexicharger_on -520 8 h 0 flexicharger_start -528 8 h 0 flexicharger_stop - -543 1 e 1 kbled_booteffect -544 16 h 0 kbled_timeout - # ----------------------------------------------------------------- # vboot nv area 800 128 r 0 vbnv @@ -52,6 +38,8 @@ enumerations #ID value text 1 0 Disable 1 1 Enable +2 0 Enable +2 1 Disable 4 0 Fallback 4 1 Normal 6 0 Emergency @@ -66,8 +54,6 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep -8 0 CtrlAltF9 -8 1 KeycodeF7F8 # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/clevo/cml-u/dsdt.asl b/src/mainboard/clevo/cml-u/dsdt.asl index 71556dbf10e..203f39e702f 100644 --- a/src/mainboard/clevo/cml-u/dsdt.asl +++ b/src/mainboard/clevo/cml-u/dsdt.asl @@ -29,8 +29,5 @@ DefinitionBlock( #include } -#if CONFIG(EC_CLEVO_IT5570E) - #include - #include -#endif + #include "acpi/mainboard.asl" } diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.mk b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.mk index 7f547fb03a5..617592897e0 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.mk +++ b/src/mainboard/clevo/cml-u/variants/l140cu/Makefile.mk @@ -1,3 +1,3 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = samsung-K4AAG165WA-BCTD diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb index 2fa7a30b1f8..1a4ef105326 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb +++ b/src/mainboard/clevo/cml-u/variants/l140cu/devicetree.cb @@ -1,5 +1,4 @@ chip soc/intel/cannonlake - register "s0ix_enable" = "true" register "common_soc_config" = "{ /* Touchpad */ .i2c[0] = { @@ -145,10 +144,13 @@ chip soc/intel/cannonlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" end device ref lpc_espi on - chip ec/clevo/it5570e - device generic 0 on end - register "pl2_on_battery" = "15" - end + # LPC configuration from lspci -s 1f.0 -xxx + # Address 0x88: Decode 0x68 - 0x6F (EC PM channel) + register "gen1_dec" = "0x00040069" + # Address 0x8C: Decode 0xE00 - 0xEFF (AP/EC command) + register "gen2_dec" = "0x00fc0e01" + # Address 0x90: Decode 0xF00 - 0xFFF (AP/EC debug) + register "gen3_dec" = "0x00fc0f01" chip drivers/pc80/tpm # TPM device pnp 0c31.0 on end end diff --git a/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c index 258f07698e4..fb658dddd4f 100644 --- a/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c +++ b/src/mainboard/clevo/cml-u/variants/l140cu/gpio.c @@ -233,9 +233,6 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPP_H21, NONE), PAD_NC(GPP_H22, UP_20K), PAD_NC(GPP_H23, UP_20K), - - /* ------- GPIO Group CPU ------- */ - PAD_CFG_NF(PECI_IO, DN_20K, DEEP, NF1), /* PECI */ }; void variant_configure_gpios(void) diff --git a/src/mainboard/clevo/tgl-u/Kconfig b/src/mainboard/clevo/tgl-u/Kconfig index 3ab0e9190f4..e36e3dfcba4 100644 --- a/src/mainboard/clevo/tgl-u/Kconfig +++ b/src/mainboard/clevo/tgl-u/Kconfig @@ -7,6 +7,7 @@ config BOARD_CLEVO_TGLU_COMMON select DRIVERS_INTEL_PMC select DRIVERS_INTEL_USB4_RETIMER select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME select HAVE_CMOS_DEFAULT select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT @@ -19,31 +20,73 @@ config BOARD_CLEVO_TGLU_COMMON select SOC_INTEL_TIGERLAKE select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP + select EC_DASHARO_EC + select EC_DASHARO_EC_BAT_THRESHOLDS + select EC_ACPI -config BOARD_CLEVO_L140MU +config BOARD_CLEVO_L140MU_BASE + bool select BOARD_CLEVO_TGLU_COMMON - select EC_CLEVO_IT5570E select HAVE_SPD_IN_CBFS +config BOARD_CLEVO_NV40MZ_BASE + bool + select BOARD_CLEVO_TGLU_COMMON + select EC_DASHARO_EC_DGPU + select DRIVER_NVIDIA_OPTIMUS + +config BOARD_CLEVO_NS50MU_BASE + bool + select BOARD_CLEVO_TGLU_COMMON + select DRIVERS_GENERIC_BAYHUB_LV2 + +config BOARD_CLEVO_L140MU + select BOARD_CLEVO_L140MU_BASE + +config BOARD_CLEVO_NV40MZ + select BOARD_CLEVO_NV40MZ_BASE + +config BOARD_CLEVO_NS50MU + select BOARD_CLEVO_NS50MU_BASE + if BOARD_CLEVO_TGLU_COMMON config MAINBOARD_DIR default "clevo/tgl-u" config VARIANT_DIR - default "l140mu" if BOARD_CLEVO_L140MU + default "l140mu" if BOARD_CLEVO_L140MU_BASE + default "nv40mz" if BOARD_CLEVO_NV40MZ_BASE + default "ns50mu" if BOARD_CLEVO_NS50MU_BASE config MAINBOARD_PART_NUMBER default "L140MU" if BOARD_CLEVO_L140MU + default "NV40MZ" if BOARD_CLEVO_NV40MZ + default "NS50MU" if BOARD_CLEVO_NS50MU + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "NS50_70MU" if BOARD_CLEVO_NS50MU_BASE + default "NV4XMB,ME,MZ" if BOARD_CLEVO_NV40MZ_BASE + +config MAINBOARD_SMBIOS_MANUFACTURER + default "Notebook" config MAINBOARD_VERSION - default "2.2A" if BOARD_CLEVO_L140MU + default "2.2A" if BOARD_CLEVO_L140MU_BASE + default "2.2A" if BOARD_CLEVO_NV40MZ_BASE + default "2.2A" if BOARD_CLEVO_NS50MU_BASE + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match stock firmware config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" config CBFS_SIZE - default 0xb00000 if BOARD_CLEVO_L140MU + default 0xb00000 if BOARD_CLEVO_L140MU_BASE + default 0xb00000 if BOARD_CLEVO_NV40MZ_BASE + default 0xb00000 if BOARD_CLEVO_NS50MU_BASE config CONSOLE_POST default y @@ -52,7 +95,31 @@ config UART_FOR_CONSOLE default 2 config TPM_PIRQ - default 0x77 if BOARD_CLEVO_L140MU # GPP_C9_IRQ + default 0x77 if BOARD_CLEVO_L140MU_BASE # GPP_C9_IRQ + default 0x1C if BOARD_CLEVO_NV40MZ_BASE # GPP_C14_IRQ + default 0x1C if BOARD_CLEVO_NS50MU_BASE # GPP_C14_IRQ + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config VBOOT_VBNV_OFFSET + hex + default 0x28 + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A config POST_DEVICE default n @@ -63,7 +130,14 @@ config SEABIOS_PS2_TIMEOUT config USE_PM_ACPI_TIMER default n -config EC_CLEVO_IT5570E_MEM_BASE - default 0xfe0b0000 +config VBOOT_FWID_VERSION + default "\$(CONFIG_LOCALVERSION)" + +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 20 + +endif endif diff --git a/src/mainboard/clevo/tgl-u/Kconfig.name b/src/mainboard/clevo/tgl-u/Kconfig.name index adbc401e97e..c172f742146 100644 --- a/src/mainboard/clevo/tgl-u/Kconfig.name +++ b/src/mainboard/clevo/tgl-u/Kconfig.name @@ -4,3 +4,9 @@ comment "Tiger Lake U" config BOARD_CLEVO_L140MU bool "L140MU / L141MU / L142MU" + +config BOARD_CLEVO_NV40MZ + bool "NV4xMB / NV4xME / NV4xMZ" + +config BOARD_CLEVO_NS50MU + bool "NS5xMU / NS7xMU" diff --git a/src/mainboard/clevo/tgl-u/Makefile.mk b/src/mainboard/clevo/tgl-u/Makefile.mk index ae492df4298..ffa1cb92a22 100644 --- a/src/mainboard/clevo/tgl-u/Makefile.mk +++ b/src/mainboard/clevo/tgl-u/Makefile.mk @@ -1,7 +1,6 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/acpi bootblock-y += bootblock.c bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c @@ -15,6 +14,4 @@ ramstage-y += variants/$(VARIANT_DIR)/gpio.c ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c -smm-$(CONFIG_EC_CLEVO_IT5570E) += smihandler.c - subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/clevo/tgl-u/acpi/backlight.asl b/src/mainboard/clevo/tgl-u/acpi/backlight.asl new file mode 100644 index 00000000000..01fa83ea610 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/backlight.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (GFX0) +{ + Name (BRIG, Package (23) { + 40, /* default AC */ + 40, /* default Battery */ + 0, + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/clevo/tgl-u/acpi/mainboard.asl b/src/mainboard/clevo/tgl-u/acpi/mainboard.asl new file mode 100644 index 00000000000..68e9645dade --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/mainboard.asl @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#define CPU_CRIT_TEMP 100 +#define GPU_CRIT_TEMP 105 +#include + +Scope (\_SB) { + #include "sleep.asl" + #include "touchpad.asl" + Scope (PCI0) { + #include "backlight.asl" + } +} diff --git a/src/mainboard/clevo/tgl-u/acpi/sleep.asl b/src/mainboard/clevo/tgl-u/acpi/sleep.asl new file mode 100644 index 00000000000..239c5dc2c6e --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/sleep.asl @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Method (PGPM, 1, Serialized) +{ + For (Local0 = 0, Local0 < 6, Local0++) + { + \_SB.PCI0.CGPM (Local0, Arg0) + } +} + +/* + * Method called from _PTS prior to system sleep state entry + * Enables dynamic clock gating for all 5 GPIO communities + */ +Method (MPTS, 1, Serialized) +{ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + + /* Bring system out of TC cold before enter Sx */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () +} + +/* + * Method called from _WAK prior to system sleep state wakeup + * Disables dynamic clock gating for all 5 GPIO communities + */ +Method (MWAK, 1, Serialized) +{ + PGPM (0) +} + +/* + * S0ix Entry/Exit Notifications + * Called from \_SB.PEPD._DSM + */ +Method (MS0X, 1, Serialized) +{ + If (Arg0 == 1) { + /* S0ix Entry */ + PGPM (MISCCFG_GPIO_PM_CONFIG_BITS) + } Else { + /* S0ix Exit */ + PGPM (0) + /* Bring system out of TC cold */ + \_SB.PCI0.TCON () + + /* Bring TBT group 0 and 1 out of D3 cold if it is in D3 cold */ + \_SB.PCI0.TG0N () + \_SB.PCI0.TG1N () + } +} diff --git a/src/mainboard/clevo/tgl-u/acpi/touchpad.asl b/src/mainboard/clevo/tgl-u/acpi/touchpad.asl new file mode 100644 index 00000000000..5e25e1de38d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/acpi/touchpad.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External (\_SB.PCI0.I2C0.H015, DeviceObj) +External (\_SB.PCI0.I2C0.H015._STA, IntObj) +External (\_SB.PCI0.I2C0.H038, DeviceObj) +External (\_SB.PCI0.I2C0.H038._STA, IntObj) + +Scope (PCI0.LPCB.EC0) +{ + Method (TPTG, 0, Serialized) + { + If (CondRefOf(\_SB.PCI0.I2C0.H015)) { + If (\_SB.PCI0.I2C0.H015._STA == Zero) { + \_SB.PCI0.I2C0.H015._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H015._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H015, One) + } ElseIf (CondRefOf(\_SB.PCI0.I2C0.H038)) { + If (\_SB.PCI0.I2C0.H038._STA == Zero) { + \_SB.PCI0.I2C0.H038._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H038._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H038, One) + } + } +} diff --git a/src/mainboard/clevo/tgl-u/bootblock.c b/src/mainboard/clevo/tgl-u/bootblock.c index ee6c0b31ce6..b351fbd8ef6 100644 --- a/src/mainboard/clevo/tgl-u/bootblock.c +++ b/src/mainboard/clevo/tgl-u/bootblock.c @@ -1,21 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include #include void bootblock_mainboard_early_init(void) { variant_configure_early_gpios(); - - /* Open LGMR window for EC */ - if (CONFIG(EC_CLEVO_IT5570E)) - lpc_open_mmio_window(CONFIG_EC_CLEVO_IT5570E_MEM_BASE, 64 * KiB); -} - -void bootblock_mainboard_init(void) -{ - if (CONFIG(EC_CLEVO_IT5570E)) - ec_configure_kbled_booteffect(); } diff --git a/src/mainboard/clevo/tgl-u/cmos.default b/src/mainboard/clevo/tgl-u/cmos.default index e5228b5742b..3808ffb7658 100644 --- a/src/mainboard/clevo/tgl-u/cmos.default +++ b/src/mainboard/clevo/tgl-u/cmos.default @@ -3,14 +3,5 @@ boot_option=Fallback debug_level=Debug power_on_after_fail=Disable - -# EC options -ac_fan_always_on=Disable -camera_boot_state=Keep -fn_win_swap=Disable -tp_toggle_mode=CtrlAltF9 -flexicharger_on=Disable -flexicharger_start=95 -flexicharger_stop=100 -kbled_booteffect=Disable -kbled_timeout=15 +kbl_brightness=0xff +kbl_color=0x00ffffff diff --git a/src/mainboard/clevo/tgl-u/cmos.layout b/src/mainboard/clevo/tgl-u/cmos.layout index b31964f0a9d..3863b242ff9 100644 --- a/src/mainboard/clevo/tgl-u/cmos.layout +++ b/src/mainboard/clevo/tgl-u/cmos.layout @@ -6,6 +6,8 @@ entries # start-bit length config config-ID name 0 120 r 0 reserved_memory +# coreboot config options: ramtop +304 80 h 0 ramtop # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option @@ -19,23 +21,9 @@ entries # coreboot config options: southbridge 410 2 e 7 power_on_after_fail -# ----------------------------------------------------------------- -# EC options -500 1 e 1 ac_fan_always_on -502 2 e 7 camera_boot_state -504 1 e 1 fn_win_swap -505 1 e 8 tp_toggle_mode - -519 1 e 1 flexicharger_on -520 8 h 0 flexicharger_start -528 8 h 0 flexicharger_stop - -543 1 e 1 kbled_booteffect -544 16 h 0 kbled_timeout - # ----------------------------------------------------------------- # vboot nv area -800 128 r 0 vbnv +432 128 r 0 vbnv # ----------------------------------------------------------------- # coreboot config options: check sums @@ -43,6 +31,10 @@ entries # ----------------------------------------------------------------- +# embedded controller settings +1024 8 h 0 kbl_brightness +1032 32 h 0 kbl_color + enumerations #ID value text @@ -64,10 +56,8 @@ enumerations 7 0 Disable 7 1 Enable 7 2 Keep -8 0 CtrlAltF9 -8 1 KeycodeF7F8 # ----------------------------------------------------------------- checksums -checksum 392 799 984 +checksum 392 431 984 diff --git a/src/mainboard/clevo/tgl-u/dsdt.asl b/src/mainboard/clevo/tgl-u/dsdt.asl index 10ad9df6d9b..a9a7085dd3e 100644 --- a/src/mainboard/clevo/tgl-u/dsdt.asl +++ b/src/mainboard/clevo/tgl-u/dsdt.asl @@ -20,7 +20,6 @@ DefinitionBlock( #include #include #include - #include } Scope (\_SB.PCI0.LPCB) @@ -30,8 +29,5 @@ DefinitionBlock( #include -#if CONFIG(EC_CLEVO_IT5570E) - #include - #include -#endif + #include } diff --git a/src/mainboard/clevo/tgl-u/fadt.c b/src/mainboard/clevo/tgl-u/fadt.c index 28ed7e97c33..0967bc9a95b 100644 --- a/src/mainboard/clevo/tgl-u/fadt.c +++ b/src/mainboard/clevo/tgl-u/fadt.c @@ -1,10 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include void mainboard_fill_fadt(acpi_fadt_t *fadt) { /* Control method power button (EC) */ - fadt->flags |= ACPI_FADT_POWER_BUTTON; + fadt->preferred_pm_profile = PM_MOBILE; } diff --git a/src/mainboard/clevo/tgl-u/include/variant/ramstage.h b/src/mainboard/clevo/tgl-u/include/variant/ramstage.h index 4b5b29db0a5..b519bbb24ee 100644 --- a/src/mainboard/clevo/tgl-u/include/variant/ramstage.h +++ b/src/mainboard/clevo/tgl-u/include/variant/ramstage.h @@ -4,5 +4,6 @@ #define VARIANT_RAMSTAGE_H void variant_configure_fsps(FSP_S_CONFIG *params); +void variant_init(void); #endif diff --git a/src/mainboard/clevo/tgl-u/ramstage.c b/src/mainboard/clevo/tgl-u/ramstage.c index 0768e515c93..ce2f8e4fab8 100644 --- a/src/mainboard/clevo/tgl-u/ramstage.c +++ b/src/mainboard/clevo/tgl-u/ramstage.c @@ -1,20 +1,228 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include +#include +#include +#include +#include +#include +#include #include #include #include +struct smfi_cmd_set_fan_curve { + uint8_t fan; + struct fan_curve curve; +} __packed; + +struct fan_curve fan_curve_silent = { + { .temp = 0, .duty = 20 }, + { .temp = 65, .duty = 25 }, + { .temp = 75, .duty = 35 }, + { .temp = 85, .duty = 100 } +}; + +struct fan_curve fan_curve_performance = { + { .temp = 0, .duty = 25 }, + { .temp = 55, .duty = 35 }, + { .temp = 75, .duty = 60 }, + { .temp = 85, .duty = 100} +}; + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + void mainboard_silicon_init_params(FSP_S_CONFIG *params) { variant_configure_fsps(params); + + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; + + // IOM config + params->PchUsbOverCurrentEnable = 0; + + // Acoustic / RFI optimizations + // TODO optimize + params->PreWake = 150; + params->RampUp = 150; + params->RampDown = 150; + params->RfiMitigation = 1; +} + +static void set_fan_curve(void) +{ + int i; + uint8_t selection = get_fan_curve_option(); + struct smfi_cmd_set_fan_curve cmd; + + switch (selection) { + case FAN_CURVE_OPTION_SILENT: + cmd.curve = fan_curve_silent; + break; + case FAN_CURVE_OPTION_PERFORMANCE: + cmd.curve = fan_curve_performance; + break; + default: + cmd.curve = fan_curve_silent; + break; + } + + for (i = 0; i < (CONFIG(EC_DASHARO_EC_DGPU) ? 2 : 1); ++i) { + cmd.fan = i; + dasharo_ec_smfi_cmd(CMD_FAN_CURVE_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); + } +} + +static void set_camera_enablement(void) +{ + bool enabled = get_camera_option(); + + dasharo_ec_smfi_cmd(CMD_CAMERA_ENABLEMENT_SET, sizeof(enabled) / sizeof(uint8_t), (uint8_t *)&enabled); +} + +static void set_battery_thresholds(void) +{ + struct battery_config bat_cfg; + + get_battery_config(&bat_cfg); + + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_START, bat_cfg.start_threshold); + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_STOP, bat_cfg.stop_threshold); +} + +static void set_power_on_ac(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_POWER_ON_AC, + 0 + }; + + cmd.value = dasharo_get_power_on_after_fail(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); +} + +static void set_usb_charge_port(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_ALWAYS_ON_USB, + 0 + }; + + cmd.value = dasharo_get_usb_port_power(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); } static void init_mainboard(void *chip_info) { variant_configure_gpios(); + variant_init(); + + set_fan_curve(); + set_camera_enablement(); + set_battery_thresholds(); + set_power_on_ac(); + set_usb_charge_port(); +} + +#if CONFIG(GENERATE_SMBIOS_TABLES) +static uint8_t read_proprietary_ec_version(uint8_t *data) +{ + int i, result; + char ec_version[16]; + + if (!data) + return -1; + + if (send_ec_command(0x93)) + return -1; + + for (i = 0; i < 16 - 1; i++) { + + result = recv_ec_data(); + if (result != -1) + ec_version[i] = result & 0xff; + + if (ec_version[i] == '$') { + ec_version[i] = '\0'; + break; + } + } + ec_version[15] = '\0'; + + data[0] = '1'; + data[1] = '.'; + + strcpy((char *)&data[2], ec_version); + + return 0; +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + char ec_version[256]; + uint8_t result; + + result = dasharo_ec_read_version((uint8_t *)ec_version); + + /* If the command fails it mean we are running proprietary EC most likely */ + if (result != 0) { + printk(BIOS_ERR, "Failed to read open EC firmware version\n"); + result = read_proprietary_ec_version((uint8_t *)ec_version); + if (result == 0) + t->count = smbios_add_string(t->eos, "EC: proprietary"); + else + t->count = smbios_add_string(t->eos, "EC: unknown"); + } else { + t->count = smbios_add_string(t->eos, "EC: open-source"); + } + + if (result == 0) { + printk(BIOS_DEBUG, "EC firmware version: %s\n", ec_version); + t->count = smbios_add_string(t->eos, strconcat("EC firmware version: ", + ec_version)); + } else { + printk(BIOS_ERR, "Unable to probe EC firmware version\n"); + t->count = smbios_add_string(t->eos, "EC firmware version: unknown"); + } + +} +#endif + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_strings = mainboard_smbios_strings; +#endif +} + +void mainboard_update_soc_chip_config(struct soc_intel_tigerlake_config *config) +{ + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S3) + config->s0ix_enable = 0; + else + config->s0ix_enable = 1; } struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, .init = init_mainboard, }; diff --git a/src/mainboard/clevo/tgl-u/smihandler.c b/src/mainboard/clevo/tgl-u/smihandler.c deleted file mode 100644 index e53ab452a6f..00000000000 --- a/src/mainboard/clevo/tgl-u/smihandler.c +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ - -#include -#include -#include -#include - -void mainboard_smi_sleep(u8 slp_typ) -{ - printk(BIOS_DEBUG, "Mainboard SMI sleep handler: %02x\n", slp_typ); - ec_smi_sleep(slp_typ); -} - -int mainboard_smi_apmc(u8 apmc) -{ - printk(BIOS_DEBUG, "Mainboard SMI APMC handler: %02x\n", apmc); - ec_smi_apmc(apmc); - - return 0; -} diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.mk b/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.mk index 361cbcd7bc9..1f81db75f35 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.mk +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/Makefile.mk @@ -1,3 +1,3 @@ -## SPDX-License-Identifier: GPL-2.0-only +# SPDX-License-Identifier: GPL-2.0-only SPD_SOURCES = samsung-M471A1G44AB0-CWE diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb index 0131e219482..66669b4a5ae 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/devicetree.cb @@ -138,7 +138,7 @@ chip soc/intel/tigerlake register "generic.hid" = ""ELAN040D"" register "generic.desc" = ""ELAN Touchpad"" register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" - register "generic.detect" = "1" + register "generic.probed" = "true" register "hid_desc_reg_offset" = "0x01" device i2c 15 on end end @@ -199,10 +199,6 @@ chip soc/intel/tigerlake end end device ref pch_espi on - chip ec/clevo/it5570e - device generic 0 on end - register "pl2_on_battery" = "15" - end chip drivers/pc80/tpm device pnp 0c31.0 on end end diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c index 831b5fe9b15..6919baf4188 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/gpio.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include @@ -233,7 +232,4 @@ static const struct pad_config gpio_table[] = { void variant_configure_gpios(void) { gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); - - /* PECI idle workaround */ - pcr_rmw32(0x6b, 0x744, ~PAD_CFG1_PULL_MASK, PAD_CFG1_PULL_DN_20K); } diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c index b6bf5c5b550..1785e136dde 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/hda_verb.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include const u32 cim_verb_data[] = { /* Realtek ALC293 */ diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c b/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c index 6933e9904d2..c0e286595ad 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/ramstage.c @@ -9,3 +9,5 @@ void variant_configure_fsps(FSP_S_CONFIG *params) params->CpuPcieRpLtrEnable[0] = 1; params->CpuPcieRpSlotImplemented[0] = 1; } + +void variant_init(void) {} diff --git a/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c index a1cfb03749e..14e81fe2fec 100644 --- a/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c +++ b/src/mainboard/clevo/tgl-u/variants/l140mu/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include void variant_configure_fspm(FSPM_UPD *memupd) diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/Makefile.mk b/src/mainboard/clevo/tgl-u/variants/ns50mu/Makefile.mk new file mode 100644 index 00000000000..24384073fd5 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/Makefile.mk @@ -0,0 +1,6 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +ramstage-y += gpio.c +ramstage-y += hda_verb.c diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/board_info.txt b/src/mainboard/clevo/tgl-u/variants/ns50mu/board_info.txt new file mode 100644 index 00000000000..6758d0fbb0d --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/board_info.txt @@ -0,0 +1,2 @@ +Board name: NS50_70MU +Release year: 2021 diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/data.vbt b/src/mainboard/clevo/tgl-u/variants/ns50mu/data.vbt new file mode 100644 index 00000000000..af16a2d54e6 Binary files /dev/null and b/src/mainboard/clevo/tgl-u/variants/ns50mu/data.vbt differ diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/ns50mu/devicetree.cb new file mode 100644 index 00000000000..7615396956a --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/devicetree.cb @@ -0,0 +1,317 @@ +chip soc/intel/tigerlake +# CPU (soc/intel/tigerlake/cpu.c) + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_psyspl2 = 65, + .tdp_psyspl3 = 67, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_psyspl2 = 65, + .tdp_psyspl3 = 67, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable s0ix, required for TGL-U + register "s0ix_enable" = "1" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + register "enable_c6dram" = "1" + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SLEW_FAST_8" + register "FastPkgCRampDisable" = "1" + register "tcc_offset" = "20" # TCC of 80C + +# Actual device tree + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x1558 0x51a1 inherit + + #From CPU EDS(575683) + device ref system_agent on end + device ref igpu on + # DDIA is eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + + # DDIB is HDMI + register "DdiPortBConfig" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + + # ACPI brightness control + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref peg on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcClkReq[0]" = "0" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD1"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D13)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end + device ref tbt_pcie_rp0 on end # TBT Type-C + device ref north_xhci on # TBT Type-C + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # TBT Type-C + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // USB-A daughterboard + [1] = USB2_PORT_TYPE_C(OC_SKIP), // USB-C mainboard + [2] = USB2_PORT_MID(OC_SKIP), // USB-A mainboard + [4] = USB2_PORT_MID(OC_SKIP), // Fingerprint Reader + [5] = USB2_PORT_TYPE_C(OC_SKIP), // TBT USB-C + [6] = USB2_PORT_MID(OC_SKIP), // CCD + [9] = USB2_PORT_MID(OC_SKIP), // BT + }" + register "usb3_ports" = "{ + [1] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C port2 (lane 0) + [2] = USB3_PORT_DEFAULT(OC_SKIP), // USB-A port3 + [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C port4 (lane 1) + }" + # USB2 + register "usb2_ports[0]" = "USB2_PORT_LONG(OC_SKIP)" # USB-A daughterboard + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB-C motherboard + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # USB-A motherboard + register "usb2_ports[4]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint Reader + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TBT + register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # CCD + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # BT + # USB3 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C (lane 0) + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-A + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB-C (lane 1) + # ACPI + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A"" + register "type" = "UPC_TYPE_A" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C (Lane 0)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 3)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C (Lane 1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port4 on end + end + end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""Elantech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref sata on + # SATA1 (SSD0) + register "SataPortsEnable[1]" = "1" + register "SataPortsDevSlp[1]" = "1" + register "SataPortsEnableDitoConfig[1]" = "1" + register "SataSalpSupport" = "1" + end + device ref shared_ram on end + device ref cnvi_wifi on + register "CnviBtCore" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c1 on + # USB-PD + register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref heci1 on end + device ref uart2 on + # Debug console + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref pcie_rp5 off end + device ref pcie_rp6 on + # PCIe root port #6 x1, Clock 2 (CARD) + register "PcieRpLtrEnable[5]" = "1" + register "PcieClkSrcUsage[2]" = "5" + register "PcieClkSrcClkReq[2]" = "2" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + end + device ref pcie_rp7 on + # PCIe root port #7 x1, Clock 3 (GLAN) + register "PcieRpLtrEnable[6]" = "1" + register "PcieClkSrcUsage[3]" = "6" + register "PcieClkSrcClkReq[3]" = "3" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # LAN_PLT_RST + register "srcclk_pin" = "3" # GLAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp8 on + # PCIe root port #8 x1, Clock 1 (WLAN) + register "PcieRpLtrEnable[7]" = "1" + register "PcieClkSrcUsage[1]" = "7" + register "PcieClkSrcClkReq[1]" = "1" + register "PcieRpSlotImplemented[7]" = "1" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_23" # GPP_C23 + device pci 00.0 on end + end + end + device ref pcie_rp9 on + # PCIe root port #9 x4, Clock 4 (SSD0) + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[4]" = "8" + register "PcieClkSrcClkReq[4]" = "4" + register "PcieRpSlotImplemented[8]" = "1" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD0"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" + register "srcclk_pin" = "4" # SSD0_CLKREQ# + device generic 0 on end + end + end + device ref pch_espi on + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x00040069" + register "gen3_dec" = "0x00fc0e01" + register "gen4_dec" = "0x00fc0f01" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # TBT Type-C + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio.c new file mode 100644 index 00000000000..16a1f1441cf --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio.c @@ -0,0 +1,636 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B2, UP_20K, DEEP, OFF, ACPI), + + /* GPP_B3 - GPIO */ + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), + + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - GPIO */ + PAD_CFG_GPO(GPP_B8, 1, DEEP), + + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - GPIO */ + PAD_CFG_GPO(GPP_B14, 0, DEEP), + + /* GPP_B15 - GPIO */ + PAD_CFG_GPO(GPP_B15, 1, DEEP), + + /* GPP_B16 - GPIO */ + PAD_CFG_GPO(GPP_B16, 1, PLTRST), + + /* GPP_B17 - GPIO */ + PAD_NC(GPP_B17, NONE), + + /* GPP_B18 - GPIO */ + PAD_NC(GPP_B18, NONE), + + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* ------- GPIO Group GPP_T (TGL UP3 only) ------- */ + + /* GPP_T2 - GPIO */ + PAD_NC(GPP_T2, NONE), + + /* GPP_T3 - GPIO */ + PAD_NC(GPP_T3, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_CLK */ + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + + /* GPP_A6 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + + /* GPP_A7 - GPIO */ + PAD_NC(GPP_A7, NONE), + + /* GPP_A8 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + + /* GPP_A9 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + + /* GPP_A10 - GPIO */ + PAD_NC(GPP_A10, NONE), + + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + + /* GPP_A12 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_A12, UP_20K, DEEP, NF1), + + /* GPP_A13 - GPIO */ + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + + /* GPP_A14 - GPIO */ + PAD_NC(GPP_A14, NONE), + + /* GPP_A15 - GPIO */ + PAD_NC(GPP_A15, NONE), + + /* GPP_A16 - GPIO */ + PAD_NC(GPP_A16, NONE), + + /* GPP_A17 - GPIO */ + PAD_NC(GPP_A17, NONE), + + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - GPIO */ + PAD_NC(GPP_A19, NONE), + + /* GPP_A20 - GPIO */ + PAD_NC(GPP_A20, NONE), + + /* GPP_A21 - GPIO */ + PAD_NC(GPP_A21, NONE), + + /* GPP_A22 - GPIO */ + PAD_NC(GPP_A22, NONE), + + /* GPP_A23 - GPIO */ + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + + /* GPP_H2 - GPIO */ + PAD_NC(GPP_H2, NONE), + + /* GPP_H3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H3, DN_20K, DEEP, OFF, ACPI), + + /* GPP_H4 - GPIO */ + PAD_NC(GPP_H4, NONE), + + /* GPP_H5 - GPIO */ + PAD_NC(GPP_H5, NONE), + + /* GPP_H6 - GPIO */ + PAD_NC(GPP_H6, NONE), + + /* GPP_H7 - GPIO */ + PAD_NC(GPP_H7, NONE), + + /* GPP_H8 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H8, DN_20K, DEEP, OFF, ACPI), + + /* GPP_H9 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_H9, DN_20K, DEEP, OFF, ACPI), + + /* GPP_H10 - SRCCLKREQ4# */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11, NONE), + + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12, NONE), + + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + + /* GPP_H15 - GPIO */ + PAD_NC(GPP_H15, NONE), + + /* GPP_H16 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - GPIO */ + PAD_NC(GPP_H19, NONE), + + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, DEEP, OFF, ACPI), + + /* GPP_D1 - GPIO */ + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + + /* GPP_D2 - GPIO */ + PAD_CFG_GPO(GPP_D2, 1, PLTRST), + + /* GPP_D3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + + /* GPP_D6 - SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + + /* GPP_D7 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + + /* GPP_D8 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D9, NONE), + + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NONE), + + /* GPP_D11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, DEEP, OFF, ACPI), + + /* GPP_D12 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_D12, DN_20K, DEEP, OFF, ACPI), + + /* GPP_D13 - GPIO */ + PAD_CFG_GPO(GPP_D13, 1, PLTRST), + + /* GPP_D14 - GPIO */ + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Group GPP_U (TGL UP3 only) ------- */ + + /* GPP_U4 - GPIO */ + PAD_CFG_GPO(GPP_U4, 0, PLTRST), + + /* GPP_U5 - GPIO */ + PAD_CFG_GPO(GPP_U5, 1, PLTRST), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD2, NONE, PWROK, OFF, ACPI), + + /* GPD3 - PRWBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + + /* GPD7 - GPIO */ + PAD_CFG_GPO(GPD7, 1, PWROK), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - GPIO */ + PAD_CFG_GPO(GPD9, 0, PWROK), + + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), + + /* GPD11 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPD11, UP_20K, DEEP, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + PAD_NC(GPP_C2, NONE), + + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + PAD_NC(GPP_C5, NONE), + + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + PAD_CFG_GPI_APIC_HIGH(GPP_C14, UP_20K, DEEP), + + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - I2C0_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + + /* GPP_C17 - I2C0_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + + /* GPP_C18 - I2C1_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + + /* GPP_C19 - I2C1_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + + /* GPP_C23 - GPIO */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + /* GPP_F1 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + /* GPP_F2 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - GPIO */ + PAD_NC(GPP_F4, NONE), + + /* GPP_F5 - GPIO */ + PAD_NC(GPP_F5, NONE), + + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + + /* GPP_F7 - GPIO */ + PAD_CFG_GPO(GPP_F7, 1, DEEP), + + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + + /* GPP_F10 - GPIO */ + PAD_NC(GPP_F10, NONE), + + /* GPP_F11 - GPIO */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - GPIO */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - GPIO */ + PAD_NC(GPP_F13, NONE), + + /* GPP_F14 - GPIO */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - GPIO */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - GPIO */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), + + /* GPP_F18 - GPIO */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - GPIO */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F21, DN_20K, DEEP, OFF, ACPI), + + /* GPP_F22 - GPIO */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + + /* GPP_E1 - GPIO */ + PAD_CFG_GPO(GPP_E1, 1, PLTRST), + + /* GPP_E2 - GPIO */ + PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + + /* GPP_E3 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E3, DN_20K, DEEP, OFF, ACPI), + + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E5 - DEVSLP1 */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + + /* GPP_E6 - GPIO */ + PAD_NC(GPP_E6, NONE), + + /* GPP_E7 - GPIO */ + PAD_CFG_GPI_SMI(GPP_E7, NONE, PLTRST, EDGE_SINGLE, INVERT), + + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - GPIO */ + PAD_NC(GPP_E13, NONE), + + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + PAD_NC(GPP_E15, NONE), + + /* GPP_E16 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E16, DN_20K, DEEP, OFF, ACPI), + + /* GPP_E17 - GPIO */ + PAD_NC(GPP_E17, NONE), + + /* GPP_E18 - GPIO */ + PAD_NC(GPP_E18, NATIVE), + + /* GPP_E19 - GPIO */ + PAD_NC(GPP_E19, NATIVE), + + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NONE), + + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NONE), + + /* GPP_E22 - GPIO */ + PAD_NC(GPP_E22, NONE), + + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE), +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio_early.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio_early.c new file mode 100644 index 00000000000..f92d993ff70 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/gpio_early.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Name format: / */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */ +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/hda_verb.c new file mode 100644 index 00000000000..d980767d1ef --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/hda_verb.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x155851a1, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x155851a1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40738205), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Tigerlake HDMI */ + 0x80862812, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/ramstage.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/ramstage.c new file mode 100644 index 00000000000..2e238c2cf48 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/ramstage.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +void variant_configure_fsps(FSP_S_CONFIG *params) +{ + /* + * Disable AER for the SSD slot to support S0ix with SSDs running + * buggy firmware + */ + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpSlotImplemented[0] = 1; + + /* + * VR configuration + * Only one VR domain in TGL-U (VCCIN) + * ICCMax: 55A + * DC_LL: 2mOhm + * OCP: 72A + */ + params->AcLoadline[0] = 200; + params->DcLoadline[0] = 200; + params->IccMax[0] = 220; +} + +void variant_init(void) +{ + config_t *cfg = config_of_soc(); + struct device *cnvi_dev = pcidev_on_root(0x14, 3); + struct device *wlan_dev = pcidev_on_root(0x1c, 7); + bool radio_enable = get_wireless_option(); + + printk(BIOS_DEBUG, "Wireless is %sabled\n", radio_enable ? "en" : "dis"); + + wlan_dev->enabled = radio_enable; + cnvi_dev->enabled = radio_enable; + cfg->usb2_ports[9].enable = radio_enable; + + dasharo_ec_smfi_cmd(CMD_WIFI_BT_ENABLEMENT_SET, 1, (uint8_t *)&radio_enable); +} diff --git a/src/mainboard/clevo/tgl-u/variants/ns50mu/romstage.c b/src/mainboard/clevo/tgl-u/variants/ns50mu/romstage.c new file mode 100644 index 00000000000..ffdaf81eaab --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/ns50mu/romstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + memcfg_init(memupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt b/src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt new file mode 100644 index 00000000000..61b2b0eca90 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/board_info.txt @@ -0,0 +1,2 @@ +Board name: NV4xMZ/MB/ME +Release year: 2021 diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt b/src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt new file mode 100644 index 00000000000..af16a2d54e6 Binary files /dev/null and b/src/mainboard/clevo/tgl-u/variants/nv40mz/data.vbt differ diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb b/src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb new file mode 100644 index 00000000000..b5089c9e74f --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/devicetree.cb @@ -0,0 +1,301 @@ +chip soc/intel/tigerlake +# CPU (soc/intel/tigerlake/cpu.c) + register "power_limits_config[POWER_LIMITS_U_4_CORE]" = "{ + .tdp_psyspl2 = 65, + .tdp_psyspl3 = 67, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + register "power_limits_config[POWER_LIMITS_U_2_CORE]" = "{ + .tdp_psyspl2 = 65, + .tdp_psyspl3 = 67, + .tdp_psyspl3_time = 6, + .tdp_psyspl3_dutycycle = 4, + .tdp_pl4 = 65, + }" + + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + +# ACPI (soc/intel/tigerlake/acpi.c) + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable s0ix, required for TGL-U + register "s0ix_enable" = "1" + +# FSP Memory (soc/intel/tigerlake/romstage/fsp_params.c) + register "enable_c6dram" = "1" + register "SaGv" = "SaGv_Enabled" + +# FSP Silicon (soc/intel/tigerlake/fsp_params.c) + register "AcousticNoiseMitigation" = "1" + register "SlowSlewRate" = "SLEW_FAST_8" + register "FastPkgCRampDisable" = "1" + register "tcc_offset" = "20" # TCC of 80C + +# Actual device tree + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x1558 0x4018 inherit + + #From CPU EDS(575683) + device ref system_agent on end + device ref igpu on + # DDIA is eDP + register "DdiPortAConfig" = "1" + register "DdiPortAHpd" = "1" + register "DdiPortADdc" = "0" + + # DDIB is HDMI + register "DdiPortBConfig" = "0" + register "DdiPortBHpd" = "1" + register "DdiPortBDdc" = "1" + + # ACPI brightness control + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref peg on + # PCIe PEG0 x4, Clock 0 (SSD1) + register "PcieClkSrcUsage[0]" = "0x40" + register "PcieClkSrcClkReq[0]" = "0" + + chip soc/intel/common/block/pcie/rtd3 + register "desc" = ""SSD1"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_DN# + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H0)" # GPP_H0_RTD3 + register "srcclk_pin" = "0" # SSD1_CLKREQ# + device generic 0 on end + end + end + device ref tbt_pcie_rp0 on end # TBT Type-C + device ref north_xhci on # TBT Type-C + register "UsbTcPortEn" = "1" + register "TcssXhciEn" = "1" + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tbt_dma0 on # TBT Type-C + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + use tcss_usb3_port1 as dfp[0].typec_port + device generic 0 on end + end + end + + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC_SKIP), // USB-A port1 + [1] = USB2_PORT_TYPE_C(OC_SKIP), // USB-C port2 + [2] = USB2_PORT_MID(OC_SKIP), // USB-A port3 + [4] = USB2_PORT_MID(OC_SKIP), // Fingerprint Reader + [5] = USB2_PORT_TYPE_C(OC_SKIP), // TBT USB-C + [6] = USB2_PORT_MID(OC_SKIP), // CCD + [9] = USB2_PORT_MID(OC_SKIP), // BT + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // USB-A port1 + [1] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C port2 (right port, lane 0) + [2] = USB3_PORT_DEFAULT(OC_SKIP), // USB-A port3 + [3] = USB3_PORT_DEFAULT(OC_SKIP), // USB-C port4 (right port, lane 1) + }" + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Fingerprint"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 3"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref usb3_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 4"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb3_port4 on end + end + end + end + end + device ref shared_ram on end + device ref cnvi_wifi on + register "CnviBtCore" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + device ref i2c0 on + # Touchpad I2C bus + register "SerialIoI2cMode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B3)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c1 on + # USB-PD + register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c2 on + # Pantone ROM + register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci" + end + device ref heci1 on end + device ref uart2 on + # Debug console + register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit" + end + device ref pcie_rp5 on + # PCIe root port #5 x4, Clock 2 (NVIDIA GPU) + register "PcieRpLtrEnable[4]" = "1" + register "PcieClkSrcUsage[2]" = "4" + register "PcieClkSrcClkReq[2]" = "2" + chip drivers/gfx/nvidia/optimus + register "desc" = ""DGPU"" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_U5)" # DGPU_PWR_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_U4)" # DGPU_RST#_PCH + register "enable_delay_ms" = "16" + register "enable_off_delay_ms" = "4" + register "reset_delay_ms" = "10" + register "reset_off_delay_ms" = "4" + register "srcclk_pin" = "2" # PEG_CLKREQ# + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device ref pcie_rp9 on + # PCIe root port #9 x1, Clock 3 (CARD) + register "PcieRpLtrEnable[8]" = "1" + register "PcieClkSrcUsage[3]" = "8" + register "PcieClkSrcClkReq[3]" = "3" + end + device ref pcie_rp10 on + # PCIe root port #10 x1, Clock 4 (GLAN) + register "PcieRpLtrEnable[9]" = "1" + register "PcieClkSrcUsage[4]" = "9" + register "PcieClkSrcClkReq[4]" = "4" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F9)" # GPIO_LAN_EN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C22)" # LAN_PLT_RST + register "srcclk_pin" = "4" # LAN_CLKREQ# + device generic 0 on end + end + end + device ref pcie_rp11 on + # PCIe root port #11 x1, Clock 1 (WLAN) + register "PcieRpSlotImplemented[10]" = "1" + register "PcieRpLtrEnable[10]" = "1" + register "PcieClkSrcUsage[1]" = "10" + register "PcieClkSrcClkReq[1]" = "1" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_23" # GPP_C23 + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref pch_espi on + register "gen1_dec" = "0x000c0081" + register "gen2_dec" = "0x00040069" + register "gen3_dec" = "0x00fc0e01" + register "gen4_dec" = "0x00fc0f01" + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + end + device ref p2sb on end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_C" + register "pmc_gpe0_dw1" = "PMC_GPP_E" + register "pmc_gpe0_dw2" = "PMC_GPD" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # TBT Type-C + use usb2_port6 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + subsystemid 0x1558 0x4019 + register "PchHdaAudioLinkHdaEnable" = "1" + register "PchHdaAudioLinkDmicEnable[0]" = "1" + register "PchHdaAudioLinkDmicEnable[1]" = "0" + end + device ref smbus on end + device ref fast_spi on end + end +end diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c new file mode 100644 index 00000000000..637aeb0745b --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio.c @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPI_INT(GPP_B3, NONE, PLTRST, LEVEL), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_CFG_GPO(GPP_B8, 1, DEEP), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B15, 1, DEEP), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_CFG_GPO(GPP_B23, 0, DEEP), + /* ------- GPIO Group GPP_T (TGL UP3 only) ------- */ + PAD_NC(GPP_T2, NONE), + PAD_NC(GPP_T3, NONE), + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_NC(GPP_A7, NONE), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF2), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF2), + PAD_NC(GPP_A10, NONE), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_GPO(GPP_A13, 1, PLTRST), + PAD_NC(GPP_A14, NONE), + PAD_NC(GPP_A15, NONE), + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_CFG_GPO(GPP_A23, 0, PLTRST), + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H0, 1, PLTRST), + PAD_NC(GPP_H1, NONE), + PAD_NC(GPP_H2, NONE), + PAD_NC(GPP_H3, NONE), + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + PAD_NC(GPP_H15, NONE), + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + PAD_NC(GPP_H19, NONE), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_D0, NONE, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D1, 1, PLTRST), + PAD_CFG_GPI_TRIG_OWN(GPP_D2, NONE, PLTRST, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D3, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_D4, NONE), + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D10, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D11, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D12, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPO(GPP_D13, 0, DEEP), + PAD_CFG_GPO(GPP_D14, 1, PLTRST), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D17, DN_20K, DEEP, OFF, ACPI), + PAD_CFG_GPI_TRIG_OWN(GPP_D18, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_D19, NONE), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPD ------- */ + PAD_CFG_NF(GPD0, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + PAD_CFG_NF(GPD2, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + PAD_CFG_GPO(GPD7, 1, RSMRST), + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + PAD_CFG_GPI_TRIG_OWN(GPD9, UP_20K, DEEP, OFF, ACPI), + PAD_CFG_NF(GPD10, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_OWN(GPD11, UP_20K, DEEP, OFF, ACPI), + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + PAD_NC(GPP_C2, NONE), + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + PAD_NC(GPP_C5, NONE), + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_CFG_GPI_APIC_LOW(GPP_C14, NONE, DEEP), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), + PAD_CFG_GPO(GPP_C22, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, LEVEL, INVERT), + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_CFG_GPO(GPP_F7, 1, DEEP), + PAD_NC(GPP_F8, NONE), + PAD_CFG_GPO(GPP_F9, 1, DEEP), + PAD_NC(GPP_F10, NONE), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + PAD_NC(GPP_F16, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + PAD_NC(GPP_F20, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_F21, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + /* ------- GPIO Group GPP_E ------- */ + PAD_NC(GPP_E0, NONE), + PAD_CFG_GPO(GPP_E1, 1, PLTRST), + PAD_CFG_GPI_SCI(GPP_E2, NONE, DEEP, LEVEL, INVERT), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + PAD_NC(GPP_E6, NONE), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + PAD_NC(GPP_E13, NONE), + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_NC(GPP_E15, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E16, DN_20K, DEEP, OFF, ACPI), + PAD_NC(GPP_E17, NONE), + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF4), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF4), + PAD_NC(GPP_E20, NONE), + PAD_NC(GPP_E21, NONE), + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +void variant_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c new file mode 100644 index 00000000000..3e426ccd986 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/gpio_early.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Name format: / */ +static const struct pad_config early_gpio_table[] = { + PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1), /* UART2_RXD */ + PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1), /* UART2_TXD */ + PAD_CFG_GPO(GPP_U4, 0, DEEP), /* DGPU_RST#_PCH */ + PAD_CFG_GPO(GPP_U5, 0, DEEP), /* DGPU_PWR_EN */ +}; + +void variant_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c new file mode 100644 index 00000000000..1979c95b74c --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/hda_verb.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC293 */ + 0x10ec0293, /* Vendor ID */ + 0x15584019, /* Subsystem ID */ + 12, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x15584018), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x15, 0x02211020), + AZALIA_PIN_CFG(0, 0x16, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x41748245), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + + /* Tigerlake HDMI */ + 0x80862812, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c new file mode 100644 index 00000000000..94dbe311858 --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/ramstage.c @@ -0,0 +1,64 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define DGPU_RST_N GPP_U4 +#define DGPU_PWR_EN GPP_U5 + +void variant_configure_fsps(FSP_S_CONFIG *params) +{ + /* + * Disable AER for the SSD slot to support S0ix with SSDs running + * buggy firmware + */ + params->CpuPcieRpAdvancedErrorReporting[0] = 0; + params->CpuPcieRpLtrEnable[0] = 1; + params->CpuPcieRpSlotImplemented[0] = 1; +} + +static void dgpu_power_enable(int onoff) { + printk(BIOS_DEBUG, "nvidia: DGPU power %d\n", onoff); + if (onoff) { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 1); + mdelay(4); + gpio_set(DGPU_RST_N, 1); + } else { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 0); + } + mdelay(50); +} + +static void mainboard_pre_device(void *unused) { + dgpu_power_enable(dasharo_is_dgpu_enabled()); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, mainboard_pre_device, NULL); + +void variant_init(void) { + config_t *cfg = config_of_soc(); + struct device *cnvi_dev = pcidev_on_root(0x14, 3); + struct device *wlan_dev = pcidev_on_root(0x1d, 2); + bool radio_enable = get_wireless_option(); + + printk(BIOS_DEBUG, "Wireless is %sabled\n", radio_enable ? "en" : "dis"); + + wlan_dev->enabled = radio_enable; + cnvi_dev->enabled = radio_enable; + cfg->usb2_ports[9].enable = radio_enable; + + dasharo_ec_smfi_cmd(CMD_WIFI_BT_ENABLEMENT_SET, 1, (uint8_t *)&radio_enable); +} diff --git a/src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c b/src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c new file mode 100644 index 00000000000..ffdaf81eaab --- /dev/null +++ b/src/mainboard/clevo/tgl-u/variants/nv40mz/romstage.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void variant_configure_fspm(FSPM_UPD *memupd) +{ + const struct mb_cfg board_cfg = { + .type = MEM_TYPE_DDR4, + }; + const struct mem_spd spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { .addr_dimm[0] = 0x50, }, + [1] = { .addr_dimm[0] = 0x52, }, + }, + }; + const bool half_populated = false; + + memcfg_init(memupd, &board_cfg, &spd_info, half_populated); +} diff --git a/src/mainboard/clevo/tgl-u/vboot-rwa.fmd b/src/mainboard/clevo/tgl-u/vboot-rwa.fmd new file mode 100644 index 00000000000..b1d36aaa9dc --- /dev/null +++ b/src/mainboard/clevo/tgl-u/vboot-rwa.fmd @@ -0,0 +1,40 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL 5M { + SI_DESC 4K + SI_ME + } + + RW_MISC 424K { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_SHARED 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_NVRAM(PRESERVE) 24K + } + + CONSOLE 0x20000 + BOOTSPLASH(CBFS) 1M + + RW_SECTION_A { + VBLOCK_A 0x2000 + FW_MAIN_A(CBFS) + RW_FWID_A 0x40 + } + + # align this with a WP region? + WP_RO 0x400000 { + RO_VPD(PRESERVE)@0x0 0x4000 + RO_SECTION@0x4000 0x3fc000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x3000 + COREBOOT(CBFS)@0x4000 0x3f8000 + } + } +} diff --git a/src/mainboard/dell/snb_ivb_workstations/Kconfig b/src/mainboard/dell/snb_ivb_workstations/Kconfig index a1e446ebe0c..1d31076686a 100644 --- a/src/mainboard/dell/snb_ivb_workstations/Kconfig +++ b/src/mainboard/dell/snb_ivb_workstations/Kconfig @@ -58,6 +58,9 @@ config USBDEBUG_HCD_INDEX config CBFS_SIZE default 0x600000 +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/default.fmd" + config INCLUDE_SMSC_SCH5545_EC_FW bool "Include SMSC SCH5545 EC firmware binary" default n diff --git a/src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl b/src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl index f890b5af541..9877edfa22f 100644 --- a/src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl +++ b/src/mainboard/dell/snb_ivb_workstations/acpi/platform.asl @@ -38,17 +38,4 @@ Scope (\_GPE) Notify (\_SB.PCI0.EHC2, 0x02) Notify (\_SB.PCI0.GLAN, 0x02) } - - Method (_L09, 0, NotSerialized) - { - Notify (\_SB.PCI0.RP01, 0x02) - Notify (\_SB.PCI0.RP02, 0x02) - Notify (\_SB.PCI0.RP03, 0x02) - Notify (\_SB.PCI0.RP04, 0x02) - Notify (\_SB.PCI0.RP05, 0x02) - Notify (\_SB.PCI0.RP06, 0x02) - Notify (\_SB.PCI0.RP07, 0x02) - Notify (\_SB.PCI0.RP08, 0x02) - Notify (\_SB.PCI0.PEGP, 0x02) - } } diff --git a/src/mainboard/dell/snb_ivb_workstations/default.fmd b/src/mainboard/dell/snb_ivb_workstations/default.fmd new file mode 100644 index 00000000000..4313ea03360 --- /dev/null +++ b/src/mainboard/dell/snb_ivb_workstations/default.fmd @@ -0,0 +1,19 @@ +FLASH@0xff400000 12M { + SI_ALL 6M { + SI_DESC 4K + SI_GBE 16K + SI_ME + } + UNUSED 2M + SI_BIOS 4M { + MISC_RW 384K { + SMMSTORE(PRESERVE) 256K + RW_MRC_CACHE 64K + RW_ELOG(PRESERVE) 64K + } + WP_RO { + FMAP 2K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/dell/snb_ivb_workstations/gpio.c b/src/mainboard/dell/snb_ivb_workstations/gpio.c index d01e6221a64..c4d48df21a4 100644 --- a/src/mainboard/dell/snb_ivb_workstations/gpio.c +++ b/src/mainboard/dell/snb_ivb_workstations/gpio.c @@ -32,7 +32,7 @@ static const struct pch_gpio_set1 pch_gpio_set1_mode = { .gpio26 = GPIO_MODE_NATIVE, .gpio27 = GPIO_MODE_GPIO, .gpio28 = GPIO_MODE_GPIO, - .gpio29 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, .gpio30 = GPIO_MODE_NATIVE, .gpio31 = GPIO_MODE_GPIO, /* Password Clear Jumper */ }; @@ -59,7 +59,6 @@ static const struct pch_gpio_set1 pch_gpio_set1_direction = { .gpio24 = GPIO_DIR_INPUT, .gpio27 = GPIO_DIR_OUTPUT, .gpio28 = GPIO_DIR_OUTPUT, - .gpio29 = GPIO_DIR_OUTPUT, .gpio31 = GPIO_DIR_INPUT, }; @@ -69,7 +68,6 @@ static const struct pch_gpio_set1 pch_gpio_set1_level = { .gpio15 = GPIO_LEVEL_LOW, .gpio27 = GPIO_LEVEL_LOW, .gpio28 = GPIO_LEVEL_LOW, - .gpio29 = GPIO_LEVEL_HIGH, }; static const struct pch_gpio_set1 pch_gpio_set1_reset = { diff --git a/src/mainboard/dell/snb_ivb_workstations/mainboard.c b/src/mainboard/dell/snb_ivb_workstations/mainboard.c index c32121112a9..699a511ed27 100644 --- a/src/mainboard/dell/snb_ivb_workstations/mainboard.c +++ b/src/mainboard/dell/snb_ivb_workstations/mainboard.c @@ -2,6 +2,7 @@ #include #include +#include #include #include #include @@ -149,6 +150,15 @@ static void mainboard_enable(struct device *dev) } } +static void mainboard_init(void *chip_info) +{ + struct device *ps2_dev = dev_find_slot_pnp(0x2e, SCH5545_LDN_KBC); + bool ps2_en = get_ps2_option(); + + ps2_dev->enabled = ps2_en & 1; + printk(BIOS_DEBUG, "PS2 Controller state: %d\n", ps2_en); +} + static void mainboard_final(void *chip_info) { int pin_sts; @@ -186,6 +196,7 @@ static void mainboard_final(void *chip_info) struct chip_operations mainboard_ops = { .enable_dev = mainboard_enable, .final = mainboard_final, + .init = mainboard_init, }; BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, sch5545_ec_hwm_init, NULL); diff --git a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb index 2ba11b436ca..31f5cde69fc 100644 --- a/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb +++ b/src/mainboard/dell/snb_ivb_workstations/variants/baseboard/devicetree.cb @@ -16,9 +16,6 @@ chip northbridge/intel/sandybridge chip southbridge/intel/bd82x6x # Intel Series 7 Panther Point PCH register "gpe0_en" = "0x00002a46" - register "alt_gp_smi_en" = "0x0004" - register "gpi2_routing" = "1" - register "gpi12_routing" = "2" register "gen1_dec" = "0x007c0a01" register "gen2_dec" = "0x007c0901" register "gen3_dec" = "0x003c07e1" diff --git a/src/mainboard/emulation/qemu-q35/Kconfig b/src/mainboard/emulation/qemu-q35/Kconfig index 70a7437fc8e..8f5b0fab4cb 100644 --- a/src/mainboard/emulation/qemu-q35/Kconfig +++ b/src/mainboard/emulation/qemu-q35/Kconfig @@ -31,6 +31,7 @@ config VBOOT config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa-8M.fmd" if VBOOT_SLOTS_RW_A && !VBOOT_SLOTS_RW_AB default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab-8M.fmd" if VBOOT_SLOTS_RW_AB + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" if ARCH_BOOTBLOCK_X86_64 diff --git a/src/mainboard/emulation/qemu-q35/board.fmd b/src/mainboard/emulation/qemu-q35/board.fmd new file mode 100644 index 00000000000..17b4bedeff4 --- /dev/null +++ b/src/mainboard/emulation/qemu-q35/board.fmd @@ -0,0 +1,8 @@ +FLASH@0xff800000 0x800000 { + BIOS 0x800000 { + SMMSTORE 0x40000 + FMAP 0x200 + BOOTSPLASH(CBFS) 0x40000 + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd index 55a38b79a94..ce2f686095c 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwa-8M.fmd @@ -6,6 +6,7 @@ FLASH@0xff800000 0x800000 { RW_FWID_A 0x40 } RW_VPD(PRESERVE) 0x1000 + BOOTSPLASH(CBFS) 0x40000 WP_RO { FMAP 0x800 diff --git a/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd b/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd index 8064fdfeafe..63b6ad2c9ff 100644 --- a/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd +++ b/src/mainboard/emulation/qemu-q35/vboot-rwab-8M.fmd @@ -16,6 +16,7 @@ FLASH@0xff800000 0x800000 { } RW_VPD(PRESERVE) 0x1000 RW_LEGACY(CBFS) 0x10000 + BOOTSPLASH(CBFS) 0x40000 WP_RO { FMAP 0x800 RO_FRID 0x40 diff --git a/src/mainboard/hardkernel/odroid-h4/Kconfig b/src/mainboard/hardkernel/odroid-h4/Kconfig index 3e03116db75..76831b774b2 100644 --- a/src/mainboard/hardkernel/odroid-h4/Kconfig +++ b/src/mainboard/hardkernel/odroid-h4/Kconfig @@ -23,6 +23,48 @@ config MAINBOARD_DIR config MAINBOARD_PART_NUMBER default "ODROID-H4" +config MAINBOARD_VENDOR + default "HARDKERNEL" + +config MAINBOARD_FAMILY + default "H4" + +config DIMM_SPD_SIZE + default 1024 + +config DIMM_MAX + default 2 + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config CBFS_SIZE + default 0xa00000 + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_NO_BOARD_SUPPORT + select HAS_RECOVERY_MRC_CACHE + select VBOOT_NO_TPM + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + config ODROID_H4_ENABLE_SAGV bool "Enable SAGV" default y diff --git a/src/mainboard/hardkernel/odroid-h4/Makefile.mk b/src/mainboard/hardkernel/odroid-h4/Makefile.mk index 2e6759f0936..6e2926fa3b0 100644 --- a/src/mainboard/hardkernel/odroid-h4/Makefile.mk +++ b/src/mainboard/hardkernel/odroid-h4/Makefile.mk @@ -5,3 +5,9 @@ bootblock-y += bootblock.c romstage-y += romstage_fsp_params.c ramstage-y += mainboard.c + +romstage-y += gpio.c +ramstage-y += gpio.c + +bootblock-y += die.c +romstage-y += die.c diff --git a/src/mainboard/hardkernel/odroid-h4/acpi/superio.asl b/src/mainboard/hardkernel/odroid-h4/acpi/superio.asl new file mode 100644 index 00000000000..b7d6a64799d --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/acpi/superio.asl @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8613E_SHOW_UARTA + +#include diff --git a/src/mainboard/hardkernel/odroid-h4/bootblock.c b/src/mainboard/hardkernel/odroid-h4/bootblock.c index 31db1352812..0999067b150 100644 --- a/src/mainboard/hardkernel/odroid-h4/bootblock.c +++ b/src/mainboard/hardkernel/odroid-h4/bootblock.c @@ -1,18 +1,40 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include +#include #include #define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) #define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) +#define ITE_GPIO_BASE 0xa00 +#define ITE_GPIO_PIN(x) (1 << ((x) % 10)) +#define ITE_GPIO_SET(x) (((x) / 10) - 1) +#define ITE_GPIO_IO_ADDR(x) (ITE_GPIO_BASE + ITE_GPIO_SET(x)) + +static void ite_set_gpio_iobase(u16 iobase) +{ + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO1, iobase); + pnp_exit_conf_state(GPIO_DEV); +} + void bootblock_mainboard_early_init(void) { - /* Set up Super I/O GPIOs, values are dumped from vendor firmware */ + /* Set up Super I/O GPIOs, some values are dumped from vendor firmware */ + + /* Internal VCC_OK */ + ite_reg_write(GPIO_DEV, 0x23, 0x40); + /* Pin7 as GP23 - USB2_EN */ ite_reg_write(GPIO_DEV, 0x26, 0xfb); + /* Pin24 as GPO50 (value of 0 on bit0 is reserved, JP1 strapping)*/ ite_reg_write(GPIO_DEV, 0x29, 0x01); + /* K8 power sequence software disabled */ ite_reg_write(GPIO_DEV, 0x2c, 0x41); + /* PCICLK 25MHz */ ite_reg_write(GPIO_DEV, 0x2d, 0x02); ite_reg_write(GPIO_DEV, 0xbc, 0xc0); ite_reg_write(GPIO_DEV, 0xbd, 0x03); @@ -22,6 +44,19 @@ void bootblock_mainboard_early_init(void) ite_reg_write(GPIO_DEV, 0xda, 0xb0); ite_reg_write(GPIO_DEV, 0xdb, 0x44); + ite_kill_watchdog(GPIO_DEV); + /* GP21 - USB3_EN, VBUS power gate for the USB3.x ports */ + ite_gpio_setup(GPIO_DEV, 21, + ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, ITE_GPIO_CONTROL_DEFAULT); + /* GP23 - USB2_EN, VBUS power gate for the USB2.x ports */ + ite_gpio_setup(GPIO_DEV, 23, + ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, ITE_GPIO_CONTROL_DEFAULT); + + ite_set_gpio_iobase(ITE_GPIO_BASE); + /* GP21 and GP23 to low to enable USB ports VBUS */ + outb(inb(ITE_GPIO_IO_ADDR(21)) & ~ITE_GPIO_PIN(21), ITE_GPIO_IO_ADDR(21)); + outb(inb(ITE_GPIO_IO_ADDR(23)) & ~ITE_GPIO_PIN(23), ITE_GPIO_IO_ADDR(23)); + ite_delay_pwrgd3(GPIO_DEV); ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/hardkernel/odroid-h4/devicetree.cb b/src/mainboard/hardkernel/odroid-h4/devicetree.cb index 48f35fd421f..546df367494 100644 --- a/src/mainboard/hardkernel/odroid-h4/devicetree.cb +++ b/src/mainboard/hardkernel/odroid-h4/devicetree.cb @@ -5,22 +5,29 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "PMC_GPP_R" register "pmc_gpe0_dw2" = "PMC_GPD" - register "sagv" = "CONFIG(ODROID_H4_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled" + # FSP configuration + register "eist_enable" = "true" + # Sagv Configuration + register "sagv" = "CONFIG(ODROID_H4_ENABLE_SAGV) ? SaGv_Enabled : SaGv_Disabled" + register "RMT" = "0" register "enable_c6dram" = "true" register "tcc_offset" = "10" # TCC of 90C device domain 0 on + subsystemid 0x8086 0x7270 inherit device ref igpu on - register "ddi_portA_config" = "1" - register "ddi_portB_config" = "1" + register "ddi_portA_config" = "1" # HDMI on port A + register "ddi_portB_config" = "1" # DP on port B + # Fixed DP in TCP0 register "ddi_ports_config" = "{ [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, }" end + device ref xhci on ## Yes, the numbering of the three USB2 ports routed to the EXT_HEAD1 ## pin header does not correlate with the numbering of the USB2 ports @@ -61,12 +68,18 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB3 Type-A (Bottom Right)"" register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" device ref usb2_port1 on end device ref usb3_port1 on end end chip drivers/usb/acpi register "desc" = ""USB3 Type-A (Top Right)"" register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" device ref usb2_port2 on end device ref usb3_port2 on end end @@ -83,6 +96,9 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A (Top Left)"" register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" device ref usb2_port5 on end end chip drivers/usb/acpi @@ -93,11 +109,15 @@ chip soc/intel/alderlake chip drivers/usb/acpi register "desc" = ""USB2 Type-A (Bottom Left)"" register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, LEFT, ACPI_PLD_GROUP(2, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" device ref usb2_port7 on end end end end end + device ref i2c0 on register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" register "common_soc_config.i2c[0]" = "{ @@ -114,31 +134,48 @@ chip soc/intel/alderlake .fall_time_ns = 110, }" end + device ref heci1 on end + device ref sata on + register "sata_salp_support" = "1" + + register "sata_ports_enable" = "{ + [0] = 0, + [1] = 1, + }" + + register "sata_ports_hotplug" = "{ + [0] = 0, + [1] = 1, + }" + end + device ref emmc on register "emmc_enable_hs400_mode" = "true" end - device ref pcie_rp3 on # LAN1 + + device ref pcie_rp3 on # LAN1 Intel i226 register "pch_pcie_rp[PCH_RP(3)]" = "{ .clk_src = 1, .clk_req = 1, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref pcie_rp4 on # LAN2 + device ref pcie_rp4 on # LAN2 Intel i226 register "pch_pcie_rp[PCH_RP(4)]" = "{ .clk_src = 2, .clk_req = 2, .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref pcie_rp7 on # ASM1064B SATA + device ref pcie_rp7 on # ASM1064B SATA (ASMedia PCie to 4xSATA) register "pch_pcie_rp[PCH_RP(7)]" = "{ .clk_src = 3, .clk_req = 3, // Use hardwired CLKREQ# to allow clock gating .flags = PCIE_RP_LTR | PCIE_RP_AER, }" end - device ref pcie_rp9 on # M.2 M (x4) + + device ref pcie_rp9 on # M.2 M NVMe (x4) register "pch_pcie_rp[PCH_RP(9)]" = "{ .clk_src = 0, .clk_req = 0, @@ -147,36 +184,20 @@ chip soc/intel/alderlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (M2_SSD1)" "SlotDataBusWidth4X" end + device ref pch_espi on + # LPC generic I/O ranges register "gen1_dec" = "0x00fc0201" register "gen2_dec" = "0x007c0a01" register "gen3_dec" = "0x000c03e1" register "gen4_dec" = "0x001c02e1" chip superio/ite/it8613e - register "ec.vin_mask" = "VIN0 | VIN1 | VIN2 | VIN4 | VIN5" - # TODO: figure out how to make PECI work - register "TMPIN1.mode" = "THERMAL_DIODE" - #register "TMPIN1.mode" = "THERMAL_PECI" - #register "TMPIN1.offset" = "0x56" - register "FAN2" = "{ - .mode = FAN_SMART_AUTOMATIC, - .smart = { - .tmpin = 1, - .tmp_off = 20, - .tmp_start = 35, - .tmp_full = 70, - .tmp_delta = 1, - .pwm_start = 20, - .slope = 3, - .smoothing = 0, - }, - }" - device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 irq 0x70 = 4 irq 0xf0 = 0x01 + irq 0xf1 = 0x52 # IRQ low level end device pnp 2e.4 on # Environment Controller io 0x60 = 0xa30 @@ -194,6 +215,7 @@ chip soc/intel/alderlake device pnp 2e.a off end # CIR end end + device ref p2sb hidden end device ref hda on register "pch_hda_dsp_enable" = "true" register "pch_hda_sdi_enable[0]" = "true" diff --git a/src/mainboard/hardkernel/odroid-h4/die.c b/src/mainboard/hardkernel/odroid-h4/die.c new file mode 100644 index 00000000000..85fe2299c79 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/die.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void die_notify(void) +{ + static uint8_t blink = 0; + + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink */ + gpio_output(GPP_B14, 0); + + while (1) { + gpio_set(GPP_B14, blink); + blink ^= 1; + mdelay(500); + } +} diff --git a/src/mainboard/hardkernel/odroid-h4/dsdt.asl b/src/mainboard/hardkernel/odroid-h4/dsdt.asl index 584f330cbb1..a6e97c4ceb9 100644 --- a/src/mainboard/hardkernel/odroid-h4/dsdt.asl +++ b/src/mainboard/hardkernel/odroid-h4/dsdt.asl @@ -22,5 +22,10 @@ DefinitionBlock( #include } + Scope (\_SB.PCI0.LPCB) + { + #include "acpi/superio.asl" + } + #include } diff --git a/src/mainboard/hardkernel/odroid-h4/gpio.c b/src/mainboard/hardkernel/odroid-h4/gpio.c new file mode 100644 index 00000000000..afe7b3d53c6 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/gpio.c @@ -0,0 +1,609 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include "gpio.h" + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + /* GPP_B3 - GPIO */ + PAD_NC(GPP_B3, NONE), + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + /* GPP_B8 - GPIO EMMC_DET# */ + PAD_CFG_GPI(GPP_B8, UP_20K, PLTRST), + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - SATA_LED# */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF4), + /* GPP_B15 - GPIO */ + PAD_NC(GPP_B15, NONE), + /* GPP_B16 - GPIO */ + PAD_NC(GPP_B16, NONE), + /* GPP_B17 - GPIO */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18 - GPIO */ + PAD_NC(GPP_B18, NONE), + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + /* GPP_B23 - GPIO */ + PAD_NC(GPP_B23, NONE), + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_T ------- */ + + /* GPP_T0 - GPIO */ + PAD_NC(GPP_T0, NONE), + /* GPP_T1 - GPIO */ + PAD_NC(GPP_T1, NONE), + /* GPP_T2 - GPIO */ + PAD_NC(GPP_T2, NONE), + /* GPP_T3 - GPIO */ + PAD_NC(GPP_T3, NONE), + /* GPP_T4 - GPIO */ + PAD_NC(GPP_T4, NONE), + /* GPP_T5 - GPIO */ + PAD_NC(GPP_T5, NONE), + /* GPP_T6 - GPIO */ + PAD_NC(GPP_T6, NONE), + /* GPP_T7 - GPIO */ + PAD_NC(GPP_T7, NONE), + /* GPP_T8 - GPIO */ + PAD_NC(GPP_T8, NONE), + /* GPP_T9 - GPIO */ + PAD_NC(GPP_T9, NONE), + /* GPP_T10 - GPIO */ + PAD_NC(GPP_T10, NONE), + /* GPP_T11 - GPIO */ + PAD_NC(GPP_T11, NONE), + /* GPP_T12 - GPIO */ + PAD_NC(GPP_T12, NONE), + /* GPP_T13 - GPIO */ + PAD_NC(GPP_T13, NONE), + /* GPP_T14 - GPIO */ + PAD_NC(GPP_T14, NONE), + /* GPP_T15 - GPIO */ + PAD_NC(GPP_T15, NONE), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + /* GPP_A6 - GPIO */ + PAD_NC(GPP_A6, NONE), + /* GPP_A7 - GPIO */ + PAD_NC(GPP_A7, NONE), + /* GPP_A8 - LAN_DISABLE# */ + PAD_CFG_GPO(GPP_VGPIO_0, 1, DEEP), + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + /* GPP_A12 - SATAXPCIE1 */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* GPP_A13 - GPIO */ + PAD_NC(GPP_A13, NONE), + /* GPP_A14 - GPIO */ + PAD_NC(GPP_A14, NONE), + /* GPP_A15 - GPIO */ + PAD_NC(GPP_A15, NONE), + /* GPP_A16 - GPIO */ + PAD_NC(GPP_A16, NONE), + /* GPP_A17 - GPIO */ + PAD_NC(GPP_A17, NONE), + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* GPP_A19 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* GPP_A20 - GPIO */ + PAD_NC(GPP_A20, NONE), + /* GPP_A21 - GPIO */ + PAD_NC(GPP_A21, NONE), + /* GPP_A22 - GPIO */ + PAD_NC(GPP_A22, NONE), + /* GPP_A23 - GPIO */ + PAD_NC(GPP_A23, NONE), + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + + /* GPP_I5 - GPIO */ + PAD_NC(GPP_I5, NONE), + /* GPP_I7 - EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* GPP_I8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* GPP_I9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* GPP_I10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* GPP_I11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* GPP_I12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* GPP_I13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* GPP_I14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* GPP_I15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* GPP_I16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* GPP_I17 - EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* GPP_I18 - EMMC_RESET# */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_NC(GPP_H0, NONE), + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + /* GPP_H2 - GPIO */ + PAD_NC(GPP_H2, NONE), + /* GPP_H3 - GPIO */ + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* GPP_H6 - I2C1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* GPP_H7 - I2C1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* GPP_H8 - GPIO */ + PAD_NC(GPP_H8, NONE), + /* GPP_H9 - GPIO */ + PAD_NC(GPP_H9, NONE), + /* GPP_H10 - GPIO */ + PAD_NC(GPP_H10, NONE), + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11, NONE), + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12, NONE), + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + /* GPP_H16 - GPIO */ + PAD_NC(GPP_H16, NONE), + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* GPP_H19 - GPIO */ + PAD_NC(GPP_H19, NONE), + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_NC(GPP_D0, NONE), + /* GPP_D1 - GPIO */ + PAD_NC(GPP_D1, NONE), + /* GPP_D2 - GPIO */ + PAD_NC(GPP_D2, NONE), + /* GPP_D3 - GPIO */ + PAD_NC(GPP_D3, NONE), + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + /* GPP_D5 - SRCCLKREQ0# to PCIE RP 9 (NVMe) */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D6 - SRCCLKREQ1# to PCIE RP 3 (LAN1) */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPP_D7 - SRCCLKREQ2# to PCIE RP 4 (LAN2) */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D8 - SRCCLKREQ3# presumably for PCIE RP7, but permanently grounded? */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D9, NATIVE), + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NATIVE), + /* GPP_D11 - GPIO */ + PAD_NC(GPP_D11, NATIVE), + /* GPP_D12 - GPIO */ + PAD_NC(GPP_D12, NATIVE), + /* GPP_D13 - GPIO */ + PAD_NC(GPP_D13, NONE), + /* GPP_D14 - GPIO */ + PAD_NC(GPP_D14, NONE), + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + /* GPP_VGPIO_THC0 - GPP_VGPIO_THC0 */ + PAD_CFG_NF(GPP_VGPIO_THC0, NONE, DEEP, NF1), + /* GPP_VGPIO_THC1 - GPP_VGPIO_THC1 */ + PAD_CFG_NF(GPP_VGPIO_THC1, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + /* GPD2 - GPIO */ + PAD_NC(GPD2, NONE), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + /* GPD7 - GPIO */ + PAD_NC(GPD7, NONE), + /* GPD8 - SUS_CLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + /* GPD11 - GPIO */ + PAD_NC(GPD11, NONE), + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* GPP_C2 - GPIO */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - GPIO */ + PAD_NC(GPP_C3, NONE), + /* GPP_C4 - GPIO */ + PAD_NC(GPP_C4, NONE), + /* GPP_C5 - GPIO */ + PAD_NC(GPP_C5, NONE), + /* GPP_C6 - GPIO */ + PAD_NC(GPP_C6, NONE), + /* GPP_C7 - GPIO */ + PAD_NC(GPP_C7, NONE), + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + /* GPP_C14 - GPIO */ + PAD_NC(GPP_C14, NONE), + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + /* GPP_C16 - GPIO */ + PAD_NC(GPP_C16, NONE), + /* GPP_C17 - GPIO */ + PAD_NC(GPP_C17, NONE), + /* GPP_C18 - GPIO */ + PAD_NC(GPP_C18, NONE), + /* GPP_C19 - GPIO */ + PAD_NC(GPP_C19, NONE), + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + /* GPP_C22 - GPIO */ + PAD_NC(GPP_C22, NONE), + /* GPP_C23 - GPIO */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - GPIO */ + PAD_NC(GPP_F0, NONE), + /* GPP_F1 - GPIO */ + PAD_NC(GPP_F1, NONE), + /* GPP_F2 - GPIO */ + PAD_NC(GPP_F2, NONE), + /* GPP_F3 - GPIO */ + PAD_NC(GPP_F3, NONE), + /* GPP_F4 - GPIO# */ + PAD_NC(GPP_F4, NONE), + /* GPP_F5 - GPIO */ + PAD_NC(GPP_F5, NONE), + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + /* GPP_F7 - GPIO */ + PAD_NC(GPP_F7, NONE), + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + /* GPP_F9 - GPIO */ + PAD_NC(GPP_F9, NONE), + /* GPP_F10 - GPIO */ + PAD_NC(GPP_F10, NONE), + /* GPP_F11 - GPIO */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12 - GPIO */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13 - GPIO */ + PAD_NC(GPP_F13, NONE), + /* GPP_F14 - GPIO */ + PAD_NC(GPP_F14, NONE), + /* GPP_F15 - GPIO */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16 - GPIO */ + PAD_NC(GPP_F16, NONE), + /* GPP_F17 - GPIO */ + PAD_NC(GPP_F17, NONE), + /* GPP_F18 - GPIO */ + PAD_NC(GPP_F18, NONE), + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + /* GPP_F20 - Reserved */ + PAD_NC(GPP_F20, NONE), + /* GPP_F21 - Reserved */ + PAD_NC(GPP_F21, NONE), + /* GPP_F22 - GPIO */ + PAD_NC(GPP_F22, NONE), + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + /* GPP_F_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + PAD_NC(GPP_L_BKLTEN, NONE), + /* GPP_L_BKLTCTL - n/a */ + PAD_NC(GPP_L_BKLTCTL, NONE), + /* GPP_L_VDDEN - n/a */ + PAD_NC(GPP_L_VDDEN, NONE), + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + /* GPP_E1 - GPIO */ + PAD_NC(GPP_E1, NONE), + /* GPP_E2 - GPIO */ + PAD_NC(GPP_E2, NONE), + /* GPP_E3 - GPIO */ + PAD_NC(GPP_E3, NONE), + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + /* GPP_E5 - GPIO */ + PAD_NC(GPP_E5, NONE), + /* GPP_E6 - GPIO */ + PAD_NC(GPP_E6, NONE), + /* GPP_E7 - GPIO */ + PAD_NC(GPP_E7, NONE), + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 - GPIO */ + PAD_NC(GPP_E13, NONE), + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* GPP_E15 - Reserved */ + PAD_NC(GPP_E15, NONE ), + /* GPP_E16 - Connetced to pad 67 in M.2 NVMe slot */ + PAD_CFG_GPI(GPP_E16, NONE, DEEP), + /* GPP_E17 - GPIO */ + PAD_NC(GPP_E17, NONE), + /* GPP_E18 - DDP1_CTRLCLK */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* GPP_E19 - DDP1_CTRLDATA */ + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NATIVE), + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NATIVE), + /* GPP_E22 - DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), + /* GPP_E23 - DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* GPP_R4 - HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE) +}; + +const struct pad_config *board_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/hardkernel/odroid-h4/gpio.h b/src/mainboard/hardkernel/odroid-h4/gpio.h new file mode 100644 index 00000000000..c6f88485c59 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef HARDKERNEL_ODROID_H4_GPIO_H +#define HARDKERNEL_ODROID_H4_GPIO_H + +const struct pad_config *board_gpio_table(size_t *num); + +#endif /* HARDKERNEL_ODROID_H4_GPIO_H */ diff --git a/src/mainboard/hardkernel/odroid-h4/mainboard.c b/src/mainboard/hardkernel/odroid-h4/mainboard.c index d8cfc8814d7..957d06f61ae 100644 --- a/src/mainboard/hardkernel/odroid-h4/mainboard.c +++ b/src/mainboard/hardkernel/odroid-h4/mainboard.c @@ -1,219 +1,30 @@ -/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* SPDX-License-Identifier: GPL-2.0-only */ -#include -#include +#include #include +#include +#include +#include -/* - * Pad configuration was derived from schematics, revision 0.1 - * - https://wiki.odroid.com/odroid-h4/hardware#odroid-h4_schematics - */ -static const struct pad_config gpio_table[] = { - - /* ------- GPIO Group GPP_A ------- */ - PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* ESPI_IO0 */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), /* ESPI_IO1 */ - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), /* ESPI_IO2 */ - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), /* ESPI_IO3 */ - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), /* ESPI_CS# */ - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* ESPI_ALERT# */ - PAD_NC(GPP_A6, NONE), - PAD_NC(GPP_A7, NONE), - PAD_CFG_GPO(GPP_A8, 1, PLTRST), /* LAN_DISABLE# */ - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), /* ESPI_CLK */ - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), /* ESPI_RESET# */ - PAD_NC(GPP_A11, NONE), - PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), /* M.2_SSD_PEDET_R */ - PAD_NC(GPP_A13, NONE), - PAD_NC(GPP_A14, NONE), - PAD_NC(GPP_A15, NONE), - PAD_NC(GPP_A16, NONE), - PAD_NC(GPP_A17, NONE), - PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), /* DDI1_HPD */ - PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), /* TCP0_HPD */ - PAD_NC(GPP_A20, NONE), - PAD_NC(GPP_A21, NONE), - PAD_NC(GPP_A22, NONE), - PAD_NC(GPP_A23, NONE), - - /* ------- GPIO Group GPP_B ------- */ - PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ - PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ - PAD_CFG_NF(GPP_B2, NONE, PLTRST, NF1), /* VRALERT# */ - PAD_NC(GPP_B3, NONE), - PAD_NC(GPP_B4, NONE), - PAD_NC(GPP_B5, NONE), - PAD_NC(GPP_B6, NONE), - PAD_NC(GPP_B7, NONE), - PAD_CFG_GPI(GPP_B8, NONE, DEEP), /* EMMC_DET#_L */ - PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* PMCALERT# */ - PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ - PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PM_PLTRST_N */ - PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF4), /* PCH_SATA_LED# */ - PAD_NC(GPP_B15, NONE), - PAD_NC(GPP_B16, NONE), - PAD_NC(GPP_B17, NONE), - PAD_NC(GPP_B18, NONE), - PAD_NC(GPP_B23, NONE), - - /* ------- GPIO Group GPP_C ------- */ - PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ - PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ - PAD_CFG_NF(GPP_C2, NONE, DEEP, NF1), /* SMB_ALERT# */ - PAD_NC(GPP_C3, NONE), - PAD_NC(GPP_C4, NONE), - PAD_NC(GPP_C5, NONE), - PAD_NC(GPP_C6, NONE), - PAD_NC(GPP_C7, NONE), - - /* ------- GPIO Group GPP_D ------- */ - PAD_NC(GPP_D0, NONE), - PAD_NC(GPP_D1, NONE), - PAD_NC(GPP_D2, NONE), - PAD_NC(GPP_D3, NONE), - PAD_NC(GPP_D4, NONE), - PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), /* PCIE_CLKREQ0_N */ - PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), /* PCIE_CLKREQ1_N */ - PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), /* PCIE_CLKREQ2_N */ - PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), /* CLKREQ3# but always asserted */ - PAD_NC(GPP_D9, NONE), - PAD_NC(GPP_D10, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D11, NONE), - PAD_NC(GPP_D13, NONE), - PAD_NC(GPP_D14, NONE), - PAD_NC(GPP_D15, NONE), - PAD_NC(GPP_D16, NONE), - PAD_NC(GPP_D17, NONE), - PAD_NC(GPP_D18, NONE), - PAD_NC(GPP_D19, NONE), - - /* ------- GPIO Group GPP_E ------- */ - PAD_NC(GPP_E0, NONE), - PAD_NC(GPP_E1, NONE), - PAD_NC(GPP_E2, NONE), - PAD_NC(GPP_E3, NONE), - PAD_NC(GPP_E4, NONE), - PAD_NC(GPP_E5, NONE), - PAD_NC(GPP_E6, NONE), - PAD_NC(GPP_E7, NONE), - PAD_NC(GPP_E8, NONE), - PAD_NC(GPP_E9, NONE), - PAD_NC(GPP_E10, NONE), - PAD_NC(GPP_E11, NONE), - PAD_NC(GPP_E12, NONE), - PAD_NC(GPP_E13, NONE), - PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDI0_HPD */ - PAD_NC(GPP_E15, NONE), - PAD_NC(GPP_E16, NONE), /* Unknown, goes to M.2 pin 67 (NC) */ - PAD_NC(GPP_E17, NONE), - PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), /* TCP0_DDCCLK */ - PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), /* TCP0_DDCDATA */ - PAD_NC(GPP_E20, NONE), - PAD_NC(GPP_E21, NONE), - PAD_CFG_NF(GPP_E22, NONE, DEEP, NF1), /* DDI0_DDCCLK */ - PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), /* DDI0_DDCDATA */ - - /* ------- GPIO Group GPP_F ------- */ - PAD_NC(GPP_F0, NONE), - PAD_NC(GPP_F1, NONE), - PAD_NC(GPP_F2, NONE), - PAD_NC(GPP_F3, NONE), - PAD_NC(GPP_F4, NONE), - PAD_NC(GPP_F5, NONE), - PAD_NC(GPP_F6, NONE), - PAD_NC(GPP_F7, NONE), - PAD_NC(GPP_F10, NONE), - PAD_NC(GPP_F11, NONE), - PAD_NC(GPP_F12, NONE), - PAD_NC(GPP_F13, NONE), - PAD_NC(GPP_F14, NONE), - PAD_NC(GPP_F15, NONE), - PAD_NC(GPP_F16, NONE), - PAD_NC(GPP_F17, NONE), - PAD_NC(GPP_F18, NONE), - PAD_NC(GPP_F22, NONE), - PAD_NC(GPP_F23, NONE), - - /* ------- GPIO Group GPP_H ------- */ - PAD_NC(GPP_H0, NONE), - PAD_NC(GPP_H1, NONE), - PAD_NC(GPP_H2, NONE), - PAD_NC(GPP_H3, NONE), - PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), /* I2C_0_SDA */ - PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), /* I2C_0_SCL */ - PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* I2C_1_SDA */ - PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), /* I2C_1_SCL */ - PAD_NC(GPP_H8, NONE), - PAD_NC(GPP_H9, NONE), - PAD_NC(GPP_H10, NONE), - PAD_NC(GPP_H11, NONE), - PAD_NC(GPP_H12, NONE), - PAD_NC(GPP_H13, NONE), - PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), /* DDI1_DDCCLK */ - PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), /* DDI1_DDCDATA */ - PAD_NC(GPP_H18, NONE), - PAD_NC(GPP_H19, NONE), - PAD_NC(GPP_H20, NONE), - PAD_NC(GPP_H21, NONE), - PAD_NC(GPP_H22, NONE), - PAD_NC(GPP_H23, NONE), - - /* ------- GPIO Group GPP_I ------- */ - PAD_NC(GPP_I5, NONE), - PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), /* EMMC_CMD */ - PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), /* EMMC_DATA_0 */ - PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), /* EMMC_DATA_1 */ - PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), /* EMMC_DATA_2 */ - PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), /* EMMC_DATA_3 */ - PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), /* EMMC_DATA_4 */ - PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), /* EMMC_DATA_5 */ - PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), /* EMMC_DATA_6 */ - PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), /* EMMC_DATA_7 */ - PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), /* EMMC_RCLK */ - PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), /* EMMC_CLK */ - PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), /* EMMC_RESET# */ +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm)); + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); - /* ------- GPIO Group GPP_R ------- */ - PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), /* HDA_BCLK_R */ - PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), /* HDA_SYNC_R */ - PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), /* HDA_SDO_R */ - PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), /* HDA_SDI_R */ - PAD_CFG_NF(GPP_R4, NATIVE, DEEP, NF1), /* HDA_RST_N */ - PAD_NC(GPP_R5, NONE), - PAD_NC(GPP_R6, NONE), - PAD_NC(GPP_R7, NONE), + params->PcieRpEnableCpm[2] = 1; // LAN1 + params->PcieRpEnableCpm[3] = 1; // LAN2 + params->PcieRpEnableCpm[6] = 1; // ASMedia PCIe to SATA + params->PcieRpEnableCpm[8] = 1; // NVMe - /* ------- GPIO Group GPP_S ------- */ - PAD_NC(GPP_S0, NONE), - PAD_NC(GPP_S1, NONE), - PAD_NC(GPP_S2, NONE), - PAD_NC(GPP_S3, NONE), - PAD_NC(GPP_S4, NONE), - PAD_NC(GPP_S5, NONE), - PAD_NC(GPP_S6, NONE), - PAD_NC(GPP_S7, NONE), + // Max payload 256B + memset(params->PcieRpMaxPayload, 1, sizeof(params->PcieRpMaxPayload)); - /* ------- GPIO Group GPP_GPD ------- */ - PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* BATLOW# */ - PAD_CFG_NF(GPD1, NONE, PWROK, NF1), /* ACPRESENT */ - PAD_NC(GPD2, NONE), - PAD_CFG_NF(GPD3, NONE, PWROK, NF1), /* PM_PWRBTN# */ - PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* SLP_S3# */ - PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* SLP_S4# */ - PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* SLP_A# */ - PAD_NC(GPD7, NONE), - PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK */ - PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* SLP_WLAN# */ - PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* SLP_S5# */ - PAD_NC(GPD11, NONE), -}; + // I2C + params->PchSerialIoI2cSdaPinMux[0] = 0x1947c404; // GPP_H4 + params->PchSerialIoI2cSclPinMux[0] = 0x1947a405; // GPP_H5 + params->PchSerialIoI2cSdaPinMux[1] = 0x1947c606; // GPP_H6 + params->PchSerialIoI2cSclPinMux[1] = 0x1947a607; // GPP_H7 -static void mainboard_init(void *chip_info) -{ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + params->CnviRfResetPinMux = 0; + params->CnviClkreqPinMux = 0; } - -struct chip_operations mainboard_ops = { - .init = mainboard_init, -}; diff --git a/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c b/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c index 549a4bdc347..683f31911f7 100644 --- a/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c +++ b/src/mainboard/hardkernel/odroid-h4/romstage_fsp_params.c @@ -3,6 +3,9 @@ #include #include #include +#include + +#include "gpio.h" static const struct mb_cfg ddr5_mem_config = { .type = MEM_TYPE_DDR5, @@ -20,6 +23,14 @@ static const struct mem_spd dimm_module_spd_info = { void mainboard_memory_init_params(FSPM_UPD *memupd) { - const bool half_populated = true; + const struct pad_config *pads; + size_t num; + + const bool half_populated = false; memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, half_populated); + + pads = board_gpio_table(&num); + gpio_configure_pads(pads, num); + + memupd->FspmConfig.DmiMaxLinkSpeed = 4; } diff --git a/src/mainboard/hardkernel/odroid-h4/vboot-rwa.fmd b/src/mainboard/hardkernel/odroid-h4/vboot-rwa.fmd new file mode 100644 index 00000000000..bfe0e6d73b6 --- /dev/null +++ b/src/mainboard/hardkernel/odroid-h4/vboot-rwa.fmd @@ -0,0 +1,36 @@ +FLASH@0xff000000 16M { + SI_ALL 6M { + SI_DESC 4K + SI_ME 0x413000 + SI_DEVICEEXT2 + } + SI_BIOS 10M { + SMMSTORE(PRESERVE) 256K + + RW_MISC 260K { + UNIFIED_MRC_CACHE(PRESERVE) { + RECOVERY_MRC_CACHE 128K + RW_MRC_CACHE 128K + } + RW_NVRAM(PRESERVE) 4K + } + + BOOTSPLASH(CBFS) 252K + + RW_SECTION_A { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + WP_RO 5M { + RO_SECTION { + FMAP 2K + RO_FRID 0x100 + RO_FRID_PAD 0x700 + GBB 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig new file mode 100644 index 00000000000..a6286a46dd3 --- /dev/null +++ b/src/mainboard/intel/minnowmax/Kconfig @@ -0,0 +1,43 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_INTEL_MINNOWMAX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_BAYTRAIL + select BOARD_ROMSIZE_KB_8192 + select ENABLE_BUILTIN_COM1 + select HAVE_SPD_IN_CBFS + select HAVE_ACPI_TABLES + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + +config MAINBOARD_DIR + string + default "intel/minnowmax" + +config MAINBOARD_PART_NUMBER + string + default "Minnow Max" + +config MAX_CPUS + int + default 16 + +config DIMM_SPD_SIZE + int + default 256 + +config CBFS_SIZE + hex + default 0x00600000 + +config POST_DEVICE + bool + default n + +config VGA_BIOS + bool + default y + +endif # BOARD_INTEL_MINNOWMAX diff --git a/src/mainboard/intel/minnowmax/Kconfig.name b/src/mainboard/intel/minnowmax/Kconfig.name new file mode 100644 index 00000000000..a8606fccc8c --- /dev/null +++ b/src/mainboard/intel/minnowmax/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_INTEL_MINNOWMAX + bool "Minnow Max" diff --git a/src/mainboard/intel/minnowmax/Makefile.mk b/src/mainboard/intel/minnowmax/Makefile.mk new file mode 100644 index 00000000000..b7e5ce29c5f --- /dev/null +++ b/src/mainboard/intel/minnowmax/Makefile.mk @@ -0,0 +1,12 @@ +## SPDX-License-Identifier: GPL-2.0-only + +ramstage-y += gpio.c +ramstage-y += irqroute.c + +#SPD_SOURCES = micron_1GiB_1066MHz_dimm_MT41K256M16HA-125 # 0b0000 +#SPD_SOURCES += micron_2GiB_1066MHz_dimm_MT41K256M16HA-125 # 0b0001 +#SPD_SOURCES += micron_1GiB_1333MHz_dimm_MT41K256M16HA-125 # 0b0010 +#SPD_SOURCES += micron_2GiB_1333MHz_dimm_MT41K256M16HA-125 # 0b0011 + +SPD_SOURCES = micron_1GiB_dimm_MT41K256M16HA-125 # 0b0000 +SPD_SOURCES += micron_2GiB_dimm_MT41K256M16HA-125 # 0b0001 diff --git a/src/mainboard/intel/minnowmax/acpi/ec.asl b/src/mainboard/intel/minnowmax/acpi/ec.asl new file mode 100644 index 00000000000..853b0877b33 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi/ec.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl new file mode 100644 index 00000000000..7d1b0a91168 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi/mainboard.asl @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPEA) +{ + Name (GBUF, ResourceTemplate () + { + }) + Method (_DIS, 0x0, NotSerialized) + { + //Add a dummy disable function + } +} + +Scope (\_SB) { + Device (PWRB) + { + Name(_HID, EisaId("PNP0C0C")) + } +} diff --git a/src/mainboard/intel/minnowmax/acpi/superio.asl b/src/mainboard/intel/minnowmax/acpi/superio.asl new file mode 100644 index 00000000000..853b0877b33 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi/superio.asl @@ -0,0 +1 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c new file mode 100644 index 00000000000..d3b6582ddf9 --- /dev/null +++ b/src/mainboard/intel/minnowmax/acpi_tables.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_fill_gnvs(struct global_nvs *gnvs) +{ + /* Enable USB ports in S3 */ + gnvs->s3u0 = 1; + gnvs->s3u1 = 1; + + /* Disable USB ports in S5 */ + gnvs->s5u0 = 0; + gnvs->s5u1 = 0; + + /* No TPM Present */ + gnvs->tpmp = 0; + + /* Enable DPTF */ + gnvs->dpte = 0; +} + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/intel/minnowmax/board_info.txt b/src/mainboard/intel/minnowmax/board_info.txt new file mode 100644 index 00000000000..5af79f8de4b --- /dev/null +++ b/src/mainboard/intel/minnowmax/board_info.txt @@ -0,0 +1,4 @@ +Category: sbc +ROM protocol: SPI +Flashrom support: y +Release year: 2014 diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout new file mode 100644 index 00000000000..b3cea3cd0fc --- /dev/null +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -0,0 +1,95 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +# Status Register A +# ----------------------------------------------------------------- +# Status Register B +# ----------------------------------------------------------------- +# Status Register C +#96 4 r 0 status_c_rsvd +#100 1 r 0 uf_flag +#101 1 r 0 af_flag +#102 1 r 0 pf_flag +#103 1 r 0 irqf_flag +# ----------------------------------------------------------------- +# Status Register D +#104 7 r 0 status_d_rsvd +#111 1 r 0 valid_cmos_ram +# ----------------------------------------------------------------- +# Diagnostic Status Register +#112 8 r 0 diag_rsvd1 + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory +#120 264 r 0 unused + +# ----------------------------------------------------------------- +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter +#390 2 r 0 unused? + +# ----------------------------------------------------------------- +# coreboot config options: console +#392 3 r 0 unused +395 4 e 6 debug_level +#399 1 r 0 unused + +# coreboot config options: cpu +400 1 e 2 hyper_threading +#401 7 r 0 unused + +# coreboot config options: southbridge +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 2 e 8 use_xhci_over_ehci +#413 3 r 0 unused + +# MRC Scrambler Seed values +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 + +# coreboot config options: check sums +984 16 h 0 check_sum +#1000 24 r 0 amd_reserved + +#save timestamps in pre-ram boot areas +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 EHCI +8 1 XHCI +8 2 Default +# ----------------------------------------------------------------- +checksums + +checksum 392 415 984 diff --git a/src/mainboard/intel/minnowmax/data.vbt b/src/mainboard/intel/minnowmax/data.vbt new file mode 100644 index 00000000000..6b88c70142d Binary files /dev/null and b/src/mainboard/intel/minnowmax/data.vbt differ diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb new file mode 100644 index 00000000000..7c4caf45efa --- /dev/null +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -0,0 +1,80 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/baytrail + # SATA port enable mask (2 ports) + register "sata_port_map" = "0x1" + register "sata_ahci" = "0x1" + register "ide_legacy_combined" = "0x0" + + # Route USB ports to XHCI + register "usb_route_to_xhci" = "1" + + # USB Port Disable Mask + register "usb2_port_disable_mask" = "0x0" + register "usb3_port_disable_mask" = "0x0" + + # USB PHY settings + # TODO: These values are from Baytrail and need tuned for MinnowMax board + register "usb2_comp_bg" = "0x4680" + register "usb2_per_port_lane0" = "0x0004C209" + register "usb2_per_port_rcomp_hs_pullup0" = "0x0300401d" + register "usb2_per_port_lane1" = "0x00049a09" + register "usb2_per_port_rcomp_hs_pullup1" = "0x0300401d" + register "usb2_per_port_lane2" = "0x00049209" + register "usb2_per_port_rcomp_hs_pullup2" = "0x01004015" + register "usb2_per_port_lane3" = "0x0004B209" + register "usb2_per_port_rcomp_hs_pullup3" = "0x0300401d" + + # SD Card controller + register "sdcard_cap_low" = "0x036864b2" + register "sdcard_cap_high" = "0x0" + + # VR PS2 control + register "vnn_ps2_enable" = "1" + register "vcc_ps2_enable" = "1" + + # Allow PCIe devices to wake system from suspend + register "pcie_wake_enable" = "1" + + + # Disable SLP_X stretching after SUS power well fail. + register "disable_slp_x_stretch_sus_fail" = "1" + + device cpu_cluster 0 on end + + device domain 0 on + device pci 00.0 on end # 8086 0F00 - SoC router + device pci 02.0 on end # 8086 0F31 - GFX micro HDMI + device pci 03.0 off end # 8086 0F38 - MIPI + device pci 10.0 off end # 8086 0F14 - EMMC Port + device pci 11.0 off end # 8086 0F15 - SDIO Port + device pci 12.0 on end # 8086 0F16 - SD Port MicroSD on SD3 + device pci 13.0 on end # 8086 0F23 - SATA AHCI Onboard & HSEC + device pci 14.0 on end # 8086 0F35 - USB XHCI - Onboard & HSEC - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime + device pci 15.0 on end # 8086 0F28 - LP Engine Audio LSEC + device pci 17.0 off end # 8086 0F50 - MMC Port + device pci 18.0 on end # 8086 0F40 - SIO - DMA + device pci 18.1 off end # 8086 0F41 - I2C Port 1 (0) + device pci 18.2 on end # 8086 0F42 - I2C Port 2 (1) - (testpoints) + device pci 18.3 off end # 8086 0F43 - I2C Port 3 (2) + device pci 18.4 off end # 8086 0F44 - I2C Port 4 (3) + device pci 18.5 off end # 8086 0F45 - I2C Port 5 (4) + device pci 18.6 on end # 8086 0F46 - I2C Port 6 (5) LSEC + device pci 18.7 on end # 8086 0F47 - I2C Port 7 (6) HSEC + device pci 1a.0 on end # 8086 0F18 - TXE + device pci 1b.0 off end # 8086 0F04 - HD Audio + device pci 1c.0 on end # 8086 0F48 - PCIe Port 1 (0) Must remain on + device pci 1c.1 on end # 8086 0F4A - PCIe Port 2 (1) Onboard GBE (some models) + device pci 1c.2 on end # 8086 0F4C - PCIe Port 3 (2) Onboard GBE + device pci 1c.3 on end # 8086 0F4E - PCIe Port 4 (3) HSEC + device pci 1d.0 on end # 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime + device pci 1e.0 on end # 8086 0F06 - SIO - DMA + device pci 1e.1 on end # 8086 0F08 - PWM 1 LSEC + device pci 1e.2 on end # 8086 0F09 - PWM 2 LSEC + device pci 1e.3 on end # 8086 0F0A - HSUART 1 LSEC + device pci 1e.4 on end # 8086 0F0C - HSUART 2 LSEC + device pci 1e.5 on end # 8086 0F0E - SPI LSEC + device pci 1f.0 on end # 8086 0F1C - LPC bridge No connector + device pci 1f.3 on end # 8086 0F12 - SMBus 0 SPC + end +end diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl new file mode 100644 index 00000000000..09db35910de --- /dev/null +++ b/src/mainboard/intel/minnowmax/dsdt.asl @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define INCLUDE_LPE 1 +#define INCLUDE_SCC 1 +#define INCLUDE_EHCI 1 +#define INCLUDE_XHCI 1 +#define INCLUDE_LPSS 1 + + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 and up + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + // Some generic macros + #include + + // global NVS and variables + #include + + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + } + } + + /* Chipset specific sleep states */ + #include + + #include "acpi/mainboard.asl" +} diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c new file mode 100644 index 00000000000..15c114129c8 --- /dev/null +++ b/src/mainboard/intel/minnowmax/gpio.c @@ -0,0 +1,218 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include "irqroute.h" + +/* + * For multiplexed functions, look in EDS: + * 10.3 Ball Name and Function by Location + * + * The pads list is in the BWG_VOL2 Rev1p2: + * Note that Pad # is not the same as GPIO# + * 37 GPIO Handling: + * Table 37-1. SCORE Pads List + * Table 37-2. SSUSORE Pads List + */ + +/* NCORE GPIOs */ +static const struct soc_gpio_map gpncore_gpio_map[] = { + GPIO_FUNC2, // GPIO_S0_NC[00] - HDMI_HPD + GPIO_FUNC2, // GPIO_S0_NC[01] - HDMI_DDCDAT + GPIO_FUNC2, // GPIO_S0_NC[02] - HDMI_DDCCLK + GPIO_NC, // GPIO_S0_NC[03] - No Connect + GPIO_NC, // GPIO_S0_NC[04] - No Connect + GPIO_NC, // GPIO_S0_NC[05] - No Connect + GPIO_NC, // GPIO_S0_NC[06] - No Connect + GPIO_FUNC2, // GPIO_S0_NC[07] - DDI1_DDCDAT + GPIO_NC, // GPIO_S0_NC[08] - No Connect + GPIO_NC, // GPIO_S0_NC[09] - No Connect + GPIO_NC, // GPIO_S0_NC[10] - No Connect + GPIO_NC, // GPIO_S0_NC[11] - No Connect + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_NC[12] - TP15 + GPIO_NC, // GPIO_S0_NC[13] - No Connect + GPIO_NC, // GPIO_S0_NC[14] - No Connect + GPIO_NC, // GPIO_S0_NC[15] - No Connect + GPIO_NC, // GPIO_S0_NC[16] - No Connect + GPIO_NC, // GPIO_S0_NC[17] - No Connect + GPIO_NC, // GPIO_S0_NC[18] - No Connect + GPIO_NC, // GPIO_S0_NC[19] - No Connect + GPIO_NC, // GPIO_S0_NC[20] - No Connect + GPIO_NC, // GPIO_S0_NC[21] - No Connect + GPIO_NC, // GPIO_S0_NC[22] - No Connect + GPIO_NC, // GPIO_S0_NC[23] - No Connect + GPIO_NC, // GPIO_S0_NC[24] - No Connect + GPIO_NC, // GPIO_S0_NC[25] - No Connect + GPIO_NC, // GPIO_S0_NC[26] - No Connect + GPIO_END +}; + +/* SCORE GPIOs (GPIO_S0_SC_XX) */ +static const struct soc_gpio_map gpscore_gpio_map[] = { + GPIO_FUNC1, // GPIO_S0_SC[000] - SATA_GP0 + GPIO_FUNC1, // GPIO_S0_SC[001] - SATA_GP1 + GPIO_FUNC1, // GPIO_S0_SC[002] - SATA_LED_B + GPIO_FUNC1, // GPIO_S0_SC[003] - PCIE_CLKREQ_0 + GPIO_FUNC1, // GPIO_S0_SC[004] - PCIE_CLKREQ_1 + GPIO_FUNC1, // GPIO_S0_SC[005] - PCIE_CLKREQ_2 + GPIO_FUNC1, // GPIO_S0_SC[006] - PCIE_CLKREQ_3 + GPIO_FUNC2, // GPIO_S0_SC[007] - SD3_WP + GPIO_NC, // GPIO_S0_SC[008] - No Connect + GPIO_NC, // GPIO_S0_SC[009] - No Connect + GPIO_NC, // GPIO_S0_SC[010] - No Connect + GPIO_NC, // GPIO_S0_SC[011] - No Connect + GPIO_NC, // GPIO_S0_SC[012] - No Connect + GPIO_NC, // GPIO_S0_SC[013] - No Connect + GPIO_NC, // GPIO_S0_SC[014] - No Connect + GPIO_NC, // GPIO_S0_SC[015] - No Connect + GPIO_NC, // GPIO_S0_SC[016] - No Connect + GPIO_NC, // GPIO_S0_SC[017] - No Connect + GPIO_NC, // GPIO_S0_SC[018] - No Connect + GPIO_NC, // GPIO_S0_SC[019] - No Connect + GPIO_NC, // GPIO_S0_SC[020] - No Connect + GPIO_NC, // GPIO_S0_SC[021] - No Connect + GPIO_NC, // GPIO_S0_SC[022] - No Connect + GPIO_NC, // GPIO_S0_SC[023] - No Connect + GPIO_NC, // GPIO_S0_SC[024] - No Connect + GPIO_NC, // GPIO_S0_SC[025] - No Connect + GPIO_NC, // GPIO_S0_SC[026] - No Connect + GPIO_NC, // GPIO_S0_SC[027] - No Connect + GPIO_NC, // GPIO_S0_SC[028] - No Connect + GPIO_NC, // GPIO_S0_SC[029] - No Connect + GPIO_NC, // GPIO_S0_SC[030] - No Connect + GPIO_NC, // GPIO_S0_SC[031] - No Connect + GPIO_NC, // GPIO_S0_SC[032] - No Connect + GPIO_FUNC1, // GPIO_S0_SC[033] - SD3_CLK + GPIO_FUNC1, // GPIO_S0_SC[034] - SD3_D0 + GPIO_FUNC1, // GPIO_S0_SC[035] - SD3_D1 + GPIO_FUNC1, // GPIO_S0_SC[036] - SD3_D2 + GPIO_FUNC1, // GPIO_S0_SC[037] - SD3_D3 + GPIO_FUNC1, // GPIO_S0_SC[038] - SD3_CD# + GPIO_FUNC1, // GPIO_S0_SC[039] - SD3_CMD + GPIO_FUNC1, // GPIO_S0_SC[040] - TP12 (SD3_1P8EN) + GPIO_FUNC1, // GPIO_S0_SC[041] - TP11 (/SD3_PWREN) + GPIO_NC, // GPIO_S0_SC[042] - No Connect + GPIO_NC, // GPIO_S0_SC[043] - No Connect + GPIO_NC, // GPIO_S0_SC[044] - No Connect + GPIO_NC, // GPIO_S0_SC[045] - No Connect + GPIO_NC, // GPIO_S0_SC[046] - No Connect + GPIO_NC, // GPIO_S0_SC[047] - No Connect + GPIO_NC, // GPIO_S0_SC[048] - No Connect + GPIO_NC, // GPIO_S0_SC[049] - No Connect + GPIO_NC, // GPIO_S0_SC[050] - No Connect + GPIO_FUNC1, // GPIO_S0_SC[051] - PCU_SMB_DATA + GPIO_FUNC1, // GPIO_S0_SC[052] - PCU_SMB_CLK + GPIO_FUNC1, // GPIO_S0_SC[053] - PCU_SMB_ALERT + GPIO_FUNC1, // GPIO_S0_SC[054] - ILB_8254_SPKR + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55) + GPIO_FUNC0, // GPIO_S0_SC[056] - GPIO_S0_SC_56 + GPIO_FUNC1, // GPIO_S0_SC[057] - PCU_UART3_TXD + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58) + GPIO_FUNC0, // GPIO_S0_SC[059] - HDMI_DCDC_ENB + GPIO_FUNC0, // GPIO_S0_SC[060] - HDMI_LDSW_ENB + GPIO_FUNC1, // GPIO_S0_SC[061] - PCU_UART3_RXD + GPIO_FUNC1, // GPIO_S0_SC[062] - LPE_I2S_CLK + GPIO_FUNC1, // GPIO_S0_SC[063] - LPE_I2S_FRM + GPIO_FUNC1, // GPIO_S0_SC[064] - LPE_I2S_DATIN + GPIO_FUNC1, // GPIO_S0_SC[065] - LPE_I2S_DATOUT + GPIO_FUNC1, // GPIO_S0_SC[066] - SOC_SIO_SPI_CS1 + GPIO_FUNC1, // GPIO_S0_SC[067] - SOC_SIO_SPI_MISO + GPIO_FUNC1, // GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI + GPIO_FUNC1, // GPIO_S0_SC[069] - SOC_SIO_SPI_CLK + GPIO_FUNC1, // GPIO_S0_SC[070] - SIO_UART1_RXD + GPIO_FUNC1, // GPIO_S0_SC[071] - SIO_UART1_TXD + GPIO_FUNC1, // GPIO_S0_SC[072] - SIO_UART1_RTSB + GPIO_FUNC1, // GPIO_S0_SC[073] - SIO_UART1_CTSB + GPIO_FUNC1, // GPIO_S0_SC[074] - SIO_UART2_RXD + GPIO_FUNC1, // GPIO_S0_SC[075] - SIO_UART2_TXD + GPIO_NC, // GPIO_S0_SC[076] - No Connect + GPIO_NC, // GPIO_S0_SC[077] - No Connect + GPIO_NC, // GPIO_S0_SC[078] - No Connect + GPIO_NC, // GPIO_S0_SC[079] - No Connect + GPIO_FUNC1, // GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA) + GPIO_FUNC1, // GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL) + GPIO_NC, // GPIO_S0_SC[082] - No Connect + GPIO_NC, // GPIO_S0_SC[083] - No Connect + GPIO_NC, // GPIO_S0_SC[084] - No Connect + GPIO_NC, // GPIO_S0_SC[085] - No Connect + GPIO_NC, // GPIO_S0_SC[086] - No Connect + GPIO_NC, // GPIO_S0_SC[087] - No Connect + GPIO_FUNC1, // GPIO_S0_SC[088] - LSS_I2C_SDA + GPIO_FUNC1, // GPIO_S0_SC[089] - LSS_I2C_SCL + GPIO_FUNC1, // GPIO_S0_SC[090] - EXP_I2C_SDA + GPIO_FUNC1, // GPIO_S0_SC[091] - EXP_I2C_SCL + GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[092] - TP13 + GPIO_FUNC(1, PULL_UP, 20K), // GPIO_S0_SC[093] - TP16 + GPIO_FUNC1, // GPIO_S0_SC[094] - SOC_PWM0 + GPIO_FUNC1, // GPIO_S0_SC[095] - SOC_PWM1 + GPIO_NC, // GPIO_S0_SC[096] - No Connect + GPIO_NC, // GPIO_S0_SC[097] - No Connect + GPIO_NC, // GPIO_S0_SC[098] - No Connect + GPIO_NC, // GPIO_S0_SC[099] - No Connect + GPIO_NC, // GPIO_S0_SC[100] - No Connect + GPIO_NC, // GPIO_S0_SC[101] - No Connect + GPIO_END +}; + +/* SSUS GPIOs (GPIO_S5) */ +static const struct soc_gpio_map gpssus_gpio_map[] = { + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[00] - SOC_GPIO_S5_0 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[01] - SOC_GPIO_S5_1 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[02] - SOC_GPIO_S5_2 + GPIO_FUNC6, // GPIO_S5[03] - mPCIE_WAKEB + GPIO_NC, // GPIO_S5[04] - No Connect + GPIO_INPUT, // GPIO_S5[05] - BOM_OP1 + // Memory: 0=1GB 1=2GB or 4GB + GPIO_INPUT, // GPIO_S5[06] - BOM_OP2 + GPIO_INPUT, // GPIO_S5[07] - BOM_OP3 + GPIO_OUT_HIGH_LEGACY, // GPIO_S5[08] - SOC_USB_HOST_EN0 + GPIO_OUT_HIGH_LEGACY, // GPIO_S5[09] - SOC_USB_HOST_EN1 + GPIO_OUT_HIGH_LEGACY, // GPIO_S5[10] - GPIO_S5_10_UNLOCK + GPIO_FUNC0, // GPIO_S5[11] - SUSPWRDNACK (TP14) + GPIO_FUNC0, // GPIO_S5[12] - PMC_SUSCLK0 + GPIO_FUNC1, // GPIO_S5[13] - PMC_SLP_S0IX (TP10) + GPIO_FUNC1, // GPIO_S5[14] - GPIO_S514_J20 + GPIO_FUNC0, // GPIO_S5[15] - PMC_PCIE_WAKE_R + GPIO_FUNC0, // GPIO_S5[16] - PMC_PWRBTN + GPIO_NC, // GPIO_S5[17] - No Connect + GPIO_FUNC1, // GPIO_S5[18] - LPCPD_L (TP7) + GPIO_FUNC0, // GPIO_S5[19] - SOC_USB_HOST_OC0 + GPIO_FUNC0, // GPIO_S5[20] - SOC_USB_HOST_OC1 + GPIO_FUNC0, // GPIO_S5[21] - SOC_SPI_CS1B + GPIO_INPUT_PD, // GPIO_S5[22] - NC or LED D2 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[23] - XDP_H_OBSDATA_A0 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[24] - XDP_H_OBSDATA_A1 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[25] - XDP_H_OBSDATA_A2 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[26] - XDP_H_OBSDATA_A3 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[27] - EXP_GPIO1 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[28] - EXP_GPIO2 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[29] - EXP_GPIO3 + GPIO_FUNC(0, PULL_UP, 20K), // GPIO_S5[30] - EXP_GPIO4 + GPIO_NC, // GPIO_S5[31] - No Connect + GPIO_NC, // GPIO_S5[32] - No Connect + GPIO_NC, // GPIO_S5[33] - No Connect + GPIO_NC, // GPIO_S5[34] - No Connect + GPIO_NC, // GPIO_S5[35] - No Connect + GPIO_NC, // GPIO_S5[36] - No Connect + GPIO_NC, // GPIO_S5[37] - No Connect + GPIO_NC, // GPIO_S5[38] - No Connect + GPIO_NC, // GPIO_S5[39] - No Connect + GPIO_NC, // GPIO_S5[40] - No Connect + GPIO_NC, // GPIO_S5[41] - No Connect + GPIO_NC, // GPIO_S5[42] - No Connect + GPIO_NC, // GPIO_S5[43] - No Connect + GPIO_END +}; + +static struct soc_gpio_config gpio_config = { + .ncore = gpncore_gpio_map, + .score = gpscore_gpio_map, + .ssus = gpssus_gpio_map, + .core_dirq = NULL, + .sus_dirq = NULL, +}; + +struct soc_gpio_config *mainboard_get_gpios(void) +{ + return &gpio_config; +} diff --git a/src/mainboard/intel/minnowmax/irqroute.c b/src/mainboard/intel/minnowmax/irqroute.c new file mode 100644 index 00000000000..6fa036672e6 --- /dev/null +++ b/src/mainboard/intel/minnowmax/irqroute.c @@ -0,0 +1,5 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "irqroute.h" + +DEFINE_IRQ_ROUTES; diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h new file mode 100644 index 00000000000..9739f6f620c --- /dev/null +++ b/src/mainboard/intel/minnowmax/irqroute.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* + *IR02h GFX INT(A) - PIRQ A + *IR10h EMMC INT(ABCD) - PIRQ DEFG + *IR11h SDIO INT(A) - PIRQ B + *IR12h SD INT(A) - PIRQ C + *IR13h SATA INT(A) - PIRQ D + *IR14h XHCI INT(A) - PIRQ E + *IR15h LP Audio INT(A) - PIRQ F + *IR17h MMC INT(A) - PIRQ F + *IR18h SIO INT(ABCD) - PIRQ BADC + *IR1Ah TXE INT(A) - PIRQ F + *IR1Bh HD Audio INT(A) - PIRQ G + *IR1Ch PCIe INT(ABCD) - PIRQ EFGH + *IR1Dh EHCI INT(A) - PIRQ D + *IR1Eh SIO INT(ABCD) - PIRQ BDEF + *IR1Fh LPC INT(ABCD) - PIRQ HGBC + */ + +/* Devices set as A, A, A, A evaluate as 0, and don't get set */ +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, B), \ + PCI_DEV_PIRQ_ROUTE(MMC_DEV, D, E, F, G), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, B, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, C, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, E, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, B, A, D, C), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, F, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, G, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, E, F, G, H), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, D, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, B, D, E, F), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, H, G, B, C) + +/* + * Route each PIRQ[A-H] to a PIC IRQ[0-15] + * Reserved: 0, 1, 2, 8, 13 + * PS2 keyboard: 12 + * ACPI/SCI: 9 + * Floppy: 6 + */ +#define PIRQ_PIC_ROUTES \ + PIRQ_PIC(A, 3), \ + PIRQ_PIC(B, 5), \ + PIRQ_PIC(C, 7), \ + PIRQ_PIC(D, 10), \ + PIRQ_PIC(E, 11), \ + PIRQ_PIC(F, 12), \ + PIRQ_PIC(G, 14), \ + PIRQ_PIC(H, 15) diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c new file mode 100644 index 00000000000..e87b3bba78f --- /dev/null +++ b/src/mainboard/intel/minnowmax/mainboard.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +/* + * mainboard_enable is executed as first thing after enumerate_buses(). + * This is the earliest point to add customization. + */ +static void mainboard_enable(struct device *dev) +{ +} + +/* + * mainboard_final is executed as one of the last items before loading the + * payload. + * + * This is the latest point to add customization. + */ +static void mainboard_final(void *chip_info) +{ +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .final = mainboard_final, +}; diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c new file mode 100644 index 00000000000..fd82d6f21ea --- /dev/null +++ b/src/mainboard/intel/minnowmax/romstage.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include + +void mainboard_fill_mrc_params(struct mrc_params *mp) +{ + uint8_t *spd_file; + void *spd_content; + size_t spd_fsize; + u8 gpio34 = 0; + u8 is_1333_sku; + + /* + * The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. There's + * no good way of knowing the SKU'ing so frequency is used as a proxy. + * The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the + * E3827 and E3845 are 1750MHz and 1910MHz, respectively. + */ + is_1333_sku = !!(tsc_freq_mhz() >= 1700); + + printk(BIOS_INFO, "Using %d MHz DDR3 settings.\n", + is_1333_sku ? 1333 : 1066); + + /* + * Minnow Max Board + * Read SSUS gpio 5 (34) to determine memory type + * 0 : 1GB SKU uses 2Gb density memory + * 1 : 2GB SKU uses 4Gb density memory + * + * devicetree.cb assumes 1GB SKU board + */ + setup_ssus_gpio(34, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT); + + gpio34 = ssus_get_gpio(34); + if (gpio34) + printk(BIOS_NOTICE, "%s GB Minnowboard Max detected.\n", + gpio34 ? "2 / 4" : "1"); + + spd_file = (uint8_t *)cbfs_map("spd.bin", &spd_fsize); + if (!spd_file) + die("SPD data not found."); + + spd_content = &spd_file[CONFIG_DIMM_SPD_SIZE * gpio34]; + + mp->mainboard.dram_type = DRAM_DDR3L; + mp->mainboard.dram_info_location = DRAM_INFO_SPD_MEM, + mp->txe_size_mb = 16; + + mp->mainboard.dram_data[0] = spd_content; + mp->mainboard.dram_data[1] = NULL; +} diff --git a/src/mainboard/intel/minnowmax/spd/micron_1GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/intel/minnowmax/spd/micron_1GiB_dimm_MT41K256M16HA-125.spd.hex new file mode 100644 index 00000000000..59e5c5635de --- /dev/null +++ b/src/mainboard/intel/minnowmax/spd/micron_1GiB_dimm_MT41K256M16HA-125.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 02 19 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 86 +20 08 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 aa 49 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 36 45 +31 20 45 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex b/src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex new file mode 100644 index 00000000000..f3bcb56245c --- /dev/null +++ b/src/mainboard/intel/minnowmax/spd/micron_2GiB_dimm_MT41K256M16HA-125.spd.hex @@ -0,0 +1,32 @@ +92 11 0b 03 04 19 02 02 +03 11 01 08 0a 00 fe 00 +69 78 69 3c 69 11 18 86 +20 08 3c 3c 01 40 83 05 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 0f 01 02 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 80 2c 00 +00 00 00 00 00 00 19 d2 +34 4b 54 46 32 35 36 36 +34 48 5a 2d 31 47 36 45 +31 20 45 31 80 2c 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff +ff ff ff ff ff ff ff ff diff --git a/src/mainboard/lenovo/m900_tiny/Kconfig b/src/mainboard/lenovo/m900_tiny/Kconfig index 8ad36e0014a..334957514b0 100644 --- a/src/mainboard/lenovo/m900_tiny/Kconfig +++ b/src/mainboard/lenovo/m900_tiny/Kconfig @@ -38,4 +38,15 @@ config PRERAM_CBMEM_CONSOLE_SIZE config DIMM_SPD_SIZE default 512 #DDR4 +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_VBNV_FLASH + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT + endif diff --git a/src/mainboard/lenovo/m900_tiny/Makefile.mk b/src/mainboard/lenovo/m900_tiny/Makefile.mk index 44db0910ed2..072d9ed81f3 100644 --- a/src/mainboard/lenovo/m900_tiny/Makefile.mk +++ b/src/mainboard/lenovo/m900_tiny/Makefile.mk @@ -10,4 +10,5 @@ romstage-y += romstage.c ramstage-y += gpio.c ramstage-y += hda_verb.c ramstage-y += ramstage.c +ramstage-y += cfr.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/m900_tiny/cfr.c b/src/mainboard/lenovo/m900_tiny/cfr.c new file mode 100644 index 00000000000..9cd0163853a --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/cfr.c @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +struct sm_object wifi_slot_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "wifi_slot_enable", + .ui_name = "Enable Wi-Fi card slot", + .ui_helptext = "Enable or disable detection of devices in the Wi-Fi card slot", + .default_value = true, +}); + +struct sm_object ssd_slot_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "ssd_slot_enable", + .ui_name = "Enable SSD slot", + .ui_helptext = "Enable or disable detection of devices in the SSD slot", + .default_value = true, +}); + +struct sm_object hdd_slot_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "hdd_slot_enable", + .ui_name = "Enable 2.5 inch disk slot", + .ui_helptext = "Enable or disable detection of devices in the 2.5 inch disk slot", + .default_value = true, +}); + +static struct sm_obj_form devices = { + .ui_name = "Devices", + .obj_list = (const struct sm_object *[]) { + &wifi_slot_enable, + &ssd_slot_enable, + &hdd_slot_enable, + NULL + }, +}; + +static struct sm_obj_form security = { + .ui_name = "Security", + .obj_list = (const struct sm_object *[]) { + &lock_bios, + &smm_bwp, + NULL + }, +}; + +static struct sm_obj_form chipset = { + .ui_name = "Chipset", + .obj_list = (const struct sm_object *[]) { + &me_mode, + &ps2_enable, + &power_on_after_fail, + NULL + }, +}; + +static struct sm_obj_form processor = { + .ui_name = "Processor", + .obj_list = (const struct sm_object *[]) { + &hyper_threading, + &throttle_offset, + &throttle_temp, + NULL + }, +}; + +static struct sm_obj_form bootloader = { + .ui_name = "Bootloader", + .obj_list = (const struct sm_object *[]) { + &network_boot, + &uefi_usb_stack, + &uefi_usb_msc, + &com0_redirection, + NULL + }, +}; + +static struct sm_obj_form *sm_root[] = { + &security, + &processor, + &chipset, + &devices, + &bootloader, + NULL +}; + +void mb_cfr_setup_menu(struct lb_cfr *cfr_root) +{ + cfr_write_setup_menu(cfr_root, sm_root); +} diff --git a/src/mainboard/lenovo/m900_tiny/ramstage.c b/src/mainboard/lenovo/m900_tiny/ramstage.c index 6e66f3a7cc7..d2392cc1faf 100644 --- a/src/mainboard/lenovo/m900_tiny/ramstage.c +++ b/src/mainboard/lenovo/m900_tiny/ramstage.c @@ -2,10 +2,14 @@ #include #include +#include #include #include #include +#include #include +#include +#include static void print_board_id(void) { @@ -32,22 +36,45 @@ static void print_board_id(void) } printk(BIOS_INFO, "Serial header %spopulated\n", !gpio_get(GPP_A22) ? "" : "un"); - printk(BIOS_INFO, "PS/2 header %spopulated\n", !gpio_get(GPP_D14) ? "" : "un"); - printk(BIOS_INFO, "USB header %spopulated\n", !gpio_get(GPP_C19) ? "" : "un"); - printk(BIOS_INFO, "DisplayPort header %spopulated\n", !gpio_get(GPP_B15) ? "" : "un"); - printk(BIOS_INFO, "PCIe / SATA header %spopulated\n", !gpio_get(GPP_B21) ? "" : "un"); } -static void mainboard_enable(struct device *dev) +static void devtree_update(void) +{ + config_t *cfg = config_of_soc(); + struct device *wifi_dev = DEV_PTR(pcie_rp7); + struct device *ssd_dev = DEV_PTR(pcie_rp17); + struct device *ps2_dev = dev_find_slot_pnp(0x2e, NCT6687D_KBC); + + if (get_uint_option("wifi_slot_enable", 1) == 0) { + cfg->usb2_ports[8].enable = 0; + wifi_dev->enabled = 0; + } + + if (get_uint_option("ssd_slot_enable", 1) == 0) { + cfg->SataPortsEnable[4] = 0; + ssd_dev->enabled = 0; + } + + if (get_uint_option("hdd_slot_enable", 1) == 0) { + cfg->SataPortsEnable[0] = 0; + cfg->SataPortsEnable[1] = 0; + } + + if (get_uint_option("ps2_enable", 1) == 0) + ps2_dev->enabled = 0; +} + +static void mainboard_init(void *chip_info) { mainboard_configure_gpios(); + devtree_update(); print_board_id(); } struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .init = mainboard_init, }; diff --git a/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd new file mode 100644 index 00000000000..40855e7c010 --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/vboot-ro.fmd @@ -0,0 +1,30 @@ +FLASH 16M { + SI_ALL 8M { + SI_DESC 4K + SI_GBE 8K + SI_ME + } + SI_BIOS 8M { + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + } + + WP_RO { + FMAP 2K + RO_FRID 128 + RO_PADDING 1920 + GBB 120K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd new file mode 100644 index 00000000000..df3bfdb417b --- /dev/null +++ b/src/mainboard/lenovo/m900_tiny/vboot-rwa.fmd @@ -0,0 +1,36 @@ +FLASH 16M { + SI_ALL 8M { + SI_DESC 4K + SI_GBE 8K + SI_ME + } + SI_BIOS 8M { + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + } + + RW_SECTION_A 3M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 128 + } + + WP_RO 3M { + FMAP 2K + RO_FRID 128 + RO_PADDING 1920 + GBB 120K + COREBOOT(CBFS) + } + } +} diff --git a/src/mainboard/msi/Kconfig b/src/mainboard/msi/Kconfig index 25350426f73..b229a9fc05e 100644 --- a/src/mainboard/msi/Kconfig +++ b/src/mainboard/msi/Kconfig @@ -14,4 +14,23 @@ source "src/mainboard/msi/*/Kconfig" config MAINBOARD_VENDOR default "MSI" +config BOARD_HAS_MSI_ROMHOLE + bool + default n + +config MSI_ROMHOLE_IN_CBFS + bool "Put the MSI ROMHOLE as CBFS file" + depends on BOARD_HAS_MSI_ROMHOLE && !VBOOT + default n + +config MSI_ROMHOLE_ADDRESS_IN_CBFS + hex "MSI ROMHOLE address in CBFS" + depends on MSI_ROMHOLE_IN_CBFS + default 0xff7c0000 if BOARD_ROMSIZE_KB_32768 + +config MSI_ROMHOLE_SIZE_IN_CBFS + hex "MSI ROMHOLE size in CBFS" + depends on MSI_ROMHOLE_IN_CBFS + default 0x20000 + endif # VENDOR_MSI diff --git a/src/mainboard/msi/ms7d25/Kconfig b/src/mainboard/msi/ms7d25/Kconfig index 1b23f0354a8..1b6e1445f11 100644 --- a/src/mainboard/msi/ms7d25/Kconfig +++ b/src/mainboard/msi/ms7d25/Kconfig @@ -9,6 +9,7 @@ config BOARD_MSI_Z690_A_PRO_WIFI_DDR5 config BOARD_MSI_MS7D25 def_bool n select SOC_INTEL_ALDERLAKE_PCH_S + select SOC_INTEL_RAPTORLAKE select BOARD_ROMSIZE_KB_32768 select SOC_INTEL_COMMON_BLOCK_HDA_VERB select SUPERIO_NUVOTON_NCT6687D @@ -19,7 +20,7 @@ config BOARD_MSI_MS7D25 select MEMORY_MAPPED_TPM select CRB_TPM select HAVE_INTEL_PTT - select USE_LEGACY_8254_TIMER + select BOARD_HAS_MSI_ROMHOLE if BOARD_MSI_MS7D25 @@ -31,27 +32,24 @@ config MAINBOARD_PART_NUMBER default "PRO Z690-A WIFI (MS-7D25)" if BOARD_MSI_Z690_A_PRO_WIFI_DDR5 config MAINBOARD_VENDOR - string default "Micro-Star International Co., Ltd." config MAINBOARD_FAMILY - string default "Default string" config MAINBOARD_VERSION - string default "2.0" if BOARD_MSI_Z690_A_PRO_WIFI_DDR5 config UART_FOR_CONSOLE - int default 0 config USE_PM_ACPI_TIMER - bool default n +config USE_LEGACY_8254_TIMER + default y + config CBFS_SIZE - hex default 0x1000000 config TPM_PIRQ @@ -65,18 +63,35 @@ config VBOOT select VBOOT_ALWAYS_ENABLE_DISPLAY select VBOOT_NO_BOARD_SUPPORT select HAS_RECOVERY_MRC_CACHE + select VBOOT_NO_TPM + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE config VBOOT_SLOTS_RW_AB default y if VBOOT +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + config FMDFILE - string default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT && VBOOT_SLOTS_RW_AB # gen_test_hwid.sh script doesn't like parentheses in the MAINBOARD_PART_NUMBER # Override the GBB_HWID config GBB_HWID - string default "MSI_MS7D25" +if !VBOOT && MSI_ROMHOLE_IN_CBFS + +# FIXME: Make coreboot build system automatically fixup the ucode and FIT location +# so that creating FIT does not fail. +config CPU_MICROCODE_CBFS_LOC + hex + default 0xff800000 + +config INTEL_FIT_LOC + hex + default 0xfffc0000 + +endif + endif diff --git a/src/mainboard/msi/ms7d25/Makefile.mk b/src/mainboard/msi/ms7d25/Makefile.mk index deb5ff625a6..6b9791768ac 100644 --- a/src/mainboard/msi/ms7d25/Makefile.mk +++ b/src/mainboard/msi/ms7d25/Makefile.mk @@ -1,10 +1,32 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += bootblock.c +$(call src-to-obj,bootblock,$(dir)/msi_id.S): $(obj)/fmap_config.h +bootblock-y += msi_id.S romstage-y += romstage_fsp_params.c ramstage-y += mainboard.c +ramstage-y += smbios.c all-y += die.c smm-y += die.c + +ifeq ($(CONFIG_MSI_ROMHOLE_IN_CBFS),y) + +$(obj)/mainboard/$(MAINBOARDDIR)/bpa.bin: + dd if=/dev/zero of=$@ bs=64K count=1 + +cbfs-files-y += bpa.bin + +bpa.bin-file := $(obj)/mainboard/$(MAINBOARDDIR)/bpa.bin +bpa.bin-type := raw +bpa.bin-compression := none +bpa.bin-position := 0xff080000 # Fixed position from original MSI firmware + +# Workaround: place build_info exactly at the EXT_BIOS_WINDOW boundary (plus +# the metadata size) to avoid files getting fragmented between +# FIXED_BIOS_WINDOW and EXT_BIOS_WINDOW. +build_info-COREBOOT-position := 0xff000040 + +endif diff --git a/src/mainboard/msi/ms7d25/acpi/mainboard.asl b/src/mainboard/msi/ms7d25/acpi/mainboard.asl new file mode 100644 index 00000000000..dd64d794bc5 --- /dev/null +++ b/src/mainboard/msi/ms7d25/acpi/mainboard.asl @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +Scope (_GPE) { + /* Empty PCI_EXP_STS handler */ + Method (_L69, 0, Serialized) { } +} + +Scope (\_SB.PCI0) { + /* This device triggers automatic drivers and MSI utilities installation on Windows */ + Device (MSIV) { + Name (_HID, "MBID0001") + Name (_UID, One) + Method (_STA, 0, NotSerialized){ + Return (One) + } + } +} diff --git a/src/mainboard/msi/ms7d25/bootblock.c b/src/mainboard/msi/ms7d25/bootblock.c index 110d6828a61..1b192eb8d10 100644 --- a/src/mainboard/msi/ms7d25/bootblock.c +++ b/src/mainboard/msi/ms7d25/bootblock.c @@ -4,42 +4,75 @@ #include #include #include +#include +#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7) #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) #define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) +#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART) +#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC) + +#define EC_IO_BASE 0xa20 void bootblock_mainboard_early_init(void) { /* Replicate vendor settings for multi-function pins in global config LDN */ - nuvoton_pnp_enter_conf_state(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low - pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + nuvoton_pnp_enter_conf_state(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low + pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low /* Below are multi-pin function */ - pnp_write_config(SERIAL_DEV, 0x15, 0xaa); - pnp_write_config(SERIAL_DEV, 0x1a, 0x02); - pnp_write_config(SERIAL_DEV, 0x1b, 0x02); - pnp_write_config(SERIAL_DEV, 0x1d, 0x00); - pnp_write_config(SERIAL_DEV, 0x1e, 0xaa); - pnp_write_config(SERIAL_DEV, 0x1f, 0xb2); - pnp_write_config(SERIAL_DEV, 0x22, 0xbd); - pnp_write_config(SERIAL_DEV, 0x23, 0xdf); - pnp_write_config(SERIAL_DEV, 0x24, 0x39); - pnp_write_config(SERIAL_DEV, 0x25, 0xfe); - pnp_write_config(SERIAL_DEV, 0x26, 0x40); - pnp_write_config(SERIAL_DEV, 0x27, 0x77); - pnp_write_config(SERIAL_DEV, 0x28, 0x00); - pnp_write_config(SERIAL_DEV, 0x29, 0xfb); - pnp_write_config(SERIAL_DEV, 0x2a, 0x80); - pnp_write_config(SERIAL_DEV, 0x2b, 0x20); - pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); - pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); + pnp_write_config(GPIO_DEV, 0x15, 0xaa); + pnp_write_config(GPIO_DEV, 0x1a, 0x02); + pnp_write_config(GPIO_DEV, 0x1b, 0x02); + pnp_write_config(GPIO_DEV, 0x1d, 0x00); + pnp_write_config(GPIO_DEV, 0x1e, 0xaa); + pnp_write_config(GPIO_DEV, 0x1f, 0xb2); + pnp_write_config(GPIO_DEV, 0x22, 0xbd); + pnp_write_config(GPIO_DEV, 0x23, 0xdf); + pnp_write_config(GPIO_DEV, 0x24, 0x39); + pnp_write_config(GPIO_DEV, 0x25, 0xfe); + pnp_write_config(GPIO_DEV, 0x26, 0x40); + pnp_write_config(GPIO_DEV, 0x27, 0x77); + pnp_write_config(GPIO_DEV, 0x28, 0x00); + pnp_write_config(GPIO_DEV, 0x29, 0xfb); + pnp_write_config(GPIO_DEV, 0x2a, 0x80); + pnp_write_config(GPIO_DEV, 0x2b, 0x20); + pnp_write_config(GPIO_DEV, 0x2c, 0x8a); + pnp_write_config(GPIO_DEV, 0x2d, 0xaa); + + /* Set GPIO 06 as high output */ + pnp_write_config(GPIO_DEV, 0xF0, 0x00); + pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40); + pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00); pnp_set_logical_device(POWER_DEV); /* Configure pin for PECI */ pnp_write_config(POWER_DEV, 0xf3, 0x80); - nuvoton_pnp_exit_conf_state(POWER_DEV); + /* Configure power fault detection */ + pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30); + pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01); + + /* Configure yellow and green LED */ + pnp_write_config(POWER_DEV, 0xe7, 0x88); + pnp_write_config(POWER_DEV, 0xe8, 0x07); + pnp_set_logical_device(P80_UART_DEV); + pnp_write_config(P80_UART_DEV, 0xe5, 0x0f); + + /* Configure EC */ + pnp_set_logical_device(EC_DEV); + pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE); + pnp_set_enable(EC_DEV, 1); + + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0); + nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03); + nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04); + + nuvoton_pnp_exit_conf_state(EC_DEV); if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms7d25/data.vbt b/src/mainboard/msi/ms7d25/data.vbt index b9085691568..ee8e76953dd 100644 Binary files a/src/mainboard/msi/ms7d25/data.vbt and b/src/mainboard/msi/ms7d25/data.vbt differ diff --git a/src/mainboard/msi/ms7d25/devicetree.cb b/src/mainboard/msi/ms7d25/devicetree.cb index 73d871d3462..6ecd69691e2 100644 --- a/src/mainboard/msi/ms7d25/devicetree.cb +++ b/src/mainboard/msi/ms7d25/devicetree.cb @@ -2,6 +2,7 @@ chip soc/intel/alderlake # FSP configuration register "eist_enable" = "true" + register "enable_hwp_scalability_tracking" = "true" # Sagv Configuration register "sagv" = "SaGv_Enabled" @@ -12,76 +13,6 @@ chip soc/intel/alderlake register "pmc_gpe0_dw1" = "GPP_VPGIO" register "pmc_gpe0_dw2" = "GPD" - # USB Configuration - register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1 - register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT - register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1 - register "usb2_ports[3]" = "USB2_PORT_LONG(OC0)" # JUSB5 - register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0 - register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty? - register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4 - register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4 - register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3 - register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3 - register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 - register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 - register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers - register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT - register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1 - register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2 - - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 - register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5 - register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2 - register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2 - register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4 - register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4 - register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3 - register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3 - register "usb3_ports[9]" = "USB3_PORT_EMPTY" - - # LPC generic I/O ranges - register "gen1_dec" = "0x00fc0201" - register "gen2_dec" = "0x003c0a01" - register "gen3_dec" = "0x000c03f1" - register "gen4_dec" = "0x000c0081" - - register "sata_salp_support" = "1" - - register "sata_ports_enable" = "{ - [0] = 1, - [1] = 1, - [2] = 1, - [3] = 1, - [4] = 1, - [5] = 1, - [6] = 1, - [7] = 1, - }" - - register "sata_ports_dev_slp" = "{ - [0] = 0, - [1] = 0, - [2] = 0, - [3] = 0, - [4] = 0, - [5] = 0, - [6] = 1, - [7] = 1, - }" - - # HDMI on port B - register "ddi_portB_config" = "1" - register "ddi_ports_config" = "{ - [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_2] = DDI_ENABLE_HPD, - [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, - [DDI_PORT_4] = DDI_ENABLE_HPD, - }" - register "hybrid_storage_mode" = "true" register "dmi_power_optimize_disable" = "true" @@ -104,7 +35,18 @@ chip soc/intel/alderlake "PCI_E1" "SlotDataBusWidth16X" end device ref pcie5_1 off end - device ref igpu on end + device ref igpu on + # HDMI on port B + register "ddi_portB_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_C] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_2] = DDI_ENABLE_HPD, + [DDI_PORT_3] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_4] = DDI_ENABLE_HPD, + }" + end device ref pcie4_0 on register "cpu_pcie_rp[CPU_RP(1)]" = "{ .clk_src = 9, @@ -114,8 +56,35 @@ chip soc/intel/alderlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" end - device ref crashlog off end - device ref xhci on end + device ref xhci on + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1 + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1 + register "usb2_ports[3]" = "USB2_PORT_LONG(OC0)" # JUSB5 + register "usb2_ports[4]" = "USB2_PORT_SHORT(OC3)" # HUB to rear USB 2.0 + register "usb2_ports[5]" = "USB2_PORT_LONG(OC3)" # empty? + register "usb2_ports[6]" = "USB2_PORT_LONG(OC7)" # JUSB4 + register "usb2_ports[7]" = "USB2_PORT_LONG(OC0)" # JUSB4 + register "usb2_ports[8]" = "USB2_PORT_LONG(OC2)" # JUSB3 + register "usb2_ports[9]" = "USB2_PORT_LONG(OC7)" # JUSB3 + register "usb2_ports[10]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 + register "usb2_ports[11]" = "USB2_PORT_SHORT(OC0)" # PS2_USB1 + register "usb2_ports[12]" = "USB2_PORT_SHORT(OC0)" # HUB to USB 2.0 headers + register "usb2_ports[13]" = "USB2_PORT_SHORT(OC6)" # CNVi BT + register "usb2_ports[14]" = "USB2_PORT_EMPTY" # USB Redirection port 1 + register "usb2_ports[15]" = "USB2_PORT_EMPTY" # USB Redirection port 2 + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # USB-C LAN_USB1 + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC2)" # USB-A LAN_USB1 + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC3)" # JUSB5 + register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC0)" # USB-A USB2 + register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC7)" # USB-A USB2 + register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC7)" # JUSB4 + register "usb3_ports[6]" = "USB3_PORT_DEFAULT(OC2)" # JUSB4 + register "usb3_ports[7]" = "USB3_PORT_DEFAULT(OC2)" # JUSB3 + register "usb3_ports[8]" = "USB3_PORT_DEFAULT(OC0)" # JUSB3 + register "usb3_ports[9]" = "USB3_PORT_EMPTY" + end device ref cnvi_wifi on # Enable CNVi BT register "cnvi_bt_core" = "true" @@ -127,12 +96,42 @@ chip soc/intel/alderlake end end device ref heci1 on end - device ref heci2 off end - device ref ide_r off end - device ref kt off end - device ref heci3 off end - device ref heci4 off end - device ref sata on end + device ref sata on + register "sata_salp_support" = "1" + + register "sata_ports_enable" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + + register "sata_ports_dev_slp" = "{ + [0] = 0, + [1] = 0, + [2] = 0, + [3] = 0, + [4] = 0, + [5] = 0, + [6] = 1, + [7] = 1, + }" + + register "sata_ports_hotplug" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" + end device ref pcie_rp1 on register "pch_pcie_rp[PCH_RP(1)]" = "{ .clk_src = 10, @@ -158,7 +157,6 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, }" end - device ref pcie_rp4 off end device ref pcie_rp5 on register "pch_pcie_rp[PCH_RP(5)]" = "{ @@ -212,7 +210,170 @@ chip soc/intel/alderlake "M2_2" "SlotDataBusWidth4X" end device ref pch_espi on + # LPC generic I/O ranges + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c03f1" + register "gen4_dec" = "0x000c0081" + chip superio/nuvoton/nct6687d + register "sensors[0]" = "PECI_AGENT0_DOMAIN0" + register "sensors[1]" = "TD0P_CURRENT_MODE" + register "sensors[2]" = "THERMISTOR15" + register "sensors[3]" = "PCH_CHIP" + register "sensors[4]" = "THERMISTOR16" + register "sensors[5]" = "THERMISTOR0" + register "sensors[6]" = "THERMISTOR1" + register "sensors[16]" = "VIN0" + register "sensors[17]" = "VIN1" + register "sensors[18]" = "VIN2" + register "sensors[19]" = "VIN3" + register "sensors[20]" = "VIN4" + register "sensors[21]" = "VIN5" + register "sensors[22]" = "VIN6" + register "sensors[23]" = "VIN7" + register "sensors[24]" = "VCC" + + register "smbus_sensor.sensor_idx" = "3" + register "smbus_sensor.sensor_en" = "true" + register "smbus_sensor.sensor_cmd" = "0x40" + register "smbus_sensor.sensor_addr" = "0x96" + register "smbus_sensor.baud_rate" = "BAUD_100K" + register "smbus_sensor.report_one_byte" = "true" + register "smbus_sensor.port_sel" = "1" + + register "peci_speed" = "PECI_1200KHZ" + + register "fan_default_val" = "60" + + register "smart_tracking.speed_boundary_low" = "1500" + register "smart_tracking.speed_boundary_high" = "2500" + register "smart_tracking.rpm_tolerance_low" = "100" + register "smart_tracking.rpm_tolerance_mid" = "100" + register "smart_tracking.rpm_tolerance_high" = "100" + register "smart_tracking.step_up" = "1" + register "smart_tracking.step_down" = "1" + + # CPU_FAN + register "FAN1.mode" = "FAN_SMART_FAN_IV" + register "FAN1.unit_sel" = "FAN_PWM" + register "FAN1.fanin_sel" = "TACH_PWM1" + register "FAN1.fanout_sel" = "TACH_PWM0" + register "FAN1.fan_alg_weight" = "10" + register "FAN1.smart_tracking_en" = "true" + register "FAN1.crit_temp" = "101" + register "FAN1.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN1.smart_fan.temp_levels" = "{ 40, 55, 70, 85, 90, 95, 100 }" + register "FAN1.smart_fan.speed_levels" = "{ 13, 38, 63, 85, 90, 95, 100 }" + register "FAN1.smart_fan.cut_off_delay" = "5" + register "FAN1.smart_fan.step_up_time" = "1" + register "FAN1.smart_fan.step_down_time" = "1" + + # PUMP_FAN + register "FAN2.mode" = "FAN_SMART_FAN_IV" + register "FAN2.unit_sel" = "FAN_PWM" + register "FAN2.fanin_sel" = "TACH_PWM3" + register "FAN2.fanout_sel" = "TACH_PWM2" + register "FAN2.fan_alg_weight" = "10" + register "FAN2.smart_tracking_en" = "true" + register "FAN2.crit_temp" = "101" + register "FAN2.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN2.smart_fan.temp_levels" = "{ 32, 32, 32, 32, 32, 32, 32 }" + register "FAN2.smart_fan.speed_levels" = "{ 100, 100, 100, 100, 100, 100, 100 }" + register "FAN2.smart_fan.cut_off_delay" = "5" + register "FAN2.smart_fan.step_up_time" = "1" + register "FAN2.smart_fan.step_down_time" = "1" + + # SYS_FAN1 + register "FAN3.mode" = "FAN_SMART_FAN_IV" + register "FAN3.unit_sel" = "FAN_PWM" + register "FAN3.fanin_sel" = "TACH_PWM11" + register "FAN3.fanout_sel" = "TACH_PWM10" + register "FAN3.fan_alg_weight" = "10" + register "FAN3.smart_tracking_en" = "true" + register "FAN3.crit_temp" = "101" + register "FAN3.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN3.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN3.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN3.smart_fan.cut_off_delay" = "5" + register "FAN3.smart_fan.step_up_time" = "1" + register "FAN3.smart_fan.step_down_time" = "1" + + # SYS_FAN2 + register "FAN4.mode" = "FAN_SMART_FAN_IV" + register "FAN4.unit_sel" = "FAN_PWM" + register "FAN4.fanin_sel" = "TACH_PWM13" + register "FAN4.fanout_sel" = "TACH_PWM12" + register "FAN4.fan_alg_weight" = "10" + register "FAN4.smart_tracking_en" = "true" + register "FAN4.crit_temp" = "101" + register "FAN4.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN4.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN4.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN4.smart_fan.cut_off_delay" = "5" + register "FAN4.smart_fan.step_up_time" = "1" + register "FAN4.smart_fan.step_down_time" = "1" + + # SYS_FAN3 + register "FAN5.mode" = "FAN_SMART_FAN_IV" + register "FAN5.unit_sel" = "FAN_PWM" + register "FAN5.fanin_sel" = "TACH_PWM15" + register "FAN5.fanout_sel" = "TACH_PWM14" + register "FAN5.fan_alg_weight" = "10" + register "FAN5.smart_tracking_en" = "true" + register "FAN5.crit_temp" = "101" + register "FAN5.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN5.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN5.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN5.smart_fan.cut_off_delay" = "5" + register "FAN5.smart_fan.step_up_time" = "1" + register "FAN5.smart_fan.step_down_time" = "1" + + # SYS_FAN4 + register "FAN6.mode" = "FAN_SMART_FAN_IV" + register "FAN6.unit_sel" = "FAN_PWM" + register "FAN6.fanin_sel" = "TACH_PWM17" + register "FAN6.fanout_sel" = "TACH_PWM16" + register "FAN6.fan_alg_weight" = "10" + register "FAN6.smart_tracking_en" = "true" + register "FAN6.crit_temp" = "101" + register "FAN6.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN6.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN6.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN6.smart_fan.cut_off_delay" = "5" + register "FAN6.smart_fan.step_up_time" = "1" + register "FAN6.smart_fan.step_down_time" = "1" + + # SYS_FAN5 + register "FAN7.mode" = "FAN_SMART_FAN_IV" + register "FAN7.unit_sel" = "FAN_PWM" + register "FAN7.fanin_sel" = "TACH_PWM19" + register "FAN7.fanout_sel" = "TACH_PWM18" + register "FAN7.fan_alg_weight" = "10" + register "FAN7.smart_tracking_en" = "true" + register "FAN7.crit_temp" = "101" + register "FAN7.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN7.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN7.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN7.smart_fan.cut_off_delay" = "5" + register "FAN7.smart_fan.step_up_time" = "1" + register "FAN7.smart_fan.step_down_time" = "1" + + # SYS_FAN6 + register "FAN8.mode" = "FAN_SMART_FAN_IV" + register "FAN8.unit_sel" = "FAN_PWM" + register "FAN8.fanin_sel" = "TACH_PWM6" + register "FAN8.fanout_sel" = "TACH_PWM4" + register "FAN8.fan_alg_weight" = "10" + register "FAN8.smart_tracking_en" = "true" + register "FAN8.crit_temp" = "101" + register "FAN8.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN8.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN8.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN8.smart_fan.cut_off_delay" = "5" + register "FAN8.smart_fan.step_up_time" = "1" + register "FAN8.smart_fan.step_down_time" = "1" + device pnp 4e.1 off end # Parallel port device pnp 4e.2 on # COM1 io 0x60 = 0x3f8 @@ -245,7 +406,7 @@ chip soc/intel/alderlake device pnp 0.0 on end # TPM end end - device ref p2sb on end + device ref p2sb hidden end device ref hda on subsystemid 0x1462 0x9d25 register "pch_hda_audio_link_hda_enable" = "1" diff --git a/src/mainboard/msi/ms7d25/dsdt.asl b/src/mainboard/msi/ms7d25/dsdt.asl index 8e512dbc853..11fd5e65280 100644 --- a/src/mainboard/msi/ms7d25/dsdt.asl +++ b/src/mainboard/msi/ms7d25/dsdt.asl @@ -26,5 +26,7 @@ DefinitionBlock( #include "acpi/superio.asl" } + #include "acpi/mainboard.asl" + #include } diff --git a/src/mainboard/msi/ms7d25/hda_verb.c b/src/mainboard/msi/ms7d25/hda_verb.c index 3906a84eb57..c7c06c49372 100644 --- a/src/mainboard/msi/ms7d25/hda_verb.c +++ b/src/mainboard/msi/ms7d25/hda_verb.c @@ -6,7 +6,8 @@ const u32 cim_verb_data[] = { /* Realtek ALC897 */ 0x10ec0897, /* Vendor ID */ 0x14629d25, /* Subsystem ID */ - 15, /* Number of entries */ + 28, /* Number of entries */ + AZALIA_RESET(0x1), AZALIA_SUBVENDOR(0, 0x14629d25), AZALIA_PIN_CFG(0, 0x11, 0x4037d540), AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), @@ -23,12 +24,83 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), + 0x0205003B, + 0x02040080, + 0x02050039, + 0x02044031, + + 0x02050013, + 0x02040053, + 0x02050030, + 0x020492D1, + + 0x02050021, + 0x02040000, + 0x02050023, + 0x02040000, + + 0x02050025, + 0x02040000, + 0x02050027, + 0x02040000, + + 0x02050029, + 0x02040000, + 0x0205002A, + 0x02041640, + + 0x0205002B, + 0x02041640, + 0x02050021, + 0x02040C00, + + 0x02050023, + 0x02040C00, + 0x02050025, + 0x02040C00, + + 0x02050027, + 0x02040C00, + 0x02050029, + 0x02040C00, + + 0x0205002A, + 0x02041641, + 0x0205002B, + 0x02041641, + + 0x02050030, + 0x02049251, + 0x0205002A, + 0x02041649, + + 0x0205002B, + 0x02041649, + 0x0205000C, + 0x02043F06, + + 0x02050007, + 0x0204F808, + 0x02050007, + 0x0204F808, + /* Alderlake HDMI */ 0x80862815, /* Vendor ID */ 0x80860101, /* Subsystem ID */ - 2, /* Number of entries */ + 7, /* Number of entries */ AZALIA_SUBVENDOR(2, 0x80860101), - AZALIA_PIN_CFG(2, 0x04, 0x18560010), + 0x00278111, + 0x00278111, + 0x00278111, + 0x00278111, + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x00278100, + 0x00278100, + 0x00278100, + 0x00278100 }; diff --git a/src/mainboard/msi/ms7d25/mainboard.c b/src/mainboard/msi/ms7d25/mainboard.c index b346ac7df06..527e0865bce 100644 --- a/src/mainboard/msi/ms7d25/mainboard.c +++ b/src/mainboard/msi/ms7d25/mainboard.c @@ -1,12 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include -#include #include #include #include #include +#include + +#define MSR_ATOM_TURBO_RATIO_LIMIT 0x650 +#define MSR_ATOM_TURBO_RATIO_LIMIT_CORES 0x651 +#define MSR_BIGCORE_TURBO_RATIO_LIMIT 0x1ad +#define MSR_BIGCORE_TURBO_RATIO_LIMIT_CORES 0x1ae + void mainboard_fill_fadt(acpi_fadt_t *fadt) { @@ -14,53 +22,35 @@ void mainboard_fill_fadt(acpi_fadt_t *fadt) fadt->iapc_boot_arch |= ACPI_FADT_LEGACY_DEVICES | ACPI_FADT_8042; } -static void mainboard_init(void *chip_info) -{ -} - -u8 smbios_mainboard_feature_flags(void) -{ - return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; -} -smbios_wakeup_type smbios_system_wakeup_type(void) +static void mainboard_init(void *chip_info) { - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} + struct device *ps2_dev = dev_find_slot_pnp(0x4e, NCT6687D_KBC); + bool ps2_en = get_ps2_option(); -const char *smbios_system_product_name(void) -{ - return "MS-7D25"; + ps2_dev->enabled = ps2_en & 1; + printk(BIOS_DEBUG, "PS2 Controller state: %d\n", ps2_en); } -const char *smbios_mainboard_product_name(void) +static void fill_turbo_ratio_limits(FSP_S_CONFIG *params) { - if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) { - if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) - return "PRO Z690-A WIFI DDR4(MS-7D25)"; - else - return "PRO Z690-A DDR4(MS-7D25)"; - } + msr_t msr; - if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5)) { - if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) - return "PRO Z690-A WIFI (MS-7D25)"; - else - return "PRO Z690-A (MS-7D25)"; - } + msr = rdmsr(MSR_BIGCORE_TURBO_RATIO_LIMIT); + memcpy(¶ms->TurboRatioLimitRatio[0], &msr.lo, 4); + memcpy(¶ms->TurboRatioLimitRatio[4], &msr.hi, 4); - return mainboard_part_number; -} + msr = rdmsr(MSR_BIGCORE_TURBO_RATIO_LIMIT_CORES); + memcpy(¶ms->TurboRatioLimitNumCore[0], &msr.lo, 4); + memcpy(¶ms->TurboRatioLimitNumCore[4], &msr.hi, 4); -/* Only baseboard serial number is populated */ -const char *smbios_system_serial_number(void) -{ - return "Default string"; -} + msr = rdmsr(MSR_ATOM_TURBO_RATIO_LIMIT); + memcpy(¶ms->AtomTurboRatioLimitRatio[0], &msr.lo, 4); + memcpy(¶ms->AtomTurboRatioLimitRatio[4], &msr.hi, 4); -const char *smbios_system_sku(void) -{ - return "Default string"; + msr = rdmsr(MSR_ATOM_TURBO_RATIO_LIMIT_CORES); + memcpy(¶ms->AtomTurboRatioLimitNumCore[0], &msr.lo, 4); + memcpy(¶ms->AtomTurboRatioLimitNumCore[4], &msr.hi, 4); } void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -86,24 +76,21 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating)); params->UsbPdoProgramming = 1; - params->CpuPcieFiaProgramming = 1; - params->PcieRpFunctionSwap = 0; params->CpuPcieRpFunctionSwap = 0; - params->PchLegacyIoLowLatency = 1; params->PchDmiAspmCtrl = 0; - params->CpuPcieRpPmSci[0] = 1; // M2_1 - params->CpuPcieRpPmSci[1] = 1; // PCI_E1 - params->PcieRpPmSci[0] = 1; // PCI_E2 - params->PcieRpPmSci[1] = 1; // PCI_E4 - params->PcieRpPmSci[2] = 1; // Ethernet - params->PcieRpPmSci[4] = 1; // PCI_E3 - params->PcieRpPmSci[8] = 1; // M2_3 - params->PcieRpPmSci[20] = 1; // M2_4 - params->PcieRpPmSci[24] = 1; // M2_2 + params->CpuPcieRpPmSci[0] = 0; // M2_1 + params->CpuPcieRpPmSci[1] = 0; // PCI_E1 + params->PcieRpPmSci[0] = 0; // PCI_E2 + params->PcieRpPmSci[1] = 0; // PCI_E4 + params->PcieRpPmSci[2] = 0; // Ethernet + params->PcieRpPmSci[4] = 0; // PCI_E3 + params->PcieRpPmSci[8] = 0; // M2_3 + params->PcieRpPmSci[20] = 0; // M2_4 + params->PcieRpPmSci[24] = 0; // M2_2 params->PcieRpMaxPayload[0] = 1; // PCI_E2 params->PcieRpMaxPayload[1] = 1; // PCI_E4 @@ -174,6 +161,12 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->SataPortsSolidStateDrive[6] = 1; // M2_3 params->SataPortsSolidStateDrive[7] = 1; // M2_4 params->SataLedEnable = 1; + + /* + * If OcLock is not set in FSP-M UPD, FSP-S UPD will take and program + * zeroed turbo ratio limits. Avoid this by populating defautl values here. + */ + fill_turbo_ratio_limits(params); } #if CONFIG(GENERATE_SMBIOS_TABLES) @@ -531,7 +524,12 @@ static void mainboard_enable(struct device *dev) #endif } +static void mainboard_final(void *chip_info) +{ +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, + .final = mainboard_final, }; diff --git a/src/mainboard/msi/ms7d25/msi_id.S b/src/mainboard/msi/ms7d25/msi_id.S new file mode 100644 index 00000000000..8be2e971651 --- /dev/null +++ b/src/mainboard/msi/ms7d25/msi_id.S @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +.section .init, "a", @progbits + +/* The following structures must reside in the last 64KiB of flash */ + +.align 16 + +build_date: + .ascii "$MSESGN$" + .ascii "E7D25IMS." +#if CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5) + .byte 'A' +#endif +#if CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4) + .byte '1' +#endif + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte ' ' + .asciz COREBOOT_DMI_DATE + +.align 8 + +msi_sign_on: + .ascii "$MS1E7D25IMS" +#if CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5) + .byte 'A' +#endif +#if CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4) + .byte '1' +#endif + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte 2 + +.align 8 + +bpa: + .ascii "$BPA" + .byte bpa_end - bpa + .byte 1 + .long 0x1000 + .long 6 + .byte 2 + .long 0x17c0000 + .long 0x20000 + .byte 3 + .long 0x1080000 + .long 64 + .byte 4 + .long 2 +bpa_end: + .byte 0, 0, 0, 0, 0 + + .asciz "@FC@" + .byte 2 + .byte 0 + .byte '1' + .asciz "/P /B /N" + .byte '2' + .byte 0 + .ascii "NULL" + .ascii "@@" + .fill 10, 1, 0 diff --git a/src/mainboard/msi/ms7d25/romhole.h b/src/mainboard/msi/ms7d25/romhole.h new file mode 100644 index 00000000000..f9ae37de919 --- /dev/null +++ b/src/mainboard/msi/ms7d25/romhole.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ROMHOLE_H_ +#define _ROMHOLE_H_ + +#define ROMHOLE_MAGIC 0x10012501 +#define NUM_PWD_ENTRIES 2 +#define PWD_SIZE 40 +#define NUM_GD_ENTRIES 8 +#define GD_SIZE 48 +#define NUM_US_ENTRIES 8 +#define US_SIZE 0x3851 +#define TYPE2_SIZE 256 +#define FTB_SIZE 105 +#define FIB_SIZE 512 +#define FDP_SIZE 1024 +#define BUV_SIZE 1024 +#define NUM_VOLUMES 7 + +struct uuid_structure { + uint8_t magic0[4]; // always sSiD + uint16_t length; // structure length, always 0x1a + uint8_t magic1[3]; // awlays $uD + uint8_t space; // always 0x1 + uint8_t uuid[16]; // SMBIOS type 1 UUID +} __packed; + +struct pwd_entry { + uint8_t magic[3]; // always $s$ + uint8_t number; // ordinal number + uint8_t length; // length of pwd + uint8_t pwd[PWD_SIZE]; // password? +} __packed; + +struct pwd_structure { + uint8_t magic[4]; // always spWd + uint16_t length; // structure length + struct pwd_entry entries[NUM_PWD_ENTRIES]; +} __packed; + +struct gd_entry { + uint8_t magic[3]; // always $gD + uint8_t number; // ordinal number + uint16_t length; // length of gd + uint8_t gd[GD_SIZE]; // global data? +} __packed; + +struct gpdt_structure { + uint8_t magic[4]; // always gPdT + uint16_t length; // structure length + uint8_t num_entries; // number of entries + uint8_t space; // awlays zero + struct gd_entry entries[NUM_GD_ENTRIES]; +} __packed; + +struct us_entry { + uint8_t magic[3]; // always $uS + uint8_t number; // ordinal number + uint16_t length; // length of us + uint8_t us[US_SIZE]; // user data? +} __packed; + +struct ucsc_structure { + uint8_t magic[4]; // always uCsC + uint16_t length; // structure length + struct us_entry entries[NUM_US_ENTRIES]; +} __packed; + +struct type2_rw { + uint8_t magic0[4]; // always t2Rw + uint16_t length; // structure length + uint8_t magic1[3]; // always $tW + uint8_t space; // always 0x1 + uint8_t smbios_type2[TYPE2_SIZE]; // SMBIOS type2 table +} __packed; + +struct ftb_structure { + uint8_t magic0[4]; // always $FTB + uint16_t length; // structure length + uint8_t magic1[4]; // always $DIB + uint16_t space0; // always 0x2 + uint16_t size; // size of data field, always 105 + uint16_t space1; // always 0x0 + uint8_t magic2[4]; // always MFTD + uint8_t data[FTB_SIZE]; // default 0xfe +} __packed; + +struct fib_structure { + uint8_t magic0[4]; // always $FIB + uint16_t length; // structure length + uint16_t size; // size of data field, always 512 + uint8_t magic1[4]; // always $MFX + uint8_t data[FIB_SIZE]; // default 0xfa +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P since A.40/1.40 */ +struct fdp_structure { + uint8_t magic0[4]; // always $FDP + uint16_t length; // structure length + uint8_t magic1[3]; // always $Fd + uint8_t number; // always 0x1 + uint8_t data[FDP_SIZE]; // default 0xff +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P A.40/1.40 */ +struct buv_structure { + uint8_t magic0[4]; // always $BuV + uint16_t length; // structure length + uint8_t magic1[3]; // always $Bv + uint8_t number; // always 0x1 + uint8_t data[BUV_SIZE]; // default 0xff +} __packed; + +struct volume_entry { + uint8_t number; // ordinal number in ascii + uint32_t address; // volume base address + uint32_t size; // volume size + uint8_t space; // always 0xff +} __packed; + +struct ris_structure { + uint8_t magic0[4]; // always $RiS + uint16_t length; // structure length + uint8_t magic1[4]; // always $RiT + /* Array below keep the addresses and sizes of UEFI Firmware Volumes */ + struct volume_entry volumes[NUM_VOLUMES]; +} __packed; + +/* Place the following struct in the ROMHOLE flash region with 64K/128K alignment */ +struct msi_romhole { + uint32_t magic0; // 0x10012501 + uint16_t length; // length of the structure + char magic1[4]; // always SYSD + uint32_t address; // romhole address in flash + uint32_t size; // romhole total size + uint8_t pad0[48]; // always 0xff + struct uuid_structure uuid; + struct pwd_structure pwd; + struct gpdt_structure gpdt; + struct ucsc_structure ucsc; + struct type2_rw t2rw; + struct ftb_structure ftb; + struct fib_structure fib; + struct fdp_structure fdp; + struct buv_structure buv; + struct ris_structure ris; + // the rest is padded with 0xff by cbfstool +} __packed; + +#endif diff --git a/src/mainboard/msi/ms7d25/romstage_fsp_params.c b/src/mainboard/msi/ms7d25/romstage_fsp_params.c index 1494deec8ba..f152de76b5f 100644 --- a/src/mainboard/msi/ms7d25/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7d25/romstage_fsp_params.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -80,8 +81,15 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.DmiAspmCtrl = 0; memupd->FspmConfig.SkipExtGfxScan = 0; + memupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1; memupd->FspmConfig.PchHdaSdiEnable[0] = 1; + memupd->FspmConfig.MmioSize = 0xb00; /* 2.75GB in MB */ + + memupd->FspmConfig.OcLock = 0; + + memupd->FspmConfig.SpdProfileSelected = dasharo_get_memory_profile(); + if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5)) diff --git a/src/mainboard/msi/ms7d25/smbios.c b/src/mainboard/msi/ms7d25/smbios.c new file mode 100644 index 00000000000..6a543521963 --- /dev/null +++ b/src/mainboard/msi/ms7d25/smbios.c @@ -0,0 +1,147 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "romhole.h" + +struct smbios_type2_v3_4 { + struct smbios_header header; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 asset_tag; + u8 feature_flags; + u8 location_in_chassis; + u16 chassis_handle; + u8 board_type; + u8 contained_objects; + u8 eos[2]; +} __packed; + +static struct msi_romhole *romhole_addr = NULL; + +static struct msi_romhole *get_msi_romhole_address(void) +{ + struct region_device rdev; + + if (romhole_addr) + return romhole_addr; + + if (fmap_locate_area_as_rdev("ROMHOLE", &rdev)) + return NULL; + + romhole_addr = (struct msi_romhole *)rdev_mmap_full(&rdev); + + return romhole_addr; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +const char *smbios_system_product_name(void) +{ + return "MS-7D25"; +} +const char *smbios_mainboard_product_name(void) +{ + if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR4)) { + if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) + return "PRO Z690-A WIFI DDR4(MS-7D25)"; + else + return "PRO Z690-A DDR4(MS-7D25)"; + } + + if (CONFIG(BOARD_MSI_Z690_A_PRO_WIFI_DDR5)) { + if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) + return "PRO Z690-A WIFI (MS-7D25)"; + else + return "PRO Z690-A (MS-7D25)"; + } + + return CONFIG_MAINBOARD_PART_NUMBER; +} + +/* Only baseboard serial number is populated */ +const char *smbios_system_serial_number(void) +{ + return "Default string"; +} + +const char *smbios_system_sku(void) +{ + return "Default string"; +} + +void smbios_system_set_uuid(u8 *uuid) +{ + if (!get_msi_romhole_address()) + return; + + memcpy(uuid, romhole_addr->uuid.uuid, 16); +} + +static const char* get_smbios_string(u8 *str_table_start, u8 string_index, + const char *fallback) +{ + u8 i; + char *smbios_str = (char *)str_table_start; + + for (i = 1; i < string_index; i++) { + if (strlen(smbios_str)) + smbios_str += strlen(smbios_str) + 1; + else + return fallback; + } + + return strlen(smbios_str) ? (const char *)smbios_str : fallback; +} + +const char *smbios_mainboard_serial_number(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + return get_smbios_string(type2->eos, type2->serial_number, + CONFIG_MAINBOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_VERSION; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_VERSION; + + return get_smbios_string(type2->eos, type2->version, + CONFIG_MAINBOARD_VERSION); +} diff --git a/src/mainboard/msi/ms7d25/smihandler.c b/src/mainboard/msi/ms7d25/smihandler.c new file mode 100644 index 00000000000..3978d4fcef1 --- /dev/null +++ b/src/mainboard/msi/ms7d25/smihandler.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) +#define ACPI_DEV PNP_DEV(0x4e, NCT6687D_ACPI) + +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +static void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +static void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +static void disable_ps2_wake(void) +{ + uint8_t reg; + + pnp_set_logical_device(ACPI_DEV); + reg = pnp_read_config(ACPI_DEV, 0xe4); + reg &= ~0xc0; /* Disable keyboard and mouse wake via PSOUT# */ + reg &= ~0x08; /* Disable keyboard wake with any key */ + pnp_write_config(ACPI_DEV, 0xe4, reg); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + nuvoton_pnp_enter_conf_state(POWER_DEV); + pnp_set_logical_device(POWER_DEV); + + switch (slp_typ) { + case 3: + pnp_write_config(POWER_DEV, 0xe7, 0x20); /* Keep LED freq at S3-S5 */ + pnp_write_config(POWER_DEV, 0xe8, 0x05); /* Blink LED at 1Hz */ + break; + case 4: + pnp_write_config(POWER_DEV, 0xe7, 0x88); /* Set AUTO_EN */ + pnp_write_config(POWER_DEV, 0xe8, 0x07); /* LED to low */ + break; + case 5: + pnp_write_config(POWER_DEV, 0xe7, 0x88); /* Set AUTO_EN */ + pnp_write_config(POWER_DEV, 0xe8, 0x07); /* LED to low */ + disable_ps2_wake(); + break; + } + + nuvoton_pnp_exit_conf_state(POWER_DEV); +} diff --git a/src/mainboard/msi/ms7d25/vboot-rwab.fmd b/src/mainboard/msi/ms7d25/vboot-rwab.fmd index 665c8949bbe..7569cda7cc4 100644 --- a/src/mainboard/msi/ms7d25/vboot-rwab.fmd +++ b/src/mainboard/msi/ms7d25/vboot-rwab.fmd @@ -6,6 +6,10 @@ FLASH 32M { UNUSED 12M + SMMSTORE(PRESERVE) 256K + RESERVED(PRESERVE) 256K + BPA(PRESERVE) 128K + RW_MISC 320K { UNIFIED_MRC_CACHE(PRESERVE) { RECOVERY_MRC_CACHE 128K @@ -21,22 +25,25 @@ FLASH 32M { } CONSOLE 128K - SMMSTORE(PRESERVE) 256K HSPHY_FW(PRESERVE) 32K + BOOTSPLASH(CBFS) 2M - RW_SECTION_A 5264K { + RW_SECTION_A 4768K { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 0x100 } - RW_SECTION_B 5264K { + # ROMHOLE must be at flash offset 0x17c0000 + ROMHOLE(PRESERVE) 128K + + RW_SECTION_B 4224K { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 0x100 } - WP_RO 5M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K diff --git a/src/mainboard/msi/ms7e06/Kconfig b/src/mainboard/msi/ms7e06/Kconfig index b0ba2163568..727e41e472a 100644 --- a/src/mainboard/msi/ms7e06/Kconfig +++ b/src/mainboard/msi/ms7e06/Kconfig @@ -3,7 +3,7 @@ config BOARD_MSI_Z790_P_PRO_WIFI_DDR4 select BOARD_MSI_MS7E06 -config BOARD_MSI_Z790_P_PRO_WIFI +config BOARD_MSI_Z790_P_PRO_WIFI_DDR5 select BOARD_MSI_MS7E06 config BOARD_MSI_MS7E06 @@ -19,6 +19,7 @@ config BOARD_MSI_MS7E06 select MEMORY_MAPPED_TPM select CRB_TPM select HAVE_INTEL_PTT + select BOARD_HAS_MSI_ROMHOLE if BOARD_MSI_MS7E06 @@ -26,8 +27,8 @@ config MAINBOARD_DIR default "msi/ms7e06" config MAINBOARD_PART_NUMBER - default "PRO Z790-P WIFI DDR4(MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI_DDR4 - default "PRO Z790-P WIFI (MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI + default "PRO Z790-P WIFI DDR4 (MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI_DDR4 + default "PRO Z790-P WIFI (MS-7E06)" if BOARD_MSI_Z790_P_PRO_WIFI_DDR5 config MAINBOARD_VENDOR default "Micro-Star International Co., Ltd." @@ -35,6 +36,9 @@ config MAINBOARD_VENDOR config MAINBOARD_FAMILY default "Default string" +config MAINBOARD_VERSION + default "2.0" if BOARD_MSI_Z790_P_PRO_WIFI_DDR5 + config UART_FOR_CONSOLE default 0 @@ -58,6 +62,8 @@ config VBOOT select VBOOT_ALWAYS_ENABLE_DISPLAY select VBOOT_NO_BOARD_SUPPORT select HAS_RECOVERY_MRC_CACHE + select VBOOT_NO_TPM + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE config VBOOT_SLOTS_RW_AB default y if VBOOT @@ -73,4 +79,19 @@ config FMDFILE config GBB_HWID default "MSI_MS7E06" +if !VBOOT && MSI_ROMHOLE_IN_CBFS + +# FIXME: Make coreboot build system automatically fixup the ucode and FIT location +# so that creating FIT does not fail. +config CPU_MICROCODE_CBFS_LOC + hex + default 0xff800000 + +config INTEL_FIT_LOC + hex + default 0xfffc0000 + +endif + + endif diff --git a/src/mainboard/msi/ms7e06/Kconfig.name b/src/mainboard/msi/ms7e06/Kconfig.name index 8154492d628..026018024b2 100644 --- a/src/mainboard/msi/ms7e06/Kconfig.name +++ b/src/mainboard/msi/ms7e06/Kconfig.name @@ -3,5 +3,5 @@ config BOARD_MSI_Z790_P_PRO_WIFI_DDR4 bool "PRO Z790-P (WIFI) DDR4" -config BOARD_MSI_Z790_P_PRO_WIFI +config BOARD_MSI_Z790_P_PRO_WIFI_DDR5 bool "PRO Z790-P (WIFI)" diff --git a/src/mainboard/msi/ms7e06/Makefile.mk b/src/mainboard/msi/ms7e06/Makefile.mk index deb5ff625a6..cc0df70e7bd 100644 --- a/src/mainboard/msi/ms7e06/Makefile.mk +++ b/src/mainboard/msi/ms7e06/Makefile.mk @@ -2,9 +2,32 @@ bootblock-y += bootblock.c +$(call src-to-obj,bootblock,$(dir)/msi_id.S): $(obj)/fmap_config.h +bootblock-y += msi_id.S + romstage-y += romstage_fsp_params.c ramstage-y += mainboard.c +ramstage-y += smbios.c all-y += die.c smm-y += die.c + +ifeq ($(CONFIG_MSI_ROMHOLE_IN_CBFS),y) + +$(obj)/mainboard/$(MAINBOARDDIR)/bpa.bin: + dd if=/dev/zero of=$@ bs=64K count=1 + +cbfs-files-y += bpa.bin + +bpa.bin-file := $(obj)/mainboard/$(MAINBOARDDIR)/bpa.bin +bpa.bin-type := raw +bpa.bin-compression := none +bpa.bin-position := 0xff080000 # Fixed position from original MSI firmware + +# Workaround: place build_info exactly at the EXT_BIOS_WINDOW boundary (plus +# the metadata size) to avoid files getting fragmented between +# FIXED_BIOS_WINDOW and EXT_BIOS_WINDOW. +build_info-COREBOOT-position := 0xff000040 + +endif diff --git a/src/mainboard/msi/ms7e06/acpi/mainboard.asl b/src/mainboard/msi/ms7e06/acpi/mainboard.asl index 8cc72ab68d7..6aca5b5e8f9 100644 --- a/src/mainboard/msi/ms7e06/acpi/mainboard.asl +++ b/src/mainboard/msi/ms7e06/acpi/mainboard.asl @@ -8,7 +8,7 @@ Scope (_GPE) { Scope (\_SB.PCI0) { /* This device triggers automatic drivers and MSI utilities installation on Windows */ Device (MSIV) { - Name (_HID, "MBID0001") + Name (_HID, "MBID0002") Name (_UID, 1) Method (_STA, 0, NotSerialized){ Return (1) diff --git a/src/mainboard/msi/ms7e06/bootblock.c b/src/mainboard/msi/ms7e06/bootblock.c index 110d6828a61..55c2a88dec0 100644 --- a/src/mainboard/msi/ms7e06/bootblock.c +++ b/src/mainboard/msi/ms7e06/bootblock.c @@ -4,42 +4,76 @@ #include #include #include +#include +#define GPIO_DEV PNP_DEV(0x4e, NCT6687D_GPIO_0_7) #define SERIAL_DEV PNP_DEV(0x4e, NCT6687D_SP1) #define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) +#define P80_UART_DEV PNP_DEV(0x4e, NCT6687D_P80_UART) +#define EC_DEV PNP_DEV(0x4e, NCT6687D_EC) + +#define EC_IO_BASE 0xa20 void bootblock_mainboard_early_init(void) { /* Replicate vendor settings for multi-function pins in global config LDN */ - nuvoton_pnp_enter_conf_state(SERIAL_DEV); - pnp_write_config(SERIAL_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low - pnp_write_config(SERIAL_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low + nuvoton_pnp_enter_conf_state(GPIO_DEV); + pnp_write_config(GPIO_DEV, 0x13, 0xff); // IRQ8-15 level triggered, low + pnp_write_config(GPIO_DEV, 0x14, 0xff); // IRQ0-7 level triggered, low /* Below are multi-pin function */ - pnp_write_config(SERIAL_DEV, 0x15, 0xaa); - pnp_write_config(SERIAL_DEV, 0x1a, 0x02); - pnp_write_config(SERIAL_DEV, 0x1b, 0x02); - pnp_write_config(SERIAL_DEV, 0x1d, 0x00); - pnp_write_config(SERIAL_DEV, 0x1e, 0xaa); - pnp_write_config(SERIAL_DEV, 0x1f, 0xb2); - pnp_write_config(SERIAL_DEV, 0x22, 0xbd); - pnp_write_config(SERIAL_DEV, 0x23, 0xdf); - pnp_write_config(SERIAL_DEV, 0x24, 0x39); - pnp_write_config(SERIAL_DEV, 0x25, 0xfe); - pnp_write_config(SERIAL_DEV, 0x26, 0x40); - pnp_write_config(SERIAL_DEV, 0x27, 0x77); - pnp_write_config(SERIAL_DEV, 0x28, 0x00); - pnp_write_config(SERIAL_DEV, 0x29, 0xfb); - pnp_write_config(SERIAL_DEV, 0x2a, 0x80); - pnp_write_config(SERIAL_DEV, 0x2b, 0x20); - pnp_write_config(SERIAL_DEV, 0x2c, 0x8a); - pnp_write_config(SERIAL_DEV, 0x2d, 0xaa); + pnp_write_config(GPIO_DEV, 0x15, 0xaa); + pnp_write_config(GPIO_DEV, 0x1a, 0x02); + pnp_write_config(GPIO_DEV, 0x1b, 0x02); + pnp_write_config(GPIO_DEV, 0x1d, 0x00); + pnp_write_config(GPIO_DEV, 0x1e, 0xaa); + pnp_write_config(GPIO_DEV, 0x1f, 0xb2); + pnp_write_config(GPIO_DEV, 0x22, 0xbd); + pnp_write_config(GPIO_DEV, 0x23, 0xdf); + pnp_write_config(GPIO_DEV, 0x24, 0x39); + pnp_write_config(GPIO_DEV, 0x25, 0xfe); + pnp_write_config(GPIO_DEV, 0x26, 0x40); + pnp_write_config(GPIO_DEV, 0x27, 0x77); + pnp_write_config(GPIO_DEV, 0x28, 0x00); + pnp_write_config(GPIO_DEV, 0x29, 0xfb); + pnp_write_config(GPIO_DEV, 0x2a, 0x80); + pnp_write_config(GPIO_DEV, 0x2b, 0x20); + pnp_write_config(GPIO_DEV, 0x2c, 0x8a); + pnp_write_config(GPIO_DEV, 0x2d, 0xaa); + + /* Set GPIO 06 as high output */ + pnp_write_config(GPIO_DEV, 0xF0, 0x00); + pnp_unset_and_set_config(GPIO_DEV, 0xe0, 0x40, 0x40); + pnp_unset_and_set_config(GPIO_DEV, 0xe3, 0x40, 0x00); pnp_set_logical_device(POWER_DEV); /* Configure pin for PECI */ pnp_write_config(POWER_DEV, 0xf3, 0x80); - nuvoton_pnp_exit_conf_state(POWER_DEV); + /* Configure power fault detection */ + pnp_unset_and_set_config(POWER_DEV, 0xf0, 0xF2, 0x30); + pnp_unset_and_set_config(POWER_DEV, 0xf0, 0x03, 0x01); + + /* Configure yellow and green LED */ + pnp_write_config(POWER_DEV, 0xe7, 0x88); + pnp_write_config(POWER_DEV, 0xe8, 0x07); + pnp_set_logical_device(P80_UART_DEV); + pnp_write_config(P80_UART_DEV, 0xe5, 0x0f); + + /* Configure EC */ + pnp_set_logical_device(EC_DEV); + pnp_set_iobase(EC_DEV, PNP_IDX_IO0, EC_IO_BASE); + pnp_set_enable(EC_DEV, 1); + + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 6, 0x61, 0x3f, 0xC0); + nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x34, 0xc0, 0x00); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x07, 0xff, 0x03); + nct6687d_ec_and_or_page(EC_IO_BASE, 0, 0x3d, 0xbf, 0x40); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 8, 0x00, 0xff, 0x01); + nct6687d_ec_and_or_page_ff(EC_IO_BASE, 0, 0x34, 0xfb, 0x04); + + + nuvoton_pnp_exit_conf_state(EC_DEV); if (CONFIG(CONSOLE_SERIAL)) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/msi/ms7e06/devicetree.cb b/src/mainboard/msi/ms7e06/devicetree.cb index eb179885c17..ac5ad95dfd8 100644 --- a/src/mainboard/msi/ms7e06/devicetree.cb +++ b/src/mainboard/msi/ms7e06/devicetree.cb @@ -7,6 +7,7 @@ chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" register "RMT" = "0" register "enable_c6dram" = "1" + register "enable_hwp_scalability_tracking" = "true" register "pmc_gpe0_dw0" = "GPP_J" register "pmc_gpe0_dw1" = "GPP_VPGIO" @@ -33,6 +34,7 @@ chip soc/intel/alderlake smbios_slot_desc "SlotTypePciExpressGen5x16" "SlotLengthLong" "PCI_E1" "SlotDataBusWidth16X" end + device ref pcie5_1 off end device ref igpu on # HDMI on port B register "ddi_portB_config" = "1" @@ -54,7 +56,9 @@ chip soc/intel/alderlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M2_1" "SlotDataBusWidth4X" end + device ref crashlog off end device ref xhci on + # USB Configuration register "usb2_ports[0]" = "USB2_PORT_SHORT(OC2)" # USB-C LAN_USB1 register "usb2_ports[1]" = "USB2_PORT_SHORT(OC1)" # MSI MYSTIC LIGHT register "usb2_ports[2]" = "USB2_PORT_SHORT(OC0)" # USB-A LAN_USB1 @@ -118,6 +122,17 @@ chip soc/intel/alderlake [6] = 1, [7] = 1, }" + + register "sata_ports_hotplug" = "{ + [0] = 1, + [1] = 1, + [2] = 1, + [3] = 1, + [4] = 1, + [5] = 1, + [6] = 1, + [7] = 1, + }" end device ref pcie_rp1 on register "pch_pcie_rp[PCH_RP(1)]" = "{ @@ -144,6 +159,7 @@ chip soc/intel/alderlake .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED | PCIE_RP_BUILT_IN, }" end + device ref pcie_rp4 off end device ref pcie_rp5 on register "pch_pcie_rp[PCH_RP(5)]" = "{ @@ -197,12 +213,170 @@ chip soc/intel/alderlake "M2_2" "SlotDataBusWidth4X" end device ref pch_espi on + # LPC generic I/O ranges register "gen1_dec" = "0x00fc0201" register "gen2_dec" = "0x003c0a01" register "gen3_dec" = "0x000c03f1" register "gen4_dec" = "0x000c0081" chip superio/nuvoton/nct6687d + register "sensors[0]" = "PECI_AGENT0_DOMAIN0" + register "sensors[1]" = "TD0P_CURRENT_MODE" + register "sensors[2]" = "THERMISTOR15" + register "sensors[3]" = "PCH_CHIP" + register "sensors[4]" = "THERMISTOR16" + register "sensors[5]" = "THERMISTOR0" + register "sensors[6]" = "THERMISTOR1" + register "sensors[16]" = "VIN0" + register "sensors[17]" = "VIN1" + register "sensors[18]" = "VIN2" + register "sensors[19]" = "VIN3" + register "sensors[20]" = "VIN4" + register "sensors[21]" = "VIN5" + register "sensors[22]" = "VIN6" + register "sensors[23]" = "VIN7" + register "sensors[24]" = "VCC" + + register "smbus_sensor.sensor_idx" = "3" + register "smbus_sensor.sensor_en" = "true" + register "smbus_sensor.sensor_cmd" = "0x40" + register "smbus_sensor.sensor_addr" = "0x96" + register "smbus_sensor.baud_rate" = "BAUD_100K" + register "smbus_sensor.report_one_byte" = "true" + register "smbus_sensor.port_sel" = "1" + + register "peci_speed" = "PECI_1200KHZ" + + register "fan_default_val" = "60" + + register "smart_tracking.speed_boundary_low" = "1500" + register "smart_tracking.speed_boundary_high" = "2500" + register "smart_tracking.rpm_tolerance_low" = "100" + register "smart_tracking.rpm_tolerance_mid" = "100" + register "smart_tracking.rpm_tolerance_high" = "100" + register "smart_tracking.step_up" = "1" + register "smart_tracking.step_down" = "1" + + # CPU_FAN + register "FAN1.mode" = "FAN_SMART_FAN_IV" + register "FAN1.unit_sel" = "FAN_PWM" + register "FAN1.fanin_sel" = "TACH_PWM1" + register "FAN1.fanout_sel" = "TACH_PWM0" + register "FAN1.fan_alg_weight" = "10" + register "FAN1.smart_tracking_en" = "true" + register "FAN1.crit_temp" = "101" + register "FAN1.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN1.smart_fan.temp_levels" = "{ 40, 55, 70, 85, 90, 95, 100 }" + register "FAN1.smart_fan.speed_levels" = "{ 13, 38, 63, 85, 90, 95, 100 }" + register "FAN1.smart_fan.cut_off_delay" = "5" + register "FAN1.smart_fan.step_up_time" = "1" + register "FAN1.smart_fan.step_down_time" = "1" + + # PUMP_FAN + register "FAN2.mode" = "FAN_SMART_FAN_IV" + register "FAN2.unit_sel" = "FAN_PWM" + register "FAN2.fanin_sel" = "TACH_PWM3" + register "FAN2.fanout_sel" = "TACH_PWM2" + register "FAN2.fan_alg_weight" = "10" + register "FAN2.smart_tracking_en" = "true" + register "FAN2.crit_temp" = "101" + register "FAN2.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN2.smart_fan.temp_levels" = "{ 32, 32, 32, 32, 32, 32, 32 }" + register "FAN2.smart_fan.speed_levels" = "{ 100, 100, 100, 100, 100, 100, 100 }" + register "FAN2.smart_fan.cut_off_delay" = "5" + register "FAN2.smart_fan.step_up_time" = "1" + register "FAN2.smart_fan.step_down_time" = "1" + + # SYS_FAN1 + register "FAN3.mode" = "FAN_SMART_FAN_IV" + register "FAN3.unit_sel" = "FAN_PWM" + register "FAN3.fanin_sel" = "TACH_PWM11" + register "FAN3.fanout_sel" = "TACH_PWM10" + register "FAN3.fan_alg_weight" = "10" + register "FAN3.smart_tracking_en" = "true" + register "FAN3.crit_temp" = "101" + register "FAN3.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN3.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN3.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN3.smart_fan.cut_off_delay" = "5" + register "FAN3.smart_fan.step_up_time" = "1" + register "FAN3.smart_fan.step_down_time" = "1" + + # SYS_FAN2 + register "FAN4.mode" = "FAN_SMART_FAN_IV" + register "FAN4.unit_sel" = "FAN_PWM" + register "FAN4.fanin_sel" = "TACH_PWM13" + register "FAN4.fanout_sel" = "TACH_PWM12" + register "FAN4.fan_alg_weight" = "10" + register "FAN4.smart_tracking_en" = "true" + register "FAN4.crit_temp" = "101" + register "FAN4.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN4.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN4.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN4.smart_fan.cut_off_delay" = "5" + register "FAN4.smart_fan.step_up_time" = "1" + register "FAN4.smart_fan.step_down_time" = "1" + + # SYS_FAN3 + register "FAN5.mode" = "FAN_SMART_FAN_IV" + register "FAN5.unit_sel" = "FAN_PWM" + register "FAN5.fanin_sel" = "TACH_PWM15" + register "FAN5.fanout_sel" = "TACH_PWM14" + register "FAN5.fan_alg_weight" = "10" + register "FAN5.smart_tracking_en" = "true" + register "FAN5.crit_temp" = "101" + register "FAN5.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN5.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN5.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN5.smart_fan.cut_off_delay" = "5" + register "FAN5.smart_fan.step_up_time" = "1" + register "FAN5.smart_fan.step_down_time" = "1" + + # SYS_FAN4 + register "FAN6.mode" = "FAN_SMART_FAN_IV" + register "FAN6.unit_sel" = "FAN_PWM" + register "FAN6.fanin_sel" = "TACH_PWM17" + register "FAN6.fanout_sel" = "TACH_PWM16" + register "FAN6.fan_alg_weight" = "10" + register "FAN6.smart_tracking_en" = "true" + register "FAN6.crit_temp" = "101" + register "FAN6.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN6.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN6.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN6.smart_fan.cut_off_delay" = "5" + register "FAN6.smart_fan.step_up_time" = "1" + register "FAN6.smart_fan.step_down_time" = "1" + + # SYS_FAN5 + register "FAN7.mode" = "FAN_SMART_FAN_IV" + register "FAN7.unit_sel" = "FAN_PWM" + register "FAN7.fanin_sel" = "TACH_PWM19" + register "FAN7.fanout_sel" = "TACH_PWM18" + register "FAN7.fan_alg_weight" = "10" + register "FAN7.smart_tracking_en" = "true" + register "FAN7.crit_temp" = "101" + register "FAN7.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN7.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN7.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN7.smart_fan.cut_off_delay" = "5" + register "FAN7.smart_fan.step_up_time" = "1" + register "FAN7.smart_fan.step_down_time" = "1" + + # SYS_FAN6 + register "FAN8.mode" = "FAN_SMART_FAN_IV" + register "FAN8.unit_sel" = "FAN_PWM" + register "FAN8.fanin_sel" = "TACH_PWM6" + register "FAN8.fanout_sel" = "TACH_PWM4" + register "FAN8.fan_alg_weight" = "10" + register "FAN8.smart_tracking_en" = "true" + register "FAN8.crit_temp" = "101" + register "FAN8.smart_fan.temp_src" = "{ 1, 0, 0, 0 }" + register "FAN8.smart_fan.temp_levels" = "{ 10, 20, 30, 40, 50, 60, 70 }" + register "FAN8.smart_fan.speed_levels" = "{ 60, 60, 60, 60, 60, 60, 60 }" + register "FAN8.smart_fan.cut_off_delay" = "5" + register "FAN8.smart_fan.step_up_time" = "1" + register "FAN8.smart_fan.step_down_time" = "1" + device pnp 4e.1 off end # Parallel port device pnp 4e.2 on # COM1 io 0x60 = 0x3f8 @@ -235,8 +409,11 @@ chip soc/intel/alderlake device pnp 0.0 on end # TPM end end + device ref p2sb hidden end device ref hda on subsystemid 0x1462 0x9e06 + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_dsp_enable" = "0" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_codec_enable" = "true" diff --git a/src/mainboard/msi/ms7e06/gpio.h b/src/mainboard/msi/ms7e06/gpio.h index 71b30e0c8c8..2014fa8ef80 100644 --- a/src/mainboard/msi/ms7e06/gpio.h +++ b/src/mainboard/msi/ms7e06/gpio.h @@ -165,14 +165,14 @@ static const struct pad_config gpio_table[] = { /* ------- GPIO Group vGPIO_0 ------- */ /* These are Virtual USB OC pins */ - _PAD_CFG_STRUCT(VGPIO_USB_0, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_0 */ - _PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_1 */ - _PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_2 */ - _PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_3 */ - _PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_8 */ - _PAD_CFG_STRUCT(VGPIO_USB_9, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_9 */ - _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_10 */ - _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_11 */ + _PAD_CFG_STRUCT(VGPIO_USB_0, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_0 */ + _PAD_CFG_STRUCT(VGPIO_USB_1, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_1 */ + _PAD_CFG_STRUCT(VGPIO_USB_2, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_2 */ + _PAD_CFG_STRUCT(VGPIO_USB_3, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_3 */ + _PAD_CFG_STRUCT(VGPIO_USB_8, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_8 */ + _PAD_CFG_STRUCT(VGPIO_USB_9, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_9 */ + _PAD_CFG_STRUCT(VGPIO_USB_10, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_10 */ + _PAD_CFG_STRUCT(VGPIO_USB_11, PAD_FUNC(NF1) | PAD_RESET(DEEP)| PAD_CFG0_NAFVWE_ENABLE, 0), /* VGPIO_USB_11 */ /* ------- GPIO Community 1 ------- */ diff --git a/src/mainboard/msi/ms7e06/hda_verb.c b/src/mainboard/msi/ms7e06/hda_verb.c index 96578fa9ab6..89def1bbb31 100644 --- a/src/mainboard/msi/ms7e06/hda_verb.c +++ b/src/mainboard/msi/ms7e06/hda_verb.c @@ -6,7 +6,8 @@ const u32 cim_verb_data[] = { /* Realtek ALC897 */ 0x10ec0897, /* Vendor ID */ 0x14629e06, /* Subsystem ID */ - 15, /* Number of entries */ + 28, /* Number of entries */ + AZALIA_RESET(0x1), AZALIA_SUBVENDOR(0, 0x14629e06), AZALIA_PIN_CFG(0, 0x11, 0x4037d540), AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_CFG_NC(0)), @@ -23,22 +24,86 @@ const u32 cim_verb_data[] = { AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), AZALIA_PIN_CFG(0, 0x1f, AZALIA_PIN_CFG_NC(0)), - /* Alderlake HDMI */ - 0x80862818, /* Vendor ID */ + 0x0205003B, + 0x02040080, + 0x02050039, + 0x02044031, + + 0x02050013, + 0x02040053, + 0x02050030, + 0x020492D1, + + 0x02050021, + 0x02040000, + 0x02050023, + 0x02040000, + + 0x02050025, + 0x02040000, + 0x02050027, + 0x02040000, + + 0x02050029, + 0x02040000, + 0x0205002A, + 0x02041640, + + 0x0205002B, + 0x02041640, + 0x02050021, + 0x02040C00, + + 0x02050023, + 0x02040C00, + 0x02050025, + 0x02040C00, + + 0x02050027, + 0x02040C00, + 0x02050029, + 0x02040C00, + + 0x0205002A, + 0x02041641, + 0x0205002B, + 0x02041641, + + 0x02050030, + 0x02049251, + 0x0205002A, + 0x02041649, + + 0x0205002B, + 0x02041649, + 0x0205000C, + 0x02043F06, + + 0x02050007, + 0x0204F808, + 0x02050007, + 0x0204F808, + + /* RaptorLake HDMI */ + 0x8086280f, /* Vendor ID */ 0x80860101, /* Subsystem ID */ 10, /* Number of entries */ AZALIA_SUBVENDOR(2, 0x80860101), - AZALIA_PIN_CFG(2, 0x04, 0x18560010), - AZALIA_PIN_CFG(2, 0x06, 0x18560010), - AZALIA_PIN_CFG(2, 0x08, 0x18560010), - AZALIA_PIN_CFG(2, 0x0a, 0x18560010), - AZALIA_PIN_CFG(2, 0x0b, 0x18560010), - AZALIA_PIN_CFG(2, 0x0c, 0x18560010), - AZALIA_PIN_CFG(2, 0x0d, 0x18560010), - AZALIA_PIN_CFG(2, 0x0e, 0x18560010), - AZALIA_PIN_CFG(2, 0x0f, 0x18560010), + 0x00278111, + 0x00278111, + 0x00278111, + 0x00278111, + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x00278100, + 0x00278100, + 0x00278100, + 0x00278100 }; + const u32 pc_beep_verbs[] = {}; AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/msi/ms7e06/mainboard.c b/src/mainboard/msi/ms7e06/mainboard.c index 2645f075d1f..be30b6fbabf 100644 --- a/src/mainboard/msi/ms7e06/mainboard.c +++ b/src/mainboard/msi/ms7e06/mainboard.c @@ -1,12 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include -#include #include #include #include #include +#include + + +#define MSR_ATOM_TURBO_RATIO_LIMIT 0x650 +#define MSR_ATOM_TURBO_RATIO_LIMIT_CORES 0x651 +#define MSR_BIGCORE_TURBO_RATIO_LIMIT 0x1ad +#define MSR_BIGCORE_TURBO_RATIO_LIMIT_CORES 0x1ae void mainboard_fill_fadt(acpi_fadt_t *fadt) @@ -17,51 +25,32 @@ void mainboard_fill_fadt(acpi_fadt_t *fadt) static void mainboard_init(void *chip_info) { -} - -u8 smbios_mainboard_feature_flags(void) -{ - return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; -} + struct device *ps2_dev = dev_find_slot_pnp(0x4e, NCT6687D_KBC); + bool ps2_en = get_ps2_option(); -smbios_wakeup_type smbios_system_wakeup_type(void) -{ - return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; -} - -const char *smbios_system_product_name(void) -{ - return "MS-7E06"; + ps2_dev->enabled = ps2_en & 1; + printk(BIOS_DEBUG, "PS2 Controller state: %d\n", ps2_en); } -const char *smbios_mainboard_product_name(void) +static void fill_turbo_ratio_limits(FSP_S_CONFIG *params) { - if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4)) { - if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) - return "PRO Z790-P WIFI DDR4(MS-7E06)"; - else - return "PRO Z790-P DDR4(MS-7E06)"; - } + msr_t msr; - if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI)) { - if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) - return "PRO Z790-P WIFI (MS-7E06)"; - else - return "PRO Z790-P (MS-7E06)"; - } + msr = rdmsr(MSR_BIGCORE_TURBO_RATIO_LIMIT); + memcpy(¶ms->TurboRatioLimitRatio[0], &msr.lo, 4); + memcpy(¶ms->TurboRatioLimitRatio[4], &msr.hi, 4); - return CONFIG_MAINBOARD_PART_NUMBER; -} + msr = rdmsr(MSR_BIGCORE_TURBO_RATIO_LIMIT_CORES); + memcpy(¶ms->TurboRatioLimitNumCore[0], &msr.lo, 4); + memcpy(¶ms->TurboRatioLimitNumCore[4], &msr.hi, 4); -/* Only baseboard serial number is populated */ -const char *smbios_system_serial_number(void) -{ - return "Default string"; -} + msr = rdmsr(MSR_ATOM_TURBO_RATIO_LIMIT); + memcpy(¶ms->AtomTurboRatioLimitRatio[0], &msr.lo, 4); + memcpy(¶ms->AtomTurboRatioLimitRatio[4], &msr.hi, 4); -const char *smbios_system_sku(void) -{ - return "Default string"; + msr = rdmsr(MSR_ATOM_TURBO_RATIO_LIMIT_CORES); + memcpy(¶ms->AtomTurboRatioLimitNumCore[0], &msr.lo, 4); + memcpy(¶ms->AtomTurboRatioLimitNumCore[4], &msr.hi, 4); } void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -171,6 +160,12 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->SataPortsSolidStateDrive[6] = 1; // M2_3 params->SataPortsSolidStateDrive[7] = 1; // M2_4 params->SataLedEnable = 1; + + /* + * If OcLock is not set in FSP-M UPD, FSP-S UPD will take and program + * zeroed turbo ratio limits. Avoid this by populating defautl values here. + */ + fill_turbo_ratio_limits(params); } #if CONFIG(GENERATE_SMBIOS_TABLES) @@ -528,7 +523,12 @@ static void mainboard_enable(struct device *dev) #endif } +static void mainboard_final(void *chip_info) +{ +} + struct chip_operations mainboard_ops = { .init = mainboard_init, .enable_dev = mainboard_enable, + .final = mainboard_final, }; diff --git a/src/mainboard/msi/ms7e06/msi_id.S b/src/mainboard/msi/ms7e06/msi_id.S new file mode 100644 index 00000000000..2633ada4b74 --- /dev/null +++ b/src/mainboard/msi/ms7e06/msi_id.S @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +.section .init, "a", @progbits + +/* The following structures must reside in the last 64KiB of flash */ + +.align 16 + +build_date: + .ascii "$MSESGN$" + .ascii "E7E06IMS." +#if CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR5) + .byte 'A' +#endif +#if CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4) + .byte '1' +#endif + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte ' ' + .asciz COREBOOT_DMI_DATE + +.align 8 + +msi_sign_on: + .ascii "$MS1E7E06IMS" +#if CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR5) + .byte 'A' +#endif +#if CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4) + .byte '1' +#endif + .byte 0x30 + DASHARO_MINOR_VERSION + .byte 0x30 + DASHARO_PATCH_VERSION + .byte 2 + +.align 8 + +bpa: + .ascii "$BPA" + .byte bpa_end - bpa + .byte 1 + .long 0x1000 + .long 6 + .byte 2 + .long 0x17c0000 + .long 0x20000 + .byte 3 + .long 0x1080000 + .long 64 + .byte 4 + .long 2 +bpa_end: + .byte 0, 0, 0, 0, 0 + + .asciz "@FC@" + .byte 2 + .byte 0 + .byte '1' + .asciz "/P /B /N" + .byte '2' + .byte 0 + .ascii "NULL" + .ascii "@@" + .fill 10, 1, 0 diff --git a/src/mainboard/msi/ms7e06/romhole.h b/src/mainboard/msi/ms7e06/romhole.h new file mode 100644 index 00000000000..f9ae37de919 --- /dev/null +++ b/src/mainboard/msi/ms7e06/romhole.h @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _ROMHOLE_H_ +#define _ROMHOLE_H_ + +#define ROMHOLE_MAGIC 0x10012501 +#define NUM_PWD_ENTRIES 2 +#define PWD_SIZE 40 +#define NUM_GD_ENTRIES 8 +#define GD_SIZE 48 +#define NUM_US_ENTRIES 8 +#define US_SIZE 0x3851 +#define TYPE2_SIZE 256 +#define FTB_SIZE 105 +#define FIB_SIZE 512 +#define FDP_SIZE 1024 +#define BUV_SIZE 1024 +#define NUM_VOLUMES 7 + +struct uuid_structure { + uint8_t magic0[4]; // always sSiD + uint16_t length; // structure length, always 0x1a + uint8_t magic1[3]; // awlays $uD + uint8_t space; // always 0x1 + uint8_t uuid[16]; // SMBIOS type 1 UUID +} __packed; + +struct pwd_entry { + uint8_t magic[3]; // always $s$ + uint8_t number; // ordinal number + uint8_t length; // length of pwd + uint8_t pwd[PWD_SIZE]; // password? +} __packed; + +struct pwd_structure { + uint8_t magic[4]; // always spWd + uint16_t length; // structure length + struct pwd_entry entries[NUM_PWD_ENTRIES]; +} __packed; + +struct gd_entry { + uint8_t magic[3]; // always $gD + uint8_t number; // ordinal number + uint16_t length; // length of gd + uint8_t gd[GD_SIZE]; // global data? +} __packed; + +struct gpdt_structure { + uint8_t magic[4]; // always gPdT + uint16_t length; // structure length + uint8_t num_entries; // number of entries + uint8_t space; // awlays zero + struct gd_entry entries[NUM_GD_ENTRIES]; +} __packed; + +struct us_entry { + uint8_t magic[3]; // always $uS + uint8_t number; // ordinal number + uint16_t length; // length of us + uint8_t us[US_SIZE]; // user data? +} __packed; + +struct ucsc_structure { + uint8_t magic[4]; // always uCsC + uint16_t length; // structure length + struct us_entry entries[NUM_US_ENTRIES]; +} __packed; + +struct type2_rw { + uint8_t magic0[4]; // always t2Rw + uint16_t length; // structure length + uint8_t magic1[3]; // always $tW + uint8_t space; // always 0x1 + uint8_t smbios_type2[TYPE2_SIZE]; // SMBIOS type2 table +} __packed; + +struct ftb_structure { + uint8_t magic0[4]; // always $FTB + uint16_t length; // structure length + uint8_t magic1[4]; // always $DIB + uint16_t space0; // always 0x2 + uint16_t size; // size of data field, always 105 + uint16_t space1; // always 0x0 + uint8_t magic2[4]; // always MFTD + uint8_t data[FTB_SIZE]; // default 0xfe +} __packed; + +struct fib_structure { + uint8_t magic0[4]; // always $FIB + uint16_t length; // structure length + uint16_t size; // size of data field, always 512 + uint8_t magic1[4]; // always $MFX + uint8_t data[FIB_SIZE]; // default 0xfa +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P since A.40/1.40 */ +struct fdp_structure { + uint8_t magic0[4]; // always $FDP + uint16_t length; // structure length + uint8_t magic1[3]; // always $Fd + uint8_t number; // always 0x1 + uint8_t data[FDP_SIZE]; // default 0xff +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P A.40/1.40 */ +struct buv_structure { + uint8_t magic0[4]; // always $BuV + uint16_t length; // structure length + uint8_t magic1[3]; // always $Bv + uint8_t number; // always 0x1 + uint8_t data[BUV_SIZE]; // default 0xff +} __packed; + +struct volume_entry { + uint8_t number; // ordinal number in ascii + uint32_t address; // volume base address + uint32_t size; // volume size + uint8_t space; // always 0xff +} __packed; + +struct ris_structure { + uint8_t magic0[4]; // always $RiS + uint16_t length; // structure length + uint8_t magic1[4]; // always $RiT + /* Array below keep the addresses and sizes of UEFI Firmware Volumes */ + struct volume_entry volumes[NUM_VOLUMES]; +} __packed; + +/* Place the following struct in the ROMHOLE flash region with 64K/128K alignment */ +struct msi_romhole { + uint32_t magic0; // 0x10012501 + uint16_t length; // length of the structure + char magic1[4]; // always SYSD + uint32_t address; // romhole address in flash + uint32_t size; // romhole total size + uint8_t pad0[48]; // always 0xff + struct uuid_structure uuid; + struct pwd_structure pwd; + struct gpdt_structure gpdt; + struct ucsc_structure ucsc; + struct type2_rw t2rw; + struct ftb_structure ftb; + struct fib_structure fib; + struct fdp_structure fdp; + struct buv_structure buv; + struct ris_structure ris; + // the rest is padded with 0xff by cbfstool +} __packed; + +#endif diff --git a/src/mainboard/msi/ms7e06/romstage_fsp_params.c b/src/mainboard/msi/ms7e06/romstage_fsp_params.c index c8955f7247a..ff4e04abe3d 100644 --- a/src/mainboard/msi/ms7e06/romstage_fsp_params.c +++ b/src/mainboard/msi/ms7e06/romstage_fsp_params.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -84,9 +85,13 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.MmioSize = 0xb00; /* 2.75GB in MB */ + memupd->FspmConfig.OcLock = 0; + + memupd->FspmConfig.SpdProfileSelected = dasharo_get_memory_profile(); + if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4)) memcfg_init(memupd, &ddr4_mem_config, &dimm_module_spd_info, false); - if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI)) + if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR5)) memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); diff --git a/src/mainboard/msi/ms7e06/smbios.c b/src/mainboard/msi/ms7e06/smbios.c new file mode 100644 index 00000000000..4d8397db926 --- /dev/null +++ b/src/mainboard/msi/ms7e06/smbios.c @@ -0,0 +1,148 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "romhole.h" + +struct smbios_type2_v3_4 { + struct smbios_header header; + u8 manufacturer; + u8 product_name; + u8 version; + u8 serial_number; + u8 asset_tag; + u8 feature_flags; + u8 location_in_chassis; + u16 chassis_handle; + u8 board_type; + u8 contained_objects; + u8 eos[2]; +} __packed; + +static struct msi_romhole *romhole_addr = NULL; + +static struct msi_romhole *get_msi_romhole_address(void) +{ + struct region_device rdev; + + if (romhole_addr) + return romhole_addr; + + if (fmap_locate_area_as_rdev("ROMHOLE", &rdev)) + return NULL; + + romhole_addr = (struct msi_romhole *)rdev_mmap_full(&rdev); + + return romhole_addr; +} + +u8 smbios_mainboard_feature_flags(void) +{ + return SMBIOS_FEATURE_FLAGS_HOSTING_BOARD | SMBIOS_FEATURE_FLAGS_REPLACEABLE; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +const char *smbios_system_product_name(void) +{ + return "MS-7E06"; +} + +const char *smbios_mainboard_product_name(void) +{ + if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR4)) { + if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) + return "PRO Z790-P WIFI DDR4 (MS-7E06)"; + else + return "PRO Z790-P DDR4 (MS-7E06)"; + } + + if (CONFIG(BOARD_MSI_Z790_P_PRO_WIFI_DDR5)) { + if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI)) + return "PRO Z790-P WIFI (MS-7E06)"; + else + return "PRO Z790-P (MS-7E06)"; + } + + return CONFIG_MAINBOARD_PART_NUMBER; +} + +/* Only baseboard serial number is populated */ +const char *smbios_system_serial_number(void) +{ + return "Default string"; +} + +const char *smbios_system_sku(void) +{ + return "Default string"; +} + +void smbios_system_set_uuid(u8 *uuid) +{ + if (!get_msi_romhole_address()) + return; + + memcpy(uuid, romhole_addr->uuid.uuid, 16); +} + +static const char* get_smbios_string(u8 *str_table_start, u8 string_index, + const char *fallback) +{ + u8 i; + char *smbios_str = (char *)str_table_start; + + for (i = 1; i < string_index; i++) { + if (strlen(smbios_str)) + smbios_str += strlen(smbios_str) + 1; + else + return fallback; + } + + return strlen(smbios_str) ? (const char *)smbios_str : fallback; +} + +const char *smbios_mainboard_serial_number(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_SERIAL_NUMBER; + + return get_smbios_string(type2->eos, type2->serial_number, + CONFIG_MAINBOARD_SERIAL_NUMBER); +} + +const char *smbios_mainboard_version(void) +{ + struct smbios_type2_v3_4 *type2; + + if (!get_msi_romhole_address()) + return CONFIG_MAINBOARD_VERSION; + + type2 = (struct smbios_type2_v3_4 *)romhole_addr->t2rw.smbios_type2; + /* Do some sanity checks first */ + if (type2->header.type != 2 || + type2->header.length == 0 || + type2->header.length == 0xff || + smbios_string_table_len(type2->eos) == 0) + return CONFIG_MAINBOARD_VERSION; + + return get_smbios_string(type2->eos, type2->version, + CONFIG_MAINBOARD_VERSION); +} diff --git a/src/mainboard/msi/ms7e06/smihandler.c b/src/mainboard/msi/ms7e06/smihandler.c new file mode 100644 index 00000000000..3978d4fcef1 --- /dev/null +++ b/src/mainboard/msi/ms7e06/smihandler.c @@ -0,0 +1,59 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#define POWER_DEV PNP_DEV(0x4e, NCT6687D_SLEEP_PWR) +#define ACPI_DEV PNP_DEV(0x4e, NCT6687D_ACPI) + +#define NUVOTON_ENTRY_KEY 0x87 +#define NUVOTON_EXIT_KEY 0xAA + +static void nuvoton_pnp_enter_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_ENTRY_KEY, port); + outb(NUVOTON_ENTRY_KEY, port); +} + +static void nuvoton_pnp_exit_conf_state(pnp_devfn_t dev) +{ + u16 port = dev >> 8; + outb(NUVOTON_EXIT_KEY, port); +} + +static void disable_ps2_wake(void) +{ + uint8_t reg; + + pnp_set_logical_device(ACPI_DEV); + reg = pnp_read_config(ACPI_DEV, 0xe4); + reg &= ~0xc0; /* Disable keyboard and mouse wake via PSOUT# */ + reg &= ~0x08; /* Disable keyboard wake with any key */ + pnp_write_config(ACPI_DEV, 0xe4, reg); +} + +void mainboard_smi_sleep(u8 slp_typ) +{ + nuvoton_pnp_enter_conf_state(POWER_DEV); + pnp_set_logical_device(POWER_DEV); + + switch (slp_typ) { + case 3: + pnp_write_config(POWER_DEV, 0xe7, 0x20); /* Keep LED freq at S3-S5 */ + pnp_write_config(POWER_DEV, 0xe8, 0x05); /* Blink LED at 1Hz */ + break; + case 4: + pnp_write_config(POWER_DEV, 0xe7, 0x88); /* Set AUTO_EN */ + pnp_write_config(POWER_DEV, 0xe8, 0x07); /* LED to low */ + break; + case 5: + pnp_write_config(POWER_DEV, 0xe7, 0x88); /* Set AUTO_EN */ + pnp_write_config(POWER_DEV, 0xe8, 0x07); /* LED to low */ + disable_ps2_wake(); + break; + } + + nuvoton_pnp_exit_conf_state(POWER_DEV); +} diff --git a/src/mainboard/msi/ms7e06/vboot-rwab.fmd b/src/mainboard/msi/ms7e06/vboot-rwab.fmd index 665c8949bbe..7569cda7cc4 100644 --- a/src/mainboard/msi/ms7e06/vboot-rwab.fmd +++ b/src/mainboard/msi/ms7e06/vboot-rwab.fmd @@ -6,6 +6,10 @@ FLASH 32M { UNUSED 12M + SMMSTORE(PRESERVE) 256K + RESERVED(PRESERVE) 256K + BPA(PRESERVE) 128K + RW_MISC 320K { UNIFIED_MRC_CACHE(PRESERVE) { RECOVERY_MRC_CACHE 128K @@ -21,22 +25,25 @@ FLASH 32M { } CONSOLE 128K - SMMSTORE(PRESERVE) 256K HSPHY_FW(PRESERVE) 32K + BOOTSPLASH(CBFS) 2M - RW_SECTION_A 5264K { + RW_SECTION_A 4768K { VBLOCK_A 64K FW_MAIN_A(CBFS) RW_FWID_A 0x100 } - RW_SECTION_B 5264K { + # ROMHOLE must be at flash offset 0x17c0000 + ROMHOLE(PRESERVE) 128K + + RW_SECTION_B 4224K { VBLOCK_B 64K FW_MAIN_B(CBFS) RW_FWID_B 0x100 } - WP_RO 5M { + WP_RO 4M { RO_VPD(PRESERVE) 16K RO_SECTION { FMAP 2K diff --git a/src/mainboard/novacustom/Kconfig b/src/mainboard/novacustom/Kconfig new file mode 100644 index 00000000000..715832d7f0c --- /dev/null +++ b/src/mainboard/novacustom/Kconfig @@ -0,0 +1,16 @@ +if VENDOR_NOVACUSTOM + +choice + prompt "Mainboard model" + +source "src/mainboard/novacustom/*/Kconfig.name" + +endchoice + +source "src/mainboard/novacustom/*/Kconfig" +source "src/mainboard/clevo/*/Kconfig" + +config MAINBOARD_VENDOR + default "Notebook" + +endif # VENDOR_NOVACUSTOM diff --git a/src/mainboard/novacustom/Kconfig.name b/src/mainboard/novacustom/Kconfig.name new file mode 100644 index 00000000000..e135a635d52 --- /dev/null +++ b/src/mainboard/novacustom/Kconfig.name @@ -0,0 +1,2 @@ +config VENDOR_NOVACUSTOM + bool "NovaCustom" diff --git a/src/mainboard/novacustom/adl-p/Kconfig b/src/mainboard/novacustom/adl-p/Kconfig new file mode 100644 index 00000000000..39d893af199 --- /dev/null +++ b/src/mainboard/novacustom/adl-p/Kconfig @@ -0,0 +1,9 @@ +config BOARD_NOVACUSTOM_NS5X_ADLP + select BOARD_CLEVO_NS50PU_BASE + +config BOARD_NOVACUSTOM_NV4X_ADLP + select BOARD_CLEVO_NV40PZ_BASE + +config MAINBOARD_PART_NUMBER + default "nv40pz" if BOARD_NOVACUSTOM_NV4X_ADLP + default "ns50pu" if BOARD_NOVACUSTOM_NS5X_ADLP diff --git a/src/mainboard/novacustom/adl-p/Kconfig.name b/src/mainboard/novacustom/adl-p/Kconfig.name new file mode 100644 index 00000000000..5b2fe3b89b4 --- /dev/null +++ b/src/mainboard/novacustom/adl-p/Kconfig.name @@ -0,0 +1,7 @@ +comment "Alder Lake P (2022)" + +config BOARD_NOVACUSTOM_NS5X_ADLP + bool "NS5x ADL" + +config BOARD_NOVACUSTOM_NV4X_ADLP + bool "NV4x ADL" diff --git a/src/mainboard/novacustom/adl-p/board_info.txt b/src/mainboard/novacustom/adl-p/board_info.txt new file mode 100644 index 00000000000..2820c1d1e74 --- /dev/null +++ b/src/mainboard/novacustom/adl-p/board_info.txt @@ -0,0 +1,7 @@ +Vendor name: NovaCustom +Board name: adl-p +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/novacustom/mtl-h/Kconfig b/src/mainboard/novacustom/mtl-h/Kconfig new file mode 100644 index 00000000000..9e38968c379 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig @@ -0,0 +1,159 @@ +config BOARD_NOVACUSTOM_MTLH_COMMON + def_bool n + select BOARD_ROMSIZE_KB_32768 + select DRIVERS_GENERIC_BAYHUB_LV2 + select DRIVERS_I2C_HID + select DRIVERS_INTEL_PMC + select DRIVERS_INTEL_USB4_RETIMER + select DRIVERS_WIFI_GENERIC + select EC_ACPI + select EC_DASHARO_EC + select HAVE_ACPI_TABLES + select HAVE_CMOS_DEFAULT + select HAVE_OPTION_TABLE + select INTEL_GMA_HAVE_VBT + select INTEL_LPSS_UART_FOR_CONSOLE + select MAINBOARD_HAS_TPM2 + select MEMORY_MAPPED_TPM + select NO_UART_ON_SUPERIO + select PMC_IPC_ACPI_INTERFACE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_CRASHLOG + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 + select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES + select SOC_INTEL_METEORLAKE_U_H + select SPD_READ_BY_WORD + select SYSTEM_TYPE_LAPTOP + +config BOARD_NOVACUSTOM_V5X0TNX_BASE + bool + select EC_DASHARO_EC_DGPU + select INCLUDE_NVIDIA_GPU_ASL + select BOARD_NOVACUSTOM_MTLH_COMMON + select DRIVERS_I2C_TAS5825M + +config BOARD_NOVACUSTOM_V540TNX + bool + select BOARD_NOVACUSTOM_V5X0TNX_BASE + +config BOARD_NOVACUSTOM_V560TNX + bool + select BOARD_NOVACUSTOM_V5X0TNX_BASE + +config BOARD_NOVACUSTOM_V5X0TU_BASE + bool + select MAINBOARD_USES_IFD_GBE_REGION + select BOARD_NOVACUSTOM_MTLH_COMMON + +config BOARD_NOVACUSTOM_V540TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +config BOARD_NOVACUSTOM_V560TU + bool + select BOARD_NOVACUSTOM_V5X0TU_BASE + +if BOARD_NOVACUSTOM_MTLH_COMMON + +config MAINBOARD_DIR + default "novacustom/mtl-h" + +config VARIANT_DIR + default "igpu" if BOARD_NOVACUSTOM_V5X0TU_BASE + default "dgpu" if BOARD_NOVACUSTOM_V5X0TNX_BASE + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config MAINBOARD_PART_NUMBER + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE + +config MAINBOARD_SMBIOS_PRODUCT_NAME + default "V54x_6x_TU" if BOARD_NOVACUSTOM_V5X0TU_BASE + default "V5xTNC_TND_TNE" if BOARD_NOVACUSTOM_V5X0TNX_BASE + +config MAINBOARD_SMBIOS_MANUFACTURER + default "Notebook" + +config MAINBOARD_VERSION + default "V540TU" if BOARD_NOVACUSTOM_V540TU + default "V560TU" if BOARD_NOVACUSTOM_V560TU + default "V540TNx" if BOARD_NOVACUSTOM_V540TNX + default "V560TNx" if BOARD_NOVACUSTOM_V560TNX + +config MAINBOARD_FAMILY + string + default "Not Applicable" # Match Insyde firmware + +config CBFS_SIZE + default 0xA00000 + +config CONSOLE_POST + default y + +config DIMM_SPD_SIZE + default 1024 + +config ONBOARD_VGA_IS_PRIMARY + default y + +config POST_DEVICE + default n + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_MOCK_SECDATA + select VBOOT_NO_BOARD_SUPPORT + +config VBOOT_SLOTS_RW_AB + default y if VBOOT + +config VBOOT_VBNV_OFFSET + default 0x28 + +config TPM_PIRQ + default 0x61 # GPP_E01 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwab.fmd" if VBOOT && VBOOT_SLOTS_RW_AB + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config VBOOT_FWID_VERSION + default "\$(CONFIG_LOCALVERSION)" + +config EC_DASHARO_EC_FLASH_SIZE + default 0x40000 + +config INCLUDE_NVIDIA_GPU_ASL + def_bool n + help + Select this if the variant has an Nvidia GPU attached to RP12 + +config PXE_ROM_ID + string + default "8086,550a" if BOARD_NOVACUSTOM_V5X0TU_BASE + +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 30 + +endif + +endif diff --git a/src/mainboard/novacustom/mtl-h/Kconfig.name b/src/mainboard/novacustom/mtl-h/Kconfig.name new file mode 100644 index 00000000000..f224cedd647 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Kconfig.name @@ -0,0 +1,13 @@ +comment "Meteor Lake H" + +config BOARD_NOVACUSTOM_V540TNX + bool "V540TU (14\", discrete graphics)" + +config BOARD_NOVACUSTOM_V560TNX + bool "V560TU (16\", discrete graphics)" + +config BOARD_NOVACUSTOM_V540TU + bool "V540TU (14\", integrated graphics)" + +config BOARD_NOVACUSTOM_V560TU + bool "V560TU (16\", integrated graphics)" diff --git a/src/mainboard/novacustom/mtl-h/Makefile.mk b/src/mainboard/novacustom/mtl-h/Makefile.mk new file mode 100644 index 00000000000..5b66f6c2176 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/Makefile.mk @@ -0,0 +1,16 @@ +# SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c + +romstage-y += romstage.c +romstage-y += variants/$(VARIANT_DIR)/gpio.c + +ramstage-y += ramstage.c +ramstage-y += variants/${VARIANT_DIR}/hda_verb.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-y += variants/$(VARIANT_DIR)/ramstage.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c +ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c diff --git a/src/mainboard/novacustom/mtl-h/acpi/backlight.asl b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl new file mode 100644 index 00000000000..01fa83ea610 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/backlight.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (GFX0) +{ + Name (BRIG, Package (23) { + 40, /* default AC */ + 40, /* default Battery */ + 0, + 5, + 10, + 15, + 20, + 25, + 30, + 35, + 40, + 45, + 50, + 55, + 60, + 65, + 70, + 75, + 80, + 85, + 90, + 95, + 100 + }) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl new file mode 100644 index 00000000000..8bf8954b82b --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gps.asl @@ -0,0 +1,96 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define GPS_FUNC_SUPPORT 0 +#define GPS_FUNC_GETCALLBACKS 0x13 +#define GPS_FUNC_PSHARESTATUS 0x20 +#define GPS_FUNC_PSHAREPARAMS 0x2a +#define GPS_FUNC_REQUESTDXSTATE 0x12 + +#define QUERY_GET_STATUS 0 +#define QUERY_GET_SUPPORTED_FIELDS 1 +#define QUERY_GET_CURRENT_LIMITS 2 + +/* GPS return Package */ +Name (GPSP, Buffer (0x24) {0x0}) +CreateDWordField (GPSP, 0, RETN) +CreateDWordField (GPSP, 4, VRV1) +CreateDWordField (GPSP, 8, TGPU) + +/* GETCALLBACKS return value + [0]: Callback for post-mode set + [1]: Callback for pre-mode set + [2]: Callback for post power state transition */ +Name (GPSR, Buffer (4) { 0x4, 0x0, 0x0, 0x0 }) + +Method (GPS, 2, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (GPS_FUNC_SUPPORT) + { + Return (LTOB( + (1 << GPS_FUNC_SUPPORT) | + (1 << GPS_FUNC_GETCALLBACKS) | + (1 << GPS_FUNC_PSHARESTATUS) | + (1 << GPS_FUNC_PSHAREPARAMS) | + (1 << GPS_FUNC_REQUESTDXSTATE))) + } + Case (GPS_FUNC_GETCALLBACKS) + { + CreateDWordField (Arg1, 0, QURY) + + /* Driver querying for which callbacks the ACPI code + wants callbacks for. */ + If (QURY == 0) + { + Return (GPSR) + } + + If (QURY & 0x4) + { + Printf("GPS: Kernel driver callback post power state transition") + Return (GPSR) + } + } + Case (GPS_FUNC_PSHARESTATUS) + { + Return (ITOB(0)) + } + Case (GPS_FUNC_PSHAREPARAMS) + { + CreateField (Arg1, 0, 4, QUTY) /* Query type */ + + /* Version of return value */ + VRV1 = 0x10000 + RETN = QUTY + + Switch (ToInteger (QUTY)) + { + Case (QUERY_GET_STATUS) + { + Return (GPSP) + } + Case (QUERY_GET_SUPPORTED_FIELDS) + { + RETN = 0x300 | ToInteger (QUTY) + CreateDWordField (GPSP, 0x0C, PDTS) + PDTS = 0x03e8 + Return (GPSP) + } + Case (QUERY_GET_CURRENT_LIMITS) + { + /* No limits */ + Return (GPSP) + } + } + } + Case (GPS_FUNC_REQUESTDXSTATE) + { + Local0 = ToInteger(\_SB.PCI0.LPCB.EC0.GPUD) + \_SB.PCI0.RP12.PXSX.DNOT (Local0, 1) + Return (NV_ERROR_SUCCESS) + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h new file mode 100644 index 00000000000..1cb03145b09 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_defines.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define NV_ERROR_SUCCESS 0x0 +#define NV_ERROR_UNSPECIFIED 0x80000001 +#define NV_ERROR_UNSUPPORTED 0x80000002 + +#define PCI_OWNER_SBIOS 0x0 +#define PCI_OWNER_DRIVER 0x1 + +#define OPTIMUS_POWER_CONTROL_DISABLE 0x2 +#define OPTIMUS_POWER_CONTROL_ENABLE 0x3 + +#define OPTIMUS_CONTROL_NO_RUN_PS0 0x0 +#define OPTIMUS_CONTROL_RUN_PS0 0x1 + +#define GC6_STATE_EXITED 0x0 +#define GC6_STATE_ENTERED 0x1 +#define GC6_STATE_TRANSITION 0x2 + +#define GC6_DEFER_DISABLE 0x0 +#define GC6_DEFER_ENABLE 0x1 + +#define NOTIFY_GPS_EVENT_STATUS_CHANGE 0xc0 +#define NOTIFY_GPS_NVPCF_STATUS_CHANGE 0xc5 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_0 0xd1 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_1 0xd2 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_2 0xd3 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_3 0xd4 +#define NOTIFY_GPS_EVENT_LIMIT_POWER_4 0xd5 + +/* Defines for NVJT subfunction */ +#define NVJT_GPC_GSS 0 +#define NVJT_GPC_EGNS 1 +#define NVJT_GPC_EGIS 2 +#define NVJT_GPS_XGXS 3 +#define NVJT_GPS_XGIS 4 + +#define UUID_NVOP "a486d8f8-0bda-471b-a72b-6042a6b5bee0" +#define UUID_NVJT "cbeca351-067b-4924-9cbd-b46b00b86f34" +#define UUID_NBCI "d4a50b75-65c7-46f7-bfb7-41514cea0244" +#define UUID_NVPCF "36b49710-2483-11e7-9598-0800200c9a66" +#define UUID_GPS "a3132d01-8cda-49ba-a52e-bc9d46df6b81" + +#define REVISION_MIN_NVOP 0x100 +#define REVISION_MIN_NVJT 0x100 +#define REVISION_MIN_NBCI 0x102 +#define REVISION_MIN_NVPCF 0x200 +#define REVISION_MIN_GPS 0x200 + +#define D1_EC 0 +#define D2_EC 1 +#define D3_EC 2 +#define D4_EC 3 +#define D5_EC 4 + +#define D1_GPU 0xD1 +#define D2_GPU 0xD2 +#define D3_GPU 0xD3 +#define D4_GPU 0xD4 +#define D5_GPU 0xD5 diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl new file mode 100644 index 00000000000..13b04294b69 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_ec.asl @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPCB.EC0) +{ + /* EC has data for GPU in memmap */ + Method (_QA0, 0, Serialized) + { + Local0 = ToInteger(GPUD) + \_SB.PCI0.RP12.PXSX.DNOT (Local0, 0) + } +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl new file mode 100644 index 00000000000..676d93c4a59 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/gpu_top.asl @@ -0,0 +1,92 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include "gpu_defines.h" + +Scope (\_SB.PCI0.RP12) +{ + #include "peg.asl" + + Device (PXSX) + { + Name (_ADR, 0x0) + OperationRegion (PCIC, PCI_Config, 0x00, 0x100) + Field (PCIC, DWordAcc, NoLock, Preserve) + { + NVID, 16, + NDID, 16, + Offset (0x40), + NVSS, 32 + } + + #include "utility.asl" + #include "power.asl" + #include "nvop.asl" + #include "nvjt.asl" + #include "nbci.asl" + #include "gps.asl" + #include "gpu_ec.asl" + + /* Convert D Notify from EC to GPU */ + Method (CNVD, 1, NotSerialized) + { + Switch (ToInteger(Arg0)) { + Case (D1_EC) { Return (D1_GPU) } + Case (D2_EC) { Return (D2_GPU) } + Case (D3_EC) { Return (D3_GPU) } + Case (D4_EC) { Return (D4_GPU) } + Case (D5_EC) { Return (D5_GPU) } + Default { Return (D5_GPU) } + } + } + + /* Current D Notify Value, defaults to D1 + * Arg0 == Shared value + * Arg1 == force notification if no change (0 or 1) + */ + Name (CDNV, D1_EC) + Method (DNOT, 2, Serialized) + { + Printf ("EC: GPU D-Notify, %o", Arg0) + If ((Arg0 != CDNV) || (Arg1 == 1)) + { + CDNV = Arg0 + Local0 = CNVD (Arg0) + Notify (\_SB.PCI0.RP12.PXSX, Local0) + } + } + + Method (_DSM, 4, Serialized) + { + If (Arg0 == ToUUID (UUID_NVOP)) + { + If (ToInteger(Arg1) >= REVISION_MIN_NVOP) + { + Return (NVOP (Arg2, Arg3)) + } + } + ElseIf (Arg0 == ToUUID (UUID_NVJT)) + { + If (ToInteger (Arg1) >= REVISION_MIN_NVJT) + { + Return (NVJT (Arg2, Arg3)) + } + } + ElseIf (Arg0 == ToUUID (UUID_NBCI)) + { + If (ToInteger (Arg1) >= REVISION_MIN_NBCI) + { + Return (NBCI (Arg2, Arg3)) + } + } + ElseIf (Arg0 == ToUUID (UUID_GPS)) + { + If (ToInteger (Arg1) >= REVISION_MIN_GPS) + { + Return (GPS (Arg2, Arg3)) + } + } + + Return (NV_ERROR_UNSUPPORTED) + } + } +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl new file mode 100644 index 00000000000..1546928aef3 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nbci.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define NBCI_FUNC_SUPPORT 0 +#define NBCI_FUNC_GETOBJBYTYPE 16 +#define NBCI_FUNC_GETCALLBACKS 19 + +#define GPS_FUNC_GETCALLBACKS 0x13 + +Method (NBCI, 2, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (NBCI_FUNC_SUPPORT) + { + Return (ITOB( + (1 << NBCI_FUNC_SUPPORT) | + (1 << NBCI_FUNC_GETCALLBACKS))) + } + Case (NBCI_FUNC_GETCALLBACKS) + { + /* Re-use the GPS subfunction's GETCALLBACKS Method */ + Return (GPS (GPS_FUNC_GETCALLBACKS, Arg1)) + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl new file mode 100644 index 00000000000..2a0790167f6 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvjt.asl @@ -0,0 +1,128 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define JT_FUNC_SUPPORT 0 +#define JT_FUNC_CAPS 1 +#define JT_FUNC_POWERCONTROL 3 +#define JT_FUNC_PLATPOLICY 4 + +Method (NVJT, 2, Serialized) +{ + Switch (ToInteger(Arg0)) + { + Case (JT_FUNC_SUPPORT) + { + Return (ITOB( + (1 << JT_FUNC_SUPPORT) | + (1 << JT_FUNC_CAPS) | + (1 << JT_FUNC_POWERCONTROL))) + } + Case (JT_FUNC_CAPS) + { + Return (ITOB( + (1 << 0) | /* JTE: G-Sync NVSR Power Features Enabled */ + (1 << 0) | /* NVSE: NVSR Disabled */ + (2 << 3) | /* PPR: Panel Power Rail */ + (0 << 5) | /* SRPR: Self-Refresh Controller Power Rail */ + (0 << 6) | /* FBPR: FB Power Rail */ + (0 << 8) | /* GPR: GPU Power Rail */ + (0 << 10) | /* GCR: GC6 ROM */ + (1 << 11) | /* PTH: No SMI Handler */ + (0 << 12) | /* NOT: Supports Notify on GC6 State done */ + (1 << 13) | /* MHYB: MS Hybrid Support (deferred GC6) */ + (1 << 14) | /* RPC: Root Port Control */ + (2 << 15) | /* GC6 Version (GC6-R) */ + (0 << 17) | /* GEI: GC6 Exit ISR Support */ + (0 << 18) | /* GSW: GC6 Self Wakeup */ + (0x200 << 20))) /* MXRV: Highest Revision */ + } + Case (JT_FUNC_POWERCONTROL) + { + CreateField (Arg1, 0, 3, GPC) /* GPU Power Control */ + CreateField (Arg1, 4, 1, PPC) /* Panel Power Control */ + CreateField (Arg1, 14, 2, DFGC) /* Defer GC6 enter/exit */ + CreateField (Arg1, 16, 3, GPCX) /* Deferred GC6 exit */ + + /* Deferred GC6 entry/exit is requested */ + If (ToInteger(GPC) != 0 || ToInteger(DFGC) != 0) + { + DFEN = ToInteger(DFGC) + DFCI = ToInteger(GPC) + DFCO = ToInteger(GPCX) + } + + Local0 = Buffer (4) { 0x0 } + CreateField (Local0, 0, 3, CGCS) /* Current GC State */ + CreateField (Local0, 3, 1, CGPS) /* Current GPU power status */ + CreateField (Local0, 7, 1, CPSS) /* Current panel and SRC state */ + + /* Leave early if deferred GC6 is requested */ + If (DFEN != 0) + { + CGCS = 1 + CGPS = 1 + Return (Local0) + } + + Switch (ToInteger(GPC)) + { + /* Get GCU GCx Sleep Status */ + Case (NVJT_GPC_GSS) + { + If (PSTA () != 0) + { + CGPS = 1 + CGCS = 1 + } + Else + { + CGPS = 0 + CGCS = 3 + } + } + Case (NVJT_GPC_EGNS) + { + /* Enter GC6; no self-refresh */ + GC6I () + CPSS = 1 + CGCS = 0 + } + Case (NVJT_GPC_EGIS) + { + /* Enter GC6; enable self-refresh */ + GC6I () + If (ToInteger (PPC) == 0) + { + CPSS = 0 + } + CGCS = 0 + } + Case (NVJT_GPS_XGXS) + { + /* Exit GC6; stop self-refresh */ + GC6O () + CGCS = 1 + CGPS = 1 + If (ToInteger (PPC) != 0) + { + CPSS = 0 + } + } + Case (NVJT_GPS_XGIS) + { + /* Exit GC6 for self-refresh */ + GC6O () + CGCS = 1 + CGPS = 1 + If (ToInteger (PPC) != 0) + { + CPSS = 0 + } + } + } + + Return (Local0) + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl new file mode 100644 index 00000000000..1f534be5496 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/nvop.asl @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#define NVOP_FUNC_SUPPORT 0x00 +#define NVOP_FUNC_OPTIMUS_CAPS 0x1a +#define NVOP_FUNC_OPTIMUS_STATUS 0x1b + +Method (NVOP, 2, Serialized) +{ + Switch (ToInteger (Arg0)) + { + Case (NVOP_FUNC_SUPPORT) + { + Return (ITOB ( + (1 << NVOP_FUNC_SUPPORT) | + (1 << NVOP_FUNC_OPTIMUS_CAPS) | + (1 << NVOP_FUNC_OPTIMUS_STATUS))) + } + Case (NVOP_FUNC_OPTIMUS_CAPS) + { + CreateField(Arg1, 0, 1, FLUP) /* Flag Update */ + CreateField(Arg1, 1, 1, CSOT) /* Change configuration Space Owner Target */ + CreateField(Arg1, 2, 1, CSOW) /* Change configuration Space Owner Write */ + CreateField(Arg1, 24, 2, NPCE) /* New Power Control Enable setting */ + + /* Change Optimus power control capabilities */ + If (ToInteger (FLUP) != 0 && ToInteger (NPCE) != 0) + { + OPCS = NPCE + } + + /* Change PCI configuration space save/restore owner */ + If (ToInteger (CSOW) == 1) + { + PCIO = CSOT + } + + /* Current GPU Control Status */ + If (PSTA () == 1) + { + Local0 = 3 + } + Else + { + Local0 = 0 + } + + Return (ITOB ( + (1 << 0) | /* Optimus Enabled */ + (Local0 << 3) | /* Current GPU Control Status */ + (1 << 6) | /* Shared Discrete GPU Hotplug Capabilities */ + (0 << 7) | /* MUXed DDC/Aux Capabilities */ + (PCIO << 8) | /* PCIe Configuration Space Owner */ + (1 << 24) | /* Platform Optimus Power Capabilities */ + (3 << 27))) /* Optimus HD Audio Codec Capabilities */ + } + Case (NVOP_FUNC_OPTIMUS_STATUS) + { + Return (ITOB ( + (1 << 0) | /* Optimus Audio Codec Control */ + (0 << 2) | /* Request GPU Power State */ + (0 << 4) | /* Evaluate Requested GPU Power State */ + (0 << 5) | /* Request Optimus Adapter Policy */ + (0 << 7))) /* Evaluate Requested Optimus Adapter Selection */ + } + } + + Return (NV_ERROR_UNSUPPORTED) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl new file mode 100644 index 00000000000..ac0c17cbb2e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/peg.asl @@ -0,0 +1,99 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +External (\_SB.PCI0.RP12.PXSX.NPON, MethodObj) +External (\_SB.PCI0.RP12.PXSX.NPOF, MethodObj) + +OperationRegion (PCIC, PCI_Config, 0x00, 0x100) +Field (PCIC, AnyAcc, NoLock, Preserve) +{ + Offset (0x4a), + CEDR, 1, /* Correctable Error Detected, RW/1C/V */ + Offset (0x52), + , 13, + LASX, 1, /* Link Active Status */ + Offset (0x69), + , 2, + LREN, 1, /* LTR Enabled */ + Offset (0xe0), + , 7, + NCB7, 1, /* Scratch bit to save L2/3 state */ + Offset (0xe2), + , 2, + L23E, 1, /* L23_Rdy Entry request */ + L23R, 1 /* L23_Rdy Detect Transition */ +} + +/* L2/3 Entry sequence */ +Method (DL23, 0, Serialized) +{ + L23E = 1 + Local0 = 8 + While (Local0 > 0) + { + If (!L23E) + { + Break + } + + Sleep (2) + Local0-- + } + NCB7 = 1 +} + +/* L2/3 exit seqeuence */ +Method (LD23, 0, Serialized) +{ + If (!NCB7) + { + Return + } + + L23R = 1 + Local0 = 20 + While (Local0 > 0) + { + If (!L23R) + { + Break + } + + Sleep (2) + Local0-- + } + + NCB7 = 0 + Local0 = 8 + While (Local0 > 0) + { + If (LASX == 1) + { + Break + } + + Sleep (2) + Local0-- + } +} + +/* PEG Power Resource */ +PowerResource (PGPR, 0, 0) +{ + Method (_ON, 0, Serialized) + { + /* Power up GPU from GCOFF (or GC6 exit if deferred) */ + \_SB.PCI0.RP12.PXSX.NPON () + _STA = 1 + } + Method (_OFF, 0, Serialized) + { + /* Power down GPU to GCOFF (or GC6 entry if deferred) */ + _STA = 0 + \_SB.PCI0.RP12.PXSX.NPOF () + } + Name (_STA, 0) +} + +Name (_PR0, Package() { PGPR }) +Name (_PR2, Package() { PGPR }) +Name (_PR3, Package() { PGPR }) diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl new file mode 100644 index 00000000000..496fd2c1476 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/power.asl @@ -0,0 +1,315 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +External (\_SB.PCI0.SPCO, MethodObj) + + +/* Board specific defines */ + +/* PCI Subsystem ID to restore after wake */ +#define GPU_SSID 0xa7611558 + +/* Power control signals */ +#define GPIO_GPU_PERST_L GPP_B09 +#define GPIO_GPU_PWR_EN GPP_D03 +#define GPIO_GPU_PWR_GD GPP_C15 +#define GPIO_GPU_NVVDD_EN GPP_F16 + +/* GPU clock pin */ +#define GPU_SRCCLK_PIN 0x6 + +#define GC6_DEFER_TYPE_EXIT_GC6 3 + +/* 250ms in "Timer" units (i.e. 100ns increments) */ +#define MIN_OFF_TIME_TIMERS 2500000 + +#define SRCCLK_DISABLE 0 +#define SRCCLK_ENABLE 1 + +#define GPU_POWER_STATE_OFF 0 +#define GPU_POWER_STATE_ON 1 + +/* Optimus Power Control State */ +Name (OPCS, OPTIMUS_POWER_CONTROL_DISABLE) + +/* PCI configuration space Owner */ +Name (PCIO, PCI_OWNER_SBIOS) + +/* Deferred GPU State */ +Name (OPS0, OPTIMUS_CONTROL_NO_RUN_PS0) + +/* GC6 Entry/Exit state */ +Name (GC6E, GC6_STATE_EXITED) + +/* Power State, GCOFF, GCON */ +Name (GPPS, GPU_POWER_STATE_ON) + +/* Defer GC6 entry / exit until D3-cold request */ +Name (DFEN, 0) +/* Deferred GC6 Enter control */ +Name (DFCI, 0) +/* Deferred GC6 Exit control */ +Name (DFCO, 0) +/* GCOFF Timer */ +Name (GCOT, 0) + +/* Copy of LTR enable bit from PEG port */ +Name (SLTR, 0) + +/* Control the PCIe SRCCLK# for dGPU */ +Method (SRCC, 1, Serialized) +{ + /* Control clock via P2SB interface */ + \_SB.PCI0.SPCO (GPU_SRCCLK_PIN, Arg0) +} + +/* "GC6 In", i.e. GC6 Entry Sequence */ +Method (GC6I, 0, Serialized) +{ + GC6E = GC6_STATE_TRANSITION + + /* Save the PEG port's LTR setting */ + SLTR = LREN + + /* Put PCIe link into L2/3 */ + \_SB.PCI0.RP12.DL23 () + + /* Wait for GPU to deassert its GPIO4, i.e. GPU_NVVDD_EN */ + GPPL (GPIO_GPU_NVVDD_EN, 0, 20) + + /* Assert GPU_PERST_L */ + CTXS (GPIO_GPU_PERST_L) + + /* Disable PCIe SRCCLK# */ + SRCC (SRCCLK_DISABLE) + + GC6E = GC6_STATE_ENTERED +} + +/* "GC6 Out", i.e. GC6 Exit Sequence */ +Method (GC6O, 0, Serialized) +{ + GC6E = GC6_STATE_TRANSITION + + /* Re-enable PCIe SRCCLK# */ + SRCC (SRCCLK_ENABLE) + + /* Deassert GPU_PERST_L */ + STXS (GPIO_GPU_PERST_L) + + /* Wait for GPU to assert GPU_NVVDD_EN */ + GPPL (GPIO_GPU_NVVDD_EN, 1, 20) + + /* Restore PCIe link back to L0 state */ + \_SB.PCI0.RP12.LD23 () + + /* Wait for dGPU to reappear on the bus */ + Local0 = 50 + While (NVID != PCI_VID_NVIDIA) + { + Stall (100) + Local0-- + If (Local0 == 0) + { + Break + } + } + + /* Restore the PEG LTR enable bit */ + LREN = SLTR + + /* Clear recoverable errors detected bit */ + CEDR = 1 + + GC6E = GC6_STATE_EXITED +} + +/* GCOFF exit sequence */ +Method (PGON, 0, Serialized) +{ + Local0 = Timer - GCOT + If (Local0 < MIN_OFF_TIME_TIMERS) + { + Local1 = (MIN_OFF_TIME_TIMERS - Local0) / 10000 + Printf("Sleeping %o to ensure min GCOFF time", Local1) + Sleep (Local1) + } + + /* Assert PERST# */ + CTXS (GPIO_GPU_PERST_L) + + /* Enable power rails */ + STXS (GPIO_GPU_PWR_EN) + + /* Wait 200ms for PWRGD */ + GPPL (GPIO_GPU_PWR_GD, 1, 200) + + /* Deassert PERST# */ + STXS (GPIO_GPU_PERST_L) + + GC6E = GC6_STATE_EXITED + GPPS = GPU_POWER_STATE_ON +} + +/* GCOFF entry sequence */ +Method (PGOF, 0, Serialized) +{ + /* Assert PERST# */ + CTXS (GPIO_GPU_PERST_L) + + /* Disable power rails */ + CTXS (GPIO_GPU_PWR_EN) + + GCOT = Timer + + GPPS = GPU_POWER_STATE_OFF +} + +/* GCOFF Out, i.e. full power-on sequence */ +Method (GCOO, 0, Serialized) +{ + If (GPPS == GPU_POWER_STATE_ON) + { + Printf ("PGON: GPU already on") + Return + } + + SRCC (SRCCLK_ENABLE) + PGON () + \_SB.PCI0.RP12.LD23 () + + /* Wait for dGPU to reappear on the bus */ + Local0 = 50 + While (NVID != PCI_VID_NVIDIA) + { + Stall (100) + Local0-- + If (Local0 == 0) + { + Break + } + } + + /* Restore the PEG LTR enable bit */ + LREN = SLTR + + /* Clear recoverable errors detected bit */ + CEDR = 1 + + /* Restore the PEG LTR enable bit */ + LREN = SLTR + + /* Clear recoverable errors detected bit */ + CEDR = 1 +} + +/* GCOFF In, i.e. full power-off sequence */ +Method (GCOI, 0, Serialized) +{ + If (GPPS == GPU_POWER_STATE_OFF) + { + Printf ("GPU already off") + Return + } + + /* Save the PEG port's LTR setting */ + SLTR = LREN + \_SB.PCI0.RP12.DL23 () + PGOF () + SRCC (SRCCLK_DISABLE) +} + +/* Handle deferred GC6 vs. poweron request */ +Method (NPON, 0, Serialized) +{ + If (DFEN == GC6_DEFER_ENABLE) + { + If (DFCO == GC6_DEFER_TYPE_EXIT_GC6) + { + GC6O () + } + + DFEN = GC6_DEFER_DISABLE + } + Else + { + GCOO () + } + NVSS = GPU_SSID +} + +/* Handle deferred GC6 vs. poweroff request */ +Method (NPOF, 0, Serialized) +{ + /* Don't touch the `DFEN` flag until the GC6 exit. */ + If (DFEN == GC6_DEFER_ENABLE) + { + /* Deferred GC6 entry */ + If (DFCI == NVJT_GPC_EGNS || DFCI == NVJT_GPC_EGIS) + { + GC6I () + } + } + Else + { + GCOI () + } +} + +Method (_ON, 0, Serialized) +{ + PGON () + NVSS = GPU_SSID +} + +Method (_OFF, 0, Serialized) +{ + PGOF () +} + +/* Put device into D0 */ +Method (_PS0, 0, NotSerialized) +{ + If (OPS0 == OPTIMUS_CONTROL_RUN_PS0) + { + /* Poweron or deferred GC6 exit */ + NPON () + + OPS0 = OPTIMUS_CONTROL_NO_RUN_PS0 + } +} + +/* Put device into D3 */ +Method (_PS3, 0, NotSerialized) +{ + If (OPCS == OPTIMUS_POWER_CONTROL_ENABLE) + { + /* Poweroff or deferred GC6 entry */ + NPOF () + + /* Because _PS3 ran NPOF, _PS0 must run NPON */ + OPS0 = OPTIMUS_CONTROL_RUN_PS0 + + /* OPCS is one-shot, so reset it */ + OPCS = OPTIMUS_POWER_CONTROL_DISABLE + } +} + +Method (PSTA, 0, Serialized) +{ + If (GC6E == GC6_STATE_EXITED && + \_SB.PCI0.GTXS(GPIO_GPU_PWR_GD) == 1) + { + Return (1) + } + Else + { + Return (0) + } +} + +Method (_STA, 0, Serialized) +{ + Return (0xF) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl b/src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl new file mode 100644 index 00000000000..49f3dca8e93 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/dgpu/utility.asl @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Poll a GPIO until it goes to the specified state + * Arg0 == GPIO # + * Arg1 == state (0 or 1) + * Arg2 == timeout in ms + */ +Method (GPPL, 3, Serialized) +{ + Local0 = 0 + Local1 = Arg2 * 10 + While (Local0 < Local1) + { + If (\_SB.PCI0.GRXS (Arg0) == Arg1) { + Return (0) + } Else { + Local0++ + } + Stall (100) + } + + If (Local0 == Arg2) { + Printf("[ERROR] GPPL for %o timed out", Arg0) + } + + Return (0xFF) +} + +/* Convert from 32-bit integer to 4-byte buffer (little-endian) */ +Method (ITOB, 1) +{ + Local0 = Buffer(4) { 0, 0, 0, 0 } + Local0[0] = Arg0 & 0xFF + Local0[1] = (Arg0 >> 8) & 0xFF + Local0[2] = (Arg0 >> 16) & 0xFF + Local0[3] = (Arg0 >> 24) & 0xFF + Return (Local0) +} + +/* Convert from 64-bit integer to 8-byte buffer (little-endian) */ +Method (LTOB, 1) +{ + Local0 = Buffer(8) { 0, 0, 0, 0, 0, 0, 0, 0 } + Local0[0] = Arg0 & 0xFF + Local0[1] = (Arg0 >> 8) & 0xFF + Local0[2] = (Arg0 >> 16) & 0xFF + Local0[3] = (Arg0 >> 24) & 0xFF + Local0[4] = (Arg0 >> 32) & 0xFF + Local0[5] = (Arg0 >> 40) & 0xFF + Local0[6] = (Arg0 >> 48) & 0xFF + Local0[7] = (Arg0 >> 56) & 0xFF + Return (Local0) +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl new file mode 100644 index 00000000000..43e4de4d500 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define EC_GPE_SCI 0x6E +#define EC_GPE_SWI 0x6B +#define CPU_CRIT_TEMP 100 +#define GPU_CRIT_TEMP 105 +#include + +Scope (\_SB) { + Scope (PCI0) { + #include "backlight.asl" + } +} diff --git a/src/mainboard/novacustom/mtl-h/acpi/touchpad.asl b/src/mainboard/novacustom/mtl-h/acpi/touchpad.asl new file mode 100644 index 00000000000..0ac407185f4 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/acpi/touchpad.asl @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +External (\_SB.PCI0.I2C0.H038, DeviceObj) +External (\_SB.PCI0.I2C0.H038._STA, IntObj) + +External (\_SB.PCI0.I2C0.H015, DeviceObj) +External (\_SB.PCI0.I2C0.H015._STA, IntObj) + +Method (TPTG, 0, Serialized) +{ + If (CondRefOf (\_SB.PCI0.I2C0.H038)) { + If (\_SB.PCI0.I2C0.H038._STA == Zero) { + \_SB.PCI0.I2C0.H038._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H038._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H038, One) + } + + If (CondRefOf (\_SB.PCI0.I2C0.H015)) { + If (\_SB.PCI0.I2C0.H015._STA == Zero) { + \_SB.PCI0.I2C0.H015._STA = 0xF + } Else { + \_SB.PCI0.I2C0.H015._STA = 0x0 + } + Notify (\_SB.PCI0.I2C0.H015, One) + } +} diff --git a/src/mainboard/novacustom/mtl-h/board_info.txt b/src/mainboard/novacustom/mtl-h/board_info.txt new file mode 100644 index 00000000000..5220e452c84 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Clevo +Category: laptop +ROM package: WSON-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/novacustom/mtl-h/bootblock.c b/src/mainboard/novacustom/mtl-h/bootblock.c new file mode 100644 index 00000000000..7bd8493df5c --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/bootblock.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_uart_gpio_table[] = { + /* UART0 */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ +}; + +void bootblock_mainboard_early_init(void) +{ + gpio_configure_pads(early_uart_gpio_table, ARRAY_SIZE(early_uart_gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/cmos.default b/src/mainboard/novacustom/mtl-h/cmos.default new file mode 100644 index 00000000000..972deace70b --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.default @@ -0,0 +1,5 @@ +boot_option=Fallback +debug_level=Debug +me_state=Enable +kbl_brightness=0xff +kbl_color=0x00ffffff diff --git a/src/mainboard/novacustom/mtl-h/cmos.layout b/src/mainboard/novacustom/mtl-h/cmos.layout new file mode 100644 index 00000000000..fa2067eb9f0 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/cmos.layout @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: GPL-2.0-only + +entries + +0 304 r 0 reserved_memory + +# coreboot config options: ramtop +304 80 h 0 ramtop + +# RTC_BOOT_BYTE (coreboot hardcoded) +384 1 e 4 boot_option +388 4 h 0 reboot_counter + +# RTC_CLK_ALTCENTURY +400 8 r 0 century + +412 4 e 6 debug_level +416 1 e 2 me_state +417 3 h 0 me_state_counter + +# Vboot non-volatile data +432 128 r 0 vbnv + +984 16 h 0 check_sum + +# embedded controller settings +1024 8 h 0 kbl_brightness +1032 32 h 0 kbl_color + +enumerations + +2 0 Enable +2 1 Disable + +4 0 Fallback +4 1 Normal + +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew + +checksums + +checksum 408 431 984 diff --git a/src/mainboard/novacustom/mtl-h/devicetree.cb b/src/mainboard/novacustom/mtl-h/devicetree.cb new file mode 100644 index 00000000000..fc5c93fcc2e --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/devicetree.cb @@ -0,0 +1,267 @@ +chip soc/intel/meteorlake + # Common SoC configuration + register "common_soc_config" = "{ + // Touchpad I2C bus + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + # Enable Enhanced Intel SpeedStep + register "eist_enable" = "1" + + # Enable S0ix / Modern Standby + register "s0ix_enable" = "1" + + # SaGv configuration + register "sagv" = "SAGV_ENABLED" + + # Enable Energy Reporting + register "pch_pm_energy_report_enable" = "1" + + # Thermal + register "tcc_offset" = "30" # TCC of 80C + + device cpu_cluster 0 on end + device domain 0 on + device ref system_agent on end + device ref igpu on + register "ddi_port_A_config" = "1" + register "gfx" = "GMA_DEFAULT_PANEL(0)" + end + device ref dtt on end + device ref pcie_rp10 on # M.2 2280 #2 + register "pcie_rp[PCH_RP(10)]" = "{ + .clk_src = 8, + .clk_req = 8, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D01)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + register "srcclk_pin" = "8" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD2)" "SlotDataBusWidth4X" + end + device ref pcie_rp11 on # M.2 2280 #1 + register "pcie_rp[PCH_RP(11)]" = "{ + .clk_src = 7, + .clk_req = 7, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "is_storage" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D05)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D02)" + register "srcclk_pin" = "7" + device generic 0 on end + end + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J_SSD1)" "SlotDataBusWidth4X" + end + device ref tbt_pcie_rp0 on end + device ref gna on end + device ref crashlog on end + device ref vpu on end + device ref tcss_xhci on + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # Bits (4,5) allocated for TCSS Port3 configuration and Bits (6,7)for TCSS Port4. + # Bit0,Bit2,Bit4,Bit6 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3,Bit5,Bit7 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0x54" + + register "tcss_ports" = "{ + [0] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 1 (TBT) */ + [1] = TCSS_PORT_DEFAULT(OC_SKIP), /* USB Type-C Port 2 (Non-TBT) */ + }" + + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref tcss_usb3_port1 on end + end + end + end + end + device ref tcss_dma0 on + chip drivers/intel/usb4/retimer + register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B21)" + use tcss_usb3_port0 as dfp[0].typec_port + device generic 0 on end + end + end + device ref ioe_shared_sram on end + device ref xhci on + + register "usb2_ports" = "{ + [0] = USB2_PORT_LONG(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB2_PORT_MID(OC_SKIP), /* USB Type-C Port 1 (Non-TBT) */ + [2] = USB2_PORT_MID(OC_SKIP), /* USB Type-A Port 2 (Right) */ + [5] = USB2_PORT_TYPE_C(OC_SKIP), /* USB Type-C Port 2 (TBT) */ + [6] = USB2_PORT_LONG(OC_SKIP), /* Integrated Camera */ + [9] = USB2_PORT_MID(OC_SKIP), /* Bluetooth on M.2 2230 */ + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 1 (Left) */ + [1] = USB3_PORT_DEFAULT(OC_SKIP), /* USB Type-A Port 2 (Right) */ + }" + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Left"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 2"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Right"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port 1 (TBT)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, CENTER, ACPI_PLD_GROUP(1, 2))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Left"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(2, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Right"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, RIGHT, ACPI_PLD_GROUP(1, 3))" + device ref usb3_port2 on end + end + end + end + end + device ref pmc_shared_sram on end + device ref cnvi_wifi on + register "cnvi_wifi_core" = "true" + register "cnvi_bt_core" = "true" + register "cnvi_bt_audio_offload" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c1 on # USB-PD EEPROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci" + end + device ref i2c3 on # Pantone ROM + register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci" + end + device ref pcie_rp6 on # SD Card Reader + register "pcie_rp[PCH_RP(6)]" = "{ + .clk_src = 3, + .clk_req = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/generic/bayhub_lv2 + register "enable_power_saving" = "1" + device pci 00.0 on end + end + end + device ref pcie_rp8 on # M.2 2230 + register "pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 5, + .clk_req = 5, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW2_09" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230 (J_WLAN1)" "SlotDataBusWidth1X" + end + device ref uart0 on # BIOS Debug Port + register "serial_io_uart_mode[PchSerialIoIndexUART0]" = "PchSerialIoPci" + end + device ref soc_espi on + register "gen1_dec" = "0x00040069" # EC PM channel + register "gen2_dec" = "0x00fc0e01" # AP/EC command + register "gen3_dec" = "0x00fc0f01" # AP/EC debug + chip drivers/pc80/tpm # SLB 9672 TPM 2.0 + device pnp 0c31.0 on end + end + end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_V" + register "pmc_gpe0_dw1" = "PMC_GPP_B" + register "pmc_gpe0_dw2" = "PMC_GPP_S" + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + # USB Type-C Port 1 (TBT) + use usb2_port6 as usb2_port + use tcss_usb3_port0 as usb3_port + device generic 0 alias conn0 on end + end + end + end + end + device ref hda on + subsystemid 0x1558 0xa763 + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_sdi_enable[0]" = "1" + register "pch_hda_dsp_enable" = "1" + register "pch_hda_idisp_codec_enable" = "1" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + + end + device ref smbus on end + device ref fast_spi on end + device ref gbe on end + end +end diff --git a/src/mainboard/novacustom/mtl-h/dsdt.asl b/src/mainboard/novacustom/mtl-h/dsdt.asl new file mode 100644 index 00000000000..b12077ebc8d --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/dsdt.asl @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + #include + #include + } + + /* Chipset specific sleep states */ + #include + + Scope (\_SB.PCI0.LPCB) + { + #include + } + + #include "acpi/mainboard.asl" + #include "acpi/touchpad.asl" + +#if CONFIG(INCLUDE_NVIDIA_GPU_ASL) + #include "acpi/dgpu/gpu_top.asl" +#endif +} diff --git a/src/mainboard/novacustom/mtl-h/fadt.c b/src/mainboard/novacustom/mtl-h/fadt.c new file mode 100644 index 00000000000..f983717e096 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/fadt.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_MOBILE; +} diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h new file mode 100644 index 00000000000..db1dd7dfe5a --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/include/mainboard/gpio.h @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h b/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h new file mode 100644 index 00000000000..50935c8b99c --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/include/mainboard/variants.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_VARIANTS_H +#define MAINBOARD_VARIANTS_H + +void variant_devtree_update(void); +void variant_final(void); + +#endif diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c new file mode 100644 index 00000000000..2d5a0323e01 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/ramstage.c @@ -0,0 +1,273 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +struct smfi_cmd_set_fan_curve { + uint8_t fan; + struct fan_curve curve; +} __packed; + +struct fan_curve fan_curve_silent = { + { .temp = 0, .duty = 20 }, + { .temp = 65, .duty = 25 }, + { .temp = 75, .duty = 35 }, + { .temp = 85, .duty = 100 } +}; + +struct fan_curve fan_curve_performance = { + { .temp = 0, .duty = 25 }, + { .temp = 55, .duty = 35 }, + { .temp = 75, .duty = 60 }, + { .temp = 85, .duty = 100} +}; + +const char *smbios_system_sku(void) +{ + return "Not Applicable"; +} + +smbios_enclosure_type smbios_mainboard_enclosure_type(void) +{ + return SMBIOS_ENCLOSURE_NOTEBOOK; +} + +smbios_wakeup_type smbios_system_wakeup_type(void) +{ + return SMBIOS_WAKEUP_TYPE_POWER_SWITCH; +} + +static void set_fan_curve(void) +{ + int i; + uint8_t selection = get_fan_curve_option(); + struct smfi_cmd_set_fan_curve cmd; + + switch (selection) { + case FAN_CURVE_OPTION_PERFORMANCE: + cmd.curve = fan_curve_performance; + break; + case FAN_CURVE_OPTION_SILENT: + default: + cmd.curve = fan_curve_silent; + break; + } + + for (i = 0; i < (CONFIG(EC_DASHARO_EC_DGPU) ? 2 : 1); ++i) { + cmd.fan = i; + dasharo_ec_smfi_cmd(CMD_FAN_CURVE_SET, sizeof(cmd), (uint8_t *)&cmd); + } +} + +static void set_camera_enablement(void) +{ + bool enabled = get_camera_option(); + + dasharo_ec_smfi_cmd(CMD_CAMERA_ENABLEMENT_SET, sizeof(enabled), (uint8_t *)&enabled); +} + +static void set_battery_thresholds(void) +{ + struct battery_config bat_cfg; + + get_battery_config(&bat_cfg); + + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_START, bat_cfg.start_threshold); + dasharo_ec_set_bat_threshold(BAT_THRESHOLD_STOP, bat_cfg.stop_threshold); +} + +static void set_power_on_ac(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_POWER_ON_AC, + 0 + }; + + cmd.value = dasharo_get_power_on_after_fail(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd), (uint8_t *)&cmd); +} + +static void set_usb_charge_port(void) +{ + struct smfi_option_get_cmd { + uint8_t index; + uint8_t value; + } __packed cmd = { + OPT_ALWAYS_ON_USB, + 0 + }; + + cmd.value = dasharo_get_usb_port_power(); + + dasharo_ec_smfi_cmd(CMD_OPTION_SET, sizeof(cmd) / sizeof(uint8_t), (uint8_t *)&cmd); +} + +void __weak variant_devtree_update(void) +{ + /* Override dev tree settings per board */ +} + +static void mainboard_init(void *chip_info) +{ + config_t *cfg = config_of_soc(); + struct device *wlan_dev = pcidev_on_root(0x1c, 7); + struct device *cnvi_dev = pcidev_on_root(0x14, 3); + bool radio_enable = get_wireless_option(); + + printk(BIOS_DEBUG, "Wireless is %sabled\n", radio_enable ? "en" : "dis"); + + wlan_dev->enabled = radio_enable; + cnvi_dev->enabled = radio_enable; + cfg->cnvi_bt_core = radio_enable; + cfg->cnvi_bt_audio_offload = radio_enable; + cfg->cnvi_wifi_core = radio_enable; + cfg->usb2_ports[9].enable = radio_enable; + + dasharo_ec_smfi_cmd(CMD_WIFI_BT_ENABLEMENT_SET, 1, (uint8_t *)&radio_enable); + + set_fan_curve(); + set_camera_enablement(); + set_battery_thresholds(); + set_power_on_ac(); + set_usb_charge_port(); + + variant_devtree_update(); +} + +#if CONFIG(GENERATE_SMBIOS_TABLES) +static uint8_t read_proprietary_ec_version(uint8_t *data) +{ + int i, result; + char ec_version[16]; + + if (!data) + return -1; + + if (send_ec_command(0x93)) + return -1; + + for (i = 0; i < 16 - 1; i++) { + + result = recv_ec_data(); + if (result != -1) + ec_version[i] = result & 0xff; + + if (ec_version[i] == '$') { + ec_version[i] = '\0'; + break; + } + } + ec_version[15] = '\0'; + + data[0] = '1'; + data[1] = '.'; + + strcpy((char *)&data[2], ec_version); + + return 0; +} + +static void mainboard_smbios_strings(struct device *dev, struct smbios_type11 *t) +{ + char ec_version[256]; + uint8_t result; + + result = dasharo_ec_read_version((uint8_t *)ec_version); + + /* If the command fails it mean we are running proprietary EC most likely */ + if (result != 0) { + printk(BIOS_ERR, "Failed to read open EC firmware version\n"); + result = read_proprietary_ec_version((uint8_t *)ec_version); + if (result == 0) + t->count = smbios_add_string(t->eos, "EC: proprietary"); + else + t->count = smbios_add_string(t->eos, "EC: unknown"); + } else { + t->count = smbios_add_string(t->eos, "EC: open-source"); + } + + if (result == 0) { + printk(BIOS_DEBUG, "EC firmware version: %s\n", ec_version); + t->count = smbios_add_string(t->eos, strconcat("EC firmware version: ", + ec_version)); + } else { + printk(BIOS_ERR, "Unable to probe EC firmware version\n"); + t->count = smbios_add_string(t->eos, "EC firmware version: unknown"); + } + +} +#endif + + +static void mainboard_enable(struct device *dev) +{ +#if CONFIG(GENERATE_SMBIOS_TABLES) + dev->ops->get_smbios_strings = mainboard_smbios_strings; +#endif +} + +void mainboard_update_soc_chip_config(struct soc_intel_meteorlake_config *config) +{ + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S3) + config->s0ix_enable = 0; + else + config->s0ix_enable = 1; +} + +void __weak variant_final(void) +{ + +} + +static void mainboard_final(void *chip_info) +{ + variant_final(); +} + +struct chip_operations mainboard_ops = { + .enable_dev = mainboard_enable, + .init = mainboard_init, + .final = mainboard_final, +}; + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + // Enable reporting CPU C10 state over eSPI + params->PchEspiHostC10ReportEnable = 1; + + // Pinmux configuration + params->PchSerialIoI2cSdaPinMux[3] = 0x1A45CA06; // GPP_H6 + params->PchSerialIoI2cSclPinMux[3] = 0x1A45AA07; // GPP_H7 + + params->PchSerialIoI2cSdaPinMux[4] = 0x8A44CC0C; // GPP_E12 + params->PchSerialIoI2cSclPinMux[4] = 0x8A44AC0D; // GPP_E13 + + params->PchSerialIoI2cSdaPinMux[5] = 0x8A46CE0D; // GPP_F13 + params->PchSerialIoI2cSclPinMux[5] = 0x8A46AE0C; // GPP_F12 + + params->CnviRfResetPinMux = 0x194CE404; // GPP_F4 + params->CnviClkreqPinMux = 0x394CE605; // GPP_F5 + + params->EnableTcssCovTypeA[1] = 1; + + /* Disable S0i2.x due to wake issues */ + params->PmcLpmS0ixSubStateEnableMask = BIT(0); + + params->LidStatus = dasharo_ec_get_lid_state(); + + params->PortResetMessageEnable[1] = 1; + params->PortResetMessageEnable[5] = 1; +} diff --git a/src/mainboard/novacustom/mtl-h/romstage.c b/src/mainboard/novacustom/mtl-h/romstage.c new file mode 100644 index 00000000000..45ee2e4ebbb --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/romstage.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const bool half_populated = false; + + static const struct mb_cfg mem_config = { + .type = MEM_TYPE_DDR5, + + .rcomp = { + /* Values for MTL-H DDR5 2R */ + .resistor = 100, + + .targets = {70, 30, 25, 25, 25}, + }, + + .ect = true, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, + + .ddr_config = { + .dq_pins_interleaved = false, + } + }; + const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + [1] = { + .addr_dimm[0] = 0x52, + }, + }, + }; + + mainboard_configure_gpios(); + mupd->FspmConfig.PrimaryDisplay = 4; + mupd->FspmConfig.RootPortIndex = 11; + + /* The values come from Clevo firmware. */ + mupd->FspmConfig.AcLoadline[0] = 190; + mupd->FspmConfig.AcLoadline[1] = 310; + mupd->FspmConfig.AcLoadline[2] = 490; + mupd->FspmConfig.DcLoadline[0] = 190; + mupd->FspmConfig.DcLoadline[1] = 310; + mupd->FspmConfig.DcLoadline[2] = 490; + + mupd->FspmConfig.MmioSize = 2560; /* 2.5 GiB */ + + memcfg_init(mupd, &mem_config, &dimm_module_spd_info, half_populated); +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt b/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt new file mode 100644 index 00000000000..add19e3e7ff Binary files /dev/null and b/src/mainboard/novacustom/mtl-h/variants/dgpu/data.vbt differ diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c new file mode 100644 index 00000000000..c28550d4d59 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/gpio.c @@ -0,0 +1,339 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group CPU ------- */ + + /* ------- GPIO Group V ------- */ + PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), /* BATLOW# */ + PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), /* ACPRESENT */ + PAD_CFG_GPI_TRIG_OWN(GPP_V02, NATIVE, DEEP, OFF, ACPI), /* GPIO - CPU_LAN_WAKEUP# */ + PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), /* PWRBTN# */ + PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), /* SLP_S3# */ + PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), /* SLP_S4# */ + PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), /* SLP_A# */ + PAD_CFG_GPO(GPP_V07, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), /* SUSCLK */ + PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), /* SLP_WLAN# */ + PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), /* SLP_S5# */ + PAD_CFG_GPO(GPP_V11, 1, DEEP), /* GPIO - GPIO_LAN_EN */ + PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), /* SLP_LAN# */ + PAD_CFG_GPO(GPP_V13, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), /* WAKE# */ + PAD_CFG_GPO(GPP_V15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V18, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), /* n/a */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), /* SMBCLK */ + PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), /* SMBDATA */ + PAD_CFG_GPI_TRIG_OWN(GPP_C02, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), /* SML0CLK */ + PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), /* SML0DATA */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), /* SML1CLK */ + PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), /* SML1DATA */ + PAD_CFG_GPO(GPP_C08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C09, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), /* SRCCLKREQ2# */ + PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), /* SRCCLKREQ3# */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_C15, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_DGPU_PWRGD */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TBT_LSX0_TXD */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TBT_LSX0_RXD */ + PAD_CFG_GPO(GPP_C18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* GPIO */ + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), /* ESPI_IO0 */ + PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), /* ESPI_IO1 */ + PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), /* ESPI_IO2 */ + PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), /* ESPI_IO3 */ + PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), /* ESPI_CS0# */ + PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), /* ESPI_CLK */ + PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), /* ESPI_RESET# */ + PAD_CFG_GPO(GPP_A07, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A09, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), /* GPIO - ADDS_CODE */ + PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), /* GPIO - WLAN_WAKEUP# */ + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), /* GPIO - M2_SSD2_RST# */ + PAD_CFG_GPI_TRIG_OWN(GPP_A14, UP_20K, DEEP, OFF, ACPI), /* GPIO - NVVDD_ALERT# */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), /* GPIO - CPU_SWI# */ + PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), /* RSVD - ESPI_ALERT0# */ + PAD_CFG_GPI_INT(GPP_A17, NONE, PLTRST, LEVEL), /* GPIO - TP_ATTN# */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), /* GPIO - TEST_R (ANX7411) */ + PAD_CFG_GPI_APIC(GPP_A19, NONE, DEEP, LEVEL, NONE), /* GPIO - INTP_OUT (ANX7411) */ + PAD_CFG_GPO(GPP_A20, 1, DEEP), /* GPIO - LAN_PLT_RST# */ + PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), /* PMCALERT# */ + PAD_NC(GPP_A22, NATIVE), /* GPIO */ + PAD_NC(GPP_A23, NATIVE), /* GPIO */ + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPI_TRIG_OWN(GPP_E00, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID7 */ + PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), /* GPIO - TPM_PIRQ# */ + PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID4 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), /* GPIO - CPU_CNVI_WAKE# */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E05, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E06, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), /* GPIO - CPU_SMI# */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E09, 1, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID6 */ + PAD_CFG_NF(GPP_E12, NONE, DEEP, NF8), /* I2C4_SDA - ANX7411 */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF8), /* I2C4_SCL - ANX7411 */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDSP_HPDA */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), /* GPIO - CPU_SCI# */ + PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), /* VRALERT# */ + PAD_CFG_GPI_TRIG_OWN(GPP_E17, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID5 */ + PAD_CFG_GPO(GPP_E18, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), /* GPIO */ + PAD_NC(GPP_E23, NONE), /* GPIO */ + PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE), /* GPIO */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + PAD_CFG_GPO(GPP_H00, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H01, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H02, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H03, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_H04, NONE, DEEP, NF2), /* CNV_MFUART2_RXD */ + PAD_CFG_NF(GPP_H05, NONE, DEEP, NF2), /* CNV_MFUART2_TXD */ + PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), /* I2C3_SDA */ + PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), /* I2C3_SCL */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H11, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), /* PROC_C10_GATE# */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_H18, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), /* I2C0_SDA */ + PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), /* I2C0_SCL */ + PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), /* I2C1_SDA */ + PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), /* I2C1_SCL */ + PAD_NC(GPP_H23, NONE), /* GPIO */ + PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE), /* GPIO */ + PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2), /* n/a */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), /* CNV_BRI_DT */ + PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), /* CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), /* CNV_RGI_DT */ + PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), /* CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), /* CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), /* MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F06, NONE, DEEP, NF1), /* CNVI_GNSS_PA_BLANKING */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F08, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), /* GPIO - TPM_DET */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID3 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF8), /* I2C5_SCL - Smart AMP */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF8), /* I2C5_SDA - Smart AMP */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, NONE, DEEP, OFF, ACPI), /* GPIO - BOARD_ID2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, NONE, DEEP, OFF, ACPI), /* GPIO - GPIO4_GC6_NVVDD_EN */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, NONE, PLTRST, OFF, ACPI), /* GPIO - CPU_GC6_FB_EN */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), /* GPIO -CCD_WP# */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), /* GPIO */ + PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE), /* GPIO */ + PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE), /* GPIO */ + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Group VGPIO3 ------- */ + PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1), /* GPP_VGPIO3_USB0 */ + PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1), /* GPP_VGPIO3_USB1 */ + PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1), /* GPP_VGPIO3_USB2 */ + PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1), /* GPP_VGPIO3_USB3 */ + PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1), /* GPP_VGPIO3_USB4 */ + PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1), /* GPP_VGPIO3_USB5 */ + PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1), /* GPP_VGPIO3_USB6 */ + PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1), /* GPP_VGPIO3_USB7 */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS0, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS1, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC0, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC1, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC2, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC3, NONE, DEEP, OFF, ACPI), /* GPIO */ + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + PAD_CFG_GPO(GPP_S00, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S01, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S02, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S03, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S05, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S06, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_S07, 0, DEEP), /* GPIO */ + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_GPO(GPP_B00, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B01, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B02, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B03, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B05, 0, DEEP), /* GPIO - CPU_KBCRST# */ + PAD_CFG_GPO(GPP_B06, 0, DEEP), /* GPIO - ROM_I2C_EN */ + PAD_CFG_GPO(GPP_B07, 0, DEEP), /* GPIO - PANTONE_WP# */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), /* GPIO - PS8461_SW (DDS for eDP) */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), /* GPIO - DGPU_RST#_PCH */ + PAD_CFG_GPI_SCI(GPP_B10, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV Type-C DP HPD */ + PAD_CFG_GPI_SCI(GPP_B11, NONE, PLTRST, EDGE_BOTH, INVERT), /* GPIO - NV HDMI HPD */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* SLP_S0# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* PLTRST# */ + PAD_CFG_GPO(GPP_B14, 0, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B17, 1, DEEP), /* GPIO - CPU_GPIO_LANRTD3 */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), /* GPIO - PCH_BT_EN */ + PAD_CFG_GPO(GPP_B19, 1, DEEP), /* GPIO - WIFI_RF_EN */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_B21, 0, PLTRST), /* GPIO - TBT_FORCE_PWR */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), /* GPIO */ + PAD_CFG_TERM_GPO(GPP_B23, 0, DN_20K, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), /* n/a */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_CFG_GPO(GPP_D00, 1, DEEP), /* GPIO - SB_BLON */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), /* GPIO - SSD2_PWR_EN */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), /* GPIO - M2_SSD1_RST# */ + PAD_CFG_GPO(GPP_D03, 0, DEEP), /* GPIO - CPU_DGPU_PWR_EN */ + PAD_CFG_GPO(GPP_D04, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D05, 1, DEEP), /* GPIO - SSD1_PWR_EN */ + PAD_CFG_GPO(GPP_D06, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D07, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D08, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D09, 0, DEEP), /* GPIO */ + PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), /* HDA_BCLK */ + PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), /* HDA_SYNC */ + PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), /* HDA_SDO */ + PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), /* HDA_SDI0 */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), /* GPIO */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), /* GPIO - GPIO_SPK_MUTE */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), /* HDA_RST# */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), /* SRCCLKREQ6# */ + PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), /* SRCCLKREQ7# */ + PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), /* SRCCLKREQ8# */ + PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), /* SRCCLKREQ5# */ + PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), /* n/a */ + PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1), /* GPP_BOOTHALT_B */ + + /* ------- GPIO Group VGPIO ------- */ + PAD_CFG_GPO(GPP_VGPIO00, 1, DEEP), /* GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO04, NONE, DEEP, OFF, ACPI), /* GPIO */ + PAD_CFG_GPO(GPP_VGPIO05, 1, DEEP), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO06, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO07, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO08, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO09, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_VGPIO10, NONE, DEEP, NF1), /* GPP_VGPIO10 */ + PAD_CFG_NF(GPP_VGPIO11, NONE, DEEP, NF1), /* GPP_VGPIO11 */ + PAD_CFG_NF(GPP_VGPIO12, NONE, DEEP, NF1), /* GPP_VGPIO12 */ + PAD_CFG_NF(GPP_VGPIO13, NONE, DEEP, NF1), /* GPP_VGPIO13 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO18, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO19, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO20, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO21, 0, NONE, DEEP, LEVEL, ACPI), /* GPIO */ + PAD_CFG_NF(GPP_VGPIO22, NONE, DEEP, NF1), /* GPP_VGPIO22 */ + PAD_CFG_NF(GPP_VGPIO23, NONE, DEEP, NF1), /* GPP_VGPIO23 */ + PAD_CFG_NF(GPP_VGPIO24, NONE, DEEP, NF1), /* GPP_VGPIO24 */ + PAD_CFG_NF(GPP_VGPIO25, NONE, DEEP, NF1), /* GPP_VGPIO25 */ + PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1), /* GPP_VGPIO34 */ + PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1), /* GPP_VGPIO35 */ + PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1), /* GPP_VGPIO36 */ + PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1), /* GPP_VGPIO37 */ + PAD_CFG_NF(GPP_VGPIO40, NONE, DEEP, NF2), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO41, NONE, DEEP, NF2), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO42, NONE, DEEP, NF2), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO43, NONE, DEEP, NF2), /* RESERVED */ + PAD_CFG_NF(GPP_VGPIO44, NONE, DEEP, NF1), /* GPP_VGPIO44 */ + PAD_CFG_NF(GPP_VGPIO45, NONE, DEEP, NF1), /* GPP_VGPIO45 */ + PAD_CFG_NF(GPP_VGPIO46, NONE, DEEP, NF1), /* GPP_VGPIO46 */ + PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1), /* GPP_VGPIO47 */ +}; + +#define DGPU_RST_N GPP_B09 +#define DGPU_PWR_EN GPP_D03 +#define DGPU_PWRGD GPP_C15 +#define DGPU_NVVDD_EN GPP_F16 + +/* Pad configuration was generated automatically using intelp2m utility */ +void mainboard_configure_gpios(void) +{ + bool result; + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + mdelay(50); + if (dasharo_is_dgpu_enabled() && !gpio_get(DGPU_PWRGD)) { + gpio_set(DGPU_RST_N, 0); + mdelay(4); + gpio_set(DGPU_PWR_EN, 1); + result = wait_ms(200, gpio_get(DGPU_PWRGD) == 1); + if (result) + gpio_set(DGPU_RST_N, 1); + else + gpio_set(DGPU_PWR_EN, 0); + } else { + gpio_set(DGPU_PWR_EN, 0); + } + printk(BIOS_ERR, "DGPU_PWRGD %d\n", gpio_get(DGPU_PWRGD)); + printk(BIOS_ERR, "DGPU_RST_N %d\n", gpio_get(DGPU_RST_N)); + printk(BIOS_ERR, "DGPU_PWR_EN %d\n", gpio_get(DGPU_PWR_EN)); + printk(BIOS_ERR, "DGPU_NVVDD_EN %d\n", gpio_get(DGPU_NVVDD_EN)); + printk(BIOS_ERR, "PEG_CLKREQ %d\n", gpio_get(GPP_D18)); + + mdelay(50); +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c new file mode 100644 index 00000000000..376ed9dc5b9 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/hda_verb.c @@ -0,0 +1,87 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a741, /* Subsystem ID */ + 30, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558a741), + AZALIA_RESET(1), + + 0x1271C30, 0x1271D01, 0x1271EA6, 0x1271F90, + 0x1371C00, 0x1371D00, 0x1371E00, 0x1371F40, + 0x1871CF0, 0x1871D11, 0x1871E11, 0x1871F41, + 0x1971CF0, 0x1971D11, 0x1971E11, 0x1971F41, + 0x1A71CF0, 0x1A71D11, 0x1A71E11, 0x1A71F41, + 0x1B71CF0, 0x1B71D11, 0x1B71E11, 0x1B71F41, + 0x1D71C2D, 0x1D71D9B, 0x1D71E68, 0x1D71F40, + 0x1E71CF0, 0x1E71D11, 0x1E71E11, 0x1E71F41, + 0x2171C20, 0x2171D10, 0x2171E21, 0x2171F04, + 0x5B50006, 0x5B40011, 0x205001A, 0x204810B, + 0x205004A, 0x2042010, 0x2050038, 0x2044909, + 0x5C50000, 0x5C43D82, 0x5C50000, 0x5C43D82, + 0x5350000, 0x534201A, 0x5350000, 0x534201A, + 0x535001D, 0x5340800, 0x535001E, 0x5340800, + 0x5350003, 0x5341EC4, 0x5350004, 0x5340000, + 0x5450000, 0x5442000, 0x545001D, 0x5440800, + 0x545001E, 0x5440800, 0x5450003, 0x5441EC4, + 0x5450004, 0x5440000, 0x5350000, 0x534A01A, + 0x205003C, 0x204F175, 0x205003C, 0x204F135, + 0x2050040, 0x2048800, 0x5A50001, 0x5A4001F, + 0x2050010, 0x2040020, 0x2050010, 0x2040020, + 0x170500, 0x170500, 0x5A50004, 0x5A40113, + 0x2050008, 0x2046A8C, 0x2050076, 0x204F000, + 0x205000E, 0x20465C0, 0x2050033, 0x2048580, + 0x2050069, 0x204FDA8, 0x2050068, 0x2040000, + 0x2050003, 0x2040002, 0x2050069, 0x2040000, + 0x2050068, 0x2040001, 0x205002E, 0x204290E, + 0x2050010, 0x2040020, 0x2050010, 0x2040020, + + /* Intel Meteor Lake HDMI */ + 0x8086281d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; + +static const u32 smartamp_verbs[] = { + 0x1471CF0, 0x1471D11, 0x1471E11, 0x1471F41, + 0x1771C10, 0x1771D01, 0x1771E17, 0x1771F90, +}; + +static const u32 no_smartamp_verbs[] = { + 0x1471C10, 0x1471D01, 0x1471E17, 0x1471F90, + 0x1771C11, 0x1771D01, 0x1771E17, 0x1771F90, + 0x205006B, 0x204A390, 0x205006B, 0x204A390, + 0x205006C, 0x2040C9E, 0x205006D, 0x2040C00, +}; + +void mainboard_azalia_program_runtime_verbs(u8 *base, u32 viddid) +{ + if (gpio_get(GPP_E00)) { + printk(BIOS_INFO, "Normal amp detected\n"); + azalia_program_verb_table(base, no_smartamp_verbs, + ARRAY_SIZE(no_smartamp_verbs)); + } else { + printk(BIOS_INFO, "Smart amp detected\n"); + azalia_program_verb_table(base, smartamp_verbs, + ARRAY_SIZE(smartamp_verbs)); + } +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb b/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb new file mode 100644 index 00000000000..cd92732225d --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/overridetree.cb @@ -0,0 +1,75 @@ +chip soc/intel/meteorlake + # Power limits, + # PsysPL2, PsysPL3, PL4 are configured by EC at runtime + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 64, + .tdp_pl4 = 120, + .psys_pmax = 180, + }" + + # MTL SOC has additional setting for PsysPmax + register "psys_pmax_watts" = "180" + + device domain 0 on + subsystemid 0x1558 0xa741 inherit + device ref pcie_rp12 on # PEG + register "pcie_rp[PCH_RP(12)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_HOTPLUG, + }" + device pci 00.0 on + subsystemid 0x1558 0xa761 + end + end + device ref igpu on + register "ddi_port_A_config" = "1" + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */ + }" + end + device ref i2c0 on # Touchpad + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_A17)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref i2c4 on # ANX7443 USB-C Retimer + register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci" + end + device ref i2c5 on # TAS5825M SmartAmp + register "serial_io_i2c_mode[PchSerialIoIndexI2C5]" = "PchSerialIoPci" + chip drivers/i2c/tas5825m + register "id" = "0" + device i2c 4e on end + end + end + device ref pcie_rp5 on # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_V11)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A20)" + register "srcclk_pin" = "2" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c new file mode 100644 index 00000000000..ff40f9b6e2d --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/ramstage.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include + +void variant_devtree_update(void) +{ + struct device *i2c_amp_dev = pcidev_on_root(0x19, 1); + if (i2c_amp_dev) { + bool have_smartamp = !gpio_get(GPP_E00); + i2c_amp_dev->enabled = have_smartamp; + } + + struct device *dgpu_dev = pcidev_on_root(0x01, 0); + if (dgpu_dev) { + dgpu_dev->enabled = dasharo_is_dgpu_enabled() != 0; + printk(BIOS_DEBUG, "dgpu_dev->enabled: %d\n", dgpu_dev->enabled); + } +} + +void variant_final(void) +{ + struct device *dgpu_rp_dev = pcidev_on_root(0x01, 0); + + if (!dgpu_rp_dev) + return; + + struct device *dgpu_dev = pcidev_path_behind(dgpu_rp_dev->downstream, PCI_DEVFN(0, 0)); + + /* + * The dGPU may fail to come up after changing from iGPU mode to dGPU + * mode. If that happens, we need to kick the platform via global reset. + */ + if (!dgpu_dev && dasharo_is_dgpu_enabled()) { + printk(BIOS_DEBUG, "dGPU did not come up! Kicking the platform to work around it\n"); + do_global_reset(); + } else { + printk(BIOS_DEBUG, "dGPU is up.\n"); + } + +} diff --git a/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c b/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c new file mode 100644 index 00000000000..5e95c4b13cd --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/dgpu/tas5825m.c @@ -0,0 +1,2396 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* + * This code was auto-generated using extract.rs from + * https://github.com/system76/smart-amp + */ + +int tas5825m_setup(struct device *dev, int id) +{ + int res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + mdelay(5); + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xFE, 0x16, 0xD5, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x90, 0xB5, 0x11, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xF6, 0x71, 0xFB, 0xF0, 0x5E, 0x48, 0xD6, + 0x07, 0xAC, 0xA4, 0x5B, 0x0F, 0xA1, 0xB7, 0x2A, + 0xF8, 0x5C, 0xE9, 0xAA, 0x08, 0x00, 0x00, 0x00, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x4B, 0x87, 0x16, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + 0x08, 0x00, 0x00, 0x00, 0xF1, 0x2E, 0x37, 0x44, + 0x06, 0xE6, 0xAE, 0x6C, 0x0E, 0xD1, 0xC8, 0xBC, + 0xF9, 0x19, 0x51, 0x94, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xE3, 0xB6, 0x0E, + 0xF0, 0x38, 0x93, 0xE5, 0x07, 0xE3, 0xB6, 0x0E, + 0x0F, 0xC7, 0x37, 0xC3, 0xF8, 0x38, 0x5F, 0x8D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xE7, 0xF3, 0x30, 0xF0, 0x30, 0x19, 0xA1, + 0x07, 0xE7, 0xF3, 0x30, 0x0F, 0xCF, 0xB1, 0xEB, + 0xF8, 0x2F, 0xE5, 0x2D, 0x07, 0xEF, 0xD5, 0xCD, + 0xF0, 0x20, 0x54, 0x66, 0x07, 0xEF, 0xD5, 0xCD, + 0x0F, 0xDF, 0x76, 0xF1, 0xF8, 0x20, 0x1F, 0xBE, + 0x07, 0xF8, 0xC3, 0x5E, 0xF0, 0x17, 0xB1, 0xEA, + 0x07, 0xEF, 0xAD, 0x9B, 0x0F, 0xE8, 0x4E, 0x16, + 0xF8, 0x17, 0x8F, 0x07, 0x08, 0x06, 0x13, 0x6A, + 0xF0, 0x0B, 0x9D, 0x15, 0x07, 0xEE, 0x72, 0x7F, + 0x0F, 0xF4, 0x3F, 0x7D, 0xF8, 0x0B, 0x56, 0xA9, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0xE3, 0xB6, 0x0E, 0xF0, 0x38, 0x93, 0xE5, + 0x07, 0xE3, 0xB6, 0x0E, 0x0F, 0xC7, 0x37, 0xC3, + 0xF8, 0x38, 0x5F, 0x8D, 0x07, 0xE7, 0xF3, 0x30, + 0xF0, 0x30, 0x19, 0xA1, 0x07, 0xE7, 0xF3, 0x30, + 0x0F, 0xCF, 0xB1, 0xEB, 0xF8, 0x2F, 0xE5, 0x2D, + 0x07, 0xEF, 0xD5, 0xCD, 0xF0, 0x20, 0x54, 0x66, + 0x07, 0xEF, 0xD5, 0xCD, 0x0F, 0xDF, 0x76, 0xF1, + 0xF8, 0x20, 0x1F, 0xBE, 0x07, 0xF8, 0xC3, 0x5E, + 0xF0, 0x17, 0xB1, 0xEA, 0x07, 0xEF, 0xAD, 0x9B, + 0x0F, 0xE8, 0x4E, 0x16, 0xF8, 0x17, 0x8F, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x06, 0x13, 0x6A, 0xF0, 0x0B, 0x9D, 0x15, + 0x07, 0xEE, 0x72, 0x7F, 0x0F, 0xF4, 0x3F, 0x7D, + 0xF8, 0x0B, 0x56, 0xA9, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x82, 0xB3, 0xD2, 0xFF, 0x00, 0xA4, 0x7A, + 0x00, 0x7C, 0xCA, 0xB8, 0x0F, 0xF6, 0xBE, 0xFB, + 0xF8, 0x09, 0x1E, 0x02, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x40); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x01, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + mdelay(5); + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x12); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x48, 0x0C); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x64); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xFE, 0x00, 0x40, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x50, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0xFC, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x00, 0x82, 0x00, 0x93, 0x00, 0xFC, 0x00, 0x00, + 0x8F, 0x00, 0xFF, 0xEF, 0x84, 0x49, 0x03, 0x27, + 0x84, 0x02, 0x04, 0x06, 0x02, 0x60, 0x00, 0x01, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x70, 0x00, 0x06, 0x02, 0x78, 0x00, 0x05, + 0x02, 0x68, 0x00, 0x02, 0x02, 0x28, 0x03, 0x4D, + 0x84, 0x2A, 0x04, 0x00, 0xE2, 0x57, 0x91, 0x9F, + 0x84, 0x82, 0x20, 0xE0, 0x84, 0x82, 0x04, 0x01, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x68, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x27, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x41, 0x03, 0x37, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x00, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x11, 0xAA, 0xF0, 0x1C, 0x11, 0xAB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1C, 0x11, 0xAC, 0xF0, 0x1F, 0x11, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x43, 0x03, 0x37, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x51, 0x03, 0x3E, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x47, 0x84, 0xC2, 0x40, 0xE0, + 0x8C, 0xFF, 0x03, 0x23, 0xE0, 0x10, 0x11, 0xB3, + 0xF0, 0x1C, 0x51, 0xB4, 0xF0, 0x1C, 0x51, 0xB5, + 0xF0, 0x1C, 0x51, 0xB6, 0xF0, 0x1F, 0x51, 0xB7, + 0x86, 0xA1, 0x01, 0xC6, 0x80, 0x27, 0x80, 0xEA, + 0x84, 0x53, 0x03, 0x3E, 0x84, 0x82, 0x04, 0x05, + 0x84, 0x51, 0x03, 0x75, 0xE2, 0x6B, 0xC0, 0x00, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x80, 0x31, 0xB8, + 0x84, 0x82, 0x40, 0xE0, 0xF0, 0x1C, 0x51, 0xB9, + 0xF0, 0x1C, 0x51, 0xBA, 0xF0, 0x1C, 0x51, 0xBB, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xF0, 0x1F, 0x51, 0xBC, 0x86, 0xA1, 0x01, 0xC5, + 0x80, 0x27, 0x80, 0xEA, 0x60, 0x00, 0x00, 0x00, + 0x80, 0x00, 0x00, 0x81, 0x84, 0xA1, 0x03, 0x4F, + 0xE0, 0x80, 0xA0, 0x00, 0x01, 0x07, 0x11, 0x20, + 0x08, 0x44, 0x26, 0x30, 0x08, 0x00, 0x98, 0x4A, + 0x84, 0x53, 0x03, 0x75, 0x08, 0x00, 0x30, 0x48, + 0x02, 0xCA, 0x00, 0x01, 0x08, 0x60, 0x26, 0x32, + 0x84, 0x51, 0x03, 0x45, 0xE4, 0x10, 0x40, 0x00, + 0x80, 0x40, 0xC0, 0x82, 0x84, 0xC2, 0x40, 0xE0, + 0x84, 0xC3, 0x03, 0x5E, 0x08, 0x00, 0x50, 0x48, + 0xE0, 0x10, 0x11, 0xBD, 0x02, 0xC2, 0x00, 0x02, + 0x08, 0x60, 0x06, 0x12, 0x84, 0xD3, 0x03, 0x4F, + 0xF0, 0x1C, 0x51, 0xBE, 0xF0, 0x1C, 0x51, 0xBF, + 0xF0, 0x1C, 0x51, 0xC0, 0xF0, 0x1F, 0x51, 0xC1, + 0x84, 0xA1, 0x03, 0x65, 0x80, 0x27, 0x80, 0xEA, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x00, 0x00, 0x00, 0x80, 0x07, 0x00, 0x83, + 0x08, 0x00, 0x98, 0x6B, 0x08, 0x00, 0x30, 0x68, + 0x84, 0x53, 0x03, 0x45, 0x08, 0x60, 0x26, 0x33, + 0x84, 0x51, 0x03, 0x25, 0xE4, 0x10, 0x60, 0x00, + 0x80, 0x40, 0xC0, 0x81, 0x02, 0x70, 0x00, 0x7F, + 0x08, 0x00, 0x50, 0x28, 0x08, 0x60, 0x06, 0x11, + 0x84, 0xCB, 0x03, 0x65, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x01, + 0x84, 0xA2, 0x04, 0x03, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x25, 0x80, 0x00, 0xC4, 0x04, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x60, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x02, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x60, 0x00, 0x01, 0x02, 0x70, 0x00, 0x04, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0x41, 0x03, 0x67, + 0x84, 0x51, 0x03, 0x6D, 0x84, 0xC0, 0x04, 0x02, + 0x04, 0x80, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x02, 0x78, 0x00, 0x03, 0x02, 0x68, 0x00, 0x02, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x84, 0x49, 0x03, 0x2F, 0xE0, 0x80, 0x71, 0xA9, + 0x02, 0x28, 0x03, 0x55, 0x84, 0x82, 0x00, 0xE0, + 0x84, 0x2A, 0x04, 0x00, 0xF0, 0x1C, 0x11, 0xAA, + 0xF0, 0x1C, 0x11, 0xAB, 0xF0, 0x1C, 0x11, 0xAC, + 0xF0, 0x1F, 0x11, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xE8, 0x84, 0x82, 0x04, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0xE0, 0x80, 0x60, 0x00, 0x84, 0x82, 0x40, 0xE0, + 0x84, 0x43, 0x03, 0x67, 0xF0, 0x1C, 0x51, 0xAF, + 0xF0, 0x1C, 0x51, 0xB0, 0xF0, 0x1C, 0x51, 0xB1, + 0xF0, 0x1F, 0x51, 0xB2, 0x02, 0x78, 0x00, 0x05, + 0x80, 0x27, 0x80, 0xEA, 0x84, 0x82, 0x04, 0x08, + 0x02, 0x70, 0x00, 0x06, 0x84, 0x53, 0x03, 0x6D, + 0x84, 0x80, 0x04, 0x07, 0xE0, 0x00, 0x00, 0x82, + 0xF0, 0x81, 0x00, 0x80, 0x80, 0x07, 0x12, 0xBC, + 0x86, 0xA1, 0x01, 0x9F, 0xE2, 0x57, 0xA0, 0x00, + 0x84, 0x82, 0x04, 0x09, 0x84, 0x82, 0x20, 0xE0, + 0xF0, 0x1C, 0x31, 0xA0, 0xF0, 0x1C, 0x31, 0xA1, + 0xF0, 0x1C, 0x31, 0xA2, 0xF0, 0x1F, 0x31, 0xA3, + 0xE4, 0x00, 0x11, 0xA6, 0x80, 0x27, 0x80, 0xE1, + 0xF4, 0x00, 0x11, 0xA4, 0xF4, 0x1D, 0x31, 0xA5, + 0xF4, 0x1C, 0x31, 0xA7, 0xF4, 0x1F, 0x31, 0xA8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x08); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0x78, 0x00, 0x03, 0xE2, 0x6A, 0xF1, 0xC3, + 0x80, 0x67, 0x80, 0xE9, 0x84, 0x4B, 0x03, 0x2F, + 0x02, 0x70, 0x00, 0x04, 0x84, 0x59, 0x03, 0x3D, + 0x80, 0x07, 0x00, 0x80, 0xE0, 0x00, 0x11, 0xA9, + 0x84, 0x82, 0x60, 0xE0, 0x8E, 0xFC, 0x04, 0x10, + 0xF0, 0x1C, 0x71, 0xAA, 0xF0, 0x1C, 0x71, 0xAB, + 0xF0, 0x1C, 0x71, 0xAC, 0xF0, 0x1F, 0x71, 0xAD, + 0x86, 0xA1, 0x01, 0xC2, 0x80, 0x27, 0x80, 0xEB, + 0x60, 0x00, 0x00, 0x00, 0x84, 0x5B, 0x03, 0x3D, + 0x80, 0x00, 0x00, 0x81, 0x0D, 0x00, 0x10, 0x20, + 0x84, 0x59, 0x03, 0x3F, 0x08, 0x44, 0x26, 0x30, + 0x84, 0xC3, 0x03, 0x57, 0x84, 0xC2, 0x60, 0xE0, + 0xE0, 0x10, 0x11, 0xB3, 0xF0, 0x1C, 0x71, 0xB4, + 0xF0, 0x1C, 0x71, 0xB5, 0xF0, 0x1C, 0x71, 0xB6, + 0xF0, 0x1F, 0x71, 0xB7, 0x86, 0xA1, 0x01, 0xC6, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x09); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x80, 0x27, 0x80, 0xEB, 0x84, 0x5B, 0x03, 0x3F, + 0x84, 0x82, 0x04, 0x0D, 0x84, 0x41, 0x03, 0x76, + 0xE2, 0x6B, 0xE0, 0x00, 0x80, 0x07, 0x00, 0x80, + 0xE0, 0x81, 0x31, 0xB8, 0x84, 0x82, 0x00, 0xE0, + 0xF0, 0x1C, 0x11, 0xB9, 0xF0, 0x1C, 0x11, 0xBA, + 0xF0, 0x1C, 0x11, 0xBB, 0xF0, 0x1F, 0x11, 0xBC, + 0x86, 0xA1, 0x01, 0xC5, 0x80, 0x27, 0x80, 0xE8, + 0x60, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x81, + 0x84, 0xA1, 0x03, 0x5D, 0xE0, 0x81, 0xA0, 0x00, + 0x01, 0x07, 0x11, 0x20, 0x08, 0x44, 0x26, 0x30, + 0x08, 0x00, 0x98, 0x4A, 0x84, 0x43, 0x03, 0x76, + 0x08, 0x00, 0x30, 0x48, 0x02, 0xCA, 0x00, 0x01, + 0x08, 0x60, 0x26, 0x32, 0x84, 0x41, 0x03, 0x46, + 0xE4, 0x10, 0x40, 0x00, 0x80, 0x40, 0xC0, 0x82, + 0x84, 0xC2, 0x00, 0xE0, 0x84, 0xC3, 0x03, 0x5F, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x50, 0x48, 0xE0, 0x10, 0x11, 0xBD, + 0x02, 0xC2, 0x00, 0x02, 0x08, 0x60, 0x06, 0x12, + 0x84, 0xD3, 0x03, 0x5D, 0xF0, 0x1C, 0x11, 0xBE, + 0xF0, 0x1C, 0x11, 0xBF, 0xF0, 0x1C, 0x11, 0xC0, + 0xF0, 0x1F, 0x11, 0xC1, 0x84, 0xA1, 0x03, 0x66, + 0x80, 0x27, 0x80, 0xE8, 0xE0, 0x00, 0x00, 0x00, + 0x80, 0x07, 0x00, 0x83, 0x08, 0x00, 0x98, 0x6B, + 0x08, 0x00, 0x30, 0x68, 0x84, 0x43, 0x03, 0x46, + 0x08, 0x60, 0x26, 0x33, 0x84, 0x51, 0x03, 0x26, + 0xE4, 0x10, 0x60, 0x00, 0x80, 0x40, 0xC0, 0x81, + 0x02, 0x70, 0x00, 0x7F, 0x08, 0x00, 0x50, 0x28, + 0x08, 0x60, 0x06, 0x11, 0x8C, 0xFF, 0x03, 0x24, + 0x84, 0xCB, 0x03, 0x66, 0xE0, 0x10, 0x51, 0xC4, + 0x84, 0x80, 0x41, 0x00, 0x02, 0xA3, 0x00, 0x10, + 0xE4, 0x00, 0x00, 0x00, 0x84, 0xD0, 0x04, 0x09, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0xA2, 0x04, 0x0B, 0x84, 0xD2, 0x50, 0x01, + 0x84, 0x53, 0x03, 0x26, 0x80, 0x00, 0xC4, 0x0C, + 0x8F, 0x30, 0x00, 0x00, 0x88, 0x67, 0x03, 0x00, + 0xE4, 0x00, 0x11, 0x9B, 0xEE, 0x64, 0x80, 0x00, + 0x02, 0xD3, 0x00, 0x10, 0x88, 0x47, 0x00, 0x80, + 0x10, 0x00, 0x18, 0x02, 0x86, 0xC1, 0x01, 0x9D, + 0xE0, 0x10, 0x31, 0xC7, 0x86, 0xC9, 0x01, 0x9E, + 0x80, 0x00, 0xC4, 0x0A, 0x02, 0x50, 0x01, 0x9C, + 0x00, 0xFF, 0x21, 0x65, 0x00, 0xFC, 0x00, 0x00, + 0x02, 0x70, 0x00, 0x04, 0x02, 0x68, 0x00, 0x01, + 0x02, 0x60, 0x00, 0x03, 0x02, 0x78, 0x00, 0x02, + 0x84, 0x49, 0x03, 0x6E, 0x84, 0x41, 0x03, 0x6F, + 0x84, 0xC8, 0x04, 0x10, 0x84, 0xC0, 0x04, 0x0A, + 0x04, 0x81, 0x91, 0x20, 0x08, 0x60, 0x26, 0x30, + 0x0D, 0x00, 0x10, 0x10, 0x08, 0x60, 0x06, 0x12, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x84, 0x00, 0x04, 0x06, 0xE0, 0x81, 0x71, 0xA9, + 0x84, 0x82, 0x20, 0xE8, 0xF0, 0x1D, 0x31, 0xAA, + 0xF0, 0x1D, 0x31, 0xAB, 0xF0, 0x1D, 0x31, 0xAC, + 0xF0, 0x1C, 0x31, 0xAD, 0x86, 0xA1, 0x01, 0xAE, + 0x80, 0x27, 0x80, 0xF9, 0x84, 0x82, 0x04, 0x0E, + 0xE0, 0x81, 0x60, 0x00, 0x84, 0x82, 0x00, 0xE8, + 0x84, 0x4B, 0x03, 0x6E, 0xF0, 0x1D, 0x11, 0xAF, + 0xF0, 0x1D, 0x11, 0xB0, 0xF0, 0x1D, 0x11, 0xB1, + 0xF0, 0x1C, 0x11, 0xB2, 0x02, 0xA3, 0x00, 0x1A, + 0x80, 0x27, 0x80, 0xF8, 0x84, 0x82, 0x04, 0x0F, + 0xE0, 0x81, 0xC0, 0x00, 0xF0, 0x81, 0xE0, 0x80, + 0x84, 0x43, 0x03, 0x6F, 0x80, 0x07, 0x12, 0xBD, + 0x02, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x11, 0x8F, 0x00, 0xFF, 0xFF, + 0x84, 0x58, 0x04, 0x01, 0x84, 0xC2, 0x04, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x02, 0xC2, 0x60, 0x00, 0x84, 0xA0, 0x61, 0x00, + 0xE0, 0x20, 0x00, 0x00, 0x00, 0xFC, 0x00, 0x00, + 0x40, 0x40, 0xA0, 0x00, 0x80, 0x00, 0xC0, 0x82, + 0x08, 0xFC, 0x48, 0x3A, 0x08, 0xFC, 0x18, 0x50, + 0x00, 0xFC, 0x00, 0x00, 0xE0, 0x10, 0x00, 0x00, + 0x86, 0xA0, 0x41, 0x00, 0x40, 0x47, 0x20, 0x00, + 0x80, 0x00, 0xC0, 0x83, 0x04, 0xE0, 0x3D, 0x1E, + 0x04, 0x80, 0x11, 0xE0, 0x08, 0x44, 0x26, 0x33, + 0x02, 0xCB, 0x00, 0x10, 0xE0, 0x10, 0x40, 0x83, + 0x08, 0x00, 0x28, 0x21, 0x84, 0xCA, 0x61, 0x00, + 0x80, 0x07, 0x00, 0x81, 0x0C, 0xE0, 0x2C, 0x09, + 0x84, 0xCA, 0x21, 0x00, 0x00, 0xFC, 0x50, 0x00, + 0x8F, 0x00, 0x00, 0x01, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x18); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x80, 0x00, 0x00, 0x04, 0x00, + 0x00, 0x00, 0x03, 0x28, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x30, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x38, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x40, 0x00, 0x00, 0x03, 0x48, + 0x00, 0x00, 0x03, 0x50, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x54, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1C); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x58, 0x00, 0x00, 0x03, 0x60, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x74, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x1C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1D); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x3C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x68, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x0C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x03, 0x70, 0x00, 0x00, 0x03, 0x78, + 0x00, 0x00, 0x04, 0x80, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x24, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x78); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x1E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x00, 0x04, 0x88, 0x00, 0x00, 0x04, 0x90, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x44, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0xA7, 0x26, 0x4A, 0x7F, 0xFF, 0xFF, 0xFF, + 0x00, 0x20, 0xC4, 0x9C, 0x00, 0x20, 0xC4, 0x9C, + 0x00, 0x00, 0x68, 0xDB, 0x00, 0x00, 0xD1, 0xB7, + 0x00, 0x00, 0x68, 0xDB, 0x0F, 0xA4, 0xA8, 0xC1, + 0xF8, 0x59, 0x7F, 0x63, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x2F, 0xB7, 0xE9, + 0x00, 0x5F, 0x6F, 0xD2, 0x00, 0x2F, 0xB7, 0xE9, + 0x0B, 0x1E, 0x4F, 0x76, 0xFC, 0x23, 0x05, 0x54, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x7D, 0xBF, 0x48, + 0xFA, 0x41, 0x20, 0x5C, 0x0B, 0x1E, 0x4F, 0x76, + 0xFC, 0x23, 0x05, 0x54, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x07, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x81, 0x6F, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0x3F, 0xE5, 0xC9, 0xF8, 0xBB, 0x98, 0xC8, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x10); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x89, 0xA0, 0x27, 0x7F, 0xEC, 0x56, 0xD5, + 0x7F, 0xFC, 0xB9, 0x23, 0x00, 0x89, 0xA0, 0x27, + 0x7F, 0xEC, 0x56, 0xD5, 0x7F, 0xFC, 0xB9, 0x23, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x40, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x11, 0xFF, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x7D, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x51, 0x05); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x19, 0xDF); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x46, 0x11); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x02, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x53, 0x01); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x54, 0x00); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x02); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x8C); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x71, 0x94, 0x9A, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x2C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0A); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0B); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x57, 0x62, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x28, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x03, 0x69, 0xC5, 0x00, 0xFE, 0x16, 0xD5, + 0x00, 0x22, 0x1D, 0x95, 0x00, 0x03, 0x69, 0xC5, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x7F, 0xF9, 0x2C, 0x60, 0x04, 0x90, 0xB5, 0x11, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x5C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x07); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x80, 0x00, 0x00, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x64, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + { + const uint8_t values[] = { + 0x40, 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0xAA); + if (res < 0) + return res; + + res = tas5825m_set_page(dev, 0x01); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xF6, 0x71, 0xFB, 0xF0, 0x5E, 0x48, 0xD6, + 0x07, 0xAC, 0xA4, 0x5B, 0x0F, 0xA1, 0xB7, 0x2A, + 0xF8, 0x5C, 0xE9, 0xAA, 0x08, 0x00, 0x00, 0x00, + 0xF0, 0xBC, 0xDB, 0x13, 0x07, 0x4B, 0x87, 0x16, + 0x0F, 0x43, 0x24, 0xED, 0xF8, 0xB4, 0x78, 0xEA, + 0x08, 0x00, 0x00, 0x00, 0xF1, 0x2E, 0x37, 0x44, + 0x06, 0xE6, 0xAE, 0x6C, 0x0E, 0xD1, 0xC8, 0xBC, + 0xF9, 0x19, 0x51, 0x94, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x30, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x02); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x07, 0xE3, 0xB6, 0x0E, + 0xF0, 0x38, 0x93, 0xE5, 0x07, 0xE3, 0xB6, 0x0E, + 0x0F, 0xC7, 0x37, 0xC3, 0xF8, 0x38, 0x5F, 0x8D, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x03); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x07, 0xE7, 0xF3, 0x30, 0xF0, 0x30, 0x19, 0xA1, + 0x07, 0xE7, 0xF3, 0x30, 0x0F, 0xCF, 0xB1, 0xEB, + 0xF8, 0x2F, 0xE5, 0x2D, 0x07, 0xEF, 0xD5, 0xCD, + 0xF0, 0x20, 0x54, 0x66, 0x07, 0xEF, 0xD5, 0xCD, + 0x0F, 0xDF, 0x76, 0xF1, 0xF8, 0x20, 0x1F, 0xBE, + 0x07, 0xF8, 0xC3, 0x5E, 0xF0, 0x17, 0xB1, 0xEA, + 0x07, 0xEF, 0xAD, 0x9B, 0x0F, 0xE8, 0x4E, 0x16, + 0xF8, 0x17, 0x8F, 0x07, 0x08, 0x06, 0x13, 0x6A, + 0xF0, 0x0B, 0x9D, 0x15, 0x07, 0xEE, 0x72, 0x7F, + 0x0F, 0xF4, 0x3F, 0x7D, 0xF8, 0x0B, 0x56, 0xA9, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x04); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x05); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x07, 0xE3, 0xB6, 0x0E, 0xF0, 0x38, 0x93, 0xE5, + 0x07, 0xE3, 0xB6, 0x0E, 0x0F, 0xC7, 0x37, 0xC3, + 0xF8, 0x38, 0x5F, 0x8D, 0x07, 0xE7, 0xF3, 0x30, + 0xF0, 0x30, 0x19, 0xA1, 0x07, 0xE7, 0xF3, 0x30, + 0x0F, 0xCF, 0xB1, 0xEB, 0xF8, 0x2F, 0xE5, 0x2D, + 0x07, 0xEF, 0xD5, 0xCD, 0xF0, 0x20, 0x54, 0x66, + 0x07, 0xEF, 0xD5, 0xCD, 0x0F, 0xDF, 0x76, 0xF1, + 0xF8, 0x20, 0x1F, 0xBE, 0x07, 0xF8, 0xC3, 0x5E, + 0xF0, 0x17, 0xB1, 0xEA, 0x07, 0xEF, 0xAD, 0x9B, + 0x0F, 0xE8, 0x4E, 0x16, 0xF8, 0x17, 0x8F, 0x07, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x06); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x06, 0x13, 0x6A, 0xF0, 0x0B, 0x9D, 0x15, + 0x07, 0xEE, 0x72, 0x7F, 0x0F, 0xF4, 0x3F, 0x7D, + 0xF8, 0x0B, 0x56, 0xA9, 0x08, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0E); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x00, 0x82, 0xB3, 0xD2, 0xFF, 0x00, 0xA4, 0x7A, + 0x00, 0x7C, 0xCA, 0xB8, 0x0F, 0xF6, 0xBE, 0xFB, + 0xF8, 0x09, 0x1E, 0x02, 0x00 + }; + res = tas5825m_write_block_at(dev, 0x6C, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_page(dev, 0x0F); + if (res < 0) + return res; + + { + const uint8_t values[] = { + 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0xFF, 0xF4, 0x49, 0x81, + 0xFF, 0xE8, 0x93, 0x02, 0xFF, 0xF4, 0x49, 0x81, + 0x0D, 0x94, 0x7A, 0x64, 0xFA, 0x3C, 0xAB, 0xA1, + 0x06, 0xD5, 0xF3, 0xB1, 0xF2, 0x54, 0x18, 0x9F, + 0x06, 0xD5, 0xF3, 0xB1, 0x0D, 0x94, 0x7A, 0x64, + 0xFA, 0x3C, 0xAB, 0xA1, 0x00, 0x00, 0x38, 0xE4, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x0F, 0xD5, 0x55, 0x55, 0xF8, 0x2A, 0x71, 0xC7, + 0x00 + }; + res = tas5825m_write_block_at(dev, 0x08, values, ARRAY_SIZE(values)); + if (res < 0) + return res; + } + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x30, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x60, 0x02); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x62, 0x09); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x4C, 0x40); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x03, 0x03); + if (res < 0) + return res; + + res = tas5825m_set_book(dev, 0x00); + if (res < 0) + return res; + + res = tas5825m_write_at(dev, 0x78, 0x80); + if (res < 0) + return res; + + return 0; +} diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt b/src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt new file mode 100644 index 00000000000..4151d024a9a Binary files /dev/null and b/src/mainboard/novacustom/mtl-h/variants/igpu/data.vbt differ diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c b/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c new file mode 100644 index 00000000000..8083d301e32 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/gpio.c @@ -0,0 +1,1268 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group CPU ------- */ + + /* ------- GPIO Group V ------- */ + + /* GPP_V00 - BATLOW# */ + /* DW0: 0x44000702, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_V00, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V00, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_V01 - ACPRESENT */ + /* DW0: 0x44000702, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_V01, NATIVE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V01, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + + /* GPP_V02 - SOC_WAKE# */ + /* DW0: 0x44000702, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_V02, NATIVE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V02, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + + /* GPP_V03 - PWRBTN# */ + /* DW0: 0x44000702, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_V03, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V03, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_V04 - SLP_S3# */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_V04, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V04, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_V05 - SLP_S4# */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_V05, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V05, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_V06 - SLP_A# */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_V06, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V06, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_V07 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_V07, 0, DEEP), + + /* GPP_V08 - SUSCLK */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_V08, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V08, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_V09 - SLP_WLAN# */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_V09, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V09, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_V10 - SLP_S5# */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_V10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_V11 - LANPHYPC */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_V11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_V12 - SLP_LAN# */ + /* DW0: 0x44000602, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_V12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), + + /* GPP_V13 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_V13, 0, DEEP), + + /* GPP_V14 - WAKE# */ + /* DW0: 0x44000602, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_V14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), + + /* GPP_V15 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_V15, 0, DEEP), + + /* GPP_V16 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_V16, 0, DEEP), + + /* GPP_V17 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_V17, 0, DEEP), + + /* GPP_V18 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_V18, 0, DEEP), + + /* GPP_V19 - n/a */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_V19, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_V20 - n/a */ + /* DW0: 0x44000602, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_V20, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), + + /* GPP_V21 - n/a */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_V21, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_V21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_V22 - GPIO */ + /* DW0: 0x44000200, DW1: 0x0003c000 */ + PAD_CFG_GPO(GPP_V22, 0, DEEP), + + /* GPP_V23 - GPIO */ + /* DW0: 0x44000200, DW1: 0x0003c000 */ + PAD_CFG_GPO(GPP_V23, 0, DEEP), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C00 - SMBCLK */ + /* DW0: 0x44000702, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_C00, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_C00, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_C01 - SMBDATA */ + /* DW0: 0x44000702, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_C01, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_C01, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_C02 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C02, 0, DEEP), + + /* GPP_C03 - SML0CLK */ + /* DW0: 0x44000702, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_C03, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_C03, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), + + /* GPP_C04 - SML0DATA */ + /* DW0: 0x44000702, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_C04, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_C04, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), + + /* GPP_C05 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C05, 0, DEEP), + + /* GPP_C06 - SML1CLK */ + /* DW0: 0x04000702, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_C06, NONE, RSMRST, NF1), */ + _PAD_CFG_STRUCT(GPP_C06, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), + + /* GPP_C07 - SML1DATA */ + /* DW0: 0x04000702, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_C07, NONE, RSMRST, NF1), */ + _PAD_CFG_STRUCT(GPP_C07, PAD_FUNC(NF1) | PAD_RESET(RSMRST) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), + + /* GPP_C08 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C08, 0, DEEP), + + /* GPP_C09 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C09, 0, DEEP), + + /* GPP_C10 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C10, 0, DEEP), + + /* GPP_C11 - SRCCLKREQ2# (LAN) */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_C11, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_C11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_C12 - SRCCLKREQ3# (SDCARD) */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_C12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_C13 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + + /* GPP_C14 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C14, 0, DEEP), + + /* GPP_C15 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C15, 0, DEEP), + + /* GPP_C16 - TBT_LSX0_TXD */ + /* DW0: 0x44000700, DW1: 0x00024000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_C16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(TxDRxE)), + + /* GPP_C17 - TBT_LSX0_RXD */ + /* DW0: 0x44000700, DW1: 0x00024000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_C17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(TxDRxE)), + + /* GPP_C18 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C18, 0, DEEP), + + /* GPP_C19 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C19, 0, DEEP), + + /* GPP_C20 - DDP2_CTRLCLK */ + /* DW0: 0x44000b00, DW1: 0x0001c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_C20, NONE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_C20, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(HIZCRx0)), + + /* GPP_C21 - DDP2_CTRLDATA */ + /* DW0: 0x44000b02, DW1: 0x0001c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_C21, NONE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_C21, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(HIZCRx0)), + + /* GPP_C22 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* GPP_C23 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A00 - ESPI_IO0 */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_A00, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A00, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_A01 - ESPI_IO1 */ + /* DW0: 0x44000702, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_A01, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A01, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_A02 - ESPI_IO2 */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_A02, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A02, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_A03 - ESPI_IO3 */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_A03, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A03, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_A04 - ESPI_CS0# */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_A04, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A04, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_A05 - ESPI_CLK */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_A05, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A05, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_A06 - ESPI_RESET# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_A06, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A06, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_A07 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A07, 0, DEEP), + + /* GPP_A08 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A08, 0, DEEP), + + /* GPP_A09 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A09, 0, DEEP), + + /* GPP_A10 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A10, 0, DEEP), + + /* GPP_A11 - GPIO (ADDS_CODE) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A11, 0, DEEP), + + /* GPP_A12 - GPIO (WLAN_WAKEUP#) */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_A12, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_A12, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_A13 - GPIO (M2_SSD2_RST#) */ + /* DW0: 0x84000201, DW1: 0x00003000 */ + PAD_CFG_TERM_GPO(GPP_A13, 1, UP_20K, PLTRST), + + /* GPP_A14 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A14, 0, DEEP), + + /* GPP_A15 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A15, 0, DEEP), + + /* GPP_A16 - RSVD/ESPI_ALERT0# */ + /* DW0: 0x44000702, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_A16, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A16, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_A17 - GPIO (TP_ATTN#_A17) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A17, 0, DEEP), + + /* GPP_A18 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A18, 0, DEEP), + + /* GPP_A19 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A19, 0, DEEP), + + /* GPP_A20 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_A20, 0, DEEP), + + /* GPP_A21 - PMCALERT# */ + /* DW0: 0x44000702, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_A21, NATIVE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_A21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + + /* GPP_A22 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003c00 */ + PAD_NC(GPP_A22, NATIVE), + + /* GPP_A23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00003c00 */ + PAD_NC(GPP_A23, NATIVE), + + /* GPP_ESPI_CLK_LPBK - n/a */ + /* DW0: 0x40000700, DW1: 0x0003c000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_ESPI_CLK_LPBK, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_ESPI_CLK_LPBK, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E00 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E00, 0, DEEP), + + /* GPP_E01 - GPIO (TPM_PIRQ#) */ + /* DW0: 0x40100102, DW1: 0x00003000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_APIC(GPP_E01, UP_20K, DEEP, LEVEL, NONE), */ + _PAD_CFG_STRUCT(GPP_E01, PAD_RESET(DEEP) | PAD_IRQ_ROUTE(IOAPIC) | PAD_BUF(TX_DISABLE) | (1 << 1), PAD_PULL(UP_20K)), + + /* GPP_E02 - GPIO (BOARD_ID4) */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_E02, NONE, DEEP, OFF, ACPI), + + /* GPP_E03 - GPIO (CNVI_WAKE#) */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_E03, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_E03, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_E04 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E04, 0, DEEP), + + /* GPP_E05 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E05, 0, DEEP), + + /* GPP_E06 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E06, 0, DEEP), + + /* GPP_E07 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E07, 0, DEEP), + + /* GPP_E08 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E08, 0, DEEP), + + /* GPP_E09 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_E09, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_E09, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_E10 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E10, 0, DEEP), + + /* GPP_E11 - GPIO (BOARD_ID6) */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_E11, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_E11, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_E12 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E12, 0, DEEP), + + /* GPP_E13 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E13, 0, DEEP), + + /* GPP_E14 - DDSP_HPDA */ + /* DW0: 0x44000700, DW1: 0x00024000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_E14, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(TxDRxE)), + + /* GPP_E15 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E15, 0, DEEP), + + /* GPP_E16 - VRALERT# */ + /* DW0: 0x44000b02, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_E16, NONE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_E16, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(IGNORE)), + + /* GPP_E17 - GPIO (BOARD_ID5) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E17, 0, DEEP), + + /* GPP_E18 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E18, 0, DEEP), + + /* GPP_E19 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E19, 0, DEEP), + + /* GPP_E20 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E20, 0, DEEP), + + /* GPP_E21 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E21, 0, DEEP), + + /* GPP_E22 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_E22, 0, DEEP), + + /* GPP_E23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_E23, NONE), + + /* GPP_THC0_GSPI_CLK_LPBK - GPIO */ + /* DW0: 0x40000300, DW1: 0x00000000 */ + PAD_NC(GPP_THC0_GSPI_CLK_LPBK, NONE), + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H00 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H00, 0, DEEP), + + /* GPP_H01 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H01, 0, DEEP), + + /* GPP_H02 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H02, 0, DEEP), + + /* GPP_H03 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H03, 0, DEEP), + + /* GPP_H04 - GPIO (TODO: should be CNV_MFUART2_RXD - NF2) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H04, 0, DEEP), + + /* GPP_H05 - GPIO (TODO: should be CNV_MFUART2_TXD - NF2) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H05, 0, DEEP), + + /* GPP_H06 - I2C3_SDA */ + /* DW0: 0x44000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_H06, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H06, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_H07 - I2C3_SCL */ + /* DW0: 0x44000600, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_H07, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H07, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), 0), + + /* GPP_H08 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + /* PAD_CFG_GPO(GPP_H08, 0, DEEP), */ + PAD_CFG_NF(GPP_H08, NONE, DEEP, NF1), /* UART0_RXD */ + + /* GPP_H09 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + /* PAD_CFG_GPO(GPP_H09, 0, DEEP), */ + PAD_CFG_NF(GPP_H09, NONE, DEEP, NF1), /* UART0_TXD */ + + /* GPP_H10 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H10, 0, DEEP), + + /* GPP_H11 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H11, 0, DEEP), + + /* GPP_H12 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H12, 0, DEEP), + + /* GPP_H13 - PROC_C10_GATE# */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_H13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_H14 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H14, 0, DEEP), + + /* GPP_H15 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H15, 0, DEEP), + + /* GPP_H16 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H16, 0, DEEP), + + /* GPP_H17 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H17, 0, DEEP), + + /* GPP_H18 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_H18, 0, DEEP), + + /* GPP_H19 - I2C0_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H20 - I2C0_SCL */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_H20, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H21 - I2C1_SDA */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H21, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_H22 - I2C1_SCL */ + /* DW0: 0x44000602, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_H22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | (1 << 1), 0), + + /* GPP_H23 - GPIO */ + /* DW0: 0x44000300, DW1: 0x00000000 */ + PAD_NC(GPP_H23, NONE), + + /* GPP_LPI3C1_CLK_LPBK - GPIO */ + /* DW0: 0x40000300, DW1: 0x00003c00 */ + PAD_NC(GPP_LPI3C1_CLK_LPBK, NATIVE), + + /* GPP_LPI3C0_CLK_LPBK - n/a */ + /* DW0: 0x40000b02, DW1: 0x00003c00 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_LPI3C0_CLK_LPBK, NATIVE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_LPI3C0_CLK_LPBK, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F00 - CNV_BRI_DT */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_F00, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F00, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_F01 - CNV_BRI_RSP */ + /* DW0: 0x44000702, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_F01, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F01, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_F02 - CNV_RGI_DT */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_F02, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F02, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_F03 - CNV_RGI_RSP */ + /* DW0: 0x44000700, DW1: 0x0003f000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_F03, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F03, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* GPP_F04 - CNV_RF_RESET# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_F04, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_F04, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_F05 - MODEM_CLKREQ */ + /* DW0: 0x44000d00, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_F05, NONE, DEEP, NF3), */ + _PAD_CFG_STRUCT(GPP_F05, PAD_FUNC(NF3) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_F06 - GPIO (should be CNV_PA_BLANKING - NF1)*/ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F06, 0, DEEP), + + /* GPP_F07 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F07, 0, DEEP), + + /* GPP_F08 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F08, 0, DEEP), + + /* GPP_F09 - GPIO (TPM_DET) */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F09, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_F09, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_F10 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + + /* GPP_F11 - GPIO (BOARD_ID3) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F11, 0, DEEP), + + /* GPP_F12 - GPIO (I2C5_SCL smart amp) */ + /* DW0: 0x44002102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F12, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_F12, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_F13 - GPIO (I2C5_SDA smart amp) */ + /* DW0: 0x44002102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_F13, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_F13, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_F14 - GPIO (BOARD_ID1) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F14, 0, DEEP), + + /* GPP_F15 - GPIO (BOARD_ID2) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + + /* GPP_F16 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F16, 0, DEEP), + + /* GPP_F17 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + + /* GPP_F18 - GPIO (CPU_CCD_WP#) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F18, 0, DEEP), + + /* GPP_F19 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F19, 0, DEEP), + + /* GPP_F20 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F20, 0, DEEP), + + /* GPP_F21 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + + /* GPP_F22 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F22, 0, DEEP), + + /* GPP_F23 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_F23, 0, DEEP), + + /* GPP_THC1_GSPI1_CLK_LPBK - GPIO */ + /* DW0: 0x40000300, DW1: 0x00000000 */ + PAD_NC(GPP_THC1_GSPI1_CLK_LPBK, NONE), + + /* GPP_GSPI0A_CLK_LOOPBK - GPIO */ + /* DW0: 0x40002300, DW1: 0x00000000 */ + /* DW0: 0 - IGNORED */ + /* PAD_NC(GPP_GSPI0A_CLK_LOOPBK, NONE), */ + _PAD_CFG_STRUCT(GPP_GSPI0A_CLK_LOOPBK, PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE), 0), + + /* ------- GPIO Group SPI ------- */ + + /* ------- GPIO Group VGPIO3 ------- */ + + /* GPP_VGPIO3_USB0 - GPP_VGPIO3_USB0 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO3_USB0, NONE, DEEP, NF1), + + /* GPP_VGPIO3_USB1 - GPP_VGPIO3_USB1 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO3_USB1, NONE, DEEP, NF1), + + /* GPP_VGPIO3_USB2 - GPP_VGPIO3_USB2 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO3_USB2, NONE, DEEP, NF1), + + /* GPP_VGPIO3_USB3 - GPP_VGPIO3_USB3 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO3_USB3, NONE, DEEP, NF1), + + /* GPP_VGPIO3_USB4 - GPP_VGPIO3_USB4 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_VGPIO3_USB4, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_VGPIO3_USB4, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + + /* GPP_VGPIO3_USB5 - GPP_VGPIO3_USB5 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_VGPIO3_USB5, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_VGPIO3_USB5, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + + /* GPP_VGPIO3_USB6 - GPP_VGPIO3_USB6 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_VGPIO3_USB6, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_VGPIO3_USB6, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + + /* GPP_VGPIO3_USB7 - GPP_VGPIO3_USB7 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_VGPIO3_USB7, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_VGPIO3_USB7, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + + /* GPP_VGPIO3_TS0 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS0, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO3_TS1 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_TS1, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO3_THC0 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC0, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_VGPIO3_THC0, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_VGPIO3_THC1 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC1, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_VGPIO3_THC1, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_VGPIO3_THC2 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC2, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO3_THC3 - GPIO */ + /* DW0: 0x44000100, DW1: 0x00000000 */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO3_THC3, NONE, DEEP, OFF, ACPI), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S00 - GPIO */ + /* DW0: 0x44000200, DW1: 0x01800000 */ + PAD_CFG_GPO(GPP_S00, 0, DEEP), + + /* GPP_S01 - GPIO */ + /* DW0: 0x44000200, DW1: 0x01800000 */ + PAD_CFG_GPO(GPP_S01, 0, DEEP), + + /* GPP_S02 - GPIO */ + /* DW0: 0x44000200, DW1: 0x01800000 */ + PAD_CFG_GPO(GPP_S02, 0, DEEP), + + /* GPP_S03 - GPIO */ + /* DW0: 0x44000200, DW1: 0x01800000 */ + PAD_CFG_GPO(GPP_S03, 0, DEEP), + + /* GPP_S04 - GPIO */ + /* DW0: 0x44000200, DW1: 0x01800000 */ + PAD_CFG_GPO(GPP_S04, 0, DEEP), + + /* GPP_S05 - GPIO */ + /* DW0: 0x44000200, DW1: 0x01800000 */ + PAD_CFG_GPO(GPP_S05, 0, DEEP), + + /* GPP_S06 - GPIO */ + /* DW0: 0x44000200, DW1: 0x01800000 */ + PAD_CFG_GPO(GPP_S06, 0, DEEP), + + /* GPP_S07 - GPIO */ + /* DW0: 0x44000200, DW1: 0x01800000 */ + PAD_CFG_GPO(GPP_S07, 0, DEEP), + + /* ------- GPIO Group JTAG ------- */ + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B00 - GPIO (TP_ATTN#) */ + /* DW0: 0x80800102, DW1: 0x00000000 */ + /* DW0: PAD_RX_POL(INVERT) | (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_B00, NONE, PLTRST, LEVEL, ACPI), */ + //_PAD_CFG_STRUCT(GPP_B00, PAD_RESET(PLTRST) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + PAD_CFG_GPI_INT(GPP_B00, NONE, PLTRST, LEVEL), + + /* GPP_B01 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B01, 0, DEEP), + + /* GPP_B02 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B02, 0, DEEP), + + /* GPP_B03 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B03, 0, DEEP), + + /* GPP_B04 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B04, 0, DEEP), + + /* GPP_B05 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B05, 0, DEEP), + + /* GPP_B06 - GPIO (ROM_I2C_EN) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B06, 0, DEEP), + + /* GPP_B07 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B07, 0, DEEP), + + /* GPP_B08 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B08, 0, DEEP), + + /* GPP_B09 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B09, 0, DEEP), + + /* GPP_B10 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B10, 0, DEEP), + + /* GPP_B11 - DDSP_HPD2 */ + /* DW0: 0x44000b02, DW1: 0x00024000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_B11, NONE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_B11, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_IOSSTATE(TxDRxE)), + + /* GPP_B12 - SLP_S0# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_B13 - PLTRST# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_B13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_B14 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_B14, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_B14, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_B15 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_B15, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_B15, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* GPP_B16 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B16, 0, DEEP), + + /* GPP_B17 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B17, 0, DEEP), + + /* GPP_B18 - GPIO (PCH_BT_EN) */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B18, 1, DEEP), + + /* GPP_B19 - GPIO (WIFI_RF_EN) */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B19, 1, DEEP), + + /* GPP_B20 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B20, 0, DEEP), + + /* GPP_B21 - GPIO (TCP_RETIMER_FORCE_PWR) */ + /* DW0: 0x84000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B21, 1, PLTRST), + + /* GPP_B22 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B22, 0, DEEP), + + /* GPP_B23 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* GPP_ACI3C0_CLK_LPBK - n/a */ + /* DW0: 0x40001302, DW1: 0x00003c00 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_ACI3C0_CLK_LPBK, NATIVE, DEEP, NF4), */ + _PAD_CFG_STRUCT(GPP_ACI3C0_CLK_LPBK, PAD_FUNC(NF4) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE)), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D00 - GPIO (SB_BLON) */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D00, 1, DEEP), + + /* GPP_D01 - GPIO (SSD2_PWR_EN) */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D01, 1, DEEP), + + /* GPP_D02 - GPIO (M2_SSD1_RST#) */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D02, 1, DEEP), + + /* GPP_D03 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D03, 0, DEEP), + + /* GPP_D04 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D04, 0, DEEP), + + /* GPP_D05 - GPIO (SSD1_PWR_EN) */ + /* DW0: 0x44000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D05, 1, DEEP), + + /* GPP_D06 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D06, 0, DEEP), + + /* GPP_D07 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D07, 0, DEEP), + + /* GPP_D08 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D08, 0, DEEP), + + /* GPP_D09 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D09, 0, DEEP), + + /* GPP_D10 - HDA_BCLK */ + /* DW0: 0x44000600, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_D10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_D11 - HDA_SYNC */ + /* DW0: 0x44000700, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_D11, NATIVE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D11, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + + /* GPP_D12 - HDA_SDO */ + /* DW0: 0x44000600, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_D12, NATIVE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D12, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + + /* GPP_D13 - HDA_SDI0 */ + /* DW0: 0x44000700, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_D13, NATIVE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + + /* GPP_D14 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D14, 0, DEEP), + + /* GPP_D15 - GPIO */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), + + /* GPP_D16 - GPIO (GPIO_SPK_MUTE) */ + /* DW0: 0x44000200, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_D16, 0, DEEP), + + /* GPP_D17 - HDA_RST# */ + /* DW0: 0x44000700, DW1: 0x0003c000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D17, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_IOSSTATE(IGNORE)), + + /* GPP_D18 - SRCCLKREQ6# (NC?) */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D18, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D19 - SRCCLKREQ7# (SSD1) */ + /* DW0: 0x44000700, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D19, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), 0), + + /* GPP_D20 - SRCCLKREQ8# (SSD2) */ + /* DW0: 0x44000702, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D20, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_D21 - SRCCLKREQ5# (WLAN) */ + /* DW0: 0x44000b02, DW1: 0x00000000 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_D21, NONE, DEEP, NF2), */ + _PAD_CFG_STRUCT(GPP_D21, PAD_FUNC(NF2) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), 0), + + /* GPP_D22 - n/a */ + /* DW0: 0x44000700, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) - IGNORED */ + /* PAD_CFG_NF(GPP_D22, NATIVE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + + /* GPP_D23 - n/a */ + /* DW0: 0x44000702, DW1: 0x0003fc00 */ + /* DW0: PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_D23, NATIVE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_D23, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(NATIVE) | PAD_IOSSTATE(IGNORE)), + + /* GPP_BOOTHALT_B - n/a */ + /* DW0: 0x40000702, DW1: 0x0003f000 */ + /* DW0: PAD_BUF(TX_RX_DISABLE) | (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_BOOTHALT_B, UP_20K, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_BOOTHALT_B, PAD_FUNC(NF1) | PAD_RESET(DEEP) | PAD_BUF(TX_RX_DISABLE) | (1 << 1), PAD_PULL(UP_20K) | PAD_IOSSTATE(IGNORE)), + + /* ------- GPIO Group VGPIO ------- */ + + /* VGPIO00 - GPIO */ + /* DW0: 0x40000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_VGPIO00, 1, DEEP), + + /* VGPIO04 - GPIO */ + /* DW0: 0x44000102, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO04, NONE, DEEP, OFF, ACPI), */ + _PAD_CFG_STRUCT(GPP_VGPIO04, PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_BUF(TX_DISABLE) | (1 << 1), 0), + + /* VGPIO05 - GPIO */ + /* DW0: 0x40000201, DW1: 0x00000000 */ + PAD_CFG_GPO(GPP_VGPIO05, 1, DEEP), + + /* VGPIO06 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO06, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO07 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO07, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO08 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO08, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO09 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO09, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO10 - VGPIO10 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_VGPIO10, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_VGPIO10, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + + /* VGPIO11 - VGPIO11 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO11, NONE, DEEP, NF1), + + /* VGPIO12 - VGPIO12 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO12, NONE, DEEP, NF1), + + /* VGPIO13 - VGPIO13 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_VGPIO13, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_VGPIO13, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + + /* VGPIO18 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO18, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO19 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO19, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO20 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO20, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO21 - GPIO */ + /* DW0: 0x40000000, DW1: 0x00000000 */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO21, 0, NONE, DEEP, LEVEL, ACPI), + + /* VGPIO22 - VGPIO22 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_VGPIO22, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_VGPIO22, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + + /* VGPIO23 - VGPIO23 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO23, NONE, DEEP, NF1), + + /* VGPIO24 - VGPIO24 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO24, NONE, DEEP, NF1), + + /* VGPIO25 - VGPIO25 */ + /* DW0: 0x40000402, DW1: 0x00000000 */ + /* DW0: (1 << 1) - IGNORED */ + /* PAD_CFG_NF(GPP_VGPIO25, NONE, DEEP, NF1), */ + _PAD_CFG_STRUCT(GPP_VGPIO25, PAD_FUNC(NF1) | PAD_RESET(DEEP) | (1 << 1), 0), + + /* VGPIO30 - RESERVED */ + /* DW0: 0x40000c00, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO30, NONE, DEEP, NF3), + + /* VGPIO31 - RESERVED */ + /* DW0: 0x40000c00, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO31, NONE, DEEP, NF3), + + /* VGPIO32 - RESERVED */ + /* DW0: 0x40000c00, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO32, NONE, DEEP, NF3), + + /* VGPIO33 - RESERVED */ + /* DW0: 0x40000c00, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO33, NONE, DEEP, NF3), + + /* VGPIO34 - VGPIO34 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO34, NONE, DEEP, NF1), + + /* VGPIO35 - VGPIO35 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO35, NONE, DEEP, NF1), + + /* VGPIO36 - VGPIO36 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO36, NONE, DEEP, NF1), + + /* VGPIO37 - VGPIO37 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO37, NONE, DEEP, NF1), + + /* VGPIO40 - RESERVED */ + /* DW0: 0x40000800, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO40, NONE, DEEP, NF2), + + /* VGPIO41 - RESERVED */ + /* DW0: 0x40000800, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO41, NONE, DEEP, NF2), + + /* VGPIO42 - RESERVED */ + /* DW0: 0x40000800, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO42, NONE, DEEP, NF2), + + /* VGPIO43 - RESERVED */ + /* DW0: 0x40000800, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO43, NONE, DEEP, NF2), + + /* VGPIO44 - VGPIO44 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO44, NONE, DEEP, NF1), + + /* VGPIO45 - VGPIO45 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO45, NONE, DEEP, NF1), + + /* VGPIO46 - VGPIO46 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO46, NONE, DEEP, NF1), + + /* VGPIO47 - VGPIO47 */ + /* DW0: 0x40000400, DW1: 0x00000000 */ + PAD_CFG_NF(GPP_VGPIO47, NONE, DEEP, NF1), +}; + +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c b/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c new file mode 100644 index 00000000000..b94a1947376 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/hda_verb.c @@ -0,0 +1,70 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Realtek, ALC245 */ + 0x10ec0245, /* Vendor ID */ + 0x1558a763, /* Subsystem ID */ + 40, /* Number of entries */ + AZALIA_SUBVENDOR(0, 0x1558a763), + AZALIA_RESET(1), + AZALIA_PIN_CFG(0, 0x12, 0x90a60130), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x411111f0), + AZALIA_PIN_CFG(0, 0x19, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1a, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1b, 0x411111f0), + AZALIA_PIN_CFG(0, 0x1d, 0x40789b2d), + AZALIA_PIN_CFG(0, 0x1e, 0x411111f0), + AZALIA_PIN_CFG(0, 0x21, 0x04211020), + + 0x5B50006, 0x5B40011, 0x205001A, 0x204810B, + 0x205004A, 0x2042010, 0x2050038, 0x2047909, + 0x5C50000, 0x5C43D82, 0x5C50000, 0x5C43D82, + 0x5350000, 0x534201A, 0x5350000, 0x534201A, + 0x535001D, 0x5340800, 0x535001E, 0x5340800, + 0x5350003, 0x5341EC4, 0x5350004, 0x5340000, + 0x5450000, 0x5442000, 0x545001D, 0x5440800, + 0x545001E, 0x5440800, 0x5450003, 0x5441EC4, + 0x5450004, 0x5440000, 0x5350000, 0x534A01A, + 0x205003C, 0x204F175, 0x205003C, 0x204F135, + 0x2050040, 0x2048800, 0x5A50001, 0x5A4001F, + 0x2050010, 0x2040020, 0x2050010, 0x2040020, + 0x205006B, 0x204A390, 0x205006B, 0x204A390, + 0x205006C, 0x2040C9E, 0x205006D, 0x2040C00, + 0x170500, 0x170500, 0x5A50004, 0x5A40113, + 0x2050008, 0x2046A8C, 0x2050076, 0x204F000, + 0x205000E, 0x20465C0, 0x2050033, 0x2048580, + 0x2050069, 0x204FDA8, 0x2050068, 0x2040000, + 0x2050003, 0x2040002, 0x2050069, 0x2040000, + 0x2050068, 0x2040001, 0x205002E, 0x204290E, + 0x2236100, 0x2235100, 0x920011, 0x970610, + 0x936000, 0x935000, 0x205000D, 0x204A020, + 0x220011, 0x270610, 0x23A046, 0x239046, + 0x173B000, 0x1770740, 0x5A50001, 0x5A4001F, + 0x5C5000F, 0x5C40003, 0x2050036, 0x20437D7, + 0x143B000, 0x1470740, 0x2050010, 0x2040020, + 0x1470C02, 0x1470C02, 0x1470C02, 0x1470C02, + + /* Intel Meteor Lake HDMI */ + 0x8086281d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 10, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010), + AZALIA_PIN_CFG(2, 0x0c, 0x18560010), + AZALIA_PIN_CFG(2, 0x0d, 0x18560010), + AZALIA_PIN_CFG(2, 0x0e, 0x18560010), + AZALIA_PIN_CFG(2, 0x0f, 0x18560010), +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb new file mode 100644 index 00000000000..d668c7c79c6 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/overridetree.cb @@ -0,0 +1,51 @@ +chip soc/intel/meteorlake + # Power limits, + # PsysPL2, PsysPL3, PL4 are configured by EC at runtime + register "power_limits_config[MTL_P_682_482_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 64, + .tdp_pl4 = 90, + .psys_pmax = 99, + }" + + # MTL SOC has additional setting for PsysPmax + register "psys_pmax_watts" = "99" + + device domain 0 on + subsystemid 0x1558 0xa743 inherit + device ref igpu on + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD, /* eDP */ + [DDI_PORT_3] = DDI_ENABLE_DDC | DDI_ENABLE_HPD, /* HDMI 2.1 */ + }" + end + device ref i2c0 on # Touchpad + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + chip drivers/i2c/hid + register "generic.hid" = ""ELAN0412"" + register "generic.desc" = ""ELAN Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 15 on end + end + chip drivers/i2c/hid + register "generic.hid" = ""FTCS1000"" + register "generic.desc" = ""FocalTech Touchpad"" + register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_B00)" + register "generic.detect" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 38 on end + end + end + device ref pcie_rp5 on # GLAN + register "pcie_rp[PCH_RP(5)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR, + }" + register "pcie_clk_config_flag[2]" = "PCIE_CLK_LAN" + end + device ref gbe on end + end +end diff --git a/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c b/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c new file mode 100644 index 00000000000..4d559dea539 --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/variants/igpu/ramstage.c @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ + +/* + * This is a placeholder, if there ever is something variant specific to + * add to ramstage, do it here. + */ diff --git a/src/mainboard/novacustom/mtl-h/vboot-rwa.fmd b/src/mainboard/novacustom/mtl-h/vboot-rwa.fmd new file mode 100644 index 00000000000..9b028748c6a --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/vboot-rwa.fmd @@ -0,0 +1,48 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K +#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION + SI_GBE 8K +#endif + SI_ME + } + SI_BIOS { + RW_UNUSED 7M + + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + BOOTSPLASH(CBFS) 1M + } + + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + + WP_RO 7M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd new file mode 100644 index 00000000000..55ac9f1a6bf --- /dev/null +++ b/src/mainboard/novacustom/mtl-h/vboot-rwab.fmd @@ -0,0 +1,52 @@ +FLASH 32M { + SI_ALL 9M { + SI_DESC 16K +#if CONFIG_MAINBOARD_USES_IFD_GBE_REGION + SI_GBE 8K +#endif + SI_ME + } + SI_BIOS { + RW_SECTION_A 7M { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 64 + } + + # This section starts at the 16M boundary in SPI flash. + # MTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_MISC 2M { + UNIFIED_MRC_CACHE(PRESERVE) 128K { + RECOVERY_MRC_CACHE 64K + RW_MRC_CACHE 64K + } + SMMSTORE(PRESERVE) 256K + RW_ELOG(PRESERVE) 16K + RW_SHARED 16K { + SHARED_DATA 8K + VBLOCK_DEV 8K + } + RW_NVRAM(PRESERVE) 24K + BOOTSPLASH(CBFS) 1M + } + + RW_SECTION_B 7M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } + + WP_RO 7M { + RO_VPD(PRESERVE) 16K + RO_GSCVD 8K + RO_SECTION { + FMAP 2K + RO_FRID 64 + GBB@4K 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/novacustom/tgl-u/Kconfig b/src/mainboard/novacustom/tgl-u/Kconfig new file mode 100644 index 00000000000..c63e7f9ab3d --- /dev/null +++ b/src/mainboard/novacustom/tgl-u/Kconfig @@ -0,0 +1,9 @@ +config BOARD_NOVACUSTOM_NV4X_TGLU + select BOARD_CLEVO_NV40MZ_BASE + +config BOARD_NOVACUSTOM_NS5X_TGLU + select BOARD_CLEVO_NS50MU_BASE + +config MAINBOARD_PART_NUMBER + default "nv40mz" if BOARD_NOVACUSTOM_NV4X_TGLU + default "ns50mu" if BOARD_NOVACUSTOM_NS5X_TGLU diff --git a/src/mainboard/novacustom/tgl-u/Kconfig.name b/src/mainboard/novacustom/tgl-u/Kconfig.name new file mode 100644 index 00000000000..3ef1695e3dc --- /dev/null +++ b/src/mainboard/novacustom/tgl-u/Kconfig.name @@ -0,0 +1,7 @@ +comment "Tiger Lake U (2021)" + +config BOARD_NOVACUSTOM_NV4X_TGLU + bool "NV4x TGL" + +config BOARD_NOVACUSTOM_NS5X_TGLU + bool "NS5x TGL" diff --git a/src/mainboard/novacustom/tgl-u/board_info.txt b/src/mainboard/novacustom/tgl-u/board_info.txt new file mode 100644 index 00000000000..a947b7df00f --- /dev/null +++ b/src/mainboard/novacustom/tgl-u/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: NovaCustom +Board name: tgl-u +Category: laptop +Release year: 2021 +ROM package: SOIC-8 +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 381bfcbd808..43c7b03d1ae 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only if BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || BOARD_PCENGINES_APU4 || \ - BOARD_PCENGINES_APU5 + BOARD_PCENGINES_APU5 || BOARD_PCENGINES_APU6 config BOARD_SPECIFIC_OPTIONS def_bool y @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE + select HAVE_SMI_HANDLER config MAINBOARD_DIR default "pcengines/apu2" @@ -30,6 +31,7 @@ config VARIANT_DIR default "apu3" if BOARD_PCENGINES_APU3 default "apu4" if BOARD_PCENGINES_APU4 default "apu5" if BOARD_PCENGINES_APU5 + default "apu6" if BOARD_PCENGINES_APU6 config DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb" @@ -39,6 +41,7 @@ config MAINBOARD_PART_NUMBER default "apu3" if BOARD_PCENGINES_APU3 default "apu4" if BOARD_PCENGINES_APU4 default "apu5" if BOARD_PCENGINES_APU5 + default "apu6" if BOARD_PCENGINES_APU6 config MAX_CPUS int @@ -66,7 +69,7 @@ config APU2_PINMUX_OFF_C config APU2_PINMUX_GPIO0 bool "GPIO" depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ - BOARD_PCENGINES_APU4 + BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 config APU2_PINMUX_UART_C bool "UART 0x3e8" @@ -83,7 +86,7 @@ config APU2_PINMUX_OFF_D config APU2_PINMUX_GPIO1 bool "GPIO" depends on BOARD_PCENGINES_APU2 || BOARD_PCENGINES_APU3 || \ - BOARD_PCENGINES_APU4 + BOARD_PCENGINES_APU4 || BOARD_PCENGINES_APU6 config APU2_PINMUX_UART_D bool "UART 0x2e8" @@ -103,4 +106,39 @@ config AGESA_USE_1_0_0_4_HEADER revisions. This option removes the changes in headers introduced with AGESA 1.0.0.A to fit the 1.0.0.4 revision. +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config VBOOT_VBNV_OFFSET + hex + default 0x38 + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select VBOOT_STARTS_IN_BOOTBLOCK + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_NO_BOARD_SUPPORT + select VBOOT_NO_TPM + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select CBFS_VERIFICATION + select VBOOT_CBFS_INTEGRATION + select VBOOT_VBNV_CMOS + select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH + +if VBOOT + +config VBOOT_SLOTS_RW_A + default y + +config RO_REGION_ONLY + default "AGESA apu/amdfw" + +endif + endif # BOARD_PCENGINES_APU2 diff --git a/src/mainboard/pcengines/apu2/Kconfig.name b/src/mainboard/pcengines/apu2/Kconfig.name index 170080396ce..8ee55dbe605 100644 --- a/src/mainboard/pcengines/apu2/Kconfig.name +++ b/src/mainboard/pcengines/apu2/Kconfig.name @@ -11,3 +11,6 @@ config BOARD_PCENGINES_APU4 config BOARD_PCENGINES_APU5 bool "APU5" + +config BOARD_PCENGINES_APU6 + bool "APU6" diff --git a/src/mainboard/pcengines/apu2/OemCustomize.c b/src/mainboard/pcengines/apu2/OemCustomize.c index 95af6ef92d5..0a0f91a65bf 100644 --- a/src/mainboard/pcengines/apu2/OemCustomize.c +++ b/src/mainboard/pcengines/apu2/OemCustomize.c @@ -1,11 +1,19 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include +#include #include +#include #include "gpio_ftns.h" -static const PCIe_PORT_DESCRIPTOR PortList[] = { +/* + * The configuration data is duplicated for different states of power management + * because modifiable globals aren't allowed in romstage. + */ + +static const PCIe_PORT_DESCRIPTOR PortListAspm[] = { { 0, PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), @@ -15,7 +23,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x01, - 0) + 1) }, /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ { @@ -27,7 +35,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x02, - 0) + 1) }, /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ { @@ -39,7 +47,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x03, - 0) + 1) }, /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ { @@ -51,7 +59,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x04, - 0) + 1) }, /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ { @@ -63,6 +71,68 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = { PcieGenMaxSupported, AspmL0sL1, 0x05, + 1) + } +}; + +static const PCIe_PORT_DESCRIPTOR PortList[] = { + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 3, 3), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 5, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x01, + 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 2, 2), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 4, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x02, + 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 1, 1), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 3, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x03, + 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ + { + 0, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 0, 0), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 2, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x04, + 0) + }, + /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ + { + DESCRIPTOR_TERMINATE_LIST, + PCIE_ENGINE_DATA_INITIALIZER(PciePortEngine, 4, 7), + PCIE_PORT_DATA_INITIALIZER_V2(PortEnabled, ChannelTypeExt6db, 2, 1, + HotplugDisabled, + PcieGenMaxSupported, + PcieGenMaxSupported, + AspmDisabled, + 0x05, 0) } }; @@ -74,11 +144,57 @@ static const PCIe_COMPLEX_DESCRIPTOR PcieComplex = { .DdiLinkList = NULL, }; +static const PCIe_COMPLEX_DESCRIPTOR PcieComplexAspm = { + .Flags = DESCRIPTOR_TERMINATE_LIST, + .SocketId = 0, + .PciePortList = PortListAspm, + .DdiLinkList = NULL, +}; + void board_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *InitEarly) { - InitEarly->GnbConfig.PcieComplexList = &PcieComplex; - InitEarly->PlatformConfig.CStateMode = CStateModeC6; - InitEarly->PlatformConfig.CpbMode = CpbModeAuto; + if (dasharo_apu_pcie_pm_enabled()) + InitEarly->GnbConfig.PcieComplexList = &PcieComplexAspm; + else + InitEarly->GnbConfig.PcieComplexList = &PcieComplex; + + if (dasharo_apu_cpu_boost_enabled()) { + InitEarly->PlatformConfig.CStateMode = CStateModeC6; + InitEarly->PlatformConfig.CpbMode = CpbModeAuto; + } + + if (boot_cpu()) { + volatile uint32_t *ptr = (uint32_t *)(ACPI_MMIO_BASE + WATCHDOG_BASE); + + /* + * Set PMxBE[RstToCpuPwrGdEn] = 1: FCH toggles CpuPwrGd on every reset. + * Without it, after watchdog causes a restart, D18F5x84[CmpCap] + * (number of cores on the node) sometimes reads as 0. Because of that + * AGESA hangs in subsequent InitReset calls, until next cold reset. + */ + volatile u8 *rc1 = (u8 *)(ACPI_MMIO_BASE + PMIO_BASE + FCH_PMIOA_REGBE); + *rc1 |= 0x80; + + uint16_t watchdog_timeout = dasharo_apu_watchdog_timeout(); + + if (watchdog_timeout == 0) { + /* watchdog disabled - default state */ + printk(BIOS_INFO, "Watchdog is disabled\n"); + } else { + /* bit 1 (WatchdogFired) is write-1-to-clear, needs to be preserved */ + uint32_t val = *ptr & ~(1 << 1); + /* enable */ + *ptr = val | (1 << 0); + /* configure timeout */ + *(ptr + 1) = (uint16_t)watchdog_timeout; + /* trigger */ + val = *ptr & ~(1 << 1); + *ptr = val | (1 << 7); + + printk(BIOS_INFO, "Watchdog is enabled, state = 0x%x, time = %d\n", + *ptr, *(ptr + 1)); + } + } } void board_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) diff --git a/src/mainboard/pcengines/apu2/board.fmd b/src/mainboard/pcengines/apu2/board.fmd new file mode 100644 index 00000000000..242e15c4e28 --- /dev/null +++ b/src/mainboard/pcengines/apu2/board.fmd @@ -0,0 +1,18 @@ +FLASH 8M { + SI_BIOS@0x0 0x800000 { + SMMSTORE(PRESERVE)@0x0 0x40000 + BOOTORDER(PRESERVE)@0x40000 0x1000 + + RW_UNUSED@0x41000 0x1bf000 + + WP_RO@0x200000 0x600000 { + RO_SECTION@0x0 0x600000{ + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_FRID_PAD@0x840 0x7c0 + GBB@0x1000 0x40000 + COREBOOT(CBFS)@0x41000 0x5bf000 + } + } + } +} diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout index fbfe445741f..93b4aeff840 100644 --- a/src/mainboard/pcengines/apu2/cmos.layout +++ b/src/mainboard/pcengines/apu2/cmos.layout @@ -11,7 +11,7 @@ entries 400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 444 1 e 1 nmi -728 256 h 0 user_data +448 128 r 0 vbnv 984 16 h 0 check_sum # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved @@ -32,4 +32,4 @@ enumerations checksums -checksum 392 983 984 +checksum 392 447 984 diff --git a/src/mainboard/pcengines/apu2/mainboard.c b/src/mainboard/pcengines/apu2/mainboard.c index 242ad9d932e..3f73eb2075d 100644 --- a/src/mainboard/pcengines/apu2/mainboard.c +++ b/src/mainboard/pcengines/apu2/mainboard.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -22,7 +23,9 @@ #define SPD_SIZE 128 #define PM_RTC_CONTROL 0x56 +#define PM_RTC_SHADOW 0x5B #define PM_S_STATE_CONTROL 0xBA +#define PM_PCI_CONFIG 0xEA /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. @@ -167,20 +170,42 @@ static int mainboard_smbios_type16(DMI_INFO *agesa_dmi, int *handle, const int len = smbios_full_table_len(&t->header, t->eos); *current += len; + *handle += 1; + return len; } -static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, +static int ddr_speed_from_bus_speed(int bus) +{ + switch (bus) { + case 166: + case 216: + case 266: + case 333: + case 1066: + case 1666: + return bus * 2 + 1; + case 556: + case 667: + case 688: + case 813: + return bus * 2 - 1; + default: + return bus * 2; + } +} + +static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, int type16, unsigned long *current) { struct smbios_type17 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE, - sizeof(*t), *handle + 1); + sizeof(*t), *handle); - t->phys_memory_array_handle = *handle; + t->phys_memory_array_handle = type16; t->memory_error_information_handle = 0xfffe; t->total_width = agesa_dmi->T17[0][0][0].TotalWidth; t->data_width = agesa_dmi->T17[0][0][0].DataWidth; - t->size = agesa_dmi->T17[0][0][0].MemorySize; + t->size = get_spd_offset() == 0 ? 2 * 1024 : 4 * 1024; /* unit: megabytes */ t->form_factor = agesa_dmi->T17[0][0][0].FormFactor; t->device_set = agesa_dmi->T17[0][0][0].DeviceSet; t->device_locator = smbios_add_string(t->eos, @@ -189,7 +214,7 @@ static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, agesa_dmi->T17[0][0][0].BankLocator); t->memory_type = agesa_dmi->T17[0][0][0].MemoryType; t->type_detail = *(u16 *)&agesa_dmi->T17[0][0][0].TypeDetail; - t->speed = agesa_dmi->T17[0][0][0].Speed; + t->speed = ddr_speed_from_bus_speed(agesa_dmi->T17[0][0][0].Speed); t->manufacturer = agesa_dmi->T17[0][0][0].ManufacturerIdCode; t->serial_number = smbios_add_string(t->eos, agesa_dmi->T17[0][0][0].SerialNumber); @@ -197,12 +222,59 @@ static int mainboard_smbios_type17(DMI_INFO *agesa_dmi, int *handle, agesa_dmi->T17[0][0][0].PartNumber); t->attributes = agesa_dmi->T17[0][0][0].Attributes; t->extended_size = agesa_dmi->T17[0][0][0].ExtSize; - t->clock_speed = agesa_dmi->T17[0][0][0].ConfigSpeed; + t->clock_speed = + ddr_speed_from_bus_speed(agesa_dmi->T17[0][0][0].ConfigSpeed); t->minimum_voltage = 1500; /* From SPD: 1.5V */ t->maximum_voltage = 1500; const int len = smbios_full_table_len(&t->header, t->eos); *current += len; + *handle += 1; + + return len; +} + +static int mainboard_smbios_type19(unsigned long *current, int *handle, int type16, u64 *addr_end) +{ + struct smbios_type19 *t = smbios_carve_table(*current, + SMBIOS_MEMORY_ARRAY_MAPPED_ADDRESS, + sizeof(*t), *handle); + + t->memory_array_handle = type16; + t->extended_ending_address = get_spd_offset() == 0 ? 2 * 1024 : 4 * 1024; /* unit: megabytes */ + t->partition_width = 1; + t->extended_ending_address *= MiB; + t->starting_address = 0; + t->ending_address = t->extended_ending_address / KiB - 1; + t->extended_starting_address = 0; + t->extended_ending_address = 0; + *addr_end = t->ending_address; + + const int len = smbios_full_table_len(&t->header, t->eos); + *current += len; + *handle += 1; + + return len; +} + +static int mainboard_smbios_type20(unsigned long *current, int *handle, int type17, int type19, + u64 addr_end) +{ + struct smbios_type20 *t = smbios_carve_table(*current, SMBIOS_MEMORY_DEVICE_MAPPED_ADDRESS, + sizeof(*t), *handle); + + t->memory_device_handle = type17; + t->memory_array_mapped_address_handle = type19; + t->addr_start = 0; + t->addr_end = addr_end; + t->partition_row_pos = 0xff; + t->interleave_pos = 0xff; + t->interleave_depth = 0xff; + + const int len = smbios_full_table_len(&t->header, t->eos); + *current += len; + *handle += 1; + return len; } @@ -211,21 +283,82 @@ static int mainboard_smbios_data(struct device *dev, int *handle, { DMI_INFO *agesa_dmi; int len = 0; + u64 addr_end; + int type16, type17, type19; agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); if (!agesa_dmi) return len; + type16 = *handle; len += mainboard_smbios_type16(agesa_dmi, handle, current); - len += mainboard_smbios_type17(agesa_dmi, handle, current); - - *handle += 2; + type17 = *handle; + len += mainboard_smbios_type17(agesa_dmi, handle, type16, current); + type19 = *handle; + len += mainboard_smbios_type19(current, handle, type16, &addr_end); + len += mainboard_smbios_type20(current, handle, type17, type19, addr_end); return len; } + +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + DMI_INFO *agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return 0; + + return agesa_dmi->T4[0].T4CurrentSpeed; +} + +unsigned int smbios_processor_external_clock(void) +{ + DMI_INFO *agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return 0; + + return agesa_dmi->T4[0].T4ExternalClock; +} + +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + DMI_INFO *agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return 0; + + return agesa_dmi->T4[0].T4MaxSpeed; +} + +unsigned int smbios_cpu_get_voltage(void) +{ + DMI_INFO *agesa_dmi = agesawrapper_getlateinitptr(PICK_DMI); + + if (!agesa_dmi) + return 0; + + return agesa_dmi->T4[0].T4Voltage; +} #endif +static void measure_amd_blobs(void) +{ + void *amdfw = NULL; + size_t size; + + /* Simply mapping the CBFS file will trigger the measurement */ + amdfw = cbfs_unverified_area_map("COREBOOT", "apu/amdfw", &size); + + if (!amdfw) { + printk(BIOS_ERR,"Could not map apu/amdfw CBFS file\n"); + return; + } + + cbfs_unmap(amdfw); +} + static void mainboard_enable(struct device *dev) { /* Maintain this text unchanged for manufacture process. */ @@ -243,15 +376,68 @@ static void mainboard_enable(struct device *dev) // pm_write16(PM_S_STATE_CONTROL, pm_read16(PM_S_STATE_CONTROL) | (1 << 14)); + // + // Enable power on after power fail + // + pm_write8(PM_RTC_SHADOW, pm_read8(PM_RTC_SHADOW) | (1 << 0)); + + // + // Enable GENINTx as GPIO + // + pm_write8(PM_PCI_CONFIG, 1); + /* Initialize the PIRQ data structures for consumption */ pirq_setup(); #if CONFIG(GENERATE_SMBIOS_TABLES) dev->ops->get_smbios_data = mainboard_smbios_data; #endif + + if (CONFIG(TPM_MEASURED_BOOT)) + measure_amd_blobs(); } static void mainboard_final(void *chip_info) { + /* ECC was not working because all memory was marked + * as excluded from ECC checking and error reporting. + * Normally one contiguous range is excluded to cover + * framebuffer region in systems with internal GPUs. + * AGESA set bit 0, EccExclEn, in register D18F5x240 as 1. + * Range was incorrectly enabled to cover all memory + * for cases without UMA (no integrated graphics). + * + * In order to clear EccExclEn DRAM scrubber needs to be + * disabled temporarily by setting D18F3x88[DisDramScrub] + */ + u32 val; + struct device *D18F3 = dev_find_device(0x1022, 0x1583, NULL); + struct device *D18F5 = dev_find_device(0x1022, 0x1585, NULL); + + /* Disable DRAM ECC scrubbing */ + val = pci_read_config32(D18F3, 0x88); + val |= (1 << 27); + pci_write_config32(D18F3, 0x88, val); + + /* Clear reserved bits in register D18F3xB8 + * + * D18F3xB8 NB Array Address has reserved bits [27:10] + * Multiple experiments showed that ECC injection + * doesn't work when these bits are set. + */ + val = pci_read_config32(D18F3, 0xB8); + val &= 0xF000003F; + pci_write_config32(D18F3, 0xB8, val); + + /* Disable ECC exclusion range */ + val = pci_read_config32(D18F5, 0x240); + val &= ~1; + pci_write_config32(D18F5, 0x240, val); + + /* Re-enable DRAM ECC scrubbing */ + val = pci_read_config32(D18F3, 0x88); + val &= ~(1 << 27); + pci_write_config32(D18F3, 0x88, val); + // // Turn off LED 2 and LED 3 // diff --git a/src/mainboard/pcengines/apu2/romstage.c b/src/mainboard/pcengines/apu2/romstage.c index 2509031f3e5..a5d35dde4c1 100644 --- a/src/mainboard/pcengines/apu2/romstage.c +++ b/src/mainboard/pcengines/apu2/romstage.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -8,6 +9,7 @@ #include #include #include +#include #include "gpio_ftns.h" @@ -17,6 +19,9 @@ void board_BeforeAgesa(struct sysinfo *cb) { u32 val; + /* CF9 shadow */ + pm_write8(FCH_PMIOA_REGC5, 0); + early_lpc_init(); /* Disable SVI2 controller to wait for command completion */ @@ -30,6 +35,31 @@ void board_BeforeAgesa(struct sysinfo *cb) pm_write8(0xea, 1); } +void board_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) +{ + u32 val; + + if (boot_cpu()) { + /* CF9 shadow: 0 */ + pm_write8(FCH_PMIOA_REGC5, 0); + + /* Check if cold boot was requested */ + val = pci_read_config32(PCI_DEV(0, 0x18, 0), 0x6C); + if (val & (1 << 4)) { + printk(BIOS_ALERT, "Forcing cold boot path\n"); + val &= ~(0x630); // ColdRstDet[4], BiosRstDet[10:9, 5] + pci_write_config32(PCI_DEV(0, 0x18, 0), 0x6C, val); + + /* S5ResetStatus */ + pm_write32(0xc0, 0x3fff003f); // Write-1-to-clear resets + + /* CF9 shadow: FullRst, SysRst, RstCmd */ + pm_write8(FCH_PMIOA_REGC5, 0xe); + printk(BIOS_ALERT, "Did not reset (yet)\n"); + } + } +} + const struct soc_amd_gpio gpio_common[] = { PAD_GPI(GPIO_49, PULL_NONE), PAD_GPI(GPIO_50, PULL_NONE), @@ -47,7 +77,7 @@ const struct soc_amd_gpio gpio_apu2[] = { PAD_GPI(GPIO_32, PULL_NONE), }; -const struct soc_amd_gpio gpio_apu34[] = { +const struct soc_amd_gpio gpio_apu346[] = { PAD_GPI(GPIO_32, PULL_NONE), PAD_GPO(GPIO_33, LOW), }; @@ -65,8 +95,9 @@ static void early_lpc_init(void) if (CONFIG(BOARD_PCENGINES_APU2)) gpio_configure_pads(gpio_apu2, ARRAY_SIZE(gpio_apu2)); - if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4)) - gpio_configure_pads(gpio_apu34, ARRAY_SIZE(gpio_apu34)); + if (CONFIG(BOARD_PCENGINES_APU3) || CONFIG(BOARD_PCENGINES_APU4) || + CONFIG(BOARD_PCENGINES_APU6)) + gpio_configure_pads(gpio_apu346, ARRAY_SIZE(gpio_apu346)); if (CONFIG(BOARD_PCENGINES_APU5)) gpio_configure_pads(gpio_apu5, ARRAY_SIZE(gpio_apu5)); diff --git a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb index 5c169208b9c..a67cb885eaa 100644 --- a/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu3/devicetree.cb @@ -48,6 +48,9 @@ chip northbridge/amd/pi/00730F01 device pnp 2e.607 off end device pnp 2e.f on end end + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM end device ref sdhci on end device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI diff --git a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb index 57eebb65220..03fe0729d3f 100644 --- a/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb +++ b/src/mainboard/pcengines/apu2/variants/apu4/devicetree.cb @@ -48,6 +48,9 @@ chip northbridge/amd/pi/00730F01 device pnp 2e.607 off end device pnp 2e.f on end end # SIO NCT5104D + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM end device ref sdhci on end device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI diff --git a/src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb b/src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb new file mode 100644 index 00000000000..5e7f01c03e8 --- /dev/null +++ b/src/mainboard/pcengines/apu2/variants/apu6/devicetree.cb @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip northbridge/amd/pi/00730F01 + device domain 0 on + subsystemid 0x1022 0x1410 inherit + + device ref iommu on end # IOMMU + device ref gpp_bridge_0 on end # LAN1 + device ref gpp_bridge_1 on end # LAN2 + device ref gpp_bridge_2 on end # LAN3 + device ref gpp_bridge_3 on end # LAN4 + device ref gpp_bridge_4 on end # mPCIe slot 1 + + chip southbridge/amd/pi/hudson + device ref xhci on end # XHCI HC0 muxed with EHCI 2 + device ref sata on end + device ref ehci_0 on end # USB EHCI0 usb[0:3] + device ref ehci_1 on end # USB EHCI1 usb[4:7] + device ref lpc_bridge on + chip superio/nuvoton/nct5104d # SIO NCT5104D + register "irq_trigger_type" = "0" + register "reset_gpios" = "1" + device pnp 2e.0 off end + device pnp 2e.2 on + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.3 on + io 0x60 = 0x2f8 + irq 0x70 = 3 + end + device pnp 2e.10 on + # UART C is conditionally turned on + io 0x60 = 0x3e8 + irq 0x70 = 4 + end + device pnp 2e.11 on + # UART D is conditionally turned on + io 0x60 = 0x2e8 + irq 0x70 = 3 + end + device pnp 2e.008 off end + device pnp 2e.108 on + io 0x60 = 0x220 + end + # GPIO0 and GPIO1 are conditionally turned on + device pnp 2e.007 on end + device pnp 2e.107 on end + device pnp 2e.607 off end + device pnp 2e.f on end + end # SIO NCT5104D + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end # LPC TPM + end + register "sd_mode" = "3" + device ref sdhci on end + device ref ehci_2 on end # USB EHCI2 usb[8:7] - muxed with XHCI + end + end +end diff --git a/src/mainboard/pcengines/apu2/vboot-rwa.fmd b/src/mainboard/pcengines/apu2/vboot-rwa.fmd new file mode 100644 index 00000000000..8f3b555d437 --- /dev/null +++ b/src/mainboard/pcengines/apu2/vboot-rwa.fmd @@ -0,0 +1,22 @@ +FLASH@0xFF800000 8M { + SI_BIOS { + SMMSTORE(PRESERVE) 256K + RW_NVRAM(PRESERVE) 4K + + RW_SECTION_A { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + WP_RO 4M { + RO_SECTION { + FMAP 4K + RO_FRID 0x100 + RO_FRID_PAD 0x700 + GBB 64K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/protectli/vault_adl_n/Kconfig b/src/mainboard/protectli/vault_adl_n/Kconfig new file mode 100644 index 00000000000..6b9e136d00a --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/Kconfig @@ -0,0 +1,93 @@ +if BOARD_PROTECTLI_VP32XX || BOARD_PROTECTLI_VP2430 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_ALDERLAKE_PCH_N + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SOC_INTEL_COMMON_BLOCK_TCSS + select SUPERIO_ITE_IT8659E + select DRIVERS_UART_8250IO + select DRIVERS_I2C_GENERIC + select DRIVERS_INTEL_PMC + select FSP_TYPE_IOT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MEMORY_MAPPED_TPM + select USE_DDR5 + +config MAINBOARD_DIR + default "protectli/vault_adl_n" + +config MAINBOARD_PART_NUMBER + default "VP32XX" if BOARD_PROTECTLI_VP32XX + default "VP2430" if BOARD_PROTECTLI_VP2430 + +config VARIANT_DIR + default "vp32xx" if BOARD_PROTECTLI_VP32XX + default "vp2430" if BOARD_PROTECTLI_VP2430 + +config MAINBOARD_VENDOR + default "Protectli" + +config MAINBOARD_FAMILY + default "Vault Pro" + +config DIMM_SPD_SIZE + default 1024 + +config DIMM_MAX + default 2 + +config UART_FOR_CONSOLE + default 0 + +config USE_PM_ACPI_TIMER + default n + +config USE_LEGACY_8254_TIMER + default y + +config CBFS_SIZE + default 0xb00000 + +config TPM_PIRQ + default 0x39 # GPP_E13_IRQ + +config INTEL_GMA_VBT_FILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/data.vbt" + +config OVERRIDE_DEVICETREE + default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" + +config VBOOT + select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_DISABLE_FWMP + select GBB_FLAG_DISABLE_LID_SHUTDOWN + select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC + select VBOOT_ALWAYS_ENABLE_DISPLAY + select VBOOT_NO_BOARD_SUPPORT + select HAS_RECOVERY_MRC_CACHE + select VBOOT_NO_TPM + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + +config VBOOT_SLOTS_RW_A + default y if VBOOT + +config SOC_INTEL_CSE_SEND_EOP_EARLY + default n + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A + +config BEEP_ON_BOOT + bool "Beep on successful boot" + default y + help + Make the platform beep using the PC speaker in final coreboot phase. + May serve as a useful indicator in headless mode that platform is + properly booting. + +endif diff --git a/src/mainboard/protectli/vault_adl_n/Kconfig.name b/src/mainboard/protectli/vault_adl_n/Kconfig.name new file mode 100644 index 00000000000..8008ec2b243 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/Kconfig.name @@ -0,0 +1,5 @@ +config BOARD_PROTECTLI_VP32XX + bool "VP3210/VP3230" + +config BOARD_PROTECTLI_VP2430 + bool "VP2430" diff --git a/src/mainboard/protectli/vault_adl_n/Makefile.mk b/src/mainboard/protectli/vault_adl_n/Makefile.mk new file mode 100644 index 00000000000..634fb45d5e3 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/Makefile.mk @@ -0,0 +1,16 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include + +bootblock-y += bootblock.c + +romstage-y += variants/$(VARIANT_DIR)/gpio.c +romstage-y += romstage_fsp_params.c + +ramstage-y += mainboard.c +ramstage-y += hda_verb.c + +all-y += die.c +smm-y += die.c + +subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/protectli/vault_adl_n/acpi/superio.asl b/src/mainboard/protectli/vault_adl_n/acpi/superio.asl new file mode 100644 index 00000000000..cf5a2c5d5fc --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/acpi/superio.asl @@ -0,0 +1,16 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8659E_SHOW_UARTA +#define IT8659E_SHOW_UARTB + +#define IT8659E_EC_IO0 +#define IT8659E_EC_IO1 +#define IT8659E_SHOW_EC + +#define IT8659E_GPIO_IO0 +#define IT8659E_GPIO_IO1 +#define IT8659E_SHOW_GPIO + +#include diff --git a/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl b/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl new file mode 100644 index 00000000000..1b24c19bd53 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/acpi/usb_pd.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +Scope (\_SB.PCI0.I2C4) +{ + Device (PD01) + { + Name (_HID, "INT3515") + Name (_UID, One) + Name (_DDN, "TPS65994 USB-C PD Controller") + Name (_STA, 0x0F) + Name (_CRS, ResourceTemplate () + { + I2cSerialBusV2 (0x0023, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , Exclusive, ) + I2cSerialBusV2 (0x0027, ControllerInitiated, 0x00061A80, + AddressingMode7Bit, "\\_SB.PCI0.I2C4", + 0x00, ResourceConsumer, , Exclusive) + Interrupt (ResourceConsumer, Level, ActiveLow) + { + GPP_F13_IRQ + } + /* Linux driver expects one interrupt resource per one I2C dev */ + Interrupt (ResourceConsumer, Level, ActiveLow) + { + GPP_F13_IRQ + } + }) + } +} diff --git a/src/mainboard/protectli/vault_adl_n/board_info.txt b/src/mainboard/protectli/vault_adl_n/board_info.txt new file mode 100644 index 00000000000..83ce8ec23e8 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/board_info.txt @@ -0,0 +1,7 @@ +Category: sbc +Board URL: https://eu.protectli.com/product/vp3230/ +ROM IC: Macronix KH25L12835F +ROM package: SOIC8 +ROM socketed: no +Flashrom support: yes +Release year: 2024 diff --git a/src/mainboard/protectli/vault_adl_n/bootblock.c b/src/mainboard/protectli/vault_adl_n/bootblock.c new file mode 100644 index 00000000000..20439474584 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/bootblock.c @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + + +#if CONFIG_UART_FOR_CONSOLE == 0 +#define UART_DEV PNP_DEV(0x2e, IT8659E_SP1) +#elif CONFIG_UART_FOR_CONSOLE == 1 +#define UART_DEV PNP_DEV(0x2e, IT8659E_SP2) +#else +#error "Wrong UART_FOR_CONSOLE setting" +#endif + +#define GPIO_DEV PNP_DEV(0x2e, IT8659E_GPIO) + +static void ite_set_gpio_iobase(u16 iobase) +{ + pnp_enter_conf_state(GPIO_DEV); + pnp_set_logical_device(GPIO_DEV); + pnp_set_iobase(GPIO_DEV, PNP_IDX_IO1, iobase); + pnp_exit_conf_state(GPIO_DEV); +} + +void bootblock_mainboard_early_init(void) +{ + /* Internal VCC_OK */ + ite_reg_write(GPIO_DEV, 0x23, 0x00); + /* Set pin native functions */ + ite_reg_write(GPIO_DEV, 0x26, 0xc0); + /* Pin28 as GP41 - PC speaker */ + ite_reg_write(GPIO_DEV, 0x28, 0x02); + /* Set GPIOs exposed on pin header as GPIO functions */ + ite_reg_write(GPIO_DEV, 0x29, 0xc0); + /* Sets a reserved bit6 to reflect original FW configuration */ + ite_reg_write(GPIO_DEV, 0x2c, 0xc9); + ite_kill_watchdog(GPIO_DEV); + /* GP41 - PC Speaker configuration */ + ite_gpio_setup(GPIO_DEV, 41, + ITE_GPIO_OUTPUT, ITE_GPIO_SIMPLE_IO_MODE, ITE_GPIO_CONTROL_DEFAULT); + ite_set_gpio_iobase(0xa00); + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/protectli/vault_adl_n/data.vbt b/src/mainboard/protectli/vault_adl_n/data.vbt new file mode 100644 index 00000000000..0ce74a433d9 Binary files /dev/null and b/src/mainboard/protectli/vault_adl_n/data.vbt differ diff --git a/src/mainboard/protectli/vault_adl_n/devicetree.cb b/src/mainboard/protectli/vault_adl_n/devicetree.cb new file mode 100644 index 00000000000..85bd98632fd --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/devicetree.cb @@ -0,0 +1,247 @@ +chip soc/intel/alderlake + # FSP configuration + + register "eist_enable" = "1" + + # Sagv Configuration + register "sagv" = "SaGv_Enabled" + register "RMT" = "0" + register "enable_c6dram" = "1" + + register "tcc_offset" = "20" # TCC of 80C + + register "common_soc_config" = "{ + // JNTP + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + // USB-PD + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 80, + .fall_time_ns = 110, + }, + }" + + + device cpu_cluster 0 on end + device domain 0 on + subsystemid 0x8086 0x7270 inherit + + device ref igpu on + register "ddi_portA_config" = "1" # HDMI on port A + register "ddi_portB_config" = "1" # DP on port B + register "ddi_ports_config" = "{ + [DDI_PORT_A] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_B] = DDI_ENABLE_HPD | DDI_ENABLE_DDC, + [DDI_PORT_1] = DDI_ENABLE_HPD, + [DDI_PORT_2] = DDI_ENABLE_HPD, + }" + end + + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB Type-C no TBT + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" # USB Type-C no TBT + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # Bits (4,5) allocated for TCSS Port3 configuration and Bits (6,7)for TCSS Port4. + # Bit0,Bit2,Bit4,Bit6 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3,Bit5,Bit7 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0x05" + # Do not configure these pads in coreboot, otherwise Type-C display won't work + # It seems coreboot attempts to program it too late. + #register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_A21, .pad_auxn_dc = GPP_A22}" + #register "typec_aux_bias_pads[1]" = "{.pad_auxp_dc = GPP_A14, .pad_auxn_dc = GPP_A15}" + + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port 1 (USB1)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref tcss_usb3_port2 on end + end + end + end + end + + device ref xhci on + register "usb2_ports[0]" = "USB2_PORT_SHORT(OC_SKIP)" # 5G + register "usb2_ports[1]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 USB2 + register "usb2_ports[2]" = "USB2_PORT_SHORT(OC_SKIP)" # FUSB1 + register "usb2_ports[3]" = "USB2_PORT_SHORT(OC_SKIP)" # USB-A 2.0 USB2 + register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C no TBT + register "usb2_ports[5]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB Type-C no TBT + register "usb2_ports[6]" = "USB2_PORT_SHORT(OC_SKIP)" # FUSB1 + register "usb2_ports[7]" = "USB2_PORT_SHORT(OC_SKIP)" # WiFi slot + + register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 5G + + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 5G (KEY_B_5G)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 2 (COM_USB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_LOWER" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 (FUSB1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port 1 (COM_USB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(FRONT, RIGHT, ACPI_PLD_GROUP(1, 2))" + register "custom_pld.vertical_position" = "PLD_VERTICAL_POSITION_UPPER" + device ref usb2_port4 on end + end + + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, RIGHT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 (FUSB1)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port7 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WiFi/Bluetooth (KEY_E_WIFI)"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port8 on end + end + end + end + end + + device ref heci1 on end + + device ref emmc on + register "emmc_enable_hs400_mode" = "true" + end + + device ref i2c0 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci" + end + + device ref i2c4 on + register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci" + end + + device ref pch_espi on + # LPC generic I/O ranges + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c0081" + + chip superio/ite/it8659e + register "TMPIN1.mode" = "THERMAL_PECI" + register "TMPIN1.offset" = "100" + register "ec.vin_mask" = "VIN0 | VIN2 | VIN3 | VIN7" + + # FAN1 is CPU fan (connector on board) + register "FAN1.mode" = "FAN_SMART_AUTOMATIC" + register "FAN1.smart.tmpin" = " 1" + register "FAN1.smart.tmp_off" = "40" + register "FAN1.smart.tmp_start" = "50" + register "FAN1.smart.tmp_full" = "85" + register "FAN1.smart.pwm_start" = "20" + register "FAN1.smart.slope" = "32" + register "FAN1.smart.tmp_delta" = "2" + + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + irq 0xf1 = 0x52 # IRQ low level + end + device pnp 2e.2 on # COM 2 + io 0x60 = 0x2f8 + irq 0x70 = 3 + irq 0xf1 = 0x52 # IRQ low level + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa20 + io 0x62 = 0xa10 + irq 0x70 = 0 # Don't use IRQ + irq 0xf0 = 0x80 # Clear 3VSB off status + irq 0xf4 = 0x60 # Use SB to control AC power loss + irq 0xfa = 0x02 # Enable 5VSB_CTRL# + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0xa08 + io 0x62 = 0xa00 + end + device pnp 2e.a off end # CIR + end + + chip drivers/pc80/tpm + device pnp 0.0 on end + end + + end + device ref p2sb hidden end + device ref pmc hidden + register "pmc_gpe0_dw0" = "PMC_GPP_A" + register "pmc_gpe0_dw1" = "PMC_GPP_R" + register "pmc_gpe0_dw2" = "PMC_GPD" + + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port5 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port6 as usb2_port + use tcss_usb3_port2 as usb3_port + device generic 1 alias conn1 on end + end + end + end + end + device ref hda on + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "true" + end + device ref smbus on end + end +end diff --git a/src/mainboard/protectli/vault_adl_n/die.c b/src/mainboard/protectli/vault_adl_n/die.c new file mode 100644 index 00000000000..5214e616d7d --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/die.c @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void die_notify(void) +{ + uint8_t beep_count = 0; + + if (ENV_POSTCAR) + return; + + /* Beep 12 times at most, constant beeps may be annoying */ + for ( ; beep_count < 12; beep_count++) { + beep(800, 300); + mdelay(200); + if (beep_count % 4 == 3) + delay(2); + } +} diff --git a/src/mainboard/protectli/vault_adl_n/dsdt.asl b/src/mainboard/protectli/vault_adl_n/dsdt.asl new file mode 100644 index 00000000000..47c0c8f6be1 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/dsdt.asl @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Device (\_SB.PCI0) { + #include + #include + #include + } + + Scope (\_SB.PCI0.LPCB) + { + #include "acpi/superio.asl" + } + + #include + + #include "acpi/usb_pd.asl" +} diff --git a/src/mainboard/protectli/vault_adl_n/hda_verb.c b/src/mainboard/protectli/vault_adl_n/hda_verb.c new file mode 100644 index 00000000000..a8a40ed595a --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/hda_verb.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* Alderlake-P HDMI */ + 0x8086281c, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 7, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + 0x00278111, + 0x00278111, + 0x00278111, + 0x00278111, + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560020), + AZALIA_PIN_CFG(2, 0x07, 0x18560030), + AZALIA_PIN_CFG(2, 0x08, 0x18560040), + 0x00278100, + 0x00278100, + 0x00278100, + 0x00278100 +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/protectli/vault_adl_n/include/variant/gpio.h b/src/mainboard/protectli/vault_adl_n/include/variant/gpio.h new file mode 100644 index 00000000000..c54657be7b8 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef VARIANT_GPIO_H +#define VARIANT_GPIO_H + +const struct pad_config *board_gpio_table(size_t *num); + +#endif /* VARIANT_GPIO_H */ diff --git a/src/mainboard/protectli/vault_adl_n/mainboard.c b/src/mainboard/protectli/vault_adl_n/mainboard.c new file mode 100644 index 00000000000..5c1e9e3efae --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/mainboard.c @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include + +const char *smbios_mainboard_product_name(void) +{ + if (CONFIG(BOARD_PROTECTLI_VP2430)) { + return "VP2430"; + } + + u32 tmp[13]; + const char *str = "Unknown Processor Name"; + + if (cpu_have_cpuid()) { + int i; + struct cpuid_result res; + if (cpu_cpuid_extended_level() >= 0x80000004) { + int j = 0; + for (i = 0; i < 3; i++) { + res = cpuid(0x80000002 + i); + tmp[j++] = res.eax; + tmp[j++] = res.ebx; + tmp[j++] = res.ecx; + tmp[j++] = res.edx; + } + tmp[12] = 0; + str = (const char *)tmp; + } + } + + if (strstr(str, "N100") != NULL) + return "VP3210"; + else if (strstr(str, "N305") != NULL) + return "VP3230"; + else + return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; +} + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + memset(params->PcieRpEnableCpm, 0, sizeof(params->PcieRpEnableCpm)); + memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); + + memset(params->CpuPcieRpEnableCpm, 0, sizeof(params->CpuPcieRpEnableCpm)); + memset(params->CpuPcieClockGating, 0, sizeof(params->CpuPcieClockGating)); + memset(params->CpuPciePowerGating, 0, sizeof(params->CpuPciePowerGating)); + memset(params->CpuPcieRpPmSci, 0, sizeof(params->CpuPcieRpPmSci)); + + // Max payload 256B + memset(params->PcieRpMaxPayload, 1, sizeof(params->PcieRpMaxPayload)); + + if (CONFIG(BOARD_PROTECTLI_VP32XX)) { + /* + * CLKREQs connected only to RP3 and RP7, but other CLKREQs are + * pulled to GND, So it should be fine to enable CPM on all RPs. + */ + params->PcieRpEnableCpm[0] = 1; + params->PcieRpEnableCpm[2] = 1; + params->PcieRpEnableCpm[4] = 1; + params->PcieRpEnableCpm[6] = 1; + params->PcieRpEnableCpm[9] = 1; + } + + // Enable port reset message on Type-C ports + params->PortResetMessageEnable[4] = 1; + params->PortResetMessageEnable[5] = 1; + + /* + * Configure AUX bias pads in FPS-S, becuase coreboot would do it too + * late and cause the Type-C displays to not work. + */ + params->IomTypeCPortPadCfg[0] = 0x09020016; // GPP_A22 + params->IomTypeCPortPadCfg[1] = 0x09020015; // GPP_A21 + params->IomTypeCPortPadCfg[2] = 0x0902000F; // GPP_A15 + params->IomTypeCPortPadCfg[3] = 0x0902000E; // GPP_A14 + + // PMC-PD controller + params->PmcPdEnable = 1; + + // IOM USB config + params->PchUsbOverCurrentEnable = 0; +} + +static void mainboard_final(void *chip_info) +{ + if (CONFIG(BEEP_ON_BOOT)) + beep(1500, 100); +} + +static void set_fan_curve(struct ite_ec_fan_config *fan, uint8_t fan_curve) +{ + switch (fan_curve) { + case FAN_CURVE_OPTION_OFF: + fan->mode = FAN_MODE_OFF; + break; + case FAN_CURVE_OPTION_PERFORMANCE: + fan->smart.pwm_start += 20; + fan->smart.tmp_full -= 10; + fan->smart.tmp_off -= 10; + fan->smart.tmp_start -= 10; + break; + case FAN_CURVE_OPTION_SILENT: + /* Do nothing, it is the default */ + default: + break; + } +} + +static void mainboard_enable(struct device *dev) +{ + struct superio_ite_it8659e_config *ite_cfg; + struct device *ite_ec = dev_find_slot_pnp(0x2e, IT8659E_EC); + uint8_t fan_curve = get_fan_curve_option(); + + if (ite_ec && ite_ec->chip_info) { + ite_cfg = (struct superio_ite_it8659e_config *)ite_ec->chip_info; + set_fan_curve(&ite_cfg->ec.fan[0], fan_curve); + if (CONFIG(BOARD_PROTECTLI_VP32XX)) + set_fan_curve(&ite_cfg->ec.fan[1], fan_curve); + } +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final, + .enable_dev = mainboard_enable +}; diff --git a/src/mainboard/protectli/vault_adl_n/romstage_fsp_params.c b/src/mainboard/protectli/vault_adl_n/romstage_fsp_params.c new file mode 100644 index 00000000000..e60c79443f9 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/romstage_fsp_params.c @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static const struct mb_cfg ddr5_mem_config = { + .type = MEM_TYPE_DDR5, + .ect = true, /* Early Command Training */ + .UserBd = BOARD_TYPE_MOBILE, + .LpDdrDqDqsReTraining = 1, +}; + +static const struct mem_spd dimm_module_spd_info = { + .topo = MEM_TOPO_DIMM_MODULE, + .smbus = { + [0] = { + .addr_dimm[0] = 0x50, + }, + }, +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct pad_config *pads; + size_t num; + + memcfg_init(memupd, &ddr5_mem_config, &dimm_module_spd_info, false); + + pads = board_gpio_table(&num); + gpio_configure_pads(pads, num); + + // Set primary display to internal graphics + memupd->FspmConfig.PrimaryDisplay = 0; + memupd->FspmConfig.DmiMaxLinkSpeed = 4; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[0] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[1] = 0; + memupd->FspmConfig.CpuPcieRpClockReqMsgEnable[2] = 0; +} diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2430/gpio.c b/src/mainboard/protectli/vault_adl_n/variants/vp2430/gpio.c new file mode 100644 index 00000000000..b02b2c4a884 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp2430/gpio.c @@ -0,0 +1,802 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + /* ------- GPIO Group GPP_B ------- */ + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + + /* GPP_B3 - GPIO */ + PAD_NC(GPP_B3, NONE), + + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + + /* GPP_B8 - GPIO */ + PAD_NC(GPP_B8, NONE), + + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + + /* GPP_B15 - GPIO */ + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + /* GPP_B18 - GPIO */ + PAD_CFG_GPO(GPP_B18, 0, DEEP), + + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_A ------- */ + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + + /* GPP_A6 - GPIO */ + PAD_NC(GPP_A6, NONE), + + /* GPP_A7 - GPIO */ + PAD_NC(GPP_A7, NONE), + + /* GPP_A8 - GPIO */ + PAD_NC(GPP_A8, NONE), + + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + + /* GPP_A12 - GPIO */ + PAD_NC(GPP_A12, NONE), + + /* GPP_A13 - GPIO */ + PAD_NC(GPP_A13, NONE), + + /* GPP_A14 - USB_C_GPP_A14 */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF6), + + /* GPP_A15 - USB_C_GPP_A15 */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF6), + + /* GPP_A16 - USB_OC3# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + + /* GPP_A17 - GPIO */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + + /* GPP_A19 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + + /* GPP_A20 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + + /* GPP_A21 - USB_C_GPP_A21 */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + + /* GPP_A22 - USB_C_GPP_A22 */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + + /* GPP_A23 - ESPI_CS1# */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), + + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + /* ------- GPIO Group GPP_S ------- */ + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + /* GPP_I0 - GPIO */ + PAD_NC(GPP_I0, NONE), + + /* GPP_I1 - GPIO */ + PAD_NC(GPP_I1, NONE), + + /* GPP_I2 - GPIO */ + PAD_NC(GPP_I2, NONE), + + /* GPP_I3 - GPIO */ + PAD_NC(GPP_I3, NONE), + + /* GPP_I4 - GPIO */ + PAD_NC(GPP_I4, NONE), + + /* GPP_I5 - GPIO */ + PAD_NC(GPP_I5, NONE), + + /* GPP_I6 - GPIO */ + PAD_NC(GPP_I6, NONE), + + /* GPP_I7 - EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + + /* GPP_I8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + + /* GPP_I9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + + /* GPP_I10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + + /* GPP_I11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + + /* GPP_I12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + + /* GPP_I13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + + /* GPP_I14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + + /* GPP_I15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + + /* GPP_I16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + + /* GPP_I17 - EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + + /* GPP_I18 - EMMC_RESET# */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* GPP_I19 - GPIO */ + PAD_NC(GPP_I19, NONE), + + /* ------- GPIO Group GPP_H ------- */ + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), + + /* GPP_H1 - GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), + + /* GPP_H2 - GPIO */ + PAD_CFG_GPO(GPP_H2, 0, DEEP), + + /* GPP_H3 - GPIO */ + PAD_NC(GPP_H3, NONE), + + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + + /* GPP_H6 - GPIO */ + PAD_NC(GPP_H6, NONE), + + /* GPP_H7 - GPIO */ + PAD_NC(GPP_H7, NONE), + + /* GPP_H8 - I2C4_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + + /* GPP_H9 - I2C4_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + + /* GPP_H10 - GPIO */ + PAD_NC(GPP_H10, NONE), + + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11, NONE), + + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12, NONE), + + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13, NONE), + + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14, NONE), + + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + + /* GPP_H16 - GPIO */ + PAD_NC(GPP_H16, NONE), + + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + + /* GPP_H19 - SRCCLKREQ4# */ + PAD_NC(GPP_H19, NONE), + + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + /* GPP_D0 - GPIO */ + PAD_NC(GPP_D0, NONE), + + /* GPP_D1 - GPIO */ + PAD_NC(GPP_D1, NONE), + + /* GPP_D2 - GPIO */ + PAD_NC(GPP_D2, NONE), + + /* GPP_D3 - GPIO */ + PAD_NC(GPP_D3, NONE), + + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + + /* GPP_D5 - SRCCLKREQ0# */ + PAD_NC(GPP_D5, NONE), + + /* GPP_D6 - SRCCLKREQ1# */ + PAD_NC(GPP_D6, NONE), + + /* GPP_D7 - SRCCLKREQ2# */ + PAD_NC(GPP_D7, NONE), + + /* GPP_D8 - SRCCLKREQ3# */ + PAD_NC(GPP_D8, NONE), + + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D11, NONE), + + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NONE), + + /* GPP_D11 - GPIO */ + PAD_NC(GPP_D11, NONE), + + /* GPP_D12 - GPIO */ + PAD_NC(GPP_D12, NONE), + + /* GPP_D13 - GPIO */ + PAD_NC(GPP_D13, NONE), + + /* GPP_D14 - GPIO */ + PAD_NC(GPP_D14, NONE), + + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Group vGPIO ------- */ + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + /* ------- GPIO Group GPP_GPD ------- */ + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + + /* GPD7 - GPIO */ + PAD_CFG_GPO(GPD7, 0, PWROK), + + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + + /* GPD9 - GPIO */ + PAD_CFG_GPO(GPD9, 0, PWROK), + + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + + /* GPD11 - GPIO */ + PAD_CFG_GPO(GPD11, 0, PWROK), + + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + /* ------- GPIO Group GPP_C ------- */ + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + + /* GPP_C2 - GPIO */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), + + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + + /* GPP_C5 - GPIO */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + + /* GPP_C14 - GPIO */ + PAD_NC(GPP_C14, NONE), + + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + + /* GPP_C16 - GPIO */ + PAD_NC(GPP_C16, NONE), + + /* GPP_C17 - GPIO */ + PAD_NC(GPP_C17, NONE), + + /* GPP_C18 - GPIO */ + PAD_NC(GPP_C18, NONE), + + /* GPP_C19 - GPIO */ + PAD_NC(GPP_C19, NONE), + + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + + /* GPP_C22 - GPIO */ + PAD_NC(GPP_C22, NONE), + + /* GPP_C23 - GPIO */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + /* GPP_F0 - CNV_BRI_DT */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + + /* GPP_F1 - CNV_BRI_RSP */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + + /* GPP_F2 - CNV_RGI_DT */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + + /* GPP_F3 - CNV_RGI_RSP */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + + /* GPP_F4 - CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + + /* GPP_F5 - MODEM_CLKREQ */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + + /* GPP_F7 - GPIO */ + PAD_CFG_GPO(GPP_F7, 0, DEEP), + + /* GPP_F8 - GPIO */ + PAD_NC(GPP_F8, NONE), + + /* GPP_F9 - GPIO */ + PAD_NC(GPP_F9, NONE), + + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + + /* GPP_F11 - GPIO */ + PAD_NC(GPP_F11, NONE), + + /* GPP_F12 - GPIO */ + PAD_NC(GPP_F12, NONE), + + /* GPP_F13 - TYPE_C_PD_IRQ */ + PAD_CFG_GPI_APIC_LOW(GPP_F13, NONE, PLTRST), + + /* GPP_F14 - GPIO */ + PAD_NC(GPP_F14, NONE), + + /* GPP_F15 - GPIO */ + PAD_NC(GPP_F15, NONE), + + /* GPP_F16 - GPIO */ + PAD_NC(GPP_F16, NONE), + + /* GPP_F17 - GPIO */ + PAD_NC(GPP_F17, NONE), + + /* GPP_F18 - GPIO */ + PAD_NC(GPP_F18, NONE), + + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + + /* GPP_F20 - Reserved */ + PAD_NC(GPP_F20, NONE), + + /* GPP_F21 - Reserved */ + PAD_NC(GPP_F21, NONE), + + /* GPP_F22 - GPIO */ + PAD_NC(GPP_F22, NONE), + + /* GPP_F23 - GPIO */ + PAD_NC(GPP_F23, NONE), + + /* GPP_F_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + /* GPP_L_BKLTEN - n/a */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), + + /* GPP_L_BKLTCTL - n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), + + /* GPP_L_VDDEN - n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), + + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + + /* GPP_E1 - GPIO */ + PAD_NC(GPP_E1, NONE), + + /* GPP_E2 - GPIO */ + PAD_NC(GPP_E2, NONE), + + /* GPP_E3 - GPIO */ + PAD_NC(GPP_E3, NONE), + + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + + /* GPP_E5 - GPIO */ + PAD_NC(GPP_E5, NONE), + + /* GPP_E6 - GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), + + /* GPP_E7 - GPIO */ + PAD_NC(GPP_E7, NONE), + + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + + /* GPP_E13 - GPIO */ + PAD_CFG_GPI_APIC_LOW(GPP_E13, NONE, PLTRST), + + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + + /* GPP_E15 - GPIO */ + PAD_NC(GPP_E15, NONE), + + /* GPP_E16 - GPIO */ + PAD_NC(GPP_E16, NONE), + + /* GPP_E17 - GPIO */ + PAD_NC(GPP_E17, NONE), + + /* GPP_E18 - GPIO */ + PAD_NC(GPP_E18, NATIVE), + + /* GPP_E19 - GPIO */ + PAD_NC(GPP_E19, NATIVE), + + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NATIVE), + + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NATIVE), + + /* GPP_E22 - DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), + + /* GPP_E23 - DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + + /* ------- GPIO Community 5 ------- */ + /* ------- GPIO Group GPP_R ------- */ + /* GPP_R0 - GPIO */ + PAD_NC(GPP_R0, NONE), + + /* GPP_R1 - GPIO */ + PAD_NC(GPP_R1, NONE), + + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + + /* GPP_R3 - GPIO */ + PAD_NC(GPP_R3, NONE), + + /* GPP_R4 - GPIO */ + PAD_NC(GPP_R4, NONE), + + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE), +}; + +const struct pad_config *board_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb b/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb new file mode 100644 index 00000000000..c9ad4c96bbb --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp2430/overridetree.cb @@ -0,0 +1,66 @@ +chip soc/intel/alderlake + # FSP configuration + + device domain 0 on + device ref sata on + register "sata_ports_enable[0]" = "1" + end + + # LAN1 + device ref pcie_rp2 on + register "pch_pcie_rp[PCH_RP(2)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 0, + }" + end + # LAN2 + device ref pcie_rp3 on + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 1, + }" + end + # LAN 3 + device ref pcie_rp4 on + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 2, + }" + end + # LAN4 + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 3, + }" + end + # WIFI + device ref pcie_rp12 on + register "pch_pcie_rp[PCH_RP(12)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 4, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device pci 00.0 on end + end + end + # NVMe x2 link + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_CLK_REQ_UNUSED, + .clk_src = 0, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_NVME2X)" "SlotDataBusWidth2X" + end + + device ref cnvi_wifi on + register "cnvi_bt_core" = "true" + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + device generic 0 on end + end + end + end +end diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp32xx/gpio.c b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/gpio.c new file mode 100644 index 00000000000..f2b71091549 --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/gpio.c @@ -0,0 +1,454 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +#include + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +/* PAD configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* GPP_B1 - CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* GPP_B2 - VRALERT# */ + PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_NC(GPP_B3, NONE), + PAD_NC(GPP_B4, NONE), + PAD_NC(GPP_B5, NONE), + PAD_NC(GPP_B6, NONE), + PAD_NC(GPP_B7, NONE), + PAD_NC(GPP_B8, NONE), + PAD_NC(GPP_B9, NONE), + PAD_NC(GPP_B10, NONE), + /* GPP_B11 - PMCALERT# */ + PAD_CFG_NF(GPP_B11, NONE, RSMRST, NF1), + /* GPP_B12 - SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PLTRST# */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, PLTRST, NF1), + PAD_NC(GPP_B15, NONE), + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + /* GPP_B18 - GPIO */ + PAD_CFG_GPO(GPP_B18, 0, DEEP), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + /* GPP_B23 - GPIO */ + PAD_CFG_GPO(GPP_B23, 0, DEEP), + /* GPP_B24 - GSPI0_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B24, NONE, DEEP, NF1), + /* GPP_B25 - GSPI1_CLK_LOOPBK */ + PAD_CFG_NF(GPP_B25, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* GPP_A1 - ESPI_IO1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* GPP_A2 - ESPI_IO2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* GPP_A3 - ESPI_IO3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* GPP_A4 - ESPI_CS0# */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* GPP_A5 - ESPI_ALERT0# */ + PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), + PAD_NC(GPP_A6, NONE), + PAD_NC(GPP_A7, NONE), + PAD_NC(GPP_A8, NONE), + /* GPP_A9 - ESPI_CLK */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), + /* GPP_A10 - ESPI_RESET# */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_NC(GPP_A13, NONE), + /* GPP_A14 - USB_C_GPP_A14 */ + PAD_CFG_NF(GPP_A14, NONE, DEEP, NF6), + /* GPP_A15 - USB_C_GPP_A15 */ + PAD_CFG_NF(GPP_A15, NONE, DEEP, NF6), + /* GPP_A16 - USB_OC3# */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* GPP_A17 - GPIO */ + PAD_CFG_GPO(GPP_A17, 1, PLTRST), + /* GPP_A18 - DDSP_HPDB */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* GPP_A19 - DDSP_HPD1 */ + PAD_CFG_NF(GPP_A19, NONE, DEEP, NF1), + /* GPP_A20 - DDSP_HPD2 */ + PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1), + /* GPP_A21 - USB_C_GPP_A21 */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF6), + /* GPP_A22 - USB_C_GPP_A22 */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF6), + /* GPP_A23 - ESPI_CS1# */ + PAD_CFG_NF(GPP_A23, UP_20K, DEEP, NF1), + /* GPP_ESPI_CLK_LOOPBK - GPP_ESPI_CLK_LOOPBK */ + PAD_CFG_NF(GPP_ESPI_CLK_LOOPBK, NONE, DEEP, NF1), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_S ------- */ + + PAD_NC(GPP_S0, NONE), + PAD_NC(GPP_S1, NONE), + PAD_NC(GPP_S2, NONE), + PAD_NC(GPP_S3, NONE), + PAD_NC(GPP_S4, NONE), + PAD_NC(GPP_S5, NONE), + PAD_NC(GPP_S6, NONE), + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_I ------- */ + + PAD_NC(GPP_I0, NONE), + PAD_NC(GPP_I1, NONE), + PAD_NC(GPP_I2, NONE), + PAD_NC(GPP_I3, NONE), + PAD_NC(GPP_I4, NONE), + PAD_NC(GPP_I5, NONE), + PAD_NC(GPP_I6, NONE), + /* GPP_I7 - EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* GPP_I8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* GPP_I9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* GPP_I10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* GPP_I11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* GPP_I12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* GPP_I13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* GPP_I14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* GPP_I15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* GPP_I16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* GPP_I17 - EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* GPP_I18 - EMMC_RESET# */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + PAD_NC(GPP_I19, NONE), + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_CFG_GPO(GPP_H0, 0, DEEP), + /* GPP_H1 - GPIO */ + PAD_CFG_GPO(GPP_H1, 0, DEEP), + /* GPP_H2 - GPIO */ + PAD_CFG_GPO(GPP_H2, 0, DEEP), + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - I2C0_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* GPP_H5 - I2C0_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + PAD_NC(GPP_H6, NONE), + PAD_NC(GPP_H7, NONE), + /* GPP_H8 - I2C4_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 - I2C4_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + PAD_NC(GPP_H8, NONE), + PAD_NC(GPP_H9, NONE), + PAD_NC(GPP_H10, NONE), + PAD_NC(GPP_H11, NONE), + PAD_NC(GPP_H12, NONE), + PAD_NC(GPP_H13, NONE), + PAD_NC(GPP_H14, NONE), + /* GPP_H15 - DDPB_CTRLCLK */ + PAD_CFG_NF(GPP_H15, NONE, DEEP, NF1), + PAD_NC(GPP_H16, NONE), + /* GPP_H17 - DDPB_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* GPP_H18 - PROC_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* GPP_H19 - SRCCLKREQ4# */ + PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), + PAD_NC(GPP_H20, NONE), + PAD_NC(GPP_H21, NONE), + PAD_NC(GPP_H22, NONE), + PAD_NC(GPP_H23, NONE), + /* ------- GPIO Group GPP_D ------- */ + + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + /* GPP_D5 - SRCCLKREQ0# */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D6 - SRCCLKREQ1# */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), + /* GPP_D7 - SRCCLKREQ2# */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D8 - SRCCLKREQ3# */ + PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), + PAD_NC(GPP_D9, NONE), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, NONE), + PAD_NC(GPP_D12, NONE), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_NC(GPP_D17, NONE), + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + /* GPP_GSPI2_CLK_LOOPBK - GPP_GSPI2_CLK_LOOPBK */ + PAD_CFG_NF(GPP_GSPI2_CLK_LOOPBK, NONE, DEEP, NF1), + /* ------- GPIO Group vGPIO ------- */ + + /* GPP_VGPIO_0 - GPIO */ + PAD_CFG_GPO(GPP_VGPIO_0, 0, DEEP), + /* GPP_VGPIO_4 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPP_VGPIO_4, NONE, DEEP, OFF, ACPI), + /* GPP_VGPIO_5 - GPIO */ + PAD_CFG_GPIO_BIDIRECT(GPP_VGPIO_5, 1, NONE, DEEP, LEVEL, ACPI), + /* GPP_VGPIO_6 - GPP_VGPIO_6 */ + PAD_CFG_NF(GPP_VGPIO_6, NONE, DEEP, NF1), + /* GPP_VGPIO_7 - GPP_VGPIO_7 */ + PAD_CFG_NF(GPP_VGPIO_7, NONE, DEEP, NF1), + /* GPP_VGPIO_8 - GPP_VGPIO_8 */ + PAD_CFG_NF(GPP_VGPIO_8, NONE, DEEP, NF1), + /* GPP_VGPIO_9 - GPP_VGPIO_9 */ + PAD_CFG_NF(GPP_VGPIO_9, NONE, DEEP, NF1), + /* GPP_VGPIO_10 - GPP_VGPIO_10 */ + PAD_CFG_NF(GPP_VGPIO_10, NONE, DEEP, NF1), + /* GPP_VGPIO_11 - GPP_VGPIO_11 */ + PAD_CFG_NF(GPP_VGPIO_11, NONE, DEEP, NF1), + /* GPP_VGPIO_12 - GPP_VGPIO_12 */ + PAD_CFG_NF(GPP_VGPIO_12, NONE, DEEP, NF1), + /* GPP_VGPIO_13 - GPP_VGPIO_13 */ + PAD_CFG_NF(GPP_VGPIO_13, NONE, DEEP, NF1), + /* GPP_VGPIO_18 - GPP_VGPIO_18 */ + PAD_CFG_NF(GPP_VGPIO_18, NONE, DEEP, NF1), + /* GPP_VGPIO_19 - GPP_VGPIO_19 */ + PAD_CFG_NF(GPP_VGPIO_19, NONE, DEEP, NF1), + /* GPP_VGPIO_20 - GPP_VGPIO_20 */ + PAD_CFG_NF(GPP_VGPIO_20, NONE, DEEP, NF1), + /* GPP_VGPIO_21 - GPP_VGPIO_21 */ + PAD_CFG_NF(GPP_VGPIO_21, NONE, DEEP, NF1), + /* GPP_VGPIO_22 - GPP_VGPIO_22 */ + PAD_CFG_NF(GPP_VGPIO_22, NONE, DEEP, NF1), + /* GPP_VGPIO_23 - GPP_VGPIO_23 */ + PAD_CFG_NF(GPP_VGPIO_23, NONE, DEEP, NF1), + /* GPP_VGPIO_24 - GPP_VGPIO_24 */ + PAD_CFG_NF(GPP_VGPIO_24, NONE, DEEP, NF1), + /* GPP_VGPIO_25 - GPP_VGPIO_25 */ + PAD_CFG_NF(GPP_VGPIO_25, NONE, DEEP, NF1), + /* GPP_VGPIO_30 - GPP_VGPIO_30 */ + PAD_CFG_NF(GPP_VGPIO_30, NONE, DEEP, NF1), + /* GPP_VGPIO_31 - GPP_VGPIO_31 */ + PAD_CFG_NF(GPP_VGPIO_31, NONE, DEEP, NF1), + /* GPP_VGPIO_32 - GPP_VGPIO_32 */ + PAD_CFG_NF(GPP_VGPIO_32, NONE, DEEP, NF1), + /* GPP_VGPIO_33 - GPP_VGPIO_33 */ + PAD_CFG_NF(GPP_VGPIO_33, NONE, DEEP, NF1), + /* GPP_VGPIO_34 - GPP_VGPIO_34 */ + PAD_CFG_NF(GPP_VGPIO_34, NONE, DEEP, NF1), + /* GPP_VGPIO_35 - GPP_VGPIO_35 */ + PAD_CFG_NF(GPP_VGPIO_35, NONE, DEEP, NF1), + /* GPP_VGPIO_36 - GPP_VGPIO_36 */ + PAD_CFG_NF(GPP_VGPIO_36, NONE, DEEP, NF1), + /* GPP_VGPIO_37 - GPP_VGPIO_37 */ + PAD_CFG_NF(GPP_VGPIO_37, NONE, DEEP, NF1), + + /* ------- GPIO Community 2 ------- */ + + /* ------- GPIO Group GPP_GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), + /* GPD1 - ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), + /* GPD7 - GPIO */ + PAD_CFG_GPO(GPD7, 0, PWROK), + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), + /* GPD9 - GPIO */ + PAD_CFG_GPO(GPD9, 0, PWROK), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), + /* GPD11 - GPIO */ + PAD_CFG_GPO(GPD11, 0, PWROK), + /* GPD_INPUT3VSEL - GPD_INPUT3VSEL */ + PAD_CFG_NF(GPD_INPUT3VSEL, NONE, PWROK, NF1), + /* GPD_SLP_LANB - GPD_SLP_LANB */ + PAD_CFG_NF(GPD_SLP_LANB, NONE, PWROK, NF1), + /* GPD_SLP_SUSB - GPD_SLP_SUSB */ + PAD_CFG_NF(GPD_SLP_SUSB, NONE, PWROK, NF1), + /* GPD_WAKEB - GPD_WAKEB */ + PAD_CFG_NF(GPD_WAKEB, NONE, PWROK, NF1), + /* GPD_DRAM_RESETB - GPD_DRAM_RESETB */ + PAD_CFG_NF(GPD_DRAM_RESETB, NONE, PWROK, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - SMBCLK */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), + /* GPP_C1 - SMBDATA */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), + /* GPP_C2 - GPIO */ + PAD_CFG_GPO(GPP_C2, 0, DEEP), + /* GPP_C3 - SML0CLK */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), + /* GPP_C4 - SML0DATA */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), + /* GPP_C5 - GPIO */ + PAD_CFG_GPO(GPP_C5, 0, DEEP), + /* GPP_C6 - SML1CLK */ + PAD_CFG_NF(GPP_C6, NONE, RSMRST, NF1), + /* GPP_C7 - SML1DATA */ + PAD_CFG_NF(GPP_C7, NONE, RSMRST, NF1), + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_NC(GPP_C16, NONE), + PAD_NC(GPP_C17, NONE), + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_NC(GPP_C21, NONE), + PAD_NC(GPP_C22, NONE), + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Group GPP_F ------- */ + + PAD_NC(GPP_F0, NONE), + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), + PAD_NC(GPP_F5, NONE), + PAD_NC(GPP_F6, NONE), + PAD_CFG_GPO(GPP_F7, 0, DEEP), + PAD_NC(GPP_F8, NONE), + PAD_NC(GPP_F9, NONE), + /* GPP_F10 - GPIO */ + PAD_CFG_GPO(GPP_F10, 0, DEEP), + PAD_NC(GPP_F11, NONE), + PAD_NC(GPP_F12, NONE), + PAD_NC(GPP_F13, NONE), + PAD_NC(GPP_F14, NONE), + PAD_NC(GPP_F15, NONE), + /* GPP_F15 - GPIO (5G Power_On_Off)*/ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + PAD_NC(GPP_F16, NONE), + PAD_NC(GPP_F17, NONE), + PAD_NC(GPP_F18, NONE), + PAD_NC(GPP_F19, NONE), + /* GPP_F20 - Reserved */ + PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), + /* GPP_F21 - Reserved */ + PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), + PAD_NC(GPP_F22, NONE), + PAD_NC(GPP_F23, NONE), + /* GPP_F_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_F_CLK_LOOPBK, NONE), + + /* ------- GPIO Group GPP_HVCMOS ------- */ + + /* GPP_L_BKLTEN - n/a */ + PAD_CFG_NF(GPP_L_BKLTEN, NONE, DEEP, NF1), + /* GPP_L_BKLTCTL - n/a */ + PAD_CFG_NF(GPP_L_BKLTCTL, NONE, DEEP, NF1), + /* GPP_L_VDDEN - n/a */ + PAD_CFG_NF(GPP_L_VDDEN, NONE, DEEP, NF1), + /* GPP_SYS_PWROK - n/a */ + PAD_CFG_NF(GPP_SYS_PWROK, NONE, DEEP, NF1), + /* GPP_SYS_RESETB - n/a */ + PAD_CFG_NF(GPP_SYS_RESETB, NONE, DEEP, NF1), + /* GPP_MLK_RSTB - n/a */ + PAD_CFG_NF(GPP_MLK_RSTB, NONE, DEEP, NF1), + + /* ------- GPIO Group GPP_E ------- */ + + PAD_NC(GPP_E0, NONE), + PAD_NC(GPP_E1, NONE), + PAD_NC(GPP_E2, NONE), + PAD_NC(GPP_E3, NONE), + PAD_NC(GPP_E4, NONE), + PAD_NC(GPP_E5, NONE), + /* GPP_E6 - GPIO */ + PAD_CFG_GPO(GPP_E6, 0, DEEP), + PAD_NC(GPP_E7, NONE), + PAD_NC(GPP_E8, NONE), + PAD_NC(GPP_E9, NONE), + PAD_NC(GPP_E10, NONE), + PAD_NC(GPP_E11, NONE), + PAD_NC(GPP_E12, NONE), + /* GPP_E13 - GPIO */ + PAD_CFG_GPI_APIC_LOW(GPP_E13, NONE, PLTRST), + /* GPP_E14 - DDSP_HPDA */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_NC(GPP_E17, NONE), + PAD_NC(GPP_E18, NATIVE), + PAD_NC(GPP_E19, NATIVE), + PAD_NC(GPP_E20, NATIVE), + PAD_NC(GPP_E21, NATIVE), + /* GPP_E22 - DDPA_CTRLCLK */ + PAD_CFG_NF(GPP_E22, DN_20K, DEEP, NF1), + /* GPP_E23 - DDPA_CTRLDATA */ + PAD_CFG_NF(GPP_E23, NONE, DEEP, NF1), + /* GPP_E_CLK_LOOPBK - GPIO */ + PAD_NC(GPP_E_CLK_LOOPBK, NONE), + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_R ------- */ + + PAD_NC(GPP_R0, NONE), + PAD_NC(GPP_R1, NATIVE), + PAD_NC(GPP_R2, NATIVE), + PAD_NC(GPP_R3, NATIVE), + PAD_NC(GPP_R4, NONE), + PAD_NC(GPP_R5, NONE), + PAD_NC(GPP_R6, NONE), + PAD_NC(GPP_R7, NONE), +}; + +const struct pad_config *board_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(gpio_table); + return gpio_table; +} diff --git a/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb new file mode 100644 index 00000000000..fedbf0d31eb --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/variants/vp32xx/overridetree.cb @@ -0,0 +1,73 @@ +chip soc/intel/alderlake + # FSP configuration + + device domain 0 on + device ref i2c4 on # JNTP1 header + register "serial_io_i2c_mode[PchSerialIoIndexI2C4]" = "PchSerialIoPci" + end + + # NVMe x1 link or ASMedia SATA Controller + device ref pcie_rp1 on + register "pch_pcie_rp[PCH_RP(1)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 4, + .clk_req = 4, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_NVME1X)" "SlotDataBusWidth1X" + end + # LAN1 + device ref pcie_rp3 on + register "pch_pcie_rp[PCH_RP(3)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 2, + .clk_req = 2, + }" + end + # WIFI + device ref pcie_rp4 on + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 3, + .clk_req = 3, + }" + end + # LAN2 + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 1, + .clk_req = 1, + }" + end + + # NVMe x4 link + device ref pcie_rp9 on + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .clk_src = 0, + .clk_req = 0, + }" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (M2_NVME4X)" "SlotDataBusWidth4X" + end + + device ref pch_espi on + chip superio/ite/it8659e + # FAN2 is CPU fan (connector on board) + register "FAN2.mode" = "FAN_SMART_AUTOMATIC" + register "FAN2.smart.tmpin" = " 1" + register "FAN2.smart.tmp_off" = "40" + register "FAN2.smart.tmp_start" = "50" + register "FAN2.smart.tmp_full" = "85" + register "FAN2.smart.pwm_start" = "20" + register "FAN2.smart.slope" = "32" + register "FAN2.smart.tmp_delta" = "2" + + # Chip scope needs at least one device. + # Otherwise it doesn't compile. + device pnp 2e.a off end # CIR + end + end + end +end diff --git a/src/mainboard/protectli/vault_adl_n/vboot-rwa.fmd b/src/mainboard/protectli/vault_adl_n/vboot-rwa.fmd new file mode 100644 index 00000000000..4607a27c15d --- /dev/null +++ b/src/mainboard/protectli/vault_adl_n/vboot-rwa.fmd @@ -0,0 +1,37 @@ +FLASH@0xff000000 16M { + SI_ALL { + SI_DESC 4K + SI_ME + } + SI_BIOS@0x500000 0xb00000 { + SMMSTORE(PRESERVE) 256K + + RW_MISC 288K { + UNIFIED_MRC_CACHE(PRESERVE) { + RECOVERY_MRC_CACHE 128K + RW_MRC_CACHE 128K + } + RW_VPD(PRESERVE) 8K + RW_NVRAM(PRESERVE) 24K + } + + BOOTSPLASH(CBFS) 512K + + RW_SECTION_A { + VBLOCK_A 64K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + + WP_RO 5M { + RO_VPD(PRESERVE) 16K + RO_SECTION { + FMAP 2K + RO_FRID 0x100 + RO_FRID_PAD 0x700 + GBB 12K + COREBOOT(CBFS) + } + } + } +} diff --git a/src/mainboard/protectli/vault_adl_p/Kconfig b/src/mainboard/protectli/vault_adl_p/Kconfig index b7578ab91bf..aa8da560753 100644 --- a/src/mainboard/protectli/vault_adl_p/Kconfig +++ b/src/mainboard/protectli/vault_adl_p/Kconfig @@ -57,6 +57,8 @@ config VBOOT select VBOOT_NO_BOARD_SUPPORT select HAS_RECOVERY_MRC_CACHE select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE + select VBOOT_NO_TPM + select VBOOT_ENABLE_CBFS_FALLBACK config VBOOT_SLOTS_RW_A default y if VBOOT diff --git a/src/mainboard/protectli/vault_adl_p/bootblock.c b/src/mainboard/protectli/vault_adl_p/bootblock.c index becc634eb7b..dd0d5dd1eac 100644 --- a/src/mainboard/protectli/vault_adl_p/bootblock.c +++ b/src/mainboard/protectli/vault_adl_p/bootblock.c @@ -27,7 +27,7 @@ static void ite_set_gpio_iobase(u16 iobase) void bootblock_mainboard_early_init(void) { /* Internal VCC_OK */ - ite_reg_write(GPIO_DEV, 0x23, 0x40); + ite_reg_write(GPIO_DEV, 0x23, 0x00); /* Set pin native functions */ ite_reg_write(GPIO_DEV, 0x26, 0xc0); /* Pin28 as GP41 - PC speaker */ diff --git a/src/mainboard/protectli/vault_adl_p/devicetree.cb b/src/mainboard/protectli/vault_adl_p/devicetree.cb index 0089a5fb463..9905a222121 100644 --- a/src/mainboard/protectli/vault_adl_p/devicetree.cb +++ b/src/mainboard/protectli/vault_adl_p/devicetree.cb @@ -248,7 +248,7 @@ chip soc/intel/alderlake chip superio/ite/it8659e register "TMPIN1.mode" = "THERMAL_PECI" - register "TMPIN1.offset" = "0x56" + register "TMPIN1.offset" = "100" register "ec.vin_mask" = "VIN0 | VIN2 | VIN3 | VIN7" # FAN1 is CPU fan (connector on board) @@ -259,6 +259,8 @@ chip soc/intel/alderlake register "FAN1.smart.tmp_full" = "85" register "FAN1.smart.pwm_start" = "20" register "FAN1.smart.slope" = "32" + register "FAN1.smart.tmp_delta" = "2" + # FAN2 is CPU fan (connector on board) register "FAN2.mode" = "FAN_SMART_AUTOMATIC" register "FAN2.smart.tmpin" = " 1" @@ -267,6 +269,7 @@ chip soc/intel/alderlake register "FAN2.smart.tmp_full" = "85" register "FAN2.smart.pwm_start" = "20" register "FAN2.smart.slope" = "32" + register "FAN2.smart.tmp_delta" = "2" device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 @@ -282,8 +285,8 @@ chip soc/intel/alderlake io 0x60 = 0xa20 io 0x62 = 0xa10 irq 0x70 = 0 # Don't use IRQ - irq 0xf4 = 0x20 # PSON_N is inverted SUSB_N - irq 0xfa = 0x20 # Enable WDT output through PWRGD + irq 0xf4 = 0x60 # Use SB to control AC power loss + irq 0xfa = 0x02 # Enable 5VSB_CTRL# end device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # Mouse diff --git a/src/mainboard/protectli/vault_adl_p/mainboard.c b/src/mainboard/protectli/vault_adl_p/mainboard.c index eef2ff9a0ec..0c94a8b4f10 100644 --- a/src/mainboard/protectli/vault_adl_p/mainboard.c +++ b/src/mainboard/protectli/vault_adl_p/mainboard.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -11,6 +12,8 @@ #include #include #include +#include +#include #include "board_beep.h" @@ -93,6 +96,39 @@ static void mainboard_final(void *chip_info) do_beep(1500, 100); } +static void set_fan_curve(struct ite_ec_fan_config *fan, uint8_t fan_curve) +{ + switch (fan_curve) { + case FAN_CURVE_OPTION_OFF: + fan->mode = FAN_MODE_OFF; + break; + case FAN_CURVE_OPTION_PERFORMANCE: + fan->smart.pwm_start += 20; + fan->smart.tmp_full -= 10; + fan->smart.tmp_off -= 10; + fan->smart.tmp_start -= 10; + break; + case FAN_CURVE_OPTION_SILENT: + /* Do nothing, it is the default */ + default: + break; + } +} + +static void mainboard_enable(struct device *dev) +{ + struct superio_ite_it8659e_config *ite_cfg; + struct device *ite_ec = dev_find_slot_pnp(0x2e, IT8659E_EC); + uint8_t fan_curve = get_fan_curve_option(); + + if (ite_ec && ite_ec->chip_info) { + ite_cfg = (struct superio_ite_it8659e_config *)ite_ec->chip_info; + set_fan_curve(&ite_cfg->ec.fan[0], fan_curve); + set_fan_curve(&ite_cfg->ec.fan[1], fan_curve); + } +} + struct chip_operations mainboard_ops = { .final = mainboard_final, + .enable_dev = mainboard_enable }; diff --git a/src/mainboard/protectli/vault_cml/Kconfig b/src/mainboard/protectli/vault_cml/Kconfig index 87de08829a8..74adcec5438 100644 --- a/src/mainboard/protectli/vault_cml/Kconfig +++ b/src/mainboard/protectli/vault_cml/Kconfig @@ -10,7 +10,6 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select HAVE_CMOS_DEFAULT - select HAVE_INTEL_PTT select HAVE_OPTION_TABLE select INTEL_GMA_HAVE_VBT select MAINBOARD_HAS_LIBGFXINIT @@ -48,10 +47,21 @@ config VBOOT select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select VBOOT_ALWAYS_ENABLE_DISPLAY select VBOOT_NO_BOARD_SUPPORT + select VBOOT_SEPARATE_VERSTAGE + select VBOOT_NO_TPM + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE config VBOOT_SLOTS_RW_A default y if VBOOT +config VBOOT_VBNV_OFFSET + default 0x56 + +config PRERAM_CBMEM_CONSOLE_SIZE + default 0x1000 + config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" diff --git a/src/mainboard/protectli/vault_cml/Makefile.mk b/src/mainboard/protectli/vault_cml/Makefile.mk index d308320b42c..4ddb0bd6bdc 100644 --- a/src/mainboard/protectli/vault_cml/Makefile.mk +++ b/src/mainboard/protectli/vault_cml/Makefile.mk @@ -10,5 +10,8 @@ ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c ramstage-y += gpio.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads -all-y += die.c + +bootblock-y += die.c +romstage-y += die.c +ramstage-y += die.c smm-y += die.c diff --git a/src/mainboard/protectli/vault_cml/cmos.layout b/src/mainboard/protectli/vault_cml/cmos.layout index b2f8e319c82..390fee855df 100644 --- a/src/mainboard/protectli/vault_cml/cmos.layout +++ b/src/mainboard/protectli/vault_cml/cmos.layout @@ -10,6 +10,10 @@ entries 395 3 e 3 debug_level 398 1 e 4 me_state 400 4 h 0 me_state_counter + +# Vboot non-volatile data +800 128 r 0 vbnv + 984 16 h 0 check_sum @@ -37,4 +41,4 @@ enumerations checksums -checksum 392 983 984 +checksum 392 799 984 diff --git a/src/mainboard/protectli/vault_cml/devicetree.cb b/src/mainboard/protectli/vault_cml/devicetree.cb index 01c5df7724d..75c0c68cd67 100644 --- a/src/mainboard/protectli/vault_cml/devicetree.cb +++ b/src/mainboard/protectli/vault_cml/devicetree.cb @@ -2,7 +2,7 @@ chip soc/intel/cannonlake # Enable Enhanced Intel SpeedStep register "eist_enable" = "true" - register "cpu_pl2_4_cfg" = "baseline" + register "cpu_pl2_4_cfg" = "performance" register "gen1_dec" = "0x00fc0201" register "gen2_dec" = "0x007c0a01" @@ -49,6 +49,7 @@ chip soc/intel/cannonlake register "enable_c6dram" = "1" + register "SataMode" = "0" register "SataPortsEnable[0]" = "1" register "SataPortsEnable[2]" = "1" @@ -60,6 +61,9 @@ chip soc/intel/cannonlake register "PcieRpEnable[9]" = "1" # LAN6 register "PcieRpEnable[11]" = "1" # M.2 WiFi register "PcieRpEnable[12]" = "1" # M.2 NVMe x4 + register "PcieRpEnable[13]" = "1" + register "PcieRpEnable[14]" = "1" + register "PcieRpEnable[15]" = "1" # Enable Advanced Error Reporting for RP 5-10, 12, 13 register "PcieRpAdvancedErrorReporting[4]" = "1" @@ -70,6 +74,9 @@ chip soc/intel/cannonlake register "PcieRpAdvancedErrorReporting[9]" = "1" register "PcieRpAdvancedErrorReporting[11]" = "1" register "PcieRpAdvancedErrorReporting[12]" = "1" + register "PcieRpAdvancedErrorReporting[13]" = "1" + register "PcieRpAdvancedErrorReporting[14]" = "1" + register "PcieRpAdvancedErrorReporting[15]" = "1" # Enable Latency Tolerance Reporting Mechanism RP 5-10, 12, 13 register "PcieRpLtrEnable[4]" = "1" @@ -80,6 +87,9 @@ chip soc/intel/cannonlake register "PcieRpLtrEnable[9]" = "1" register "PcieRpLtrEnable[11]" = "1" register "PcieRpLtrEnable[12]" = "1" + register "PcieRpLtrEnable[13]" = "1" + register "PcieRpLtrEnable[14]" = "1" + register "PcieRpLtrEnable[15]" = "1" register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" @@ -140,7 +150,11 @@ chip soc/intel/cannonlake }" device domain 0 on - device ref igpu on end + subsystemid 0x8086 0x7270 inherit + device ref system_agent on end + device ref igpu on + subsystemid 0x8086 0x2212 + end device ref dptf on end device ref thermal on end device ref xhci on end @@ -159,6 +173,9 @@ chip soc/intel/cannonlake smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280 (J1)" "SlotDataBusWidth4X" end + device ref pcie_rp14 on end + device ref pcie_rp15 on end + device ref pcie_rp16 on end device ref lpc_espi on chip superio/ite/it8784e register "TMPIN1.mode" = "THERMAL_RESISTOR" @@ -177,13 +194,13 @@ chip soc/intel/cannonlake register "FAN1.smart.tmp_delta" = " 2" register "FAN1.smart.pwm_start" = "20" register "FAN1.smart.slope" = "24" - register "FAN2.mode" = "FAN_MODE_OFF" - register "FAN3.mode" = "FAN_MODE_OFF" + register "FAN2.mode" = "FAN_MODE_OFF" + register "FAN3.mode" = "FAN_MODE_OFF" device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 irq 0x70 = 4 end - device pnp 2e.2 on end # COM 2 + device pnp 2e.2 off end # COM 2 device pnp 2e.3 off end # Printer Port device pnp 2e.4 on # Environment Controller io 0x60 = 0xa40 diff --git a/src/mainboard/protectli/vault_cml/die.c b/src/mainboard/protectli/vault_cml/die.c index 34fa75b1a3a..7a8f0bd5b16 100644 --- a/src/mainboard/protectli/vault_cml/die.c +++ b/src/mainboard/protectli/vault_cml/die.c @@ -8,7 +8,7 @@ static void beep_and_blink(void) { static uint8_t blink = 0; - static uint8_t beep_count = 0; + static uint8_t beep_count = 0;; gpio_set(GPP_E8, blink); /* Beep 12 times at most, constant beeps may be annoying */ diff --git a/src/mainboard/protectli/vault_cml/mainboard.c b/src/mainboard/protectli/vault_cml/mainboard.c index 1e06fc5feee..5bcc921533c 100644 --- a/src/mainboard/protectli/vault_cml/mainboard.c +++ b/src/mainboard/protectli/vault_cml/mainboard.c @@ -1,41 +1,51 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include -#include +#include +#include #include -#include -#include +#include +#include +#include #include -#include +#include +#include #include -#include +#include #include +#include +#include #include -static bool need_global_reset = false; - -/* Flash Master 1 : HOST/BIOS */ -#define FLMSTR1 0x80 - -#define FLASH_SIGNATURE_OFFSET 0x10 -#define FLMSTR_WR_SHIFT_V2 20 -#define FLASH_SIGNATURE_VAL 0x0FF0A55A - -#define SI_DESC_SIZE (4 * KiB) -#define SI_DESC_REGION "SI_DESC" +#include "gpio.h" const char *smbios_mainboard_product_name(void) { - char processor_name[49]; - - fill_processor_name(processor_name); + u32 tmp[13]; + const char *str = "Unknown Processor Name"; + + if (cpu_have_cpuid()) { + int i; + struct cpuid_result res = cpuid(0x80000000); + if (res.eax >= 0x80000004) { + int j = 0; + for (i = 0; i < 3; i++) { + res = cpuid(0x80000002 + i); + tmp[j++] = res.eax; + tmp[j++] = res.ebx; + tmp[j++] = res.ecx; + tmp[j++] = res.edx; + } + tmp[12] = 0; + str = (const char *)tmp; + } + } - if (strstr(processor_name, "i3-10110U") != NULL) + if (strstr(str, "i3-10110U") != NULL) return "VP4630"; - else if (strstr(processor_name, "i5-10210U") != NULL) + else if (strstr(str, "i5-10210U") != NULL) return "VP4650"; - else if (strstr(processor_name, "i7-10810U") != NULL) + else if (strstr(str, "i7-10810U") != NULL) return "VP4670"; else return CONFIG_MAINBOARD_SMBIOS_PRODUCT_NAME; @@ -43,85 +53,49 @@ const char *smbios_mainboard_product_name(void) static void mainboard_final(void *unused) { + if (CONFIG(BEEP_ON_BOOT)) beep(1500, 100); } -/* It checks whether host (Flash Master 1) has write access to the Descriptor Region or not */ -static bool is_descriptor_writeable(uint8_t *desc) -{ - /* Check flash has valid signature */ - if (read32((void *)(desc + FLASH_SIGNATURE_OFFSET)) != FLASH_SIGNATURE_VAL) { - printk(BIOS_ERR, "Flash Descriptor is not valid\n"); - printk(BIOS_ERR, "Descriptor needs to be fixed to ensure proper operation\n"); - return false; - } - - /* Check host has write access to the Descriptor Region */ - if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { - printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); - return false; - } - - return true; -} +struct chip_operations mainboard_ops = { + .final = mainboard_final, +}; -static void configure_descriptor_for_lpc_tpm(void) +void mainboard_silicon_init_params(FSPS_UPD *supd) { - uint8_t si_desc_buf[SI_DESC_SIZE]; - struct region_device desc_rdev; - - if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { - printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); - return; + struct soc_power_limits_config *soc_conf; + config_t *conf = config_of_soc(); + uint16_t sa_devid = pci_read_config16(pcidev_on_root(0, 0), PCI_DEVICE_ID); + + soc_conf = &conf->power_limits_config; + + if (sa_devid == PCI_DID_INTEL_CML_ULT_2_2) { /* VP4630 */ + soc_conf->tdp_pl2_override = 35; + soc_conf->tdp_pl4 = 51; + soc_conf->psys_pmax = 60; + } else if (sa_devid == PCI_DID_INTEL_CML_ULT) { /* VP4650 */ + soc_conf->tdp_pl2_override = 64; + soc_conf->tdp_pl4 = 90; + soc_conf->psys_pmax = 100; + } else if (sa_devid == PCI_DID_INTEL_CML_ULT_6_2) { /* VP4670 */ + soc_conf->tdp_pl1_override = 25; + soc_conf->tdp_pl2_override = 85; + soc_conf->tdp_pl4 = 90; + soc_conf->psys_pmax = 100; } - if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { - printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); - return; - } - - if (!is_descriptor_writeable(si_desc_buf)) - return; - - /* Disable SPI TPM if necessary */ - if ((si_desc_buf[0x1f0] & 0xfe) == si_desc_buf[0x1f0]) { - printk(BIOS_DEBUG, "Update of Descriptor is not required!\n"); - return; - } - - si_desc_buf[0x1f0] &= 0xfe; - - if (rdev_eraseat(&desc_rdev, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { - printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); - return; - } - - if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { - printk(BIOS_ERR, "Failed to update Descriptor Region\n"); - return; - } - - printk(BIOS_DEBUG, "Update of Descriptor successful\n"); - need_global_reset = true; + supd->FspsTestConfig.PkgCStateLimit = 0; + supd->FspsTestConfig.PkgCStateDemotion = 0; + supd->FspsTestConfig.PkgCStateUnDemotion = 0; + supd->FspsTestConfig.C1StateAutoDemotion = 0; + supd->FspsTestConfig.C1StateUnDemotion = 0; + supd->FspsTestConfig.C3StateAutoDemotion = 0; + supd->FspsTestConfig.C3StateUnDemotion = 0; + supd->FspsTestConfig.PowerLimit3Lock = 0; + supd->FspsTestConfig.PowerLimit3 = 0; + supd->FspsTestConfig.PowerLimit3Time = 0; + supd->FspsTestConfig.PowerLimit3DutyCycle = 0; + + supd->FspsConfig.TxtEnable = CONFIG(INTEL_TXT); } - -void mainboard_silicon_init_params(FSPS_UPD *supd) -{ - /* Call it right before Silicon Init, so that we avoid EOP */ - configure_descriptor_for_lpc_tpm(); - cse_enable_ptt(false); - /* - * We wait with global reset after descriptor update until PTT state change to avoid - * double global reset. In case PTT was already disabled or cse_enable_ptt will fail - * for some reason, but descriptor has been updated we need to do global reset here, - * otherwise cse_enable_ptt will do the global reset and the branch below won't be - * reached. - */ - if (need_global_reset) - do_global_reset(); -} - -struct chip_operations mainboard_ops = { - .final = mainboard_final, -}; diff --git a/src/mainboard/protectli/vault_cml/romstage.c b/src/mainboard/protectli/vault_cml/romstage.c index 453566234a8..34a0bd6476c 100644 --- a/src/mainboard/protectli/vault_cml/romstage.c +++ b/src/mainboard/protectli/vault_cml/romstage.c @@ -1,7 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include +#include #include #include +#include static const struct cnl_mb_cfg board_memcfg_cfg = { /* Access memory info through SMBUS. */ @@ -41,4 +45,24 @@ static const struct cnl_mb_cfg board_memcfg_cfg = { void mainboard_memory_init_params(FSPM_UPD *memupd) { cannonlake_memcfg_init(&memupd->FspmConfig, &board_memcfg_cfg); + +/* Use pre-processor because CONFIG_INTEL_TXT_CBFS_BIOS_ACM is not defined otherwise */ +#if CONFIG(INTEL_TXT) + size_t acm_size = 0; + uintptr_t acm_base; + + intel_txt_log_bios_acm_error(); + + acm_base = (uintptr_t)cbfs_map(CONFIG_INTEL_TXT_CBFS_BIOS_ACM, &acm_size); + + memupd->FspmConfig.TxtImplemented = 1; + memupd->FspmConfig.Txt = 1; + memupd->FspmConfig.SinitMemorySize = CONFIG_INTEL_TXT_SINIT_SIZE; + memupd->FspmConfig.TxtHeapMemorySize = CONFIG_INTEL_TXT_HEAP_SIZE; + memupd->FspmConfig.TxtDprMemorySize = CONFIG_INTEL_TXT_DPR_SIZE << 20; + memupd->FspmConfig.TxtDprMemoryBase = 1; // Set to non-zero, FSP will update it + memupd->FspmConfig.BiosAcmBase = acm_base; + memupd->FspmConfig.BiosAcmSize = acm_size; + memupd->FspmConfig.ApStartupBase = 1; // Set to non-zero, FSP does NULL check +#endif } diff --git a/src/mainboard/protectli/vault_cml/vboot-rwa.fmd b/src/mainboard/protectli/vault_cml/vboot-rwa.fmd index b5c233f3832..8ae286e5d07 100644 --- a/src/mainboard/protectli/vault_cml/vboot-rwa.fmd +++ b/src/mainboard/protectli/vault_cml/vboot-rwa.fmd @@ -17,24 +17,22 @@ FLASH@0xff000000 0x1000000 { RW_NVRAM(PRESERVE) 24K } - CONSOLE 0x20000 + BOOTSPLASH(CBFS) 512K RW_SECTION_A { VBLOCK_A 0x2000 FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + RW_FWID_A 0x100 } - # T/B = 0 - # BP3 = 0 BP2 = 1 BP1 = 1 BP0 = 1 - WP_RO@0xC00000 0x400000 { + WP_RO 0x480000 { RO_VPD(PRESERVE)@0x0 0x4000 - RO_SECTION@0x4000 0x3fc000 { + RO_SECTION@0x4000 { FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + RO_FRID@0x800 0x100 + RO_FRID_PAD@0x900 0x700 GBB@0x1000 0x3000 - COREBOOT(CBFS)@0x4000 0x3f8000 + COREBOOT(CBFS)@0x4000 } } } diff --git a/src/mainboard/protectli/vault_ehl/Kconfig b/src/mainboard/protectli/vault_ehl/Kconfig index 5f283eed32d..e5b0f669444 100644 --- a/src/mainboard/protectli/vault_ehl/Kconfig +++ b/src/mainboard/protectli/vault_ehl/Kconfig @@ -32,6 +32,9 @@ config CBFS_SIZE config DIMM_MAX default 1 +config DIMM_SPD_SIZE + default 512 + config VBOOT select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC select GBB_FLAG_DISABLE_FWMP @@ -39,9 +42,12 @@ config VBOOT select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC select VBOOT_ALWAYS_ENABLE_DISPLAY select VBOOT_NO_BOARD_SUPPORT + select VBOOT_NO_TPM select VBOOT_VBNV_CMOS select VBOOT_VBNV_CMOS_BACKUP_TO_FLASH - select VBOOT_SEPARATE_VERSTAGE + select HAS_RECOVERY_MRC_CACHE + select VBOOT_ENABLE_CBFS_FALLBACK + select VBOOT_CLEAR_RECOVERY_IN_RAMSTAGE config VBOOT_SLOTS_RW_A default y if VBOOT @@ -49,4 +55,11 @@ config VBOOT_SLOTS_RW_A config FMDFILE default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rwa.fmd" if VBOOT && VBOOT_SLOTS_RW_A +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 5 + +endif + endif # BOARD_PROTECTLI_VP2420 diff --git a/src/mainboard/protectli/vault_ehl/acpi/superio.asl b/src/mainboard/protectli/vault_ehl/acpi/superio.asl new file mode 100644 index 00000000000..7127793fe44 --- /dev/null +++ b/src/mainboard/protectli/vault_ehl/acpi/superio.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8613E_SHOW_UARTA +#undef IT8613E_SHOW_KBC +#undef IT8613E_SHOW_PS2M +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8613E_SHOW_UARTA 1 + +#include diff --git a/src/mainboard/protectli/vault_ehl/bootblock.c b/src/mainboard/protectli/vault_ehl/bootblock.c index 11bd669f0b6..e45fb8bfa03 100644 --- a/src/mainboard/protectli/vault_ehl/bootblock.c +++ b/src/mainboard/protectli/vault_ehl/bootblock.c @@ -11,7 +11,10 @@ void bootblock_mainboard_early_init(void) { ite_reg_write(GPIO_DEV, 0x29, 0xc1); + ite_reg_write(GPIO_DEV, 0x2a, 0x00); /* Disable FAN_CTL4 */ ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK=25MHz */ + ite_kill_watchdog(GPIO_DEV); ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/protectli/vault_ehl/devicetree.cb b/src/mainboard/protectli/vault_ehl/devicetree.cb index 10782b265d1..e71a9d72e7b 100644 --- a/src/mainboard/protectli/vault_ehl/devicetree.cb +++ b/src/mainboard/protectli/vault_ehl/devicetree.cb @@ -1,3 +1,4 @@ + chip soc/intel/elkhartlake #register "enable_vtd" = "1" @@ -82,7 +83,7 @@ chip soc/intel/elkhartlake register "DdiPortADdc" = "1" register "DdiPortBDdc" = "1" - device cpu_cluster 0 on end + device cpu_cluster 0 on end device domain 0 on device pci 00.0 on end # Host Bridge device pci 02.0 on end # Integrated Graphics Device @@ -182,13 +183,24 @@ chip soc/intel/elkhartlake device pci 1e.7 off end # IOAPIC device pci 1f.0 on # eSPI interface + # LPC generic I/O ranges + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x003c0a01" + register "gen3_dec" = "0x000c0081" + chip superio/ite/it8613e - device pnp 2e.0 off end - device pnp 2e.1 on # COM 1 + device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 irq 0x70 = 4 + irq 0xf0 = 1 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa20 + io 0x62 = 0xa10 + irq 0x70 = 0 # Don't use IRQ + irq 0xf0 = 0x80 # Clear 3VSB off status + irq 0xf4 = 0x60 # Use SB to control AC power loss end - device pnp 2e.4 off end # Environment Controller device pnp 2e.5 off end # Keyboard device pnp 2e.6 off end # Mouse device pnp 2e.7 off end # GPIO diff --git a/src/mainboard/protectli/vault_ehl/die.c b/src/mainboard/protectli/vault_ehl/die.c index 00366dcad96..4d38a280eb2 100644 --- a/src/mainboard/protectli/vault_ehl/die.c +++ b/src/mainboard/protectli/vault_ehl/die.c @@ -2,6 +2,7 @@ #include #include +#include #include #include diff --git a/src/mainboard/protectli/vault_ehl/dsdt.asl b/src/mainboard/protectli/vault_ehl/dsdt.asl index b60f57b2380..f0603388229 100644 --- a/src/mainboard/protectli/vault_ehl/dsdt.asl +++ b/src/mainboard/protectli/vault_ehl/dsdt.asl @@ -24,5 +24,9 @@ DefinitionBlock( } } + Scope (\_SB.PCI0.LPCB) { + #include "acpi/superio.asl" + } + #include } diff --git a/src/mainboard/protectli/vault_ehl/mainboard.c b/src/mainboard/protectli/vault_ehl/mainboard.c index 388a4e40fc8..9163984edf2 100644 --- a/src/mainboard/protectli/vault_ehl/mainboard.c +++ b/src/mainboard/protectli/vault_ehl/mainboard.c @@ -10,9 +10,16 @@ static void mainboard_final(void *chip_info) beep(1500, 200); } - void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) { + /* + * HWP is too aggressive in power savings and does not let using full + * bandwidth of Ethernet controllers without additional stressing of + * the CPUs (2Gb/s vs 2.35Gb/s with stressing, measured with iperf3). + * Let the Linux use acpi-cpufreq governor driver instead of + * intel_pstate by disabling HWP. + */ + silconfig->Hwp = 0; } struct chip_operations mainboard_ops = { diff --git a/src/mainboard/protectli/vault_ehl/romstage.c b/src/mainboard/protectli/vault_ehl/romstage.c index 7bd1aaffe23..d4e5d04a20e 100644 --- a/src/mainboard/protectli/vault_ehl/romstage.c +++ b/src/mainboard/protectli/vault_ehl/romstage.c @@ -28,7 +28,6 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); get_spd_smbus(&blk); - dump_spd_info(&blk); if (blk.spd_array[0] == NULL) die("No memory detected. Insert DIMM module"); diff --git a/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd b/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd index 3d5a61c62ab..f1f7679a4ac 100644 --- a/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd +++ b/src/mainboard/protectli/vault_ehl/vboot-rwa.fmd @@ -19,18 +19,20 @@ FLASH 16M { CONSOLE 0x20000 + BOOTSPLASH(CBFS) 1M + RW_SECTION_A { VBLOCK_A 0x2000 FW_MAIN_A(CBFS) - RW_FWID_A 0x40 + RW_FWID_A 0x100 } WP_RO@0xC00000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 - RO_FRID@0x800 0x40 - RO_FRID_PAD@0x840 0x7c0 + RO_FRID@0x800 0x100 + RO_FRID_PAD@0x900 0x700 GBB@0x1000 0x3000 COREBOOT(CBFS)@0x4000 0x3f8000 } diff --git a/src/mainboard/protectli/vault_glk/Kconfig b/src/mainboard/protectli/vault_glk/Kconfig new file mode 100644 index 00000000000..fb37ae42666 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/Kconfig @@ -0,0 +1,68 @@ +## SPDX-License-Identifier: GPL-2.0-only + +if BOARD_PROTECTLI_VP2410 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_GEMINILAKE + select BOARD_ROMSIZE_KB_8192 + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select MEMORY_MAPPED_TPM + select SUPERIO_ITE_IT8613E + select SPI_FLASH_MACRONIX + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SEABIOS_ADD_SERCON_PORT_FILE if PAYLOAD_SEABIOS + select NEED_IFWI + +config MAINBOARD_DIR + string + default "protectli/vault_glk" + +config DEVICETREE + string + default "devicetree.cb" + +config MAINBOARD_PART_NUMBER + string + default "VP2410" + +config MAINBOARD_FAMILY + default "Vault Pro" + +config DIMM_MAX + default 1 + +config DIMM_SPD_SIZE + default 512 + +config MAX_CPUS + default 4 + +config SOC_INTEL_COMMON_BLOCK_SGX_ENABLE + default y + +config USE_LEGACY_8254_TIMER + default y + +config FMDFILE + string + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" if !VBOOT + +config BEEP_ON_BOOT + bool "Beep on successful boot" + default y + help + Make the platform beep using the PC speaker in final coreboot phase. + May serve as a useful indicator in headless mode that platform is + properly booting. + +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 5 + +endif + +endif # BOARD_PROTECTLI_VP2410 diff --git a/src/mainboard/protectli/vault_glk/Kconfig.name b/src/mainboard/protectli/vault_glk/Kconfig.name new file mode 100644 index 00000000000..f246bcb4dfd --- /dev/null +++ b/src/mainboard/protectli/vault_glk/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-only + +config BOARD_PROTECTLI_VP2410 + bool "VP2410" diff --git a/src/mainboard/protectli/vault_glk/Makefile.mk b/src/mainboard/protectli/vault_glk/Makefile.mk new file mode 100644 index 00000000000..9680cbeeef2 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/Makefile.mk @@ -0,0 +1,12 @@ +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c + +bootblock-y += die.c +romstage-y += die.c +ramstage-y += die.c +smm-y += die.c diff --git a/src/mainboard/protectli/vault_glk/acpi/superio.asl b/src/mainboard/protectli/vault_glk/acpi/superio.asl new file mode 100644 index 00000000000..7127793fe44 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/acpi/superio.asl @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#undef IT8613E_SHOW_UARTA +#undef IT8613E_SHOW_KBC +#undef IT8613E_SHOW_PS2M +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x2e +#define IT8613E_SHOW_UARTA 1 + +#include diff --git a/src/mainboard/protectli/vault_glk/board.fmd b/src/mainboard/protectli/vault_glk/board.fmd new file mode 100644 index 00000000000..b7d4c8328af --- /dev/null +++ b/src/mainboard/protectli/vault_glk/board.fmd @@ -0,0 +1,24 @@ +FLASH 8M { + SI_DESC@0x0 0x1000 + SI_BIOS@0x1000 0x6fe000 { + IFWI@0x0 0x2ff000 + OBB@0x2ff000 0x3ff000 { + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + BOOTSPLASH(CBFS) 0x80000 + WP_RO { + FMAP 0x1000 + COREBOOT(CBFS) + } + SMMSTORE(PRESERVE) 0x40000 + BIOS_UNUSABLE 0x40000 + } + } + SI_DEVICEEXT@0x6ff000 0x101000 { + DEVICE_EXTENSION@0x0 0x100000 + UNUSED_HOLE@0x100000 0x1000 + } +} diff --git a/src/mainboard/protectli/vault_glk/board_info.txt b/src/mainboard/protectli/vault_glk/board_info.txt new file mode 100644 index 00000000000..c06641a55e3 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Protectli +Board name: VP2410 +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault_glk/bootblock.c b/src/mainboard/protectli/vault_glk/bootblock.c new file mode 100644 index 00000000000..f90ed342e04 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/bootblock.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + + +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) +#define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) + +void bootblock_mainboard_early_init(void) +{ + ite_reg_write(GPIO_DEV, 0x25, 0x05); /* PCIRST1# and PCIRST3# as GPIO */ + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */ + ite_reg_write(GPIO_DEV, 0x2d, 0x02); /* PCICLK 25MHz */ + + ite_reg_write(GPIO_DEV, 0xc0, 0x05); /* PCIRST3# and 5VSB_CTRL GPIO Simple I/O */ + ite_reg_write(GPIO_DEV, 0xc1, 0x02); /* GP22 GPIO Simple I/O */ + ite_reg_write(GPIO_DEV, 0xc9, 0x02); /* GP22 GPIO output */ + + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); +} diff --git a/src/mainboard/protectli/vault_glk/data.vbt b/src/mainboard/protectli/vault_glk/data.vbt new file mode 100644 index 00000000000..e9aaa197bcf Binary files /dev/null and b/src/mainboard/protectli/vault_glk/data.vbt differ diff --git a/src/mainboard/protectli/vault_glk/devicetree.cb b/src/mainboard/protectli/vault_glk/devicetree.cb new file mode 100644 index 00000000000..2869a88e0f9 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/devicetree.cb @@ -0,0 +1,181 @@ +chip soc/intel/apollolake + # Assign first CLKREQ numbers to the used ports, rest don't care. + # FSP sets the CLKREQ despite passing PcieRpClkReqSupported as disabled + # So we must use the only 4 CLKREQ pins we have for the used ports + register "pcie_rp_clkreq_pin[0]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[1]" = "CLKREQ_DISABLED" + register "pcie_rp_clkreq_pin[2]" = "0" + register "pcie_rp_clkreq_pin[3]" = "1" + register "pcie_rp_clkreq_pin[4]" = "2" + register "pcie_rp_clkreq_pin[5]" = "3" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_PRT0_UDEF" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C3A" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28272929" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x003B263B" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + register "emmc_rx_strobe_cntl" = "0x0a0a" + register "emmc_tx_cmd_cntl" = "0x1305" + + register "enable_vtd" = "1" + + register "power_limits_config" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 15, + }" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_SCC_63_32" + register "gpe0_dw2" = "PMC_GPE_N_31_0" + register "gpe0_dw3" = "PMC_GPE_SCC_31_0" + + register "gen1_dec" = "0x00fc0201" + register "gen2_dec" = "0x007c0a01" + register "gen3_dec" = "0x000c03e1" + register "gen4_dec" = "0x001c02e1" + + register "pnp_settings" = "PNP_PERF_POWER" + register "tcc_offset" = "5" # TCC of 95C + register "serirq_mode" = "SERIRQ_CONTINUOUS" + + # USB configuration + register "usb_config_override" = "1" + register "disable_compliance_mode" = "1" + register "disable_xhci_lfps_pm" = "0" + register "mod_phy_if_value" = "0x16" + + register "usb2_port[0]" = "PORT_EN(OC_SKIP)" # USB3.0 Type A + register "usb2_port[1]" = "PORT_EN(OC_SKIP)" # USB3.0 Type A + register "usb2_port[2]" = "PORT_EN(OC_SKIP)" # USB3.0 Type C + register "usb2_port[3]" = "PORT_EN(OC_SKIP)" # M.2 WiFi + register "usb2_port[4]" = "PORT_EN(OC_SKIP)" # mPCIe LTE + register "usb2_port[5]" = "PORT_DIS" + register "usb2_port[6]" = "PORT_DIS" + register "usb2_port[7]" = "PORT_DIS" + + register "usb3_port[0]" = "PORT_EN(OC_SKIP)" # USB3.0 Type A + register "usb3_port[1]" = "PORT_EN(OC_SKIP)" # USB3.0 Type A + register "usb3_port[2]" = "PORT_EN(OC_SKIP)" # USB3.0 Type C + register "usb3_port[3]" = "PORT_DIS" + register "usb3_port[4]" = "PORT_DIS" + register "usb3_port[5]" = "PORT_DIS" + + register "sata_ports_enable[0]" = "1" + register "sata_ports_enable[1]" = "1" + register "sata_ports_ssd[0]" = "1" + + device cpu_cluster 0 on end + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 off end # - DPTF + device pci 00.2 off end # - NPK + device pci 02.0 on end # - Gen + device pci 0c.0 off end # - CNVi + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on end # - Audio + device pci 0f.0 on end # - Heci1 + device pci 0f.1 off end # - Heci2 + device pci 0f.2 off end # - Heci3 + device pci 11.0 off end # - ISH + device pci 12.0 on end # - SATA + device pci 13.0 on end # - PCIe-A 0 LAN1 + device pci 13.1 on end # - PCIe-A 1 LAN2 + device pci 13.2 on end # - PCIe-A 2 ASMedia Switch: LAN3/WiFi + device pci 13.3 on end # - PCIe-A 3 LAN4 + device pci 14.0 off end # - PCIe-B 0 + device pci 14.1 off end # - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 off end # - I2C 0 + device pci 16.1 off end # - I2C 1 + device pci 16.2 off end # - I2C 2 + device pci 16.3 off end # - I2C 3 + device pci 17.0 off end # - I2C 4 + device pci 17.1 off end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 + device pci 18.0 off end # - UART 0 + device pci 18.1 off end # - UART 1 + device pci 18.2 off end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 off end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 off end # - PWM + device pci 1b.0 off end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip drivers/pc80/tpm + device pnp 0c31.0 on end + end + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 on # Environment Controller + io 0x60 = 0xa30 + io 0x62 = 0xa20 + irq 0x70 = 9 + irq 0xf0 = 0x80 # Clear 3VSB + irq 0xf1 = 0x80 # Clear AVCC3 + irq 0xf4 = 0x60 # Use SB to control AC power loss + end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0xa10 + io 0x62 = 0xa00 + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/protectli/vault_glk/die.c b/src/mainboard/protectli/vault_glk/die.c new file mode 100644 index 00000000000..f46c6f9a9a4 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/die.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void beep_and_blink(void) +{ + static uint8_t blink = 0; + static uint8_t beep_count = 0; + + gpio_set(GPIO_142, blink); + /* Beep 12 times at most, constant beeps may be annoying */ + if (beep_count < 12) { + beep(800, 300); + mdelay(200); + beep_count++; + } else { + mdelay(500); + } + + blink ^= 1; +} + +void die_notify(void) +{ + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink and use PC SPKR */ + gpio_output(GPIO_142, 0); + + while (1) { + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + delay(2); + } +} diff --git a/src/mainboard/protectli/vault_glk/dsdt.asl b/src/mainboard/protectli/vault_glk/dsdt.asl new file mode 100644 index 00000000000..0ff068f43a0 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/dsdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + /* global NVS and variables */ + #include + + /* CPU */ + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + #include + } + } + + #include +} diff --git a/src/mainboard/protectli/vault_glk/gpio.h b/src/mainboard/protectli/vault_glk/gpio.h new file mode 100644 index 00000000000..7058ae51bf9 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/gpio.h @@ -0,0 +1,483 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include + +/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT_IOS +#define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +#endif + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + + +/* Pad configuration was generated automatically using intelp2m utility */ +static const struct pad_config gpio_table[] = { + + /* ----- GPIO Community NorthWest ----- */ + + /* ------- GPIO Group NorthWest ------- */ + + /* GPIO_0 - JTAG_TCK */ + PAD_CFG_NF(GPIO_0, DN_20K, DEEP, NF1), + /* GPIO_1 - JTAG_TRST_N */ + PAD_CFG_NF(GPIO_1, DN_20K, DEEP, NF1), + /* GPIO_2 - JTAG_TMS */ + PAD_CFG_NF(GPIO_2, UP_20K, DEEP, NF1), + /* GPIO_3 - JTAG_TDI */ + PAD_CFG_NF(GPIO_3, UP_20K, DEEP, NF1), + /* GPIO_4 - JTAG_TDO */ + PAD_CFG_NF(GPIO_4, UP_20K, DEEP, NF1), + /* GPIO_5 - JTAGX */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_5, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_6 - JTAG_PREQ_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_6, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_7 - JTAG_PRDY_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_7, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_8 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_8, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_9 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_9, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_10 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_10, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_11 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_11, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_12 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_12, DN_20K, PWROK, NF5, HIZCRx0, ENPD), + /* GPIO_13 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_13, DN_20K, DEEP, NF5, HIZCRx0, ENPD), + /* GPIO_14 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_14, DN_20K, DEEP, NF5, HIZCRx0, ENPD), + /* GPIO_15 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_15, DN_20K, DEEP, NF5, HIZCRx0, ENPD), + /* GPIO_16 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_16, DN_20K, DEEP, NF5, HIZCRx0, ENPD), + /* GPIO_17 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_17, 0, DEEP, UP_20K, TxDRxE, ENPU), + /* GPIO_18 - GPIO */ + PAD_CFG_GPI_APIC_IOS(GPIO_18, UP_20K, DEEP, LEVEL, NONE, IGNORE, ENPU), + /* GPIO_19 - GPIO */ + PAD_CFG_GPI_APIC_IOS(GPIO_19, UP_20K, DEEP, EDGE_SINGLE, NONE, TxDRxE, ENPU), + /* GPIO_20 - GPIO */ + PAD_CFG_GPI_APIC_IOS(GPIO_20, NONE, DEEP, LEVEL, NONE, IGNORE, SAME), + /* GPIO_21 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_21, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_22 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_22, 1, DEEP, UP_20K, TxDRxE, ENPU), + /* GPIO_23 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_23, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_24 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_24, UP_20K, DEEP, OFF, TxLASTRxE, ENPU, ACPI), + /* GPIO_25 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_25, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_26 - GPIO */ + PAD_CFG_GPI_SCI_IOS(GPIO_26, UP_20K, DEEP, EDGE_SINGLE, INVERT, IGNORE, ENPU), + /* GPIO_27 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_27, 1, DEEP, NONE, IGNORE, DISPUPD), + /* GPIO_28 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_28, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_29 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_29, 1, DEEP, UP_20K, HIZCRx1, DISPUPD), + /* GPIO_30 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_30, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_31 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_31, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_32 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_32, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_33 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_33, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_34 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_34, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_35 - SPKR */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_35, UP_20K, DEEP, NF4, IGNORE, ENPU), + /* GPIO_36 - BSSB_DI */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_36, UP_20K, DEEP, NF6, IGNORE, ENPU), + /* GPIO_37 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_37, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_38 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_38, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_39 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_39, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_40 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_40, UP_20K, DEEP, IGNORE, ENPU), + /* GPIO_41 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_41, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_42 - MDSI_A_TE */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_42, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_43 - MDSI_C_TE */ + PAD_CFG_NF(GPIO_43, NONE, DEEP, NF1), + /* GPIO_44 - USB2_OC0_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_44, UP_20K, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_45 - USB2_OC1_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_45, UP_20K, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_46 - MIPI_I2C_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_46, NONE, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_47 - MIPI_I2C_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_47, NONE, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_48 - PMC_I2C_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_48, UP_1K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_49 - PMC_I2C_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_49, UP_1K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_50 - SIO_I2C0_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_50, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_51 - SIO_I2C0_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_51, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_52 - SIO_I2C1_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_52, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_53 - SIO_I2C1_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_53, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_54 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_54, UP_1K, DEEP, HIZCRx1, ENPU), + /* GPIO_55 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_55, UP_1K, DEEP, HIZCRx1, ENPU), + /* GPIO_56 - SIO_I2C3_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_56, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_57 - SIO_I2C3_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_57, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_58 - SIO_I2C4_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_58, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_59 - SIO_I2C4_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_59, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_60 - SIO_UART0_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_60, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_61 - SIO_UART0_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_61, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_62 - SIO_UART0_RTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_62, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_63 - SIO_UART0_CTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_63, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_64 - SIO_UART2_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_64, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_65 - SIO_UART2_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_65, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_66 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_66, 1, DEEP, UP_20K, TxLASTRxE, ENPU), + /* GPIO_67 - SIO_UART2_CTS_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_67, NONE, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_68 - PMC_SPI_FS0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_68, UP_20K, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_69 - PMC_SPI_FS1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_69, NONE, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_70 - PMC_SPI_FS2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_70, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_71 - PMC_SPI_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_71, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_72 - PMC_SPI_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_72, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_73 - PMC_SPI_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_73, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_74 - THERMTRIP_N */ + PAD_CFG_NF(GPIO_74, UP_20K, DEEP, NF1), + /* GPIO_75 - PROCHOT_N */ + PAD_CFG_NF(GPIO_75, UP_20K, DEEP, NF1), + /* GPIO_211 - RESERVED */ + /* GPIO_212 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_212, UP_20K, DEEP, OFF, HIZCRx0, ENPU, ACPI), + /* GPIO_213 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_213, 1, DEEP, UP_20K, HIZCRx0, ENPU), + /* GPIO_214 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_214, 1, DEEP, NONE, IGNORE, SAME), + + /* --- GPIO Community North --- */ + + /* ----- GPIO Group North ----- */ + + /* GPIO_76 - SVID0_ALERT_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_76, NONE, DEEP, NF1), + /* GPIO_77 - SVID0_DATA */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_77, NONE, DEEP, NF1), + /* GPIO_78 - SVID0_CLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_78, NONE, DEEP, NF1), + /* GPIO_79 - SIO_SPI_0_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_79, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_80 - SIO_SPI_0_FS0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_80, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_81 - FST_SPI_CS2_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_81, NONE, DEEP, NF3), + /* GPIO_82 - SIO_SPI_0_RXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_82, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_83 - SIO_SPI_0_TXD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_83, DN_20K, DEEP, NF1, IGNORE, ENPD), + /* GPIO_84 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_84, DN_20K, DEEP, OFF, ACPI), + /* GPIO_85 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_85, DN_20K, DEEP, TxLASTRxE, SAME), + /* GPIO_86 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_86, DN_20K, DEEP, TxLASTRxE, SAME), + /* GPIO_87 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_87, DN_20K, DEEP, TxLASTRxE, SAME), + /* GPIO_88 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_88, DN_20K, DEEP, OFF, ACPI), + /* GPIO_89 - GPIO */ + PAD_CFG_GPI_TRIG_OWN(GPIO_89, DN_20K, DEEP, OFF, ACPI), + /* GPIO_90 - FST_SPI_CS0_N */ + PAD_CFG_NF(GPIO_90, NATIVE, DEEP, NF1), + /* GPIO_91 - FST_SPI_CS1_N */ + PAD_CFG_NF(GPIO_91, NATIVE, DEEP, NF1), + /* GPIO_92 - FST_SPI_MOSI_IO0 */ + PAD_CFG_NF(GPIO_92, NATIVE, DEEP, NF1), + /* GPIO_93 - FST_SPI_MISO_IO1 */ + PAD_CFG_NF(GPIO_93, NATIVE, DEEP, NF1), + /* GPIO_94 - FST_SPI_IO2 */ + PAD_CFG_NF(GPIO_94, NATIVE, DEEP, NF1), + /* GPIO_95 - FST_SPI_IO3 */ + PAD_CFG_NF(GPIO_95, NATIVE, DEEP, NF1), + /* GPIO_96 - FST_SPI_CLK */ + PAD_CFG_NF(GPIO_96, NATIVE, DEEP, NF1), + /* GPIO_97 - FST_SPI_CLK_FB */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + /* GPIO_98 - PMU_PLTRST_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_98, NONE, DEEP, NF1), + /* GPIO_99 - PMU_PWRBTN_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_99, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_100 - PMU_SLP_S0_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_100, NONE, DEEP, NF1), + /* GPIO_101 - PMU_SLP_S3_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_101, NONE, DEEP, NF1), + /* GPIO_102 - PMU_SLP_S4_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_102, NONE, DEEP, NF1), + /* GPIO_103 - SUSPWRDNACK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_103, NONE, DEEP, NF1), + /* GPIO_104 - EMMC_PWR_EN_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_104, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_105 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_105, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_106 - PMU_BATLOW_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_106, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_107 - PMU_RSTBTN_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_107, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_108 - PMU_SUSCLK */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_108, NONE, DEEP, NF1), + /* GPIO_109 - SUS_STAT_N */ + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_109, NONE, DEEP, NF1), + /* GPIO_110 - ISH_I2C0_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_110, UP_1K, DEEP, NF2, IGNORE, ENPU), + /* GPIO_111 - ISH_I2C0_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_111, UP_1K, DEEP, NF2, IGNORE, ENPU), + /* GPIO_112 - ISH_I2C1_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_112, UP_1K, DEEP, NF2, IGNORE, ENPU), + /* GPIO_113 - ISH_I2C1_ScL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_113, UP_1K, DEEP, NF2, IGNORE, ENPU), + /* GPIO_114 - SIO_I2C7_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_114, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_115 - SIO_I2C7_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_115, UP_1K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_116 - PCIE_WAKE0_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_116, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_117 - PCIE_WAKE1_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_117, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_118 - PCIE_WAKE2_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_118, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_119 - PCIE_WAKE3_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_119, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_120 - PCIE_CLKREQ0_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_120, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_121 - PCIE_CLKREQ1_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_121, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_122 - PCIE_CLKREQ2_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_122, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_123 - PCIE_CLKREQ3_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_123, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_124 - DDI0_DDC_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_124, NONE, DEEP, NF1, HIZCRx0, ENPU), + /* GPIO_125 - DDI0_DDC_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_125, NONE, DEEP, NF1, HIZCRx0, ENPU), + /* GPIO_126 - DDI1_DDC_SDA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_126, UP_20K, DEEP, NF1, HIZCRx0, ENPU), + /* GPIO_127 - DDI1_DDC_SCL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_127, UP_20K, DEEP, NF1, HIZCRx0, ENPU), + /* GPIO_128 - PNL0_VDDEN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_128, DN_20K, DEEP, NF1, Tx0RxDCRx0, ENPD), + /* GPIO_129 - PNL0_BKLTEN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_129, DN_20K, DEEP, NF1, Tx0RxDCRx0, ENPD), + /* GPIO_130 - PNL0_BKLCTL */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_130, DN_20K, DEEP, NF1, Tx0RxDCRx0, ENPD), + /* GPIO_131 - DDI0_HPD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_131, UP_20K, DEEP, NF1, TxDRxE, ENPU), + /* GPIO_132 - DDI1_HPD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_132, UP_20K, DEEP, NF1, TxDRxE, ENPU), + /* GPIO_133 - DDI2_HPD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_133, NONE, DEEP, NF1, TxDRxE, ENPU), + /* GPIO_134 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_134, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_135 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_135, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_136 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_136, 0, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_137 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_137, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_138 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_138, 1, DEEP, NONE, TxLASTRxE, ENPU), + /* GPIO_139 - SATA_GP1 */ + PAD_CFG_NF(GPIO_139, NONE, DEEP, NF5), + /* GPIO_140 - SATA_DEVSLP0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_140, DN_20K, DEEP, NF5, TxLASTRxE, ENPD), + /* GPIO_141 - GPIO */ + PAD_CFG_GPIO_BIDIRECT_IOS(GPIO_141, 0, NONE, DEEP, OFF, HIZCRx1, ENPU, ACPI), + /* GPIO_142 - SATA_LEDN */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_142, UP_20K, DEEP, NF5, HIZCRx1, ENPU), + /* GPIO_143 - GPIO */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_143, NONE, DEEP, OFF, HIZCRx1, ACPI), + /* GPIO_144 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_144, 0, DEEP, DN_20K, HIZCRx1, ENPD), + /* GPIO_145 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_145, 0, DEEP, DN_20K, HIZCRx1, ENPD), + /* GPIO_146 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_146, UP_20K, DEEP, NF5, HIZCRx1, ENPU), + /* GPIO_147 - LPC_SERIRQ */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_147, UP_20K, DEEP, NF1, TxLASTRxE, ENPU), + /* GPIO_148 - LPC_CLKOUT0 */ + PAD_CFG_NF_IOSSTATE(GPIO_148, NONE, DEEP, NF1, HIZCRx1), + /* GPIO_149 - LPC_CLKOUT1 */ + PAD_CFG_NF_IOSSTATE(GPIO_149, NONE, DEEP, NF1, HIZCRx1), + /* GPIO_150 - LPC_AD0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_150, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_151 - LPC_AD1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_151, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_152 - LPC_AD2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_152, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_153 - LPC_AD3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_153, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_154 - LPC_CLKRUN_N */ + PAD_CFG_NF(GPIO_154, UP_20K, DEEP, NF1), + /* GPIO_155 - LPC_FRAME_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + + /* --- GPIO Community Audio --- */ + + /* ----- GPIO Group Audio ----- */ + + /* GPIO_156 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_156, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_157 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_157, DN_20K, DEEP, OFF, IGNORE, ENPD, ACPI), + /* GPIO_158 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_158, 0, DEEP, DN_20K, IGNORE, ENPD), + /* GPIO_159 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_159, 1, DEEP, UP_20K, TxDRxE, DISPUPD), + /* GPIO_160 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_160, 0, DEEP, DN_20K, IGNORE, ENPD), + /* GPIO_161 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_161, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_162 - GPIO */ + PAD_CFG_GPIO_HI_Z(GPIO_162, UP_20K, DEEP, IGNORE, ENPU), + /* GPIO_163 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_163, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_164 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_164, 1, DEEP, UP_5K, TxDRxE, ENPU), + /* GPIO_165 - GPIO */ + PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_165, DN_20K, DEEP, OFF, IGNORE, ENPD, ACPI), + /* GPIO_166 - AVS_HDA_BCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_166, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_167 - AVS_HDA_WS_SYNC */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_167, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_168 - AVS_HDA_SDI */ + PAD_CFG_NF_IOSSTATE(GPIO_168, NONE, DEEP, NF1, HIZCRx1), + /* GPIO_169 - AVS_HDA_SDO */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_169, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_170 - AVS_HDA_RST_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_170, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_171 - AVS_DMIC_CLK_A1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_171, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_172 - AVS_DMIC_CLK_B1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_173 - AVS_DMIC_DATA_1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_173, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_174 - AVS_DMIC_CLK_AB2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + /* GPIO_175 - AVS_DMIC_DATA_2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1, ENPD), + + /* --- GPIO Community SCC --- */ + + /* ----- GPIO Group SCC ----- */ + + /* GPIO_176 - SMB_ALERT_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_176, UP_20K, PWROK, NF1, IGNORE, ENPU), + /* GPIO_177 - SMB_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_177, UP_5K, PWROK, NF1, IGNORE, ENPU), + /* GPIO_178 - SMB_DATA */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_178, UP_5K, PWROK, NF1, IGNORE, ENPU), + /* GPIO_187 - SDCARD_LVL_WP */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_187, UP_20K, DEEP, NF1, IGNORE, ENPU), + /* GPIO_179 - SDCARD_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_179, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* GPIO_180 - SDCARD_CLK_FB */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_180, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_181 - SDCARD_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_181, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_182 - SDCARD_D1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_182, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_183 - SDCARD_D2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_183, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_184 - SDCARD_D3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_184, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_185 - SDCARD_CMD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_185, UP_20K, DEEP, NF1, HIZCRx0, DISPUPD), + /* GPIO_186 - GPIO */ + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_186, NONE, DEEP, EDGE_SINGLE, TxDRxE, ACPI), + /* GPIO_188 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_188, 0, DEEP, DN_20K, TxLASTRxE, ENPD), + /* GPIO_210 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_210, 1, DEEP, UP_20K, HIZCRx0, ENPD), + /* GPIO_189 - OSC_CLK_OUT_0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_189, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* GPIO_190 - OSC_CLK_OUT_1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_190, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* GPIO_191 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_191, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_192 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_192, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_193 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_193, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_194 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_194, 1, DEEP, UP_20K, IGNORE, ENPU), + /* GPIO_195 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_195, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_196 - GPIO */ + PAD_CFG_GPO_IOSSTATE_IOSTERM(GPIO_196, 1, DEEP, NONE, IGNORE, SAME), + /* GPIO_197 - n/a */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_197, DN_20K, DEEP, NF2, TxLASTRxE, ENPD), + /* GPIO_198 - EMMC_CLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_198, DN_20K, DEEP, NF1, HIZCRx0, ENPD), + /* GPIO_199 - EMMC_D0 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_199, DN_20K, DEEP, NF1, TxLASTRxE, ENPD), + /* GPIO_200 - EMMC_D1 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_200, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_201 - EMMC_D2 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_201, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_202 - EMMC_D3 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_202, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_203 - EMMC_D4 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_203, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_204 - EMMC_D5 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_204, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_205 - EMMC_D6 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_205, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_206 - EMMC_D7 */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_206, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_207 - EMMC_CMD */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_207, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_208 - EMMC_RCLK */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_208, UP_20K, DEEP, NF1, HIZCRx1, ENPU), + /* GPIO_209 - EMMC_RST_N */ + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_209, DN_20K, DEEP, NF1, HIZCRx0, ENPD) +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/protectli/vault_glk/hda_verb.c b/src/mainboard/protectli/vault_glk/hda_verb.c new file mode 100644 index 00000000000..9a7345b29ba --- /dev/null +++ b/src/mainboard/protectli/vault_glk/hda_verb.c @@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* GeminiLake HDMI */ + 0x8086280d, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 4, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x05, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x07, 0x18560010) +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/protectli/vault_glk/mainboard.c b/src/mainboard/protectli/vault_glk/mainboard.c new file mode 100644 index 00000000000..341ef0497a5 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/mainboard.c @@ -0,0 +1,84 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void mainboard_final(void *chip_info) +{ + if (CONFIG(BEEP_ON_BOOT)) + beep(1500, 100); +} + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + silconfig->C1e = 0x1; + silconfig->PkgCStateLimit = 0xFE; + silconfig->CStateAutoDemotion = 0x3; + silconfig->CStateUnDemotion = 0x3; + silconfig->PkgCStateDemotion = 0x1; + silconfig->PkgCStateUnDemotion = 0x1; + silconfig->Usb30Mode = 0x1; + silconfig->DspEnable = 0x0; + silconfig->UsbPdoProgramming = 0x1; + + silconfig->PcieRpHotPlug[0] = 0x0; + silconfig->PcieRpPmSci[0] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[0] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[0] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[0] = 0x1003; + silconfig->PcieRpClkReqSupported[0] = 0x0; + silconfig->AdvancedErrorReporting[0] = 0x1; + silconfig->PmeInterrupt[0] = 0x1; + + silconfig->PcieRpHotPlug[1] = 0x0; + silconfig->PcieRpPmSci[1] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[1] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[1] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[1] = 0x1003; + silconfig->PcieRpClkReqSupported[1] = 0x0; + silconfig->AdvancedErrorReporting[1] = 0x1; + silconfig->PmeInterrupt[1] = 0x1; + + silconfig->PcieRpHotPlug[2] = 0x0; + silconfig->PcieRpPmSci[2] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[2] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[2] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[2] = 0x1003; + silconfig->PcieRpClkReqSupported[2] = 0x0; + silconfig->AdvancedErrorReporting[2] = 0x1; + silconfig->PmeInterrupt[2] = 0x1; + + silconfig->PcieRpHotPlug[3] = 0x0; + silconfig->PcieRpPmSci[3] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[3] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[3] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[3] = 0x1003; + silconfig->PcieRpClkReqSupported[3] = 0x0; + silconfig->AdvancedErrorReporting[3] = 0x1; + silconfig->PmeInterrupt[3] = 0x1; + + silconfig->PcieRpHotPlug[4] = 0x0; + silconfig->PcieRpPmSci[4] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[4] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[4] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[4] = 0x1003; + silconfig->PcieRpClkReqSupported[4] = 0x0; + silconfig->AdvancedErrorReporting[4] = 0x1; + silconfig->PmeInterrupt[4] = 0x1; + + silconfig->PcieRpHotPlug[5] = 0x0; + silconfig->PcieRpPmSci[5] = 0x1; + silconfig->PcieRpTransmitterHalfSwing[5] = 0x0; + silconfig->PcieRpLtrMaxNonSnoopLatency[5] = 0x1003; + silconfig->PcieRpLtrMaxSnoopLatency[5] = 0x1003; + silconfig->PcieRpClkReqSupported[5] = 0x0; + silconfig->AdvancedErrorReporting[5] = 0x1; + silconfig->PmeInterrupt[5] = 0x1; +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final, +}; diff --git a/src/mainboard/protectli/vault_glk/romstage.c b/src/mainboard/protectli/vault_glk/romstage.c new file mode 100644 index 00000000000..5a1102bf195 --- /dev/null +++ b/src/mainboard/protectli/vault_glk/romstage.c @@ -0,0 +1,174 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#include "gpio.h" + +/* DDR4 specific swizzling data start */ + +/* Channel 0 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch0_ddr4[] = { + 1, 0, 5, 7, 2, 3, 6, 4, 24, 29, 28, 26, 25, 30, 31, 27, + 19, 18, 23, 22, 17, 16, 21, 20, 8, 9, 12, 13, 10, 15, 11, 14, +}; + +/* Channel 1 PHY 0 to DUnit DQ mapping */ +static const uint8_t swizzling_ch1_ddr4[] = { + 5, 6, 0, 2, 4, 7, 3, 1, 12, 13, 10, 11, 15, 14, 9, 8, + 21, 22, 18, 16, 23, 19, 17, 20, 28, 30, 27, 26, 29, 24, 31, 25, +}; + +/* DDR4 specific swizzling data end */ + +static void fill_ddr4_params(FSP_M_CONFIG *cfg) +{ + cfg->Ch0_DeviceWidth = 0x00; /* Only for memory down */ + cfg->Ch0_DramDensity = 0x00; /* Only for memory down */ + cfg->Ch0_Mode2N = 0x00; /* Only for DDR3L */ + cfg->Ch0_OdtConfig = 0; + cfg->Ch0_OdtLevels = 0; /* ODT connected to SoC */ + /* bit0 Rank Select Interleaving Enable , + bit1 Bank Address Hashing enabled */ + cfg->Ch0_Option = 0x03; + /* bit0 enable rank 0, + * bit1 enable rank 1. + * This is allowed maximum, it may be trimmed down by FSP based on SPD data. + */ + cfg->Ch0_RankEnable = 0x03; + cfg->Ch0_TristateClk1 = 0x00; + + cfg->Ch1_DeviceWidth = 0x00; + cfg->Ch1_DramDensity = 0x00; + cfg->Ch1_Mode2N = 0x00; + cfg->Ch1_OdtConfig = 0; + cfg->Ch1_OdtLevels = 0; + cfg->Ch1_Option = 0x03; + cfg->Ch1_RankEnable = 0x03; + cfg->Ch1_TristateClk1 = 0x00; + + cfg->Ch2_DeviceWidth = 0x00; + cfg->Ch2_DramDensity = 0x00; + cfg->Ch2_Mode2N = 0x00; + cfg->Ch2_OdtConfig = 0; + cfg->Ch2_OdtLevels = 0; + cfg->Ch2_Option = 0x03; + cfg->Ch2_RankEnable = 0x03; + cfg->Ch2_TristateClk1 = 0x00; + + cfg->Ch3_DramDensity = 0x00; + cfg->Ch3_Mode2N = 0x00; + cfg->Ch3_OdtConfig = 0; + cfg->Ch3_OdtLevels = 0; + cfg->Ch3_Option = 0x03; + cfg->Ch3_RankEnable = 0x03; + cfg->Ch3_TristateClk1 = 0x00; + + cfg->ChannelHashMask = 0x00; + cfg->ChannelsSlicesEnable = 0x00; + cfg->DDR3LASR = 0x00; /* Only for memory down */ + cfg->DDR3LPageSize = 0x00; /* Only for memory down */ + cfg->DIMM0SPDAddress = 0xA0; + cfg->DIMM1SPDAddress = 0xA4; + cfg->DisableFastBoot = 0x00; /* Use saved training data if valid */ + cfg->DualRankSupportEnable = 0x01; + cfg->eMMCTraceLen = 0x0; + cfg->EnhancePort8xhDecoding = 1; + cfg->HighMemoryMaxValue = 0x00; + cfg->Igd = 0x01; + cfg->IgdApertureSize = 0x1; /* 128MB */ + cfg->IgdDvmt50PreAlloc = 0x02; /* 64MB */ + cfg->GttSize = 0x3; /* 8MB */ + cfg->InterleavedMode = 0x02; /* Enable = 0x2? */ + cfg->LowMemoryMaxValue = 0x0000; + cfg->MemoryDown = 0x0; + cfg->MemorySizeLimit = 0x0000; + cfg->MinRefRate2xEnable = 0x01; + cfg->MrcDataSaving = 0x01; + cfg->MrcFastBoot = 0x01; + cfg->MsgLevelMask = 0x00000000; + /* Specifies CA Mapping for all technologies. + * 0 - SODIMM(Default) + * 1 - BGA + * 2 - BGA mirrored (LPDDR3 only) + * 3 - SODIMM/UDIMM with Rank 1 Mirrored (DDR3L) + */ + cfg->Package = 0x00; + cfg->PreMemGpioTableEntryNum = 0; + cfg->PreMemGpioTablePinNum[0] = 0; + cfg->PreMemGpioTablePinNum[1] = 0; + cfg->PreMemGpioTablePinNum[2] = 0; + cfg->PreMemGpioTablePinNum[3] = 0; + cfg->PreMemGpioTablePtr = 0x00000000; + /* + * FSP headers say: 0x0:AUTO, 0x2:IGD, 0x3:PCI, but the Geminilake FSP + * code says: 0x0:IGD, 0x1:PCI + */ + cfg->PrimaryVideoAdaptor = 0x0; + /* + * Profiles: + * 0x01:LPDDR3_1333_10_12_12, + * 0x02:LPDDR3_1600_12_15_15, + * 0x03:LPDDR3_1866_14_17_17, + * 0x04:LPDDR4_1600_14_15_15, + * 0x05:LPDDR4_1866_20_17_17, + * 0x06:LPDDR4_2133_20_20_20, + * 0x07:LPDDR4_2400_24_22_22, + * 0x08:LPDDR4_2666_24_24_24, + * 0x09:LPDDR4_3200_28_29_29, + * 0x0A:DDR4_1600_10_10_10, + * 0x0B:DDR4_1600_11_11_11, + * 0x0C:DDR4_1600_12_12_12, + * 0x0D:DDR4_1866_12_12_12, + * 0x0E:DDR4_1866_13_13_13, + * 0x0F:DDR4_1866_14_14_14, + * 0x10:DDR4_2133_14_14_14, + * 0x11:DDR4_2133_15_15_15, + * 0x12:DDR4_2133_16_16_16, + * 0x13:DDR4_2400_15_15_15, + * 0x14:DDR4_2400_16_16_16, + * 0x15:DDR4_2400_17_17_17 (default), + * 0x16:DDR4_2400_18_18_18, + * 0x17:DDR4_2666_17_17_17, + * 0x18:DDR4_2666_18_18_18, + * 0x19:DDR4_2666_19_19_19, + * 0x1A:DDR4_2666_20_20_20 + */ + cfg->Profile = 0x15; + cfg->OemLoadingBase = 0; + /* Tolerance percentage o failing margins */ + cfg->RmtMarginCheckScaleHighThreshold = 0x0000; + cfg->RmtMode = 0x00; + cfg->ScramblerSupport = 0x01; + cfg->SerialDebugPortAddress = 0x000003f8; + cfg->SerialDebugPortDevice = 0x03; /* External device */ + cfg->SerialDebugPortStrideSize = 0x00; /* Stride 1 byte */ + cfg->SerialDebugPortType = 0x01; /* I/O */ + cfg->SliceHashMask = 0x00; + cfg->SpdWriteEnable = 0x00; + cfg->StartTimerTickerOfPfetAssert = 0x4E20; + + /* phy0 ch0 */ + memcpy(cfg->Ch0_Bit_swizzling, swizzling_ch0_ddr4, sizeof(swizzling_ch0_ddr4)); + /* phy0 ch1 */ + memcpy(cfg->Ch1_Bit_swizzling, swizzling_ch1_ddr4, sizeof(swizzling_ch1_ddr4)); + /* phy1 ch1 */ + memset(cfg->Ch2_Bit_swizzling, 0, sizeof(cfg->Ch2_Bit_swizzling)); + /* phy1 ch0 */ + memset(cfg->Ch3_Bit_swizzling, 0, sizeof(cfg->Ch3_Bit_swizzling)); +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + FSP_M_CONFIG *cfg = &memupd->FspmConfig; + fill_ddr4_params(cfg); + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} + +void mainboard_save_dimm_info(void) +{ + save_ddr4_dimm_info(); +} diff --git a/src/mainboard/protectli/vault_jsl/Kconfig b/src/mainboard/protectli/vault_jsl/Kconfig new file mode 100644 index 00000000000..fdbe11ef4a7 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/Kconfig @@ -0,0 +1,61 @@ +if BOARD_PROTECTLI_V1210 || BOARD_PROTECTLI_V1211 || BOARD_PROTECTLI_V1410 || BOARD_PROTECTLI_V1610 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_16384 + select SOC_INTEL_JASPERLAKE + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select SUPERIO_ITE_IT8613E + select INTEL_GMA_HAVE_VBT + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS + select USE_LPDDR4 + select CRB_TPM + select HAVE_INTEL_PTT + select MAINBOARD_HAS_TPM2 + +config MAX_CPUS + default 4 + +config MAINBOARD_DIR + string + default "protectli/vault_jsl" + +config OVERRIDE_DEVICETREE + default "override_v12xx.cb" if BOARD_PROTECTLI_V1210 || BOARD_PROTECTLI_V1211 + default "override_v1410.cb" if BOARD_PROTECTLI_V1410 + default "override_v1610.cb" if BOARD_PROTECTLI_V1610 + +config MAINBOARD_PART_NUMBER + string + default "V1210" if BOARD_PROTECTLI_V1210 + default "V1211" if BOARD_PROTECTLI_V1211 + default "V1410" if BOARD_PROTECTLI_V1410 + default "V1610" if BOARD_PROTECTLI_V1610 + +config MAINBOARD_FAMILY + string + default "Vault" + +config DIMM_MAX + default 2 + +config DIMM_SPD_SIZE + default 512 + +config CBFS_SIZE + default 0x800000 + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" + +config BEEP_ON_BOOT + bool "Beep on successful boot" + default y + help + Make the platform beep using the PC speaker in final coreboot phase. + May serve as a useful indicator in headless mode that platform is + properly booting. + +endif diff --git a/src/mainboard/protectli/vault_jsl/Kconfig.name b/src/mainboard/protectli/vault_jsl/Kconfig.name new file mode 100644 index 00000000000..caaa9f444ed --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/Kconfig.name @@ -0,0 +1,11 @@ +config BOARD_PROTECTLI_V1210 + bool "V1210" + +config BOARD_PROTECTLI_V1211 + bool "V1211" + +config BOARD_PROTECTLI_V1410 + bool "V1410" + +config BOARD_PROTECTLI_V1610 + bool "V1610" diff --git a/src/mainboard/protectli/vault_jsl/Makefile.mk b/src/mainboard/protectli/vault_jsl/Makefile.mk new file mode 100644 index 00000000000..1c840117da4 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/Makefile.mk @@ -0,0 +1,17 @@ + +# SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += bootblock.c + +romstage-y += romstage.c + +ramstage-y += mainboard.c + +bootblock-y += die.c +romstage-y += die.c +ramstage-y += die.c +smm-y += die.c + +#SPD_SOURCES = MT53E512M32D4NQ-053 # 2GBx4 (pre-production V1210) +SPD_SOURCES = MT53D512M64D4RQ-046 # 2GBx4 (production V1210) +SPD_SOURCES += MT53E1G32D2NP-046 # 4GBx4 diff --git a/src/mainboard/protectli/vault_jsl/board.fmd b/src/mainboard/protectli/vault_jsl/board.fmd new file mode 100644 index 00000000000..7b055e11707 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/board.fmd @@ -0,0 +1,15 @@ +FLASH@0xff000000 0x1000000 { + SI_ALL 8M { + SI_DESC 4K + SI_ME + } + + SMMSTORE(PRESERVE) 256K + RW_MRC_CACHE 64K + CONSOLE 0x20000 + BOOTSPLASH(CBFS) 1M + WP_RO { + FMAP 4K + COREBOOT(CBFS) + } +} diff --git a/src/mainboard/protectli/vault_jsl/board_info.txt b/src/mainboard/protectli/vault_jsl/board_info.txt new file mode 100644 index 00000000000..257dc512e62 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Protectli +Board name: V1210/V1410/V1610 +Category: sbc +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/protectli/vault_jsl/bootblock.c b/src/mainboard/protectli/vault_jsl/bootblock.c new file mode 100644 index 00000000000..2b925ee1f58 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/bootblock.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include + +#define SERIAL1_DEV PNP_DEV(0x2e, IT8613E_SP1) +#define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) + +static void ite_set_gpio_base(pnp_devfn_t dev, uint16_t iobase) +{ + pnp_enter_conf_state(dev); + pnp_set_logical_device(dev); + pnp_set_iobase(dev, PNP_IDX_IO1, iobase); + pnp_exit_conf_state(dev); +} + +void bootblock_mainboard_early_init(void) +{ + ite_kill_watchdog(GPIO_DEV); + ite_reg_write(GPIO_DEV, 0x26, 0xfb); /* Pin7 as GP23 */ + ite_reg_write(GPIO_DEV, 0x29, 0x00); + ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable K8 power seq */ + ite_reg_write(SERIAL1_DEV, 0xf0, 0x01); /* enable IRQ sharing */ + ite_enable_serial(SERIAL1_DEV, CONFIG_TTYS0_BASE); + + ite_reg_write(GPIO_DEV, 0xc1, 0x0a); /* GP21 and GP23 as simple I/O */ + ite_reg_write(GPIO_DEV, 0xc9, 0x0a); /* GP21 and GP23 as output */ + ite_set_gpio_base(GPIO_DEV, 0xa00); + + /* GP21 and GP23 to low to enable USB ports VBUS */ + outb(inb(0xa01) & ~0x0a, 0xa01); +} diff --git a/src/mainboard/protectli/vault_jsl/data.vbt b/src/mainboard/protectli/vault_jsl/data.vbt new file mode 100644 index 00000000000..5e399d752dd Binary files /dev/null and b/src/mainboard/protectli/vault_jsl/data.vbt differ diff --git a/src/mainboard/protectli/vault_jsl/devicetree.cb b/src/mainboard/protectli/vault_jsl/devicetree.cb new file mode 100644 index 00000000000..d30376d778d --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/devicetree.cb @@ -0,0 +1,156 @@ +chip soc/intel/jasperlake + + device cpu_cluster 0 on end + + register "eist_enable" = "1" + + register "enable_c6dram" = "1" + + register "tcc_offset" = "20" + + # GPE configuration + register "pmc_gpe0_dw0" = "GPP_G" + register "pmc_gpe0_dw1" = "GPP_C" + register "pmc_gpe0_dw2" = "GPP_R" + + # FSP configuration + register "SaGv" = "SaGv_Enabled" + register "SmbusEnable" = "1" + register "ScsEmmcHs400Enabled" = "1" + + # Display related UPDs + + # Enable HPD for DDI port C + register "DdiPortCHpd" = "1" + + # Enable DDC for DDI port C + register "DdiPortCDdc" = "1" + + register "SkipExtGfxScan" = "1" + + register "usb2_ports" = "{ + [1] = USB2_PORT_SHORT(OC_SKIP), // Type A port1 + [2] = USB2_PORT_SHORT(OC_SKIP), // M.2 LTE + [3] = USB2_PORT_SHORT(OC_SKIP), // WiFi slot BT + [4] = USB2_PORT_SHORT(OC_SKIP), // VIA VL817 hub + }" + + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC_SKIP), // Type A Port1 + [1] = USB3_PORT_DEFAULT(OC_SKIP), // VIA VL817 hub + [5] = USB3_PORT_DEFAULT(OC_SKIP), // M.2 LTE + }" + + register "usb2_wake_enable_bitmap" = "0x0012" + register "usb3_wake_enable_bitmap" = "0x0003" + + register "SataSalpSupport" = "1" + register "SataPortsEnable[1]" = "1" + + register "gen1_dec" = "0x003c0a01" + register "gen2_dec" = "0x000c0081" + register "gen3_dec" = "0x00fc0201" + + # Skip the CPU replacement check + register "SkipCpuReplacementCheck" = "1" + + register "PchHdaDspEnable" = "1" + register "PchHdaAudioLinkHdaEnable" = "1" + + register "PcieClkSrcUsage[0]" = "PCIE_CLK_FREE" # WiFi + register "PcieClkSrcUsage[1]" = "PCIE_CLK_FREE" # M.2 NVMe + register "PcieClkSrcUsage[2]" = "PCIE_CLK_FREE" # LAN1 + register "PcieClkSrcUsage[3]" = "PCIE_CLK_FREE" # LAN2 + register "PcieClkSrcUsage[4]" = "PCIE_CLK_FREE" # clock buffer for LAN3-6 + register "PcieClkSrcUsage[5]" = "PCIE_CLK_NOTUSED" + + # Set the minimum assertion width + register "PchPmSlpS3MinAssert" = "3" # 50ms + register "PchPmSlpS4MinAssert" = "1" # 1s + register "PchPmSlpSusMinAssert" = "3" # 1s + register "PchPmSlpAMinAssert" = "3" # 98ms + + # Set xHCI LFPS period sampling off time, the default is 9ms. + register "xhci_lfps_sampling_offtime_ms" = "9" + + register "disable_external_bypass_vr" = "true" + + # Add PL1 and PL2 values + register "power_limits_config[JSL_N5105_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + register "power_limits_config[JSL_N6005_10W_CORE]" = "{ + .tdp_pl1_override = 10, + .tdp_pl2_override = 20, + }" + + device domain 0 on + device pci 00.0 on end # Host Bridge + device pci 02.0 on end # Integrated Graphics Device + device pci 04.0 off end # SA Thermal device + device pci 05.0 off end # IPU + device pci 08.0 off end # GNA + device pci 09.0 off end # Intel Trace Hub + device pci 12.0 off end # Thermal Subsystem + device pci 12.5 off end # UFS SCS + device pci 12.6 off end # GSPI 2 + device pci 14.0 on end # USB xHCI + device pci 14.1 off end # USB xDCI (OTG) + device pci 14.2 on end # PMC SRAM + device pci 14.3 off end # CNVi + device pci 14.5 off end # SDCard + device pci 15.0 off end # I2C 0 + device pci 15.1 off end # I2C 1 + device pci 15.2 off end # I2C 2 + device pci 15.3 off end # I2C 3 + device pci 16.0 on end # HECI 1 + device pci 16.1 off end # HECI 2 + device pci 16.4 off end # HECI 3 + device pci 16.5 off end # HECI 4 + device pci 17.0 on end # SATA + device pci 19.0 off end # I2C 4 + device pci 19.1 off end # I2C 5 + device pci 19.2 off end # UART 2 + device pci 1c.0 off end # PCI Express Root Port 1 + device pci 1c.1 off end # PCI Express Root Port 2 + device pci 1c.2 off end # PCI Express Root Port 3 + device pci 1c.3 off end # PCI Express Root Port 4 + device pci 1c.4 off end # PCI Express Root Port 5 + device pci 1c.5 off end # PCI Express Root Port 6 + device pci 1c.6 off end # PCI Express Root Port 7 + device pci 1c.7 off end # PCI Express Root Port 8 + device pci 1a.0 on end # eMMC + device pci 1e.0 off end # UART 0 + device pci 1e.1 off end # UART 1 + device pci 1e.2 off end # GSPI 0 + device pci 1e.3 off end # GSPI 1 + device pci 1f.0 on # eSPI + chip superio/ite/it8613e + device pnp 2e.0 off end + device pnp 2e.1 on # COM 1 + io 0x60 = 0x3f8 + irq 0x70 = 4 + end + device pnp 2e.4 off end # Environment Controller + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse + device pnp 2e.7 on # GPIO + io 0x60 = 0xa10 + io 0x62 = 0xa00 + end + device pnp 2e.a off end # CIR + end + end + device pci 1f.1 hidden end # P2SB + device pci 1f.2 hidden end # Power Management Controller + device pci 1f.3 on end # Intel HDA/cAVS + device pci 1f.4 on end # SMBus + device pci 1f.5 on end # PCH SPI + device pci 1f.7 off end # Intel Trace Hub + + chip drivers/crb + device mmio 0xfed40000 on end + end + end +end diff --git a/src/mainboard/protectli/vault_jsl/die.c b/src/mainboard/protectli/vault_jsl/die.c new file mode 100644 index 00000000000..3a48f4623a9 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/die.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +static void beep_and_blink(void) +{ + static uint8_t blink = 0; + static uint8_t beep_count = 0;; + + gpio_set(GPP_E5, blink); + /* Beep 12 times at most, constant beeps may be annoying */ + if (beep_count < 12) { + beep(800, 300); + mdelay(200); + beep_count++; + } else { + mdelay(500); + } + + blink ^= 1; +} + +void die_notify(void) +{ + if (ENV_POSTCAR) + return; + + /* Make SATA LED blink and use PC SPKR */ + gpio_output(GPP_E5, 0); + + while (1) { + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + beep_and_blink(); + delay(2); + } +} diff --git a/src/mainboard/protectli/vault_jsl/dsdt.asl b/src/mainboard/protectli/vault_jsl/dsdt.asl new file mode 100644 index 00000000000..b1c96de6940 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/dsdt.asl @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 +) +{ + #include + #include + #include + #include + + Scope (\_SB) { + Device (PCI0) + { + #include + #include + } + } + + #include +} diff --git a/src/mainboard/protectli/vault_jsl/gpio.h b/src/mainboard/protectli/vault_jsl/gpio.h new file mode 100644 index 00000000000..b486a500388 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/gpio.h @@ -0,0 +1,446 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef CFG_GPIO_H +#define CFG_GPIO_H + +#include + +static const struct pad_config gpio_table[] = { + + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_G ------- */ + + /* GPP_G0 - GPIO */ + PAD_NC(GPP_G0, NONE), + /* GPP_G1 - GPIO */ + PAD_NC(GPP_G1, NONE), + /* GPP_G2 - GPIO */ + PAD_NC(GPP_G2, NONE), + /* GPP_G3 - GPIO */ + PAD_NC(GPP_G3, NONE), + /* GPP_G4 - GPIO */ + PAD_NC(GPP_G4, NONE), + /* GPP_G5 - GPIO */ + PAD_NC(GPP_G5, NONE), + /* GPP_G6 - GPIO */ + PAD_NC(GPP_G6, NONE), + /* GPP_G7 - GPIO */ + PAD_NC(GPP_G7, NONE), + + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_E ------- */ + + /* GPP_E0 - GPIO */ + PAD_NC(GPP_E0, NONE), + /* GPP_E1 - GPIO */ + PAD_NC(GPP_E1, NONE), + /* GPP_E2 - GPIO */ + PAD_NC(GPP_E2, NONE), + /* GPP_E3 - GPIO */ + PAD_NC(GPP_E3, NONE), + /* GPP_E4 - GPIO */ + PAD_NC(GPP_E4, NONE), + /* GPP_E5 - SATA_LED_N */ + PAD_CFG_NF(GPP_E5, NONE, DEEP, NF1), + /* GPP_E6 - GPIO */ + PAD_NC(GPP_E6, NONE), + /* GPP_E7 - GPIO */ + PAD_NC(GPP_E7, NONE), + /* GPP_E8 - GPIO */ + PAD_NC(GPP_E8, NONE), + /* GPP_E9 - GPIO */ + PAD_NC(GPP_E9, NONE), + /* GPP_E10 - GPIO */ + PAD_NC(GPP_E10, NONE), + /* GPP_E11 - GPIO */ + PAD_NC(GPP_E11, NONE), + /* GPP_E12 - GPIO */ + PAD_NC(GPP_E12, NONE), + /* GPP_E13 - GPIO */ + PAD_NC(GPP_E13, NONE), + /* GPP_E14 - GPIO */ + PAD_NC(GPP_E14, NONE), + /* GPP_E15 - DDI1_DDC_SCL */ + PAD_CFG_NF(GPP_E15, NONE, PLTRST, NF1), + /* GPP_E16 - DDI1_DDC_SDA */ + PAD_CFG_NF(GPP_E16, NONE, PLTRST, NF1), + /* GPP_E17 - DDI2_DDC_SCL */ + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), + /* GPP_E18 - DDI2_DDC_SDA */ + PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1), + /* GPP_E19 - GPIO */ + PAD_NC(GPP_E19, NONE), + /* GPP_E20 - GPIO */ + PAD_NC(GPP_E20, NONE), + /* GPP_E21 - GPIO */ + PAD_NC(GPP_E21, NONE), + /* GPP_E22 - GPIO */ + PAD_NC(GPP_E22, NONE), + /* GPP_E23 - GPIO */ + PAD_NC(GPP_E23, NONE), + + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPD ------- */ + + /* GPD0 - BATLOW# */ + PAD_CFG_NF(GPD0, NONE, RSMRST, NF1), + /* GPD1 - PMC_ACPRESENT */ + PAD_CFG_NF(GPD1, NATIVE, RSMRST, NF1), + /* GPD2 - LAN_WAKE# */ + PAD_CFG_NF(GPD2, NATIVE, RSMRST, NF1), + /* GPD3 - PWRBTN# */ + PAD_CFG_NF(GPD3, UP_20K, RSMRST, NF1), + /* GPD4 - SLP_S3# */ + PAD_CFG_NF(GPD4, NONE, RSMRST, NF1), + /* GPD5 - SLP_S4# */ + PAD_CFG_NF(GPD5, NONE, RSMRST, NF1), + /* GPD6 - SLP_A# */ + PAD_CFG_NF(GPD6, NONE, DEEP, NF1), + /* GPD7 - GPIO */ + PAD_NC(GPD7, NONE), + /* GPD8 - SUSCLK */ + PAD_CFG_NF(GPD8, NONE, RSMRST, NF1), + /* GPD9 - SLP_WLAN# */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), + /* GPD10 - SLP_S5# */ + PAD_CFG_NF(GPD10, NONE, DEEP, NF1), + + /* ------- GPIO Community 4 ------- */ + + /* ------- GPIO Group GPP_H ------- */ + + /* GPP_H0 - GPIO */ + PAD_NC(GPP_H0, NONE), + /* GPP_H1 - GPIO */ + PAD_NC(GPP_H1, NONE), + /* GPP_H2 - GPIO */ + PAD_NC(GPP_H2,NONE), + /* GPP_H3 - GPIO */ + PAD_NC(GPP_H3, NONE), + /* GPP_H4 - GPIO */ + PAD_NC(GPP_H4, NONE), + /* GPP_H5 - GPIO */ + PAD_NC(GPP_H5, NONE), + /* GPP_H6 - GPIO */ + PAD_NC(GPP_H6, NONE), + /* GPP_H7 - GPIO */ + PAD_NC(GPP_H7, NONE), + /* GPP_H8 - GPIO */ + PAD_NC(GPP_H8, NONE), + /* GPP_H9 - GPIO */ + PAD_NC(GPP_H9, NONE), + /* GPP_H10 - GPIO */ + PAD_NC(GPP_H10, NONE), + /* GPP_H11 - GPIO */ + PAD_NC(GPP_H11,NONE), + /* GPP_H12 - GPIO */ + PAD_NC(GPP_H12,NONE), + /* GPP_H13 - GPIO */ + PAD_NC(GPP_H13,NONE), + /* GPP_H14 - GPIO */ + PAD_NC(GPP_H14,NONE), + /* GPP_H15 - GPIO */ + PAD_NC(GPP_H15, NONE), + /* GPP_H16 - GPIO */ + PAD_NC(GPP_H16,NONE), + /* GPP_H17 - GPIO */ + PAD_NC(GPP_H17, NONE), + /* GPP_H18 - GPIO */ + PAD_NC(GPP_H18,NONE), + /* GPP_H19 - GPIO */ + PAD_NC(GPP_H19,NONE), + /* GPP_H20 - GPIO */ + PAD_NC(GPP_H20, NONE), + /* GPP_H21 - GPIO */ + PAD_NC(GPP_H21, NONE), + /* GPP_H22 - GPIO */ + PAD_NC(GPP_H22, NONE), + /* GPP_H23 - GPIO */ + PAD_NC(GPP_H23, NONE), + + /* ------- GPIO Group GPP_D ------- */ + + /* GPP_D0 - GPIO */ + PAD_NC(GPP_D0, NONE), + /* GPP_D1 - GPIO */ + PAD_NC(GPP_D1, NONE), + /* GPP_D2 - GPIO */ + PAD_NC(GPP_D2, NONE), + /* GPP_D3 - GPIO */ + PAD_NC(GPP_D3, NONE), + /* GPP_D4 - GPIO */ + PAD_NC(GPP_D4, NONE), + /* GPP_D5 - GPIO */ + PAD_NC(GPP_D5, NONE), + /* GPP_D6 - GPIO */ + PAD_NC(GPP_D6, NONE), + /* GPP_D7 - GPIO */ + PAD_NC(GPP_D7, NONE), + /* GPP_D8 - GPIO */ + PAD_NC(GPP_D8, NONE), + /* GPP_D9 - GPIO */ + PAD_NC(GPP_D9, NONE), + /* GPP_D10 - GPIO */ + PAD_NC(GPP_D10, NONE), + /* GPP_D11 - GPIO */ + PAD_NC(GPP_D11, NONE), + /* GPP_D12 - GPIO */ + PAD_NC(GPP_D12, NONE), + /* GPP_D13 - GPIO */ + PAD_NC(GPP_D13, NONE), + /* GPP_D14 - GPIO */ + PAD_NC(GPP_D14, NONE), + /* GPP_D15 - GPIO */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16 - GPIO */ + PAD_NC(GPP_D16, NONE), + /* GPP_D17 - GPIO */ + PAD_NC(GPP_D17, NONE), + /* GPP_D18 - GPIO */ + PAD_NC(GPP_D18, NONE), + /* GPP_D19 - GPIO */ + PAD_NC(GPP_D19, NONE), + /* GPP_D20 - GPIO */ + PAD_NC(GPP_D20, NONE), + /* GPP_D21 - GPIO */ + PAD_NC(GPP_D21, NONE), + /* GPP_D22 - GPIO */ + PAD_NC(GPP_D22, NONE), + /* GPP_D23 - GPIO */ + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_C ------- */ + + /* GPP_C0 - GPIO */ + PAD_NC(GPP_C0, NONE), + /* GPP_C1 - GPIO */ + PAD_NC(GPP_C1, NONE), + /* GPP_C2 - GPIO */ + PAD_NC(GPP_C2, NONE), + /* GPP_C3 - GPIO */ + PAD_NC(GPP_C3, NONE), + /* GPP_C4 - GPIO */ + PAD_NC(GPP_C4, NONE), + /* GPP_C5 - GPIO */ + PAD_NC(GPP_C5, NONE), + /* GPP_C6 - M2_PEDET (NVME=1, SATA=0) */ + PAD_CFG_GPI(GPP_C6, UP_20K, DEEP), + /* GPP_C7 - GPIO */ + PAD_NC(GPP_C7, NONE), + /* GPP_C8 - GPIO */ + PAD_NC(GPP_C8, NONE), + /* GPP_C9 - GPIO */ + PAD_NC(GPP_C9, NONE), + /* GPP_C10 - GPIO */ + PAD_NC(GPP_C10, NONE), + /* GPP_C11 - GPIO */ + PAD_NC(GPP_C11, NONE), + /* GPP_C12 - GPIO */ + PAD_NC(GPP_C12, NONE), + /* GPP_C13 - GPIO */ + PAD_NC(GPP_C13, NONE), + /* GPP_C14 - GPIO */ + PAD_NC(GPP_C14, NONE), + /* GPP_C15 - GPIO */ + PAD_NC(GPP_C15, NONE), + /* GPP_C16 - GPIO */ + PAD_NC(GPP_C16, NONE), + /* GPP_C17 - GPIO */ + PAD_NC(GPP_C17, NONE), + /* GPP_C18 - GPIO */ + PAD_NC(GPP_C18, NONE), + /* GPP_C19 - GPIO */ + PAD_NC(GPP_C19, NONE), + /* GPP_C20 - GPIO */ + PAD_NC(GPP_C20, NONE), + /* GPP_C21 - GPIO */ + PAD_NC(GPP_C21, NONE), + /* GPP_C22 - GPIO */ + PAD_NC(GPP_C22, NONE), + /* GPP_C23 - GPIO */ + PAD_NC(GPP_C23, NONE), + + /* ------- GPIO Community 5 ------- */ + + /* ------- GPIO Group GPP_F ------- */ + + /* GPP_F0 - GPIO */ + PAD_NC(GPP_F0, NONE), + /* GPP_F1 - GPIO */ + PAD_NC(GPP_F1, NONE), + /* GPP_F2 - GPIO */ + PAD_NC(GPP_F2, NONE), + /* GPP_F3 - GPIO */ + PAD_NC(GPP_F3, NONE), + /* GPP_F4 - GPIO */ + PAD_NC(GPP_F4, NONE), + /* GPP_F5 - GPIO */ + PAD_NC(GPP_F5, NONE), + /* GPP_F6 - GPIO */ + PAD_NC(GPP_F6, NONE), + /* GPP_F7 - EMMC_CMD */ + PAD_CFG_NF(GPP_F7, NONE, DEEP, NF1), + /* GPP_F8 - EMMC_DATA0 */ + PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), + /* GPP_F9 - EMMC_DATA1 */ + PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), + /* GPP_F10 - EMMC_DATA2 */ + PAD_CFG_NF(GPP_F10, NONE, DEEP, NF1), + /* GPP_F11 - EMMC_DATA3 */ + PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1), + /* GPP_F12 - EMMC_DATA4 */ + PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1), + /* GPP_F13 - EMMC_DATA5 */ + PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1), + /* GPP_F14 - EMMC_DATA6 */ + PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1), + /* GPP_F15 - EMMC_DATA7 */ + PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1), + /* GPP_F16 - EMMC_RCLK */ + PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1), + /* GPP_F17 - EMMC_CLK */ + PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1), + /* GPP_F18 - EMMC_RESET_N */ + PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), + /* GPP_F19 - GPIO */ + PAD_NC(GPP_F19, NONE), + + /* ------- GPIO Group GPP_B ------- */ + + /* GPP_B0 - PMC_CORE_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* GPP_B1 - PMC_CORE_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* GPP_B2 - GPIO */ + PAD_NC(GPP_B2, NONE), + /* GPP_B3 - GPIO */ + PAD_NC(GPP_B3, NONE), + /* GPP_B4 - GPIO */ + PAD_NC(GPP_B4, NONE), + /* GPP_B5 - GPIO */ + PAD_NC(GPP_B5, NONE), + /* GPP_B6 - GPIO */ + PAD_NC(GPP_B6, NONE), + /* GPP_B7 - GPIO */ + PAD_NC(GPP_B7, NONE), + /* GPP_B8 - GPIO */ + PAD_NC(GPP_B8, NONE), + /* GPP_B9 - GPIO */ + PAD_NC(GPP_B9, NONE), + /* GPP_B10 - GPIO */ + PAD_NC(GPP_B10, NONE), + /* GPP_B11 - GPIO */ + PAD_NC(GPP_B11, NONE), + /* GPP_B12 - PMC_SLP_S_N */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* GPP_B13 - PMC_PLTRST_N */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), + /* GPP_B14 - SPKR */ + PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), + /* GPP_B15 - GPIO */ + PAD_NC(GPP_B15, NONE), + /* GPP_B16 - GPIO */ + PAD_NC(GPP_B16, NONE), + /* GPP_B17 - GPIO */ + PAD_NC(GPP_B17, NONE), + /* GPP_B18 - GPIO */ + PAD_NC(GPP_B18, NONE), + /* GPP_B19 - GPIO */ + PAD_NC(GPP_B19, NONE), + /* GPP_B20 - GPIO */ + PAD_NC(GPP_B20, NONE), + /* GPP_B21 - GPIO */ + PAD_NC(GPP_B21, NONE), + /* GPP_B22 - GPIO */ + PAD_NC(GPP_B22, NONE), + /* GPP_B23 - DDI2_HPD */ + PAD_CFG_NF(GPP_B23, NONE, PLTRST, NF1), + + /* ------- GPIO Group GPP_A ------- */ + + /* GPP_A0 - ESPI_IO_0 */ + PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), + /* GPP_A1 - ESPI_IO_1 */ + PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), + /* GPP_A2 - ESPI_IO_2 */ + PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), + /* GPP_A3 - ESPI_IO_3 */ + PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), + /* GPP_A4 - ESPI_CS_N */ + PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), + /* GPP_A5 - ESPI_CLK */ + PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), + /* GPP_A6 - ESPI_RESET_N */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + /* GPP_A7 - SMB_CLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* GPP_A8 - SMB_DATA */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* GPP_A9 - GPIO */ + PAD_NC(GPP_A9, NONE), + /* GPP_A10 - GPIO */ + PAD_NC(GPP_A10, NONE), + /* GPP_A11 - GPIO */ + PAD_NC(GPP_A11, NONE), + /* GPP_A12 - GPIO */ + PAD_NC(GPP_A12, NONE), + /* GPP_A13 - GPIO */ + PAD_NC(GPP_A13, NONE), + /* GPP_A14 - GPIO */ + PAD_NC(GPP_A14, NONE), + /* GPP_A15 - GPIO */ + PAD_NC(GPP_A15, NONE), + /* GPP_A16 - DDI1_HPD */ + PAD_CFG_NF(GPP_A16, NONE, PLTRST, NF1), + /* GPP_A17 - DDI0_HPD */ + PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1), + /* GPP_A18 - GPIO */ + PAD_NC(GPP_A18, NONE), + /* GPP_A19 - GPIO */ + PAD_NC(GPP_A19, NONE), + + /* ------- GPIO Group GPP_S ------- */ + + /* GPP_S0 - GPIO */ + PAD_NC(GPP_S0, NONE), + /* GPP_S1 - GPIO */ + PAD_NC(GPP_S1, NONE), + /* GPP_S2 - GPIO */ + PAD_NC(GPP_S2, NONE), + /* GPP_S3 - GPIO */ + PAD_NC(GPP_S3, NONE), + /* GPP_S4 - GPIO */ + PAD_NC(GPP_S4, NONE), + /* GPP_S5 - GPIO */ + PAD_NC(GPP_S5, NONE), + /* GPP_S6 - GPIO */ + PAD_NC(GPP_S6, NONE), + /* GPP_S7 - GPIO */ + PAD_NC(GPP_S7, NONE), + + /* ------- GPIO Group GPP_R ------- */ + + /* GPP_R0 - HDA_BCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* GPP_R1 - HDA_SYNC */ + PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), + /* GPP_R2 - HDA_SDO */ + PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), + /* GPP_R3 - HDA_SDI0 */ + PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), + /* GPP_R4 - HDA_RST_N */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* GPP_R5 - GPIO */ + PAD_NC(GPP_R5, NONE), + /* GPP_R6 - GPIO */ + PAD_NC(GPP_R6, NONE), + /* GPP_R7 - GPIO */ + PAD_NC(GPP_R7, NONE), +}; + +#endif /* CFG_GPIO_H */ diff --git a/src/mainboard/protectli/vault_jsl/hda_verb.c b/src/mainboard/protectli/vault_jsl/hda_verb.c new file mode 100644 index 00000000000..f23e38dd03a --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/hda_verb.c @@ -0,0 +1,20 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + /* JasperLake HDMI */ + 0x8086281a, /* Vendor ID */ + 0x80860101, /* Subsystem ID */ + 6, /* Number of entries */ + AZALIA_SUBVENDOR(2, 0x80860101), + AZALIA_PIN_CFG(2, 0x04, 0x18560010), + AZALIA_PIN_CFG(2, 0x06, 0x18560010), + AZALIA_PIN_CFG(2, 0x08, 0x18560010), + AZALIA_PIN_CFG(2, 0x0a, 0x18560010), + AZALIA_PIN_CFG(2, 0x0b, 0x18560010) +}; + +const u32 pc_beep_verbs[] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/protectli/vault_jsl/mainboard.c b/src/mainboard/protectli/vault_jsl/mainboard.c new file mode 100644 index 00000000000..1baf829e434 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/mainboard.c @@ -0,0 +1,150 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define IFD_FIA_COMBO_PORT0 0x189 +#define FIA_PCIE 5 +#define FIA_SATA 7 + +/* Flash Master 1 : HOST/BIOS */ +#define FLMSTR1 0x80 +/* Flash signature Offset */ +#define FLASH_SIGN_OFFSET 0x10 +#define FLMSTR_WR_SHIFT_V2 20 +#define FLASH_VAL_SIGN 0xFF0A55A +#define SI_DESC_SIZE 0x1000 +#define SI_DESC_REGION "SI_DESC" + +/* It checks whether host (Flash Master 1) has write access to the Descriptor Region or not */ +static bool is_descriptor_writeable(uint8_t *desc) +{ + /* Check flash has valid signature */ + if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { + printk(BIOS_ERR, "Flash Descriptor is not valid\n"); + return 0; + } + /* Check host has write access to the Descriptor Region */ + if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); + return 0; + } + return 1; +} + +static void descriptor_patch_pcie8_lane(int is_nvme) +{ + uint8_t *si_desc_buf; + struct region_device desc_rdev; + uint8_t state = is_nvme ? FIA_PCIE : FIA_SATA; + + si_desc_buf = (uint8_t *)malloc(SI_DESC_SIZE); + + if (!si_desc_buf) { + printk(BIOS_ERR, "Failed to allocate buffer for %s\n", SI_DESC_REGION); + return; + } + + if (fmap_locate_area_as_rdev_rw(SI_DESC_REGION, &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + free(si_desc_buf); + return; + } + if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + free(si_desc_buf); + return; + } + if (!is_descriptor_writeable(si_desc_buf)) { + free(si_desc_buf); + return; + } + + /* + * Offset 0x189 bits [0:3]: 5=PCIe, 7=SATA. + * Not patching the descriptor will result in SATA or NVMe not working. + */ + if ((si_desc_buf[IFD_FIA_COMBO_PORT0] & 0xf) == state) { + printk(BIOS_DEBUG, "Update of Descriptor is not required!\n"); + free(si_desc_buf); + return; + } + + si_desc_buf[IFD_FIA_COMBO_PORT0] &= 0xf0; + si_desc_buf[IFD_FIA_COMBO_PORT0] |= state; + + /* FIT als sets reserved offset 0x1a4 bits [0:3]: 5=PCIe, 1=SATA */ + if (state == FIA_PCIE) { + si_desc_buf[0x1a4] &= 0xf0; + si_desc_buf[0x1a4] |= 5; + } else { + si_desc_buf[0x1a4] &= 0xf0; + si_desc_buf[0x1a4] |= 1; + } + + if (rdev_eraseat(&desc_rdev, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); + free(si_desc_buf); + return; + } + + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to update Descriptor Region\n"); + free(si_desc_buf); + return; + } + + printk(BIOS_DEBUG, "Update of Descriptor successful\n"); + free(si_desc_buf); + do_global_reset(); +} + +void mainboard_silicon_init_params(FSP_S_CONFIG *params) +{ + params->UsbPdoProgramming = 0; + + for (uint8_t i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + params->PcieRpAcsEnabled[i] = 1; + params->PcieRpAdvancedErrorReporting[i] = 1; + params->PcieRpLtrEnable[i] = 1; + params->PcieRpMaxPayload[i] = 1; // 256B + params->PcieRpSlotImplemented[i] = 1; + } + + if (CONFIG(BOARD_PROTECTLI_V1610)) { + /* Read GPP_C6 (M2_PEDET) to check for disk type: 1=NVME, 0=SATA */ + gpio_input_pullup(GPP_C6); + /* + * Patch the descriptor accordingly, by default the lanes 7 and 8 + * are in 1x2 mode. Lane 8 can be statically assigned to either + * PCIe or SATA + */ + descriptor_patch_pcie8_lane(gpio_get(GPP_C6)); + } + + /* + * HWP is too aggressive in power savings and does not let using full + * bandwidth of Ethernet controllers without additional stressing of + * the CPUs (2Gb/s vs 2.35Gb/s with stressing, measured with iperf3). + * Let the Linux use acpi-cpufreq governor driver instead of + * intel_pstate by disabling HWP. + */ + params->Hwp = 0; +} + +static void mainboard_final(void *unused) +{ + if (CONFIG(BEEP_ON_BOOT)) + beep(1500, 100); +} + +struct chip_operations mainboard_ops = { + .final = mainboard_final, +}; diff --git a/src/mainboard/protectli/vault_jsl/override_v12xx.cb b/src/mainboard/protectli/vault_jsl/override_v12xx.cb new file mode 100644 index 00000000000..538daf3ab5f --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/override_v12xx.cb @@ -0,0 +1,19 @@ +chip soc/intel/jasperlake + device domain 0 on + # Using x2 link on PCIe 5/6 to avoid switching to SATA + device pci 1c.0 on # PCI Express Root Port 1 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (NVMe)" "SlotDataBusWidth2X" + end + device pci 1c.1 off end # PCI Express Root Port 2 + device pci 1c.2 off end # PCI Express Root Port 3 + device pci 1c.3 off end # PCI Express Root Port 4 + device pci 1c.4 on # PCI Express Root Port 5 + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (WIFI)" "SlotDataBusWidth1X" + end + device pci 1c.5 on end # PCI Express Root Port 6 (LAN1) + device pci 1c.6 on end # PCI Express Root Port 7 (LAN2) + device pci 1c.7 off end # PCI Express Root Port 8 + end +end diff --git a/src/mainboard/protectli/vault_jsl/override_v1410.cb b/src/mainboard/protectli/vault_jsl/override_v1410.cb new file mode 100644 index 00000000000..a5ac9e7cfa0 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/override_v1410.cb @@ -0,0 +1,20 @@ +chip soc/intel/jasperlake + device domain 0 on + device pci 1c.0 on end # PCI Express Root Port 1 (LAN1) + device pci 1c.1 on end # PCI Express Root Port 2 (LAN2) + # NVMe x1 link, making it x2 link with lane reversal + # would mess up the LAN port order + device pci 1c.2 on # PCI Express Root Port 3 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (NVMe)" "SlotDataBusWidth1X" + end + device pci 1c.3 off end # PCI Express Root Port 4 + device pci 1c.4 on # PCI Express Root Port 5 + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (WIFI)" "SlotDataBusWidth1X" + end + device pci 1c.5 on end # PCI Express Root Port 6 (LAN3) + device pci 1c.6 on end # PCI Express Root Port 7 (LAN4) + device pci 1c.7 off end # PCI Express Root Port 8 + end +end diff --git a/src/mainboard/protectli/vault_jsl/override_v1610.cb b/src/mainboard/protectli/vault_jsl/override_v1610.cb new file mode 100644 index 00000000000..6f576053f32 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/override_v1610.cb @@ -0,0 +1,20 @@ +chip soc/intel/jasperlake + device domain 0 on + # ASMedia PCIe switch with x2 link to 4x1 ports (3 LANs and WiFi) + device pci 1c.0 on end # PCI Express Root Port 1 + device pci 1c.1 off end # PCI Express Root Port 2 + # NVMe with x2 link, lane 8 switchable to SATA + device pci 1c.2 on # PCI Express Root Port 3 + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" + "M.2/M 2280 (NVMe)" "SlotDataBusWidth2X" + end + device pci 1c.3 off end # PCI Express Root Port 4 + device pci 1c.4 on # PCI Express Root Port 5 + smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" + "M.2/E 2230 (WIFI)" "SlotDataBusWidth1X" + end + device pci 1c.5 on end # PCI Express Root Port 6 (LAN3) + device pci 1c.6 on end # PCI Express Root Port 7 (LAN4) + device pci 1c.7 off end # PCI Express Root Port 8 + end +end diff --git a/src/mainboard/protectli/vault_jsl/romstage.c b/src/mainboard/protectli/vault_jsl/romstage.c new file mode 100644 index 00000000000..c27610d836c --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/romstage.c @@ -0,0 +1,67 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +#include "gpio.h" + +static const struct mb_cfg memcfg_cfg = { + + /* Static array from the worksheet */ + .dq_map[DDR_CH0] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + .dq_map[DDR_CH1] = { + {0xf, 0xf0}, + {0xf, 0xf0}, + {0xff, 0x0}, + {0x0, 0x0}, + {0x0, 0x0}, + {0x0, 0x0} + }, + + /* Copied from the worksheet after filling DQS map */ + .dqs_map[DDR_CH0] = {0, 1, 2, 3, 4, 5, 6, 7}, + .dqs_map[DDR_CH1] = {0, 1, 2, 3, 4, 5, 6, 7}, + + /* Copied from the worksheet for JSL LPDDR4X */ + .rcomp_resistor = {100, 100, 100}, + .rcomp_targets = {60, 40, 30, 20, 30}, + + /* Enable Early Command Training */ + .ect = 1, + + /* User Board Type */ + .UserBd = BOARD_TYPE_ULT_ULX, +}; + +static int get_spd_index(void) +{ + return (CONFIG(BOARD_PROTECTLI_V1410) || CONFIG(BOARD_PROTECTLI_V1610)); +} + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + const struct spd_info board_spd_info = { + .read_type = READ_SPD_CBFS, + .spd_spec.spd_index = get_spd_index(), + }; + + memcfg_init(&memupd->FspmConfig, &memcfg_cfg, &board_spd_info, false); + + /* + * V1210 and V1410 populate only channel 1. + * V1211 and V1610 populate both channels. + */ + if (CONFIG(BOARD_PROTECTLI_V1210) || CONFIG(BOARD_PROTECTLI_V1410)) + memupd->FspmConfig.MemorySpdPtr00 = 0; + + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/protectli/vault_jsl/spd/MT53D512M64D4RQ-046.spd.hex b/src/mainboard/protectli/vault_jsl/spd/MT53D512M64D4RQ-046.spd.hex new file mode 100644 index 00000000000..303192f84a6 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/spd/MT53D512M64D4RQ-046.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 15 21 90 08 00 40 00 00 02 22 00 00 +00 00 04 0F 92 54 05 00 87 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 A7 77 46 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 4D 54 35 33 44 35 31 +32 4D 36 34 44 34 52 51 2D 30 34 36 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 \ No newline at end of file diff --git a/src/mainboard/protectli/vault_jsl/spd/MT53E1G32D2NP-046.spd.hex b/src/mainboard/protectli/vault_jsl/spd/MT53E1G32D2NP-046.spd.hex new file mode 100644 index 00000000000..ab961ca9aa2 --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/spd/MT53E1G32D2NP-046.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 16 21 90 08 00 40 00 00 02 22 00 00 +00 00 05 0F 92 54 01 00 8a 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 a7 77 46 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 4D 54 35 33 44 35 31 +32 4D 36 34 44 34 52 51 2D 30 34 36 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/protectli/vault_jsl/spd/MT53E512M32D4NQ-053.spd.hex b/src/mainboard/protectli/vault_jsl/spd/MT53E512M32D4NQ-053.spd.hex new file mode 100644 index 00000000000..82617e0759b --- /dev/null +++ b/src/mainboard/protectli/vault_jsl/spd/MT53E512M32D4NQ-053.spd.hex @@ -0,0 +1,32 @@ +23 11 11 0E 14 21 B0 08 00 40 00 00 0A 22 00 00 +00 00 05 0F 92 54 01 00 8a 00 90 A8 90 C0 08 60 +04 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 92 00 a7 77 46 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 20 00 00 00 4D 54 35 33 44 35 31 +32 4D 36 34 44 34 52 51 2D 30 34 36 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/protectli/vault_kbl/Kconfig b/src/mainboard/protectli/vault_kbl/Kconfig index 10f8c400b71..23229d386df 100644 --- a/src/mainboard/protectli/vault_kbl/Kconfig +++ b/src/mainboard/protectli/vault_kbl/Kconfig @@ -47,4 +47,11 @@ config CBFS_SIZE config USE_PM_ACPI_TIMER default n +if PAYLOAD_EDK2 + +config EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT + default 5 + +endif + endif diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index 55074435abd..465d72acf78 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -551,6 +551,11 @@ static void fam16_finalize(void *chip_info) if (dev != NULL) { pci_and_config32(dev, 0x60, ~(1 << 11)); } + + /* Enable access to PSP MMIO BARs. This is needed for CCP. */ + dev = pcidev_on_root(8, 0); + if (dev != NULL) + pci_update_config8(dev, 0x48, 0xff, 0x3d); } struct hw_mem_hole_info { @@ -660,9 +665,9 @@ struct device_operations amd_fam16_mod30_pci_domain_ops = { void mp_init_cpus(struct bus *cpu_bus) { - extern const struct mp_ops amd_mp_ops_no_smm; + extern const struct mp_ops amd_mp_ops_with_smm; /* TODO: Handle mp_init_with_smm failure? */ - mp_init_with_smm(cpu_bus, &amd_mp_ops_no_smm); + mp_init_with_smm(cpu_bus, &amd_mp_ops_with_smm); /* The flash is now no longer cacheable. Reset to WP for performance. */ mtrr_use_temp_range(OPTIMAL_CACHE_ROM_BASE, OPTIMAL_CACHE_ROM_SIZE, diff --git a/src/northbridge/amd/pi/00730F01/state_machine.c b/src/northbridge/amd/pi/00730F01/state_machine.c index a05e9e04e81..38ed0916fce 100644 --- a/src/northbridge/amd/pi/00730F01/state_machine.c +++ b/src/northbridge/amd/pi/00730F01/state_machine.c @@ -10,6 +10,7 @@ #include #include #include +#include void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) { @@ -18,6 +19,9 @@ void platform_BeforeInitReset(struct sysinfo *cb, AMD_RESET_PARAMS *Reset) void platform_BeforeInitEarly(struct sysinfo *cb, AMD_EARLY_PARAMS *Early) { Early->GnbConfig.PsppPolicy = PsppDisabled; + + /* Init Reset reconfigures ROM address registers */ + hudson_enable_lpc_rom(); } void platform_BeforeInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) @@ -33,9 +37,9 @@ void platform_AfterInitPost(struct sysinfo *cb, AMD_POST_PARAMS *Post) * UMA may or may not be cacheable, so Sub4GCacheTop could be * higher than UmaBase. With UMA_NONE we see UmaBase==0. */ if (Post->MemConfig.UmaBase) - backup_top_of_low_cacheable(Post->MemConfig.UmaBase << 16); + backup_top_of_low_cacheable((Post->MemConfig.UmaBase << 16) - CONFIG_SMM_TSEG_SIZE); else - backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop); + backup_top_of_low_cacheable(Post->MemConfig.Sub4GCacheTop - CONFIG_SMM_TSEG_SIZE); } void platform_BeforeInitEnv(struct sysinfo *cb, AMD_ENV_PARAMS *Env) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 973eed8bbd4..42c61e5940e 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -8,6 +8,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE select INTEL_GMA_ACPI select NEED_SMALL_2MB_PAGE_TABLES select USE_DDR3 + select UDK_2017_BINDING if NORTHBRIDGE_INTEL_SANDYBRIDGE diff --git a/src/northbridge/intel/sandybridge/acpi/peg.asl b/src/northbridge/intel/sandybridge/acpi/peg.asl index 65b71d1cc34..e99053342d2 100644 --- a/src/northbridge/intel/sandybridge/acpi/peg.asl +++ b/src/northbridge/intel/sandybridge/acpi/peg.asl @@ -12,12 +12,15 @@ Device (PEGP) Device (DEV0) { Name(_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } Method (_PRT) { Return (\_SB.PCI0.IRQM (1)) } + + Name (_PRW, Package() { 9, 4 }) } Device (PEG1) @@ -32,12 +35,15 @@ Device (PEG1) Device (DEV0) { Name(_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } Method (_PRT) { Return (\_SB.PCI0.IRQM (2)) } + + Name (_PRW, Package() { 9, 4 }) } Device (PEG2) @@ -52,12 +58,15 @@ Device (PEG2) Device (DEV0) { Name(_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } Method (_PRT) { Return (\_SB.PCI0.IRQM (3)) } + + Name (_PRW, Package() { 9, 4 }) } Device (PEG6) @@ -72,10 +81,13 @@ Device (PEG6) Device (DEV0) { Name(_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } Method (_PRT) { Return (\_SB.PCI0.IRQM (4)) } + + Name (_PRW, Package() { 9, 4 }) } diff --git a/src/security/intel/cbnt/cbnt.h b/src/security/intel/cbnt/cbnt.h index 08011f59655..e318387229c 100644 --- a/src/security/intel/cbnt/cbnt.h +++ b/src/security/intel/cbnt/cbnt.h @@ -10,6 +10,7 @@ #define CBNT_ERRORCODE (CBNT_BASE_ADDRESS + 0x30) #define CBNT_BOOTSTATUS (CBNT_BASE_ADDRESS + 0xa0) #define CBNT_BIOSACM_ERRORCODE (CBNT_BASE_ADDRESS + 0x328) +#define CBNT_BIOSACM_POLICY_STS (CBNT_BASE_ADDRESS + 0x378) void intel_cbnt_log_registers(void); diff --git a/src/security/intel/cbnt/logging.c b/src/security/intel/cbnt/logging.c index 90d138d7c24..6225e4de755 100644 --- a/src/security/intel/cbnt/logging.c +++ b/src/security/intel/cbnt/logging.c @@ -23,8 +23,9 @@ union sacm_info { uint64_t : 24; uint64_t btg_cap : 1; uint64_t : 1; - uint64_t txt_cap : 1; - uint64_t : 29; + uint64_t txt_server_cap : 1; + uint64_t no_rst_secrets_prot : 1; + uint64_t : 28; }; msr_t msr; uint64_t raw; @@ -41,12 +42,20 @@ static const char *const tpm_type[] = { union cbnt_bootstatus { struct { - uint64_t : 59; + uint64_t : 30; + uint64_t txt_startup_success : 1; + uint64_t btg_startup_success : 1; + uint64_t block_boot_en : 1; + uint64_t pfr_startup_success : 1; + uint64_t : 13; + uint64_t mem_pwr_down : 1; + uint64_t btg_failed : 1; + uint64_t : 10; uint64_t bios_trusted : 1; uint64_t txt_dis_pol : 1; uint64_t btg_startup_err : 1; uint64_t txt_err : 1; - uint64_t type7 : 1; + uint64_t sacm_success : 1; }; uint64_t raw; }; @@ -102,6 +111,29 @@ union cbnt_biosacm_errorcode { _Static_assert(sizeof(union cbnt_biosacm_errorcode) == sizeof(uint32_t), "Wrong size of cbnt_biosacm_errorcode"); +union cbnt_biosacm_policy { + struct { + uint64_t km_id : 4; + uint64_t bp : 9; + uint64_t tpm_type : 2; + uint64_t tpm_success : 1; + uint64_t : 1; + uint64_t pfr : 1; + uint64_t bckup_act : 2; + uint64_t txt_profile : 5; + uint64_t scrub_policy : 2; + uint64_t : 2; + uint64_t dma_protection : 1; + uint64_t : 2; + uint64_t scrtm_status : 3; + uint64_t cpu_co_signing : 1; + uint64_t tpm_startup_locality : 1; + uint64_t : 27; + } status; + uint64_t raw; +}; +_Static_assert(sizeof(union cbnt_biosacm_policy) == sizeof(uint64_t), + "Wrong size of cbnt_biosacm_policy"); static const char *decode_err_type(uint8_t type) { @@ -117,6 +149,36 @@ static const char *decode_err_type(uint8_t type) } } +static const char* backup_actions[] = { + "Memory Power Down", + "BtG Unbreakable Shutdown", + "PFR Recovery", + "Reserved", +}; + +static const char* scrub_policies[] = { + "Default - trust valid BIOS to scrub memory", + "BIOS action to scrub memory.", + "ACM action to scrub memory", + "Reserved", +}; + +static const char *decode_scrtm_status(uint8_t status) +{ + switch (status) { + case 0: + return "None"; + case 1: + return "Boot Guard established"; + case 2: + return "TXT established"; + case 4: + return "PFR established"; + default: + return "Reserved"; + } +} + void intel_cbnt_log_registers(void) { const union sacm_info acm_info = { .msr = rdmsr(MSR_BOOT_GUARD_SACM_INFO) }; @@ -129,17 +191,24 @@ void intel_cbnt_log_registers(void) LOG(" verified boot: %u\n", acm_info.verified_boot); LOG(" revoked: %u\n", acm_info.revoked); LOG(" BtG capable: %u\n", acm_info.btg_cap); - LOG(" TXT capable: %u\n", acm_info.txt_cap); + LOG(" Server TXT capable: %u\n", acm_info.txt_server_cap); + LOG(" RST Secrets Protection: %s\n", acm_info.no_rst_secrets_prot? "no" : "yes"); const union cbnt_bootstatus btsts = { .raw = read64p(CBNT_BOOTSTATUS), }; LOG("BOOTSTATUS (0xA0) raw: 0x%016llx\n", btsts.raw); + LOG(" TXT startup success: %u\n", btsts.bios_trusted); + LOG(" BtG startup success: %u\n", btsts.bios_trusted); + LOG(" Block boot: %s\n", btsts.block_boot_en ? "enabled" : "disabled"); + LOG(" PFR startup success: %u\n", btsts.bios_trusted); + LOG(" Memory power down: %sexecuted\n", btsts.mem_pwr_down ? "" : "not "); + LOG(" BtG failed: %s\n", btsts.btg_failed ? "yes" : "no"); LOG(" Bios trusted: %u\n", btsts.bios_trusted); LOG(" TXT disabled by policy: %u\n", btsts.txt_dis_pol); - LOG(" Bootguard startup error: %u\n", btsts.btg_startup_err); + LOG(" BtG startup error: %u\n", btsts.btg_startup_err); LOG(" TXT ucode or ACM error: %u\n", btsts.txt_err); - LOG(" TXT measurement type 7: %u\n", btsts.type7); + LOG(" S-ACM success: %s\n", btsts.sacm_success ? "yes" : "no"); const union cbnt_errorcode err = { .raw = read32p(CBNT_ERRORCODE), @@ -190,4 +259,37 @@ void intel_cbnt_log_registers(void) LOG(" KMID: 0x%x\n", biosacm_err.btg.km_id); LOG(" BootPolicies: 0x%x\n", biosacm_err.btg.bp); } + + const union cbnt_biosacm_policy biosacm_sts = { + .raw = read64p(CBNT_BIOSACM_POLICY_STS), + }; + + LOG("CBNT_BIOSACM_POLICY_STS (0x378) raw: 0x%016llx\n", biosacm_sts.raw); + LOG(" KMID: 0x%x\n", biosacm_sts.status.km_id); + LOG(" Boot policies : 0x%x\n", biosacm_sts.status.bp); + LOG(" TPM type: %s\n", tpm_type[biosacm_sts.status.tpm_type]); + LOG(" TPM success: %s\n", biosacm_sts.status.tpm_success ? "yes" : "no"); + LOG(" PFR supported: %s\n", biosacm_sts.status.pfr ? "yes" : "no"); + LOG(" Backup action: %s\n", backup_actions[biosacm_sts.status.bckup_act]); + + if (biosacm_sts.status.txt_profile == 1) + LOG(" TXT Profile: " + "B - BIOS is trusted to create alias-free memory topology\n"); + else if (biosacm_sts.status.txt_profile == 2) + LOG(" TXT Profile: " + "D - BIOS runs ACHECK to verify alias-free topology\n"); + else + LOG(" TXT Profile: Unknown\n"); + + LOG(" Memory scrubbing policy: %s\n", scrub_policies[biosacm_sts.status.scrub_policy]); + LOG(" IBB DMA protection: %s\n", biosacm_sts.status.dma_protection ? + "enabled" : "disabled"); + LOG(" S-CRTM status: %s\n", + decode_scrtm_status(biosacm_sts.status.scrtm_status)); + LOG(" CPU Co-signing: %s\n", biosacm_sts.status.cpu_co_signing ? + "enabled" : "disabled"); + LOG(" TPM Startup locality: %d\n", + biosacm_sts.status.tpm_startup_locality ? 3 : 0); + + } diff --git a/src/security/intel/txt/Kconfig b/src/security/intel/txt/Kconfig index 637a6a787b0..69ba95ae0bc 100644 --- a/src/security/intel/txt/Kconfig +++ b/src/security/intel/txt/Kconfig @@ -16,6 +16,7 @@ config INTEL_TXT select ENABLE_VMX if CPU_INTEL_COMMON select AP_IN_SIPI_WAIT select TPM_MEASURED_BOOT_INIT_BOOTBLOCK if TPM_MEASURED_BOOT + select TPM_STARTUP_IGNORE_POSTINIT depends on TPM depends on PLATFORM_HAS_DRAM_CLEAR depends on (SOC_INTEL_COMMON_BLOCK_SA || HAVE_CF9_RESET) diff --git a/src/security/intel/txt/common.c b/src/security/intel/txt/common.c index 6fba95850a8..72bfea2d046 100644 --- a/src/security/intel/txt/common.c +++ b/src/security/intel/txt/common.c @@ -11,6 +11,7 @@ #include #include #include +#include #if CONFIG(SOC_INTEL_COMMON_BLOCK_SA) #include @@ -214,7 +215,7 @@ static int validate_acm(const void *ptr) struct acm_info_table *info = find_info_table(ptr); if (!info) return ACM_E_NO_INFO_TABLE; - if (info->chipset_acm_type != BIOS) + if (info->chipset_acm_type != BIOS_ACM) return ACM_E_NOT_BIOS_ACM; static const u8 acm_uuid[] = { @@ -385,6 +386,92 @@ static bool check_precondition(const int cond) return !cond; } +#if CONFIG(TPM2) +#define TXT_TPM2_AUX_INDEX (0x1c10102 - NV_INDEX_FIRST) +#define TXT_TPM2_PS_INDEX (0x1c10103 - NV_INDEX_FIRST) + +static const TPMA_NV txt_tpm2_aux_index_attributes = { + .TPMA_NV_POLICYWRITE = 1, + .TPMA_NV_POLICY_DELETE = 1, + .TPMA_NV_WRITE_STCLEAR = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_NO_DA = 1, + .TPMA_NV_PLATFORMCREATE = 1, +}; + +static const uint8_t txt_tpm2_aux_index_policy[VB2_SHA256_DIGEST_SIZE] = { + 0xef, 0x9a, 0x26, 0xfc, 0x22, 0xd1, 0xae, 0x8c, 0xec, 0xff, 0x59, 0xe9, + 0x48, 0x1a, 0xc1, 0xec, 0x53, 0x3d, 0xbe, 0x22, 0x8b, 0xec, 0x6d, 0x17, + 0x93, 0x0f, 0x4c, 0xb2, 0xcc, 0x5b, 0x97, 0x24 +}; + +static const TPMA_NV txt_tpm2_ps_index_attributes = { + .TPMA_NV_POLICYWRITE = 1, + .TPMA_NV_POLICY_DELETE = 1, + .TPMA_NV_AUTHREAD = 1, + .TPMA_NV_NO_DA = 1, + .TPMA_NV_PLATFORMCREATE = 1, +}; + +/* Returns true if TPM indices are not in good condition. */ +static bool check_tpm2_indices(void) +{ + struct nv_read_public_response nvrp_resp; + + if (tlcl2_nv_read_public(TXT_TPM2_AUX_INDEX, &nvrp_resp) != TPM_SUCCESS) { + printk(BIOS_ERR, "TEE-TXT: Failed to read public data of TPM2 AUX index\n"); + return true; + } + + /* The index could have been written already, but we don't care. */ + nvrp_resp.nvPublic.t.nvPublic.attributes.TPMA_NV_WRITTEN = 0; + + if (memcmp(&nvrp_resp.nvPublic.t.nvPublic.attributes, &txt_tpm2_aux_index_attributes, + sizeof(TPMA_NV))) { + printk(BIOS_ERR, "TEE-TXT: Incorrect TPM2 AUX index attributes\n"); + return true; + } + + /* FIXME: Support other algorithms */ + if (nvrp_resp.nvPublic.t.nvPublic.nameAlg != TPM_ALG_SHA256) { + printk(BIOS_ERR, "TEE-TXT: Unsupported TPM2 AUX index auth hash algo (%02x)\n", + nvrp_resp.nvPublic.t.nvPublic.nameAlg); + return true; + } + + if (memcmp(nvrp_resp.nvPublic.t.nvPublic.authPolicy.t.buffer, + &txt_tpm2_aux_index_policy, + nvrp_resp.nvPublic.t.nvPublic.authPolicy.t.size)) { + printk(BIOS_ERR, "TEE-TXT: Incorrect TPM2 AUX index policy\n"); + return true; + } + + /* CBnT does not need PS/PO index */ + if (CONFIG(INTEL_CBNT_SUPPORT)) + return false; + + if (tlcl2_nv_read_public(TXT_TPM2_PS_INDEX, &nvrp_resp) != TPM_SUCCESS) { + printk(BIOS_ERR, "TEE-TXT: Failed to read public data of TPM2 PS/PO index\n"); + return true; + } + + /* The index could have been written already, but we don't care. */ + nvrp_resp.nvPublic.t.nvPublic.attributes.TPMA_NV_WRITTEN = 0; + + if (memcmp(&nvrp_resp.nvPublic.t.nvPublic.attributes, &txt_tpm2_ps_index_attributes, + sizeof(TPMA_NV))) { + printk(BIOS_ERR, "TEE-TXT: Incorrect TPM2 PS/PO index attributes\n"); + return true; + } + + /* + * We don't check the policy, as it may be any policy the platform + * owner/supplier sets. + */ + return false; +} +#endif + /* * Test all bits that are required for Intel TXT. * Enable SMX if available. @@ -514,7 +601,16 @@ bool intel_txt_prepare_txt_env(void) break; } } - +#if CONFIG(TPM2) + if (tlcl_get_family() == TPM_2) { + /* + * We can't do SCHECK without the mandatory TPM indices present, + * otherwise we will end up in reset loop + */ + if (check_tpm2_indices()) + return true; + } +#endif /* Need to park all APs. */ if (CONFIG(PARALLEL_MP_AP_WORK)) mp_park_aps(); diff --git a/src/security/intel/txt/logging.c b/src/security/intel/txt/logging.c index e1692cf283c..17b0bd2213e 100644 --- a/src/security/intel/txt/logging.c +++ b/src/security/intel/txt/logging.c @@ -110,10 +110,12 @@ void txt_dump_acm_info(const struct acm_header_v0 *acm_header) if (acm_header->module_type == CHIPSET_ACM) printk(BIOS_INFO, " Type: Chipset ACM\n"); - if (acm_header->module_sub_type == 0) - printk(BIOS_INFO, " Subtype: undefined\n"); - else if (acm_header->module_sub_type == 1) - printk(BIOS_INFO, " Subtype: Run at reset\n"); + if (acm_header->module_sub_type == BIOS_ACM) + printk(BIOS_INFO, " Subtype: BIOS\n"); + else if (acm_header->module_sub_type == SINIT_ACM) + printk(BIOS_INFO, " Subtype: SINIT\n"); + else if (acm_header->module_sub_type == BOOTGUARD_ACM) + printk(BIOS_INFO, " Subtype: BOOTGUARD\n"); printk(BIOS_INFO, " Header: v%u.%u\n", acm_header->header_version[0], acm_header->header_version[1]); diff --git a/src/security/intel/txt/ramstage.c b/src/security/intel/txt/ramstage.c index 5c03da909a9..eca8162c5bd 100644 --- a/src/security/intel/txt/ramstage.c +++ b/src/security/intel/txt/ramstage.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -179,6 +180,8 @@ static void init_intel_txt(void *unused) if (intel_txt_run_bios_acm(ACMINPUT_SCHECK) < 0) { printk(BIOS_ERR, "TEE-TXT: Error calling BIOS ACM.\n"); return; + } else { + restart_aps(); } } } diff --git a/src/security/intel/txt/romstage.c b/src/security/intel/txt/romstage.c index 643e7a90eba..74b8d76340a 100644 --- a/src/security/intel/txt/romstage.c +++ b/src/security/intel/txt/romstage.c @@ -1,11 +1,20 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include #include #include +#include +#if CONFIG(SOC_INTEL_COMMON_BLOCK_PMC) +#include +#endif +#if CONFIG(SOUTHBRIDGE_INTEL_COMMON_PMBASE) #include +#include +#endif +#include #include #include "txt.h" @@ -82,8 +91,12 @@ void intel_txt_romstage_init(void) } /* FIXME: Clear SLP_TYP# */ - write_pmbase32(4, read_pmbase32(4) & ~(0x7 << 10)); - +#if CONFIG(SOC_INTEL_COMMON_BLOCK_PMC) + pmc_disable_pm1_control(SLP_TYP); +#endif +#if CONFIG(SOUTHBRIDGE_INTEL_COMMON_PMBASE) + write_pmbase32(PM1_CNT, read_pmbase32(PM1_CNT) & ~SLP_TYP); +#endif intel_txt_run_sclean(); /* If running the BIOS ACM is impossible, manual intervention is required */ diff --git a/src/security/intel/txt/txt_register.h b/src/security/intel/txt/txt_register.h index a00084511fa..59ef5561e16 100644 --- a/src/security/intel/txt/txt_register.h +++ b/src/security/intel/txt/txt_register.h @@ -32,7 +32,7 @@ #define ACMERROR_TXT_CLASS_SHIFT 4 #define ACMERROR_TXT_TYPE_SHIFT 0 -#define ACMERROR_TXT_PROGRESS_CODE (0xffull << ACMERROR_TXT_PROGRESS_SHIFT) +#define ACMERROR_TXT_PROGRESS_CODE (0x1ffull << ACMERROR_TXT_PROGRESS_SHIFT) #define ACMERROR_TXT_MINOR_CODE (0x01ull << ACMERROR_TXT_MINOR_SHIFT) #define ACMERROR_TXT_MAJOR_CODE (0x1full << ACMERROR_TXT_MAJOR_SHIFT) #define ACMERROR_TXT_CLASS_CODE (0x3full << ACMERROR_TXT_CLASS_SHIFT) @@ -184,8 +184,9 @@ typedef enum { } acm_module_type; typedef enum { - BIOS = 0, - SINIT = 1, + BIOS_ACM = 0, + SINIT_ACM = 1, + BOOTGUARD_ACM = 3, } acm_module_sub_type; /* diff --git a/src/security/lockdown/Kconfig b/src/security/lockdown/Kconfig index 8de7979904e..fac338017e4 100644 --- a/src/security/lockdown/Kconfig +++ b/src/security/lockdown/Kconfig @@ -62,7 +62,6 @@ config BOOTMEDIA_LOCK_WHOLE_NO_ACCESS config BOOTMEDIA_LOCK_WPRO_VBOOT_RO bool "Write-protect WP_RO FMAP region in boot medium" - depends on VBOOT help Select this if you want to write-protect the WP_RO region as specified in the VBOOT FMAP. You will be able to write every region outside @@ -76,7 +75,7 @@ config BOOTMEDIA_LOCK_WPRO_VBOOT_RO endchoice config BOOTMEDIA_LOCK_IN_VERSTAGE - depends on BOOTMEDIA_LOCK_WPRO_VBOOT_RO + depends on VBOOT bool "Lock boot media down in verstage" help Select this if you want to write-protect the WP_RO region as soon as diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c index c2e2ac35019..233968e955e 100644 --- a/src/security/lockdown/lockdown.c +++ b/src/security/lockdown/lockdown.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include @@ -15,6 +16,11 @@ void boot_device_security_lockdown(void) struct region_device dev; enum bootdev_prot_type lock_type; + if (!is_vboot_locking_permitted()) { + printk(BIOS_DEBUG, "BM-LOCKDOWN: Skipping enabling boot media protection\n"); + return; + } + printk(BIOS_DEBUG, "BM-LOCKDOWN: Enabling boot media protection scheme "); if (CONFIG(BOOTMEDIA_LOCK_CONTROLLER)) { diff --git a/src/security/tpm/Kconfig b/src/security/tpm/Kconfig index 377d6dcb887..292867e7fbf 100644 --- a/src/security/tpm/Kconfig +++ b/src/security/tpm/Kconfig @@ -122,7 +122,7 @@ endchoice config TPM_MEASURED_BOOT_INIT_BOOTBLOCK bool - depends on TPM_MEASURED_BOOT && !VBOOT + depends on TPM_MEASURED_BOOT help Initialize TPM inside the bootblock instead of ramstage. This is useful with some form of hardware assisted root of trust diff --git a/src/security/tpm/tis.h b/src/security/tpm/tis.h index 67ba911e03f..3555ef61a4b 100644 --- a/src/security/tpm/tis.h +++ b/src/security/tpm/tis.h @@ -53,18 +53,6 @@ enum tpm_family { typedef tpm_result_t (*tis_sendrecv_fn)(const u8 *sendbuf, size_t send_size, u8 *recvbuf, size_t *recv_len); -/* - * Probe for the TPM device and set it up for use within locality 0. - * - * @family - pointer which is set to TPM family of the device - * - * Returns pointer to send-receive function on success or NULL on failure. - * - * Do not call this explicitly, it's meant to be used exclusively by TSS - * implementation (tlcl_lib_init() function to be specific). - */ -typedef tis_sendrecv_fn (*tis_probe_fn)(enum tpm_family *family); - /* * tis_vendor_write() * diff --git a/src/security/tpm/tspi/log-tpm1.c b/src/security/tpm/tspi/log-tpm1.c index 481b569cd55..453e74b4e80 100644 --- a/src/security/tpm/tspi/log-tpm1.c +++ b/src/security/tpm/tspi/log-tpm1.c @@ -33,7 +33,7 @@ void *tpm1_log_cbmem_init(void) if (!tclt) return NULL; - memset(tclt, 0, sizeof(*tclt)); + memset(tclt, 0, tpm_log_len); hdr = &tclt->spec_id; /* Fill in first "header" entry. */ diff --git a/src/security/tpm/tspi/tspi.c b/src/security/tpm/tspi/tspi.c index 56b8fa8ede3..002655297f9 100644 --- a/src/security/tpm/tspi/tspi.c +++ b/src/security/tpm/tspi/tspi.c @@ -99,7 +99,7 @@ static inline int tspi_tpm_is_setup(void) * need to check tpm_is_setup. Skip that check in all other stages so * this whole function can be evaluated at compile time. */ - if (CONFIG(VBOOT)) { + if (CONFIG(VBOOT) && !CONFIG(VBOOT_NO_TPM)) { if (verification_should_run()) return tpm_is_setup; return vboot_logic_executed(); diff --git a/src/security/tpm/tss/tcg-2.0/tss.c b/src/security/tpm/tss/tcg-2.0/tss.c index 282845e44c1..68d50f4f194 100644 --- a/src/security/tpm/tss/tcg-2.0/tss.c +++ b/src/security/tpm/tss/tcg-2.0/tss.c @@ -391,6 +391,34 @@ tpm_result_t tlcl2_define_space(uint32_t space_index, size_t space_size, } } +tpm_result_t tlcl2_nv_read_public(uint32_t space_index, + struct nv_read_public_response *nvrp_resp) +{ + struct tpm2_nv_read_public_cmd nvrp_cmd; + struct tpm2_response *response; + + /* Prepare the define space command structure. */ + memset(&nvrp_cmd, 0, sizeof(nvrp_cmd)); + + nvrp_cmd.nvIndex = HR_NV_INDEX + space_index; + + response = tlcl2_process_command(TPM2_NV_ReadPublic, &nvrp_cmd); + printk(BIOS_INFO, "%s: response is %x\n", __func__, + response ? response->hdr.tpm_code : -1); + + if (!response) + return TPM_CB_NO_DEVICE; + + /* Map TPM2 return codes into common vboot representation. */ + switch (response->hdr.tpm_code) { + case TPM2_RC_SUCCESS: + memcpy(nvrp_resp, &response->nvrp, sizeof(*nvrp_resp)); + return TPM_SUCCESS; + default: + return TPM_CB_INTERNAL_INCONSISTENCY; + } +} + uint16_t tlcl2_get_hash_size_from_algo(TPMI_ALG_HASH hash_algo) { uint16_t value; diff --git a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c index 3039a8b8bae..5bf293e0723 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_marshaling.c +++ b/src/security/tpm/tss/tcg-2.0/tss_marshaling.c @@ -197,6 +197,13 @@ static int marshal_nv_define_space(struct obuf *ob, return rc; } +static int marshal_nv_read_public(struct obuf *ob, + const struct tpm2_nv_read_public_cmd *nvrp_in) +{ + return obuf_write_be32(ob, nvrp_in->nvIndex); +} + + static int marshal_nv_setbits(struct obuf *ob, const struct tpm2_nv_setbits_cmd *command_body) { @@ -401,6 +408,10 @@ int tpm_marshal_command(TPM_CC command, const void *tpm_command_body, struct obu rc |= marshal_nv_define_space(ob, tpm_command_body); break; + case TPM2_NV_ReadPublic: + rc |= marshal_nv_read_public(ob, tpm_command_body); + break; + case TPM2_NV_SetBits: rc |= marshal_nv_setbits(ob, tpm_command_body); break; @@ -563,6 +574,80 @@ static int unmarshal_nv_read(struct ibuf *ib, struct nv_read_response *nvr) return 0; } +static int unmarshal_TPM2B_NV_PUBLIC(struct ibuf *ib, TPM2B_NV_PUBLIC *nv_public) +{ + int rc = 0; + + rc |= ibuf_read_be16(ib, &nv_public->t.size); + rc |= ibuf_read_be32(ib, &nv_public->t.nvPublic.nvIndex); + rc |= ibuf_read_be16(ib, &nv_public->t.nvPublic.nameAlg); + rc |= ibuf_read_be32(ib, (uint32_t *)&nv_public->t.nvPublic.attributes); + rc |= ibuf_read_be16(ib, &nv_public->t.nvPublic.authPolicy.t.size); + + nv_public->t.nvPublic.authPolicy.t.buffer = + ibuf_oob_drain(ib, nv_public->t.nvPublic.authPolicy.t.size); + + rc |= ibuf_read_be16(ib, &nv_public->t.nvPublic.dataSize); + + return rc; +} + +static int unmarshal_TPM2B_NAME(struct ibuf *ib, TPM2B_NAME *name) +{ + int rc = 0; + size_t digest_size; + + rc |= ibuf_read_be16(ib, &name->size); + + if (name->size == 0) + return rc; + + /* If size is 4 it is a handle, otherwise it should be a digest */ + if (name->size == 4) { + rc |= ibuf_read_be32(ib, &name->name.handle); + return rc; + } + + rc |= ibuf_read_be16(ib, &name->name.digest.hashAlg); + + switch(name->name.digest.hashAlg) { + case TPM_ALG_SHA1: + digest_size = SHA1_DIGEST_SIZE; + break; + case TPM_ALG_SHA256: + digest_size = SHA256_DIGEST_SIZE; + break; + case TPM_ALG_SHA384: + digest_size = SHA384_DIGEST_SIZE; + break; + case TPM_ALG_SHA512: + digest_size = SHA512_DIGEST_SIZE; + break; + case TPM_ALG_SM3_256: + digest_size = SM3_256_DIGEST_SIZE; + break; + default: + printk(BIOS_WARNING, "%s: Unknown hash algorithm (%02x)\n", + __func__, name->name.digest.hashAlg); + return 1; + } + + memcpy(&name->name.digest.digest, ibuf_oob_drain(ib, digest_size), digest_size); + + return rc; +} + + +static int unmarshal_nv_read_public(struct ibuf *ib, struct nv_read_public_response *nvrp) +{ + int rc = 0; + + rc |= unmarshal_TPM2B_NV_PUBLIC(ib, &nvrp->nvPublic); + rc |= unmarshal_TPM2B_NAME(ib, &nvrp->nvName); + + return rc; +} + static int unmarshal_vendor_command(struct ibuf *ib, struct vendor_command_response *vcr) { @@ -635,6 +720,10 @@ struct tpm2_response *tpm_unmarshal_response(TPM_CC command, struct ibuf *ib) rc |= unmarshal_nv_read(ib, &tpm2_static_resp.nvr); break; + case TPM2_NV_ReadPublic: + rc |= unmarshal_nv_read_public(ib, &tpm2_static_resp.nvrp); + break; + case TPM2_Hierarchy_Control: case TPM2_Clear: case TPM2_ClearControl: diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index f2682b18784..5893ffdb68d 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -88,6 +88,7 @@ struct tpm_header { #define TPM2_Startup ((TPM_CC)0x00000144) #define TPM2_Shutdown ((TPM_CC)0x00000145) #define TPM2_NV_Read ((TPM_CC)0x0000014E) +#define TPM2_NV_ReadPublic ((TPM_CC)0x00000169) #define TPM2_GetCapability ((TPM_CC)0x0000017A) #define TPM2_PCR_Extend ((TPM_CC)0x00000182) /* TPM2 specifies vendor commands need to have this bit set. Vendor command @@ -345,6 +346,21 @@ struct nv_read_response { TPM2B_MAX_NV_BUFFER buffer; }; +typedef union { + TPMT_HA digest; + TPM_HANDLE handle; +} TPMU_NAME; + +typedef struct { + uint16_t size; + TPMU_NAME name; +} TPM2B_NAME; + +struct nv_read_public_response { + TPM2B_NV_PUBLIC nvPublic; + TPM2B_NAME nvName; +}; + struct vendor_command_response { uint16_t vc_subcommand; union { @@ -391,6 +407,7 @@ struct tpm2_response { union { struct get_cap_response gc; struct nv_read_response nvr; + struct nv_read_public_response nvrp; struct tpm2_session_header def_space; struct vendor_command_response vcr; }; @@ -401,6 +418,10 @@ struct tpm2_nv_define_space_cmd { TPMS_NV_PUBLIC publicInfo; }; +struct tpm2_nv_read_public_cmd { + TPMI_RH_NV_INDEX nvIndex; +}; + struct tpm2_nv_write_cmd { TPMI_RH_NV_INDEX nvIndex; TPM2B_MAX_NV_BUFFER data; diff --git a/src/security/tpm/tss2.h b/src/security/tpm/tss2.h index 16ccf5db6fb..9bb562a2349 100644 --- a/src/security/tpm/tss2.h +++ b/src/security/tpm/tss2.h @@ -28,6 +28,13 @@ tpm_result_t tlcl2_define_space(uint32_t space_index, size_t space_size, const TPMA_NV nv_attributes, const uint8_t *nv_policy, size_t nv_policy_size); +/* + * Read the public data of NV index. [index] is the index for the space, + * [nvrp_resp] is hte NV index output data. The TPM error code is returned. + */ +tpm_result_t tlcl2_nv_read_public(uint32_t space_index, + struct nv_read_public_response *nvrp_resp); + /* * Issue TPM2_GetCapability command */ diff --git a/src/security/vboot/Kconfig b/src/security/vboot/Kconfig index 7e291e0c701..9cd2cc265b7 100644 --- a/src/security/vboot/Kconfig +++ b/src/security/vboot/Kconfig @@ -105,6 +105,16 @@ config VBOOT_STARTS_IN_ROMSTAGE memory initialization). This implies that the vboot work buffer is in CBMEM from the start and doesn't need to be reserved in memlayout. +config VBOOT_NO_TPM + bool + default y if !TPM + default n + select VBOOT_MOCK_SECDATA + help + When this option is enabled, vboot doesn't attempt to access the TPM + even if one is present. Select this option if you expect the TPM to + not always be available (removed, or disabled in the case of fTPM) + config VBOOT_MOCK_SECDATA bool "Mock secdata for firmware verification" default n diff --git a/src/security/vboot/Makefile.mk b/src/security/vboot/Makefile.mk index e9b3eb69f14..e2e829809a8 100644 --- a/src/security/vboot/Makefile.mk +++ b/src/security/vboot/Makefile.mk @@ -25,7 +25,7 @@ VBOOT_CFLAGS_$(1) += -DVBOOT_DEBUG $$(VBOOT_LIB_$(1)): $(obj)/config.h printf " MAKE $(subst $(obj)/,,$(@))\n" +FIRMWARE_ARCH=$$(ARCHDIR-$$(ARCH-$(1)-y)) \ - CC="$$(CC_$(1))" \ + CC="$$(call vboot-fixup-includes,$$(CC_$(1)))" \ CFLAGS="$$(VBOOT_CFLAGS_$(1))" VBOOT2="y" \ EC_EFS="$(CONFIG_VBOOT_EC_EFS)" \ X86_SHA_EXT="$(if $(CONFIG_ARCH_$(call toupper,$(1))_X86_32)$(CONFIG_ARCH_$(call toupper,$(1))_X86_64),$\ @@ -128,7 +128,9 @@ romstage-$(CONFIG_TPM2) += secdata_tpm2.c ramstage-$(CONFIG_TPM2) += secdata_tpm2.c endif -verstage-$(CONFIG_TPM) += tpm_common.c +ifneq ($(CONFIG_VBOOT_NO_TPM),y) +verstage-y += tpm_common.c +endif romstage-y += common.c @@ -395,7 +397,7 @@ files_added:: $(obj)/coreboot.rom $(FUTILITY) $(CBFSTOOL) --kernelkey "$(CONFIG_VBOOT_KERNEL_KEY)" \ --version $(CONFIG_VBOOT_KEYBLOCK_VERSION) \ --flags $(CONFIG_VBOOT_KEYBLOCK_PREAMBLE_FLAGS) \ - $(obj)/coreboot.rom + $(obj)/coreboot.rom 2> /dev/null if [ "$(CONFIG_VBOOT_SLOTS_RW_AB)" = 'y' ]; then \ printf " FLASHMAP Layout generated for RO, A and B partition.\n"; \ elif [ "$(CONFIG_VBOOT_SLOTS_RW_A)" = 'y' ]; then \ diff --git a/src/security/vboot/tpm_common.h b/src/security/vboot/tpm_common.h index 22ece8927bd..619f328fa2c 100644 --- a/src/security/vboot/tpm_common.h +++ b/src/security/vboot/tpm_common.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#if CONFIG(TPM) +#if !CONFIG(VBOOT_NO_TPM) /* Start of the root of trust */ tpm_result_t vboot_setup_tpm(struct vb2_context *ctx); diff --git a/src/soc/amd/common/block/smi/smi_util.c b/src/soc/amd/common/block/smi/smi_util.c index 8ec900f762d..b285c992e5d 100644 --- a/src/soc/amd/common/block/smi/smi_util.c +++ b/src/soc/amd/common/block/smi/smi_util.c @@ -155,6 +155,8 @@ void clear_smi_sci_status(void) smi_write32(SMI_SCI_STATUS, smi_read32(SMI_SCI_STATUS)); } +#if !CONFIG(HUDSON_PSP) + static void clear_psp_smi(void) { uint32_t reg32; @@ -178,3 +180,5 @@ void configure_psp_smi(void) reset_psp_smi(); configure_smi(SMITYPE_PSP, SMI_MODE_SMI); } + +#endif diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index f6e918204bf..4303bd7d297 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -42,7 +42,7 @@ config SOC_INTEL_ALDERLAKE select CPU_INTEL_COMMON_VOLTAGE select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BASECODE_RAMTOP if CHROMEOS select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC @@ -86,6 +86,7 @@ config SOC_INTEL_ALDERLAKE select SOC_INTEL_CRASHLOG if MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SEND_EOP_LATE if !BOARD_GOOGLE_BRYA_COMMON && !BOARD_GOOGLE_BROX_COMMON select SOC_INTEL_CSE_SET_EOP + select HAVE_INTEL_ME_HAP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select HAVE_INTEL_COMPLIANCE_TEST_MODE select SSE2 @@ -403,10 +404,8 @@ config FSP_HEADER_PATH default "src/vendorcode/intel/fsp/fsp2_0/alderlake_n/" if !FSP_USE_REPO && SOC_INTEL_ALDERLAKE_PCH_N default "src/vendorcode/intel/fsp/fsp2_0/raptorlake/" if !FSP_USE_REPO && SOC_INTEL_RAPTORLAKE default "src/vendorcode/intel/fsp/fsp2_0/alderlake/" if !FSP_USE_REPO - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Include/" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Include/" if SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Include/" if SOC_INTEL_ALDERLAKE_PCH_S @@ -414,10 +413,8 @@ config FSP_HEADER_PATH config FSP_FD_PATH string depends on FSP_USE_REPO - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P && SOC_INTEL_RAPTORLAKE - default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_RAPTORLAKE_PCH_S - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeP/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P - default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeS/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeP/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_P + default "3rdparty/fsp/RaptorLakeFspBinPkg/IoT/RaptorLakeS/FSP.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_S default "3rdparty/fsp/AlderLakeFspBinPkg/IoT/AlderLakeN/Fsp.fd" if FSP_TYPE_IOT && SOC_INTEL_ALDERLAKE_PCH_N default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeP/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_P default "3rdparty/fsp/RaptorLakeFspBinPkg/Client/RaptorLakeS/Fsp.fd" if SOC_INTEL_ALDERLAKE_PCH_S diff --git a/src/soc/intel/alderlake/Makefile.mk b/src/soc/intel/alderlake/Makefile.mk index 55fc83ea7c5..a3a26bfb3a1 100644 --- a/src/soc/intel/alderlake/Makefile.mk +++ b/src/soc/intel/alderlake/Makefile.mk @@ -18,6 +18,7 @@ bootblock-y += espi.c bootblock-y += p2sb.c bootblock-$(CONFIG_ALDERLAKE_CONFIGURE_DESCRIPTOR) += bootblock/update_descriptor.c +romstage-y += cpu_util.c romstage-$(CONFIG_SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY) += cse_telemetry.c romstage-y += espi.c romstage-y += meminit.c @@ -76,13 +77,7 @@ CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/iot/raptorlake_s endif ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_S),y) -# 06-97-00, 06-97-01, 06-97-04 are ADL-S Engineering Samples -# 06-97-02 are ADL-S/HX Quality Samples but also ADL-HX Engineering Samples -# 06-b7-00 are RPL-S Engineering Samples -# ADL-S/HX C0/H0 and RPL-S C0/H0 -cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-97-05 -# RPL-S/HX B0 -cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-b7-01 +cpu_microcode_bins += 3rdparty/dasharo-blobs/msi/ms7e06/microcode.bin else ifeq ($(CONFIG_SOC_INTEL_ALDERLAKE_PCH_N),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-be-00 else diff --git a/src/soc/intel/alderlake/acpi.c b/src/soc/intel/alderlake/acpi.c index ba3a5bcd1ec..cab4b66e8b1 100644 --- a/src/soc/intel/alderlake/acpi.c +++ b/src/soc/intel/alderlake/acpi.c @@ -104,7 +104,11 @@ static const acpi_cstate_t cstate_map[NUM_C_STATES] = { static int cstate_set_non_s0ix[] = { C_STATE_C1, C_STATE_C6_LONG_LAT, +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) + C_STATE_C8 +#else C_STATE_C7S_LONG_LAT +#endif }; static int cstate_set_s0ix[] = { @@ -337,6 +341,8 @@ void soc_fill_gnvs(struct global_nvs *gnvs) /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + gnvs->s0ix = config->s0ix_enable; } int soc_madt_sci_irq_polarity(int sci) diff --git a/src/soc/intel/alderlake/acpi/oc_wdt.asl b/src/soc/intel/alderlake/acpi/oc_wdt.asl new file mode 100644 index 00000000000..072cf89047c --- /dev/null +++ b/src/soc/intel/alderlake/acpi/oc_wdt.asl @@ -0,0 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Scope (\_SB.PCI0.LPCB) { + + /* OC Watchdog */ + Device(CWDT) + { +#if CONFIG(SOC_INTEL_RAPTORLAKE) + Name(_HID,"INTC109C") +#else + Name(_HID,"INTC1099") +#endif + Name(_CID,EISAID("PNP0C02")) + + Name (RBUF, ResourceTemplate () { + IO(Decode16, 0, 0, 0x4, 0x4, OCWD) + }) + + Method (_CRS, 0x0, NotSerialized) + { + CreateWordField(^RBUF, ^OCWD._MIN, OMIN) + CreateWordField(^RBUF, ^OCWD._MAX, OMAX) + + OMIN = ACPI_BASE_ADDRESS + 0x54 + OMAX = ACPI_BASE_ADDRESS + 0x54 + + Return (RBUF) + } + } +} diff --git a/src/soc/intel/alderlake/acpi/pcie.asl b/src/soc/intel/alderlake/acpi/pcie.asl index 414ced2cb75..919ca8effdd 100644 --- a/src/soc/intel/alderlake/acpi/pcie.asl +++ b/src/soc/intel/alderlake/acpi/pcie.asl @@ -309,6 +309,11 @@ Device (RP12) Device (PEG0) { Name (_ADR, 0x00060000) + + Method (_PRT) + { + Return (IRQM (1)) + } } #endif diff --git a/src/soc/intel/alderlake/acpi/pcie_pch_s.asl b/src/soc/intel/alderlake/acpi/pcie_pch_s.asl index 5437730af12..c2f22b54c0f 100644 --- a/src/soc/intel/alderlake/acpi/pcie_pch_s.asl +++ b/src/soc/intel/alderlake/acpi/pcie_pch_s.asl @@ -275,14 +275,26 @@ Device (RP28) Device (PEG0) { Name (_ADR, 0x00060000) + Method (_PRT) + { + Return (IRQM (1)) + } } Device (PEG1) { Name (_ADR, 0x00010000) + Method (_PRT) + { + Return (IRQM (1)) + } } Device (PEG2) { Name (_ADR, 0x00010001) + Method (_PRT) + { + Return (IRQM (2)) + } } diff --git a/src/soc/intel/alderlake/acpi/southbridge.asl b/src/soc/intel/alderlake/acpi/southbridge.asl index 651d26c4eff..fc89cd41f23 100644 --- a/src/soc/intel/alderlake/acpi/southbridge.asl +++ b/src/soc/intel/alderlake/acpi/southbridge.asl @@ -16,6 +16,9 @@ /* ESPI 0:1f.0 */ #include +/* OC WDT */ +#include "oc_wdt.asl" + /* PCH HDA */ #include "pch_hda.asl" diff --git a/src/soc/intel/alderlake/acpi/tcss.asl b/src/soc/intel/alderlake/acpi/tcss.asl index 6f8eddafe07..85f57f0d89b 100644 --- a/src/soc/intel/alderlake/acpi/tcss.asl +++ b/src/soc/intel/alderlake/acpi/tcss.asl @@ -331,7 +331,7 @@ Scope (\_SB.PCI0) Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) - Name (_STA, 0xF) + Name (_STA, 0xB) } /* @@ -542,47 +542,6 @@ Scope (\_SB.PCI0) } } - PowerResource (TBT0, 5, 1) - { - Method (_STA, 0) - { - Return (\_SB.PCI0.TDM0.STAT) - } - - Method (_ON, 0) - { - TG0N() - } - - Method (_OFF, 0) - { - If (\_SB.PCI0.TDM0.SD3C == 0) { - TG0F() - } - } - } - - PowerResource (TBT1, 5, 1) - { - Method (_STA, 0) - { - Return (\_SB.PCI0.TDM1.STAT) - } - - Method (_ON, 0) - { - TG1N() - } - - Method (_OFF, 0) - { - If (\_SB.PCI0.TDM1.SD3C == 0) { - TG1F() - } - } - } - -#if CONFIG(D3COLD_SUPPORT) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -594,9 +553,9 @@ Scope (\_SB.PCI0) /* Wait for ack, the maximum wait time for the ack is 100 msec. */ While ((TACK != 0) && (Local0 < TCSS_IOM_ACK_TIMEOUT_IN_MS)) { /* - * Wait in this loop until TACK becomes 0 with timeout - * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. - */ + * Wait in this loop until TACK becomes 0 with timeout + * TCSS_IOM_ACK_TIMEOUT_IN_MS by default. + */ Sleep (1) /* Delay of 1ms. */ Local0++ } @@ -617,7 +576,7 @@ Scope (\_SB.PCI0) Method (TCOF, 0) { If ((\_SB.PCI0.TXHC.SD3C != 0) || (\_SB.PCI0.TDM0.SD3C != 0) - || (\_SB.PCI0.TDM1.SD3C != 0)) + || (\_SB.PCI0.TDM1.SD3C != 0)) { Printf("Skip D3C entry.") Return @@ -627,33 +586,74 @@ Scope (\_SB.PCI0) TD3C = 1 } - PowerResource (D3C, 5, 0) - { - /* - * Variable to save power state - * 1 - TC Cold request cleared. - * 0 - TC Cold request sent. - */ - Name (STAT, 0x1) - - Method (_STA, 0) + If (S0IX == 1) { + PowerResource (TBT0, 5, 1) { - Return (STAT) + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM0.STAT) + } + + Method (_ON, 0) + { + TG0N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM0.SD3C == 0) { + TG0F() + } + } } - Method (_ON, 0) + PowerResource (TBT1, 5, 1) { - \_SB.PCI0.TCON() - STAT = 1 + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM1.STAT) + } + + Method (_ON, 0) + { + TG1N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM1.SD3C == 0) { + TG1F() + } + } } - Method (_OFF, 0) + PowerResource (D3C, 5, 0) { - \_SB.PCI0.TCOF() - STAT = 0 + /* + * Variable to save power state + * 1 - TC Cold request cleared. + * 0 - TC Cold request sent. + */ + Name (STAT, 0x1) + + Method (_STA, 0) + { + Return (STAT) + } + + Method (_ON, 0) + { + \_SB.PCI0.TCON() + STAT = 1 + } + + Method (_OFF, 0) + { + \_SB.PCI0.TCOF() + STAT = 0 + } } - } -#endif // D3COLD_SUPPORT + } /* S0IX == 1 */ /* * TCSS xHCI device diff --git a/src/soc/intel/alderlake/acpi/tcss_dma.asl b/src/soc/intel/alderlake/acpi/tcss_dma.asl index 2586ecbbc75..428ff083d47 100644 --- a/src/soc/intel/alderlake/acpi/tcss_dma.asl +++ b/src/soc/intel/alderlake/acpi/tcss_dma.asl @@ -28,49 +28,32 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ Method (_S0W, 0x0) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x04) -#else - Return (0x03) -#endif // D3COLD_SUPPORT -} - -/* - * Get power resources that are dependent on this device for Operating System Power Management - * to put the device in the D0 device state - */ -Method (_PR0) -{ -#if CONFIG(D3COLD_SUPPORT) - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } -#else - If (DUID == 0) { - Return (Package() { \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + Return (0x04) } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + Return (0x03) } -#endif // D3COLD_SUPPORT } -Method (_PR3) -{ -#if CONFIG(D3COLD_SUPPORT) - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + +If (S0IX == 1) { + Method (_PR0) + { + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#else - If (DUID == 0) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + + Method (_PR3) + { + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl index 6dbde46f49d..77f513a5f0c 100644 --- a/src/soc/intel/alderlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/alderlake/acpi/tcss_pcierp.asl @@ -247,45 +247,33 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x4) -#else - Return (0x3) -#endif // D3COLD_SUPPORT -} - -Method (_PR0) -{ -#if CONFIG(D3COLD_SUPPORT) - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + Return (0x04) } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + Return (0x03) } -#else - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) - } -#endif // D3COLD_SUPPORT } -Method (_PR3) -{ -#if CONFIG(D3COLD_SUPPORT) - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + +If (S0IX == 1) { + Method (_PR0) + { + + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#else - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + + Method (_PR3) + { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/alderlake/acpi/tcss_xhci.asl b/src/soc/intel/alderlake/acpi/tcss_xhci.asl index ddc5a6665dc..1ca4117697c 100644 --- a/src/soc/intel/alderlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/alderlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x4) -#else - Return (0x3) -#endif // D3COLD_SUPPORT + If (S0IX == 1) { + Return (0x4) + } Else { + Return (0x3) + } } /* @@ -43,17 +43,17 @@ Method (_S0W, 0x0, NotSerialized) */ Name (SD3C, 0) -#if CONFIG(D3COLD_SUPPORT) -Method (_PR0) -{ - Return (Package () { \_SB.PCI0.D3C }) -} +If (S0IX == 1) { + Method (_PR0) + { + Return (Package () { \_SB.PCI0.D3C }) + } -Method (_PR3) -{ - Return (Package () { \_SB.PCI0.D3C }) + Method (_PR3) + { + Return (Package () { \_SB.PCI0.D3C }) + } } -#endif // D3COLD_SUPPORT /* * XHCI controller _DSM method diff --git a/src/soc/intel/alderlake/bootblock/report_platform.c b/src/soc/intel/alderlake/bootblock/report_platform.c index 57e4f522da6..21aea57fc5f 100644 --- a/src/soc/intel/alderlake/bootblock/report_platform.c +++ b/src/soc/intel/alderlake/bootblock/report_platform.c @@ -102,6 +102,7 @@ static struct { { PCI_DID_INTEL_RPL_S_ID_3, "Raptorlake-S (8+8)" }, { PCI_DID_INTEL_RPL_S_ID_4, "Raptorlake-S (6+8)" }, { PCI_DID_INTEL_RPL_S_ID_5, "Raptorlake-S (6+4)" }, + { PCI_DID_INTEL_RPL_S_ID_6, "Raptorlake-S (8+12)" }, }; static struct { @@ -219,6 +220,8 @@ static struct { { PCI_DID_INTEL_ADL_N_GT1, "Alderlake N GT1" }, { PCI_DID_INTEL_ADL_N_GT2, "Alderlake N GT2" }, { PCI_DID_INTEL_ADL_N_GT3, "Alderlake N GT3" }, + { PCI_DID_INTEL_ADL_N_GT4, "Alderlake N GT4" }, + { PCI_DID_INTEL_ADL_N_GT5, "Alderlake N GT5" }, { PCI_DID_INTEL_ADL_S_GT1, "Alderlake S GT1" }, { PCI_DID_INTEL_ADL_S_GT1_1, "Alderlake S GT1" }, { PCI_DID_INTEL_ADL_S_GT2, "Alderlake S GT2" }, @@ -242,6 +245,8 @@ static struct { { PCI_DID_INTEL_RPL_S_GT1_1, "Raptorlake S GT1" }, { PCI_DID_INTEL_RPL_S_GT1_2, "Raptorlake S GT1" }, { PCI_DID_INTEL_RPL_S_GT1_3, "Raptorlake S GT1" }, + { PCI_DID_INTEL_RPL_S_GT1_4, "Raptorlake S GT1" }, + { PCI_DID_INTEL_RPL_S_GT1_5, "Raptorlake S GT1" }, { PCI_DID_INTEL_TWL_GT1_1, "Twinlake GT1" }, { PCI_DID_INTEL_TWL_GT1_2, "Twinlake GT1" }, }; diff --git a/src/soc/intel/alderlake/chip.c b/src/soc/intel/alderlake/chip.c index 0256de4f820..25ad220c7d0 100644 --- a/src/soc/intel/alderlake/chip.c +++ b/src/soc/intel/alderlake/chip.c @@ -74,7 +74,13 @@ const char *soc_acpi_name(const struct device *dev) return NULL; switch (dev->path.pci.devfn) { - case SA_DEVFN_ROOT: return "MCHC"; + case SA_DEVFN_ROOT: + /* MCHC only for bus 0 */ + if (dev->upstream && dev->upstream->secondary == 0) + return "MCHC"; + else + /* FIXME: handle RTD3 generic dev path in PEP to return correct acpi_name */ + return "PXSX"; #if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) case SA_DEVFN_CPU_PCIE1_0: return "PEG1"; case SA_DEVFN_CPU_PCIE1_1: return "PEG2"; diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h index 040b3d131d2..5169c76b7ef 100644 --- a/src/soc/intel/alderlake/chip.h +++ b/src/soc/intel/alderlake/chip.h @@ -109,6 +109,9 @@ enum soc_intel_alderlake_power_limits { RPL_S_201_35W_CORE, RPL_S_201_46W_CORE, RPL_S_201_65W_CORE, + RPL_S_8121_35W_CORE, + RPL_S_8121_65W_CORE, + RPL_S_8121_125W_CORE, RPL_HX_8_16_55W_CORE, RPL_HX_8_12_55W_CORE, RPL_HX_8_8_55W_CORE, @@ -145,87 +148,91 @@ static const struct { unsigned int cpu_id; enum soc_intel_alderlake_power_limits limits; enum soc_intel_alderlake_cpu_tdps cpu_tdp; + uint8_t pl1_time; } cpuid_to_adl[] = { - { PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_442_482_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_442_482_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_282_442_482_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W }, - { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W }, - { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_ADL_N_ID_6, ADL_N_041_12W_CORE, TDP_12W }, - { PCI_DID_INTEL_ADL_N_ID_7, ADL_N_041_12W_CORE, TDP_12W }, - { PCI_DID_INTEL_ADL_N_ID_8, ADL_N_021_6W_CORE, TDP_6W }, - { PCI_DID_INTEL_ADL_N_ID_9, ADL_N_021_10W_CORE, TDP_10W }, - { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_150W_CORE, TDP_150W }, - { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_ADL_S_ID_8, ADL_S_642_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_58W_CORE, TDP_58W }, - { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W }, - { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W }, - { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W }, - { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W }, - { PCI_DID_INTEL_RPL_P_ID_6, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_P_ID_7, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_642_482_45W_CORE, TDP_45W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_150W_CORE, TDP_150W }, - { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_125W_CORE, TDP_125W }, - { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_80W_CORE, TDP_80W }, - { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_95W_CORE, TDP_90W }, - { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_58W_CORE, TDP_58W }, - { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_60W_CORE, TDP_60W }, - { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_35W_CORE, TDP_35W }, - { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_46W_CORE, TDP_46W }, - { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_65W_CORE, TDP_65W }, - { PCI_DID_INTEL_RPL_HX_ID_1, RPL_HX_8_16_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_2, RPL_HX_8_12_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_3, RPL_HX_8_8_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_4, RPL_HX_6_8_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_5, RPL_HX_6_4_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_6, RPL_HX_8_8_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_7, RPL_HX_6_8_55W_CORE, TDP_55W }, - { PCI_DID_INTEL_RPL_HX_ID_8, RPL_HX_6_4_55W_CORE, TDP_55W }, + { PCI_DID_INTEL_ADL_P_ID_10, ADL_P_142_242_282_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_142_242_282_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_6, ADL_P_142_242_282_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_7, ADL_P_282_442_482_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_282_442_482_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_682_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_5, ADL_P_442_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_4, ADL_P_642_682_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_3, ADL_P_642_682_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_442_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_P_ID_1, ADL_P_282_442_482_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_12W_CORE, TDP_12W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_M_ID_1, ADL_M_282_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_M_ID_2, ADL_M_242_CORE, TDP_9W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_1, ADL_N_081_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_2, ADL_N_041_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_3, ADL_N_041_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_4, ADL_N_021_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_5, ADL_N_041_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_6, ADL_N_041_12W_CORE, TDP_12W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_7, ADL_N_041_12W_CORE, TDP_12W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_8, ADL_N_021_6W_CORE, TDP_6W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_N_ID_9, ADL_N_021_10W_CORE, TDP_10W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_1, ADL_S_882_150W_CORE, TDP_150W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_3, ADL_S_842_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_8, ADL_S_642_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_10, ADL_S_602_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_58W_CORE, TDP_58W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, ADL_S_402_60W_CORE, TDP_60W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, ADL_S_202_46W_CORE, TDP_46W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_1, RPL_P_682_482_282_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_482_282_28W_CORE, TDP_28W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_2, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_3, RPL_P_282_242_142_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_4, RPL_P_282_242_142_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_5, RPL_P_282_242_142_15W_CORE, TDP_15W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_6, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_7, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_P_ID_8, RPL_P_682_642_482_45W_CORE, TDP_45W, MOBILE_SKU_PL1_TIME_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_95W_CORE, TDP_95W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_1, RPL_S_8161_150W_CORE, TDP_150W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_3, RPL_S_881_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_4, RPL_S_681_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_5, RPL_S_641_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_6, RPL_S_8121_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_6, RPL_S_8121_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_6, RPL_S_8121_125W_CORE, TDP_125W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_80W_CORE, TDP_80W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_S_ID_2, RPL_S_801_95W_CORE, TDP_90W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_58W_CORE, TDP_58W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_60W_CORE, TDP_60W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_11, RPL_S_401_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_35W_CORE, TDP_35W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_46W_CORE, TDP_46W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_ADL_S_ID_12, RPL_S_201_65W_CORE, TDP_65W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_1, RPL_HX_8_16_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_2, RPL_HX_8_12_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_3, RPL_HX_8_8_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_4, RPL_HX_6_8_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_5, RPL_HX_6_4_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_6, RPL_HX_8_8_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_7, RPL_HX_6_8_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, + { PCI_DID_INTEL_RPL_HX_ID_8, RPL_HX_6_4_55W_CORE, TDP_55W, POWER_LIMIT1_TIME_56_SEC }, }; /* Types of display ports */ @@ -413,6 +420,7 @@ struct soc_intel_alderlake_config { bool sata_salp_support; bool sata_ports_enable[8]; bool sata_ports_dev_slp[8]; + bool sata_ports_hotplug[8]; /* * Enable(0)/Disable(1) SATA Power Optimizer on PCH side. diff --git a/src/soc/intel/alderlake/chipset_pch_s.cb b/src/soc/intel/alderlake/chipset_pch_s.cb index 6bcfab1f450..ad998094cee 100644 --- a/src/soc/intel/alderlake/chipset_pch_s.cb +++ b/src/soc/intel/alderlake/chipset_pch_s.cb @@ -260,6 +260,24 @@ chip soc/intel/alderlake .tdp_pl4 = 65, }" + register "power_limits_config[RPL_S_8121_35W_CORE]" = "{ + .tdp_pl1_override = 35, + .tdp_pl2_override = 106, + .tdp_pl4 = 194, + }" + + register "power_limits_config[RPL_S_8121_65W_CORE]" = "{ + .tdp_pl1_override = 65, + .tdp_pl2_override = 219, + .tdp_pl4 = 341, + }" + + register "power_limits_config[RPL_S_8121_125W_CORE]" = "{ + .tdp_pl1_override = 125, + .tdp_pl2_override = 253, + .tdp_pl4 = 380, + }" + # NOTE: if any variant wants to override this value, use the same format # as register "common_soc_config.pch_thermal_trip" = "value", instead of # putting it under register "common_soc_config" in overridetree.cb file. diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 00c683c654c..f712d8e1175 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -265,7 +265,8 @@ enum adl_cpu_type get_adl_cpu_type(void) PCI_DID_INTEL_RPL_S_ID_2, PCI_DID_INTEL_RPL_S_ID_3, PCI_DID_INTEL_RPL_S_ID_4, - PCI_DID_INTEL_RPL_S_ID_5 + PCI_DID_INTEL_RPL_S_ID_5, + PCI_DID_INTEL_RPL_S_ID_6 }; const uint16_t rpl_p_mch_ids[] = { diff --git a/src/soc/intel/alderlake/cpu_util.c b/src/soc/intel/alderlake/cpu_util.c new file mode 100644 index 00000000000..b0bc33b6675 --- /dev/null +++ b/src/soc/intel/alderlake/cpu_util.c @@ -0,0 +1,120 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define __SIMPLE_DEVICE__ + +#include +#include +#include +#include +#include + +struct sku_table { + uint16_t sa_devid; + uint8_t num_p_cores; + uint8_t num_e_cores; +}; + +static const struct sku_table adl_sku_table[] = { + // AlderLake CPU Desktop SA Device IDs + { 0x4660, 8, 8 }, // AlderLake Desktop (8+8+GT) SA DID + { 0x4664, 8, 6 }, // AlderLake Desktop (8+6+GT) SA DID + { 0x4668, 8, 4 }, // AlderLake Desktop (8+4+GT) SA DID + { 0x466C, 8, 2 }, // AlderLake Desktop (8+2+GT) SA DID + { 0x4670, 8, 0 }, // AlderLake Desktop (8+0+GT) SA DID + { 0x4640, 6, 8 }, // AlderLake Desktop (6+8+GT) SA DID + { 0x4644, 6, 6 }, // AlderLake Desktop (6+6+GT) SA DID + { 0x4648, 6, 4 }, // AlderLake Desktop (6+4+GT) SA DID + { 0x464C, 6, 2 }, // AlderLake Desktop (6+2+GT) SA DID + { 0x4650, 6, 0 }, // AlderLake Desktop (6+0+GT) SA DID + { 0x4630, 4, 0 }, // AlderLake Desktop (4+0+GT) SA DID + { 0x4610, 2, 0 }, // AlderLake Desktop (2+0+GT) SA DID + { 0x4673, 8, 6 }, // AlderLake Desktop (8+6+GT) SA DID + { 0x4663, 8, 8 }, // AlderLake Desktop BGA (8+8+GT) SA DID + { 0x466B, 8, 4 }, // AlderLake Desktop BGA (8+4+GT) SA DID + { 0x4653, 6, 0 }, // AlderLake Desktop BGA (6+0+GT) SA DID + { 0x4633, 4, 0 }, // AlderLake Desktop BGA (4+0+GT) SA DID + { 0x4637, 8, 8 }, // AlderLake Mobile S BGA (8+8+GT) SA DID + { 0x463B, 6, 8 }, // AlderLake Mobile S BGA (6+8+GT) SA DID + { 0x4623, 4, 8 }, // AlderLake Mobile S BGA (4+8+GT) SA DID + { 0x462B, 4, 4 }, // AlderLake Mobile S BGA (4+4+GT) SA DID + { 0x4647, 6, 4 }, // AlderLake Mobile S BGA (6+4+GT) SA DID + // AlderLake CPU Mobile SA Device IDs + { 0x4641, 6, 8 }, // AlderLake P (6+8+GT) SA DID + { 0x4649, 6, 4 }, // AlderLake P (6+4+GT) SA DID + { 0x4621, 4, 8 }, // AlderLake P (4+8+GT) SA DID + { 0x4609, 2, 4 }, // AlderLake P (2+4+GT) SA DID + { 0x4601, 2, 8 }, // AlderLake P (2+8+GT) SA DID + { 0x4661, 6, 8 }, // AlderLake P (6+8+2) SA DID + { 0x4629, 4, 4 }, // AlderLake P (4+4+1) SA DID + { 0x4619, 1, 4 }, // AlderLake P (1+4+GT) SA DID + { 0x4659, 1, 8 }, // AlderLake P (1+8+GT) SA DID + { 0x4645, 6, 6 }, // AlderLake P (6+6+GT) SA DID + { 0x4602, 2, 8 }, // AlderLake M (2+8+GT) SA DID + { 0x460A, 2, 4 }, // AlderLake M (2+4+GT) SA DID + { 0x461A, 1, 4 }, // AlderLake M (1+4+GT) SA DID + { 0x4622, 1, 8 }, // AlderLake M (1+8+GT) SA DID + { 0x4617, 0, 8 }, // AlderLake N (0+8+1) SA DID + { 0x4614, 0, 2 }, // AlderLake N Celeron (0+2+0) SA DID + { 0x4618, 0, 4 }, // AlderLake N (0+4+0) SA DID + { 0x461B, 0, 4 }, // AlderLake N Pentium (0+4+0) SA DID + { 0x461C, 0, 4 }, // AlderLake N Celeron (0+4+0) SA DID + { 0x4603, 2, 8 }, // AlderLake PS (2+8+GT) SA DID + { 0x4643, 6, 8 }, // AlderLake PS (6+8+GT) SA DID + { 0x4627, 4, 8 }, // AlderLake PS (4+8+GT) SA DID + { 0x460B, 2, 4 }, // AlderLake PS (2+4+GT) SA DID + { 0x464B, 4, 4 }, // AlderLake PS (4+4+GT) SA DID + { 0x467B, 1, 4 }, // AlderLake PS (1+4+GT) SA DID + // RaptorLake CPU Desktop SA Device IDs + { 0xA700, 8, 16 }, // RaptorLake Desktop (8+16+GT) SA DID + { 0xA701, 8, 0 }, // RaptorLake Desktop (8+0+GT) SA DID + { 0xA702, 8, 16 }, // RaptorLake Desktop(BGA) (8+16+GT) SA DID + { 0xA703, 8, 8 }, // RaptorLake Desktop (8+8+GT) SA DID + { 0xA704, 6, 8 }, // RaptorLake Desktop (6+8+GT) SA DID + { 0xA705, 6, 4 }, // RaptorLake Desktop (6+4+GT) SA DID + { 0xA717, 8, 0 }, // RaptorLake Desktop(BGA) (8+0+GT) SA DID + { 0xA718, 8, 4 }, // RaptorLake Desktop(BGA) (8+4+GT) SA DID + { 0xA719, 6, 4 }, // RaptorLake Desktop(BGA) (6+4+GT) SA DID + { 0xA71A, 4, 4 }, // RaptorLake Desktop(BGA) (4+4+GT) SA DID + { 0xA728, 8, 8 }, // RaptorLake Desktop(BGA) (8+8+GT) SA DID + { 0xA729, 8, 12 }, // RaptorLake Desktop(BGA) (8+12+GT) SA DID + { 0xA72A, 6, 8 }, // RaptorLake Desktop(BGA) (6+8+GT) SA DID + { 0xA72B, 4, 0 }, // RaptorLake Desktop (4+0+GT) SA DID + { 0xA740, 8, 12 }, // RaptorLake Desktop (8+12+GT) SA DID + // RaptorLake CPU Mobile SA Device IDs + { 0xA706, 6, 8 }, // RaptorLake P (6+8+GT) SA DID + { 0xA707, 4, 8 }, // RaptorLake P (4+8+GT) SA DID + { 0xA708, 2, 8 }, // RaptorLake P (2+8+GT) SA DID + { 0xA716, 4, 4 }, // RaptorLake P (4+4+GT) SA DID + { 0xA709, 6, 8 }, // RaptorLake Px (6+8+GT) SA DID + { 0xA70A, 4, 8 }, // RaptorLake Px (4+8+GT) SA DID + { 0xA70B, 2, 8 }, // RaptorLake Px (2+8+GT) SA DID + { 0xA715, 6, 4 }, // RaptorLake P (6+4+GT) SA DID + { 0xA71B, 2, 4 }, // RaptorLake P (2+4+GT) SA DID + { 0xA71C, 1, 4 }, // RaptorLake P (1+4+GT) SA DID + { 0xA734, 6, 8 }, // RaptorLake PS (6+8+GT) SA DID + { 0xA735, 4, 8 }, // RaptorLake PS (4+8+GT) SA DID + { 0xA736, 2, 8 }, // RaptorLake PS (2+8+GT) SA DID + { 0xA737, 2, 4 }, // RaptorLake PS (2+4+GT) SA DID + { 0xA738, 6, 4 }, // RaptorLake PS (6+4+GT) SA DID + { 0xA739, 4, 4 }, // RaptorLake PS (4+4+GT) SA DID + { 0xA73A, 1, 4 } // RaptorLake PS (1+4+GT) SA DID +}; + +void get_num_core_types(uint8_t *num_e_cores, uint8_t *num_p_cores) +{ + uint16_t sa_devid = pci_read_config16(SA_DEV_ROOT, 2); + + *num_p_cores = 0; + *num_e_cores = 0; + + if (pci_read_config16(SA_DEV_ROOT, 0) != 0x8086) + return; + + for (size_t i = 0; i < ARRAY_SIZE(adl_sku_table); i++) { + if (adl_sku_table[i].sa_devid == sa_devid) { + *num_p_cores = adl_sku_table[i].num_p_cores; + *num_e_cores = adl_sku_table[i].num_e_cores; + break; + } + } +} diff --git a/src/soc/intel/alderlake/finalize.c b/src/soc/intel/alderlake/finalize.c index 700fde977b3..615729d3dd3 100644 --- a/src/soc/intel/alderlake/finalize.c +++ b/src/soc/intel/alderlake/finalize.c @@ -85,7 +85,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + tbt_finalize(); if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c index 8a03b05c213..1b9492fa066 100644 --- a/src/soc/intel/alderlake/fsp_params.c +++ b/src/soc/intel/alderlake/fsp_params.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -647,6 +648,7 @@ static uint16_t get_vccin_aux_imon_iccmax(const struct soc_intel_alderlake_confi case PCI_DID_INTEL_RPL_S_ID_3: case PCI_DID_INTEL_RPL_S_ID_4: case PCI_DID_INTEL_RPL_S_ID_5: + case PCI_DID_INTEL_RPL_S_ID_6: return ICC_MAX_RPL_S; default: printk(BIOS_ERR, "Unknown MCH ID: 0x%4x, skipping VccInAuxImonIccMax config\n", @@ -756,9 +758,11 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, */ s_cfg->ITbtConnectTopologyTimeoutInMs = 0; + s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER); + /* D3Hot and D3Cold for TCSS */ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; - s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT); + s_cfg->D3ColdEnable = get_sleep_type_option() == SLEEP_TYPE_OPTION_S0IX; s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { @@ -862,6 +866,8 @@ static void fill_fsps_sata_params(FSP_S_CONFIG *s_cfg, sizeof(s_cfg->SataPortsEnable)); memcpy(s_cfg->SataPortsDevSlp, config->sata_ports_dev_slp, sizeof(s_cfg->SataPortsDevSlp)); + memcpy(s_cfg->SataPortsHotPlug, config->sata_ports_hotplug, + sizeof(s_cfg->SataPortsHotPlug)); } /* @@ -894,7 +900,7 @@ static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, s_cfg->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); /* Set TccActivationOffset */ - s_cfg->TccActivationOffset = config->tcc_offset; + s_cfg->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); } static void fill_fsps_gna_params(FSP_S_CONFIG *s_cfg, @@ -1038,7 +1044,7 @@ static void fill_fsps_pcie_params(FSP_S_CONFIG *s_cfg, } s_cfg->PcieComplianceTestMode = CONFIG(SOC_INTEL_COMPLIANCE_TEST_MODE); -#if CONFIG(FSP_TYPE_IOT) && !CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#if CONFIG(FSP_TYPE_IOT) /* * Intel requires that all enabled PCH PCIe ports have a CLK_REQ signal connected. * The CLK_REQ is used to wake the silicon when link entered L1 link-state. L1 @@ -1184,7 +1190,7 @@ static void fill_fsps_misc_power_params(FSP_S_CONFIG *s_cfg, s_cfg->C1e = config->enable_c1e; else s_cfg->C1e = 1; -#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) +#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_TYPE_IOT) s_cfg->EnableHwpScalabilityTracking = config->enable_hwp_scalability_tracking; #endif } diff --git a/src/soc/intel/alderlake/hsphy.c b/src/soc/intel/alderlake/hsphy.c index 005d85149f4..05e15d452be 100644 --- a/src/soc/intel/alderlake/hsphy.c +++ b/src/soc/intel/alderlake/hsphy.c @@ -4,6 +4,7 @@ #include #include +#include #include #include #include @@ -43,6 +44,8 @@ struct ip_push_model { uint32_t data[]; } __packed; +static bool dma_protection_en = CONFIG(ENABLE_EARLY_DMA_PROTECTION) ? true : false; + static int heci_get_hsphy_payload(void *buf, uint32_t *buf_size, uint8_t *hash_buf, uint8_t *hash_alg, uint32_t *status) { @@ -319,7 +322,7 @@ static void *allocate_hsphy_buf(void) void *hsphy_buf; size_t dma_buf_size; - if (CONFIG(ENABLE_EARLY_DMA_PROTECTION)) { + if (dma_protection_en) { hsphy_buf = vtd_get_dma_buffer(&dma_buf_size); if (!hsphy_buf || dma_buf_size < HSPHY_PAYLOAD_SIZE) { printk(BIOS_ERR, "DMA protection enabled but DMA buffer does not" @@ -360,6 +363,8 @@ void load_and_init_hsphy(void) return; } + dma_protection_en = CONFIG(ENABLE_EARLY_DMA_PROTECTION) && dma_protection_enabled(); + /* * Try to get HSPHY payload from CSME first, so we can always keep our * HSPHY cache up to date. If we cannot allocate the buffer for it, the @@ -400,7 +405,7 @@ void load_and_init_hsphy(void) printk(BIOS_ERR, "%s: CSME not enabled or not visible, but required\n", __func__); printk(BIOS_ERR, "Aborting HSPHY FW loading, PCIe Gen5 won't work.\n"); - if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + if (!dma_protection_en) free(hsphy_buf); return; } @@ -424,7 +429,7 @@ void load_and_init_hsphy(void) cache_hsphy_fw_in_flash(hsphy_buf, buf_size, hsphy_hash, hash_type); - if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + if (!dma_protection_en) free(hsphy_buf); return; } else { @@ -434,7 +439,7 @@ void load_and_init_hsphy(void) printk(BIOS_ERR, "Failed to get HSPHY FW over HECI.\n"); } - if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + if (!dma_protection_en) free(hsphy_buf); /* We failed to get HSPHY payload from CSME, cache is our last chance. */ diff --git a/src/soc/intel/alderlake/include/soc/cpu.h b/src/soc/intel/alderlake/include/soc/cpu.h index d081e85a575..c83f959a0d4 100644 --- a/src/soc/intel/alderlake/include/soc/cpu.h +++ b/src/soc/intel/alderlake/include/soc/cpu.h @@ -35,4 +35,6 @@ enum adl_cpu_type get_adl_cpu_type(void); /* Get a bitmask of supported LPM states */ uint8_t get_supported_lpm_mask(void); +void get_num_core_types(uint8_t *num_e_cores, uint8_t *num_p_cores); + #endif diff --git a/src/soc/intel/alderlake/include/soc/gpio.h b/src/soc/intel/alderlake/include/soc/gpio.h index 1cea6cc766f..1d11fc67c56 100644 --- a/src/soc/intel/alderlake/include/soc/gpio.h +++ b/src/soc/intel/alderlake/include/soc/gpio.h @@ -3,7 +3,7 @@ #ifndef _SOC_ALDERLAKE_GPIO_H_ #define _SOC_ALDERLAKE_GPIO_H_ -#if CONFIG(SOC_INTEL_RAPTORLAKE) && CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#if CONFIG(SOC_INTEL_RAPTORLAKE_PCH_S) #include #define CROS_GPIO_NAME "INTC1085" #define CROS_GPIO_DEVICE_NAME "INTC1085:00" diff --git a/src/soc/intel/alderlake/pmc.c b/src/soc/intel/alderlake/pmc.c index 8930a06251c..58c9fa87712 100644 --- a/src/soc/intel/alderlake/pmc.c +++ b/src/soc/intel/alderlake/pmc.c @@ -108,7 +108,7 @@ static void soc_pmc_fill_ssdt(const struct device *dev) acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Alder Lake IPC Controller"); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index 4a03b7438f5..33be0c8dddc 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -82,7 +84,12 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, enum pcie_rp_typ m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; clk_req_mapping |= 1 << cfg[i].clk_req; } - m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); + /* + * Override the usage only if the clock is unused, otherwise we lose + * FSP_CLK_FREE_RUNNING and FSP_CLK_LAN setting from fill_fspm_pcie_rp_params. + */ + if (m_cfg->PcieClkSrcUsage[cfg[i].clk_src] == FSP_CLK_NOTUSED) + m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = clk_src_to_fsp(type, i); } } @@ -163,7 +170,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->DdrFreqLimit = config->max_dram_speed_mts; m_cfg->DdrSpeedControl = 1; } -#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_USE_REPO) +#if CONFIG(SOC_INTEL_RAPTORLAKE) && !CONFIG(FSP_TYPE_IOT) m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; m_cfg->DisableSagvReorder = config->disable_sagv_reorder; #endif @@ -172,6 +179,8 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_alderlake_config *config) { + uint8_t max_e_cores, max_p_cores; + m_cfg->TsegSize = CONFIG_SMM_TSEG_SIZE; /* CpuRatio Settings */ if (config->cpu_ratio_override) @@ -182,7 +191,28 @@ static void fill_fspm_cpu_params(FSP_M_CONFIG *m_cfg, m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; - m_cfg->HyperThreading = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); + m_cfg->HyperThreading = get_hyper_threading_option(); + + m_cfg->ActiveCoreCount = get_active_core_count_option(); + m_cfg->ActiveSmallCoreCount = get_active_small_core_count_option(); + + get_num_core_types(&max_e_cores, &max_p_cores); + + if (max_e_cores == 0 && max_p_cores == 0) { + /* Could not identify SKU, enable all cores */ + m_cfg->ActiveCoreCount = ALL_CORES_ACTIVE; + m_cfg->ActiveSmallCoreCount = ALL_CORES_ACTIVE; + } + + if (m_cfg->ActiveCoreCount == 0) { + /* Invalid setting, enable all P-cores */ + m_cfg->ActiveCoreCount = ALL_CORES_ACTIVE; + } + + if (max_p_cores == 0 && m_cfg->ActiveSmallCoreCount == 0) { + /* Invalid setting, enable all E-cores */ + m_cfg->ActiveSmallCoreCount = ALL_CORES_ACTIVE; + } } static void fill_fspm_security_params(FSP_M_CONFIG *m_cfg, @@ -316,7 +346,7 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, m_cfg->VtdIgdEnable = m_cfg->InternalGfx; m_cfg->VtdIpuEnable = m_cfg->SaIpuEnable; - m_cfg->PreBootDmaMask = CONFIG(ENABLE_EARLY_DMA_PROTECTION); + m_cfg->PreBootDmaMask = CONFIG(ENABLE_EARLY_DMA_PROTECTION) && dma_protection_enabled(); if (m_cfg->VtdIgdEnable && m_cfg->VtdBaseAddress[VTD_GFX] == 0) { m_cfg->VtdIgdEnable = 0; diff --git a/src/soc/intel/alderlake/spi.c b/src/soc/intel/alderlake/spi.c index 11494251014..3c71efd39be 100644 --- a/src/soc/intel/alderlake/spi.c +++ b/src/soc/intel/alderlake/spi.c @@ -10,7 +10,8 @@ #include #include -#define PSF_SPI_DESTINATION_ID 0x23a8 +#define PCH_LP_PSF_SPI_DESTINATION_ID 0x23a8 +#define PCH_S_PSF_SPI_DESTINATION_ID 0x23b8 int spi_soc_devfn_to_bus(unsigned int devfn) { @@ -29,5 +30,8 @@ int spi_soc_devfn_to_bus(unsigned int devfn) uint32_t soc_get_spi_psf_destination_id(void) { - return PSF_SPI_DESTINATION_ID; + if (CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)) + return PCH_S_PSF_SPI_DESTINATION_ID; + else + return PCH_LP_PSF_SPI_DESTINATION_ID; } diff --git a/src/soc/intel/alderlake/systemagent.c b/src/soc/intel/alderlake/systemagent.c index be0c6996a49..91cd684aa7b 100644 --- a/src/soc/intel/alderlake/systemagent.c +++ b/src/soc/intel/alderlake/systemagent.c @@ -183,7 +183,7 @@ void soc_systemagent_init(struct device *dev) if (sa_pci_id == cpuid_to_adl[i].cpu_id && tdp == cpuid_to_adl[i].cpu_tdp) { soc_config = &config->power_limits_config[cpuid_to_adl[i].limits]; - set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config); + set_power_limits(cpuid_to_adl[i].pl1_time, soc_config); break; } } diff --git a/src/soc/intel/alderlake/vr_config.c b/src/soc/intel/alderlake/vr_config.c index 95dba9fbd03..423c02d3872 100644 --- a/src/soc/intel/alderlake/vr_config.c +++ b/src/soc/intel/alderlake/vr_config.c @@ -170,6 +170,9 @@ static const struct vr_lookup vr_config_ll[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_LOADLINE(1.1, 4.0) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_LOADLINE(1.7, 4.0) }, @@ -240,6 +243,9 @@ static const struct vr_lookup vr_config_icc[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_ICC(120, 30) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_ICC(140, 30) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_ICC(100, 30) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_ICC(307, 30) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_ICC(279, 30) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_ICC(165, 30) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_ICC(215, 30) }, @@ -310,6 +316,9 @@ static const struct vr_lookup vr_config_tdc_timewindow[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC(56000, 56000) }, @@ -380,6 +389,9 @@ static const struct vr_lookup vr_config_tdc_currentlimit[] = { { PCI_DID_INTEL_RPL_S_ID_4, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(51, 22) }, { PCI_DID_INTEL_RPL_S_ID_5, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(69, 22) }, { PCI_DID_INTEL_RPL_S_ID_5, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(44, 22) }, + { PCI_DID_INTEL_RPL_S_ID_6, 125, VR_CFG_ALL_DOMAINS_TDC_CURRENT(140, 22) }, + { PCI_DID_INTEL_RPL_S_ID_6, 65, VR_CFG_ALL_DOMAINS_TDC_CURRENT(94, 22) }, + { PCI_DID_INTEL_RPL_S_ID_6, 35, VR_CFG_ALL_DOMAINS_TDC_CURRENT(57, 22) }, { PCI_DID_INTEL_RPL_HX_ID_1, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, { PCI_DID_INTEL_RPL_HX_ID_2, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, { PCI_DID_INTEL_RPL_HX_ID_3, 55, VR_CFG_ALL_DOMAINS_TDC_CURRENT(89, 22) }, diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 55f59b3bed7..18152a920e8 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -60,14 +60,18 @@ config SOC_INTEL_APOLLOLAKE select SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT select SOC_INTEL_COMMON_BLOCK_GPIO_MULTI_ACPI_DEVICES select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY + select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS - select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG + select SOC_INTEL_COMMON_BLOCK_SMBUS select SOC_INTEL_COMMON_BLOCK_SMM + select SOC_INTEL_COMMON_BLOCK_SMM_NO_MSR_SPCL_CHIPSET_USAGE + select SOC_INTEL_COMMON_BLOCK_TCO + select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_RESET select SOC_INTEL_INTEGRATED_SOUTHCLUSTER diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index a304331f1d3..d4c148504dd 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -56,6 +56,84 @@ Method (_CRS, 0, Serialized) 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, 0x00020000,,,) + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000) + /* * PCI MMIO Region (TOLUD - PCI extended base MMCONF) * This assumes that MMCONF is placed after PCI config space, @@ -75,6 +153,12 @@ Method (_CRS, 0, Serialized) NonCacheable, ReadWrite, 0x00000000, 0x00010000, 0x0001ffff, 0x00000000, 0x00010000,,, PM02) + + /* TPM Area (0xfed40000-0xfed47fff) */ + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0xfed40000, 0xfed47fff, 0x00000000, + 0x00008000) }) /* Find PCI resource area in MCRS */ diff --git a/src/soc/intel/apollolake/acpi/pci_irqs.asl b/src/soc/intel/apollolake/acpi/pci_irqs.asl index b47ac24c3ee..6d557a6fa73 100644 --- a/src/soc/intel/apollolake/acpi/pci_irqs.asl +++ b/src/soc/intel/apollolake/acpi/pci_irqs.asl @@ -58,6 +58,7 @@ Method(_PRT) Package(){0x001DFFFF, 0, 0, UFS_INT}, #endif Package(){0x001EFFFF, 0, 0, SDIO_INT}, - Package(){0x001FFFFF, 0, 0, SMBUS_INT}, + Package(){0x001FFFFF, 0, 0, ESPI_INT}, + Package(){0x001FFFFF, 1, 0, SMBUS_INT}, }) } diff --git a/src/soc/intel/apollolake/acpi/smbus.asl b/src/soc/intel/apollolake/acpi/smbus.asl new file mode 100644 index 00000000000..468e84469d5 --- /dev/null +++ b/src/soc/intel/apollolake/acpi/smbus.asl @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* Intel SMBus Controller 0:1f.4 */ + +Device (SBUS) +{ + Name (_ADR, 0x001f0001) +} diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index f857bb97a07..c7db6049763 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -20,6 +20,9 @@ /* LPC */ #include +/* SMBUS */ +#include "smbus.asl" + /* eMMC */ #include "scs.asl" diff --git a/src/soc/intel/apollolake/chip.c b/src/soc/intel/apollolake/chip.c index ab5b5d884d0..c6730afbab0 100644 --- a/src/soc/intel/apollolake/chip.c +++ b/src/soc/intel/apollolake/chip.c @@ -348,6 +348,10 @@ static void soc_final(void *data) static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig) { switch (dev->path.pci.devfn) { + case PCH_DEVFN_DPTF: + /* FSP does not offer an option to disable DPTF, use DEVEN register */ + pci_update_config32(pcidev_path_on_root(SA_DEVFN_ROOT), 0x54, ~2, 0); + break; case PCH_DEVFN_NPK: /* * Disable this device in the parse_devicetree_setting() function @@ -711,6 +715,9 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->SpiEiss = 0; silconfig->RtcLock = 0; + /* Enable CLKRUN */ + silconfig->PciClockRun = 1; + /* Enable Audio clk gate and power gate */ silconfig->HDAudioClkGate = cfg->hdaudio_clk_gate_enable; silconfig->HDAudioPwrGate = cfg->hdaudio_pwr_gate_enable; @@ -733,6 +740,19 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) silconfig->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD); + /* High Precision Timer options */ + silconfig->HpetBdfValid = 1; + silconfig->HpetBusNumber = 0xFA; + silconfig->HpetDeviceNumber = 0x0F; + silconfig->HpetFunctionNumber = 0; + + /* IO-APIC options */ + silconfig->IoApicId = 2; + silconfig->IoApicBdfValid = 1; + silconfig->IoApicBusNumber = 0xFA; + silconfig->IoApicDeviceNumber = 0x1F; + silconfig->IoApicFunctionNumber = 0; + silconfig->PavpEnable = CONFIG(PAVP); /* SATA config */ @@ -750,6 +770,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd) /* 8254 Timer */ bool use_8254 = get_uint_option("legacy_8254_timer", CONFIG(USE_LEGACY_8254_TIMER)); + /* Timer8254ClkSetting is in fact Timer8254ClkGateEn, so invert the value */ silconfig->Timer8254ClkSetting = !use_8254; /* FSP should let coreboot set subsystem IDs, which are read/write-once */ diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index b8bf39197ea..3c15edbf274 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -28,7 +28,19 @@ #include #include #include -#include +#include + +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + msr_t msr; + msr = rdmsr(IA32_PERF_STATUS); + return ((msr.lo >> 8) & 0xff) * CONFIG_CPU_BCLK_MHZ; +} + +unsigned int smbios_processor_external_clock(void) +{ + return CONFIG_CPU_BCLK_MHZ; +} static const struct reg_script core_msr_script[] = { #if !CONFIG(SOC_INTEL_GEMINILAKE) @@ -76,6 +88,9 @@ void soc_core_init(struct device *cpu) if (CONFIG(SOC_INTEL_COMMON_BLOCK_SGX_ENABLE) || acpi_get_sleep_type() == ACPI_S5) mca_configure(); + /* Enable the local CPU apics */ + enable_lapic_tpr(); + /* Set core MSRs */ reg_script_run(core_msr_script); @@ -91,6 +106,12 @@ void soc_core_init(struct device *cpu) */ enable_pm_timer_emulation(); + /* Enable Direct Cache Access */ + configure_dca_cap(); + + /* Set energy policy */ + set_energy_perf_bias(ENERGY_POLICY_NORMAL); + /* Set Max Non-Turbo ratio if RAPL is disabled. */ if (CONFIG(SOC_INTEL_DISABLE_POWER_LIMITS)) { cpu_set_p_state_to_max_non_turbo_ratio(); diff --git a/src/soc/intel/apollolake/include/soc/irq.h b/src/soc/intel/apollolake/include/soc/irq.h index 8e28ca182b8..e63be223c1e 100644 --- a/src/soc/intel/apollolake/include/soc/irq.h +++ b/src/soc/intel/apollolake/include/soc/irq.h @@ -43,6 +43,7 @@ #define EMMC_INT 39 #define PMC_INT 40 #define SDIO_INT 42 +#define ESPI_INT 43 #define CNVI_INT 44 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/apollolake/include/soc/meminit.h b/src/soc/intel/apollolake/include/soc/meminit.h index aaa5f9b3524..509bbaa7dbb 100644 --- a/src/soc/intel/apollolake/include/soc/meminit.h +++ b/src/soc/intel/apollolake/include/soc/meminit.h @@ -125,6 +125,8 @@ void meminit_lpddr4_by_sku(FSP_M_CONFIG *cfg, void save_lpddr4_dimm_info(const struct lpddr4_cfg *lpcfg, size_t mem_sku); void save_lpddr4_dimm_info_part_num(const char *dram_part_num); +void save_ddr4_dimm_info(void); + /* Retrieve the amount of memory configured in the system in MiB. It's only * valid during romstage. */ size_t memory_in_system_in_mib(void); diff --git a/src/soc/intel/apollolake/include/soc/pci_devs.h b/src/soc/intel/apollolake/include/soc/pci_devs.h index cc31370d93f..e891e127d70 100644 --- a/src/soc/intel/apollolake/include/soc/pci_devs.h +++ b/src/soc/intel/apollolake/include/soc/pci_devs.h @@ -39,6 +39,9 @@ #define SA_GLK_DEV_GMM PCI_DEV(0, SA_GLK_DEV_SLOT_GMM, 0) /* PCH Devices */ +#define PCH_DEV_SLOT_DPTF 0x00 +#define PCH_DEVFN_DPTF _PCH_DEVFN(DPTF, 1) +#define PCH_DEV_DPTF _PCH_DEV(DPTF,1) #define PCH_DEV_SLOT_NPK 0x00 #define PCH_DEVFN_NPK _PCH_DEVFN(NPK, 2) diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index c7a57c8f9dc..8455d08779c 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include +#include +#include #include #include #include @@ -24,9 +27,24 @@ void lpc_soc_init(struct device *dev) const struct soc_intel_apollolake_config *cfg; cfg = config_of(dev); + /* Legacy initialization */ + isa_dma_init(); + pch_misc_init(); + + lpc_enable_pci_clk_cntl(); + /* Set LPC Serial IRQ mode */ lpc_set_serirq_mode(cfg->serirq_mode); + /* Interrupt configuration */ + pch_enable_ioapic(); + pch_pirq_init(); + setup_i8259(); + i8259_configure_irq_trigger(9, 1); + + /* Initialize i8254 timers */ + setup_i8254(); + /* Initialize RTC */ rtc_init(); } diff --git a/src/soc/intel/apollolake/meminit_util_glk.c b/src/soc/intel/apollolake/meminit_util_glk.c index 753451a3530..8016f5fdfc9 100644 --- a/src/soc/intel/apollolake/meminit_util_glk.c +++ b/src/soc/intel/apollolake/meminit_util_glk.c @@ -7,6 +7,9 @@ #include #include #include +#include + +#include #define FSP_SMBIOS_MEMORY_INFO_GUID \ { \ @@ -112,3 +115,109 @@ void save_lpddr4_dimm_info(const struct lpddr4_cfg *lp4cfg, size_t mem_sku) save_lpddr4_dimm_info_part_num(part_num); } + +/* Save the DIMM information for SMBIOS table 17 */ +void save_ddr4_dimm_info(void) +{ + int channel, dimm, dimm_max, index, node; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const FSP_SMBIOS_MEMORY_INFO *memory_info_hob; + const uint8_t smbios_memory_info_guid[16] = + FSP_SMBIOS_MEMORY_INFO_GUID; + + /* Locate the memory info HOB, presence validated by raminit */ + memory_info_hob = + fsp_find_extension_hob_by_guid(smbios_memory_info_guid, + &hob_size); + if (memory_info_hob == NULL || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (mem_info == NULL) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Describe the first N DIMMs in the system */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (node = 0; node < MAX_NODE_NUM; node++) { + ctrlr_info = &memory_info_hob->Controller[node]; + + if (!ctrlr_info->ChannelCount) { + printk(BIOS_DEBUG, "No valid channels on controller %d\n", node); + continue; + } + + for (channel = 0; channel < MAX_CHANNELS_NUM; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + + if (index >= dimm_max) + break; + + if (!channel_info->Status) { + printk(BIOS_DEBUG, "Channel %d not present\n", channel); + continue; + } + + if (!channel_info->DimmCount) { + printk(BIOS_DEBUG, "No valid DIMMs on controller %d channel %d\n", node, channel); + continue; + } + + for (dimm = 0; dimm < MAX_DIMMS_NUM; dimm++) { + if (index >= dimm_max) + break; + + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + + if (!src_dimm->Status) { + printk(BIOS_DEBUG, "DIMM %d/%d/%d not present\n", node, channel, dimm); + continue; + } + + if (!src_dimm->DimmCapacity) { + printk(BIOS_DEBUG, "DIMM %d/%d/%d has 0 capacity\n", node, channel, dimm); + continue; + } + + u8 memProfNum = memory_info_hob->MemoryProfile; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + memory_info_hob->MemoryType, + memory_info_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + (const char *)src_dimm->ModulePartNum, + sizeof(src_dimm->ModulePartNum), + src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL, + memory_info_hob->DataWidth, + memory_info_hob->VddVoltage[memProfNum], + memory_info_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType, + node, + memory_info_hob->MaximumMemoryClockSpeed); + index++; + } // for dimm + } // for channel + } // for node + mem_info->dimm_cnt = index; + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); +} diff --git a/src/soc/intel/apollolake/pmutil.c b/src/soc/intel/apollolake/pmutil.c index 5366ca8bafb..ed445e0e792 100644 --- a/src/soc/intel/apollolake/pmutil.c +++ b/src/soc/intel/apollolake/pmutil.c @@ -93,11 +93,23 @@ uint32_t soc_get_smi_status(uint32_t generic_sts) return generic_sts & ~(1 << GPE0_STS_BIT); } + +/* + * TCO + */ const char *const *soc_tco_sts_array(size_t *a) { static const char *const tco_sts_bits[] = { + [0] = "NMI2SMI", + [1] = "SW_TCO", + [2] = "TCO_INT", [3] = "TIMEOUT", - [17] = "SECOND_TO", + [7] = "NEWCENTURY", + [8] = "BIOSWR", + [9] = "DMISCI", + [10] = "DMISMI", + [12] = "DMISERR", + [13] = "SLVSEL", }; *a = ARRAY_SIZE(tco_sts_bits); diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 09fdbbaae40..01c49909755 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -6,7 +6,6 @@ config SOC_INTEL_BAYTRAIL select ACPI_COMMON_MADT_LAPIC select ACPI_INTEL_HARDWARE_SLEEP_VALUES select ARCH_X86 - select BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES select BOOT_DEVICE_SUPPORTS_WRITES select CACHE_MRC_SETTINGS select CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED @@ -34,6 +33,7 @@ config SOC_INTEL_BAYTRAIL select TCO_SPACE_NOT_YET_SPLIT select USE_DDR3 select NEED_SMALL_2MB_PAGE_TABLES + select UDK_2017_BINDING help Bay Trail M/D part support. @@ -83,7 +83,11 @@ config MRC_BIN_ADDRESS default 0xfffa0000 config MRC_RMT - bool "Enable MRC RMT training + debug prints" + bool "Enable MRC RMT training" + default n + +config MRC_DEBUG_PRINTS + bool "Enable MRC debug prints" default n # Cache As RAM region layout: @@ -158,4 +162,110 @@ config VGA_BIOS_ID depends on VGA_BIOS default "8086,0f31" +config TXE_SECURE_BOOT + bool "Perform verified boot with TXE Secure Boot" + depends on !VBOOT + default n + help + The TXE on Baytrail SOC has Secure Boot capability. Choose this + option to enable the TXE Secure Boot verified boot flow in coreboot. + +config TXE_SB_INCLUDE_KEY_MANIFEST + bool "Include TXE Secure Boot Key Manifest" + depends on TXE_SECURE_BOOT + default n + help + The TXE on Baytrail SOC has Secure Boot capability. Choose this + option to include the TXE Secure Boot Key Manifest, which can be + used to authorize the Secure Boot firmware signing key. This key + should be fused into TXE FPF instead of Secure Boot firmware signing + key. TXE Key Manifest ID FPF must not be zero in such case. + + Key Manifest is optional. + +config TXE_SB_GENERATE_KEY_MANIFEST + bool "Generate TXE Secure Boot Key Manifest" + depends on TXE_SB_INCLUDE_KEY_MANIFEST + default n + help + The TXE on Baytrail SOC has Secure Boot capability. Choose this + option to generate the TXE Secure Boot Key Manifest, which can be + used to authorize the Secure Boot firmware signing key. This key + should be fused into TXE FPF instead of Secure Boot firmware signing + key. TXE Key Manifest ID FPF must not be zero in such case. + + Key Manifest is optional. + +config TXE_SB_KEY_MANIFEST_PATH + string "TXE Secure Boot Key Manifest file path" + depends on TXE_SB_INCLUDE_KEY_MANIFEST && !TXE_SB_GENERATE_KEY_MANIFEST + default "" + help + THe path to a pre-generated TXE Secure Boot Key Manifest to be included + in the coreboot image. + + Key Manifest is optional. + +config TXE_SB_KEY_MANIFEST_KEY_PATH + string "Include TXE Secure Boot Key Manifest Signing Key path" + depends on TXE_SB_GENERATE_KEY_MANIFEST + default "" + help + Path to the signing key used to generate TXE Secure Boot Key Manifest. + RSA2048 private key in PEM or DER format required. + + Key Manifest is optional. + +config TXE_SB_KEY_MANIFEST_ID + int "TXE Secure Boot Key Manifest ID value" + depends on TXE_SB_GENERATE_KEY_MANIFEST + range 1 15 + default 1 + help + Key Manifest ID used to generate TXE Secure Boot Key Manifest. + + Key Manifest is optional. + +config TXE_SB_KEY_MANIFEST_SVN + int "TXE Secure Boot Key Manifest SVN value" + depends on TXE_SB_GENERATE_KEY_MANIFEST + range 0 15 + default 2 + help + Secure Version Number used to generate TXE Secure Boot Key Manifest. + + Key Manifest is optional. + +config TXE_SB_SBM_MANIFEST_KEY_PATH + string "Include TXE Secure Boot Manifest Signing Key path" + depends on TXE_SECURE_BOOT + default "" + help + Path to the signing key used to generate TXE Secure Boot Manifest. + RSA2048 private key in PEM or DER format required. + +config TXE_SB_SBM_MANIFEST_SVN + int "TXE Secure Boot Manifest SVN value" + depends on TXE_SECURE_BOOT + range 0 63 + default 2 + help + Secure Version Number used to generate TXE Secure Boot Manifest. + + Key Manifest is optional. + +if TXE_SECURE_BOOT + +# Put the microcode right after the manifest, so it will be verified by IBB +# and accessible without walkcbfs ASM routine if CBFS_VERIFICATION is enabled. +config CPU_MICROCODE_CBFS_LOC + hex + default 0xfffe1000 + +config CPU_MICROCODE_CBFS_LEN + hex + default 0x19800 + +endif + endif diff --git a/src/soc/intel/baytrail/Makefile.mk b/src/soc/intel/baytrail/Makefile.mk index 281175c9a8d..615d289e144 100644 --- a/src/soc/intel/baytrail/Makefile.mk +++ b/src/soc/intel/baytrail/Makefile.mk @@ -84,4 +84,53 @@ mrc.bin-position := $(shell printf "0x%x" $$(( $(mrcelfentry) - $(mrcelfoffset) mrc.bin-type := mrc endif + +ifeq ($(CONFIG_TXE_SECURE_BOOT),y) + +cbfs-files-y += manifests.bin +manifests.bin-file := $(objcbfs)/sb_manifests +manifests.bin-type := raw + +ifeq ($(CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST),y) + +manifests.bin-COREBOOT-position := $(call int-subtract, 0x100000000 0x21000) + +ifneq ($(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH)),) + +$(objcbfs)/sb_manifests: $(call strip_quotes,$(CONFIG_TXE_SB_KEY_MANIFEST_PATH)) + dd if=/dev/zero of=$@ bs=5120 count=1 2> /dev/null + dd if=$< of=$@ conv=notrunc 2> /dev/null +else + +$(objcbfs)/sb_manifests: + dd if=/dev/zero of=$@ bs=5120 count=1 2> /dev/null + endif + +else # CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST + +manifests.bin-COREBOOT-position := $(call int-subtract, 0x100000000 0x20000) + +$(objcbfs)/sb_manifests: + dd if=/dev/zero of=$@ bs=1024 count=1 2> /dev/null + +endif # CONFIG_TXE_SB_INCLUDE_KEY_MANIFEST + +files_added:: $(obj)/coreboot.rom $(TXESBMANTOOL) + if [ "$(CONFIG_TXE_SB_GENERATE_KEY_MANIFEST)" = 'y' ]; then \ + $(TXESBMANTOOL) $(obj)/coreboot.rom generate-km \ + --sbm-key-file $(CONFIG_TXE_SB_SBM_MANIFEST_KEY_PATH) \ + --km-key-file $(CONFIG_TXE_SB_KEY_MANIFEST_KEY_PATH) \ + --km-id $(CONFIG_TXE_SB_KEY_MANIFEST_ID) \ + --svn $(CONFIG_TXE_SB_KEY_MANIFEST_SVN) \ + ;\ + printf " TXE Secure Boot Key Manifest generated.\n"; \ + fi; \ + $(TXESBMANTOOL) $(obj)/coreboot.rom generate-sbm \ + --sbm-key-file $(CONFIG_TXE_SB_SBM_MANIFEST_KEY_PATH) \ + --svn $(CONFIG_TXE_SB_SBM_MANIFEST_SVN) ;\ + printf " TXE Secure Boot Manifest generated.\n\n"; \ + +endif # CONFIG_TXE_SECURE_BOOT + +endif # CONFIG_SOC_INTEL_BAYTRAIL diff --git a/src/soc/intel/baytrail/acpi/lpc.asl b/src/soc/intel/baytrail/acpi/lpc.asl index 5933070a6b2..e41fcc09601 100644 --- a/src/soc/intel/baytrail/acpi/lpc.asl +++ b/src/soc/intel/baytrail/acpi/lpc.asl @@ -118,6 +118,23 @@ Device (LPCB) }) } +#if CONFIG(ENABLE_BUILTIN_COM1) + Device (COM1) { + Name (_HID, EISAID ("PNP0501")) + Name (_UID, 1) + + Method (_STA, 0, NotSerialized) { + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x03F8, 0x3F8, 0x08, 0x08) + IRQNoFlags () {4} + }) + } +#endif + /* Include mainboard's superio.asl file. */ #include "acpi/superio.asl" } diff --git a/src/soc/intel/baytrail/bootblock/bootblock.c b/src/soc/intel/baytrail/bootblock/bootblock.c index 3f07a6b4396..d1bd2b9d381 100644 --- a/src/soc/intel/baytrail/bootblock/bootblock.c +++ b/src/soc/intel/baytrail/bootblock/bootblock.c @@ -66,15 +66,21 @@ static void spi_init(void) static void byt_config_com1_and_enable(void) { - uint32_t reg; + uint32_t reg32; - /* Enable the UART hardware for COM1. */ - reg = 1; - pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, reg); + /* Enable COM1 for debug message output. */ + reg32 = read32((const volatile void *)(PMC_BASE_ADDRESS + GEN_PMCON1)); + reg32 &= ~(SUS_PWR_FLR | PWR_FLR); + reg32 |= UART_EN; + write32 ((volatile void *)(PMC_BASE_ADDRESS + GEN_PMCON1), reg32); /* Set up the pads to select the UART function */ + ssus_enable_internal_pull(UART_RXD_PAD, PAD_PU_2K | PAD_PULL_UP); score_select_func(UART_RXD_PAD, 1); score_select_func(UART_TXD_PAD, 1); + + /* Enable the legacy UART hardware. */ + pci_write_config32(PCI_DEV(0, LPC_DEV, 0), UART_CONT, 1); } static void setup_mmconfig(void) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index 2a4616cec35..81c0212aab9 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -14,12 +14,38 @@ #include #include #include +#include #include #include #include #include #include +unsigned int smbios_cpu_get_current_speed_mhz(void) +{ + unsigned int ratio = (rdmsr(IA32_PERF_STATUS).lo >> 8) & 0x1f; + + return bus_freq_khz() * ratio / 1000; +} + +unsigned int smbios_processor_external_clock(void) +{ + return bus_freq_khz() / 1000; +} + +unsigned int smbios_cpu_get_max_speed_mhz(void) +{ + unsigned int ratio = (rdmsr(IA32_PLATFORM_ID).lo >> 8) & 0x1f; + + return bus_freq_khz() * ratio / 1000; +} + +unsigned int smbios_processor_family(struct cpuid_result res) +{ + return 0x2b; /* Intel Atom */ +} + + /* Core level MSRs */ static const struct reg_script core_msr_script[] = { /* Dynamic L2 shrink enable and threshold, clear SINGLE_PCTL bit 11 */ diff --git a/src/soc/intel/baytrail/include/soc/gpio.h b/src/soc/intel/baytrail/include/soc/gpio.h index 0b19922f14d..ba94c5d5bea 100644 --- a/src/soc/intel/baytrail/include/soc/gpio.h +++ b/src/soc/intel/baytrail/include/soc/gpio.h @@ -233,7 +233,7 @@ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_INPUT, } -#define GPIO_OUT_LOW \ +#define GPIO_OUT_LOW_LEGACY \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ @@ -242,7 +242,7 @@ .gp_lvl = GPIO_LEVEL_LOW, \ .is_gpio = 1 } -#define GPIO_OUT_HIGH \ +#define GPIO_OUT_HIGH_LEGACY \ { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ .pad_conf1 = PAD_CONFIG1_DEFAULT, \ .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ @@ -251,6 +251,24 @@ .gp_lvl = GPIO_LEVEL_HIGH, \ .is_gpio = 1 } +#define GPIO_OUT_LOW \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_LOW, \ + .use_sel = GPIO_USE_MMIO, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_LOW, \ + .is_gpio = 1 } + +#define GPIO_OUT_HIGH \ + { .pad_conf0 = PAD_PULL_DISABLE | PAD_CONFIG0_DEFAULT, \ + .pad_conf1 = PAD_CONFIG1_DEFAULT, \ + .pad_val = PAD_VAL_OUTPUT | PAD_VAL_HIGH, \ + .use_sel = GPIO_USE_MMIO, \ + .io_sel = GPIO_DIR_OUTPUT, \ + .gp_lvl = GPIO_LEVEL_HIGH, \ + .is_gpio = 1 } + /* Define no-pull / PU / PD configs for each functional config option */ #define GPIO_FUNC(_func, _pudir, _str) \ { .use_sel = GPIO_USE_MMIO, \ @@ -448,4 +466,32 @@ static inline void ssus_enable_internal_pull(int pad, int mask) (read32(ssus_pconf0(pad)) & pull_mask) | mask); } +static inline void setup_ssus_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val) +{ + uint32_t reg; + uint32_t *pad_addr = ssus_pconf0(gpio_num); + /* + * Pad Configuration 0 Register + * 2:0 - func_pin_mux + * 8:7 - Pull assignment: 00 - Non pull 01 - Pull Up 10 - Pull down + * 11 - reserved + * 10:9 - Pull strength: 00 - 2K 01 - 10K 10 - 20K 11 - 40K + */ + reg = PAD_CONFIG0_DEFAULT; + reg |= pconf0 & 0x787; + write32(pad_addr + (PAD_CONF0_REG/sizeof(u32)), reg); + + /* + * Pad Value Register + * 0: Pad value + * 1: output enable (0 is enabled) + * 2: input enable (0 is enabled) + */ + reg = read32(pad_addr + (PAD_VAL_REG/sizeof(u32))); + reg &= ~0x7; + reg |= pad_val & 0x7; + write32(pad_addr + (PAD_VAL_REG/sizeof(u32)), reg); +} + + #endif /* _BAYTRAIL_GPIO_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/irq.h b/src/soc/intel/baytrail/include/soc/irq.h index 3a1d7c79e42..e13cae82a46 100644 --- a/src/soc/intel/baytrail/include/soc/irq.h +++ b/src/soc/intel/baytrail/include/soc/irq.h @@ -77,7 +77,6 @@ #define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) /* PIC IRQ settings. */ -#define PIRQ_PIC_IRQDISABLE 0x0 #define PIRQ_PIC_IRQ3 0x3 #define PIRQ_PIC_IRQ4 0x4 #define PIRQ_PIC_IRQ5 0x5 @@ -89,6 +88,8 @@ #define PIRQ_PIC_IRQ12 0xc #define PIRQ_PIC_IRQ14 0xe #define PIRQ_PIC_IRQ15 0xf +#define PIRQ_PIC_IRQDISABLE 0x80 +#define PIRQ_PIC_UNKNOWN_UNUSED 0xff /* Overloaded term, but these values determine the per device route. */ #define PIRQA 0 @@ -110,7 +111,7 @@ # define SCIS_IRQ21 0x05 # define SCIS_IRQ22 0x06 # define SCIS_IRQ23 0x07 - +#define ILB_MC 0x04 /* * In each mainboard directory there should exist a header file irqroute.h that * defines the PCI_DEV_PIRQ_ROUTES and PIRQ_PIC_ROUTES macros which diff --git a/src/soc/intel/baytrail/include/soc/lpc.h b/src/soc/intel/baytrail/include/soc/lpc.h index 7b3fbf8c900..6fb1aa8ed5e 100644 --- a/src/soc/intel/baytrail/include/soc/lpc.h +++ b/src/soc/intel/baytrail/include/soc/lpc.h @@ -36,4 +36,14 @@ enum baytrail_stepping { #define GCS 0x00 # define BILD (1 << 0) +/* iLB Memory Mapped IO */ +#define ILB_OIC 0x60 +#define SIRQEN (1 << 12) +#define AEN (1 << 8) + +/* Memory Mapped IO in LPC bridge */ +#define ILB_SERIRQ_CNTL 0x10 +#define SCNT_CONTINUOUS_MODE (1 << 7) +#define SCNT_QUIET_MODE 0 + #endif /* _BAYTRAIL_LPC_H_ */ diff --git a/src/soc/intel/baytrail/include/soc/pci_devs.h b/src/soc/intel/baytrail/include/soc/pci_devs.h index 74acb8ea45c..dff1307fa84 100644 --- a/src/soc/intel/baytrail/include/soc/pci_devs.h +++ b/src/soc/intel/baytrail/include/soc/pci_devs.h @@ -13,6 +13,10 @@ #define GFX_DEV 0x2 #define GFX_FUNC 0 +/* MIPI */ +#define MIPI_DEV 0x3 +#define MIPI_FUNC 0 + /* MMC Port */ #define MMC_DEV 0x10 #define MMC_FUNC 0 @@ -37,6 +41,10 @@ #define LPE_DEV 0x15 #define LPE_FUNC 0 +/* OTG */ +#define OTG_DEV 0x16 +#define OTG_FUNC 0 + /* MMC45 Port */ #define MMC45_DEV 0x17 #define MMC45_FUNC 0 @@ -107,6 +115,7 @@ #define SOC_DEVID 0x0f00 #define GFX_DEVID 0x0f31 +#define MIPI_DEVID 0x0f38 #define MMC_DEVID 0x0f14 #define SDIO_DEVID 0x0f15 #define SD_DEVID 0x0f16 @@ -116,6 +125,7 @@ #define AHCI2_DEVID 0x0f23 #define XHCI_DEVID 0x0f35 #define LPE_DEVID 0x0f28 +#define OTG_DEVID 0x0f37 #define MMC45_DEVID 0x0f50 #define SIO_DMA1_DEVID 0x0f40 #define I2C1_DEVID 0x0f41 diff --git a/src/soc/intel/baytrail/include/soc/pm.h b/src/soc/intel/baytrail/include/soc/pm.h index dea44733833..9d276ec1343 100644 --- a/src/soc/intel/baytrail/include/soc/pm.h +++ b/src/soc/intel/baytrail/include/soc/pm.h @@ -66,10 +66,13 @@ #define HSUART1_DIS (1 << 3) #define HSUART2_DIS (1 << 4) #define SPI_DIS (1 << 5) -#define MMC_DIS (1 << 8) +/* Baytrail EDS says this should be 11 but it appears to be wrong */ +#define MIPI_DIS (1 << 8) #define SDIO_DIS (1 << 9) #define SD_DIS (1 << 10) -#define MMC45_DIS (1 << 11) +/* Baytrail EDS says these should be 8 but it appears to be wrong */ +#define MMC45_DIS (1 << 11) +#define MMC_DIS (1 << 11) #define HDA_DIS (1 << 12) #define LPE_DIS (1 << 13) #define OTG_DIS (1 << 14) diff --git a/src/soc/intel/baytrail/lpss.c b/src/soc/intel/baytrail/lpss.c index fa1b957ba12..9ed7c3b6d1f 100644 --- a/src/soc/intel/baytrail/lpss.c +++ b/src/soc/intel/baytrail/lpss.c @@ -8,6 +8,7 @@ #include #include +#include #include #include #include @@ -104,6 +105,55 @@ static void dev_ctl_reg(struct device *dev, int *iosf_reg, int *nvs_index) } #define CASE_I2C(name_) case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC) +#define PIN_SET_FOR_I2C 0x2003C881 + +static void i2c_set_pins(struct device *dev) +{ + switch (dev->path.pci.devfn) { + CASE_I2C(I2C1) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0210), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0200), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C2) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x01F0), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x01E0), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C3) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x01D0), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x01B0), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C4) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0190), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x01C0), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C5) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x01A0), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0170), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C6) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0150), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0140), + PIN_SET_FOR_I2C); + break; + CASE_I2C(I2C7) : + write32((volatile void *)(IO_BASE_ADDRESS + 0x0180), + PIN_SET_FOR_I2C); + write32((volatile void *)(IO_BASE_ADDRESS + 0x0160), + PIN_SET_FOR_I2C); + break; + } +} static void i2c_disable_resets(struct device *dev) { @@ -144,6 +194,7 @@ static void lpss_init(struct device *dev) } dev_enable_snoop_and_pm(dev, iosf_reg); i2c_disable_resets(dev); + i2c_set_pins(dev); if (config->lpss_acpi_mode) dev_enable_acpi_mode(dev, iosf_reg, nvs_index); diff --git a/src/soc/intel/baytrail/romstage/raminit.c b/src/soc/intel/baytrail/romstage/raminit.c index 6244072c55c..37565317f74 100644 --- a/src/soc/intel/baytrail/romstage/raminit.c +++ b/src/soc/intel/baytrail/romstage/raminit.c @@ -50,7 +50,8 @@ int smbus_enable_iobar(uintptr_t base) static void ABI_X86 send_to_console(unsigned char b) { - do_putchar(b); + if (CONFIG(MRC_DEBUG_PRINTS)) + do_putchar(b); } static void populate_smbios_tables(void *dram_data, int speed, int num_channels) diff --git a/src/soc/intel/baytrail/romstage/romstage.c b/src/soc/intel/baytrail/romstage/romstage.c index 658da2c44b0..c1d6a08dc5a 100644 --- a/src/soc/intel/baytrail/romstage/romstage.c +++ b/src/soc/intel/baytrail/romstage/romstage.c @@ -85,6 +85,16 @@ static int chipset_prev_sleep_state(const struct chipset_power_state *ps) return prev_sleep_state; } +static void print_txe_status(const char* timepoint) +{ + pci_devfn_t txe = PCI_DEV(0, TXE_DEV, TXE_FUNC); + + printk(BIOS_DEBUG, "TXE status %s\n", timepoint); + printk(BIOS_DEBUG, "TXE SEC FWSTS0 %08x\n", pci_read_config32(txe, 0x40)); + printk(BIOS_DEBUG, "TXE SEC FWSTS1 %08x\n", pci_read_config32(txe, 0x48)); + printk(BIOS_DEBUG, "TXE SB STATUS %08x\n", pci_read_config32(txe, 0x50)); +} + /* Entry from cpu/intel/car/romstage.c */ void mainboard_romstage_entry(void) { @@ -112,9 +122,13 @@ void mainboard_romstage_entry(void) elog_boot_notify(s3resume); + print_txe_status("before MRC"); + /* Initialize RAM */ raminit(&mp, prev_sleep_state); + print_txe_status("after MRC"); + timestamp_add_now(TS_INITRAM_END); romstage_handoff_init(s3resume); diff --git a/src/soc/intel/baytrail/southcluster.c b/src/soc/intel/baytrail/southcluster.c index 1afea590a23..45c61d30f69 100644 --- a/src/soc/intel/baytrail/southcluster.c +++ b/src/soc/intel/baytrail/southcluster.c @@ -2,6 +2,8 @@ #include #include +#include +#include #include #include #include @@ -11,6 +13,9 @@ #include #include #include +#include +#include +#include #include #include @@ -135,30 +140,265 @@ static void com1_configure_resume(struct device *dev) outb(3, port + UART8250_LCR); } -static void sc_init(struct device *dev) + +static void sc_enable_ioapic(struct device *dev) { int i; + u32 reg32; + volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR); + volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10); + u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f); + + /* + * Enable ACPI I/O and power management. + * Set SCI IRQ to IRQ9 + */ + write32(ilb_base + ILB_OIC, 0x100); /* AEN */ + reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */ + write32(ilb_base + ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */ + + *ioapic_index = 0; + *ioapic_data = (1 << 25); + + /* affirm full set of redirection table entries ("write once") */ + *ioapic_index = 1; + reg32 = *ioapic_data; + *ioapic_index = 1; + *ioapic_data = reg32; + + *ioapic_index = 0; + reg32 = *ioapic_data; + printk(BIOS_DEBUG, "Southbridge APIC ID = %x\n", (reg32 >> 24) & 0x0f); + if (reg32 != (1 << 25)) + die("APIC Error\n"); + + printk(BIOS_SPEW, "Dumping IOAPIC registers\n"); + for (i=0; i<3; i++) { + *ioapic_index = i; + printk(BIOS_SPEW, " reg 0x%04x:", i); + reg32 = *ioapic_data; + printk(BIOS_SPEW, " 0x%08x\n", reg32); + } + + *ioapic_index = 3; /* Select Boot Configuration register. */ + *ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */ +} + +static void sc_enable_serial_irqs(struct device *dev) +{ +#ifdef SETUPSERIQ /* NOT defined. Remove when the TODO is done. */ + /* + * TODO: SERIRQ seems to have a number of problems on baytrail. + * With it enabled, we get some spurious interrupts (ps2) + * in seabios. It also caused IOCHK# NMIs. Remove it + * until we understand how it needs to be configured. + */ + u8 reg8; + u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); + + /* + * Disable the IOCHK# NMI. Let the NMI handler enable it if it needs. + */ + reg8 = inb(0x61); + reg8 &= 0x0f; /* Higher Nibble must be 0 */ + reg8 |= (1 << 3); /* IOCHK# NMI Disable for now */ + outb(reg8, 0x61); + + write32(ibase + ILB_OIC, read32(ibase + ILB_OIC) | SIRQEN); + write8(ibase + ILB_SERIRQ_CNTL, SCNT_CONTINUOUS_MODE); + + if (!CONFIG(SERIRQ_CONTINUOUS_MODE)) { + /* + * SoC requires that the System BIOS first set the SERIRQ logic to + * continuous mode operation for at least one frame before switching + * it into quiet mode operation. + */ + outb(0x00, 0xED); /* I/O Delay to get the 1 frame */ + write8(ibase + ILB_SERIRQ_CNTL, SCNT_QUIET_MODE); + } +#endif /* DON'T SET UP IRQS */ +} + +/* + * Write PCI config space IRQ assignments. PCI devices have the INT_LINE + * (0x3C) and INT_PIN (0x3D) registers which report interrupt routing + * information to operating systems and drivers. The INT_PIN register is + * generally read only and reports which interrupt pin A - D it uses. The + * INT_LINE register is configurable and reports which IRQ (generally the + * PIC IRQs 1 - 15) it will use. This needs to take interrupt pin swizzling + * on devices that are downstream on a PCI bridge into account. + * + * This function will loop through all enabled PCI devices and program the + * INT_LINE register with the correct PIC IRQ number for the INT_PIN that it + * uses. It then configures each interrupt in the pic to be level triggered. + */ +static void write_pci_config_irqs(void) +{ + struct device *irq_dev; + struct device *targ_dev; + uint8_t int_line = 0; + uint8_t original_int_pin = 0; + uint8_t new_int_pin = 0; + uint16_t current_bdf = 0; + uint16_t parent_bdf = 0; + uint8_t pirq = 0; + uint8_t device_num = 0; + const struct baytrail_irq_route *ir = &global_baytrail_irq_route; + + if (ir == NULL) { + printk(BIOS_WARNING, "Warning: Can't write PCI IRQ assignments because" + " 'global_baytrail_irq_route' structure does not exist\n"); + return; + } + + /* + * Loop through all enabled devices and program their + * INT_LINE, INT_PIN registers from values taken from + * the Interrupt Route registers in the ILB + */ + printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PCI config space IRQ assignments\n"); + for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) { + + if ((irq_dev->path.type != DEVICE_PATH_PCI) || + (!irq_dev->enabled)) + continue; + + current_bdf = irq_dev->path.pci.devfn | + irq_dev->upstream->secondary << 8; + + /* + * Step 1: Get the INT_PIN and device structure to look for + * in the pirq_data table defined in the mainboard directory. + */ + targ_dev = NULL; + new_int_pin = get_pci_irq_pins(irq_dev, &targ_dev); + if (targ_dev == NULL || new_int_pin < 1) + continue; + + /* + * Adjust the INT routing for the PCIe root ports + * See 'Interrupt Generated for INT[A-D] Interrupts' + * Table 241 in Document Number: 538136, Rev. 3.9 + */ + if (PCI_SLOT(targ_dev->path.pci.devfn) == PCIE_DEV && + targ_dev != irq_dev) + new_int_pin = ((new_int_pin - 1 + + PCI_FUNC(targ_dev->path.pci.devfn)) % 4) + 1; + + /* Get the original INT_PIN for record keeping */ + original_int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + + parent_bdf = targ_dev->path.pci.devfn + | targ_dev->upstream->secondary << 8; + device_num = PCI_SLOT(parent_bdf); + + /* Find the PIRQ that is attached to the INT_PIN this device uses */ + pirq = (ir->pcidev[device_num] >> ((new_int_pin - 1) * 4)) & 0xF; + + /* Get the INT_LINE this device/function will use */ + int_line = ir->pic[pirq]; + + if (int_line != PIRQ_PIC_IRQDISABLE) { + /* Set this IRQ to level triggered since it is used by a PCI device */ + i8259_configure_irq_trigger(int_line, IRQ_LEVEL_TRIGGERED); + /* Set the Interrupt Line register in PCI config space */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); + } else { + /* Set the Interrupt line register as "unknown or unused" */ + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, + PIRQ_PIC_UNKNOWN_UNUSED); + } + + printk(BIOS_SPEW, "\tINT_PIN\t\t: %d (%s)\n", + original_int_pin, pin_to_str(original_int_pin)); + if (parent_bdf != current_bdf) + printk(BIOS_SPEW, "\tSwizzled to\t: %d (%s)\n", + new_int_pin, pin_to_str(new_int_pin)); + printk(BIOS_SPEW, "\tPIRQ\t\t: %c\n" + "\tINT_LINE\t: 0x%X (IRQ %d)\n", + 'A' + pirq, int_line, int_line); + } + printk(BIOS_DEBUG, "PCI_CFG IRQ: Finished writing PCI config space IRQ assignments\n"); +} + +static void sc_pirq_init(struct device *dev) +{ + int i, j; + int pirq; u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08); u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20); - u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL); const struct baytrail_irq_route *ir = &global_baytrail_irq_route; - struct soc_intel_baytrail_config *config = config_of(dev); /* Set up the PIRQ PIC routing based on static config. */ + printk(BIOS_SPEW, "Start writing IRQ assignments\n" + "PIRQ\tA\tB\tC\tD\tE\tF\tG\tH\n" + "IRQ "); for (i = 0; i < NUM_PIRQS; i++) { write8(pr_base + i, ir->pic[i]); + printk(BIOS_SPEW, "\t%d", ir->pic[i]); } - /* Set up the per device PIRQ routing base on static config. */ - for (i = 0; i < NUM_IR_DEVS; i++) { + printk(BIOS_SPEW, "\n\n"); + + /* Set up the per device PIRQ routing based on static config. */ + printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n" + "Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n"); + for (i = 0; i < 32; i++) { write16(ir_base + i, ir->pcidev[i]); + + /* If the entry is more than just 0, print it out */ + if (ir->pcidev[i]) { + printk(BIOS_SPEW, " %d: ", i); + for (j = 0; j < 4; j++) { + pirq = (ir->pcidev[i] >> (j * 4)) & 0xF; + printk(BIOS_SPEW, "\t%-4c (%d)", 'A' + pirq, ir->pic[pirq]); + } + printk(BIOS_SPEW, "\n"); + } } /* Route SCI to IRQ9 */ write32(actl, (read32(actl) & ~SCIS_MASK) | SCIS_IRQ9); + printk(BIOS_SPEW, "Finished writing IRQ assignments\n"); + + /* Write IRQ assignments to PCI config space */ + write_pci_config_irqs(); +} + +static void sc_init(struct device *dev) +{ + struct soc_intel_baytrail_config *config = config_of(dev); + u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1); + u8 *ibase; + + printk(BIOS_DEBUG, "soc: southcluster_init\n"); + + ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF); + + write8(ibase + ILB_MC, 0); cmos_init(rtc_failure()); + /* Set the value for PCI command register. */ + pci_write_config16(dev, PCI_COMMAND, + PCI_COMMAND_IO | PCI_COMMAND_MEMORY | + PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL); + + /* IO APIC initialization. */ + sc_enable_ioapic(dev); + + sc_enable_serial_irqs(dev); + + /* Setup the PIRQ. */ + sc_pirq_init(dev); + + /* Initialize ISA DMA. */ + isa_dma_init(); + + setup_i8259(); + + setup_i8254(); + if (config->disable_slp_x_stretch_sus_fail) { printk(BIOS_DEBUG, "Disabling slp_x stretching.\n"); write32(gen_pmcon1, read32(gen_pmcon1) | DIS_SLP_X_STRCH_SUS_UP); @@ -175,6 +415,14 @@ static void sc_init(struct device *dev) * Common code for the south cluster devices. */ +#define SET_DIS_MASK(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask |= name_ ## _DIS +#define SET_DIS_MASK2(name_) \ + case PCI_DEVFN(name_ ## _DEV, name_ ## _FUNC): \ + mask2 |= name_ ## _DIS + + /* Set bit in function disable register to hide this device. */ static void sc_disable_devfn(struct device *dev) { @@ -184,94 +432,72 @@ static void sc_disable_devfn(struct device *dev) uint32_t mask2 = 0; switch (dev->path.pci.devfn) { - case PCI_DEVFN(MMC_DEV, MMC_FUNC): - mask |= MMC_DIS; + SET_DIS_MASK(MIPI); break; - case PCI_DEVFN(SDIO_DEV, SDIO_FUNC): - mask |= SDIO_DIS; + SET_DIS_MASK(SDIO); break; - case PCI_DEVFN(SD_DEV, SD_FUNC): - mask |= SD_DIS; + SET_DIS_MASK(SD); break; - case PCI_DEVFN(SATA_DEV, SATA_FUNC): - mask |= SATA_DIS; + SET_DIS_MASK(SATA); break; - case PCI_DEVFN(XHCI_DEV, XHCI_FUNC): - mask |= XHCI_DIS; + SET_DIS_MASK(XHCI); /* Disable super speed PHY when XHCI is not available. */ mask2 |= USH_SS_PHY_DIS; break; - case PCI_DEVFN(LPE_DEV, LPE_FUNC): - mask |= LPE_DIS; + SET_DIS_MASK(LPE); break; - case PCI_DEVFN(MMC45_DEV, MMC45_FUNC): - mask |= MMC45_DIS; + SET_DIS_MASK(MMC); break; - case PCI_DEVFN(SIO_DMA1_DEV, SIO_DMA1_FUNC): - mask |= SIO_DMA1_DIS; + SET_DIS_MASK(MMC45); break; - case PCI_DEVFN(I2C1_DEV, I2C1_FUNC): - mask |= I2C1_DIS; + SET_DIS_MASK(SIO_DMA1); break; - case PCI_DEVFN(I2C2_DEV, I2C2_FUNC): - mask |= I2C1_DIS; + SET_DIS_MASK(I2C1); break; - case PCI_DEVFN(I2C3_DEV, I2C3_FUNC): - mask |= I2C3_DIS; + SET_DIS_MASK(I2C2); break; - case PCI_DEVFN(I2C4_DEV, I2C4_FUNC): - mask |= I2C4_DIS; + SET_DIS_MASK(I2C3); break; - case PCI_DEVFN(I2C5_DEV, I2C5_FUNC): - mask |= I2C5_DIS; + SET_DIS_MASK(I2C4); break; - case PCI_DEVFN(I2C6_DEV, I2C6_FUNC): - mask |= I2C6_DIS; + SET_DIS_MASK(I2C5); break; - case PCI_DEVFN(I2C7_DEV, I2C7_FUNC): - mask |= I2C7_DIS; + SET_DIS_MASK(I2C6); break; - case PCI_DEVFN(TXE_DEV, TXE_FUNC): - mask |= TXE_DIS; + SET_DIS_MASK(I2C7); break; - case PCI_DEVFN(HDA_DEV, HDA_FUNC): - mask |= HDA_DIS; + SET_DIS_MASK(TXE); break; - case PCI_DEVFN(PCIE_PORT1_DEV, PCIE_PORT1_FUNC): - mask |= PCIE_PORT1_DIS; + SET_DIS_MASK(HDA); break; - case PCI_DEVFN(PCIE_PORT2_DEV, PCIE_PORT2_FUNC): - mask |= PCIE_PORT2_DIS; + SET_DIS_MASK(PCIE_PORT1); break; - case PCI_DEVFN(PCIE_PORT3_DEV, PCIE_PORT3_FUNC): - mask |= PCIE_PORT3_DIS; + SET_DIS_MASK(PCIE_PORT2); break; - case PCI_DEVFN(PCIE_PORT4_DEV, PCIE_PORT4_FUNC): - mask |= PCIE_PORT4_DIS; + SET_DIS_MASK(PCIE_PORT3); break; - case PCI_DEVFN(EHCI_DEV, EHCI_FUNC): - mask |= EHCI_DIS; + SET_DIS_MASK(PCIE_PORT4); break; - case PCI_DEVFN(SIO_DMA2_DEV, SIO_DMA2_FUNC): - mask |= SIO_DMA2_DIS; + SET_DIS_MASK2(SMBUS); break; - case PCI_DEVFN(PWM1_DEV, PWM1_FUNC): - mask |= PWM1_DIS; + SET_DIS_MASK(EHCI); break; - case PCI_DEVFN(PWM2_DEV, PWM2_FUNC): - mask |= PWM2_DIS; + SET_DIS_MASK(SIO_DMA2); break; - case PCI_DEVFN(HSUART1_DEV, HSUART1_FUNC): - mask |= HSUART1_DIS; + SET_DIS_MASK(PWM1); break; - case PCI_DEVFN(HSUART2_DEV, HSUART2_FUNC): - mask |= HSUART2_DIS; + SET_DIS_MASK(PWM2); break; - case PCI_DEVFN(SPI_DEV, SPI_FUNC): - mask |= SPI_DIS; + SET_DIS_MASK(HSUART1); break; - case PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC): - mask2 |= SMBUS_DIS; + SET_DIS_MASK(HSUART2); + break; + SET_DIS_MASK(SPI); + break; + + SET_DIS_MASK(OTG); + /* Disable OTG PHY when OTG is not available. */ + mask2 |= OTG_SS_PHY_DIS; break; } @@ -526,6 +752,8 @@ static void finalize_chipset(void *unused) write32(spi + UVSCC, cfg.uvscc); write32(spi + LVSCC, cfg.lvscc | VCL); } + + apm_control(APM_CNT_FINALIZE); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 59b09a5d332..a37a9ec54e8 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -22,6 +22,7 @@ config SOC_INTEL_CANNONLAKE_BASE select HAVE_FSP_LOGO_SUPPORT select HAVE_HYPERTHREADING select HAVE_INTEL_FSP_REPO + select HAVE_INTEL_ME_HAP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -51,6 +52,7 @@ config SOC_INTEL_CANNONLAKE_BASE select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_ME_SPEC_12 + select SOC_INTEL_COMMON_BLOCK_OC_WDT select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS @@ -95,7 +97,7 @@ config SOC_INTEL_COMETLAKE select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BASECODE_RAMTOP if CHROMEOS config SOC_INTEL_COMETLAKE_1 bool @@ -324,10 +326,25 @@ config PRERAM_CBMEM_CONSOLE_SIZE hex default 0xe00 +config SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS + default 300 + +if INTEL_TXT + config INTEL_TXT_BIOSACM_ALIGNMENT - hex default 0x40000 # 256KB +config INTEL_TXT_DPR_SIZE + default 4 + +config INTEL_TXT_SINIT_SIZE + default 0x50000 + +config INTEL_TXT_HEAP_SIZE + default 0xf0000 + +endif + config INTEL_GMA_BCLV_OFFSET default 0xc8258 diff --git a/src/soc/intel/cannonlake/finalize.c b/src/soc/intel/cannonlake/finalize.c index 974794bd977..461ba3a884e 100644 --- a/src/soc/intel/cannonlake/finalize.c +++ b/src/soc/intel/cannonlake/finalize.c @@ -87,7 +87,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC)) heci1_disable(); diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index df5fcee36f1..488780bc892 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -670,7 +671,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) #endif /* Set TccActivationOffset */ - tconfig->TccActivationOffset = config->tcc_offset; + tconfig->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); tconfig->TccOffsetClamp = config->tcc_offset > 0; /* Unlock all GPIO pads */ @@ -709,6 +710,13 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) s_cfg->PchLockDownRtcMemoryLock = lockdown_by_fsp; tconfig->SkipPamLock = !lockdown_by_fsp; #if CONFIG(SOC_INTEL_COMETLAKE) + supd->FspsConfig.DebugInterfaceEnable = 0; + supd->FspsTestConfig.DebugInterfaceEnable = 0; + /* + * IA32_DEBUG_INTERFACE_MSR has to be locked by coreboot, + * because FSP does not do it unless DebugInterfaceEnable is 1 + */ + supd->FspsTestConfig.DebugInterfaceLockEnable = 0; /* * Making this config "0" means FSP won't set the FLOCKDN bit * of SPIBAR + 0x04 (i.e., Bit 15 of BIOS_HSFSTS_CTL). diff --git a/src/soc/intel/cannonlake/lockdown.c b/src/soc/intel/cannonlake/lockdown.c index 3205c7f303b..c2656e620af 100644 --- a/src/soc/intel/cannonlake/lockdown.c +++ b/src/soc/intel/cannonlake/lockdown.c @@ -1,11 +1,17 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include +#include #include #include #include #include #include +#define MSR_IA32_DEBUG_INTERFACE 0xc80 +#define MSR_IA32_DEBUG_INTERFACE_EN (1 << 0) +#define MSR_IA32_DEBUG_INTERFACE_LOCK (1 << 30) + static void pmc_lock_pmsync(void) { uint8_t *pmcbase; @@ -55,8 +61,22 @@ static void pmc_lockdown_cfg(int chipset_lockdown) pmc_lock_smi(); } +static void cpu_lockdown_cfg(void) +{ + msr_t msr = rdmsr(MSR_IA32_DEBUG_INTERFACE); + + if (!(msr.lo & MSR_IA32_DEBUG_INTERFACE_LOCK)) { + if (CONFIG(INTEL_TXT)) + msr.lo &= ~MSR_IA32_DEBUG_INTERFACE_EN; + + msr.lo |= MSR_IA32_DEBUG_INTERFACE_LOCK; + wrmsr(MSR_IA32_DEBUG_INTERFACE, msr); + } +} + void soc_lockdown_config(int chipset_lockdown) { /* PMC lock down configuration */ pmc_lockdown_cfg(chipset_lockdown); + cpu_lockdown_cfg(); } diff --git a/src/soc/intel/cannonlake/romstage/romstage.c b/src/soc/intel/cannonlake/romstage/romstage.c index b3777b686f7..bd4be6a635d 100644 --- a/src/soc/intel/cannonlake/romstage/romstage.c +++ b/src/soc/intel/cannonlake/romstage/romstage.c @@ -6,9 +6,11 @@ #include #include #include +#include #include #include #include +#include #include #include #include @@ -122,6 +124,8 @@ void mainboard_romstage_entry(void) bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); + setup_oc_wdt(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ @@ -130,6 +134,10 @@ void mainboard_romstage_entry(void) cse_init(HECI1_BASE_ADDRESS); s3wake = pmc_fill_power_state(ps) == ACPI_S3; + + if (CONFIG(INTEL_TXT)) + intel_txt_romstage_init(); + fsp_memory_init(s3wake); pmc_set_disb(); if (!s3wake) { diff --git a/src/soc/intel/common/block/acpi/Kconfig b/src/soc/intel/common/block/acpi/Kconfig index 827bedd50d3..df354c77cfd 100644 --- a/src/soc/intel/common/block/acpi/Kconfig +++ b/src/soc/intel/common/block/acpi/Kconfig @@ -54,6 +54,15 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID help Defines hybrid CPU specific ACPI helper functions. +config SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS + bool + depends on SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID + help + Core performance and efficient scaling factors are read at runtime + using the soc_read_core_scaling_factors() function instead of using + statically defined values SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR and + SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR. + config SOC_INTEL_UFS_OCP_TIMER_DISABLE bool help diff --git a/src/soc/intel/common/block/acpi/acpi.c b/src/soc/intel/common/block/acpi/acpi.c index d683726d866..a9bb3b7f875 100644 --- a/src/soc/intel/common/block/acpi/acpi.c +++ b/src/soc/intel/common/block/acpi/acpi.c @@ -402,6 +402,7 @@ void generate_cpu_entries(const struct device *device) sgx_fill_ssdt(); } +#if !CONFIG(SOC_INTEL_COMMON_OC_WDT_WDAT) static bool fill_wdat_timeout_entry(acpi_wdat_entry_t *entry) { @@ -574,3 +575,5 @@ unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) return current; } + +#endif /* #if !CONFIG(SOC_INTEL_COMMON_OC_WDT_WDAT) */ diff --git a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl index adda519e901..e9bbb737eba 100644 --- a/src/soc/intel/common/block/acpi/acpi/globalnvs.asl +++ b/src/soc/intel/common/block/acpi/acpi/globalnvs.asl @@ -23,4 +23,5 @@ Field (GNVS, ByteAcc, NoLock, Preserve) U3WE, 16, // 0x2d - 0x2e USB3 Wake Enable Bitmap UIOR, 8, // 0x2f - UART debug controller init on S3 resume , 64, // 0x30 - 0x37 Hest log buffer (used in SMM, not ASL code) + S0IX, 8, // 0x38 - Sleep Type (1 = S0IX, 0 = S3) } diff --git a/src/soc/intel/common/block/acpi/cpu_hybrid.c b/src/soc/intel/common/block/acpi/cpu_hybrid.c index 68abba7eb8d..2c3b84ceee9 100644 --- a/src/soc/intel/common/block/acpi/cpu_hybrid.c +++ b/src/soc/intel/common/block/acpi/cpu_hybrid.c @@ -15,11 +15,6 @@ #define CPPC_NOM_FREQ_IDX 22 #define CPPC_NOM_PERF_IDX 3 -enum cpu_perf_eff_type { - CPU_TYPE_EFF, - CPU_TYPE_PERF, -}; - struct cpu_apic_info_type { /* * Ordered APIC IDs based on core type. @@ -113,18 +108,27 @@ void set_dev_core_type(void) static void acpi_get_cpu_nomi_perf(u16 *eff_core_nom_perf, u16 *perf_core_nom_perf) { u8 max_non_turbo_ratio = cpu_get_max_non_turbo_ratio(); + static u16 performance, efficient; - _Static_assert(CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR != 0, + _Static_assert(CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS) || + CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR != 0, "CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR must not be zero"); - _Static_assert(CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR != 0, + _Static_assert(CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS) || + CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR != 0, "CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR must not be zero"); - *perf_core_nom_perf = (u16)((max_non_turbo_ratio * - CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR) / 100); + if (!performance) { + if (CONFIG(SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS)) { + soc_read_core_scaling_factors(&performance, &efficient); + } else { + performance = CONFIG_SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR; + efficient = CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR; + } + } - *eff_core_nom_perf = (u16)((max_non_turbo_ratio * - CONFIG_SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR) / 100); + *perf_core_nom_perf = (u16)((max_non_turbo_ratio * performance) / 100); + *eff_core_nom_perf = (u16)((max_non_turbo_ratio * efficient) / 100); } static u16 acpi_get_cpu_nominal_freq(void) diff --git a/src/soc/intel/common/block/acpi/pep.c b/src/soc/intel/common/block/acpi/pep.c index a6ae454d063..183c53513e5 100644 --- a/src/soc/intel/common/block/acpi/pep.c +++ b/src/soc/intel/common/block/acpi/pep.c @@ -190,6 +190,9 @@ static void acpi_lpi_get_constraints(void *unused) if (min_sleep_state == ACPI_DEVICE_SLEEP_NONE) continue; + if (dev->path.type == DEVICE_PATH_PCI && !dev->enabled) + continue; + acpigen_write_package(3); { /* Emit the device path */ diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index c077fb84418..b681f362ac2 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -300,17 +301,20 @@ uint8_t cpu_get_max_non_turbo_ratio(void) void configure_tcc_thermal_target(void) { const config_t *conf = config_of_soc(); + uint32_t tcc_offset; msr_t msr; - if (!conf->tcc_offset) + tcc_offset = get_cpu_throttling_offset(conf->tcc_offset); + + if (!tcc_offset) return; /* Set TCC activation offset */ msr = rdmsr(MSR_PLATFORM_INFO); if ((msr.lo & BIT(30))) { msr = rdmsr(MSR_TEMPERATURE_TARGET); - msr.lo &= ~(0xf << 24); - msr.lo |= (conf->tcc_offset & 0xf) << 24; + msr.lo &= ~(0x3f << 24); + msr.lo |= (tcc_offset & 0x3f) << 24; wrmsr(MSR_TEMPERATURE_TARGET, msr); } diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 63890444280..42c4ed6af2d 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -3,13 +3,16 @@ #define __SIMPLE_DEVICE__ #include +#include #include #include +#include #include #include #include #include #include +#include #include #include #include @@ -275,6 +278,11 @@ bool cse_is_hfs1_com_secover_mei_msg(void) return cse_check_hfs1_com(ME_HFS1_COM_SECOVER_MEI_MSG); } +bool cse_is_hfs1_com_debug(void) +{ + return cse_check_hfs1_com(ME_HFS1_COM_DEBUG); +} + bool cse_is_hfs1_com_soft_temp_disable(void) { return cse_check_hfs1_com(ME_HFS1_COM_SOFT_TEMP_DISABLE); @@ -1173,7 +1181,7 @@ void cse_enable_ptt(bool state) */ if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal() || !cse_is_hfs1_fw_init_complete() || !ENV_RAMSTAGE) { - printk(BIOS_ERR, "HECI: Unmet prerequisites for" + printk(BIOS_ERR, "HECI: Unmet prerequisites for " "FW FEATURE SHIPMENT TIME STATE OVERRIDE\n"); return; } @@ -1216,6 +1224,97 @@ void cse_enable_ptt(bool state) #if ENV_RAMSTAGE +#ifndef HAP_OFFSET +#define HAP_OFFSET 0 +#endif + +/* Flash Master 1 : HOST/BIOS */ +#define FLMSTR1 0x80 +/* Flash signature Offset */ +#define FLASH_SIGN_OFFSET 0x10 +#define FLMSTR_WR_SHIFT_V2 20 +#define FLASH_VAL_SIGN 0xFF0A55A +#define SI_DESC_SIZE 0x1000 +#define SI_DESC_REGION "SI_DESC" + +/* It checks whether host (Flash Master 1) has write access to the Descriptor Region or not */ +static bool is_descriptor_writeable(uint8_t *desc) +{ + /* Check flash has valid signature */ + if (read32((void *)(desc + FLASH_SIGN_OFFSET)) != FLASH_VAL_SIGN) { + printk(BIOS_ERR, "Flash Descriptor is not valid\n"); + return 0; + } + /* Check host has write access to the Descriptor Region */ + if (!((read32((void *)(desc + FLMSTR1)) >> FLMSTR_WR_SHIFT_V2) & BIT(0))) { + printk(BIOS_ERR, "Host doesn't have write access to Descriptor Region\n"); + return 0; + } + return 1; +} + +static void cse_set_hap_bit(bool state) +{ + uint8_t *si_desc_buf; + struct region_device desc_rdev; + + si_desc_buf = (uint8_t *)malloc(SI_DESC_SIZE); + + if (!si_desc_buf) { + printk(BIOS_ERR, "Failed to allocate buffer for %s\n", SI_DESC_REGION); + return; + } + + if (fmap_locate_area_as_rdev_rw("SI_DESC", &desc_rdev) < 0) { + printk(BIOS_ERR, "Failed to locate %s in the FMAP\n", SI_DESC_REGION); + free(si_desc_buf); + return; + } + if (rdev_readat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to read Descriptor Region from SPI Flash\n"); + free(si_desc_buf); + return; + } + if (!is_descriptor_writeable(si_desc_buf)) { + free(si_desc_buf); + return; + } + + if (!!(si_desc_buf[HAP_OFFSET] & 1) == state) { + printk(BIOS_DEBUG, "Update of Descriptor is not required!\n"); + if (state) + printk(BIOS_INFO, "ME is HAP disabled\n"); + free(si_desc_buf); + return; + } + + si_desc_buf[HAP_OFFSET] ^= 1; + if (rdev_eraseat(&desc_rdev, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to erase Descriptor Region area\n"); + free(si_desc_buf); + return; + } + + if (rdev_writeat(&desc_rdev, si_desc_buf, 0, SI_DESC_SIZE) != SI_DESC_SIZE) { + printk(BIOS_ERR, "Failed to update Descriptor Region\n"); + free(si_desc_buf); + return; + } + + printk(BIOS_DEBUG, "Update of Descriptor successful\n"); + free(si_desc_buf); + do_global_reset(); +} + +static void set_hap_bit(void *unused) +{ + bool state = cse_get_me_disable_mode() == ME_MODE_DISABLE_HAP; + if (HAP_OFFSET != 0) + cse_set_hap_bit(state); +} + +BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, set_hap_bit, NULL); + /* * Disable the Intel (CS)Management Engine via HECI based on a cmos value * of `me_state`. A value of `0` will result in a (CS)ME state of `0` (working) @@ -1315,37 +1414,71 @@ static void cse_set_state(struct device *dev) int send; int result; + int enable_timeout = 0; /* * Check if the CMOS value "me_state" exists, if it doesn't, then * don't do anything. */ + + const unsigned int efi_me_state = cse_get_me_disable_mode() == ME_MODE_DISABLE_HECI; const unsigned int cmos_me_state = get_uint_option("me_state", UINT_MAX); + unsigned int me_state; - if (cmos_me_state == UINT_MAX) - return; + /* EFI setting takes priority */ + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + me_state = efi_me_state; + else if (CONFIG(USE_OPTION_TABLE)) + me_state = cmos_me_state; + else + me_state = CONFIG_INTEL_ME_DEFAULT_STATE; + + printk(BIOS_DEBUG, "me_state = %u\n", me_state); printk(BIOS_DEBUG, "CMOS: me_state = %u\n", cmos_me_state); + /* + * Skip action while ME is in debug (HAP) mode, as HECI will not work + * in this state + */ + + if (cse_is_hfs1_com_debug()) { + printk(BIOS_DEBUG, "ME is in HAP mode, skipping soft temp disable"); + return; + } + /* * We only take action if the me_state doesn't match the CS(ME) working state */ const unsigned int soft_temp_disable = cse_is_hfs1_com_soft_temp_disable(); - if (cmos_me_state && !soft_temp_disable) { + if (me_state && !soft_temp_disable) { /* me_state should be disabled, but it's enabled */ printk(BIOS_DEBUG, "ME needs to be disabled.\n"); send = heci_send_receive(&me_disable, sizeof(me_disable), &disable_reply, &disable_reply_size, HECI_MKHI_ADDR); result = disable_reply.hdr.result; - } else if (!cmos_me_state && soft_temp_disable) { + } else if (!me_state && soft_temp_disable) { /* me_state should be enabled, but it's disabled */ printk(BIOS_DEBUG, "ME needs to be enabled.\n"); send = heci_send_receive(&me_enable, sizeof(me_enable), &enable_reply, &enable_reply_size, HECI_MKHI_ADDR); result = enable_reply.hdr.result; + + while (1) { + if (cse_is_hfs1_cws_normal()) + break; + + delay(1); + enable_timeout++; + if (enable_timeout > 5) { + printk(BIOS_ERR, "Timeout occurred, ME HFSTS1: %08x\n", + me_read_config32(PCI_ME_HFSTS1)); + break; + } + } } else { - printk(BIOS_DEBUG, "ME is %s.\n", cmos_me_state ? "disabled" : "enabled"); + printk(BIOS_DEBUG, "ME is %s.\n", me_state ? "disabled" : "enabled"); unsigned int cmos_me_state_counter = get_uint_option("me_state_counter", UINT_MAX); /* set me_state_counter to 0 */ @@ -1468,9 +1601,24 @@ static void cse_final(struct device *dev) cse_final_end_of_firmware(); } +#if ENV_RAMSTAGE +static void heci_read_resources(struct device *dev) +{ + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + if (ENV_X86_32) { + /* Put resource below 4G to ensure coreboot can access it */ + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + res->limit = 0xffffffff; + res->flags &= ~IORESOURCE_ABOVE_4G; + } +} +#endif + struct device_operations cse_ops = { .set_resources = pci_dev_set_resources, - .read_resources = pci_dev_read_resources, + .read_resources = heci_read_resources, .enable_resources = pci_dev_enable_resources, .init = pci_dev_init, .ops_pci = &pci_dev_ops_pci, diff --git a/src/soc/intel/common/block/cse/cse_eop.c b/src/soc/intel/common/block/cse/cse_eop.c index 265fe04bbc4..87254da7b3a 100644 --- a/src/soc/intel/common/block/cse/cse_eop.c +++ b/src/soc/intel/common/block/cse/cse_eop.c @@ -131,13 +131,19 @@ static enum cse_cmd_result cse_send_eop(void) * 3) Only sent after DID (accomplished by compiling this into ramstage) */ - if (cse_is_hfs1_com_soft_temp_disable()) { + if (cse_is_hfs1_com_soft_temp_disable() || cse_is_hfs1_com_debug()) { printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); if (CONFIG(SOC_INTEL_CSE_LITE_SKU)) return CSE_CMD_RESULT_ERROR; return CSE_CMD_RESULT_DISABLED; } + if (cse_is_hfs1_com_secover_mei_msg()) { + printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); + /* For CSE Lite this is expected state in update flow, so don't return an error */ + return CSE_CMD_RESULT_DISABLED; + } + if (!cse_is_hfs1_cws_normal() || !cse_is_hfs1_com_normal()) { printk(BIOS_ERR, "HECI: Prerequisites not met for sending EOP\n"); return CSE_CMD_RESULT_ERROR; @@ -285,14 +291,16 @@ static bool is_cse_eop_supported(void) /* CSE Lite */ if ((CONFIG(SOC_INTEL_CSE_LITE_SKU) && vboot_recovery_mode_enabled()) && cse_is_hfs1_com_soft_temp_disable()) { - printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE Lite in expected " - "SOFT TEMP DISABLE state, skipping EOP\n"); + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE Lite in expected SOFT TEMP DISABLE state, skipping EOP\n"); return false; } /* Other CSE Type */ if (cse_is_hfs1_com_soft_temp_disable()) { - printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected " - "SOFT TEMP DISABLE state, skipping EOP\n"); + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected SOFT TEMP DISABLE state, skipping EOP\n"); + return false; + } + if (cse_is_hfs1_com_debug()) { + printk(BIOS_INFO, "HECI: coreboot in recovery mode; found CSE in expected Debug Mode state, skipping EOP\n"); return false; } diff --git a/src/soc/intel/common/block/fast_spi/Kconfig b/src/soc/intel/common/block/fast_spi/Kconfig index 3a541f861c9..48b80ccb478 100644 --- a/src/soc/intel/common/block/fast_spi/Kconfig +++ b/src/soc/intel/common/block/fast_spi/Kconfig @@ -52,6 +52,13 @@ config EXT_BIOS_WIN_SIZE region greater than 16MiB. The actual mapped window might be smaller depending upon the size of the BIOS region. +config EXT_BIOS_FILL_UP + bool + default n + help + Extend BIOS region to the beginning of the flash for the + purposes of mapping. + config FAST_SPI_GENERATE_SSDT bool default n diff --git a/src/soc/intel/common/block/fast_spi/mmap_boot.c b/src/soc/intel/common/block/fast_spi/mmap_boot.c index 2315c44bbde..b688a5d4633 100644 --- a/src/soc/intel/common/block/fast_spi/mmap_boot.c +++ b/src/soc/intel/common/block/fast_spi/mmap_boot.c @@ -100,6 +100,12 @@ static void bios_mmap_init(void) /* Read the offset and size of BIOS region in the SPI flash address space. */ bios_start = fast_spi_get_bios_region(&bios_size); + /* Optionally extend BIOS region to the beginning of the flash. */ + if (CONFIG(EXT_BIOS_FILL_UP)) { + bios_size += bios_start; + bios_start = 0; + } + /* * By default, fixed decode window (maximum size 16MiB) is mapped just below the 4G * boundary. This window maps the top part of the BIOS region in the SPI flash address diff --git a/src/soc/intel/common/block/graphics/graphics.c b/src/soc/intel/common/block/graphics/graphics.c index 144e8c30d6e..ab2f13863ed 100644 --- a/src/soc/intel/common/block/graphics/graphics.c +++ b/src/soc/intel/common/block/graphics/graphics.c @@ -288,6 +288,13 @@ static void graphics_dev_read_resources(struct device *dev) pci_dev_set_resources(dev); res_bar0->flags |= IORESOURCE_FIXED; } + + if (ENV_X86_32) { + /* Place framebuffer below 4G to ensure coreboot can access it */ + struct resource *res_bar2 = find_resource(dev, PCI_BASE_ADDRESS_2); + res_bar2->limit = 0xffffffff; + res_bar2->flags &= ~IORESOURCE_ABOVE_4G; + } } static void graphics_join_mbus(void) @@ -459,16 +466,26 @@ static const unsigned short pci_device_ids[] = { PCI_DID_INTEL_ADL_N_GT1, PCI_DID_INTEL_ADL_N_GT2, PCI_DID_INTEL_ADL_N_GT3, + PCI_DID_INTEL_ADL_N_GT4, + PCI_DID_INTEL_ADL_N_GT5, PCI_DID_INTEL_RPL_S_GT0, PCI_DID_INTEL_RPL_S_GT1_1, PCI_DID_INTEL_RPL_S_GT1_2, PCI_DID_INTEL_RPL_S_GT1_3, + PCI_DID_INTEL_RPL_S_GT1_4, + PCI_DID_INTEL_RPL_S_GT1_5, PCI_DID_INTEL_RPL_HX_GT1, PCI_DID_INTEL_RPL_HX_GT2, PCI_DID_INTEL_RPL_HX_GT3, PCI_DID_INTEL_RPL_HX_GT4, PCI_DID_INTEL_TWL_GT1_1, PCI_DID_INTEL_TWL_GT1_2, + PCI_DID_INTEL_MTL_M_GT2, + PCI_DID_INTEL_MTL_P_GT2_1, + PCI_DID_INTEL_MTL_P_GT2_2, + PCI_DID_INTEL_MTL_P_GT2_3, + PCI_DID_INTEL_MTL_P_GT2_4, + PCI_DID_INTEL_MTL_P_GT2_5, 0, }; diff --git a/src/soc/intel/common/block/i2c/i2c.c b/src/soc/intel/common/block/i2c/i2c.c index 3c2f211d282..4d7ff7c74ff 100644 --- a/src/soc/intel/common/block/i2c/i2c.c +++ b/src/soc/intel/common/block/i2c/i2c.c @@ -134,6 +134,19 @@ uintptr_t dw_i2c_base_address(unsigned int bus) return (uintptr_t)ALIGN_DOWN(pci_read_config32(dev, PCI_BASE_ADDRESS_0), 16); } +static void dw_i2c_read_resources(struct device *dev) +{ + /* Read standard PCI resources. */ + pci_dev_read_resources(dev); + + if (ENV_X86_32) { + /* Put resource below 4G to ensure coreboot can access it */ + struct resource *res = find_resource(dev, PCI_BASE_ADDRESS_0); + res->limit = 0xffffffff; + res->flags &= ~IORESOURCE_ABOVE_4G; + } +} + /* * This function ensures that the device is actually out of reset and * its ready for initialization sequence. @@ -161,7 +174,7 @@ static void dw_i2c_device_init(struct device *dev) } struct device_operations i2c_dev_ops = { - .read_resources = pci_dev_read_resources, + .read_resources = dw_i2c_read_resources, .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .scan_bus = scan_static_bus, diff --git a/src/soc/intel/common/block/include/intelblocks/acpi.h b/src/soc/intel/common/block/include/intelblocks/acpi.h index fa320925686..a3f82481c97 100644 --- a/src/soc/intel/common/block/include/intelblocks/acpi.h +++ b/src/soc/intel/common/block/include/intelblocks/acpi.h @@ -18,8 +18,21 @@ enum core_type { CPUID_UNKNOWN = 0xff, }; +/* CPU Performance Type */ +enum cpu_perf_eff_type { + CPU_TYPE_EFF, + CPU_TYPE_PERF, +}; + unsigned long acpi_create_madt_lapics_with_nmis_hybrid(unsigned long current); +/* + * Read the performance and efficient core ratios. + * This is to be implemented by the SoC specific code if + * SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS is selected. + */ +enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient); + /* Generates ACPI code to define _CPC control method */ void acpigen_write_CPPC_hybrid_method(int core_id); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index c97e4ec65ce..25aa468d4d5 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -61,6 +61,7 @@ enum mkhi_group_id { /* ME Current Operation Modes */ #define ME_HFS1_COM_NORMAL 0x0 +#define ME_HFS1_COM_DEBUG 0x2 #define ME_HFS1_COM_SOFT_TEMP_DISABLE 0x3 #define ME_HFS1_COM_SECOVER_MEI_MSG 0x5 @@ -461,6 +462,12 @@ bool cse_is_hfs1_com_normal(void); */ bool cse_is_hfs1_com_secover_mei_msg(void); +/* + * Checks CSE's current operation mode is Debug Mode or not. + * Returns true if CSE's current operation mode is Debug Mode, otherwise false. + */ +bool cse_is_hfs1_com_debug(void); + /* * Checks CSE's current operation mode is Soft Disable Mode or not. * Returns true if CSE's current operation mode is Soft Disable Mode, otherwise false. diff --git a/src/soc/intel/common/block/include/intelblocks/me_12.h b/src/soc/intel/common/block/include/intelblocks/me_12.h index 9e9a3c18349..7e4d8c642d7 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_12.h +++ b/src/soc/intel/common/block/include/intelblocks/me_12.h @@ -3,6 +3,15 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_12_H_ #define _SOC_INTEL_COMMON_ME_SPEC_12_H_ +/* HAP bit */ +#if CONFIG(SOC_INTEL_COMETLAKE_1) || CONFIG(SOC_INTEL_COMETLAKE_2) || CONFIG(SOC_INTEL_COMETLAKE_1_2) +#define HAP_OFFSET 0x172 +#elif CONFIG(SOC_INTEL_COMETLAKE_V) +#define HAP_OFFSET 0x102 +#elif CONFIG(SOC_INTEL_COMETLAKE_S) +#define HAP_OFFSET 0x182 +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/me_13.h b/src/soc/intel/common/block/include/intelblocks/me_13.h index 912930d6adc..e7cbb5344a8 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_13.h +++ b/src/soc/intel/common/block/include/intelblocks/me_13.h @@ -3,6 +3,11 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_13_H_ #define _SOC_INTEL_COMMON_ME_SPEC_13_H_ +/* HAP bit */ +#if CONFIG(SOC_INTEL_JASPERLAKE) +#define HAP_OFFSET 0x16A +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/me_15.h b/src/soc/intel/common/block/include/intelblocks/me_15.h index 60fbbae5205..47188fbbc1c 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_15.h +++ b/src/soc/intel/common/block/include/intelblocks/me_15.h @@ -3,6 +3,15 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_15_H_ #define _SOC_INTEL_COMMON_ME_SPEC_15_H_ +/* HAP bit */ +#if CONFIG(SOC_INTEL_TIGERLAKE_PCH_H) +#define HAP_OFFSET 0x196 +#elif CONFIG(SOC_INTEL_TIGERLAKE) +#define HAP_OFFSET 0x17E +#elif CONFIG(SOC_INTEL_ELKHARTLAKE) +#define HAP_OFFSET 0x186 +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/me_16.h b/src/soc/intel/common/block/include/intelblocks/me_16.h index ef3dbd1b4c0..89dd95ef00d 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_16.h +++ b/src/soc/intel/common/block/include/intelblocks/me_16.h @@ -3,6 +3,13 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_16_H_ #define _SOC_INTEL_COMMON_ME_SPEC_16_H_ +/* HAP bit */ +#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S) +#define HAP_OFFSET 0x1DE +#elif CONFIG(SOC_INTEL_ALDERLAKE_PCH_P) || CONFIG(SOC_INTEL_ALDERLAKE_PCH_N) +#define HAP_OFFSET 0x17E +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/me_18.h b/src/soc/intel/common/block/include/intelblocks/me_18.h index b226ebc5019..e32ee958b7b 100644 --- a/src/soc/intel/common/block/include/intelblocks/me_18.h +++ b/src/soc/intel/common/block/include/intelblocks/me_18.h @@ -3,6 +3,10 @@ #ifndef _SOC_INTEL_COMMON_ME_SPEC_18_H_ #define _SOC_INTEL_COMMON_ME_SPEC_18_H_ +#if CONFIG(SOC_INTEL_METEORLAKE_U_H) +#define HAP_OFFSET 0x21E +#endif + /* ME Host Firmware Status register 1 */ union me_hfsts1 { uint32_t data; diff --git a/src/soc/intel/common/block/include/intelblocks/nvs.h b/src/soc/intel/common/block/include/intelblocks/nvs.h index 071be665ea3..0fd1d4ae43f 100644 --- a/src/soc/intel/common/block/include/intelblocks/nvs.h +++ b/src/soc/intel/common/block/include/intelblocks/nvs.h @@ -25,6 +25,7 @@ struct __packed global_nvs { u16 u3we; /* 0x2d - 0x2e USB3 Wake Enable Bitmap */ u8 uior; /* 0x2f - UART debug controller init on S3 resume */ u64 hest_log_addr; /* 0x30 - 0x37 err log addr (used in SMM, not ASL code) */ + u8 s0ix; /* 0x38 - Sleep Type (1 = S0IX, 0 = S3) */ }; #endif diff --git a/src/soc/intel/common/block/include/intelblocks/oc_wdt.h b/src/soc/intel/common/block/include/intelblocks/oc_wdt.h index bc0f0b1a27a..f5b50db87a7 100644 --- a/src/soc/intel/common/block/include/intelblocks/oc_wdt.h +++ b/src/soc/intel/common/block/include/intelblocks/oc_wdt.h @@ -5,6 +5,19 @@ #include +/* OC WDT configuration */ +#define PCH_OC_WDT_CTL (ACPI_BASE_ADDRESS + 0x54) +#define PCH_OC_WDT_CTL_RLD BIT(31) +#define PCH_OC_WDT_CTL_ICCSURV_STS BIT(25) +#define PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT(24) +#define PCH_OC_WDT_CTL_SCRATCH_OFFSET 0x10 +#define PCH_OC_WDT_CTL_SCRATCH_MASK (0xFF << PCH_OC_WDT_CTL_SCRATCH_OFFSET) +#define PCH_OC_WDT_CTL_FORCE_ALL BIT(15) +#define PCH_OC_WDT_CTL_EN BIT(14) +#define PCH_OC_WDT_CTL_ICCSURV BIT(13) +#define PCH_OC_WDT_CTL_LCK BIT(12) +#define PCH_OC_WDT_CTL_TOV_MASK 0x3FF + /* Starts and reloads the OC watchdog if enabled in Kconfig */ void setup_oc_wdt(void); diff --git a/src/soc/intel/common/block/include/intelblocks/power_limit.h b/src/soc/intel/common/block/include/intelblocks/power_limit.h index d02eaa1352d..ebf4128bcea 100644 --- a/src/soc/intel/common/block/include/intelblocks/power_limit.h +++ b/src/soc/intel/common/block/include/intelblocks/power_limit.h @@ -14,6 +14,7 @@ /* Default power limit value in secs */ #define MOBILE_SKU_PL1_TIME_SEC 28 +#define POWER_LIMIT1_TIME_56_SEC 56 #define MILLIWATTS_TO_WATTS 1000 diff --git a/src/soc/intel/common/block/include/intelblocks/tcss.h b/src/soc/intel/common/block/include/intelblocks/tcss.h index a3fec18086a..ff78b030759 100644 --- a/src/soc/intel/common/block/include/intelblocks/tcss.h +++ b/src/soc/intel/common/block/include/intelblocks/tcss.h @@ -177,15 +177,15 @@ bool ioe_tcss_valid_tbt_auth(void); #define FW_RESET_TIME 50000 /* Number of microseconds to wait after data link layer active report */ -#define FW_DL_UP_TIME 1 +#define FW_DL_UP_TIME Ones /* Number of microseconds to wait after a function level reset */ -#define FW_FLR_RESET_TIME 1 +#define FW_FLR_RESET_TIME Ones /* Number of microseconds to wait from D3 hot to D0 transition */ #define FW_D3HOT_TO_D0_TIME 50000 /* Number of microseconds to wait after setting the VF enable bit */ -#define FW_VF_ENABLE_TIME 1 +#define FW_VF_ENABLE_TIME Ones #endif /* _TCSS_H_ */ diff --git a/src/soc/intel/common/block/lpc/Makefile.mk b/src/soc/intel/common/block/lpc/Makefile.mk index b510cd0ec35..60792654b5a 100644 --- a/src/soc/intel/common/block/lpc/Makefile.mk +++ b/src/soc/intel/common/block/lpc/Makefile.mk @@ -5,3 +5,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc.c + +ifeq ($(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM),y) +smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_LPC) += lpc_lib.c +endif diff --git a/src/soc/intel/common/block/oc_wdt/Kconfig b/src/soc/intel/common/block/oc_wdt/Kconfig index f0966e0f383..107e3b66e98 100644 --- a/src/soc/intel/common/block/oc_wdt/Kconfig +++ b/src/soc/intel/common/block/oc_wdt/Kconfig @@ -18,7 +18,7 @@ config SOC_INTEL_COMMON_OC_WDT_ENABLE config SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS int - depends on SOC_INTEL_COMMON_OC_WDT_ENABLE + depends on SOC_INTEL_COMMON_OC_WDT_ENABLE || SOC_INTEL_COMMON_OC_WDT_WDAT range 70 1024 default 600 help @@ -32,6 +32,7 @@ config SOC_INTEL_COMMON_OC_WDT_RELOAD_IN_PERIODIC_SMI bool "Reload the overclocking watchdog using periodic SMI" depends on SOC_INTEL_COMMON_OC_WDT_ENABLE depends on SOC_INTEL_COMMON_BLOCK_SMM + default n if SOC_INTEL_COMMON_OC_WDT_WDAT default y help Enables Intel chipset Overclocking Watchdog reloading in the periodic @@ -39,3 +40,10 @@ config SOC_INTEL_COMMON_OC_WDT_RELOAD_IN_PERIODIC_SMI unless the OS drivers are installed for this watchdog. If unsure, say Y. + +config SOC_INTEL_COMMON_OC_WDT_WDAT + bool "Expose the overclocking watchdog in ACPI WDAT table" + depends on SOC_INTEL_COMMON_BLOCK_OC_WDT + select ACPI_WDAT_WDT + help + Select this option to expose the OC watchdog in ACPI WDAT tables. diff --git a/src/soc/intel/common/block/oc_wdt/Makefile.mk b/src/soc/intel/common/block/oc_wdt/Makefile.mk index 8f7282a004d..d7bd7746ca2 100644 --- a/src/soc/intel/common/block/oc_wdt/Makefile.mk +++ b/src/soc/intel/common/block/oc_wdt/Makefile.mk @@ -1,4 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only all-$(CONFIG_SOC_INTEL_COMMON_BLOCK_OC_WDT) += oc_wdt.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_OC_WDT_WDAT) += acpi.c + smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_OC_WDT) += oc_wdt.c diff --git a/src/soc/intel/common/block/oc_wdt/acpi.c b/src/soc/intel/common/block/oc_wdt/acpi.c new file mode 100644 index 00000000000..90214842bdf --- /dev/null +++ b/src/soc/intel/common/block/oc_wdt/acpi.c @@ -0,0 +1,167 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +#define OC_WDT_MIN_VALUE 0 +#define OC_WDT_MAX_VALUE 1023 +#define OC_WDT_PERIOD_MS 1000 + +static bool fill_wdat_timeout_entry(acpi_wdat_entry_t *entry) +{ + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = ACPI_WDAT_SET_COUNTDOWN; + entry->instruction = ACPI_WDAT_WRITE_COUNTDOWN | ACPI_WDAT_PRESERVE_REGISTER; + entry->mask = PCH_OC_WDT_CTL_TOV_MASK | PCH_OC_WDT_CTL_ICCSURV_STS + | PCH_OC_WDT_CTL_NO_ICCSURV_STS; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = PCH_OC_WDT_CTL; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_DWORD; + + return true; +} + +static bool fill_wdat_boot_status_entry(acpi_wdat_entry_t *entry, uint8_t action, + uint8_t instruction, uint32_t value, uint32_t mask) +{ + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = action; + entry->instruction = instruction; + entry->value = value; + entry->mask = mask; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = PCH_OC_WDT_CTL; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_DWORD; + + return true; +} + +static bool fill_wdat_run_state_entry(acpi_wdat_entry_t *entry, uint8_t action, + uint8_t instruction, uint32_t value, uint32_t mask) +{ + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = action; + entry->instruction = instruction; + entry->value = value; + entry->mask = mask; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = PCH_OC_WDT_CTL; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_DWORD; + + return true; +} + +static bool fill_wdat_ping_entry(acpi_wdat_entry_t *entry) +{ + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = ACPI_WDAT_RESET; + entry->instruction = ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER; + entry->value = PCH_OC_WDT_CTL_RLD; + entry->mask = + PCH_OC_WDT_CTL_RLD | PCH_OC_WDT_CTL_ICCSURV_STS | PCH_OC_WDT_CTL_NO_ICCSURV_STS; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = PCH_OC_WDT_CTL; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_DWORD; + + return true; +} + +unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) +{ + if (!wdat) + return current; + + wdat->pci_segment = 0xff; + wdat->pci_bus = 0xff; + wdat->pci_device = 0xff; + wdat->pci_function = 0xff; + + wdat->timer_period = OC_WDT_PERIOD_MS; + wdat->min_count = OC_WDT_MIN_VALUE; + wdat->max_count = OC_WDT_MAX_VALUE; + wdat->flags = ACPI_WDAT_FLAG_ENABLED; + wdat->entries = 0; + + acpi_wdat_entry_t *entry = (acpi_wdat_entry_t *)current; + + /* Write countdown */ + if (!fill_wdat_timeout_entry(entry)) + goto out_err; + + entry++; + + /* Get boot status */ + if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_GET_STATUS, ACPI_WDAT_READ_VALUE, + PCH_OC_WDT_CTL_SCRATCH_MASK, + PCH_OC_WDT_CTL_SCRATCH_MASK)) + + goto out_err; + + entry++; + + /* Set boot status */ + if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_SET_STATUS, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, 0, + PCH_OC_WDT_CTL_SCRATCH_MASK + | PCH_OC_WDT_CTL_ICCSURV_STS + | PCH_OC_WDT_CTL_NO_ICCSURV_STS)) + + goto out_err; + + entry++; + + /* Get running status */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_RUNNING_STATE, ACPI_WDAT_READ_VALUE, + PCH_OC_WDT_CTL_EN, PCH_OC_WDT_CTL_EN)) + goto out_err; + + entry++; + + /* Start the watchdog */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_RUNNING_STATE, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, + PCH_OC_WDT_CTL_EN, + PCH_OC_WDT_CTL_EN | PCH_OC_WDT_CTL_ICCSURV_STS + | PCH_OC_WDT_CTL_NO_ICCSURV_STS)) + goto out_err; + + entry++; + + /* Get stopped status */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_STOPPED_STATE, ACPI_WDAT_READ_VALUE, + 0, PCH_OC_WDT_CTL_EN)) + goto out_err; + + entry++; + + /* Stop the watchdog */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_STOPPED_STATE, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, 0, + PCH_OC_WDT_CTL_EN | PCH_OC_WDT_CTL_ICCSURV_STS + | PCH_OC_WDT_CTL_NO_ICCSURV_STS)) + goto out_err; + + entry++; + + /* Ping */ + if (!fill_wdat_ping_entry(entry)) + goto out_err; + + entry++; + + wdat->entries = ((unsigned long)entry - current) / sizeof(acpi_wdat_entry_t); + + return (unsigned long)entry; + +out_err: + wdat->flags = ACPI_WDAT_FLAG_DISABLED; + printk(BIOS_ERR, "Fail to populate WDAT ACPI Table"); + + return current; +} diff --git a/src/soc/intel/common/block/oc_wdt/oc_wdt.c b/src/soc/intel/common/block/oc_wdt/oc_wdt.c index d0f054a074a..d3280a5a9de 100644 --- a/src/soc/intel/common/block/oc_wdt/oc_wdt.c +++ b/src/soc/intel/common/block/oc_wdt/oc_wdt.c @@ -2,21 +2,12 @@ #include #include +#include #include #include #include -/* OC WDT configuration */ -#define PCH_OC_WDT_CTL (ACPI_BASE_ADDRESS + 0x54) -#define PCH_OC_WDT_CTL_RLD BIT(31) -#define PCH_OC_WDT_CTL_ICCSURV_STS BIT(25) -#define PCH_OC_WDT_CTL_NO_ICCSURV_STS BIT(24) -#define PCH_OC_WDT_CTL_FORCE_ALL BIT(15) -#define PCH_OC_WDT_CTL_EN BIT(14) -#define PCH_OC_WDT_CTL_ICCSURV BIT(13) -#define PCH_OC_WDT_CTL_LCK BIT(12) -#define PCH_OC_WDT_CTL_TOV_MASK 0x3FF - +static struct watchdog_config wdt_config; /* * Starts and reloads the OC watchdog with given timeout. * @@ -25,9 +16,7 @@ static void oc_wdt_start(unsigned int timeout) { uint32_t oc_wdt_ctrl; - - if (!CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE)) - return; + bool bootstatus; if ((timeout < 70) || (timeout > (PCH_OC_WDT_CTL_TOV_MASK + 1))) { timeout = CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS; @@ -35,11 +24,19 @@ static void oc_wdt_start(unsigned int timeout) " using config default: %ds\n", timeout); } - printk(BIOS_SPEW, "OC Watchdog: start and relaod timer (timeout %ds)\n", timeout); + printk(BIOS_SPEW, "OC Watchdog: start and reload timer (timeout %ds)\n", timeout); oc_wdt_ctrl = inl(PCH_OC_WDT_CTL); - oc_wdt_ctrl |= (PCH_OC_WDT_CTL_EN | PCH_OC_WDT_CTL_FORCE_ALL | PCH_OC_WDT_CTL_ICCSURV); + bootstatus = !!(oc_wdt_ctrl & (PCH_OC_WDT_CTL_ICCSURV_STS | PCH_OC_WDT_CTL_NO_ICCSURV_STS)); + if (bootstatus) + printk(BIOS_ALERT, "OC Watchdog: Last reset caused by timeout!\n"); + + /* Store bootstatus in scratch register to be consumed by WDAT */ + oc_wdt_ctrl &= ~PCH_OC_WDT_CTL_SCRATCH_MASK; + oc_wdt_ctrl |= bootstatus << PCH_OC_WDT_CTL_SCRATCH_OFFSET; + + oc_wdt_ctrl |= (PCH_OC_WDT_CTL_EN | PCH_OC_WDT_CTL_FORCE_ALL | PCH_OC_WDT_CTL_ICCSURV); oc_wdt_ctrl &= ~PCH_OC_WDT_CTL_TOV_MASK; oc_wdt_ctrl |= (timeout - 1); @@ -91,8 +88,10 @@ unsigned int oc_wdt_get_current_timeout(void) /* Starts and reloads the OC watchdog if enabled in Kconfig */ void setup_oc_wdt(void) { - if (CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE)) { - oc_wdt_start(CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS); + get_watchdog_config(&wdt_config); + + if (wdt_config.wdt_enable) { + oc_wdt_start(wdt_config.wdt_timeout); if (is_oc_wdt_enabled()) printk(BIOS_DEBUG, "OC Watchdog enabled\n"); else diff --git a/src/soc/intel/common/block/pcie/pcie.c b/src/soc/intel/common/block/pcie/pcie.c index ddea3b667b4..7a9733c93fa 100644 --- a/src/soc/intel/common/block/pcie/pcie.c +++ b/src/soc/intel/common/block/pcie/pcie.c @@ -306,6 +306,7 @@ static const unsigned short pcie_device_ids[] = { PCI_DID_INTEL_ADL_P_PCIE_RP1, PCI_DID_INTEL_ADL_P_PCIE_RP2, PCI_DID_INTEL_ADL_P_PCIE_RP3, + PCI_DID_INTEL_ADL_P_PCIE_RP4, PCI_DID_INTEL_ADP_P_PCIE_RP1, PCI_DID_INTEL_ADP_P_PCIE_RP2, PCI_DID_INTEL_ADP_P_PCIE_RP3, diff --git a/src/soc/intel/common/block/pcie/pcie_rp.c b/src/soc/intel/common/block/pcie/pcie_rp.c index 650da1ff914..8cf48f6513a 100644 --- a/src/soc/intel/common/block/pcie/pcie_rp.c +++ b/src/soc/intel/common/block/pcie/pcie_rp.c @@ -117,7 +117,10 @@ static bool pcie_rp_update_dev( printk(BIOS_NOTICE, "%s: Couldn't find PCIe Root Port #%u " "(originally %s) which was enabled in devicetree, removing and disabling.\n", __func__, rp_idx + 1, dev_path(dev)); + /* Disable the dev and its children if not present */ dev->enabled = 0; + if (dev->downstream) + disable_children(dev->downstream); } return true; } else if (PCI_FUNC(dev->path.pci.devfn) != new_fn) { diff --git a/src/soc/intel/common/block/pcie/rtd3/rtd3.c b/src/soc/intel/common/block/pcie/rtd3/rtd3.c index 3a7c8b4afcb..8cf67ff7331 100644 --- a/src/soc/intel/common/block/pcie/rtd3/rtd3.c +++ b/src/soc/intel/common/block/pcie/rtd3/rtd3.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -533,7 +534,7 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) acpigen_write_device(acpi_device_name(dev)); acpigen_write_ADR(0); acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); - if (CONFIG(D3COLD_SUPPORT)) + if (get_sleep_type_option() == SLEEP_TYPE_OPTION_S0IX) acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_COLD); else acpigen_write_name_integer("_S0W", ACPI_DEVICE_SLEEP_D3_HOT); @@ -543,7 +544,13 @@ static void pcie_rtd3_acpi_fill_ssdt(const struct device *dev) acpigen_pop_len(); /* Device */ printk(BIOS_INFO, "%s: Added StorageD3Enable property\n", scope); - } + } else { + /* Write the device to make PEP happy */ + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_ADR(0); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_pop_len(); /* Device */ + } acpigen_pop_len(); /* Scope */ } diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 0fadd6e4096..2a79b3fcae8 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -760,8 +761,7 @@ void pmc_clear_pmcon_sts(void) void pmc_set_power_failure_state(const bool target_on) { - const unsigned int state = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); + const unsigned int state = dasharo_get_power_on_after_fail(); /* * On the shutdown path (target_on == false), we only need to diff --git a/src/soc/intel/common/block/smbus/Kconfig b/src/soc/intel/common/block/smbus/Kconfig index 31bef05f717..30f403840ea 100644 --- a/src/soc/intel/common/block/smbus/Kconfig +++ b/src/soc/intel/common/block/smbus/Kconfig @@ -19,3 +19,10 @@ config SOC_INTEL_COMMON_BLOCK_TCO_ENABLE_THROUGH_SMBUS depends on SOC_INTEL_COMMON_BLOCK_TCO help Select this config to enable TCO BAR through SMBUS + +config SOC_INTEL_COMMON_BLOCK_TCO_WDT_WDAT + bool + depends on SOC_INTEL_COMMON_BLOCK_TCO + select ACPI_WDAT_WDT + help + Select this option to expose the TCO watchdog in ACPI WDAT tables. diff --git a/src/soc/intel/common/block/smbus/Makefile.mk b/src/soc/intel/common/block/smbus/Makefile.mk index 2ef3a5b752d..9c16f56d123 100644 --- a/src/soc/intel/common/block/smbus/Makefile.mk +++ b/src/soc/intel/common/block/smbus/Makefile.mk @@ -9,6 +9,7 @@ romstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_SMBUS) += smbus.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO_WDT_WDAT) += acpi.c postcar-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c smm-$(CONFIG_SOC_INTEL_COMMON_BLOCK_TCO) += tco.c diff --git a/src/soc/intel/common/block/smbus/acpi.c b/src/soc/intel/common/block/smbus/acpi.c new file mode 100644 index 00000000000..0389380f89a --- /dev/null +++ b/src/soc/intel/common/block/smbus/acpi.c @@ -0,0 +1,178 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static bool fill_wdat_timeout_entry(acpi_wdat_entry_t *entry) +{ + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + return false; + + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = ACPI_WDAT_SET_COUNTDOWN; + entry->instruction = ACPI_WDAT_WRITE_COUNTDOWN | ACPI_WDAT_PRESERVE_REGISTER; + entry->mask = TCO_TMR_MASK; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = tcobase + TCO_TMR; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + + return true; +} + +static bool fill_wdat_boot_status_entry(acpi_wdat_entry_t *entry, uint8_t action, + uint8_t instruction, uint32_t value) +{ + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + return false; + + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = action; + entry->instruction = instruction; + entry->value = value; + entry->mask = TCO2_STS_SECOND_TO; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = tcobase + TCO_MESSAGE1; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_BYTE; + + return true; +} + +static bool fill_wdat_run_state_entry(acpi_wdat_entry_t *entry, uint8_t action, + uint8_t instruction, uint32_t value) +{ + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + return false; + + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = action; + entry->instruction = instruction; + entry->value = value; + entry->mask = TCO1_TMR_HLT; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = tcobase + TCO1_CNT; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + + return true; +} + +static bool fill_wdat_ping_entry(acpi_wdat_entry_t *entry) +{ + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + return false; + + memset((void *)entry, 0, sizeof(acpi_wdat_entry_t)); + + entry->action = ACPI_WDAT_RESET; + entry->instruction = ACPI_WDAT_WRITE_VALUE; + entry->value = 0x01; + entry->mask = 0x01; + entry->register_region.space_id = ACPI_ADDRESS_SPACE_IO; + entry->register_region.addrl = tcobase + TCO_RLD; + entry->register_region.access_size = ACPI_WDAT_ACCESS_SIZE_WORD; + + return true; +} + +unsigned long acpi_soc_fill_wdat(acpi_wdat_t *wdat, unsigned long current) +{ + if (!wdat) + return current; + + uint16_t tcobase = tco_get_bar(); + + if (tcobase == 0) + goto out_err; + + wdat->pci_segment = 0xff; + wdat->pci_bus = 0xff; + wdat->pci_device = 0xff; + wdat->pci_function = 0xff; + + wdat->timer_period = tco_get_timer_period(); + wdat->min_count = tco_get_timer_min_value(); + wdat->max_count = tco_get_timer_max_value(); + wdat->flags = ACPI_WDAT_FLAG_ENABLED; + wdat->entries = 0; + + acpi_wdat_entry_t *entry = (acpi_wdat_entry_t *)current; + + /* Write countdown */ + if (!fill_wdat_timeout_entry(entry)) + goto out_err; + + entry++; + + /* Get boot status */ + if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_GET_STATUS, + ACPI_WDAT_READ_VALUE, TCO2_STS_SECOND_TO)) + goto out_err; + + entry++; + + /* Set boot status */ + if (!fill_wdat_boot_status_entry(entry, ACPI_WDAT_SET_STATUS, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, + 0)) + goto out_err; + + entry++; + + /* Get running status */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_RUNNING_STATE, + ACPI_WDAT_READ_VALUE, 0)) + goto out_err; + + entry++; + + /* Start the watchdog */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_RUNNING_STATE, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, + 0)) + goto out_err; + + entry++; + + /* Get stopped status */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_GET_STOPPED_STATE, + ACPI_WDAT_READ_VALUE, TCO1_TMR_HLT)) + goto out_err; + + entry++; + + /* Stop the watchdog */ + if (!fill_wdat_run_state_entry(entry, ACPI_WDAT_SET_STOPPED_STATE, + ACPI_WDAT_WRITE_VALUE | ACPI_WDAT_PRESERVE_REGISTER, + TCO1_TMR_HLT)) + goto out_err; + + entry++; + + /* Ping */ + if (!fill_wdat_ping_entry(entry)) + goto out_err; + + entry++; + + wdat->entries = ((unsigned long)entry - current) / sizeof(acpi_wdat_entry_t); + + return (unsigned long)entry; + +out_err: + wdat->flags = ACPI_WDAT_FLAG_DISABLED; + printk(BIOS_ERR, "Fail to populate WDAT ACPI Table"); + + return current; +} diff --git a/src/soc/intel/common/block/smbus/smbuslib.c b/src/soc/intel/common/block/smbus/smbuslib.c index cf60e64c1d4..3bd1cc57a51 100644 --- a/src/soc/intel/common/block/smbus/smbuslib.c +++ b/src/soc/intel/common/block/smbus/smbuslib.c @@ -13,8 +13,11 @@ static void update_spd_len(struct spd_block *blk) if (blk->spd_array[i] != NULL) j |= blk->spd_array[i][SPD_DRAM_TYPE]; + /* If spd used is DDR5, then its length is 1024 byte. */ + if (j == SPD_DRAM_DDR5) + blk->len = SPD_LEN_DDR5; /* If spd used is DDR4, then its length is 512 byte. */ - if (j == SPD_DRAM_DDR4) + else if (j == SPD_DRAM_DDR4) blk->len = SPD_PAGE_LEN_DDR4; else blk->len = SPD_PAGE_LEN; @@ -37,6 +40,58 @@ static void spd_read(u8 *spd, u8 addr) } } +static void switch_page(u8 spd_addr, u8 new_page) +{ + /* + * By default, an SPD5 hub accepts 1 byte addressing pointing + * to the first 128 bytes of memory. MR11[2:0] selects the page + * pointer to address the entire 1024 bytes of non-volatile memory. + */ + smbus_write_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR11), new_page); +} + +/* + * Read the SPD data over the SMBus, at the specified SPD address, + * starting at the specified starting offset and read the given amount of data. + */ +static void smbus_read_spd5(u8 *spd, u8 spd_addr, u16 size) +{ + u8 page = ~0; + u32 max_page_size = MAX_SPD_PAGE_SIZE_SPD5; + + if (size > MAX_SPD_SIZE) { + printk(BIOS_ERR, "Maximum SPD size reached\n"); + return; + } + for (int i = 0; i < size; i++) { + u8 next_page = (u8) (i / max_page_size); + if (next_page != page) { + switch_page(spd_addr, next_page); + page = next_page; + } + unsigned int byte_addr = SPD_HUB_MEMREG(i % max_page_size); + spd[i] = smbus_read_byte(spd_addr, byte_addr); + } +} + +/* Read SPD5 MR0 and check if SPD Byte 0 matches the SPD5 HUB MR0 identifier.*/ +static int is_spd5_hub(u8 spd_addr) +{ + u8 spd_hub_byte; + + spd_hub_byte = smbus_read_byte(spd_addr, SPD5_MEMREG_REG(SPD5_MR0)); + return spd_hub_byte == SPD5_MR0_SPD5_HUB_DEV; +} + +/* + * Reset the SPD page back to page 0 on an SPD5 Hub device at the + * input SPD SMbus address. + */ +static void reset_page_spd5(u8 spd_addr) +{ + switch_page(spd_addr, 0); +} + /* return -1 if SMBus errors otherwise return 0 */ static int get_spd(u8 *spd, u8 addr) { @@ -52,26 +107,34 @@ static int get_spd(u8 *spd, u8 addr) return -1; } - /* IMC doesn't support i2c eeprom read. */ - if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) || - i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { - printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - spd_read(spd, addr); - } - - /* Check if module is DDR4, DDR4 spd is 512 byte. */ - if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { - /* Switch to page 1 */ - spd_write_byte(SPD_PAGE_1, 0, 0); + if (is_spd5_hub(addr)) { + smbus_read_spd5(spd, addr, SPD_LEN_DDR5); + /* Reset the page for the next loop iteration */ + reset_page_spd5(addr); + } else { /* IMC doesn't support i2c eeprom read. */ if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) || - i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { + i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd) < 0) { printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); - spd_read(spd + SPD_PAGE_LEN, addr); + spd_read(spd, addr); + } + + /* Check if module is DDR4, DDR4 spd is 512 byte. */ + if (spd[SPD_DRAM_TYPE] == SPD_DRAM_DDR4 && + CONFIG_DIMM_SPD_SIZE > SPD_PAGE_LEN) { + /* Switch to page 1 */ + smbus_write_byte(SPD_PAGE_1, 0, 0); + + /* IMC doesn't support i2c eeprom read. */ + if (CONFIG(SOC_INTEL_COMMON_BLOCK_IMC) || + i2c_eeprom_read(addr, 0, SPD_PAGE_LEN, spd + SPD_PAGE_LEN) < 0) { + printk(BIOS_INFO, "do_i2c_eeprom_read failed, using fallback\n"); + spd_read(spd + SPD_PAGE_LEN, addr); + } + /* Restore to page 0 */ + smbus_write_byte(SPD_PAGE_0, 0, 0); } - /* Restore to page 0 */ - spd_write_byte(SPD_PAGE_0, 0, 0); } return 0; } diff --git a/src/soc/intel/common/block/smm/Kconfig b/src/soc/intel/common/block/smm/Kconfig index 84c406ef3e0..fe23172558d 100644 --- a/src/soc/intel/common/block/smm/Kconfig +++ b/src/soc/intel/common/block/smm/Kconfig @@ -55,3 +55,12 @@ config PERIODIC_SMI_RATE_SELECTION_IN_GEN_PMCON_B Intel Core processors select the periodic SMI rate via GEN_PMCON_A. On Intel Atom processors the register is different and they use GEN_PMCON_B/GEN_PMCON2 with different address. + +config SOC_INTEL_COMMON_BLOCK_SMM_NO_MSR_SPCL_CHIPSET_USAGE + bool + depends on SOC_INTEL_COMMON_BLOCK_SMM + default n + help + Intel Core processors write the MSR_SPCL_CHIPSET_USAGE to allow + writes to the BIOS region when EISS is enabled. Some processors + may not have this MSR. If so, select this option. diff --git a/src/soc/intel/common/block/smm/smihandler.c b/src/soc/intel/common/block/smm/smihandler.c index 59489a4f037..65a15b09649 100644 --- a/src/soc/intel/common/block/smm/smihandler.c +++ b/src/soc/intel/common/block/smm/smihandler.c @@ -9,17 +9,20 @@ #include #include #include +#include #include #include #include #include #include +#include #include #include #include #include #include #include +#include #include #include #include @@ -275,7 +278,8 @@ static void set_insmm_sts(const bool enable_writes) else msr.lo &= ~1; - wrmsr(MSR_SPCL_CHIPSET_USAGE, msr); + if (!CONFIG(SOC_INTEL_COMMON_BLOCK_SMM_NO_MSR_SPCL_CHIPSET_USAGE)) + wrmsr(MSR_SPCL_CHIPSET_USAGE, msr); } static void southbridge_smi_store( @@ -345,11 +349,19 @@ static void finalize(void) } finalize_done = 1; + if (CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) { + /* SPI lock down configuration */ + fast_spi_lockdown_bios(CHIPSET_LOCKDOWN_COREBOOT); + + /* LPC/eSPI lock down configuration */ + lpc_lockdown_config(CHIPSET_LOCKDOWN_COREBOOT); + } + if (CONFIG(SPI_FLASH_SMM)) /* Re-init SPI driver to handle locked BAR */ fast_spi_init(); - if (CONFIG(BOOTMEDIA_SMM_BWP)) { + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) { fast_spi_enable_wp(); set_insmm_sts(false); } @@ -440,7 +452,7 @@ void smihandler_southbridge_tco( fast_spi_clear_sync_smi_status(); /* If enabled, enforce SMM BIOS write protection */ - if (CONFIG(BOOTMEDIA_SMM_BWP) && fast_spi_wpd_status()) { + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted() && fast_spi_wpd_status()) { /* * BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS diff --git a/src/soc/intel/common/block/systemagent/systemagent.c b/src/soc/intel/common/block/systemagent/systemagent.c index 098c3c4385b..a8a8fde9f2e 100644 --- a/src/soc/intel/common/block/systemagent/systemagent.c +++ b/src/soc/intel/common/block/systemagent/systemagent.c @@ -551,6 +551,7 @@ static const unsigned short systemagent_ids[] = { PCI_DID_INTEL_RPL_S_ID_3, PCI_DID_INTEL_RPL_S_ID_4, PCI_DID_INTEL_RPL_S_ID_5, + PCI_DID_INTEL_RPL_S_ID_6, PCI_DID_INTEL_RPL_P_ID_1, PCI_DID_INTEL_RPL_P_ID_2, PCI_DID_INTEL_RPL_P_ID_3, diff --git a/src/soc/intel/common/block/vtd/vtd.c b/src/soc/intel/common/block/vtd/vtd.c index 12ca151c7af..edaa1d2098c 100644 --- a/src/soc/intel/common/block/vtd/vtd.c +++ b/src/soc/intel/common/block/vtd/vtd.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -251,6 +252,11 @@ void vtd_enable_dma_protection(void) if (!CONFIG(ENABLE_EARLY_DMA_PROTECTION)) return; + if (!dma_protection_enabled()) { + printk(BIOS_INFO, "VT-d DMA protection disabled by option\n"); + return; + } + vtd_engine_enable_dma_protection(VTVC0_BASE_ADDRESS); /* * FIXME: GFX VT-d will fail to set PMR (tested on ADL-S). diff --git a/src/soc/intel/common/pch/include/intelpch/lockdown.h b/src/soc/intel/common/pch/include/intelpch/lockdown.h index b5aba06fe0e..1b96f41a2a4 100644 --- a/src/soc/intel/common/pch/include/intelpch/lockdown.h +++ b/src/soc/intel/common/pch/include/intelpch/lockdown.h @@ -22,4 +22,7 @@ int get_lockdown_config(void); */ void soc_lockdown_config(int chipset_lockdown); +void fast_spi_lockdown_bios(int chipset_lockdown); +void lpc_lockdown_config(int chipset_lockdown); + #endif /* SOC_INTEL_COMMON_PCH_LOCKDOWN_H */ diff --git a/src/soc/intel/common/pch/lockdown/Kconfig b/src/soc/intel/common/pch/lockdown/Kconfig index 38f60d20569..545185c52f2 100644 --- a/src/soc/intel/common/pch/lockdown/Kconfig +++ b/src/soc/intel/common/pch/lockdown/Kconfig @@ -3,7 +3,22 @@ config SOC_INTEL_COMMON_PCH_LOCKDOWN bool default n + select HAVE_INTEL_CHIPSET_LOCKDOWN help This option allows to have chipset lockdown for DMI, FAST_SPI and soc_lockdown_config() to implement any additional lockdown as PMC, LPC for supported PCH. + +config SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM + bool "Lock down SPI controller in SMM" + default n + depends on HAVE_SMI_HANDLER && !INTEL_CHIPSET_LOCKDOWN + select SPI_FLASH_SMM + help + This option allows to have chipset lockdown for FAST_SPI and LPC for + supported PCH. If selected, coreboot will skip locking down the SPI + and LPC controller. The payload or OS is responsible for locking it + using APM_CNT_FINALIZE SMI. Used by heads to set and lock PR0 flash + protection. + + If unsure, say N. diff --git a/src/soc/intel/common/pch/lockdown/Makefile.mk b/src/soc/intel/common/pch/lockdown/Makefile.mk index 71466f8edd1..64aad562acf 100644 --- a/src/soc/intel/common/pch/lockdown/Makefile.mk +++ b/src/soc/intel/common/pch/lockdown/Makefile.mk @@ -1,2 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_lpc.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_PCH_LOCKDOWN) += lockdown_spi.c + +smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_lpc.c +smm-$(CONFIG_SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM) += lockdown_spi.c diff --git a/src/soc/intel/common/pch/lockdown/lockdown.c b/src/soc/intel/common/pch/lockdown/lockdown.c index eec3beb01b4..2d229e1a90a 100644 --- a/src/soc/intel/common/pch/lockdown/lockdown.c +++ b/src/soc/intel/common/pch/lockdown/lockdown.c @@ -60,56 +60,17 @@ static void fast_spi_lockdown_cfg(int chipset_lockdown) /* Set FAST_SPI opcode menu */ fast_spi_set_opcode_menu(); - /* Discrete Lock Flash PR registers */ - fast_spi_pr_dlock(); - /* Check if SPI transaction is pending */ fast_spi_cycle_in_progress(); /* Clear any outstanding status bits like AEL, FCERR, FDONE, SAF etc. */ fast_spi_clear_outstanding_status(); - /* Lock FAST_SPIBAR */ - fast_spi_lock_bar(); - /* Set Vendor Component Lock (VCL) */ fast_spi_vscc0_lock(); - /* Set BIOS Interface Lock, BIOS Lock */ - if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - /* BIOS Interface Lock */ - fast_spi_set_bios_interface_lock_down(); - - /* Only allow writes in SMM */ - if (CONFIG(BOOTMEDIA_SMM_BWP)) { - fast_spi_set_eiss(); - fast_spi_enable_wp(); - } - - /* BIOS Lock */ - fast_spi_set_lock_enable(); - - /* EXT BIOS Lock */ - fast_spi_set_ext_bios_lock_enable(); - } -} - -static void lpc_lockdown_config(int chipset_lockdown) -{ - /* Set BIOS Interface Lock, BIOS Lock */ - if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { - /* BIOS Interface Lock */ - lpc_set_bios_interface_lock_down(); - - /* Only allow writes in SMM */ - if (CONFIG(BOOTMEDIA_SMM_BWP)) { - lpc_set_eiss(); - lpc_enable_wp(); - } - - /* BIOS Lock */ - lpc_set_lock_enable(); - } + if (!CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) + fast_spi_lockdown_bios(chipset_lockdown); } static void sa_lockdown_config(int chipset_lockdown) @@ -135,8 +96,9 @@ static void platform_lockdown_config(void *unused) /* SPI lock down configuration */ fast_spi_lockdown_cfg(chipset_lockdown); - /* LPC/eSPI lock down configuration */ - lpc_lockdown_config(chipset_lockdown); + if (!CONFIG(SOC_INTEL_COMMON_SPI_LOCKDOWN_SMM)) + /* LPC/eSPI lock down configuration */ + lpc_lockdown_config(chipset_lockdown); /* GPMR lock down configuration */ gpmr_lockdown_cfg(); diff --git a/src/soc/intel/common/pch/lockdown/lockdown_lpc.c b/src/soc/intel/common/pch/lockdown/lockdown_lpc.c new file mode 100644 index 00000000000..79a27d520f3 --- /dev/null +++ b/src/soc/intel/common/pch/lockdown/lockdown_lpc.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void lpc_lockdown_config(int chipset_lockdown) +{ + /* Set BIOS Interface Lock, BIOS Lock */ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + /* BIOS Interface Lock */ + lpc_set_bios_interface_lock_down(); + + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) { + lpc_set_eiss(); + lpc_enable_wp(); + } + + /* BIOS Lock */ + lpc_set_lock_enable(); + } +} diff --git a/src/soc/intel/common/pch/lockdown/lockdown_spi.c b/src/soc/intel/common/pch/lockdown/lockdown_spi.c new file mode 100644 index 00000000000..0815a370bf0 --- /dev/null +++ b/src/soc/intel/common/pch/lockdown/lockdown_spi.c @@ -0,0 +1,33 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void fast_spi_lockdown_bios(int chipset_lockdown) +{ + /* Discrete Lock Flash PR registers */ + fast_spi_pr_dlock(); + + /* Lock FAST_SPIBAR */ + fast_spi_lock_bar(); + + /* Set BIOS Interface Lock, BIOS Lock */ + if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) { + /* BIOS Interface Lock */ + fast_spi_set_bios_interface_lock_down(); + + /* Only allow writes in SMM */ + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted()) { + fast_spi_set_eiss(); + fast_spi_enable_wp(); + } + + /* BIOS Lock */ + fast_spi_set_lock_enable(); + + /* EXT BIOS Lock */ + fast_spi_set_ext_bios_lock_enable(); + } +} diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index 7dc971ea92a..c4f7681c621 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -536,7 +536,8 @@ static const struct pci_driver lpc_driver __pci_driver = { static void finalize_chipset(void *unused) { - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); } BOOT_STATE_INIT_ENTRY(BS_OS_RESUME, BS_ON_ENTRY, finalize_chipset, NULL); diff --git a/src/soc/intel/elkhartlake/Kconfig b/src/soc/intel/elkhartlake/Kconfig index ff3c82f6ff1..7abdde014d6 100644 --- a/src/soc/intel/elkhartlake/Kconfig +++ b/src/soc/intel/elkhartlake/Kconfig @@ -15,6 +15,7 @@ config SOC_INTEL_ELKHARTLAKE select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_FSP_GOP + select HAVE_INTEL_ME_HAP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_CAR_NEM @@ -47,6 +48,7 @@ config SOC_INTEL_ELKHARTLAKE select HAVE_INTEL_FSP_REPO select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT select SOC_INTEL_COMMON_BLOCK_ME_SPEC_15 + select SOC_INTEL_COMMON_BLOCK_OC_WDT select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_COMMON_BLOCK_SA @@ -256,4 +258,7 @@ config SOC_INTEL_ELKHARTLAKE_TCO_NO_REBOOT_EN config DIMM_SPD_SIZE default 512 +config SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS + default 300 + endif diff --git a/src/soc/intel/elkhartlake/finalize.c b/src/soc/intel/elkhartlake/finalize.c index 275413b4efa..3fcc29e2a13 100644 --- a/src/soc/intel/elkhartlake/finalize.c +++ b/src/soc/intel/elkhartlake/finalize.c @@ -33,8 +33,16 @@ static void pch_finalize(void) static void heci_finalize(void) { + bool heci_disable = false; + heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + + if (is_cse_enabled()) { + heci_disable = cse_is_hfs1_com_debug() || + cse_is_hfs1_com_soft_temp_disable(); + } + + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || heci_disable) heci1_disable(); } @@ -43,7 +51,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && CONFIG(USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE)) heci_finalize(); diff --git a/src/soc/intel/elkhartlake/fsp_params.c b/src/soc/intel/elkhartlake/fsp_params.c index 7b715f83d9a..6274cf3a59c 100644 --- a/src/soc/intel/elkhartlake/fsp_params.c +++ b/src/soc/intel/elkhartlake/fsp_params.c @@ -2,6 +2,7 @@ #include #include #include +#include #include #include #include @@ -448,7 +449,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) } /* TccActivationOffset config */ - params->TccActivationOffset = config->tcc_offset; + params->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); params->TccOffsetClamp = config->tcc_offset_clamp; params->TccOffsetLock = 0x1; //lock Tcc Offset register diff --git a/src/soc/intel/elkhartlake/romstage/romstage.c b/src/soc/intel/elkhartlake/romstage/romstage.c index 3dfb7c247dc..8b89406024f 100644 --- a/src/soc/intel/elkhartlake/romstage/romstage.c +++ b/src/soc/intel/elkhartlake/romstage/romstage.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -128,6 +129,8 @@ void mainboard_romstage_entry(void) bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); + setup_oc_wdt(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 3fd6826e121..48a247f38e6 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -16,6 +16,7 @@ config SOC_INTEL_JASPERLAKE select FSP_M_XIP select GENERIC_GPIO_LIB select HAVE_DPTF_EISA_HID + select HAVE_INTEL_ME_HAP select HAVE_FSP_GOP select INTEL_DESCRIPTOR_MODE_CAPABLE select HAVE_SMI_HANDLER @@ -48,6 +49,7 @@ config SOC_INTEL_JASPERLAKE select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_ME_SPEC_13 + select SOC_INTEL_COMMON_BLOCK_OC_WDT select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SMM @@ -206,4 +208,8 @@ config INTEL_GMA_BCLM_OFFSET config INTEL_GMA_BCLM_WIDTH default 32 + +config SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS + default 300 + endif diff --git a/src/soc/intel/jasperlake/acpi/pmc.asl b/src/soc/intel/jasperlake/acpi/pmc.asl index 648cb416613..8c846399d59 100644 --- a/src/soc/intel/jasperlake/acpi/pmc.asl +++ b/src/soc/intel/jasperlake/acpi/pmc.asl @@ -8,6 +8,7 @@ Scope (\_SB.PCI0) { { Name (_HID, "INTC1026") Name (_DDN, "Intel(R) Jasper Lake IPC Controller") + Name (_STA, 0xB) /* * PCH preserved 32 MB MMIO range from 0xFC800000 to 0xFE7FFFFF. * 64KB (0xFE000000 - 0xFE00FFFF) for PMC MBAR. diff --git a/src/soc/intel/jasperlake/bootblock/report_platform.c b/src/soc/intel/jasperlake/bootblock/report_platform.c index e3214c9054d..d783b0e634e 100644 --- a/src/soc/intel/jasperlake/bootblock/report_platform.c +++ b/src/soc/intel/jasperlake/bootblock/report_platform.c @@ -24,12 +24,12 @@ static struct { u16 mchid; const char *name; } mch_table[] = { - { PCI_DID_INTEL_JSL_ID_1, "Jasperlake SKU4-1" }, - { PCI_DID_INTEL_JSL_ID_2, "Jasperlake SKU4-2" }, - { PCI_DID_INTEL_JSL_ID_3, "Jasperlake SKU2-1" }, - { PCI_DID_INTEL_JSL_ID_4, "Jasperlake SKU2-2" }, - { PCI_DID_INTEL_JSL_ID_5, "Jasperlake SKU4-3" }, - { PCI_DID_INTEL_JSL_ID_6, "Jasperlake SKU4-3" }, + { PCI_DID_INTEL_JSL_ID_1, "Jasperlake N4500" }, + { PCI_DID_INTEL_JSL_ID_2, "Jasperlake N6000" }, + { PCI_DID_INTEL_JSL_ID_3, "Jasperlake N5100" }, + { PCI_DID_INTEL_JSL_ID_4, "Jasperlake N4505" }, + { PCI_DID_INTEL_JSL_ID_5, "Jasperlake N5105" }, + { PCI_DID_INTEL_JSL_ID_6, "Jasperlake N6005" }, }; static struct { diff --git a/src/soc/intel/jasperlake/finalize.c b/src/soc/intel/jasperlake/finalize.c index 8788db155d6..4840c0c04c5 100644 --- a/src/soc/intel/jasperlake/finalize.c +++ b/src/soc/intel/jasperlake/finalize.c @@ -76,7 +76,8 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); /* Indicate finalize step with post code */ post_code(POSTCODE_OS_BOOT); diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c index 3bad5334240..d2583aefabc 100644 --- a/src/soc/intel/jasperlake/fsp_params.c +++ b/src/soc/intel/jasperlake/fsp_params.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include #include +#include #include #include #include @@ -177,8 +178,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) /* Enable Processor Thermal Control */ params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); + params->GnaEnable = is_devfn_enabled(SA_DEVFN_GNA); + /* Set TccActivationOffset */ - params->TccActivationOffset = config->tcc_offset; + params->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); /* eMMC configuration */ params->ScsEmmcEnabled = is_devfn_enabled(PCH_DEVFN_EMMC); diff --git a/src/soc/intel/jasperlake/romstage/romstage.c b/src/soc/intel/jasperlake/romstage/romstage.c index 787eb77c913..dd6c4f369ab 100644 --- a/src/soc/intel/jasperlake/romstage/romstage.c +++ b/src/soc/intel/jasperlake/romstage/romstage.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -128,6 +129,8 @@ void mainboard_romstage_entry(void) bool s3wake; struct chipset_power_state *ps = pmc_get_power_state(); + setup_oc_wdt(); + /* Program MCHBAR, DMIBAR, GDXBAR and EDRAMBAR */ systemagent_early_init(); /* Program SMBus base address and enable it */ diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 73d68df2969..63426efc7c1 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -28,6 +28,7 @@ config SOC_INTEL_METEORLAKE select HAVE_FSP_LOGO_SUPPORT if RUN_FSP_GOP select HAVE_HYPERTHREADING select HAVE_INTEL_COMPLIANCE_TEST_MODE + select HAVE_INTEL_ME_HAP select HAVE_SMI_HANDLER select IDT_IN_EVERY_STAGE select INTEL_DESCRIPTOR_MODE_CAPABLE @@ -81,10 +82,11 @@ config SOC_INTEL_METEORLAKE select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP select SOC_INTEL_COMMON_BLOCK_SMM_TCO_ENABLE select SOC_INTEL_COMMON_BLOCK_THERMAL_BEHIND_PMC + select SOC_INTEL_COMMON_BLOCK_VTD select SOC_INTEL_COMMON_BLOCK_XHCI select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BASECODE_RAMTOP if CHROMEOS select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET @@ -158,6 +160,10 @@ config MAX_CPUS int default 22 +config CPU_MAX_TEMPERATURE + int + default 110 + config DCACHE_RAM_BASE default 0xfef00000 @@ -250,7 +256,7 @@ config PCR_BASE_ADDRESS config IOE_PCR_BASE_ADDRESS hex - default 0x3fff0000000 + default 0x60000000 help This option allows you to select MMIO Base Address of IOE sideband bus. @@ -449,4 +455,16 @@ config SOC_PHYSICAL_ADDRESS_WIDTH int default 42 +config INTEL_GMA_BCLV_OFFSET + default 0xc8258 + +config INTEL_GMA_BCLV_WIDTH + default 32 + +config INTEL_GMA_BCLM_OFFSET + default 0xc8254 + +config INTEL_GMA_BCLM_WIDTH + default 32 + endif diff --git a/src/soc/intel/meteorlake/Makefile.mk b/src/soc/intel/meteorlake/Makefile.mk index f3dce871318..9276b8a2b5e 100644 --- a/src/soc/intel/meteorlake/Makefile.mk +++ b/src/soc/intel/meteorlake/Makefile.mk @@ -60,6 +60,9 @@ smm-y += xhci.c CPPFLAGS_common += -I$(src)/soc/intel/meteorlake CPPFLAGS_common += -I$(src)/soc/intel/meteorlake/include +# Include the missing MemInfoHob.h from vendorcode +CPPFLAGS_common += -I$(src)/vendorcode/intel/fsp/fsp2_0/iot/meteorlake + ifeq ($(CONFIG_SOC_INTEL_METEORLAKE_U_H),y) cpu_microcode_bins += 3rdparty/intel-microcode/intel-ucode/06-aa-04 endif diff --git a/src/soc/intel/meteorlake/acpi/pcie.asl b/src/soc/intel/meteorlake/acpi/pcie.asl index 386a57d26c0..889889cffdb 100644 --- a/src/soc/intel/meteorlake/acpi/pcie.asl +++ b/src/soc/intel/meteorlake/acpi/pcie.asl @@ -296,6 +296,16 @@ Device (RP12) Method (_PRT) { - Return (IRQM (RPPN)) + Return (IRQM (1)) } } + +Device (SRAM) +{ + Name (_ADR, 0x00140002) +} + +Device (HEC1) +{ + Name (_ADR, 0x00160000) +} diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index a0a13997cb7..b3ec0ad6610 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -73,6 +73,7 @@ const char *soc_acpi_name(const struct device *dev) switch (dev->path.pci.devfn) { case PCI_DEVFN_ROOT: return "MCHC"; case PCI_DEVFN_IGD: return "GFX0"; + case PCI_DEVFN_DPTF: return "DPTF"; case PCI_DEVFN_TCSS_XHCI: return "TXHC"; case PCI_DEVFN_TCSS_XDCI: return "TXDC"; case PCI_DEVFN_TCSS_DMA0: return "TDM0"; @@ -116,6 +117,8 @@ const char *soc_acpi_name(const struct device *dev) case PCI_DEVFN_HDA: return "HDAS"; case PCI_DEVFN_SMBUS: return "SBUS"; case PCI_DEVFN_GBE: return "GLAN"; + case PCI_DEVFN_CSE: return "HEC1"; + case PCI_DEVFN_SRAM: return "SRAM"; } printk(BIOS_DEBUG, "Missing ACPI Name for PCI: 00:%02x.%01x\n", PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); diff --git a/src/soc/intel/meteorlake/finalize.c b/src/soc/intel/meteorlake/finalize.c index 1fd1d98fb5f..3e95c8547a3 100644 --- a/src/soc/intel/meteorlake/finalize.c +++ b/src/soc/intel/meteorlake/finalize.c @@ -54,8 +54,16 @@ static void sa_finalize(void) static void heci_finalize(void) { + bool heci_disable = false; + heci_set_to_d0i3(); - if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) + + if (is_cse_enabled()) { + heci_disable = cse_is_hfs1_com_debug() || + cse_is_hfs1_com_soft_temp_disable(); + } + + if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) || heci_disable) heci1_disable(); } @@ -64,7 +72,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + tbt_finalize(); sa_finalize(); if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 5bd28aad2cd..b2fdeb36ca2 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -437,7 +438,7 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg, /* D3Hot and D3Cold for TCSS */ s_cfg->D3HotEnable = !config->tcss_d3_hot_disable; - s_cfg->D3ColdEnable = CONFIG(D3COLD_SUPPORT); + s_cfg->D3ColdEnable = get_sleep_type_option() == SLEEP_TYPE_OPTION_S0IX; s_cfg->UsbTcPortEn = 0; for (int i = 0; i < MAX_TYPE_C_PORTS; i++) { @@ -565,7 +566,7 @@ static void fill_fsps_thermal_params(FSP_S_CONFIG *s_cfg, s_cfg->Device4Enable = is_devfn_enabled(PCI_DEVFN_DPTF); /* Set TccActivationOffset */ - s_cfg->TccActivationOffset = config->tcc_offset; + s_cfg->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); } static void fill_fsps_lan_params(FSP_S_CONFIG *s_cfg, @@ -744,7 +745,7 @@ static void arch_silicon_init_params(FSPS_ARCHx_UPD *s_arch_cfg) #endif /* Assign FspEventHandler arch Upd to use coreboot debug event handler */ - if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(CONSOLE_SERIAL) && + if (CONFIG(FSP_USES_CB_DEBUG_EVENT_HANDLER) && CONFIG(FSP_ENABLE_SERIAL_DEBUG)) #if CONFIG(PLATFORM_USES_FSP2_X86_32) diff --git a/src/soc/intel/meteorlake/include/soc/iomap.h b/src/soc/intel/meteorlake/include/soc/iomap.h index 742af482e37..03ef56d3d81 100644 --- a/src/soc/intel/meteorlake/include/soc/iomap.h +++ b/src/soc/intel/meteorlake/include/soc/iomap.h @@ -66,9 +66,10 @@ #define IOE_P2SB_BAR IOE_PCR_ABOVE_4G_BASE_ADDR #define IOE_P2SB_SIZE (256 * MiB) -#define IOM_BASE_ADDR 0x3fff0aa0000 +/* IOE_P2SB_BAR + 0xaa0000, but iasl refuses to perform arithmetics */ +#define IOM_BASE_ADDR 0x60aa0000 #define IOM_BASE_SIZE 0x1600 -#define IOM_BASE_ADDR_MAX 0x3fff0aa15ff +#define IOM_BASE_ADDR_MAX 0x60aa15ff /* * I/O port address space diff --git a/src/soc/intel/meteorlake/meminit.c b/src/soc/intel/meteorlake/meminit.c index dae175fd1a0..2b2edcca38d 100644 --- a/src/soc/intel/meteorlake/meminit.c +++ b/src/soc/intel/meteorlake/meminit.c @@ -38,18 +38,16 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { .num_phys_channels = DDR5_CHANNELS, .phys_to_mrc_map = { [0] = 0, - [1] = 1, - [2] = 4, - [3] = 5, + [1] = 4, }, .md_phy_masks = { /* - * Physical channels 0 and 1 are populated in case of - * half-populated configurations. + * Only channel 0 is populated in case of half-populated + * configuration. */ - .half_channel = BIT(0) | BIT(1), - /* In mixed topologies, channels 2 and 3 are always memory-down. */ - .mixed_topo = BIT(2) | BIT(3), + .half_channel = BIT(0), + /* In mixed topologies, either channel 0 or 1 can be memory-down. */ + .mixed_topo = BIT(0) | BIT(1), }, }, [MEM_TYPE_LP5X] = { @@ -75,7 +73,8 @@ static const struct soc_mem_cfg soc_mem_cfg[] = { }, }; -static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data) +static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_data *data, + bool expand_channels) { efi_uintn_t *spd_upds[MRC_CHANNELS][CONFIG_DIMMS_PER_CHANNEL] = { [0] = { &mem_cfg->MemorySpdPtr000, &mem_cfg->MemorySpdPtr001, }, @@ -108,7 +107,16 @@ static void mem_init_spd_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da for (dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { efi_uintn_t *spd_ptr = spd_upds[ch][dimm]; - *spd_ptr = data->spd[ch][dimm]; + // In DDR5 systems, we need to copy the SPD data such that: + // Channel 0 data is used by channel 0 and 1 + // Channel 2 data is used by channel 2 and 3 + // Channel 4 data is used by channel 4 and 5 + // Channel 6 data is used by channel 6 and 7 + if (expand_channels) + *spd_ptr = data->spd[ch & 6][dimm]; + else + *spd_ptr = data->spd[ch][dimm]; + if (*spd_ptr) enable_channel = 1; } @@ -174,27 +182,12 @@ static void mem_init_dqs_upds(FSP_M_CONFIG *mem_cfg, const struct mem_channel_da mem_init_dq_dqs_upds(dqs_upds, mb_cfg->dqs_map, upd_size, data, auto_detect); } -#define DDR5_CH_DIMM_OFFSET(ch, dimm) ((ch) * CONFIG_DIMMS_PER_CHANNEL + (dimm)) - -static void ddr5_fill_dimm_module_info(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *mb_cfg, - const struct mem_spd *spd_info) -{ - for (size_t ch = 0; ch < soc_mem_cfg[MEM_TYPE_DDR5].num_phys_channels; ch++) { - for (size_t dimm = 0; dimm < CONFIG_DIMMS_PER_CHANNEL; dimm++) { - size_t mrc_ch = soc_mem_cfg[MEM_TYPE_DDR5].phys_to_mrc_map[ch]; - mem_cfg->SpdAddressTable[DDR5_CH_DIMM_OFFSET(mrc_ch, dimm)] = - spd_info->smbus[ch].addr_dimm[dimm] << 1; - } - } - mem_init_dq_upds(mem_cfg, NULL, mb_cfg, true); - mem_init_dqs_upds(mem_cfg, NULL, mb_cfg, true); -} - void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, const struct mem_spd *spd_info, bool half_populated) { struct mem_channel_data data; bool dq_dqs_auto_detect = false; + bool expand_channels = false; FSP_M_CONFIG *mem_cfg = &memupd->FspmConfig; mem_cfg->ECT = mb_cfg->ect; @@ -205,14 +198,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, case MEM_TYPE_DDR5: meminit_ddr(mem_cfg, &mb_cfg->ddr_config); dq_dqs_auto_detect = true; - /* - * TODO: Drop this workaround once SMBus driver in coreboot is updated to - * support DDR5 EEPROM reading. - */ - if (spd_info->topo == MEM_TOPO_DIMM_MODULE) { - ddr5_fill_dimm_module_info(mem_cfg, mb_cfg, spd_info); - return; - } + expand_channels = true; break; case MEM_TYPE_LP5X: meminit_lp5x(mem_cfg, &mb_cfg->lp5x_config); @@ -221,9 +207,9 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, die("Unsupported memory type(%d)\n", mb_cfg->type); } - mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, - half_populated, &data); - mem_init_spd_upds(mem_cfg, &data); + mem_populate_channel_data(memupd, &soc_mem_cfg[mb_cfg->type], spd_info, half_populated, + &data); + mem_init_spd_upds(mem_cfg, &data, expand_channels); mem_init_dq_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); mem_init_dqs_upds(mem_cfg, &data, mb_cfg, dq_dqs_auto_detect); } diff --git a/src/soc/intel/meteorlake/romstage/fsp_params.c b/src/soc/intel/meteorlake/romstage/fsp_params.c index 82706ed3bff..100c50d3df4 100644 --- a/src/soc/intel/meteorlake/romstage/fsp_params.c +++ b/src/soc/intel/meteorlake/romstage/fsp_params.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -17,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -62,7 +64,12 @@ static void pcie_rp_init(FSP_M_CONFIG *m_cfg, uint32_t en_mask, m_cfg->PcieClkSrcClkReq[cfg[i].clk_src] = cfg[i].clk_req; clk_req_mapping |= 1 << cfg[i].clk_req; } - m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; + /* + * Override the usage only if the clock is unused, otherwise we lose + * FSP_CLK_FREE_RUNNING and FSP_CLK_LAN setting from fill_fspm_pcie_rp_params. + */ + if (m_cfg->PcieClkSrcUsage[cfg[i].clk_src] == FSP_CLK_NOTUSED) + m_cfg->PcieClkSrcUsage[cfg[i].clk_src] = i; } } @@ -168,7 +175,7 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->RMC = 0; m_cfg->MarginLimitCheck = 0; /* Enable MRC Fast Boot */ - m_cfg->MrcFastBoot = 1; + m_cfg->MrcFastBoot = !vbnv_cmos_failed(); m_cfg->LowerBasicMemTestSize = config->lower_basic_mem_test_size; } @@ -285,6 +292,8 @@ static void fill_fspm_misc_params(FSP_M_CONFIG *m_cfg, static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_meteorlake_config *config) { + const struct device *dev; + /* Audio: HDAUDIO_LINK_MODE I2S/SNDW */ m_cfg->PchHdaEnable = is_devfn_enabled(PCI_DEVFN_HDA); m_cfg->PchHdaDspEnable = config->pch_hda_dsp_enable; @@ -299,6 +308,13 @@ static void fill_fspm_audio_params(FSP_M_CONFIG *m_cfg, memset(m_cfg->PchHdaAudioLinkDmicEnable, 0, sizeof(m_cfg->PchHdaAudioLinkDmicEnable)); memset(m_cfg->PchHdaAudioLinkSspEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSspEnable)); memset(m_cfg->PchHdaAudioLinkSndwEnable, 0, sizeof(m_cfg->PchHdaAudioLinkSndwEnable)); + + dev = pcidev_path_on_root(PCI_DEVFN_HDA); + if (dev) { + uint16_t svid = CONFIG_SUBSYSTEM_VENDOR_ID ? : (dev->subsystem_vendor ? : 0x8086); + uint16_t ssid = CONFIG_SUBSYSTEM_DEVICE_ID ? : (dev->subsystem_device ? : 0x7e28); + m_cfg->PchHdaSubSystemIds = (ssid << 16) | svid; + } } static void fill_fspm_cnvi_params(FSP_M_CONFIG *m_cfg, @@ -359,6 +375,8 @@ static void fill_fspm_vtd_params(FSP_M_CONFIG *m_cfg, /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); + + m_cfg->PreBootDmaMask = CONFIG(ENABLE_EARLY_DMA_PROTECTION) && dma_protection_enabled(); } static void fill_fspm_trace_params(FSP_M_CONFIG *m_cfg, diff --git a/src/soc/intel/meteorlake/romstage/romstage.c b/src/soc/intel/meteorlake/romstage/romstage.c index 5ceb6d55778..9284b67383b 100644 --- a/src/soc/intel/meteorlake/romstage/romstage.c +++ b/src/soc/intel/meteorlake/romstage/romstage.c @@ -9,6 +9,7 @@ #include #include #include +#include #include #include #include @@ -47,7 +48,6 @@ static void save_dimm_info(void) printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); return; } - /* * Allocate CBMEM area for DIMM information used to populate SMBIOS * table 17 @@ -69,6 +69,10 @@ static void save_dimm_info(void) dimm_max = ARRAY_SIZE(mem_info->dimm); for (node = 0; node < MAX_NODE; node++) { ctrlr_info = &meminfo_hob->Controller[node]; + + if (ctrlr_info->Status != CHANNEL_PRESENT) + continue; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { channel_info = &ctrlr_info->ChannelInfo[channel]; if (channel_info->Status != CHANNEL_PRESENT) @@ -91,6 +95,8 @@ static void save_dimm_info(void) uint8_t memProfNum = meminfo_hob->MemoryProfile; serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; + printk(BIOS_DEBUG, "Filling DIMM info for Controller %d Channel %d DIMM %d\n", + node, channel, dimm); /* Populate the DIMM information */ dimm_info_fill(dest_dimm, src_dimm->DimmCapacity, @@ -155,4 +161,7 @@ void mainboard_romstage_entry(void) pmc_set_disb(); if (!s3wake) save_dimm_info(); + + if (CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + vtd_enable_dma_protection(); } diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 81dbe8050d1..4f6f658fc14 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -79,6 +79,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 select SOC_INTEL_COMMON_BLOCK_PMC_EPOC select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_COMMON_BLOCK_RUNTIME_CORE_SCALING_FACTORS select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SMM select SOC_INTEL_COMMON_BLOCK_SMM_IO_TRAP @@ -248,14 +249,6 @@ config P2SB_2_PCR_BASE_ADDRESS config ECAM_MMCONF_BASE_ADDRESS default 0xe0000000 -config SOC_INTEL_PERFORMANCE_CORE_SCALE_FACTOR - int - default 125 # TODO: Update with PTL data - -config SOC_INTEL_EFFICIENT_CORE_SCALE_FACTOR - int - default 100 # TODO: Update with PTL data - config CPU_BCLK_MHZ int default 100 diff --git a/src/soc/intel/pantherlake/finalize.c b/src/soc/intel/pantherlake/finalize.c index 05ec3eaaca9..186a2b87b42 100644 --- a/src/soc/intel/pantherlake/finalize.c +++ b/src/soc/intel/pantherlake/finalize.c @@ -64,6 +64,9 @@ static void soc_finalize(void *unused) pch_finalize(); apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + tbt_finalize(); sa_finalize(); if (CONFIG(USE_FSP_NOTIFY_PHASE_READY_TO_BOOT) && diff --git a/src/soc/intel/pantherlake/include/soc/systemagent.h b/src/soc/intel/pantherlake/include/soc/systemagent.h index fbe8dd25cce..4139c37aff5 100644 --- a/src/soc/intel/pantherlake/include/soc/systemagent.h +++ b/src/soc/intel/pantherlake/include/soc/systemagent.h @@ -23,6 +23,8 @@ #define MCH_DDR_POWER_LIMIT_HI 0x58e4 #define MCH_PKG_POWER_LIMIT_LO 0x59a0 #define MCH_PKG_POWER_LIMIT_HI 0x59a4 +#define PCODE_MAILBOX_DATA 0x5da0 +#define PCODE_MAILBOX_INTERFACE 0x5da4 #define BIOS_RESET_CPL 0x5da8 #define IMRBASE 0x6a40 #define IMRLIMIT 0x6a48 diff --git a/src/soc/intel/pantherlake/systemagent.c b/src/soc/intel/pantherlake/systemagent.c index e7a0701f98b..a5a734f02dc 100644 --- a/src/soc/intel/pantherlake/systemagent.c +++ b/src/soc/intel/pantherlake/systemagent.c @@ -2,9 +2,12 @@ #include #include +#include #include +#include #include #include +#include #include #include #include @@ -183,6 +186,142 @@ static void configure_tdp(struct device *dev) } } +union pcode_mailbox_command { + struct { + uint32_t command: 8; + uint32_t param1: 8; + uint32_t param2: 13; + uint32_t reserved: 2; + /* + * Run/Busy bit. This bit is set by BIOS to indicate the mailbox buffer is + * ready. pcode will clear this bit after the message is + * consumed. + */ + uint32_t runbusy: 1; + } fields; + uint32_t data; +}; + +union pcode_scaling_factor { + struct { + /* Core scaling factor */ + uint32_t scaling_factor: 16; + /* + * Number of modules with consecutive module id sharing the same scaling + * factor + */ + uint32_t num_equivalent_module: 8; + uint32_t reserved: 8; + } fields; + uint32_t data; +}; + +#define MAILBOX_WAIT_TIMEOUT_US 1000 +#define PCODE_READ_CORE_SCALING_FACTOR_CMD 0x21 + +static bool poll_mailbox_ready(void) +{ + union pcode_mailbox_command cmd; + size_t i; + + for (i = 0; i < MAILBOX_WAIT_TIMEOUT_US; i++) { + cmd.data = MCHBAR32(PCODE_MAILBOX_INTERFACE); + if (!cmd.fields.runbusy) + return true; + udelay(1); + } + return false; +} + +static u16 u88_to_scaling_factor(u16 u88) +{ + unsigned int tmp = (u88 & 0xff) * 100; + unsigned int fraction = tmp / (1 << 8); + + /* Rounding */ + if (((tmp & 0xff) << 1) >= (1 << 8)) + fraction++; + return ((u88 >> 8) * 100) + fraction; +} + +/* + * The following function sends commands to the pcode mailbox interface to read the core scaling + * factors for performance and efficient cores. + * + * The READ_CORE_SCALING_FACTOR command takes a module ID as a parameter. The function iterates + * over all the CPU devices to identify module IDs of different core types (efficient and + * performance). + * + * If no efficient cores are present, no efficient factor is returned. + * + * Return values: + * - CB_ERR_ARG: If any of the input pointers were NULL. + * - CB_ERR: If there was a generic error while reading the scaling factors. + * - CB_SUCCESS: If the scaling factors were read successfully. + */ +enum cb_err soc_read_core_scaling_factors(u16 *performance, u16 *efficient) +{ + extern struct cpu_info cpu_infos[]; + union pcode_mailbox_command cmd = { + .fields = { + .command = PCODE_READ_CORE_SCALING_FACTOR_CMD, + .runbusy = 1 + } + }; + union pcode_scaling_factor res; + bool has_efficient_core = false; + + if (!performance || !efficient) + return CB_ERR_ARG; + + for (size_t i = 0; i < CONFIG_MAX_CPUS; i++) { + struct device *cpu = cpu_infos[i].cpu; + + if (!cpu) + continue; + + if (cpu->path.apic.core_type != CPU_TYPE_PERF) + has_efficient_core = true; + + if (cpu->path.apic.core_type == CPU_TYPE_PERF && *performance) + continue; + + cmd.fields.param1 = cpu->path.apic.module_id; + + if (!poll_mailbox_ready()) { + printk(BIOS_ERR, "pcode mailbox is busy\n"); + return CB_ERR; + } + + MCHBAR32(PCODE_MAILBOX_INTERFACE) = cmd.data; + + if (!poll_mailbox_ready()) { + printk(BIOS_ERR, "pcode command mailbox not completing in time\n"); + return CB_ERR; + } + + res.data = MCHBAR32(PCODE_MAILBOX_DATA); + + if (cpu->path.apic.core_type == CPU_TYPE_PERF) + *performance = u88_to_scaling_factor(res.fields.scaling_factor); + else + *efficient = u88_to_scaling_factor(res.fields.scaling_factor); + + if (*performance && *efficient) + break; + } + + if (!*performance) { + printk(BIOS_ERR, "Could not read performance scaling factor\n"); + return CB_ERR; + } + if (has_efficient_core && !*efficient) { + printk(BIOS_ERR, "Could not read efficient scaling factor\n"); + return CB_ERR; + } + return CB_SUCCESS; +} + /* * SoC implementation * diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a6844e068a0..153777a95d9 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -501,7 +502,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) tconfig->Eist = config->eist_enable; /* Set TccActivationOffset */ - tconfig->TccActivationOffset = config->tcc_offset; + tconfig->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); /* Already handled in coreboot code, so tell FSP to ignore UPDs */ params->PchIoApicBdfValid = 0; diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index fd80aeac1a0..a147b62e46f 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -106,7 +106,8 @@ static void soc_finalize(void *unused) pch_finalize_script(dev); soc_lockdown(dev); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); /* Indicate finalize step with post code */ post_code(POSTCODE_OS_BOOT); diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 1b04fbc0c8f..ff7cf652892 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -69,6 +69,7 @@ config SOC_INTEL_TIGERLAKE select SOC_INTEL_COMMON_BLOCK_USB4 select SOC_INTEL_COMMON_BLOCK_USB4_PCIE select SOC_INTEL_COMMON_BLOCK_USB4_XHCI + select SOC_INTEL_COMMON_BLOCK_VTD select SOC_INTEL_COMMON_BLOCK_XHCI_ELOG select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT @@ -76,17 +77,15 @@ config SOC_INTEL_TIGERLAKE select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT select SOC_INTEL_CSE_SEND_EOP_LATE select SOC_INTEL_CSE_SET_EOP + select HAVE_INTEL_ME_HAP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_2017_BINDING - select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM - select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT - select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE select SOC_INTEL_COMMON_BASECODE - select SOC_INTEL_COMMON_BASECODE_RAMTOP + select SOC_INTEL_COMMON_BASECODE_RAMTOP if CHROMEOS select CR50_USE_LONG_INTERRUPT_PULSES if TPM_GOOGLE_CR50 select X86_CLFLUSH_CAR help diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c index dd9ef731a3d..bb12f697a48 100644 --- a/src/soc/intel/tigerlake/acpi.c +++ b/src/soc/intel/tigerlake/acpi.c @@ -326,6 +326,8 @@ void soc_fill_gnvs(struct global_nvs *gnvs) /* Set USB2/USB3 wake enable bitmaps. */ gnvs->u2we = config->usb2_wake_enable_bitmap; gnvs->u3we = config->usb3_wake_enable_bitmap; + + gnvs->s0ix = config->s0ix_enable; } int soc_madt_sci_irq_polarity(int sci) diff --git a/src/soc/intel/tigerlake/acpi/tcss.asl b/src/soc/intel/tigerlake/acpi/tcss.asl index 588ed5e2857..fd827ed70cf 100644 --- a/src/soc/intel/tigerlake/acpi/tcss.asl +++ b/src/soc/intel/tigerlake/acpi/tcss.asl @@ -331,7 +331,7 @@ Scope (\_SB.PCI0) Name (_CRS, ResourceTemplate () { Memory32Fixed (ReadWrite, IOM_BASE_ADDRESS, IOM_BASE_SIZE) }) - Name (_STA, 0xF) + Name (_STA, 0xB) } /* @@ -542,47 +542,6 @@ Scope (\_SB.PCI0) } } - PowerResource (TBT0, 5, 1) - { - Method (_STA, 0) - { - Return (\_SB.PCI0.TDM0.STAT) - } - - Method (_ON, 0) - { - TG0N() - } - - Method (_OFF, 0) - { - If (\_SB.PCI0.TDM0.SD3C == 0) { - TG0F() - } - } - } - - PowerResource (TBT1, 5, 1) - { - Method (_STA, 0) - { - Return (\_SB.PCI0.TDM1.STAT) - } - - Method (_ON, 0) - { - TG1N() - } - - Method (_OFF, 0) - { - If (\_SB.PCI0.TDM1.SD3C == 0) { - TG1F() - } - } - } - -#if CONFIG(D3COLD_SUPPORT) Method (TCON, 0) { /* Reset IOM D3 cold bit if it is in D3 cold now. */ @@ -627,33 +586,74 @@ Scope (\_SB.PCI0) TD3C = 1 } - PowerResource (D3C, 5, 0) - { - /* - * Variable to save power state - * 1 - TC Cold request cleared. - * 0 - TC Cold request sent. - */ - Name (STAT, 0x1) - - Method (_STA, 0) + If (S0IX == 1) { + PowerResource (TBT0, 5, 1) { - Return (STAT) + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM0.STAT) + } + + Method (_ON, 0) + { + TG0N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM0.SD3C == 0) { + TG0F() + } + } } - Method (_ON, 0) + PowerResource (TBT1, 5, 1) { - \_SB.PCI0.TCON() - STAT = 1 + Method (_STA, 0) + { + Return (\_SB.PCI0.TDM1.STAT) + } + + Method (_ON, 0) + { + TG1N() + } + + Method (_OFF, 0) + { + If (\_SB.PCI0.TDM1.SD3C == 0) { + TG1F() + } + } } - Method (_OFF, 0) + PowerResource (D3C, 5, 0) { - \_SB.PCI0.TCOF() - STAT = 0 + /* + * Variable to save power state + * 1 - TC Cold request cleared. + * 0 - TC Cold request sent. + */ + Name (STAT, 0x1) + + Method (_STA, 0) + { + Return (STAT) + } + + Method (_ON, 0) + { + \_SB.PCI0.TCON() + STAT = 1 + } + + Method (_OFF, 0) + { + \_SB.PCI0.TCOF() + STAT = 0 + } } - } -#endif // D3COLD_SUPPORT + } // S0IX == 1 /* * TCSS xHCI device diff --git a/src/soc/intel/tigerlake/acpi/tcss_dma.asl b/src/soc/intel/tigerlake/acpi/tcss_dma.asl index 2586ecbbc75..54cc68ffb40 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_dma.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_dma.asl @@ -28,49 +28,32 @@ Name (STAT, 0x1) /* Variable to save power state 1 - D0, 0 - D3C */ Method (_S0W, 0x0) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x04) -#else - Return (0x03) -#endif // D3COLD_SUPPORT -} - -/* - * Get power resources that are dependent on this device for Operating System Power Management - * to put the device in the D0 device state - */ -Method (_PR0) -{ -#if CONFIG(D3COLD_SUPPORT) - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) - } -#else - If (DUID == 0) { - Return (Package() { \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + Return (0x04) } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + Return (0x03) } -#endif // D3COLD_SUPPORT } -Method (_PR3) -{ -#if CONFIG(D3COLD_SUPPORT) - If (DUID == 0) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) +If (S0IX == 1) { + Method (_PR0) + { + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#else - If (DUID == 0) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + + Method (_PR3) + { + + If (DUID == 0) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl index 6dbde46f49d..f40c012b4f5 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_pcierp.asl @@ -245,47 +245,34 @@ Method (_PS3, 0, Serialized) } } -Method (_S0W, 0x0, NotSerialized) -{ -#if CONFIG(D3COLD_SUPPORT) - Return (0x4) -#else - Return (0x3) -#endif // D3COLD_SUPPORT -} -Method (_PR0) +Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + If (S0IX == 1) { + Return (0x04) } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + Return (0x03) } -#else - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) - } -#endif // D3COLD_SUPPORT } -Method (_PR3) -{ -#if CONFIG(D3COLD_SUPPORT) - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) +If (S0IX == 1) { + Method (_PR0) + { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#else - If ((TUID == 0) || (TUID == 1)) { - Return (Package() { \_SB.PCI0.TBT0 }) - } Else { - Return (Package() { \_SB.PCI0.TBT1 }) + + Method (_PR3) + { + If ((TUID == 0) || (TUID == 1)) { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT0 }) + } Else { + Return (Package() { \_SB.PCI0.D3C, \_SB.PCI0.TBT1 }) + } } -#endif // D3COLD_SUPPORT } /* diff --git a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl index ddc5a6665dc..1ca4117697c 100644 --- a/src/soc/intel/tigerlake/acpi/tcss_xhci.asl +++ b/src/soc/intel/tigerlake/acpi/tcss_xhci.asl @@ -30,11 +30,11 @@ Method (_PS3, 0, Serialized) Method (_S0W, 0x0, NotSerialized) { -#if CONFIG(D3COLD_SUPPORT) - Return (0x4) -#else - Return (0x3) -#endif // D3COLD_SUPPORT + If (S0IX == 1) { + Return (0x4) + } Else { + Return (0x3) + } } /* @@ -43,17 +43,17 @@ Method (_S0W, 0x0, NotSerialized) */ Name (SD3C, 0) -#if CONFIG(D3COLD_SUPPORT) -Method (_PR0) -{ - Return (Package () { \_SB.PCI0.D3C }) -} +If (S0IX == 1) { + Method (_PR0) + { + Return (Package () { \_SB.PCI0.D3C }) + } -Method (_PR3) -{ - Return (Package () { \_SB.PCI0.D3C }) + Method (_PR3) + { + Return (Package () { \_SB.PCI0.D3C }) + } } -#endif // D3COLD_SUPPORT /* * XHCI controller _DSM method diff --git a/src/soc/intel/tigerlake/finalize.c b/src/soc/intel/tigerlake/finalize.c index cd02745a9e6..158b2fb6916 100644 --- a/src/soc/intel/tigerlake/finalize.c +++ b/src/soc/intel/tigerlake/finalize.c @@ -55,7 +55,9 @@ static void soc_finalize(void *unused) printk(BIOS_DEBUG, "Finalizing chipset.\n"); pch_finalize(); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); + tbt_finalize(); if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT)) heci1_disable(); diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c index c3400b45c93..0060a4e1592 100644 --- a/src/soc/intel/tigerlake/fsp_params.c +++ b/src/soc/intel/tigerlake/fsp_params.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -329,7 +330,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) if (cpu_id == CPUID_TIGERLAKE_A0) params->D3ColdEnable = 0; else - params->D3ColdEnable = CONFIG(D3COLD_SUPPORT); + params->D3ColdEnable = get_sleep_type_option() == SLEEP_TYPE_OPTION_S0IX; params->UsbTcPortEn = config->UsbTcPortEn; params->TcssAuxOri = config->TcssAuxOri; @@ -489,7 +490,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) params->Device4Enable = is_devfn_enabled(SA_DEVFN_DPTF); /* Set TccActivationOffset */ - params->TccActivationOffset = config->tcc_offset; + params->TccActivationOffset = get_cpu_throttling_offset(config->tcc_offset); /* LAN */ params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE); diff --git a/src/soc/intel/tigerlake/include/soc/dptf.h b/src/soc/intel/tigerlake/include/soc/dptf.h index 467ac659158..83278f4dfcf 100644 --- a/src/soc/intel/tigerlake/include/soc/dptf.h +++ b/src/soc/intel/tigerlake/include/soc/dptf.h @@ -10,5 +10,9 @@ #define DPTF_GEN_DEVICE "INTC1043" /* Fan ACPI Device ID */ #define DPTF_FAN_DEVICE "INTC1044" +/* TPWR ACPI Device ID */ +#define DPTF_TPWR_DEVICE "INTC1047" +/* BAT1 ACPI Device ID */ +#define DPTF_BAT1_DEVICE "INTC1050" #endif /* _SOC_DPTF_H_ */ diff --git a/src/soc/intel/tigerlake/include/soc/pmc.h b/src/soc/intel/tigerlake/include/soc/pmc.h index ee02a48a444..ee5783aa6a2 100644 --- a/src/soc/intel/tigerlake/include/soc/pmc.h +++ b/src/soc/intel/tigerlake/include/soc/pmc.h @@ -77,6 +77,10 @@ extern struct device_operations pmc_ops; #define PRSTS 0x1810 +#define PM_CFG 0x1818 +#define PM_CFG_DBG_MODE_LOCK (1 << 27) +#define PM_CFG_XRAM_READ_DISABLE (1 << 22) + #define S3_PWRGATE_POL 0x1828 #define S3DC_GATE_SUS (1 << 1) #define S3AC_GATE_SUS (1 << 0) @@ -157,6 +161,9 @@ extern struct device_operations pmc_ops; #define ACPI_EN (1 << 7) #define SCI_IRQ_SEL (7 << 0) +#define ST_PG_FDIS1 0x1e20 +#define ST_FDIS_LOCK (1 << 31) + #define SCIS_IRQ9 0 #define SCIS_IRQ10 1 #define SCIS_IRQ11 2 diff --git a/src/soc/intel/tigerlake/lockdown.c b/src/soc/intel/tigerlake/lockdown.c index 2f7ccebc8b3..5413fae5ac6 100644 --- a/src/soc/intel/tigerlake/lockdown.c +++ b/src/soc/intel/tigerlake/lockdown.c @@ -8,10 +8,17 @@ #include #include +#include +#include #include +#include #include #include +/* PCR PSTH Control Register */ +#define PCR_PSTH_CTRLREG 0x1d00 +#define PSTH_CTRLREG_IOSFPTCGE (1 << 2) + static void pmc_lock_pmsync(void) { uint8_t *pmcbase; @@ -50,6 +57,8 @@ static void pmc_lock_smi(void) static void pmc_lockdown_cfg(int chipset_lockdown) { + uint8_t *pmcbase = pmc_mmio_regs(); + /* PMSYNC */ pmc_lock_pmsync(); /* Lock down ABASE and sleep stretching policy */ @@ -57,10 +66,31 @@ static void pmc_lockdown_cfg(int chipset_lockdown) if (chipset_lockdown == CHIPSET_LOCKDOWN_COREBOOT) pmc_lock_smi(); + + if (!CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) { + setbits32(pmcbase + ST_PG_FDIS1, ST_FDIS_LOCK); + setbits32(pmcbase + SSML, SSML_SSL_EN); + setbits32(pmcbase + PM_CFG, PM_CFG_DBG_MODE_LOCK | + PM_CFG_XRAM_READ_DISABLE); + } + + /* Send PMC IPC to inform about PCI enumeration done */ + pmc_send_bios_reset_pci_enum_done(); +} + +static void pch_lockdown_cfg(void) +{ + if (CONFIG(USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM)) + return; + + /* Enable IOSF Primary Trunk Clock Gating */ + pcr_rmw32(PID_PSTH, PCR_PSTH_CTRLREG, ~0, PSTH_CTRLREG_IOSFPTCGE); } void soc_lockdown_config(int chipset_lockdown) { /* PMC lock down configuration */ pmc_lockdown_cfg(chipset_lockdown); + /* PCH lock down configuration */ + pch_lockdown_cfg(); } diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 8912cb3c63e..8846c944648 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -107,7 +107,7 @@ static void soc_pmc_fill_ssdt(const struct device *dev) acpigen_write_name_string("_HID", PMC_HID); acpigen_write_name_string("_DDN", "Intel(R) Tiger Lake IPC Controller"); - acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + acpigen_write_STA(ACPI_STATUS_DEVICE_HIDDEN_ON); /* * Part of the PCH's reserved 32 MB MMIO range (0xFC800000 - 0xFE7FFFFF). diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 5ebd46dd75d..ee6a1fd7451 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -183,6 +184,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->VtdBaseAddress[6] = TBT3_BASE_ADDRESS; } + m_cfg->PreBootDmaMask = CONFIG(ENABLE_EARLY_DMA_PROTECTION) && dma_protection_enabled(); + /* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */ m_cfg->VmxEnable = CONFIG(ENABLE_VMX); diff --git a/src/soc/intel/tigerlake/romstage/romstage.c b/src/soc/intel/tigerlake/romstage/romstage.c index 1985ea3c5bc..b7a13d28384 100644 --- a/src/soc/intel/tigerlake/romstage/romstage.c +++ b/src/soc/intel/tigerlake/romstage/romstage.c @@ -8,6 +8,7 @@ #include #include #include +#include #include #include #include @@ -150,4 +151,7 @@ void mainboard_romstage_entry(void) save_dimm_info(); } + + if (CONFIG(ENABLE_EARLY_DMA_PROTECTION)) + vtd_enable_dma_protection(); } diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c index a7b36027442..f0cd8a1998f 100644 --- a/src/soc/intel/xeon_sp/finalize.c +++ b/src/soc/intel/xeon_sp/finalize.c @@ -59,7 +59,8 @@ static void soc_finalize(void *unused) if (!CONFIG(USE_PM_ACPI_TIMER)) setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); - apm_control(APM_CNT_FINALIZE); + if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3()) + apm_control(APM_CNT_FINALIZE); if (CONFIG_MAX_SOCKET > 1) { /* This MSR is package scope but run for all cpus for code simplicity */ diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 134b57546d2..11bb87c7ac1 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -13,7 +13,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS select ACPI_COMMON_MADT_IOAPIC select ACPI_COMMON_MADT_LAPIC select ACPI_CUSTOM_MADT - select HAVE_CONFIGURABLE_APMC_SMI_PORT select HAVE_USBDEBUG_OPTIONS select HAVE_CF9_RESET select HAVE_CF9_RESET_PREPARE @@ -24,6 +23,9 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS select SOC_AMD_COMMON_BLOCK_BANKED_GPIOS_NON_SOC_CODEBASE select SOC_AMD_COMMON_BLOCK_PCI_MMCONF + select SOC_AMD_COMMON_BLOCK_SPI if SOUTHBRIDGE_AMD_PI_AVALON + select BOOT_DEVICE_SUPPORTS_WRITES if SOUTHBRIDGE_AMD_PI_AVALON + select BOOT_DEVICE_SPI_FLASH_RW_NOMMAP_EARLY if SOUTHBRIDGE_AMD_PI_AVALON select USE_AMDFWTOOL config EHCI_BAR diff --git a/src/southbridge/amd/pi/hudson/Makefile.mk b/src/southbridge/amd/pi/hudson/Makefile.mk index e7ec1b73ec5..2e40edcaa64 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.mk +++ b/src/southbridge/amd/pi/hudson/Makefile.mk @@ -35,6 +35,7 @@ all-y += reset.c smm-y += smihandler.c smm-y += smi_util.c +smm-y += lpc_simpledev.c CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include @@ -50,7 +51,7 @@ CPPFLAGS_common += -I$(src)/southbridge/amd/pi/hudson/include ifeq ($(CONFIG_AMDFW_OUTSIDE_CBFS),y) HUDSON_FWM_POSITION=$(call int-add, $(call int-subtract, 0xffffffff $(CONFIG_ROM_SIZE)) 0x20000 1) else -HUDSON_FWM_POSITION=0xfff20000 +HUDSON_FWM_POSITION=0xfffa0000 endif ifeq ($(CONFIG_HUDSON_PSP), y) diff --git a/src/southbridge/amd/pi/hudson/bootblock.c b/src/southbridge/amd/pi/hudson/bootblock.c index faf549d2e8e..282dc0fc909 100644 --- a/src/southbridge/amd/pi/hudson/bootblock.c +++ b/src/southbridge/amd/pi/hudson/bootblock.c @@ -6,49 +6,11 @@ #include #include -/* - * Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF. - * - * Hardware should enable LPC ROM by pin straps. This function does not - * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. - * - * The HUDSON power-on default is to map 512K ROM space. - * - */ -static void hudson_enable_rom(void) -{ - u8 reg8; - const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); - - /* Decode variable LPC ROM address ranges 1 and 2. */ - reg8 = pci_s_read_config8(dev, 0x48); - reg8 |= (1 << 3) | (1 << 4); - pci_s_write_config8(dev, 0x48, reg8); - - /* LPC ROM address range 1: */ - /* Enable LPC ROM range mirroring start at 0x000e(0000). */ - pci_s_write_config16(dev, 0x68, 0x000e); - /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ - pci_s_write_config16(dev, 0x6a, 0x000f); - - /* LPC ROM address range 2: */ - /* - * Enable LPC ROM range start at: - * 0xfff8(0000): 512KB - * 0xfff0(0000): 1MB - * 0xffe0(0000): 2MB - * 0xffc0(0000): 4MB - */ - pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); - /* Enable LPC ROM range end at 0xffff(ffff). */ - pci_s_write_config16(dev, 0x6e, 0xffff); -} - void bootblock_early_southbridge_init(void) { u32 data; - hudson_enable_rom(); + hudson_enable_lpc_rom(); enable_acpimmio_decode_pm04(); hudson_lpc_decode(); diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 1e1a2f44aec..ad91cd36df2 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include @@ -191,13 +192,13 @@ void hudson_clk_output_48Mhz(void) misc_write32(FCH_MISC_REG40, ctrl); } -static uintptr_t hudson_spibase(void) +uintptr_t lpc_get_spibase(void) { /* Make sure the base address is predictable */ const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) - & 0xfffffff0; + & 0xffffffc0; if (!base) { base = SPI_BASE_ADDRESS; pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base @@ -209,7 +210,7 @@ static uintptr_t hudson_spibase(void) void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) { - uintptr_t base = hudson_spibase(); + uintptr_t base = lpc_get_spibase(); write16p(base + SPI100_SPEED_CONFIG, (norm << SPI_NORM_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) | @@ -221,7 +222,7 @@ void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm) void hudson_disable_4dw_burst(void) { - uintptr_t base = hudson_spibase(); + uintptr_t base = lpc_get_spibase(); write16p(base + SPI100_HOST_PREF_CONFIG, read16p(base + SPI100_HOST_PREF_CONFIG) & ~SPI_RD4DW_EN_HOST); @@ -230,7 +231,7 @@ void hudson_disable_4dw_burst(void) /* Hudson 1-3 only. For Hudson 1, call with fast=1 */ void hudson_set_readspeed(u16 norm, u16 fast) { - uintptr_t base = hudson_spibase(); + uintptr_t base = lpc_get_spibase(); write16p(base + SPI_CNTRL1, (read16p(base + SPI_CNTRL1) & ~SPI_CNTRL1_SPEED_MASK) @@ -240,7 +241,7 @@ void hudson_set_readspeed(u16 norm, u16 fast) void hudson_read_mode(u32 mode) { - uintptr_t base = hudson_spibase(); + uintptr_t base = lpc_get_spibase(); write32p(base + SPI_CNTRL0, (read32p(base + SPI_CNTRL0) & ~SPI_READ_MODE_MASK) | mode); @@ -255,4 +256,43 @@ void hudson_tpm_decode_spi(void) | ROUTE_TPM_2_SPI); } +/* + * Enable LPC ROM access at 0xFFXX0000 - 0xFFFFFFFF. + * + * Hardware should enable LPC ROM by pin straps. This function does not + * handle the theoretically possible PCI ROM, FWH, or SPI ROM configurations. + * + * The HUDSON power-on default is to map 512K ROM space. + * + */ +void hudson_enable_lpc_rom(void) +{ + u8 reg8; + const pci_devfn_t dev = PCI_DEV(0, 0x14, 3); + + /* Decode variable LPC ROM address ranges 1 and 2. */ + reg8 = pci_s_read_config8(dev, 0x48); + reg8 |= (1 << 3) | (1 << 4); + pci_s_write_config8(dev, 0x48, reg8); + + /* LPC ROM address range 1: */ + /* Enable LPC ROM range mirroring start at 0x000e(0000). */ + pci_s_write_config16(dev, 0x68, 0x000e); + /* Enable LPC ROM range mirroring end at 0x000f(ffff). */ + pci_s_write_config16(dev, 0x6a, 0x000f); + + /* LPC ROM address range 2: */ + /* + * Enable LPC ROM range start at: + * 0xfff8(0000): 512KB + * 0xfff0(0000): 1MB + * 0xffe0(0000): 2MB + * 0xffc0(0000): 4MB + * ... + */ + pci_s_write_config16(dev, 0x6c, 0x10000 - (CONFIG_COREBOOT_ROMSIZE_KB >> 6)); + /* Enable LPC ROM range end at 0xffff(ffff). */ + pci_s_write_config16(dev, 0x6e, 0xffff); +} + #endif diff --git a/src/southbridge/amd/pi/hudson/hudson.c b/src/southbridge/amd/pi/hudson/hudson.c index 26fb2588790..9d034d9bcdb 100644 --- a/src/southbridge/amd/pi/hudson/hudson.c +++ b/src/southbridge/amd/pi/hudson/hudson.c @@ -16,13 +16,6 @@ #include "smi.h" #include "fchec.h" -int acpi_get_sleep_type(void) -{ - u16 tmp = inw(ACPI_PM1_CNT_BLK); - tmp = ((tmp & (7 << 10)) >> 10); - return (int)tmp; -} - void hudson_enable(struct device *dev) { printk(BIOS_DEBUG, "%s()\n", __func__); diff --git a/src/southbridge/amd/pi/hudson/hudson.h b/src/southbridge/amd/pi/hudson/hudson.h index 96a5367a448..d742dd34bb5 100644 --- a/src/southbridge/amd/pi/hudson/hudson.h +++ b/src/southbridge/amd/pi/hudson/hudson.h @@ -167,6 +167,7 @@ void hudson_set_readspeed(u16 norm, u16 fast); void lpc_wideio_512_window(uint16_t base); void lpc_wideio_16_window(uint16_t base); void hudson_tpm_decode_spi(void); +void hudson_enable_lpc_rom(void); void hudson_enable(struct device *dev); void s3_resume_init_data(void *FchParams); diff --git a/src/southbridge/amd/pi/hudson/include/soc/acpi.h b/src/southbridge/amd/pi/hudson/include/soc/acpi.h new file mode 100644 index 00000000000..80fcc9921ec --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/acpi.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_ACPI_H +#define SOC_ACPI_H + +#endif /* SOC_ACPI_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/iomap.h b/src/southbridge/amd/pi/hudson/include/soc/iomap.h new file mode 100644 index 00000000000..df40f0fe714 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/iomap.h @@ -0,0 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_IOMAP_H +#define SOC_IOMAP_H + +#endif /* SOC_IOMAP_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/lpc.h b/src/southbridge/amd/pi/hudson/include/soc/lpc.h new file mode 100644 index 00000000000..0c966e93838 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/lpc.h @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_LPC_H +#define SOC_LPC_H + +#define SPIROM_BASE_ADDRESS_REGISTER 0xa0 +#define SPI_BASE_ALIGNMENT BIT(6) +#define SPI_BASE_RESERVED (BIT(0) | BIT(2) | BIT(4) | BIT(5)) +#define ROUTE_TPM_2_SPI BIT(3) +#define SPI_ROM_ENABLE BIT(1) +#define SPI_PRESERVE_BITS (BIT(1) | BIT(3)) + +#endif /* SOC_LPC_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/nvs.h b/src/southbridge/amd/pi/hudson/include/soc/nvs.h new file mode 100644 index 00000000000..c4db17e8db7 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/nvs.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_NVS_H +#define SOC_NVS_H + +struct __packed global_nvs { + // TODO + uint8_t rsv0; + uint8_t rsv1; + uint8_t rsv2; + uint32_t rsv3; + uint64_t pm1i; /* 0x07 - 0x0e - System Wake Source - PM1 Index */ + uint64_t gpei; /* 0x0f - 0x16 - GPE Wake Source */ + uint8_t rsv4; + uint8_t rsv5; + uint8_t rsv6; +}; + +#endif /* SOC_NVS_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/pci_devs.h b/src/southbridge/amd/pi/hudson/include/soc/pci_devs.h new file mode 100644 index 00000000000..747ccfc0884 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/pci_devs.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_PCI_DEVS_H +#define SOC_PCI_DEVS_H + +#include + +#if !defined(__SIMPLE_DEVICE__) +#include +#define _SOC_DEV(slot, func) pcidev_on_root(slot, func) +#else +#define _SOC_DEV(slot, func) PCI_DEV(0, slot, func) +#endif + +/* LPC BUS */ +#define PCU_DEV 0x14 +#define LPC_FUNC 3 +#define LPC_DEVFN PCI_DEVFN(PCU_DEV, LPC_FUNC) +#define SOC_LPC_DEV _SOC_DEV(PCU_DEV, LPC_FUNC) + +#endif /* SOC_PCI_DEVS_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/smi.h b/src/southbridge/amd/pi/hudson/include/soc/smi.h index da5ddbc2f73..0ee3721c0f4 100644 --- a/src/southbridge/amd/pi/hudson/include/soc/smi.h +++ b/src/southbridge/amd/pi/hudson/include/soc/smi.h @@ -3,9 +3,43 @@ #ifndef SOC_SMI_H #define SOC_SMI_H +/* TODO: include Fch.h and use macros from there? */ + +#define SCI_GPES 32 +#define SCIMAPS 64 +#define SMI_GEVENTS 24 +#define NUMBER_SMITYPES 160 + +#define SMITYPE_SMI_CMD_PORT 0x4b + +#define SMI_EVENT_STATUS 0x00 #define SMI_SCI_TRIG 0x08 #define SMI_SCI_LEVEL 0x0c #define SMI_SCI_STATUS 0x10 #define SMI_SCI_EN 0x14 +#define SMI_SCI_MAP0 0x40 +#define SMI_SCI_MAP(X) (SMI_SCI_MAP0 + (X)) + +#define SMI_REG_SMISTS0 0x80 +#define GEVENT_MASK 0x00ffffff +#define SMI_REG_SMISTS1 0x84 +#define SMI_REG_SMISTS2 0x88 +#define SMI_REG_SMISTS3 0x8c +#define SMI_REG_SMISTS4 0x90 + +#define SMI_REG_POINTER 0x94 +#define SMI_STATUS_SRC_SCI (1 << 0) +#define SMI_STATUS_SRC_0 (1 << 1) +#define SMI_STATUS_SRC_1 (1 << 2) +#define SMI_STATUS_SRC_2 (1 << 3) +#define SMI_STATUS_SRC_3 (1 << 4) +#define SMI_STATUS_SRC_4 (1 << 5) + +#define SMI_REG_SMITRIG0 0x98 +#define SMITRG0_SMIENB (1 << 31) +#define SMITRG0_EOS (1 << 28) + +#define SMI_REG_CONTROL0 0xa0 + #endif /* SOC_SMI_H */ diff --git a/src/southbridge/amd/pi/hudson/include/soc/southbridge.h b/src/southbridge/amd/pi/hudson/include/soc/southbridge.h new file mode 100644 index 00000000000..bea21c50e38 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/include/soc/southbridge.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_SOUTHBRIDGE_H +#define SOC_SOUTHBRIDGE_H + +#define PM1_LIMIT 16 +#define GPE0_LIMIT 32 +#define TOTAL_BITS(a) (8 * sizeof(a)) + +#define PM_ACPI_SMI_CMD 0x6a + +#define PWRBTN_STS (1 << 8) +#define RTC_STS (1 << 10) +#define PCIEXPWAK_STS (1 << 14) +#define WAK_STS (1 << 15) + +#endif /* SOC_SOUTHBRIDGE_H */ diff --git a/src/southbridge/amd/pi/hudson/lpc.c b/src/southbridge/amd/pi/hudson/lpc.c index 66ec82414fe..1cce7428736 100644 --- a/src/southbridge/amd/pi/hudson/lpc.c +++ b/src/southbridge/amd/pi/hudson/lpc.c @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include #include #include #include @@ -314,6 +316,18 @@ static void hudson_lpc_enable_resources(struct device *dev) hudson_lpc_enable_childrens_resources(dev); } +uintptr_t lpc_get_spibase(void) +{ + struct device *dev = pcidev_on_root(0x14, 3); + + u32 base = pci_read_config32(dev, SPIROM_BASE_ADDRESS_REGISTER) & 0xffffffc0; + if (!base) { + base = SPI_BASE_ADDRESS; + pci_write_config32(dev, SPIROM_BASE_ADDRESS_REGISTER, base | SPI_ROM_ENABLE); + } + return (uintptr_t)base; +} + static const char *lpc_acpi_name(const struct device *dev) { if (dev->path.type != DEVICE_PATH_PCI) @@ -328,10 +342,12 @@ static const char *lpc_acpi_name(const struct device *dev) static void lpc_final(struct device *dev) { if (!acpi_is_wakeup_s3()) { + acpi_clear_pm_gpe_status(); + if (CONFIG(HAVE_SMI_HANDLER)) - outl(0x0, ACPI_PM1_CNT_BLK); /* clear SCI_EN */ + acpi_disable_sci(); else - outl(0x1, ACPI_PM1_CNT_BLK); /* set SCI_EN */ + acpi_enable_sci(); } } diff --git a/src/southbridge/amd/pi/hudson/lpc_simpledev.c b/src/southbridge/amd/pi/hudson/lpc_simpledev.c new file mode 100644 index 00000000000..bee7ed66740 --- /dev/null +++ b/src/southbridge/amd/pi/hudson/lpc_simpledev.c @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +#include "hudson.h" +#include "pci_devs.h" + +uintptr_t lpc_get_spibase(void) +{ + u32 base; + + base = pci_read_config32(PCI_DEV(0, LPC_DEV, LPC_FUNC), + SPIROM_BASE_ADDRESS_REGISTER); + base &= 0xffffffc0; + return (uintptr_t)base; +} diff --git a/src/southbridge/amd/pi/hudson/smi.c b/src/southbridge/amd/pi/hudson/smi.c index 560b66679b5..193e64d2c84 100644 --- a/src/southbridge/amd/pi/hudson/smi.c +++ b/src/southbridge/amd/pi/hudson/smi.c @@ -4,16 +4,11 @@ * Utilities for SMM setup */ -#include +#include #include -#include "smi.h" - -/** Set the EOS bit and enable SMI generation from southbridge */ -void global_smi_enable(void) +void smm_region(uintptr_t *start, size_t *size) { - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg &= ~SMITRG0_SMIENB; /* Enable SMI generation */ - reg |= SMITRG0_EOS; /* Set EOS bit */ - smi_write32(SMI_REG_SMITRIG0, reg); + *start = (uintptr_t)cbmem_top(); + *size = CONFIG_SMM_TSEG_SIZE; } diff --git a/src/southbridge/amd/pi/hudson/smi_util.c b/src/southbridge/amd/pi/hudson/smi_util.c index 70b35850d6e..3dc2d8a31e5 100644 --- a/src/southbridge/amd/pi/hudson/smi_util.c +++ b/src/southbridge/amd/pi/hudson/smi_util.c @@ -6,9 +6,7 @@ #include #include -#include -#include "hudson.h" #include "smi.h" #define HUDSON_SMI_ACPI_COMMAND 75 @@ -79,8 +77,3 @@ void hudson_enable_acpi_cmd_smi(void) { configure_smi(HUDSON_SMI_ACPI_COMMAND, SMI_MODE_SMI); } - -uint16_t pm_acpi_smi_cmd_port(void) -{ - return pm_read16(PM_ACPI_SMI_CMD); -} diff --git a/src/southbridge/amd/pi/hudson/smihandler.c b/src/southbridge/amd/pi/hudson/smihandler.c index 8b88c06de3f..8aa77135d4c 100644 --- a/src/southbridge/amd/pi/hudson/smihandler.c +++ b/src/southbridge/amd/pi/hudson/smihandler.c @@ -4,125 +4,44 @@ * SMI handler for Hudson southbridges */ -#include +#include +#include +#include +#include #include #include -#include "hudson.h" -#include "smi.h" - -#define SMI_0x88_ACPI_COMMAND (1 << 11) - -enum smi_source { - SMI_SOURCE_SCI = (1 << 0), - SMI_SOURCE_GPE = (1 << 1), - SMI_SOURCE_0x84 = (1 << 2), - SMI_SOURCE_0x88 = (1 << 3), - SMI_SOURCE_IRQ_TRAP = (1 << 4), - SMI_SOURCE_0x90 = (1 << 5) -}; - -static void hudson_apmc_smi_handler(void) +static void fch_apmc_smi_handler_no_psp(void) { - u32 reg32; - const uint8_t cmd = apm_get_apmc(); + const uint8_t cmd = inb(pm_acpi_smi_cmd_port()); switch (cmd) { case APM_CNT_ACPI_ENABLE: - reg32 = inl(ACPI_PM1_CNT_BLK); - reg32 |= (1 << 0); /* SCI_EN */ - outl(reg32, ACPI_PM1_CNT_BLK); + acpi_clear_pm_gpe_status(); + acpi_enable_sci(); break; case APM_CNT_ACPI_DISABLE: - reg32 = inl(ACPI_PM1_CNT_BLK); - reg32 &= ~(1 << 0); /* clear SCI_EN */ - outl(ACPI_PM1_CNT_BLK, reg32); + acpi_disable_sci(); + break; + case APM_CNT_SMMSTORE: + if (CONFIG(SMMSTORE)) + handle_smi_store(); break; } mainboard_smi_apmc(cmd); } -static void process_smi_sci(void) -{ - const uint32_t status = smi_read32(0x10); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x10, status); -} - -static void process_gpe_smi(void) -{ - const uint32_t status = smi_read32(0x80); - const uint32_t gevent_mask = (1 << 24) - 1; - - /* Only Bits [23:0] indicate GEVENT SMIs. */ - if (status & gevent_mask) { - /* A GEVENT SMI occurred */ - mainboard_smi_gpi(status & gevent_mask); - } - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x80, status); -} - -static void process_smi_0x84(void) -{ - const uint32_t status = smi_read32(0x84); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x84, status); -} - -static void process_smi_0x88(void) -{ - const uint32_t status = smi_read32(0x88); - - if (status & SMI_0x88_ACPI_COMMAND) { - /* Command received via ACPI SMI command port */ - hudson_apmc_smi_handler(); - } - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x88, status); -} - -static void process_smi_0x8c(void) -{ - const uint32_t status = smi_read32(0x8c); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x8c, status); -} - -static void process_smi_0x90(void) -{ - const uint32_t status = smi_read32(0x90); - - /* Clear events to prevent re-entering SMI if event isn't handled */ - smi_write32(0x90, status); -} +static const struct smi_sources_t smi_sources[] = { + { .type = SMITYPE_SMI_CMD_PORT, .handler = fch_apmc_smi_handler_no_psp }, +}; -void southbridge_smi_handler(void) +void *get_smi_source_handler(int source) { - const uint16_t smi_src = smi_read16(0x94); - - if (smi_src & SMI_SOURCE_SCI) - process_smi_sci(); - if (smi_src & SMI_SOURCE_GPE) - process_gpe_smi(); - if (smi_src & SMI_SOURCE_0x84) - process_smi_0x84(); - if (smi_src & SMI_SOURCE_0x88) - process_smi_0x88(); - if (smi_src & SMI_SOURCE_IRQ_TRAP) - process_smi_0x8c(); - if (smi_src & SMI_SOURCE_0x90) - process_smi_0x90(); -} + size_t i; -void southbridge_smi_set_eos(void) -{ - uint32_t reg = smi_read32(SMI_REG_SMITRIG0); - reg |= SMITRG0_EOS; - smi_write32(SMI_REG_SMITRIG0, reg); + for (i = 0 ; i < ARRAY_SIZE(smi_sources) ; i++) + if (smi_sources[i].type == source) + return smi_sources[i].handler; + return NULL; } diff --git a/src/southbridge/intel/bd82x6x/acpi/pch.asl b/src/southbridge/intel/bd82x6x/acpi/pch.asl index 5ecbbd5dbf5..63e8b94b5d7 100644 --- a/src/southbridge/intel/bd82x6x/acpi/pch.asl +++ b/src/southbridge/intel/bd82x6x/acpi/pch.asl @@ -259,3 +259,125 @@ Method (_OSC, 4) Return (Arg3) } + +Scope (_GPE) +{ + Method (_L09, 0, NotSerialized) + { + If ((RP1D == Zero)) + { + \_SB.PCI0.RP01.HPME () + Notify (\_SB.PCI0.RP01, 0x02) + } + + If ((RP2D == Zero)) + { + \_SB.PCI0.RP02.HPME () + Notify (\_SB.PCI0.RP02, 0x02) + } + + If ((RP3D == Zero)) + { + \_SB.PCI0.RP03.HPME () + Notify (\_SB.PCI0.RP03, 0x02) + } + + If ((RP4D == Zero)) + { + \_SB.PCI0.RP04.HPME () + Notify (\_SB.PCI0.RP04, 0x02) + } + + If ((RP5D == Zero)) + { + \_SB.PCI0.RP05.HPME () + Notify (\_SB.PCI0.RP05, 0x02) + } + + If ((RP6D == Zero)) + { + \_SB.PCI0.RP06.HPME () + Notify (\_SB.PCI0.RP06, 0x02) + } + + If ((RP7D == Zero)) + { + \_SB.PCI0.RP07.HPME () + Notify (\_SB.PCI0.RP07, 0x02) + } + + If ((RP8D == Zero)) + { + \_SB.PCI0.RP08.HPME () + Notify (\_SB.PCI0.RP08, 0x02) + } + + Notify (\_SB.PCI0.PEGP, 0x02) + Notify (\_SB.PCI0.PEGP.DEV0, 0x02) + Notify (\_SB.PCI0.PEG1, 0x02) + Notify (\_SB.PCI0.PEG1.DEV0, 0x02) + Notify (\_SB.PCI0.PEG2, 0x02) + Notify (\_SB.PCI0.PEG2.DEV0, 0x02) + Notify (\_SB.PCI0.PEG6, 0x02) + Notify (\_SB.PCI0.PEG6.DEV0, 0x02) + } + + Method (_L01, 0, NotSerialized) + { + If (((RP1D == Zero) && \_SB.PCI0.RP01.HPCS)) + { + If (\_SB.PCI0.RP01.HPEV () == 1) { + Notify (\_SB.PCI0.RP01, 0) + } + } + + If (((RP2D == Zero) && \_SB.PCI0.RP02.HPCS)) + { + If (\_SB.PCI0.RP02.HPEV () == 1) { + Notify (\_SB.PCI0.RP02, 0) + } + } + + If (((RP3D == Zero) && \_SB.PCI0.RP03.HPCS)) + { + If (\_SB.PCI0.RP03.HPEV () == 1) { + Notify (\_SB.PCI0.RP03, 0) + } + } + + If (((RP4D == Zero) && \_SB.PCI0.RP04.HPCS)) + { + If (\_SB.PCI0.RP04.HPEV () == 1) { + Notify (\_SB.PCI0.RP04, 0) + } + } + + If (((RP5D == Zero) && \_SB.PCI0.RP05.HPCS)) + { + If (\_SB.PCI0.RP05.HPEV () == 1) { + Notify (\_SB.PCI0.RP05, 0) + } + } + + If (((RP6D == Zero) && \_SB.PCI0.RP06.HPCS)) + { + If (\_SB.PCI0.RP06.HPEV () == 1) { + Notify (\_SB.PCI0.RP06, 0) + } + } + + If (((RP7D == Zero) && \_SB.PCI0.RP07.HPCS)) + { + If (\_SB.PCI0.RP07.HPEV () == 1) { + Notify (\_SB.PCI0.RP07, 0) + } + } + + If (((RP8D == Zero) && \_SB.PCI0.RP08.HPCS)) + { + If (\_SB.PCI0.RP08.HPEV () == 1) { + Notify (\_SB.PCI0.RP08, 0) + } + } + } +} diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 67d883ad485..fa05a4379ec 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -1,6 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include +#include #include #include #include @@ -159,8 +160,7 @@ static void pch_power_options(struct device *dev) * * If the option is not existent (Laptops), use Kconfig setting. */ - const unsigned int pwr_on = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); + const unsigned int pwr_on = dasharo_get_power_on_after_fail(); reg16 = pci_read_config16(dev, GEN_PMCON_3); reg16 &= 0xfffe; diff --git a/src/southbridge/intel/common/acpi/pcie_port.asl b/src/southbridge/intel/common/acpi/pcie_port.asl index 988c8170e98..d97bc1272b1 100644 --- a/src/southbridge/intel/common/acpi/pcie_port.asl +++ b/src/southbridge/intel/common/acpi/pcie_port.asl @@ -5,13 +5,69 @@ OperationRegion (RPCS, PCI_Config, 0x00, 0xFF) Field (RPCS, AnyAcc, NoLock, Preserve) { + Offset (0x10), + L0SE, 1, Offset (0x4c), // Link Capabilities , 24, RPPN, 8, // Root Port Number Offset (0x5A), , 3, - PDC, 1, + PDCX, 1, + , 2, + PDSX, 1, + Offset (0x60), // RSTS - Root Status Register + , 16, + PSPX, 1, // PME Status + Offset (0xDB), // MPC - Miscellaneous Port Configuration Register + , 6, + HPEX, 1, // Hot Plug SCI Enable + PMEX, 1, // Power Management SCI Enable +} + +Field (RPCS, AnyAcc, NoLock, WriteAsZeros) +{ Offset (0xDF), , 6, - HPCS, 1, + HPCS, 1, // Hot Plug SCI Status + PMCS, 1, // Power Management SCI Status +} + +Method (HPME, 0, Serialized) { + If (PMCS == 1) { + Notify (PXSX, 0x2) + PMCS = 1 // clear rootport's PME SCI status + PSPX = 1 // consume one pending PME notification to prevent it from blocking the queue + } +} + +Method (HPEV, 0, Serialized) { + Sleep (0x64) + If (PDCX == 1) + { + PDCX = 1 + HPCS = 1 + If (PDSX == 0) + { + L0SE = 0 + } + Return (1) + } + Else + { + HPCS = 1 + Return (0) + } +} + +Name (_HPP, Package (0x04) { + 0x08, + 0x40, + 1, + 0 +}) + +Device(PXSX) +{ + Name (_ADR, 0x00000000) + Name (_PRW, Package() { 9, 4 }) } diff --git a/src/southbridge/intel/common/firmware/Kconfig b/src/southbridge/intel/common/firmware/Kconfig index 95eda31c9d2..055202fbf79 100644 --- a/src/southbridge/intel/common/firmware/Kconfig +++ b/src/southbridge/intel/common/firmware/Kconfig @@ -24,6 +24,14 @@ config IFD_BIN_PATH default "3rdparty/blobs/mainboard/\$(MAINBOARDDIR)/descriptor.bin" depends on HAVE_IFD_BIN +config IFDTOOL_DISABLE_ME + bool "Set AltMeDisable/HAP bit with ifdtool" + default n + depends on HAVE_IFD_BIN + help + Uses ifdtool to set AltMeDisable/HAP in Intel Flash Descriptor binary + if added to the build. + config HAVE_ME_BIN bool "Add Intel ME/TXE firmware" depends on HAVE_IFD_BIN @@ -107,6 +115,47 @@ config USE_ME_CLEANER comment "Please test coreboot with the original, unmodified ME firmware before using me_cleaner" depends on USE_ME_CLEANER +config HAVE_INTEL_ME_HAP + bool + default n + help + SoC should select this option if it support disablign ME with HAP bit. + +choice + prompt "Default ME state option value" + default INTEL_ME_ENABLED + help + Provides a default for the power state the system should + go into after G3 (power loss). On many boards this can be + overridden by an NVRAM option. + +config INTEL_ME_DISABLED_HECI + bool "ME disabled (soft)" + help + Choose this option if you want to put ME into soft disabled state via + HECI by default. + +config INTEL_ME_DISABLED_HAP + bool "ME disabled (HAP)" + depends on HAVE_INTEL_ME_HAP + help + Choose this option if you want to put ME into HAP disabled state by + default. + +config INTEL_ME_ENABLED + bool "ME enabled" + help + Choose this option if you want to keep ME enabled by default. + You can always set ME to disabled state via setup option + +endchoice + +config INTEL_ME_DEFAULT_STATE + int + default 2 if INTEL_ME_DISABLED_HAP || IFDTOOL_DISABLE_ME + default 1 if INTEL_ME_DISABLED_HECI + default 0 + config ME_CLEANER_ARGS string depends on USE_ME_CLEANER diff --git a/src/southbridge/intel/common/firmware/Makefile.mk b/src/southbridge/intel/common/firmware/Makefile.mk index 1425d5a352d..c97c61972ba 100644 --- a/src/southbridge/intel/common/firmware/Makefile.mk +++ b/src/southbridge/intel/common/firmware/Makefile.mk @@ -48,6 +48,14 @@ add_intel_firmware: $(obj)/coreboot.pre $(IFDTOOL) printf " DD Adding Intel Firmware Descriptor\n" dd if=$(IFD_BIN_PATH) \ of=$(obj)/coreboot.pre conv=notrunc >/dev/null 2>&1 +ifeq ($(CONFIG_IFDTOOL_DISABLE_ME),y) + printf " IFDTOOL set AltMeDisable/HAP bit\n" + $(objutil)/ifdtool/ifdtool \ + $(IFDTOOL_USE_CHIPSET) \ + --altmedisable 1 \ + -O $(obj)/coreboot.pre \ + $(obj)/coreboot.pre +endif ifeq ($(CONFIG_VALIDATE_INTEL_DESCRIPTOR),y) printf " IFDTOOL validate IFD against FMAP\n" $(objutil)/ifdtool/ifdtool \ diff --git a/src/southbridge/intel/common/smihandler.c b/src/southbridge/intel/common/smihandler.c index 798f2f13876..6a7e13441f3 100644 --- a/src/southbridge/intel/common/smihandler.c +++ b/src/southbridge/intel/common/smihandler.c @@ -6,6 +6,7 @@ #include #include #include +#include #include #include #include @@ -99,8 +100,7 @@ static int power_on_after_fail(void) u8 tmp70, tmp72; tmp70 = inb(0x70); tmp72 = inb(0x72); - const unsigned int s5pwr = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); + const unsigned int s5pwr = dasharo_get_power_on_after_fail(); outb(tmp70, 0x70); outb(tmp72, 0x72); @@ -249,12 +249,30 @@ static void southbridge_smi_gsmi(void) *ret = gsmi_exec(sub_command, param); } +static bool spi_get_wp(void) +{ + return !(pci_read_config8(PCI_DEV(0, 31, 0), 0xdc) & 1); +} + +static void spi_set_wp(bool enable) +{ + uint8_t bios_cntl = pci_read_config8(PCI_DEV(0, 31, 0), 0xdc); + + if (enable) + bios_cntl &= ~1; + else + bios_cntl |= 1; + + pci_write_config8(PCI_DEV(0, 31, 0), 0xdc, bios_cntl); +} + static void southbridge_smi_store(void) { u8 sub_command, ret; em64t101_smm_state_save_area_t *io_smi = smi_apmc_find_state_save(APM_CNT_SMMSTORE); uintptr_t reg_rbx; + bool wp_enabled; if (!io_smi) return; @@ -264,9 +282,16 @@ static void southbridge_smi_store(void) /* Parameter buffer in EBX */ reg_rbx = (uintptr_t)io_smi->rbx; + wp_enabled = spi_get_wp(); + + spi_set_wp(false); + /* drivers/smmstore/smi.c */ ret = smmstore_exec(sub_command, (void *)reg_rbx); io_smi->rax = ret; + + if (wp_enabled) + spi_set_wp(true); } static int mainboard_finalized = 0; @@ -375,7 +400,7 @@ static void southbridge_smi_tco(void) bios_cntl = pci_read_config8(PCI_DEV(0, 0x1f, 0), 0xdc); - if (bios_cntl & 1) { + if (CONFIG(BOOTMEDIA_SMM_BWP) && is_smm_bwp_permitted() && (bios_cntl & 1)) { /* BWE is RW, so the SMI was caused by a * write to BWE, not by a write to the BIOS */ diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 068062bae0e..66b1eca02ab 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -1102,7 +1103,7 @@ void spi_finalize_ops(void) } writew_(optype, cntlr.optype); - spi_set_smm_only_flashing(CONFIG(BOOTMEDIA_SMM_BWP)); + spi_set_smm_only_flashing(is_smm_bwp_permitted()); } __weak void intel_southbridge_override_spi(struct intel_swseq_spi_config *spi_config) diff --git a/src/superio/ite/it8613e/acpi/superio.asl b/src/superio/ite/it8613e/acpi/superio.asl new file mode 100644 index 00000000000..67d4931e23a --- /dev/null +++ b/src/superio/ite/it8613e/acpi/superio.asl @@ -0,0 +1,118 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* + * Include this file into a mainboard's DSDT _SB device tree and it will + * expose the IT8613E SuperIO and some of its functionality. + * + * It allows the change of IO ports, IRQs and DMA settings on logical + * devices, disabling and reenabling logical devices. + * + * LDN State + * 0x1 UARTA Implemented, untested + * 0x4 EC Not implemented + * 0x5 KBC Implemented, untested + * 0x6 MOUSE Implemented, untested + * 0x7 GPIO Not implemented + * 0xa CIR Not implemented + * + + * Controllable through preprocessor defines: + * SUPERIO_DEV Device identifier for this SIO (e.g. SIO0) + * SUPERIO_PNP_BASE I/O address of the first PnP configuration register + * IT8613E_SHOW_UARTA If defined, UARTA will be exposed. + * IT8613E_SHOW_KBC If defined, the KBC will be exposed. + * IT8613E_SHOW_PS2M If defined, PS/2 mouse support will be exposed. + */ + +#undef SUPERIO_CHIP_NAME +#define SUPERIO_CHIP_NAME IT8613E +#include + +#undef PNP_DEFAULT_PSC +#define PNP_DEFAULT_PSC Return (0) /* no power management */ + +#define CONFIGURE_CONTROL CCTL + +Device (SUPERIO_DEV) { + Name (_HID, EisaId("PNP0A05")) + Name (_STR, Unicode("ITE IT8613E Super I/O")) + Name (_UID, SUPERIO_UID(SUPERIO_DEV,)) + + /* Mutex for accesses to the configuration ports */ + Mutex (CRMX, 1) + + /* SuperIO configuration ports */ + OperationRegion (CREG, SystemIO, SUPERIO_PNP_BASE, 0x02) + Field (CREG, ByteAcc, NoLock, Preserve) + { + PNP_ADDR_REG, 8, + PNP_DATA_REG, 8 + } + IndexField (PNP_ADDR_REG, PNP_DATA_REG, ByteAcc, NoLock, Preserve) + { + Offset (0x02), + CONFIGURE_CONTROL, 8, /* Global configure control */ + + Offset (0x07), + PNP_LOGICAL_DEVICE, 8, /* Logical device selector */ + + Offset (0x30), + PNP_DEVICE_ACTIVE, 1, /* Logical device activation */ + + Offset (0x60), + PNP_IO0_HIGH_BYTE, 8, /* First I/O port base - high byte */ + PNP_IO0_LOW_BYTE, 8, /* First I/O port base - low byte */ + Offset (0x62), + PNP_IO1_HIGH_BYTE, 8, /* Second I/O port base - high byte */ + PNP_IO1_LOW_BYTE, 8, /* Second I/O port base - low byte */ + + Offset (0x70), + PNP_IRQ0, 8, /* First IRQ */ + } + + Method (_CRS) + { + /* Announce the used i/o ports to the OS */ + Return (ResourceTemplate () { + IO (Decode16, SUPERIO_PNP_BASE, SUPERIO_PNP_BASE, 0x01, 0x02) + }) + } + + #undef PNP_ENTER_MAGIC_1ST + #undef PNP_ENTER_MAGIC_2ND + #undef PNP_ENTER_MAGIC_3RD + #undef PNP_ENTER_MAGIC_4TH + #undef PNP_EXIT_MAGIC_1ST + #define PNP_ENTER_MAGIC_1ST 0x87 + #define PNP_ENTER_MAGIC_2ND 0x01 + #define PNP_ENTER_MAGIC_3RD 0x55 +#if SUPERIO_PNP_BASE == 0x2e + #define PNP_ENTER_MAGIC_4TH 0x55 +#else + #define PNP_ENTER_MAGIC_4TH 0xaa +#endif + #define PNP_EXIT_SPECIAL_REG CONFIGURE_CONTROL + #define PNP_EXIT_SPECIAL_VAL 0x02 + #include + +#ifdef IT8613E_SHOW_UARTA + #undef SUPERIO_UART_LDN + #undef SUPERIO_UART_DDN + #undef SUPERIO_UART_PM_REG + #undef SUPERIO_UART_PM_VAL + #undef SUPERIO_UART_PM_LDN + #define SUPERIO_UART_LDN 1 + #include +#endif + +#ifdef IT8613E_SHOW_KBC + #undef SUPERIO_KBC_LDN + #undef SUPERIO_KBC_PS2M + #undef SUPERIO_KBC_PS2LDN + #define SUPERIO_KBC_LDN 5 +#ifdef IT8613E_SHOW_PS2M + #define SUPERIO_KBC_PS2LDN 6 +#endif + #include +#endif +} diff --git a/src/superio/nuvoton/nct6687d/Makefile.mk b/src/superio/nuvoton/nct6687d/Makefile.mk index d4785f726e6..899cf5daec1 100644 --- a/src/superio/nuvoton/nct6687d/Makefile.mk +++ b/src/superio/nuvoton/nct6687d/Makefile.mk @@ -1,3 +1,8 @@ # SPDX-License-Identifier: GPL-2.0-or-later +bootblock-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c +romstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_ec.c + +ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += nct6687d_hwm.c ramstage-$(CONFIG_SUPERIO_NUVOTON_NCT6687D) += superio.c diff --git a/src/superio/nuvoton/nct6687d/chip.h b/src/superio/nuvoton/nct6687d/chip.h new file mode 100644 index 00000000000..edd0deb23a3 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/chip.h @@ -0,0 +1,361 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT6687D_CHIP_H +#define SUPERIO_NUVOTON_NCT6687D_CHIP_H + +#include + +#define MAX_TEMP_SPEED_LEVELS 7 +#define MAX_TEMP_SRC 4 +#define MAX_NUM_FANS 10 +#define MAX_NUM_SENSORS 32 +#define MAX_WEIGHT_POINTS 8 +#define MAX_DTS_CTL_POINTS 5 + +enum nct6687d_sensor_src_select { + /* TIN sources */ + SENSOR_DISABLE = 0x00, + SENSOR_LOCAL = 0x01, + TD0P_CURRENT_MODE = 0x02, + TD1P_CURRENT_MODE = 0x03, + TD2P_CURRENT_MODE = 0x04, + TD0P_VOLTAGE_MODE = 0x05, + TD1P_VOLTAGE_MODE = 0x06, + TD2P_VOLTAGE_MODE = 0x07, + THERMISTOR14 = 0x08, + THERMISTOR15 = 0x09, + THERMISTOR16 = 0x0A, + THERMISTOR0 = 0x0B, + THERMISTOR1 = 0x0C, + THERMISTOR2 = 0x0D, + THERMISTOR3 = 0x0E, + THERMISTOR4 = 0x0F, + THERMISTOR5 = 0x10, + THERMISTOR6 = 0x11, + THERMISTOR7 = 0x12, + THERMISTOR8 = 0x13, + THERMISTOR9 = 0x14, + THERMISTOR10 = 0x15, + THERMISTOR11 = 0x16, + THERMISTOR12 = 0x17, + THERMISTOR13 = 0x18, + PECI_AGENT0_DOMAIN0 = 0x20, + PECI_AGENT1_DOMAIN0 = 0x21, + PECI_AGENT2_DOMAIN0 = 0x22, + PECI_AGENT3_DOMAIN0 = 0x23, + PECI_AGENT0_DOMAIN1 = 0x24, + PECI_AGENT1_DOMAIN1 = 0x25, + PECI_AGENT2_DOMAIN1 = 0x26, + PECI_AGENT3_DOMAIN1 = 0x27, + PECI_DIMM_TMP0 = 0x28, + PECI_DIMM_TMP1 = 0x29, + PECI_DIMM_TMP2 = 0x2A, + PECI_DIMM_TMP3 = 0x2B, + PCH_CPU = 0x30, + PCH_CHIP = 0x31, + PCH_CHIP_CPU_MAX = 0x32, + PCH_MCH = 0x33, + PCH_DIMM0 = 0x34, + PCH_DIMM1 = 0x35, + PCH_DIMM2 = 0x36, + PCH_DIMM3 = 0x37, + SMBUS_THERMAL_SENSOR0 = 0x38, + SMBUS_THERMAL_SENSOR1 = 0x39, + SMBUS_THERMAL_SENSOR2 = 0x3A, + SMBUS_THERMAL_SENSOR3 = 0x3B, + SMBUS_THERMAL_SENSOR4 = 0x3C, + SMBUS_THERMAL_SENSOR5 = 0x3D, + DIMM_THERMAL_SENSOR0 = 0x3E, + DIMM_THERMAL_SENSOR1 = 0x3F, + DIMM_THERMAL_SENSOR2 = 0x40, + DIMM_THERMAL_SENSOR3 = 0x41, + AMD_TSI_ADDRESS_0x90 = 0x42, + AMD_TSI_ADDRESS_0x92 = 0x43, + AMD_TSI_ADDRESS_0x94 = 0x44, + AMD_TSI_ADDRESS_0x96 = 0x45, + AMD_TSI_ADDRESS_0x98 = 0x46, + AMD_TSI_ADDRESS_0x9A = 0x47, + AMD_TSI_ADDRESS_0x9C = 0x48, + AMD_TSI_ADDRESS_0x9D = 0x49, + VIRTUAL_TEMPIN0 = 0x50, + VIRTUAL_TEMPIN1 = 0x51, + VIRTUAL_TEMPIN2 = 0x52, + VIRTUAL_TEMPIN3 = 0x53, + VIRTUAL_TEMPIN4 = 0x54, + VIRTUAL_TEMPIN5 = 0x55, + VIRTUAL_TEMPIN6 = 0x56, + VIRTUAL_TEMPIN7= 0x57, + /* VIN soruces */ + VCC= 0x60, + VSB= 0x61, + AVSB = 0x62, + VTT = 0x63, + VBAT = 0x64, + VREF = 0x65, + VIN0 = 0x66, + VIN1 = 0x67, + VIN2 = 0x68, + VIN3 = 0x69, + VIN4 = 0x6A, + VIN5 = 0x6B, + VIN6 = 0x6C, + VIN7 = 0x6D, + VIN8 = 0x6E, + VIN9 = 0x6F, + VIN10 = 0x70, + VIN11 = 0x71, + VIN12 = 0x72, + VIN13 = 0x73, + VIN14 = 0x74, + VIN15 = 0x75, + VIN16 = 0x76, +}; + +enum nct6687d_peci_speed { + PECI_2MHZ = 0, + PECI_1200KHZ, + PECI_800KHZ, + PECI_400KHZ, +}; + +enum nct6687d_baud_rate { + BAUD_12_5K = 0, + BAUD_25K, + BAUD_50K, + BAUD_100K, + BAUD_200K, + BAUD_400K, + BAUD_800K, + BAUD_1200K, +}; + +enum nct6687d_fan_mode { + FAN_IGNORE = 0, + FAN_THERMAL_CRUISE, + FAN_SPEED_CRUISE, + FAN_SMART_FAN_IV, + FAN_PID_CONTROL, + FAN_MODE_MANUAL, +}; + +enum nct6687d_tach_pwm_sel { + TACH_PWM0 = 0, + TACH_PWM1, + TACH_PWM2, + TACH_PWM3, + TACH_PWM4, + TACH_PWM5, + TACH_PWM6, + TACH_PWM7, + TACH_PWM8, + TACH_PWM9, + TACH_PWM10, + TACH_PWM11, + TACH_PWM12, + TACH_PWM13, + TACH_PWM14, + TACH_PWM15, + TACH_PWM16, + TACH_PWM17, + TACH_PWM18, + TACH_PWM19, + TACH_PWM20, + TACH_PWM21, + TACH_PWM22, + TACH_PWM23, +}; + +enum nct6687d_fan_unit_sel { + FAN_PWM = 0, + FAN_RPM, +}; + +enum nct6687d_fast_track_weight { + WEIGHT_DIV_1 = 0, + WEIGHT_DIV_2, + WEIGHT_DIV_4, + WEIGHT_DIV_8, + WEIGHT_DIV_16, + WEIGHT_DIV_32, + WEIGHT_DIV_64, +}; + +struct nct6687d_pch_smbus_sensor { + bool sensor_en; + uint8_t sensor_idx; + bool report_one_byte; + uint8_t port_sel; + enum nct6687d_baud_rate baud_rate; + uint8_t sensor_addr; + uint8_t sensor_cmd; +}; + +struct nct6687d_dts_sensor_config { + uint8_t ambient_temp[MAX_DTS_CTL_POINTS]; + uint16_t rpm_start_point[MAX_DTS_CTL_POINTS]; + uint16_t rpm_end_point[MAX_DTS_CTL_POINTS]; + uint8_t temp_start; + uint8_t temp_end; + uint16_t max_speed; + bool peci_adjust; + uint8_t peci_agent_idx; +}; + +struct nct6687d_dts2_sensor_config { + int8_t target_margin; + uint8_t target_margin_tolerance; + int8_t t_control; + int8_t t_control_offset; + uint16_t step_speed; + uint16_t min_speed; + /* Unit is 1s */ + uint8_t delay_time; + uint8_t divisor; +}; + +struct nct6687d_smart_fan_iv_config { + uint8_t temp_src[MAX_TEMP_SRC]; + uint8_t temp_levels[MAX_TEMP_SPEED_LEVELS]; + uint16_t speed_levels[MAX_TEMP_SPEED_LEVELS]; + uint8_t temp_hystheresis; + uint8_t temp_cut_off; + uint8_t cut_off_delay; + /* Time in 100ms units */ + uint8_t step_up_time; + uint8_t step_down_time; +}; + +struct nct6687d_manual_fan_config { + uint8_t manual_duty; +}; + +struct nct6687d_fan_thermal_cruise_config { + bool keep_min_fan_output; + uint8_t target_temp; + uint8_t temp_tolerance; + uint8_t initial_value; + uint8_t stop_value; + /* Time in 100ms units */ + uint8_t stop_time; + uint8_t step_up_time; + uint8_t step_down_time; +}; + +struct nct6687d_fan_speed_cruise_config { + uint16_t target_rpm; + uint16_t rpm_tolerance; + /* Time in 100ms units */ + uint8_t step_up_time; + uint8_t step_down_time; +}; + +struct nct6687d_ambient_floor_fan_config { + /* Units is RPM */ + uint16_t minout_start; + uint16_t minout_end; + uint16_t minout_max; +}; + +struct nct6687d_ambient_floor_config { + uint8_t temp_start; + uint8_t temp_end; +}; + +struct nct6687d_smart_tracking_config { + uint8_t rpm_tolerance_low; + uint8_t rpm_tolerance_mid; + uint8_t rpm_tolerance_high; + + uint16_t speed_boundary_low; + uint16_t speed_boundary_high; + + /* Step tracking setting */ + uint8_t step_up; + uint8_t step_down; + + /* Fast tracking settings */ + uint8_t temp_boundary; + + enum nct6687d_fast_track_weight weight_up_low; + enum nct6687d_fast_track_weight weight_up_mid; + enum nct6687d_fast_track_weight weight_up_high; + enum nct6687d_fast_track_weight weight_down_low; + enum nct6687d_fast_track_weight weight_down_mid; + enum nct6687d_fast_track_weight weight_down_high; + + uint8_t duty_step_low; + uint8_t duty_step_mid; + uint8_t duty_step_high; + + /* Markup tracking setting */ + uint8_t ambient_temp_boundary; + uint8_t weight_val; +}; + + +struct nct6687d_fan_config { + enum nct6687d_fan_mode mode; + enum nct6687d_fan_unit_sel unit_sel; + enum nct6687d_tach_pwm_sel fanin_sel; + enum nct6687d_tach_pwm_sel fanout_sel; + + struct nct6687d_smart_fan_iv_config smart_fan; + struct nct6687d_manual_fan_config manual_fan; + struct nct6687d_fan_thermal_cruise_config thermal_cruise_fan; + struct nct6687d_fan_speed_cruise_config speed_cruise_fan; + + /* Fan ALG_FUNCTRL */ + uint8_t fan_alg_weight; + + uint8_t crit_temp; + uint8_t crit_temp_tolerance; + + uint8_t temp_err_duty; + + bool dts1_en; + bool dts2_en; + bool dts_ub_en; + + /* Fan FUN_CTRL */ + bool smart_tracking_en; + bool fast_tracking_en; + bool markup_tracking_en; + + bool ambient_floor_en; + struct nct6687d_ambient_floor_fan_config amb_floor_fan_cfg; + + uint8_t startup_duty; + uint8_t manual_offset; + uint8_t min_duty; +}; + +struct superio_nuvoton_nct6687d_config { + struct nct6687d_fan_config fans[MAX_NUM_FANS]; + enum nct6687d_sensor_src_select sensors[MAX_NUM_SENSORS]; + + enum nct6687d_peci_speed peci_speed; + + struct nct6687d_pch_smbus_sensor smbus_sensor; + struct nct6687d_dts_sensor_config dts_sensor; + struct nct6687d_dts2_sensor_config dts2_sensor; + + struct nct6687d_ambient_floor_config ambient_floor; + struct nct6687d_smart_tracking_config smart_tracking; + + uint8_t fan_default_val; +}; + +#define FAN1 fans[0] +#define FAN2 fans[1] +#define FAN3 fans[2] +#define FAN4 fans[3] +#define FAN5 fans[4] +#define FAN6 fans[5] +#define FAN7 fans[6] +#define FAN8 fans[7] +#define FAN9 fans[8] +#define FAN10 fans[9] + +void nct6687d_hwm_init(uint16_t hwm_base, const struct superio_nuvoton_nct6687d_config *conf); + +#endif /* SUPERIO_NUVOTON_NCT6687D_CHIP_H */ diff --git a/src/superio/nuvoton/nct6687d/nct6687d_ec.c b/src/superio/nuvoton/nct6687d/nct6687d_ec.c new file mode 100644 index 00000000000..0b25b164b46 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/nct6687d_ec.c @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +#include "nct6687d_ec.h" + +void nct6687d_ec_write_page(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value) +{ + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + outb(index, iobase + EC_PORT0_INDEX); + outb(value, iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); +} + +void nct6687d_ec_write_page_ff(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value) +{ + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + /* Extra 0xff to the index register */ + outb(0xff, iobase + EC_PORT0_INDEX); + outb(index, iobase + EC_PORT0_INDEX); + outb(value, iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); +} + +void nct6687d_ec_and_or_page(uint16_t iobase, uint8_t page, uint8_t index, + uint8_t and_mask, uint8_t or_mask) +{ + uint8_t val; + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + outb(index, iobase + EC_PORT0_INDEX); + val = inb(iobase + EC_PORT0_DATA); + val &= and_mask; + val |= or_mask; + outb(val, iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); +} + +void nct6687d_ec_and_or_page_ff(uint16_t iobase, uint8_t page, uint8_t index, + uint8_t and_mask, uint8_t or_mask) +{ + uint8_t val; + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + /* Extra 0xff to the index register */ + outb(0xff, iobase + EC_PORT0_INDEX); + outb(index, iobase + EC_PORT0_INDEX); + val = inb(iobase + EC_PORT0_DATA); + val &= and_mask; + val |= or_mask; + outb(val, iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); +} + +uint8_t nct6687d_ec_read_page(uint16_t iobase, uint8_t page, uint8_t index) +{ + uint8_t value; + /* Need to write 0xff first to set the page */ + outb(0xff, iobase + EC_PORT0_PAGE); + outb(page, iobase + EC_PORT0_PAGE); + outb(index, iobase + EC_PORT0_INDEX); + value = inb(iobase + EC_PORT0_DATA); + /* Need to write 0xff at the end of transaction */ + outb(0xff, iobase + EC_PORT0_PAGE); + + return value; +} diff --git a/src/superio/nuvoton/nct6687d/nct6687d_ec.h b/src/superio/nuvoton/nct6687d/nct6687d_ec.h new file mode 100644 index 00000000000..d32f32c4678 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/nct6687d_ec.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT6687D_EC_H +#define SUPERIO_NUVOTON_NCT6687D_EC_H + +#include + +/* Offsets in the EC IO base. Port0 for firmware use, Port1 for software use */ +#define EC_PORT0_PAGE 0 +#define EC_PORT0_INDEX 1 +#define EC_PORT0_DATA 2 +#define EC_PORT0_HOST_IF_EVENT 3 + +#define EC_PORT1_PAGE 4 +#define EC_PORT1_INDEX 5 +#define EC_PORT1_DATA 6 +#define EC_PORT1_HOST_IF_EVENT 7 + +void nct6687d_ec_write_page(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value); +void nct6687d_ec_write_page_ff(uint16_t iobase, uint8_t page, uint8_t index, uint8_t value); +void nct6687d_ec_and_or_page(uint16_t iobase, uint8_t page, uint8_t index, + uint8_t and_mask, uint8_t or_mask); +void nct6687d_ec_and_or_page_ff(uint16_t iobase, uint8_t page, uint8_t index, + uint8_t and_mask, uint8_t or_mask); +uint8_t nct6687d_ec_read_page(uint16_t iobase, uint8_t page, uint8_t index); + +#endif /* SUPERIO_NUVOTON_NCT6687D_EC_H */ diff --git a/src/superio/nuvoton/nct6687d/nct6687d_hwm.c b/src/superio/nuvoton/nct6687d/nct6687d_hwm.c new file mode 100644 index 00000000000..54d37cb20ae --- /dev/null +++ b/src/superio/nuvoton/nct6687d/nct6687d_hwm.c @@ -0,0 +1,960 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include + +#include "chip.h" +#include "nct6687d_hwm.h" + +uint16_t nct6687d_hwm_base = 0; + +static bool check_cond(const bool cond, const char* error) +{ + if (!cond) + printk(BIOS_ERR, "NCT6687D: %s\n", error); + + return !cond; +} + +static inline void print_status_bit(const char* status, const bool cond) +{ + printk(BIOS_DEBUG, "\t%-45s: %s\n", status, cond ? "yes" : "no"); +} + +static void print_fan_engine_status(void) +{ + uint8_t fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + + printk(BIOS_DEBUG, "NCT6687D: Fan Engine Status:\n"); + print_status_bit("PECI configuration adjusted", fan_eng_sts & FAN_PECI_CFG_ADJUSTED); + print_status_bit("All enabled fan channels processed", + fan_eng_sts & FAN_UNFINISHED_FLAG); + print_status_bit("Configuration phase", fan_eng_sts & FAN_CFG_PHASE); + print_status_bit("Configuration invalid", fan_eng_sts & FAN_CFG_INVALID); + print_status_bit("Configuration check done", fan_eng_sts & FAN_CFG_CHECK_DONE); + print_status_bit("Configuration locked", fan_eng_sts & FAN_CFG_LOCK); + printk(BIOS_DEBUG, "Fans in automatic mode driven by %s register\n", + (fan_eng_sts & FAN_DRIVE_BY_DEFAULT_VAL) ? "DEFAULT_VAL" : "MOD_SEL"); +} + +static bool unlock_fan_register_set(void) +{ + uint8_t fan_eng_sts; + bool done = false; + unsigned int i; + + fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + + if (!(fan_eng_sts & FAN_CFG_LOCK) && (fan_eng_sts & FAN_CFG_PHASE)) + return true; + + for (i = 1000; i > 0; i--) { + /* Wait until EC exits config phase and config request is clear */ + if ((hwm_reg_read(FAN_ENGINE_STS_REG) & FAN_CFG_PHASE) == 0 && + (hwm_reg_read(FAN_CFG_CTRL_REG) & FAN_CFG_REQUEST) == 0) { + done = true; + break; + } + mdelay(1); + } + + if (!done) { + printk(BIOS_WARNING, "Timeout waiting for EC to exit config phase or clear" + "config request\n"); + print_fan_engine_status(); + return false; + } + + done = false; + + hwm_reg_write(FAN_CFG_CTRL_REG, FAN_CFG_REQUEST); + + for (i = 1000; i > 0; i--) { + /* Wait until EC unlock the register set */ + if ((hwm_reg_read(FAN_ENGINE_STS_REG) & FAN_CFG_LOCK) == 0) { + done = true; + break; + } + mdelay(1); + } + + if (!done) { + printk(BIOS_WARNING, "Timeout waiting for EC to unlock the fan registers\n"); + print_fan_engine_status(); + return false; + } + + return true; +} + +static void print_last_err(uint8_t error_code) +{ + uint8_t debug_level = BIOS_WARNING; + uint8_t last_err_code = hwm_reg_read(FAN_LAST_ERROR_CODE_REG); + + if (last_err_code == FAN_NO_ERROR) { + printk(BIOS_DEBUG, "No error occurred.\n"); + return; + } + + /* Lower the debug level if it is an error we care about */ + if (last_err_code == error_code) + debug_level = BIOS_ERR; + + switch (last_err_code) { + case FAN_ERR_MODE_SELECT: + printk(debug_level, "Mode Select invalid configuration\n"); + break; + case FAN_ERR_CRIT_TEMP_PROTECT: + printk(debug_level, "Critical Temperature Protection invalid configuration\n"); + break; + case FAN_ERR_ITL_FAN_CONTROL: + printk(debug_level, "Intel DTS Sensor invalid configuration\n"); + break; + case FAN_ERR_SMART_TRACKING: + printk(debug_level, "Smart Tracking invalid configuration\n"); + break; + case FAN_ERR_THERMAL_CRUISE: + printk(debug_level, "Thermal Cruise invalid configuration\n"); + break; + case FAN_ERR_SPEED_CRUISE: + printk(debug_level, "Speed Cruise invalid configuration\n"); + break; + case FAN_ERR_SMART_FAN_IV: + printk(debug_level, "Smart Fan IV invalid configuration\n"); + break; + case FAN_ERR_PID_CONTROL: + printk(debug_level, "PID control invalid configuration\n"); + break; + default: + printk(debug_level, "Unkown fan configuration error %02x\n", last_err_code); + break; + } +} + +static void lock_fan_register_set_and_check(uint8_t error_code) +{ + uint8_t fan_eng_sts; + bool done = false; + unsigned int i; + + fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + + if (fan_eng_sts & FAN_CFG_LOCK || !(fan_eng_sts & FAN_CFG_PHASE)) { + printk(BIOS_DEBUG, "Fan register set already locked or not in config phase\n"); + return; + } + + hwm_reg_write(FAN_CFG_CTRL_REG, FAN_CFG_DONE); + + for (i = 1000; i > 0; i--) { + fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + /* Wait until EC checks the configuration */ + if (fan_eng_sts & FAN_CFG_CHECK_DONE) { + done = true; + break; + } + mdelay(1); + } + + if (!done) { + printk(BIOS_WARNING, "Timeout waiting for configuration check done\n"); + print_fan_engine_status(); + return; + } + + fan_eng_sts = hwm_reg_read(FAN_ENGINE_STS_REG); + + if (fan_eng_sts & FAN_CFG_INVALID) { + printk(BIOS_WARNING, "NCT6687D: Configuration error ocurred\n"); + print_last_err(error_code); + } + + if (!(fan_eng_sts & FAN_CFG_LOCK)) { + printk(BIOS_WARNING, "NCT6687D: Configuration registers did not lock\n"); + print_fan_engine_status(); + } +} + +static void init_pch_smbus_sensor(const struct nct6687d_pch_smbus_sensor *smbus_sensor) +{ + if (!smbus_sensor->sensor_addr || !smbus_sensor->sensor_cmd) { + printk(BIOS_ERR, "NCT6687D SMBus sensor CMD or ADDR missing!\n"); + return; + } + + /* Enable SMBUS first */ + hwm_reg_write(SMBUS_MASTER_CFG2_REG, 0x04); + hwm_reg_write(SMBUS_MASTER_BAUD_RATE_SEL_REG, SMB_MASTER_BAUD_100K); + hwm_reg_set_bits(SMBUS_MASTER_CFG1_REG, SMB_MASTER_EN); + + hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_BAUD_SEL_MASK, + smbus_sensor->baud_rate & PCH_BAUD_SEL_MASK); + hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_PORT_SEL_MASK, + PCH_THERMAL_PORT(smbus_sensor->port_sel) & PCH_PORT_SEL_MASK); + + if (smbus_sensor->report_one_byte) + hwm_reg_set_bits(PCH_THERMAL_DATA_CFG_REG, PCH_ONE_BYTE_REPORT); + else + hwm_reg_and_or(PCH_THERMAL_DATA_CFG_REG, ~PCH_ONE_BYTE_REPORT & 0xff, 0); + + + hwm_reg_write(PCH_DEVICE_ADDR_REG, smbus_sensor->sensor_addr); + hwm_reg_write(PCH_THERMAL_CMD_REG, smbus_sensor->sensor_cmd); +} + +static void init_sensors(const struct superio_nuvoton_nct6687d_config *conf) +{ + unsigned int i; + bool peci_en = false; + const enum nct6687d_sensor_src_select *sensors = conf->sensors; + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping sensors programming\n"); + return; + } + + printk(BIOS_DEBUG, "NCT6687D programming sensors\n"); + /* Start monitoring */ + hwm_reg_set_bits(HWM_CONFIG_REG, HWM_EN); + + for (i = 0; i < MAX_NUM_SENSORS; i++) { + hwm_reg_write(SENSOR_CFG_REG(i), sensors[i] & SENSOR_SRC_SEL_MASK); + + if (sensors[i] >= PECI_AGENT0_DOMAIN0 && + sensors[i] <= PECI_AGENT3_DOMAIN1) { + hwm_reg_and_or(PECI_AGENT_EN_REG, ~PECI_AGENT_EN_MASK, + PECI_AGENT_EN(sensors[i] & 0x3)); + peci_en = true; + } + + /* Only PCH SMBus sensor supported right now */ + if (sensors[i] >= PCH_CPU && sensors[i] <= PCH_DIMM3 && + i == conf->smbus_sensor.sensor_idx && + conf->smbus_sensor.sensor_en) { + init_pch_smbus_sensor(&conf->smbus_sensor); + } + } + + if (peci_en) { + hwm_reg_and_or(PECI_CFG_REG, PECI_SPEED_SEL_MASK, + conf->peci_speed & PECI_SPEED_SEL_MASK); + hwm_reg_set_bits(PECI_CFG_REG, PECI_AGENT_INIT | PECI_EN); + } + + lock_fan_register_set_and_check(FAN_NO_ERROR); +} + +static bool intel_dts_sensor_control_point_check(const struct nct6687d_dts_sensor_config *dts, + unsigned int i) +{ + bool failure = false; + + failure |= check_cond(dts->ambient_temp[i] <= 127, + "DTS Sensor Ambient Temperature Levels should be <= 127"); + + if (i < MAX_DTS_CTL_POINTS - 1) { + failure |= check_cond(dts->ambient_temp[i + 1] >= dts->ambient_temp[i], + "DTS Sensor next Ambient Temperature Level must be " + "higher or equal to previous Ambient Temperature Level"); + failure |= check_cond(dts->rpm_start_point[i + 1] > dts->rpm_start_point[i], + "DTS Sensor next RPM Start Point must be higher than " + "previous RPM Start Point"); + failure |= check_cond(dts->rpm_end_point[i + 1] > dts->rpm_end_point[i], + "DTS Sensor next RPM End Point must be higher than " + "previous RPM End Point"); + } + + failure |= check_cond(dts->rpm_end_point[i] > dts->rpm_start_point[i], + "DTS Sensor RPM End Point must be higher than corresponding RPM " + "Start Point"); + + return failure; +} + +static bool intel_dts_sensor_config_check(const struct nct6687d_dts_sensor_config *dts) +{ + bool failure = false; + unsigned int i; + + failure |= check_cond(dts->temp_end > dts->temp_start, + "DTS Sensor Temperture End Point should be > " + "Temperture End Point"); + failure |= check_cond(dts->temp_start <= 127, + "DTS Sensor Temperture Start Point should be <= 127"); + failure |= check_cond(dts->temp_end <= 127, + "DTS Sensor Temperture End Point should be <= 127"); + + if (dts->peci_adjust) { + failure |= check_cond(dts->peci_agent_idx < 8, + "DTS Sensor PECI Agent Index should be < 8"); + } + + for (i = 0; i < MAX_DTS_CTL_POINTS; i++) + failure |= intel_dts_sensor_control_point_check(dts, i); + + return failure; +} + +static void init_intel_dts_sensor(const struct nct6687d_dts_sensor_config *dts) +{ + static int init_once = 0; + unsigned int i; + + if (init_once) + return; + + if (intel_dts_sensor_config_check(dts)) { + printk(BIOS_ERR, "NCT6687D DTS Sensor invalid config, " + "skipping sensor programming\n"); + return; + } + + printk(BIOS_DEBUG, "NCT6687D programming DTS sensor\n"); + + hwm_reg_write(ITL_TEMP_START_POINT_REG, dts->temp_start); + hwm_reg_write(ITL_TEMP_END_POINT_REG, dts->temp_end); + + hwm_reg_write(ITL_RPM_MAX_SPEED_HI_REG, dts->max_speed >> 8); + hwm_reg_write(ITL_RPM_MAX_SPEED_LO_REG, dts->max_speed & 0xff); + + for (i = 0; i < MAX_DTS_CTL_POINTS; i++) { + hwm_reg_write(ITL_AMB_TEMP_START_POINT_REG(i), dts->ambient_temp[i]); + hwm_reg_write(ITL_RPM_START_POINT_HI_REG(i), dts->rpm_start_point[i] >> 8); + hwm_reg_write(ITL_RPM_START_POINT_LO_REG(i), dts->rpm_start_point[i] & 0xff); + hwm_reg_write(ITL_RPM_END_POINT_HI_REG(i), dts->rpm_end_point[i] >> 8); + hwm_reg_write(ITL_RPM_END_POINT_LO_REG(i), dts->rpm_end_point[i] & 0xff); + } + + if (dts->peci_adjust) { + hwm_reg_and_or(ITL_DTS_CFG_REG, ~ITL_DTS_PECI_AGENT_IDX_SEL_MASK, + dts->peci_agent_idx & ITL_DTS_PECI_AGENT_IDX_SEL_MASK); + hwm_reg_set_bits(ITL_DTS_CFG_REG, ITL_DTS_PECI_CFG_ADJUSTMENT); + } + + init_once = 1; +} + +static void init_intel_dts2_sensor(const struct nct6687d_dts2_sensor_config *dts2) +{ + static int init_once = 0; + + if (init_once) + return; + + printk(BIOS_DEBUG, "NCT6687D programming DTS2 sensor\n"); + + hwm_reg_write(DTS2_TARGET_MARGIN_REG, (uint8_t)dts2->target_margin); + hwm_reg_write(DTS2_TCONTROL_REG, (uint8_t)dts2->t_control); + hwm_reg_write(DTS2_TCONTROL_OFFSET_REG, (uint8_t)dts2->t_control_offset); + hwm_reg_write(DTS2_TARGET_TOLERANCE_REG, dts2->target_margin_tolerance); + + hwm_reg_write(DTS2_STEP_SPEED_HI_REG, dts2->step_speed >> 8); + hwm_reg_write(DTS2_STEP_SPEED_LO_REG, dts2->step_speed & 0xff); + hwm_reg_write(DTS2_MIN_SPEED_HI_REG, dts2->min_speed >> 8); + hwm_reg_write(DTS2_MIN_SPEED_LO_REG, dts2->min_speed & 0xff); + + hwm_reg_write(DTS2_DELAY_TIME_COUNTER_REG, dts2->delay_time); + hwm_reg_write(DTS2_DIVISOR_REG, dts2->divisor); + + init_once = 1; +} + +static void lock_sensor_config(void) +{ + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping misc fan config programming\n"); + return; + } + hwm_reg_set_bits(HWM_CONFIG_REG, LOCK_SENSOR_CFG); + lock_fan_register_set_and_check(FAN_NO_ERROR); +} + +static void init_ambient_floor_alg(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + static int init_once = 0; + const struct nct6687d_ambient_floor_fan_config *amb_floor_fan; + const struct nct6687d_ambient_floor_config *amb_floor_cfg = &conf->ambient_floor; + + amb_floor_fan = &conf->fans[idx - 1].amb_floor_fan_cfg; + + printk(BIOS_DEBUG, "NCT6687D initializing ambient floor algorithm\n"); + + if (!init_once) { + hwm_reg_write(AMBIENT_FLOOR_TEMP_START_POINT_REG, amb_floor_cfg->temp_start); + hwm_reg_write(AMBIENT_FLOOR_TEMP_END_POINT_REG, amb_floor_cfg->temp_end); + init_once = 1; + } + + hwm_reg_write(FAN_AMB_FLOOR_MIN_OUT_START_REG(idx), + FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_start)); + hwm_reg_write(FAN_AMB_FLOOR_MIN_OUT_END_REG(idx), + FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_end)); + hwm_reg_write(FAN_AMB_FLOOR_MAX_OUT_REG(idx), + FAN_AMB_FLOOR_RPM_TO_REG(amb_floor_fan->minout_max)); +} + +static void init_smart_tracking_alg(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + static int init_once = 0; + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_smart_tracking_config *smart_track = &conf->smart_tracking; + + printk(BIOS_DEBUG, "NCT6687D initializing smart tracking algorithm\n"); + + if (!init_once) { + hwm_reg_write(FAN_LOW_RPM_SPEED_BOUNDARY_HI_REG, + smart_track->speed_boundary_low >> 8); + hwm_reg_write(FAN_LOW_RPM_SPEED_BOUNDARY_LO_REG, + smart_track->speed_boundary_low & 0xff); + hwm_reg_write(FAN_HIGH_RPM_SPEED_BOUNDARY_HI_REG, + smart_track->speed_boundary_high >> 8); + hwm_reg_write(FAN_HIGH_RPM_SPEED_BOUNDARY_LO_REG, + smart_track->speed_boundary_high & 0xff); + hwm_reg_write(FAN_LOW_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_low); + hwm_reg_write(FAN_MID_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_mid); + hwm_reg_write(FAN_HIGH_RPM_TOLERANCE_REG, smart_track->rpm_tolerance_high); + + hwm_reg_write(FAN_TRACKING_STEP_REG, ((smart_track->step_up & 0xf) << 4) | + (smart_track->step_down & 0xf)); + + hwm_reg_write(FAN_FAST_TRACK_TEMP_BOUNDARY_REG, smart_track->temp_boundary); + + hwm_reg_write(FAN_LOW_RPM_FAST_TRACK_WEIGHT_REG, + ((smart_track->weight_up_low & 7) << 4) | + (smart_track->weight_down_low & 7)); + hwm_reg_write(FAN_MID_RPM_FAST_TRACK_WEIGHT_REG, + ((smart_track->weight_up_mid & 7) << 4) | + (smart_track->weight_down_mid & 7)); + hwm_reg_write(FAN_HIGH_RPM_FAST_TRACK_WEIGHT_REG, + ((smart_track->weight_up_high & 7) << 4) | + (smart_track->weight_down_high & 7)); + + hwm_reg_write(FAN_LOW_RPM_FAST_TRACK_DUTY_STEP_REG, + smart_track->duty_step_low & 0xf); + hwm_reg_write(FAN_MID_RPM_FAST_TRACK_DUTY_STEP_REG, + smart_track->duty_step_mid & 0xf); + hwm_reg_write(FAN_HIGH_RPM_FAST_TRACK_DUTY_STEP_REG, + smart_track->duty_step_high & 0xf); + + hwm_reg_write(FAN_MARKUP_TRACK_AMB_TEMP_BOUNDARY_REG, + smart_track->ambient_temp_boundary); + + hwm_reg_write(FAN_MARKUP_TRACK_WEIGHT_REG, smart_track->weight_val & 7); + + init_once = 1; + } + + if (fan->fast_tracking_en) + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_FAST_TRACK_EN); + + + if (fan->markup_tracking_en) + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MARKUP_TRACK_EN); +} + +static void misc_fan_config(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping misc fan config programming\n"); + return; + } + + if (fan->fan_alg_weight) { + printk(BIOS_DEBUG, "Programming algorithm weight for FAN%d\n", idx); + hwm_reg_and_or(FAN_ALG_ENGINE_WEIGHT_VAL_REG(idx), + ~FAN_ALG_ENGINE_WEIGHT_MASK(idx), + (fan->fan_alg_weight & 0xf) << + FAN_ALG_ENGINE_WEIGHT_SHIFT(idx)); + hwm_reg_set_bits(FAN_ALG_ENGINE_WEIGHT_EN_REG(idx), + FAN_ALG_ENGINE_WEIGHT_CHANNEL_EN(idx)); + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_ALG_EN); + } + + if (fan->crit_temp) { + if (!check_cond(fan->crit_temp >= fan->crit_temp_tolerance, + "Fan Critical Temperature should be >= " + "Critical Temperature Tolerance")) { + printk(BIOS_DEBUG, "Enabling critical temperature for FAN%d\n", idx); + hwm_reg_write(FAN_CRIT_TEMP_CFG_REG(idx), fan->crit_temp & 0x7f); + if (fan->crit_temp_tolerance) + hwm_reg_write(FAN_CRIT_TEMP_TOLERANCE_REG(idx), + fan->crit_temp_tolerance & 0xf); + + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), + FAN_ALG_FUNCTRL_CRIT_TEMP_EN); + } + } + + if (fan->temp_err_duty) { + hwm_reg_write(FAN_TEMP_ERR_DUTY_VAL_REG(idx), fan->temp_err_duty); + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_TEMP_ERR); + } + + if (fan->dts1_en && fan->dts2_en) { + printk(BIOS_ERR, "DTS and DTS2 sensors can't coexist!\n"); + printk(BIOS_ERR, "Skipping DTS configuration\n"); + } else { + if (fan->dts1_en) { + init_intel_dts_sensor(&conf->dts_sensor); + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS1_EN); + } + + if (fan->dts2_en) { + init_intel_dts2_sensor(&conf->dts2_sensor); + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS2_EN); + } + } + + if (fan->dts_ub_en) + hwm_reg_set_bits(FAN_ALG_FUNCTRL_REG(idx), FAN_ALG_FUNCTRL_DTS_UB_EN); + + + if (fan->smart_tracking_en) { + init_smart_tracking_alg(conf, idx); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_SMART_TRACK_EN); + } + + if (conf->fan_default_val && conf->fan_default_val <= 100) + hwm_reg_write(FAN_DEFAULT_VAL_REG, + FAN_PWM_PERCENT_TO_HEX(conf->fan_default_val)); + + /* Some registers for functionalities below are missing for fan 9 and 10 */ + if (idx > 8) { + lock_fan_register_set_and_check(FAN_NO_ERROR); + return; + } + + if (fan->ambient_floor_en) { + init_ambient_floor_alg(conf, idx); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_AMBIENT_FLOOR_EN); + } + + if (fan->startup_duty && fan->startup_duty <= 100) { + hwm_reg_write(FAN_STARTUP_DUTY_REG(idx), + FAN_PWM_PERCENT_TO_HEX(fan->startup_duty)); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_STARTUP_EN); + } + + if (fan->manual_offset) { + hwm_reg_write(FAN_MANUAL_OFFSET_REG(idx), fan->manual_offset); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MANUAL_OFFSET_EN); + } + + if (fan->min_duty && fan->min_duty <= 100) { + hwm_reg_write(FAN_MIN_DUTY_REG(idx), FAN_PWM_PERCENT_TO_HEX(fan->min_duty)); + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_MINDUTY_EN); + } + + lock_fan_register_set_and_check(FAN_NO_ERROR); +} + +static void set_fan_pins_and_mode(const struct nct6687d_fan_config *fan, unsigned int idx) +{ + enum nct6687d_fan_mode mode = fan->mode; + + /* FAN_IGNORE takes the mapping of manual mode to detect unitialized fans */ + if (mode == FAN_MODE_MANUAL) + mode = 0; + + hwm_reg_and_or(FAN_MODE_SEL_REG(idx), ~FAN_MODE_SEL_MASK, mode & FAN_MODE_SEL_MASK); + hwm_reg_and_or(FANIN_CFG_REG(idx), ~FANIN_PIN_SEL_MASK, + fan->fanin_sel & FANIN_PIN_SEL_MASK); + hwm_reg_set_bits(FANIN_CFG_REG(idx), FANIN_MONITOR_EN); + + hwm_reg_and_or(FANOUT_CFG_REG(idx), ~FANOUT_PIN_SEL_MASK, + fan->fanout_sel & FANOUT_PIN_SEL_MASK); + hwm_reg_set_bits(FANOUT_CFG_REG(idx), FANOUT_EN); +} + +static bool smart_fan_level_check(const struct nct6687d_fan_config *fan, + const struct nct6687d_smart_fan_iv_config *s_fan, + int i) +{ + bool failure = false; + + failure |= check_cond(s_fan->temp_levels[i] <= 127, + "Smart Fan IV Temperature Levels should be <= 127"); + if (i < MAX_TEMP_SPEED_LEVELS - 1) { + failure |= check_cond(s_fan->temp_levels[i + 1] >= s_fan->temp_levels[i], + "Smart Fan IV next Temperature Level must be higher" + " or equal to previous Temperature Level"); + failure |= check_cond(s_fan->speed_levels[i + 1] >= s_fan->speed_levels[i], + "Smart Fan IV next Speed Level must be higher or " + "equal to previous Speed Level"); + } + + if (fan->unit_sel == FAN_PWM) { + failure |= check_cond(s_fan->speed_levels[i] <= 100, + "Smart Fan IV PWM Speed Levels should be <= 100"); + } else if (fan->unit_sel == FAN_RPM) { + failure |= check_cond(s_fan->speed_levels[i] <= 0x3fff, + "Smart Fan IV RPM Speed Levels should be" + "<= 16383 RPM"); + } else { + failure |= check_cond(false, "Smart Fan IV invalid Fan Unit Selection"); + } + + return failure; + +} + +static bool smart_fan_config_check(const struct nct6687d_fan_config *fan, + const struct nct6687d_smart_fan_iv_config *s_fan) +{ + bool failure = false; + unsigned int i; + + for (i = 0; i < MAX_TEMP_SPEED_LEVELS; i++) + failure |= smart_fan_level_check(fan, s_fan, i); + + failure |= check_cond(s_fan->temp_levels[0] >= s_fan->temp_cut_off, + "Smart Fan IV Temperature Level 1 should be >= " + "Temperature Cut Off"); + failure |= check_cond(s_fan->temp_levels[0] >= + (s_fan->temp_cut_off + s_fan->temp_hystheresis), + "Smart Fan IV Temperature Level 1 should be >= " + "Temperature Cut Off + Temperature Hysteresis"); + + return failure; +} + +static void init_smart_fan(const struct superio_nuvoton_nct6687d_config *conf, unsigned int idx) +{ + unsigned int i; + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_smart_fan_iv_config *sfan = &fan->smart_fan; + + if (smart_fan_config_check(fan, sfan)) { + printk(BIOS_ERR, "NCT6687D Smart Fan IV invalid config, " + "skipping fan programming\n"); + return; + } + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping Smart Fan IV config programming\n"); + return; + } + + set_fan_pins_and_mode(fan, idx); + + if (fan->unit_sel == FAN_PWM) + hwm_reg_and_or(FAN_FUNCTION_CTRL(idx), ~FAN_FUN_UNIT_RPM & 0xff, + FAN_FUN_UNIT_PWM_DUTY); + else if (fan->unit_sel == FAN_RPM) + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM); + + /* Registers start from MSB */ + for (i = 0; i < MAX_TEMP_SRC; i++) { + hwm_reg_write(FAN_MTZ_DCS_DATA_REG(MAX_TEMP_SRC - 1 - i, idx), + sfan->temp_src[i]); + } + + for (i = 0; i < MAX_TEMP_SPEED_LEVELS; i++) { + if (sfan->temp_levels[i]) + hwm_reg_write(FAN_SF4_TEMP_LVL_REG(idx, i), + sfan->temp_levels[i]); + if (sfan->speed_levels[i]) { + if (fan->unit_sel == FAN_PWM) { + hwm_reg_write(FAN_SF4_PWM_RPM_LVL_HI_REG(idx, i), 0); + hwm_reg_write(FAN_SF4_PWM_RPM_LVL_LO_REG(idx, i), + FAN_PWM_PERCENT_TO_HEX(sfan->speed_levels[i])); + } + + if (fan->unit_sel == FAN_RPM) { + hwm_reg_write(FAN_SF4_PWM_RPM_LVL_HI_REG(idx, i), + sfan->speed_levels[i] >> 8); + hwm_reg_write(FAN_SF4_PWM_RPM_LVL_LO_REG(idx, i), + sfan->speed_levels[i] & 0xff); + } + } + } + + hwm_reg_write(FAN_SF4_TEMP_OFF_HYSTHERESIS_REG(idx), sfan->temp_hystheresis); + hwm_reg_write(FAN_SF4_TEMP_CUT_OFF_REG(idx), sfan->temp_cut_off); + hwm_reg_write(FAN_SF4_TEMP_OFF_DELAY_REG(idx), sfan->cut_off_delay); + + hwm_reg_write(FAN_STEP_UP_TIME_REG(idx), sfan->step_up_time); + hwm_reg_write(FAN_STEP_DOWN_TIME_REG(idx), sfan->step_down_time); + + /* Set fan mode to automatic */ + hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0x00); + + hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); + + lock_fan_register_set_and_check(FAN_ERR_SMART_FAN_IV); + + misc_fan_config(conf, idx); +} + +static void init_manual_fan(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_manual_fan_config *manual_fan = &fan->manual_fan; + + if (manual_fan->manual_duty || manual_fan->manual_duty > 100) { + printk(BIOS_ERR, "NCT6687D: invalid duty cycle for manual fan mode\n"); + return; + } + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping manual fan config programming\n"); + return; + } + + set_fan_pins_and_mode(fan, idx); + + if (fan->unit_sel == FAN_PWM) + hwm_reg_and_or(FAN_FUNCTION_CTRL(idx), ~FAN_FUN_UNIT_RPM & 0xff, + FAN_FUN_UNIT_PWM_DUTY); + else if (fan->unit_sel == FAN_RPM) + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM); + + hwm_reg_write(FAN_MANUAL_VALUE_REG(idx), + FAN_PWM_PERCENT_TO_HEX(manual_fan->manual_duty)); + + hwm_reg_set_bits(FAN_MANUAL_EN_REG(idx), FAN_MANUAL_EN(idx)); + + hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); + + lock_fan_register_set_and_check(FAN_NO_ERROR); + + misc_fan_config(conf, idx); +} + +static bool thermal_cruise_config_check(const struct nct6687d_fan_thermal_cruise_config *tc_fan) +{ + bool failure = false; + + failure |= check_cond(tc_fan->step_down_time > 0, + "Thermal Cruise Step-Down Time should be > 0"); + failure |= check_cond(tc_fan->step_up_time > 0, + "Thermal Cruise Step-Up Time should be > 0"); + failure |= check_cond(tc_fan->initial_value > tc_fan->stop_value, + "Thermal Cruise Initial value should be > Stop Value"); + failure |= check_cond(tc_fan->target_temp >= tc_fan->temp_tolerance, + "Thermal Cruise Target Temperature should be" + " >= Temperature Tolerance"); + if (tc_fan->keep_min_fan_output) { + failure |= check_cond(tc_fan->stop_value > 0, + "Thermal Cruise Stop Value should be > 0"); + } else { + failure |= check_cond(tc_fan->stop_time > 0, + "Thermal Cruise Stop Time should be > 0"); + } + + return failure; +} + +static void init_thermal_cruise_fan(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_fan_thermal_cruise_config *tc_fan = &fan->thermal_cruise_fan; + + if (thermal_cruise_config_check(tc_fan)) { + printk(BIOS_ERR, "NCT6687D Thermal Cruise invalid config, " + "skipping fan programming\n"); + return; + } + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping Thermal Cruise fan config programming\n"); + return; + } + + set_fan_pins_and_mode(fan, idx); + + hwm_reg_write(FAN_TC_TARGET_TEMP_REG(idx), + tc_fan->target_temp & FAN_TC_TARGET_TEMP_MASK); + + if (tc_fan->keep_min_fan_output) { + hwm_reg_set_bits(FAN_TC_TARGET_TEMP_REG(idx), FAN_TC_KEEP_MIN_OUTPUT); + hwm_reg_write(FAN_TC_STOP_VALUE_REG(idx), tc_fan->stop_value); + } + + hwm_reg_write(FAN_TC_TARGET_TEMP_TOLERANCE_REG(idx), + tc_fan->temp_tolerance & FAN_TC_TEMP_TOLERANCE_MASK); + + hwm_reg_write(FAN_INITIAL_VALUE_REG(idx), tc_fan->initial_value); + + hwm_reg_write(FAN_TC_STOP_TIME_REG(idx), tc_fan->stop_time); + hwm_reg_write(FAN_TC_STEP_DOWN_TIME_REG(idx), tc_fan->step_up_time); + hwm_reg_write(FAN_TC_STEP_UP_TIME_REG(idx), tc_fan->step_down_time); + + /* Set fan mode to automatic */ + hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0); + + hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); + + lock_fan_register_set_and_check(FAN_ERR_THERMAL_CRUISE); + + misc_fan_config(conf, idx); +} + +static bool speed_cruise_config_check(const struct nct6687d_fan_speed_cruise_config *sc_fan) +{ + bool failure = false; + + failure |= check_cond(sc_fan->target_rpm <= 0x3fff, + "Speed Cruise Target RPM should be <= 16838 RPM"); + failure |= check_cond(sc_fan->target_rpm >= sc_fan->rpm_tolerance, + "Speed Cruise Target RPM should be >= RPM Tolerance"); + failure |= check_cond(sc_fan->step_down_time > 0, + "Speed Cruise Step-Down Time should be > 0"); + failure |= check_cond(sc_fan->step_up_time > 0, + "Speed Cruise Step-Up Time should be > 0"); + + return failure; +} + +static void init_speed_cruise_fan(const struct superio_nuvoton_nct6687d_config *conf, + unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + const struct nct6687d_fan_speed_cruise_config *sc_fan = &fan->speed_cruise_fan; + + if (speed_cruise_config_check(sc_fan)) { + printk(BIOS_ERR, "NCT6687D Speed Cruise invalid config, " + "skipping fan programming\n"); + return; + } + + if (!unlock_fan_register_set()) { + printk(BIOS_ERR, "NCT6687D failed to unlock registers, " + "skipping Speed Cruise fan config programming\n"); + return; + } + + set_fan_pins_and_mode(fan, idx); + + /* Speed cruise should only enable RPM units */ + hwm_reg_set_bits(FAN_FUNCTION_CTRL(idx), FAN_FUN_UNIT_RPM); + + hwm_reg_write(FAN_SC_TARGET_RPM_HI_REG(idx), sc_fan->target_rpm >> 8); + hwm_reg_write(FAN_SC_TARGET_RPM_LO_REG(idx), sc_fan->target_rpm & 0xff); + + hwm_reg_write(FAN_SC_TARGET_RPM_TOLERANCE_HI_REG(idx), sc_fan->rpm_tolerance >> 8); + hwm_reg_write(FAN_SC_TARGET_RPM_TOLERANCE_LO_REG(idx), sc_fan->rpm_tolerance & 0xff); + + hwm_reg_write(FAN_SC_STEP_DOWN_TIME_REG(idx), sc_fan->step_up_time); + hwm_reg_write(FAN_SC_STEP_UP_TIME_REG(idx), sc_fan->step_down_time); + + /* Set fan mode to automatic */ + hwm_reg_and_or(FAN_MANUAL_EN_REG(idx), ~FAN_MANUAL_EN(idx), 0x00); + + hwm_reg_set_bits(FAN_CHANNEL_EN_REG(idx), FAN_CHANNEL_EN(idx)); + + lock_fan_register_set_and_check(FAN_ERR_SPEED_CRUISE); + + misc_fan_config(conf, idx); +}; + +static void init_one_fan(const struct superio_nuvoton_nct6687d_config *conf, unsigned int idx) +{ + const struct nct6687d_fan_config *fan = &conf->fans[idx - 1]; + + switch(fan->mode) { + case FAN_THERMAL_CRUISE: + printk(BIOS_DEBUG, "Initializing Thermal Cruise for FAN%d\n", idx); + init_thermal_cruise_fan(conf, idx); + break; + case FAN_SPEED_CRUISE: + printk(BIOS_DEBUG, "Initializing Speed Cruise for FAN%d\n", idx); + init_speed_cruise_fan(conf, idx); + break; + case FAN_SMART_FAN_IV: + printk(BIOS_DEBUG, "Initializing Smart FAN IV for FAN%d\n", idx); + init_smart_fan(conf, idx); + break; + case FAN_PID_CONTROL: + printk(BIOS_WARNING, "NCT6687D: PID Control fan mode not yet supported\n"); + break; + case FAN_MODE_MANUAL: + printk(BIOS_DEBUG, "Initializing manual fan mode for FAN%d\n", idx); + init_manual_fan(conf, idx); + break; + default: + printk(BIOS_ERR, "NCT6687D: unknown fan mode detected!\n"); + } +} + +static void init_fans(const struct superio_nuvoton_nct6687d_config *conf) +{ + unsigned int i; + const struct nct6687d_fan_config *fans = conf->fans; + + for (i = 1; i <= MAX_NUM_FANS; i++) { + if (fans[i - 1].mode == FAN_IGNORE) + continue; + + init_one_fan(conf, i); + } +} + +static void report_ec_info(void) +{ + unsigned int i; + + printk(BIOS_DEBUG, "NCT6687D EC info:\n"); + printk(BIOS_DEBUG, "\tChip ID: %04x\n", + (uint16_t)hwm_reg_read(CHIP_ID0_REG) | + (uint16_t)(hwm_reg_read(CHIP_ID1_REG) << 8)); + printk(BIOS_DEBUG, "\tCustomer ID: %04x\n", + (uint16_t)hwm_reg_read(CUSTOMER_ID0_REG) | + (uint16_t)(hwm_reg_read(CUSTOMER_ID1_REG) << 8)); + printk(BIOS_DEBUG, "\tFW build date: %02d/%02d/20%02d\n", + hwm_reg_read(FW_BUILD_DAY_REG), + hwm_reg_read(FW_BUILD_MONTH_REG), + hwm_reg_read(FW_BUILD_YEAR_REG)); + printk(BIOS_DEBUG, "\tFW build serial number: %d\n", + hwm_reg_read(FW_BUILD_SERIALNUM_REG)); + printk(BIOS_DEBUG, "\tFW version: %d.%d\n", + hwm_reg_read(FW_VER0_REG), + hwm_reg_read(FW_VER1_REG)); + printk(BIOS_DEBUG, "\tProfile version: %d\n", + hwm_reg_read(PROFILE_VER_REG)); + printk(BIOS_DEBUG, "\tROM version: %d.%d.%d.%d\n", + hwm_reg_read(ROM_VER0_REG), hwm_reg_read(ROM_VER1_REG), + hwm_reg_read(ROM_VER2_REG), hwm_reg_read(ROM_VER3_REG)); + printk(BIOS_DEBUG, "\tISP build date: %02d/%02d/20%02d\n", + hwm_reg_read(ISP_BUILD_DAY_REG), + hwm_reg_read(ISP_BUILD_MONTH_REG), + hwm_reg_read(ISP_BUILD_YEAR_REG)); + printk(BIOS_DEBUG, "\tISP build serial number: %d\n", + hwm_reg_read(ISP_BUILD_SERIALNUM_REG)); + printk(BIOS_DEBUG, "\tISP version: %d.%d\n", + hwm_reg_read(ISP_VER0_REG), + hwm_reg_read(ISP_VER1_REG)); + printk(BIOS_DEBUG, "\tOEM version:"); + + for (i = 0; i < OEM_VER_LEN; i++) + printk(BIOS_DEBUG, "%02x", hwm_reg_read(OEM_VER_REG + i)); + + printk(BIOS_DEBUG, "\n"); +} + +void nct6687d_hwm_init(uint16_t hwm_base, const struct superio_nuvoton_nct6687d_config *conf) +{ + nct6687d_hwm_base = hwm_base; + + report_ec_info(); + + init_sensors(conf); + init_fans(conf); + + lock_sensor_config(); + print_fan_engine_status(); +} diff --git a/src/superio/nuvoton/nct6687d/nct6687d_hwm.h b/src/superio/nuvoton/nct6687d/nct6687d_hwm.h new file mode 100644 index 00000000000..0a7b83b7e39 --- /dev/null +++ b/src/superio/nuvoton/nct6687d/nct6687d_hwm.h @@ -0,0 +1,922 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SUPERIO_NUVOTON_NCT6687D_HWM_H +#define SUPERIO_NUVOTON_NCT6687D_HWM_H + +#include +#include + +#include "chip.h" +#include "nct6687d_ec.h" + +/* + * EC page number will be concatenated with the register offset to mark + * which page the register belongs to. + */ +#define EC_PAGE(page) ((page) << 8) +#define EC_PAGE_REG(page, reg) (EC_PAGE(page) + (reg)) + +/* EC page 1 */ +#define SENSOR_READ_HI_REG(x) EC_PAGE_REG(1, 0x00 + 2*(x)) +#define SENSOR_READ_LO_REG(x) EC_PAGE_REG(1, 0x01 + 2*(x)) +#define FAN_RPM_READ_HI_REG(x) EC_PAGE_REG(1, 0x40 + 2*((x) - 1)) +#define FAN_RPM_READ_LO_REG(x) EC_PAGE_REG(1, 0x41 + 2*((x) - 1)) + +#define FAN_DUTY_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0xf0 + ((fan)-8)) \ + : EC_PAGE_REG(1, 0x60 + 2*((fan) - 1))) + +#define SENSOR_MON_STS_REG EC_PAGE_REG(1, 0x70) +#define TEMP_OVERLOAD (1 << 1) +#define VOLT_OVERLOAD (1 << 1) +#define FAN_OVERLOAD (1 << 2) + +/* Errors and statuses */ +#define PROCHOT_MON_STS_REG EC_PAGE_REG(1, 0x71) +#define SENSOR_ERROR_STS_REG(x) EC_PAGE_REG(1, 0x74 + (x)) +#define TMPIN_IDLE_STS_REG(x) EC_PAGE_REG(1, 0x78 + (x)) +#define FANIN_ERROR_STS_REG(x) EC_PAGE_REG(1, 0x7C + (x)) +#define FANOUT_ERROR_STS_REG EC_PAGE_REG(1, 0x7e) +#define FAN_INIT_STS_REG EC_PAGE_REG(1, 0x7f) + +#define HWM_CONFIG_REG EC_PAGE_REG(1, 0x80) +#define SMI_SCI_SEL (1 << 2) +#define LOCK_SENSOR_CFG (1 << 5) +#define HWM_EN (1 << 7) + +#define SENSOR_MON_VCC_DELAY_REG EC_PAGE_REG(1, 0x81) +#define TEMPIN_IDLE_COUNTER_REG EC_PAGE_REG(1, 0x82) +#define VIRTUAL_INPUT_CFG_REG EC_PAGE_REG(1, 0x83) +#define TMPIN_POLLING_RATE_REG EC_PAGE_REG(1, 0x85) +#define VIN_POLLING_RATE_REG EC_PAGE_REG(1, 0x86) +#define FAN_POLLING_RATE_REG EC_PAGE_REG(1, 0x87) + +#define ADC_CLOCKK_DIV_REG EC_PAGE_REG(1, 0x88) +#define ADC_AVG_NUM_REG EC_PAGE_REG(1, 0x89) +#define ADC_SLOPE_HI_REG EC_PAGE_REG(1, 0x8a) +#define ADC_SLOPE_LO_REG EC_PAGE_REG(1, 0x8b) + +#define PROCHOT_CFG_REG EC_PAGE_REG(1, 0x8e) +#define REFRESH_RATE_MASK (3 << 0) +#define REFRESH_RATE_100MS (0 << 0) +#define REFRESH_RATE_200MS (1 << 0) +#define REFRESH_RATE_500MS (2 << 0) +#define REFRESH_RATE_1S (3 << 0) +#define AVG_TIME_MASK (3 << 2) +#define AVG_TIME_1 (0 << 2) +#define AVG_TIME_2 (1 << 2) +#define AVG_TIME_4 (2 << 2) +#define AVG_TIME_8 (3 << 2) +#define MONITOR_MODE_MASK (3 << 4) +#define MONITOR_MODE_CAPTURE (0 << 4) +#define MONITOR_MODE_8BIT (1 << 4) +#define MONITOR_MODE_12BIT (2 << 4) +#define MONITOR_MODE_16BIT (3 << 4) +#define CLK_SRC_40K (0 << 6) +#define CLK_SRC_MCLK (1 << 6) +#define PROCHOT_EN (1 << 7) + +#define PROCHOT_OUT_REG EC_PAGE_REG(1, 0x8f) + +#define VIRTUAL_SENSOR_INPUT_REG(x) EC_PAGE_REG(1, 0x90 + (x)) + +#define SENSOR_CFG_REG(x) EC_PAGE_REG(1, 0xa0 + (x)) +#define FILTER_EN (1 << 7) +#define SENSOR_SRC_SEL_MASK 0x7f + +#define FANIN_CFG_REG(fan) EC_PAGE_REG(1, 0xc0 + ((fan) - 1)) +#define FANIN_PIN_SEL_MASK 0x1f +#define FANIN_PULSE_REV_MASK (3 << 5) +#define FANIN_PULSE_REV_SHIFT 5 +#define FANIN_MONITOR_EN (1 << 7) + +#define FANOUT_CFG_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0xf4 + ((fan) - 9)) \ + : EC_PAGE_REG(1, 0xd0 + ((fan) - 1))) +#define FANOUT_PIN_SEL_MASK 0x1f +#define FANOUT_TYPE_PP (0 << 5) +#define FANOUT_TYPE_OD (1 << 5) +#define FANOUT_INV_EN (1 << 6) +#define FANOUT_EN (1 << 7) + +#define FAN_INIT_RPM_HI_REG(fan) EC_PAGE_REG(1, 0xe0 + 2*((fan) - 1)) +#define FAN_INIT_RPM_LO_REG(fan) EC_PAGE_REG(1, 0xe1 + 2*((fan) - 1)) +#define FAN_INIT_DUTY_VAL_REG(fan) EC_PAGE_REG(1, 0xf0 + ((fan) - 1)) +#define FAN_INIT_MODE_REG EC_PAGE_REG(1, 0xf8) +#define FAN_INIT_MODE_RPM(fan) (1 << ((fan) - 1)) +#define FAN_INIT_MODE_PWM(fan) (0 << ((fan) - 1)) + +#define FAN_RPM_INIT_UNIT_REG EC_PAGE_REG(1, 0xf9) +#define FAN_RPM_INIT_TOLERANCE_REG EC_PAGE_REG(1, 0xfa) +#define FAN_RPM_INIT_STABLE_COUNTER_REG EC_PAGE_REG(1, 0xfb) +#define FAN_RPM_INIT_TIME_COUNTER_REG EC_PAGE_REG(1, 0xfc) + +/* EC Page 2 - GPIO */ + +#define TIN_OFFSET_REG(x) EC_PAGE_REG(2, 0x00 + (x)) + +#define GPI_FALLING_TRIG_EN_HI_REG EC_PAGE_REG(2, 0xb0) +#define GPI_FALLING_TRIG_EN_LO_REG EC_PAGE_REG(2, 0xb1) +#define GPI_RISING_TRIG_EN_HI_REG EC_PAGE_REG(2, 0xb2) +#define GPI_RISING_TRIG_EN_LO_REG EC_PAGE_REG(2, 0xb3) +#define GPI_DATA_HI_REG EC_PAGE_REG(2, 0xb4) +#define GPI_DATA_LO_REG EC_PAGE_REG(2, 0xb5) +#define GPI_SEL_REG(x) EC_PAGE_REG(2, 0xc0 + (x)) +#define GPO_TYPE_HI_REG EC_PAGE_REG(2, 0xd0) +#define GPO_TYPE_LO_REG EC_PAGE_REG(2, 0xd1) +#define GPO_DATA_HI_REG EC_PAGE_REG(2, 0xd4) +#define GPO_DATA_LO_REG EC_PAGE_REG(2, 0xd5) +#define GPO_SEL_REG(x) EC_PAGE_REG(2, 0xe0 + (x)) + +/* EC page 3 */ + +#define SENSOR_INT_CFG_REG(x) EC_PAGE_REG(3, 0x10 + (x)) +#define TMPIN_INT_SEL_MASK (7 << 0) +#define TMPIN_INT_DISABLE (0 << 0) +#define TMPIN_INT_SHUTDOWN_MODE (1 << 0) +#define TMPIN_INT_SYST_FAN_COMP_MODE (2 << 0) +#define TMPIN_INT_CPUT_FAN_COMP_MODE (3 << 0) +#define TMPIN_INT_TWO_TIMES_MODE (4 << 0) +#define TMPIN_INT_ONE_TIME_MODE (5 << 0) +#define TMPIN_INT_OVT_COMP_MODE (6 << 0) +#define TMPIN_INT_OVT_MODE (7 << 0) +#define VIN_INT_EN (1 << 7) + +#define TMPIN_HYSTERSIS_REG(x) EC_PAGE_REG(3, 0x30 + (x)) +#define TMPIN_OVERTEMP_REG(x) EC_PAGE_REG(3, 0x50 + (x)) +#define TIN_SHUTDOWN_VIN_LIMIT_HI_REG(x) EC_PAGE_REG(3, 0x70 + 2*(x)) +#define TIN_SHUTDOWN_VIN_LIMIT_LO_REG(x) EC_PAGE_REG(3, 0x71 + 2*(x)) + +#define FAN_RPM_INT_EN1_REG EC_PAGE_REG(3, 0xb0) +#define FAN_RPM_INT_EN2_REG EC_PAGE_REG(3, 0xb1) + +#define FAN_RPM_LIMIT_HI_REG(fan) EC_PAGE_REG(3, 0xb8 + 2*(fan)) +#define FAN_RPM_LIMIT_LO_REG(fan) EC_PAGE_REG(3, 0xb9 + 2*(fan)) + +/* EC Page 4 - SMBus */ + +#define PCH_ERR_STS_REG EC_PAGE_REG(4, 0x00) +#define TSI_ERR_STS_REG EC_PAGE_REG(4, 0x01) +#define SMBUS_MASTER_ERR_STS_REG EC_PAGE_REG(4, 0x04) +#define SMBUS_THERM_SENSOR_ERR_STS_REG(x) EC_PAGE_REG(4, 0x06 + (x)) +#define SMBUS_DIMM_SENSOR_ERR_STS_REG(x) EC_PAGE_REG(4, 0x0c + (x)) + +#define PCH_THERMAL_DATA_CFG_REG EC_PAGE_REG(4, 0x10) +#define PCH_BAUD_SEL_MASK (7 << 0) +#define PCH_BAUD_12_5K (0 << 0) +#define PCH_BAUD_25K (1 << 0) +#define PCH_BAUD_50K (2 << 0) +#define PCH_BAUD_100K (3 << 0) +#define PCH_BAUD_200K (4 << 0) +#define PCH_BAUD_400K (5 << 0) +#define PCH_BAUD_800K (6 << 0) +#define PCH_BAUD_1200K (7 << 0) +#define PCH_PORT_SEL_MASK (3 << 4) +#define PCH_THERMAL_PORT(x) ((x) << 4) +#define PCH_ONE_BYTE_REPORT (1 << 7) + +#define PCH_DEVICE_ADDR_REG EC_PAGE_REG(4, 0x11) +#define PCH_THERMAL_CMD_REG EC_PAGE_REG(4, 0x12) + +#define TSI_THERMAL_DATA_CFG_REG EC_PAGE_REG(4, 0x14) +#define TSI_BAUD_SEL_MASK (7 << 0) +#define TSI_BAUD_12_5K (0 << 0) +#define TSI_BAUD_25K (1 << 0) +#define TSI_BAUD_50K (2 << 0) +#define TSI_BAUD_100K (3 << 0) +#define TSI_BAUD_200K (4 << 0) +#define TSI_BAUD_400K (5 << 0) +#define TSI_BAUD_800K (6 << 0) +#define TSI_BAUD_1200K (7 << 0) +#define TSI_PORT_SEL_MASK (3 << 4) +#define TSI_THERMAL_PORT(x) ((x) << 4) + +#define SMBUS_SENSOR_CFG_REG(x) EC_PAGE_REG(4, 0x1a + 5*(x)) +#define SMB_BAUD_SEL_MASK (7 << 0) +#define SMB_BAUD_12_5K (0 << 0) +#define SMB_BAUD_25K (1 << 0) +#define SMB_BAUD_50K (2 << 0) +#define SMB_BAUD_100K (3 << 0) +#define SMB_BAUD_200K (4 << 0) +#define SMB_BAUD_400K (5 << 0) +#define SMB_BAUD_800K (6 << 0) +#define SMB_BAUD_1200K (7 << 0) +#define SMB_PORT_SEL_MASK (3 << 4) +#define SMB_SENSOR_PORT(x) ((x) << 4) +#define SMB_SENSOR_DATA_LEN_1B (0 << 6) +#define SMB_SENSOR_DATA_LEN_2B (1 << 6) +#define SMB_SENSOR_DIRECT_ACCESS (1 << 7) + +#define SMBUS_SENSOR_ADDR_REG(x) EC_PAGE_REG(4, 0x1b + 5*(x)) +#define SMBUS_SENSOR_CMD_REG(x) EC_PAGE_REG(4, 0x1c + 5*(x)) +#define SMBUS_SENSOR_DATA_REG(x) EC_PAGE_REG(4, 0x1d + 5*(x)) +#define SMBUS_SENSOR_READ_CMD_REG(x) EC_PAGE_REG(4, 0x1e + 5*(x)) + +#define SMBUS_DIMM_SENSOR_CFG0(x) EC_PAGE_REG(4, 0x3a + 4*(x)) +#define SMB_DIMM_ADDR_MASK 0x07 +#define SMB_DIMM_BAUD_SEL_MASK (7 << 4) +#define SMB_DIMM_BAUD_12_5K (0 << 0) +#define SMB_DIMM_BAUD_25K (1 << 0) +#define SMB_DIMM_BAUD_50K (2 << 0) +#define SMB_DIMM_BAUD_100K (3 << 0) +#define SMB_DIMM_BAUD_200K (4 << 0) +#define SMB_DIMM_BAUD_400K (5 << 0) +#define SMB_DIMM_BAUD_800K (6 << 0) +#define SMB_DIMM_BAUD_1200K (7 << 0) +#define SMBUS_DIMM_SENSOR_EN (1 << 7) + +#define SMBUS_DIMM_SENSOR_CFG1_REG(x) EC_PAGE_REG(4, 0x3b + 4*(x)) +/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */ +#define SMD_DIMM_ADDR_MASK 0x07 +#define SMB_PORT_SEL_MASK (3 << 4) +#define SMB_SENSOR_PORT(x) ((x) << 4) + +#define SMBUS_DIMM_SENSOR_CFG2_REG(x) EC_PAGE_REG(4, 0x3c + 4*(x)) +/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */ + +#define SMBUS_DIMM_SENSOR_CFG3_REG(x) EC_PAGE_REG(4, 0x3d + 4*(x)) +/* Bits 0-2 is address as in CFG0, bit 7 is DIMM sensor enable */ + +#define SMBUS_MASTER_CFG1_REG EC_PAGE_REG(4, 0x60) +#define SMB_MASTER_POLLRATE_MASK 0x07 +#define SMB_MASTER_POLLRATE_ONCE (0 << 0) +#define SMB_MASTER_POLLRATE_100MS (0 << 0) +#define SMB_MASTER_POLLRATE_200MS (0 << 0) +#define SMB_MASTER_POLLRATE_400MS (0 << 0) +#define SMB_MASTER_POLLRATE_800MS (0 << 0) +#define SMB_MASTER_POLLRATE_1S (0 << 0) +#define SMB_MASTER_POLLRATE_2S (0 << 0) +#define SMB_MASTER_POLLRATE_4S (0 << 0) +#define SMB_MASTER_CLEAR_BUF (1 << 3) +#define SMB_MASTER_HOLD_RDY (1 << 5) +#define SMB_MASTER_START (1 << 6) +#define SMB_MASTER_EN (1 << 7) + +#define SMBUS_MASTER_CFG2_REG EC_PAGE_REG(4, 0x61) +#define SMB_MASTER_PORT_SEL_MASK 0x03 +#define SMB_MASTER_PORT(x) ((x) << 0) +#define SMB_MASTER_PEC_EN (1 << 3) + +#define SMBUS_MASTER_BAUD_RATE_SEL_REG EC_PAGE_REG(4, 0x62) +#define SMB_MASTER_BAUD_SEL_MASK (7 << 4) +#define SMB_MASTER_BAUD_12_5K (0 << 0) +#define SMB_MASTER_BAUD_25K (1 << 0) +#define SMB_MASTER_BAUD_50K (2 << 0) +#define SMB_MASTER_BAUD_100K (3 << 0) +#define SMB_MASTER_BAUD_200K (4 << 0) +#define SMB_MASTER_BAUD_400K (5 << 0) +#define SMB_MASTER_BAUD_800K (6 << 0) +#define SMB_MASTER_BAUD_1200K (7 << 0) + +#define SMBUS_MASTER_PROTOCOL_SEL_REG EC_PAGE_REG(4, 0x63) +#define SMBUS_MASTER_QUICK_WRITE 0x00 +#define SMBUS_MASTER_SEND_BYTE 0x01 +#define SMBUS_MASTER_WRITE_BYTE 0x02 +#define SMBUS_MASTER_WRITE_WORD 0x03 +#define SMBUS_MASTER_BLOCK_WRITE 0x04 +#define SMBUS_MASTER_PROCESS_CALL 0x05 +#define SMBUS_MASTER_BLOCK_WRITE_READ 0x06 +#define SMBUS_MASTER_RECEIVE_BYTE 0x81 +#define SMBUS_MASTER_READ_BYTE 0x82 +#define SMBUS_MASTER_READ_WORD 0x83 +#define SMBUS_MASTER_BLOCK_READ 0x84 + +#define SMBUS_MASTER_BLOCK_WR_LEN_REG EC_PAGE_REG(4, 0x64) +#define SMBUS_MASTER_DEV_ADDR_REG EC_PAGE_REG(4, 0x65) +#define SMBUS_MASTER_CMD_REG EC_PAGE_REG(4, 0x66) + +#define SMBUS_MASTER_WRITE_BUFFER(x) EC_PAGE_REG(4, 0x70 + (x)) +#define SMBUS_MASTER_WRITE_BUFFER_LEN 64 +#define SMBUS_MASTER_READ_BUFFER(x) EC_PAGE_REG(4, 0xb0 + (x)) +#define SMBUS_MASTER_READ_BUFFER_LEN 64 + +/* EC page 5 - PECI */ + +#define PECI_PING_INFO_REG EC_PAGE_REG(5, 0x00) +#define PECI_AGENT_ALIVE(agent) (1 << (agent)) +#define PECI_OVER_SMBUS (1 << 7) + +#define PECI_INFO_STS_REG EC_PAGE_REG(5, 0x01) +#define PECI_AGENT_INFO_RDY(agent) (1 << (agent)) + +#define PECI_DEVICE_INFO_REG EC_PAGE_REG(5, 0x02) +#define PECI_AGENT_TWO_DOMAIN_SUPPORT (1 << 2) + +#define PECI_REVISION_INFO_REG EC_PAGE_REG(5, 0x03) +#define PECI_REV_MINOR_MASK 0x0f +#define PECI_REV_MINOR_SHIFT 0 +#define PECI_REV_MAJOR_MASK 0xf0 +#define PECI_REV_MAJOR_SHIFT 4 + +#define PECI_DOM0_MARGIN_HI_REG(agent) EC_PAGE_REG(5, 0x20 + 2*(agent)) +#define PECI_DOM0_MARGIN_LO_REG(agent) EC_PAGE_REG(5, 0x21 + 2*(agent)) +#define PECI_DOM1_MARGIN_HI_REG(agent) EC_PAGE_REG(5, 0x28 + 2*(agent)) +#define PECI_DOM1_MARGIN_LO_REG(agent) EC_PAGE_REG(5, 0x29 + 2*(agent)) + +#define PECI_DOM0_TEMP_HI_REG(agent) EC_PAGE_REG(5, 0x30 + 2*(agent)) +#define PECI_DOM0_TEMP_LO_REG(agent) EC_PAGE_REG(5, 0x31 + 2*(agent)) +#define PECI_DOM1_TEMP_HI_REG(agent) EC_PAGE_REG(5, 0x38 + 2*(agent)) +#define PECI_DOM1_TEMP_LO_REG(agent) EC_PAGE_REG(5, 0x39 + 2*(agent)) + +#define PECI_TCONTROL_REG(dom, agent) EC_PAGE_REG(5, 0x40 + 4*(dom) + (agent)) +#define PECI_TJMAX_REG(dom, agent) EC_PAGE_REG(5, 0x48 + 4*(dom) + (agent)) + +#define PECI_PCS_ERR_STS_REG EC_PAGE_REG(5, 0x52) +#define PECI_MASTER_ERR_STS_REG EC_PAGE_REG(5, 0x53) + +#define PECI_CFG_REG EC_PAGE_REG(5, 0x60) +#define PECI_SPEED_SEL_MASK (3 << 0) +#define PECI_SPEED_2MHZ (0 << 0) +#define PECI_SPEED_1_2MHZ (1 << 0) +#define PECI_SPEED_800KHZ (2 << 0) +#define PECI_SPEED_400KHZ (3 << 0) +#define PECI_USER_TJMAX_FROM_CPU (0 << 5) +#define PECI_USER_TJMAX_FROM_EC (1 << 5) +#define PECI_AGENT_INIT (1 << 6) +#define PECI_EN (1 << 7) + +#define PECI_AGENT_EN_REG EC_PAGE_REG(5, 0x61) +#define PECI_AGENT_EN_MASK 0xf +#define PECI_AGENT_EN(agent) (1 << (agent)) + +#define PECI_HOSTID_REG EC_PAGE_REG(5, 0x62) +#define PECI_ERR_RETRY_CFG_REG EC_PAGE_REG(5, 0x63) +#define PECI_MARGIN_CFG_REG EC_PAGE_REG(5, 0x64) +#define PECI_MARGIN_POLLRATE_MASK 0x07 +#define PECI_MARGIN_POLLRATE_ONCE (0 << 0) +#define PECI_MARGIN_POLLRATE_100MS (1 << 0) +#define PECI_MARGIN_POLLRATE_200MS (2 << 0) +#define PECI_MARGIN_POLLRATE_400MS (3 << 0) +#define PECI_MARGIN_POLLRATE_800MS (4 << 0) +#define PECI_MARGIN_POLLRATE_1S (5 << 0) +#define PECI_MARGIN_POLLRATE_2S (6 << 0) +#define PECI_MARGIN_POLLRATE_4S (7 << 0) +#define PECI_GET_MARGIN_EN (1 << 7) + +#define PECI_USER_TJMAX_REG(dom, agent) EC_PAGE_REG(5, 0x68 + 4*(dom) + (agent)) +#define PECI_PCS_CFG_REG 0x70 +#define PECI_PCS_POLLRATE_MASK 0x07 +#define PECI_PCS_POLLRATE_ONCE (0 << 0) +#define PECI_PCS_POLLRATE_100MS (1 << 0) +#define PECI_PCS_POLLRATE_200MS (2 << 0) +#define PECI_PCS_POLLRATE_400MS (3 << 0) +#define PECI_PCS_POLLRATE_800MS (4 << 0) +#define PECI_PCS_POLLRATE_1S (5 << 0) +#define PECI_PCS_POLLRATE_2S (6 << 0) +#define PECI_PCS_POLLRATE_4S (7 << 0) +#define PECI_PCS_STOP_ERR (1 << 4) +#define PECI_PCS_HOLD_RDY (1 << 5) +#define PECI_PCS_START (1 << 6) +#define PECI_PCS_EN (1 << 7) + +#define PECI_PCS_CFG2_REG EC_PAGE_REG(5, 0x71) +#define PECI_PCS_AGENT_SEL_MASK 0x03 +#define PECI_PCS_SEL_DOM0 (0 << 4) +#define PECI_PCS_SEL_DOM1 (1 << 4) +#define PECI_PCS_WRITE_PKG_CFG (1 << 7) + +#define PECI_PCS_IDX_REG EC_PAGE_REG(5, 0x72) +#define PECI_PCS_PARAM_LO_REG EC_PAGE_REG(5, 0x73) +#define PECI_PCS_PARAM_HI_REG EC_PAGE_REG(5, 0x74) + +#define PECI_PCS_COMPLETION_CODE_REG EC_PAGE_REG(5, 0x75) +#define PECI_PCS_DATA_VALID 0x40 +#define PECI_PCS_RESP_TIMEOUT_RETRY 0x80 +#define PECI_PCS_RESP_TIMEOUT 0x81 +#define PECI_PCS_INVALID_REQUEST 0x90 +#define PECI_PCS_PECI_CONTROL_HW 0x91 + +#define PECI_PCS_BUF_REG(x) EC_PAGE_REG(5, 0x76 + (x)) +#define PECI_PCS_BUF_LEN 4 + +#define PECI_MASTER_CFG_REG EC_PAGE_REG(5, 0x7a) +#define PECI_MASTER_POLLRATE_MASK 0x07 +#define PECI_MASTER_POLLRATE_ONCE (0 << 0) +#define PECI_MASTER_POLLRATE_100MS (1 << 0) +#define PECI_MASTER_POLLRATE_200MS (2 << 0) +#define PECI_MASTER_POLLRATE_400MS (3 << 0) +#define PECI_MASTER_POLLRATE_800MS (4 << 0) +#define PECI_MASTER_POLLRATE_1S (5 << 0) +#define PECI_MASTER_POLLRATE_2S (6 << 0) +#define PECI_MASTER_POLLRATE_4S (7 << 0) +#define PECI_MASTER_STOP_ERR (1 << 4) +#define PECI_MASTER_HOLD_RDY (1 << 5) +#define PECI_MASTER_START (1 << 6) +#define PECI_MASTER_EN (1 << 7) + +#define PECI_MASTER_CFG2_REG EC_PAGE_REG(5, 0x7b) +#define PECI_MASTER_CPL_CODE_SUPP (1 << 6) +#define PECI_MASTER_AWFCS_EN (1 << 7) + +#define PECI_MASTER_CLIENT_ADDR_REG EC_PAGE_REG(5, 0x7c) +#define PECI_MASTER_CMD_CODE_REG EC_PAGE_REG(5, 0x7d) +#define PECI_MASTER_WRITE_LEN_REG EC_PAGE_REG(5, 0x7e) +#define PECI_MASTER_READ_LEN_REG EC_PAGE_REG(5, 0x7f) + +#define PECI_MASTER_WRITE_BUF(x) EC_PAGE_REG(5, 0x80 + (x)) +#define PECI_MASTER_WRITE_BUF_LEN 12 +#define PECI_MASTER_READ_BUF(x) EC_PAGE_REG(5, 0x90 + (x)) +#define PECI_MASTER_READ_BUF_LEN 12 + +#define PECI_DRAM_TEMP_WR_STS_REG(x) EC_PAGE_REG(5, 0xa0 + (x)) +#define PECI_DIMM_AMB_TEMP_WR_STS_REG(x) EC_PAGE_REG(5, 0xa4 + (x)) +#define PECI_DIMM_TEMP_RD_STS_REG(x) EC_PAGE_REG(5, 0xa8 + (x)) +#define PECI_ACC_ENERGRY_RD_STS_REG(x) EC_PAGE_REG(5, 0xac + (x)) + +#define PECI_DRAM_TEMP_WR_POLL_RATE_REG EC_PAGE_REG(5, 0xb0) +#define PECI_DRAM_POLLRATE_MASK 0x07 +#define PECI_DRAM_POLLRATE_ONCE (0 << 0) +#define PECI_DRAM_POLLRATE_100MS (1 << 0) +#define PECI_DRAM_POLLRATE_200MS (2 << 0) +#define PECI_DRAM_POLLRATE_400MS (3 << 0) +#define PECI_DRAM_POLLRATE_800MS (4 << 0) +#define PECI_DRAM_POLLRATE_1S (5 << 0) +#define PECI_DRAM_POLLRATE_2S (6 << 0) +#define PECI_DRAM_POLLRATE_4S (7 << 0) + +#define PECI_DIMM_AMB_TEMP_WR_POLL_RATE_REG EC_PAGE_REG(5, 0xb1) +#define PECI_DIMM_AMB_POLLRATE_MASK 0x07 +#define PECI_DIMM_AMB_POLLRATE_ONCE (0 << 0) +#define PECI_DIMM_AMB_POLLRATE_100MS (1 << 0) +#define PECI_DIMM_AMB_POLLRATE_200MS (2 << 0) +#define PECI_DIMM_AMB_POLLRATE_400MS (3 << 0) +#define PECI_DIMM_AMB_POLLRATE_800MS (4 << 0) +#define PECI_DIMM_AMB_POLLRATE_1S (5 << 0) +#define PECI_DIMM_AMB_POLLRATE_2S (6 << 0) +#define PECI_DIMM_AMB_POLLRATE_4S (7 << 0) + +#define PECI_ACC_ENERGRY_RD_POLL_RATE_REG EC_PAGE_REG(5, 0xb2) +#define PECI_ACC_ENERGRY_RD_POLLRATE_MASK 0x07 +#define PECI_ACC_ENERGRY_RD_POLLRATE_ONCE (0 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_100MS (1 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_200MS (2 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_400MS (3 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_800MS (4 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_1S (5 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_2S (6 << 0) +#define PECI_ACC_ENERGRY_RD_POLLRATE_4S (7 << 0) + +#define PECI_DRAM_TEMP_WR_CFG1_REG(x) EC_PAGE_REG(5, 0xb8 + 2*(x)) +#define PECI_DRAM_TEMP_WR_CH_IDX_MASK (7 << 0) +#define PECI_DRAM_TEMP_WR_CH_IDX_SHIFT 0 +#define PECI_DRAM_TEMP_WR_DIMM_IDX_MASK (7 << 3) +#define PECI_DRAM_TEMP_WR_DIMM_IDX_SHIFT 3 +#define PECI_DRAM_TEMP_WR_POLLING (1 << 6) +#define PECI_DRAM_TEMP_WR_START (1 << 7) + +#define PECI_DRAM_TEMP_WR_CFG2_REG(x) EC_PAGE_REG(5, 0xb9 + 2*(x)) +#define PECI_DRAM_TEMP_WR_AGENT_IDX_MASK (3 << 1) +#define PECI_DRAM_TEMP_WR_AGENT_IDX_SHIFT 1 +#define PECI_DRAM_TEMP_WR_DOM0 (0 << 6) +#define PECI_DRAM_TEMP_WR_DOM1 (1 << 6) +#define PECI_DRAM_TEMP_WR_CH_SEL (1 << 7) + +#define PECI_DIMM_AMB_TEMP_WR_CFG1_REG(x) EC_PAGE_REG(5, 0xc0 + 2*(x)) +#define PECI_DIMM_AMB_TEMP_WR_CH_IDX_MASK (7 << 0) +#define PECI_DIMM_AMB_TEMP_WR_CH_IDX_SHIFT 0 +#define PECI_DIMM_AMB_TEMP_WR_POLLING (1 << 6) +#define PECI_DIMM_AMB_TEMP_WR_START (1 << 7) + +#define PECI_DIMM_AMB_TEMP_WR_CFG2_REG(x) EC_PAGE_REG(5, 0xc1 + 2*(x)) +#define PECI_DIMM_AMB_TEMP_WR_AGENT_IDX_MASK (3 << 1) +#define PECI_DIMM_AMB_TEMP_WR_AGENT_IDX_SHIFT 1 +#define PECI_DIMM_AMB_TEMP_WR_DOM0 (0 << 6) +#define PECI_DIMM_AMB_TEMP_WR_DOM1 (1 << 6) +#define PECI_DIMM_AMB_TEMP_WR_CH_SEL (1 << 7) + +#define PECI_DIMM_TEMP_RD_CFG1_REG(x) EC_PAGE_REG(5, 0xc8 + (x)) +#define PECI_DIMM_TEMP_RD_AGENT_IDX_MASK (3 << 0) +#define PECI_DIMM_TEMP_RD_AGENT_IDX_SHIFT 0 +#define PECI_DIMM_TEMP_RD_DOM0 (0 << 2) +#define PECI_DIMM_TEMP_RD_DOM1 (1 << 2) +#define PECI_DIMM_TEMP_RD_DIMM_SEL_MASK (3 << 4) +#define PECI_DIMM_TEMP_RD_DIMM0 (0 << 4) +#define PECI_DIMM_TEMP_RD_DIMM1 (1 << 4) +#define PECI_DIMM_TEMP_RD_DIMM0_MAX (2 << 4) +#define PECI_DIMM_TEMP_RD_DIMM1_MAX (3 << 4) +#define PECI_DIMM_TEMP_RD_DIMM_CH0 (0 << 6) +#define PECI_DIMM_TEMP_RD_DIMM_CH1 (1 << 6) + +#define PECI_ACC_ENERGRY_RD_CFG_REG(x) EC_PAGE_REG(5, 0xcc + (x)) +#define PECI_ACC_ENERGRY_RD_AGENT_IDX_MASK (3 << 0) +#define PECI_ACC_ENERGRY_RD_AGENT_IDX_SHIFT 0 +#define PECI_ACC_ENERGRY_RD_DOM0 (0 << 2) +#define PECI_ACC_ENERGRY_RD_DOM1 (1 << 2) +#define PECI_ACC_ENERGRY_RD_REPORT_CURR (0 << 3) +#define PECI_ACC_ENERGRY_RD_REPORT_INCR (1 << 3) +#define PECI_DIMM_TEMP_RD_PWR_PLANE_SEL_MASK (3 << 4) +#define PECI_DIMM_TEMP_RD_PWR_PLANE0 (0 << 4) +#define PECI_DIMM_TEMP_RD_PWR_PLANE1 (1 << 4) +#define PECI_DIMM_TEMP_RD_PKG_PWR_PLANE0 (2 << 4) +#define PECI_DIMM_TEMP_RD_PKG_PWR_PLANE1 (3 << 4) +#define PECI_ACC_ENERGRY_RD_POLLING (1 << 6) +#define PECI_ACC_ENERGRY_RD_START (1 << 7) + +#define PECI_ACC_ENERGRY_RD_VAL_B0_REG(x) EC_PAGE_REG(5, 0xd0 + 4*(x)) +#define PECI_ACC_ENERGRY_RD_VAL_B1_REG(x) EC_PAGE_REG(5, 0xd1 + 4*(x)) +#define PECI_ACC_ENERGRY_RD_VAL_B2_REG(x) EC_PAGE_REG(5, 0xd2 + 4*(x)) +#define PECI_ACC_ENERGRY_RD_VAL_B3_REG(x) EC_PAGE_REG(5, 0xd3 + 4*(x)) + +/* EC Page 6 - EC FW Information and Configuration */ + +#define CHIP_ID0_REG EC_PAGE_REG(6, 0x00) +#define CHIP_ID1_REG EC_PAGE_REG(6, 0x01) +#define CUSTOMER_ID0_REG EC_PAGE_REG(6, 0x02) +#define CUSTOMER_ID1_REG EC_PAGE_REG(6, 0x03) +#define FW_BUILD_YEAR_REG EC_PAGE_REG(6, 0x04) +#define FW_BUILD_MONTH_REG EC_PAGE_REG(6, 0x05) +#define FW_BUILD_DAY_REG EC_PAGE_REG(6, 0x06) +#define FW_BUILD_SERIALNUM_REG EC_PAGE_REG(6, 0x07) +#define FW_VER0_REG EC_PAGE_REG(6, 0x08) +#define FW_VER1_REG EC_PAGE_REG(6, 0x09) +#define PROFILE_VER_REG EC_PAGE_REG(6, 0x0a) +#define ROM_VER0_REG EC_PAGE_REG(6, 0x0c) +#define ROM_VER1_REG EC_PAGE_REG(6, 0x0d) +#define ROM_VER2_REG EC_PAGE_REG(6, 0x0e) +#define ROM_VER3_REG EC_PAGE_REG(6, 0x0f) +#define ISP_BUILD_YEAR_REG EC_PAGE_REG(6, 0x12) +#define ISP_BUILD_MONTH_REG EC_PAGE_REG(6, 0x13) +#define ISP_BUILD_DAY_REG EC_PAGE_REG(6, 0x14) +#define ISP_BUILD_SERIALNUM_REG EC_PAGE_REG(6, 0x15) +#define ISP_VER0_REG EC_PAGE_REG(6, 0x16) +#define ISP_VER1_REG EC_PAGE_REG(6, 0x17) + +#define OEM_VER_REG EC_PAGE_REG(6, 0x18) +#define OEM_VER_LEN 8 + +#define EC_ALIVE_COUNTER_REG EC_PAGE_REG(6, 0x20) + +#define EC_HEARTBEAT_CFG_REG EC_PAGE_REG(6, 0x2e) +#define EC_HEARBEAT_TOGGLE_RATE_MASK 0x0f +#define EC_HEARBEAT_TYPE_OD (0 << 6) +#define EC_HEARBEAT_TYPE_PP (1 << 6) +#define EC_HEARBEAT_EN (1 << 7) + +#define EC_HEARTBEAT_GPSEL_REG EC_PAGE_REG(6, 0x2f) +#define EC_HEARBEAT_GPIO_PIN_MASK 0x0f +#define EC_HEARBEAT_GPIO_PIN_SHIFT 0 +#define EC_HEARBEAT_GPIO_GROUP_MASK 0xf0 +#define EC_HEARBEAT_GPIO_GROUP_SHIFT 4 + +#define EC_MCU_SPEED_REG EC_PAGE_REG(6, 0x38) +#define EC_MCU_SPEED_MCLK_MASK 0x0f +#define EC_MCU_SPEED_MCLK_10KHZ (0 << 0) +#define EC_MCU_SPEED_MCLK_160KHZ (1 << 0) +#define EC_MCU_SPEED_MCLK_1MHZ (2 << 0) +#define EC_MCU_SPEED_MCLK_4MHZ (3 << 0) +#define EC_MCU_SPEED_MCLK_8MHZ (4 << 0) +#define EC_MCU_SPEED_MCLK_16MHZ (5 << 0) +#define EC_MCU_SPEED_MCLK_24MHZ (6 << 0) +#define EC_MCU_SPEED_MCLK_48MHZ (7 << 0) +#define EC_MCU_CACHE_EN (1 << 6) + +#define EC_FLASH_SPEED_REG EC_PAGE_REG(6, 0x39) +#define EC_FLASH_CLK_DIV_MASK (3 << 4) +#define EC_FLASH_CLK_DIV_1 (0 << 4) +#define EC_FLASH_CLK_DIV_2 (1 << 4) +#define EC_FLASH_CLK_DIV_4 (2 << 4) +#define EC_FLASH_CLK_DIV_16 (3 << 4) +#define EC_FLASH_FETCH_MODE_MASK (3 << 6) +#define EC_FLASH_FETCH_MODE_READ (0 << 6) +#define EC_FLASH_FETCH_MODE_FAST_READ (1 << 6) +#define EC_FLASH_FETCH_MODE_DUAL_OUT (2 << 6) +#define EC_FLASH_FETCH_MODE_DUAL_IN_OUT (3 << 6) + +#define EC_FLASH_MANUFACTURE_REG EC_PAGE_REG(6, 0x3a) +#define EC_FLASH_MEMORY_TYPE_REG EC_PAGE_REG(6, 0x3b) +#define EC_FLASH_CAPACITY_REG EC_PAGE_REG(6, 0x3c) + +#define EC_MCU_SPEED_CTL_VSB_REG EC_PAGE_REG(6, 0x40) +#define EC_FLASH_CLK_VSB_DIV_MASK (3 << 0) +#define EC_FLASH_CLK_VSB_DIV_1 (0 << 0) +#define EC_FLASH_CLK_VSB_DIV_2 (1 << 0) +#define EC_FLASH_CLK_VSB_DIV_4 (2 << 0) +#define EC_FLASH_CLK_VSB_DIV_16 (3 << 0) +#define EC_FLASH_FETCH_MODE_VSB_MASK (3 << 2) +#define EC_FLASH_FETCH_MODE_VSB_READ (0 << 2) +#define EC_FLASH_FETCH_MODE_VSB_FAST_READ (1 << 2) +#define EC_FLASH_FETCH_MODE_VSB_DUAL_OUT (2 << 2) +#define EC_FLASH_FETCH_MODE_VSB_DUAL_IN_OUT (3 << 2) +#define EC_MCU_SPEED_MCLK_VSB_MASK (3 << 4) +#define EC_MCU_SPEED_MCLK_VSB_1MHZ (0 << 4) +#define EC_MCU_SPEED_MCLK_VSB_4MHZ (1 << 4) +#define EC_MCU_SPEED_MCLK_VSB_24MHZ (2 << 4) +#define EC_MCU_SPEED_MCLK_VSB_48MHZ (3 << 4) +#define EC_MCU_CACHE_VSB_EN (1 << 6) + +#define EC_MCU_SPEED_CTL_VCC_REG EC_PAGE_REG(6, 0x42) +#define EC_MCU_SPEED_MCLK_VCC_MASK 0x0f +#define EC_MCU_SPEED_MCLK_VCC_10KHZ (0 << 0) +#define EC_MCU_SPEED_MCLK_VCC_160KHZ (1 << 0) +#define EC_MCU_SPEED_MCLK_VCC_1MHZ (2 << 0) +#define EC_MCU_SPEED_MCLK_VCC_4MHZ (3 << 0) +#define EC_MCU_SPEED_MCLK_VCC_8MHZ (4 << 0) +#define EC_MCU_SPEED_MCLK_VCC_16MHZ (5 << 0) +#define EC_MCU_SPEED_MCLK_VCC_24MHZ (6 << 0) +#define EC_MCU_SPEED_MCLK_VCC_48MHZ (7 << 0) +#define EC_MCU_CACHE_VCC_EN (1 << 6) +#define EC_MCU_SPEED_VCC_LOAD_CFG (1 << 7) + +#define EC_FLASH_SPEED_CTL_VCC_REG EC_PAGE_REG(6, 0x43) +#define EC_FLASH_CLK_VCC_DIV_MASK (3 << 2) +#define EC_FLASH_CLK_VCC_DIV_1 (0 << 2) +#define EC_FLASH_CLK_VCC_DIV_2 (1 << 2) +#define EC_FLASH_CLK_VCC_DIV_4 (2 << 2) +#define EC_FLASH_CLK_VCC_DIV_16 (3 << 2) +#define EC_FLASH_FETCH_MODE_VCC_MASK (3 << 4) +#define EC_FLASH_FETCH_MODE_VCC_READ (0 << 4) +#define EC_FLASH_FETCH_MODE_VCC_FAST_READ (1 << 4) +#define EC_FLASH_FETCH_MODE_VCC_DUAL_OUT (2 << 4) +#define EC_FLASH_FETCH_MODE_VCC_DUAL_IN_OUT (3 << 4) +#define EC_FLASH_SPEED_VCC_LOAD_CFG (1 << 7) + +#define EC_FLASH_WREN_CMD_REG EC_PAGE_REG(6, 0x47) + +#define EC_FLASH_WRITE_LOCK_REG EC_PAGE_REG(6, 0x4f) +#define EC_FLASH_WRITE_LOCK (1 << 0) +#define EC_FLASH_WRITE_LOCK_EN (1 << 7) + +/* EC Page 8 - NCT6687D specific, not present in NCT6686D */ + +#define FAN9_FAN10_MANUAL_EN_REG EC_PAGE_REG(8, 0x0f) + +#define FAN_STEP_UP_TIME_REG(fan) EC_PAGE_REG(8, 0x1a + ((fan) - 1)) +#define FAN_STEP_DOWN_TIME_REG(fan) EC_PAGE_REG(8, 0x24 + ((fan) - 1)) + +/* These are also included in macros in page 1, 10 and 12 */ +#define FAN9_FUNCTION_CTL_REG EC_PAGE_REG(8, 0xe0) +#define FAN10_FUNCTION_CTL_REG EC_PAGE_REG(8, 0xe1) +#define FAN9_MANUAL_OUTPUT_VAL_REG EC_PAGE_REG(8, 0xe8) +#define FAN10_MANUAL_OUTPUT_VAL_REG EC_PAGE_REG(8, 0xe9) +#define FAN9_DUTY_REG EC_PAGE_REG(8, 0xf0) +#define FAN10_DUTY_REG EC_PAGE_REG(8, 0xf1) +#define FAN9OUT_CFG_REG EC_PAGE_REG(8, 0xf4) +#define FAN10OUT_CFG_REG EC_PAGE_REG(8, 0xf5) + +/* EC Page 9 - Fan Algorithm Function Control */ + +#define FAN_ALG_FUNCTRL_REG(fan) EC_PAGE_REG(9, 0x00 + ((fan) - 1)) +#define FAN_ALG_FUNCTRL_DTS_UB_EN (1 << 2) +#define FAN_ALG_FUNCTRL_DTS2_EN (1 << 3) +#define FAN_ALG_FUNCTRL_DTS1_EN (1 << 4) +#define FAN_ALG_FUNCTRL_TEMP_ERR (1 << 5) +#define FAN_ALG_FUNCTRL_CRIT_TEMP_EN (1 << 6) +#define FAN_ALG_FUNCTRL_ALG_EN (1 << 7) + +/* Main temperature zone decision */ +#define FAN_MTZ_DCS_DATA_REG(x, fan) EC_PAGE_REG(9, 0x10 + (x) + 4*((fan) - 1)) +/* Ambient temperature zone decision */ +#define FAN_ATZ_DCS_DATA_REG(x, fan) EC_PAGE_REG(9, 0x50 + (x) 4*((fan) - 1)) + +#define FAN_INITIAL_VALUE_REG(fan) EC_PAGE_REG(9, 0x90 + ((fan) - 1)) +#define FAN_CRIT_TEMP_CFG_REG(fan) EC_PAGE_REG(9, 0xA0 + ((fan) - 1)) +#define FAN_CRIT_TEMP_TOLERANCE_REG(fan) EC_PAGE_REG(9, 0xB0 + ((fan) - 1)) +#define FAN_TEMP_ERR_DUTY_VAL_REG(fan) EC_PAGE_REG(9, 0xC0 + ((fan) - 1)) + +#define FAN_MODE_SEL_REG(fan) EC_PAGE_REG(9, 0xD0 + ((fan) - 1)) +#define FAN_MODE_SEL_MASK 0xf +#define FAN_MODE_MODE_MANUAL (0 << 0) +#define FAN_MODE_THERMAL_CRUISE (1 << 0) +#define FAN_MODE_SPEED_CRUISE (2 << 0) +#define FAN_MODE_SMART_FAN_IV (3 << 0) +#define FAN_MODE_PID_CONTROL (4 << 0) + +/* EC Page 10 - Fan Function Control & Weight Matrix */ + +#define FAN_MANUAL_EN_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0x0f) \ + : EC_PAGE_REG(10, 0x00)) +#define FAN_MANUAL_EN(fan) (1 << (((fan) - 1) % 8)) + +#define FAN_CFG_CTRL_REG EC_PAGE_REG(10, 0x01) +#define FAN_CFG_DONE (1 << 6) +#define FAN_CFG_REQUEST (1 << 7) + +#define FAN_FUNCTION_CTRL(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0xe0 + ((fan) - 9)) \ + : EC_PAGE_REG(10, 0x08 + ((fan) - 1))) +#define FAN_FUN_MINDUTY_EN (1 << 0) +#define FAN_FUN_MANUAL_OFFSET_EN (1 << 1) +#define FAN_FUN_STARTUP_EN (1 << 2) +#define FAN_FUN_AMBIENT_FLOOR_EN (1 << 3) +#define FAN_FUN_MARKUP_TRACK_EN (1 << 4) +#define FAN_FUN_FAST_TRACK_EN (1 << 5) +#define FAN_FUN_SMART_TRACK_EN (1 << 6) +#define FAN_FUN_UNIT_PWM_DUTY (0 << 7) +#define FAN_FUN_UNIT_RPM (1 << 7) + +/* The unit for below Ambient Floor register is 100 RPM */ +#define FAN_AMB_FLOOR_RPM_TO_REG(rpm) ((rpm) ? (rpm) / 100 : 1) +#define FAN_AMB_FLOOR_MIN_OUT_START_REG(fan) EC_PAGE_REG(10, 0x10 + ((fan) - 1)) +#define FAN_AMB_FLOOR_MIN_OUT_END_REG(fan) EC_PAGE_REG(10, 0x18 + ((fan) - 1)) +#define FAN_AMB_FLOOR_MAX_OUT_REG(fan) EC_PAGE_REG(10, 0x20 + ((fan) - 1)) + +#define FAN_MANUAL_VALUE_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(8, 0xe8 + ((fan) - 9)) \ + : EC_PAGE_REG(10, 0x28 + ((fan) - 1))) + +#define FAN_MANUAL_OFFSET_REG(fan) EC_PAGE_REG(10, 0x30 + ((fan) - 1)) +#define FAN_MIN_DUTY_REG(fan) EC_PAGE_REG(10, 0x38 + ((fan) - 1)) +#define FAN_STARTUP_DUTY_REG(fan) EC_PAGE_REG(10, 0x40 + ((fan) - 1)) + +/* Smart Tracking registers */ + +#define FAN_LOW_RPM_SPEED_BOUNDARY_HI_REG EC_PAGE_REG(10, 0x48) +#define FAN_LOW_RPM_SPEED_BOUNDARY_LO_REG EC_PAGE_REG(10, 0x49) +#define FAN_HIGH_RPM_SPEED_BOUNDARY_HI_REG EC_PAGE_REG(10, 0x4a) +#define FAN_HIGH_RPM_SPEED_BOUNDARY_LO_REG EC_PAGE_REG(10, 0x4b) + +#define FAN_LOW_RPM_TOLERANCE_REG EC_PAGE_REG(10, 0x4c) +#define FAN_MID_RPM_TOLERANCE_REG EC_PAGE_REG(10, 0x4d) +#define FAN_HIGH_RPM_TOLERANCE_REG EC_PAGE_REG(10, 0x4e) + +#define FAN_TRACKING_STEP_REG EC_PAGE_REG(10, 0x4f) +#define FAN_TRACK_STEP_DOWN_MASK 0x0f +#define FAN_TRACK_STEP_DOWN_SHIFT 0 +#define FAN_TRACK_STEP_UP_MASK 0x0f +#define FAN_TRACK_STEP_UP_SHIFT 4 + +#define FAN_FAST_TRACK_TEMP_BOUNDARY_REG EC_PAGE_REG(10, 0x50) + +/* Below definitions are dividers for fast tracking weight registers */ +#define FAN_FAST_TRACK_WEIGHT_DIV_1 1 +#define FAN_FAST_TRACK_WEIGHT_DIV_2 2 +#define FAN_FAST_TRACK_WEIGHT_DIV_4 3 +#define FAN_FAST_TRACK_WEIGHT_DIV_8 4 +#define FAN_FAST_TRACK_WEIGHT_DIV_16 5 +#define FAN_FAST_TRACK_WEIGHT_DIV_32 6 +#define FAN_FAST_TRACK_WEIGHT_DIV_64 7 + +/* Below definitions are shifts and masks for fast tracking weight registers */ +#define FAN_FAST_TRACK_WEIGHT_DOWN_MASK 0x07 +#define FAN_FAST_TRACK_WEIGHT_DOWN_SHIFT 0 +#define FAN_FAST_TRACK_WEIGHT_UP_MASK 0x07 +#define FAN_FAST_TRACK_WEIGHT_UP_SHIFT 4 + +#define FAN_LOW_RPM_FAST_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x51) +#define FAN_MID_RPM_FAST_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x52) +#define FAN_HIGH_RPM_FAST_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x53) + +/* Below definitions are shifts and masks for fast tracking duty step registers */ +#define FAN_FAST_TRACK_DUTY_STEP_MASK 0x0f +#define FAN_FAST_TRACK_DUTY_STEP_SHIFT 0 + +#define FAN_LOW_RPM_FAST_TRACK_DUTY_STEP_REG EC_PAGE_REG(10, 0x54) +#define FAN_MID_RPM_FAST_TRACK_DUTY_STEP_REG EC_PAGE_REG(10, 0x55) +#define FAN_HIGH_RPM_FAST_TRACK_DUTY_STEP_REG EC_PAGE_REG(10, 0x56) + +#define FAN_MARKUP_TRACK_AMB_TEMP_BOUNDARY_REG EC_PAGE_REG(10, 0x57) +#define FAN_MARKUP_TRACK_WEIGHT_REG EC_PAGE_REG(10, 0x58) +#define FAN_MARKUP_TRACK_WEIGHT_MASK 0x07 +#define FAN_MARKUP_TRACK_WEIGHT_SHIFT 0 + +/* Intel Sensor Based (DTS) Fan Control registers */ + +#define ITL_TEMP_START_POINT_REG EC_PAGE_REG(10, 0x59) +#define ITL_TEMP_END_POINT_REG EC_PAGE_REG(10, 0x5a) +#define ITL_AMB_TEMP_START_POINT_REG(x) EC_PAGE_REG(10, 0x5b + (x)) + +#define ITL_RPM_START_POINT_HI_REG(x) EC_PAGE_REG(10, 0x60 + 2*(x)) +#define ITL_RPM_START_POINT_LO_REG(x) EC_PAGE_REG(10, 0x61 + 2*(x)) +#define ITL_RPM_END_POINT_HI_REG(x) EC_PAGE_REG(10, 0x6a + 2*(x)) +#define ITL_RPM_END_POINT_LO_REG(x) EC_PAGE_REG(10, 0x6a + 2*(x)) +#define ITL_RPM_MAX_SPEED_HI_REG EC_PAGE_REG(10, 0x74) +#define ITL_RPM_MAX_SPEED_LO_REG EC_PAGE_REG(10, 0x75) + +#define ITL_DTS_CFG_REG EC_PAGE_REG(10, 0x76) +#define ITL_DTS_PECI_AGENT_IDX_SEL_MASK 0x0f +#define ITL_DTS_PECI_AGENT_IDX_SEL_SHIFT 0 +#define ITL_DTS_PECI_CFG_ADJUSTMENT (1 << 7) + +#define AMBIENT_FLOOR_TEMP_START_POINT_REG EC_PAGE_REG(10, 0x77) +#define AMBIENT_FLOOR_TEMP_END_POINT_REG EC_PAGE_REG(10, 0x78) + +/* DTS 2.0 sensor registers */ + +#define DTS2_TARGET_MARGIN_REG EC_PAGE_REG(10, 0x59) +#define DTS2_TCONTROL_REG EC_PAGE_REG(10, 0x5a) +#define DTS2_TCONTROL_OFFSET_REG EC_PAGE_REG(10, 0x5b) +#define DTS2_TARGET_TOLERANCE_REG EC_PAGE_REG(10, 0x5c) +#define DTS2_DIVISOR_REG EC_PAGE_REG(10, 0x5d) +#define DTS2_STEP_SPEED_HI_REG EC_PAGE_REG(10, 0x5e) +#define DTS2_STEP_SPEED_LO_REG EC_PAGE_REG(10, 0x5f) +#define DTS2_MIN_SPEED_HI_REG EC_PAGE_REG(10, 0x60) +#define DTS2_MIN_SPEED_LO_REG EC_PAGE_REG(10, 0x61) +#define DTS2_DELAY_TIME_COUNTER_REG EC_PAGE_REG(10, 0x62) + +/* Weight Matrix Configuration */ + +#define FAN_ALG_ENGINE_WEIGHT_EN_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(10, 0xC1 + 8*((fan) - 9)) \ + : EC_PAGE_REG(10, 0x80 + 8*((fan) - 1))) +#define FAN_ALG_ENGINE_WEIGHT_CHANNEL_EN(fan) (1 << (((fan) - 1) % 8)) + +#define FAN_ALG_ENGINE_WEIGHT_VAL_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(10, 0xC3 + ((fan) - 9)/2 + 8*((fan) - 9)) \ + : EC_PAGE_REG(10, 0x84 + ((fan) - 1)/2 + 8*((fan) - 1))) +#define FAN_ALG_ENGINE_WEIGHT_MASK(fan) (0xf << (4 * (((fan) - 1) % 2))) +#define FAN_ALG_ENGINE_WEIGHT_SHIFT(fan) (4 * (((fan) - 1) % 2)) + +/* EC Page 11 - Thermal Cruise, Speed Cruise, Smart Fan IV */ + +#define FAN_PWM_PERCENT_TO_HEX(x) ((x) * 255 / 100) + + +/* For x larger than 10, the registers are placed in page 12 */ +/* Thermal Cruise (TC) Registers */ + +#define FAN_TC_TARGET_TEMP_TOLERANCE_REG(fan) EC_PAGE_REG(11, 0x00 + 24*((fan) - 1)) +#define FAN_TC_TEMP_TOLERANCE_MASK 0xf +#define FAN_TC_TEMP_TOLERANCE_SHIFT 0 + +#define FAN_TC_TARGET_TEMP_REG(fan) EC_PAGE_REG(11, 0x01 + 24*((fan) - 1)) +#define FAN_TC_TARGET_TEMP_MASK 0x7f +#define FAN_TC_TARGET_TEMP_SHIFT 0 +#define FAN_TC_KEEP_MIN_OUTPUT (1 << 7) + +#define FAN_TC_STOP_VALUE_REG(fan) EC_PAGE_REG(11, 0x02 + 24*((fan) - 1)) + +#define FAN_TC_TIME_TO_SECONDS(x) ((x)*10) +#define FAN_TC_STOP_TIME_REG(fan) EC_PAGE_REG(11, 0x03 + 24*((fan) - 1)) +#define FAN_TC_STEP_DOWN_TIME_REG(fan) EC_PAGE_REG(11, 0x04 + 24*((fan) - 1)) +#define FAN_TC_STEP_UP_TIME_REG(fan) EC_PAGE_REG(11, 0x05 + 24*((fan) - 1)) + +/* Speed Cruise (SC) Registers */ + +#define FAN_SC_TARGET_RPM_HI_REG(fan) EC_PAGE_REG(11, 0x00 + 24*((fan) - 1)) +#define FAN_SC_TARGET_RPM_LO_REG(fan) EC_PAGE_REG(11, 0x01 + 24*((fan) - 1)) +#define FAN_SC_TARGET_RPM_TOLERANCE_HI_REG(fan) EC_PAGE_REG(11, 0x02 + 24*((fan) - 1)) +#define FAN_SC_TARGET_RPM_TOLERANCE_LO_REG(fan) EC_PAGE_REG(11, 0x03 + 24*((fan) - 1)) + +#define FAN_SC_TIME_TO_SECONDS(x) ((x)*10) +#define FAN_SC_STEP_DOWN_TIME_REG(fan) EC_PAGE_REG(11, 0x04 + 24*((fan) - 1)) +#define FAN_SC_STEP_UP_TIME_REG(fan) EC_PAGE_REG(11, 0x05 + 24*((fan) - 1)) + +/* Smart Fan IV (SF4) Registers */ + +#define FAN_SF4_TEMP_LVL_REG(fan, level) EC_PAGE_REG(11, 0x00 + (level) + 24*((fan) - 1)) +#define FAN_SF4_PWM_RPM_LVL_HI_REG(fan, level) EC_PAGE_REG(11, 0x07 + (level)*2 + 24*((fan) - 1)) +#define FAN_SF4_PWM_RPM_LVL_LO_REG(fan, level) EC_PAGE_REG(11, 0x08 + (level)*2 + 24*((fan) - 1)) +#define FAN_SF4_TEMP_OFF_HYSTHERESIS_REG(fan) EC_PAGE_REG(11, 0x15 + 24*((fan) - 1)) +#define FAN_SF4_TEMP_CUT_OFF_REG(fan) EC_PAGE_REG(11, 0x16 + 24*((fan) - 1)) +#define FAN_SF4_TEMP_OFF_DELAY_REG(fan) EC_PAGE_REG(11, 0x17 + 24*((fan) - 1)) + +/* EC Page 12 - Fan Function Control */ + +#define FAN_ENGINE_STS_REG EC_PAGE_REG(12, 0xf8) +#define FAN_PECI_CFG_ADJUSTED (1 << 1) +#define FAN_UNFINISHED_FLAG (1 << 2) +#define FAN_CFG_PHASE (1 << 3) +#define FAN_CFG_INVALID (1 << 4) +#define FAN_CFG_CHECK_DONE (1 << 5) +#define FAN_CFG_LOCK (1 << 6) +#define FAN_DRIVE_BY_MOD_SEL (0 << 7) +#define FAN_DRIVE_BY_DEFAULT_VAL (1 << 7) + +#define FAN_LAST_ERROR_CODE_REG EC_PAGE_REG(12, 0xf9) +#define FAN_NO_ERROR 0x00 +#define FAN_ERR_MODE_SELECT 0x01 +#define FAN_ERR_CRIT_TEMP_PROTECT 0x02 +#define FAN_ERR_ITL_FAN_CONTROL 0x04 +#define FAN_ERR_SMART_TRACKING 0x05 +#define FAN_ERR_THERMAL_CRUISE 0x10 +#define FAN_ERR_SPEED_CRUISE 0x20 +#define FAN_ERR_SMART_FAN_IV 0x40 +#define FAN_ERR_PID_CONTROL 0x50 + +#define FAN_CHANNEL_EN_REG(fan) \ + (((fan) > 8) ? EC_PAGE_REG(12, 0xfb) \ + : EC_PAGE_REG(12, 0xfc)) +#define FAN_CHANNEL_EN(fan) (1 << (((fan) - 1) % 8)) + +#define FAN_DEFAULT_VAL_REG EC_PAGE_REG(12, 0xfd) + +extern uint16_t nct6687d_hwm_base; + +static __always_inline void hwm_reg_and_or(uint16_t page_reg, uint8_t and_mask, uint8_t or_mask) +{ + assert(nct6687d_hwm_base != 0); + nct6687d_ec_and_or_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, + and_mask, or_mask); +} + +static __always_inline void hwm_reg_set_bits(uint16_t page_reg, uint8_t bits) +{ + assert(nct6687d_hwm_base != 0); + nct6687d_ec_and_or_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, + ~bits, bits); +} + +static __always_inline void hwm_reg_write(uint16_t page_reg, uint8_t value) +{ + assert(nct6687d_hwm_base != 0); + nct6687d_ec_write_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff, value); +} + +static __always_inline uint8_t hwm_reg_read(uint16_t page_reg) +{ + assert(nct6687d_hwm_base != 0); + return nct6687d_ec_read_page(nct6687d_hwm_base, page_reg >> 8, page_reg & 0xff); +} + +#endif /* SUPERIO_NUVOTON_NCT6687D_HWM_H */ diff --git a/src/superio/nuvoton/nct6687d/superio.c b/src/superio/nuvoton/nct6687d/superio.c index c28092736f4..ef9e323dd9c 100644 --- a/src/superio/nuvoton/nct6687d/superio.c +++ b/src/superio/nuvoton/nct6687d/superio.c @@ -1,12 +1,14 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include +#include #include #include #include #include #include +#include "chip.h" #include "nct6687d.h" #define MAINBOARD_POWER_OFF 0 @@ -21,35 +23,98 @@ #define NCT6687D_ACPI_POWER_PREV_STATE (2 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT) #define NCT6687D_ACPI_POWER_USER_DEFINED (3 << NCT6687D_ACPI_POWER_LOSS_CONTROL_SHIFT) +/* 0xe7 register definitions */ +#define NCT6687D_ACPI_ON_PSOUT_MASK 0x10 +#define NCT6687D_ACPI_ON_PSOUT_SHIFT 4 +#define NCT6687D_ACPI_ON_PSOUT_DIS (0 << NCT6687D_ACPI_ON_PSOUT_SHIFT) +#define NCT6687D_ACPI_ON_PSOUT_EN (1 << NCT6687D_ACPI_ON_PSOUT_SHIFT) + +static void nct6687d_configure_power_fail_state(struct device *dev) +{ + uint8_t reg_eb, reg_e7; + uint8_t power_status; + /* Set power state after power fail */ + power_status = dasharo_get_power_on_after_fail(); + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + reg_eb = pnp_read_config(dev, 0xeb); + reg_e7 = pnp_read_config(dev, 0xe7); + reg_eb &= ~NCT6687D_ACPI_POWER_LOSS_CONTROL_MASK; + reg_e7 &= ~NCT6687D_ACPI_ON_PSOUT_MASK; + + if (power_status == MAINBOARD_POWER_ON) { + reg_eb |= NCT6687D_ACPI_POWER_ALWAYS_ON; + reg_e7 |= NCT6687D_ACPI_ON_PSOUT_EN; + } else if (power_status == MAINBOARD_POWER_KEEP) { + reg_eb |= NCT6687D_ACPI_POWER_PREV_STATE; + reg_e7 |= NCT6687D_ACPI_ON_PSOUT_EN; + } + + pnp_write_config(dev, 0xeb, reg_eb); + pnp_write_config(dev, 0xe7, reg_e7); + pnp_exit_conf_mode(dev); + + printk(BIOS_INFO, "set power %s after power fail\n", + power_status ? "on" : "off"); +} + +static void nct6687d_configure_ps2_wake(struct device *dev) +{ + uint8_t reg; + struct device *ps2_dev = dev_find_slot_pnp(dev->path.pnp.port, NCT6687D_KBC); + + if (!ps2_dev || !ps2_dev->enabled) + return; + + pnp_enter_conf_mode(dev); + pnp_set_logical_device(dev); + + reg = pnp_read_config(dev, 0xe0); + reg |= 0x01; /* Any character from the keybaord can wake up the system */ + reg &= 0xed; /* Clear MSXKEY and MSRKEY to allow either left or right click to wake */ + pnp_write_config(dev, 0xe0, reg); + + reg = pnp_read_config(dev, 0xe6); + reg |= 0x80; /* Set ENMDAT to allow either left or right click to wake */ + pnp_write_config(dev, 0xe6, reg); + + reg = pnp_read_config(dev, 0xe7); + reg &= 0x3f; /* Disable 2nd and 3rd set of wake-up key combinations */ + reg |= 0x20; /* Enable Win98 dedicated wake up key */ + pnp_write_config(dev, 0xe7, reg); + + reg = pnp_read_config(dev, 0xe4); + reg |= 0xc0; /* Enable keyboard and mouse wake via PSOUT# */ + reg |= 0x08; /* Enable keyboard wake with any key */ + pnp_write_config(dev, 0xe4, reg); + + pnp_exit_conf_mode(dev); +} + static void nct6687d_init(struct device *dev) { + const struct superio_nuvoton_nct6687d_config *conf; + const struct resource *res; + if (!dev->enabled) return; - uint8_t byte; - uint8_t power_status; switch (dev->path.pnp.device) { - /* TODO: Might potentially need code for EC, GPIOs, etc. */ case NCT6687D_KBC: pc_keyboard_init(PROBE_AUX_DEVICE); break; case NCT6687D_ACPI: - /* Set power state after power fail */ - power_status = get_uint_option("power_on_after_fail", - CONFIG_MAINBOARD_POWER_FAILURE_STATE); - pnp_enter_conf_mode(dev); - pnp_set_logical_device(dev); - byte = pnp_read_config(dev, 0xeb); - byte &= ~NCT6687D_ACPI_POWER_LOSS_CONTROL_MASK; - if (power_status == MAINBOARD_POWER_ON) - byte |= NCT6687D_ACPI_POWER_ALWAYS_ON; - else if (power_status == MAINBOARD_POWER_KEEP) - byte |= NCT6687D_ACPI_POWER_PREV_STATE; - pnp_write_config(dev, 0xeb, byte); - pnp_exit_conf_mode(dev); - printk(BIOS_INFO, "set power %s after power fail\n", - power_status ? "on" : "off"); + nct6687d_configure_power_fail_state(dev); + nct6687d_configure_ps2_wake(dev); break; + case NCT6687D_EC: + conf = dev->chip_info; + res = probe_resource(dev, PNP_IDX_IO0); + if (!conf || !res) + break; + nct6687d_hwm_init(res->base, conf); } } diff --git a/src/superio/smsc/sch5545/acpi/superio.asl b/src/superio/smsc/sch5545/acpi/superio.asl index 06ef7b018be..e3c9be77a66 100644 --- a/src/superio/smsc/sch5545/acpi/superio.asl +++ b/src/superio/smsc/sch5545/acpi/superio.asl @@ -288,7 +288,6 @@ Device(SIO1) { PMS1 = (Local0 | 0x18) Local0 = PMES PMES = (Local0 | 1) - Local0 = PME1 If (KBFG) { @@ -337,23 +336,16 @@ Device(SIO1) { /* SIO wake method */ Method (SIOW, 1, NotSerialized) { - If (Arg0 == 1) - { - GPKM () - ENTER_CONFIG_MODE (1) - Local0 = OPT0 - OPT0 = (Local0 & 0x9F) - EXIT_CONFIG_MODE () - } - - If (Arg0 == 0x03) + If (Arg0 == 0x03 || Arg0 == 1) { GPKM () ENTER_CONFIG_MODE (1) Local0 = OPT0 OPT0 = (Local0 & 0x9F) - OPT2 |= 1 - OPT2 &= 0xFE + If (Arg0 == 0x03) { + OPT2 |= 1 + OPT2 &= 0xFE + } EXIT_CONFIG_MODE () } } diff --git a/src/vendorcode/Makefile.mk b/src/vendorcode/Makefile.mk index 36a13bb6f67..3bf1ad22a08 100644 --- a/src/vendorcode/Makefile.mk +++ b/src/vendorcode/Makefile.mk @@ -5,3 +5,4 @@ subdirs-y += siemens subdirs-y += cavium subdirs-y += eltan subdirs-y += mediatek +subdirs-y += dasharo diff --git a/src/vendorcode/amd/pi/Makefile.mk b/src/vendorcode/amd/pi/Makefile.mk index 446e9d47794..46797224489 100644 --- a/src/vendorcode/amd/pi/Makefile.mk +++ b/src/vendorcode/amd/pi/Makefile.mk @@ -106,6 +106,7 @@ CC_bootblock := $(CC_bootblock) $(AGESA_INC) $(AGESA_CFLAGS) CC_romstage := $(CC_romstage) $(AGESA_INC) $(AGESA_CFLAGS) CC_postcar:= $(CC_postcar) -I$(src)/southbridge/amd/pi/hudson -I$(AGESA_ROOT)/binaryPI CC_ramstage := $(CC_ramstage) $(AGESA_INC) $(AGESA_CFLAGS) +CC_smm := $(CC_smm) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_32 := $(CC_x86_32) $(AGESA_INC) $(AGESA_CFLAGS) CC_x86_64 := $(CC_x86_64) $(AGESA_INC) $(AGESA_CFLAGS) @@ -165,9 +166,11 @@ ramstage-libs += $(agesa_output_path)/libagesa.a ####################################################################### -cbfs-files-y += $(CONFIG_AGESA_CBFS_NAME) -$(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE) -$(CONFIG_AGESA_CBFS_NAME)-type := raw -$(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) +AGESA_CBFS_FILE=$(call strip_quotes,$(CONFIG_AGESA_CBFS_NAME)) + +cbfs-files-y += $(AGESA_CBFS_FILE) +$(AGESA_CBFS_FILE)-file := $(CONFIG_AGESA_BINARY_PI_FILE) +$(AGESA_CBFS_FILE)-type := raw +$(AGESA_CBFS_FILE)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) endif diff --git a/src/vendorcode/dasharo/Kconfig b/src/vendorcode/dasharo/Kconfig new file mode 100644 index 00000000000..9eb23f90836 --- /dev/null +++ b/src/vendorcode/dasharo/Kconfig @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only + +if GENERATE_SMBIOS_TABLES + +config BIOS_VENDOR + default "3mdeb" + +endif + +comment "Dasharo" + +menu "Dasharo Configuration" + +config DASHARO_PREFER_S3_SLEEP + bool "Prefer S3 suspend over S0ix" + depends on HAVE_ACPI_RESUME + default n if PAYLOAD_EDK2 + default y + help + Enables S3 sleep state as default in the coreboot and EDK2 UEFI Payload. + +config DASHARO_FIRMWARE_UPDATE_MODE + bool "Enable Firmware Update Mode in the project" + default y if PAYLOAD_EDK2 + help + Enables Frimware Update Flow in coreboot and shows the FUM option in + Dasharo menu. + +endmenu + diff --git a/src/vendorcode/dasharo/Makefile.mk b/src/vendorcode/dasharo/Makefile.mk new file mode 100644 index 00000000000..7bc03c60a2b --- /dev/null +++ b/src/vendorcode/dasharo/Makefile.mk @@ -0,0 +1,8 @@ +## SPDX-License-Identifier: GPL-2.0-only + +CPPFLAGS_common += -Isrc/vendorcode/dasharo/include/ + +smm-y += options.c +all-y += options.c + +ramstage-y += smbios.c diff --git a/src/vendorcode/dasharo/include/dasharo/cfr.h b/src/vendorcode/dasharo/include/dasharo/cfr.h new file mode 100644 index 00000000000..98fd218c9c6 --- /dev/null +++ b/src/vendorcode/dasharo/include/dasharo/cfr.h @@ -0,0 +1,151 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DASHARO_CFR_H +#define DASHARO_CFR_H + +#include +#include +#include "options.h" + +struct sm_object lock_bios = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "lock_bios", + .ui_name = "Lock the BIOS boot medium", + .ui_helptext = "This option locks down the BIOS flash", + .default_value = true, +}); + +static void smm_bwp_callback(const struct sm_object *obj, struct sm_object *new) +{ + if (!CONFIG(BOOTMEDIA_SMM_BWP)) + new->sm_bool.flags |= CFR_OPTFLAG_SUPPRESS; +} + +struct sm_object smm_bwp = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "smm_bwp", + .ui_name = "SMM BIOS Write Protection", + .ui_helptext = "This option prevents flash writes outside of SMM", + .default_value = false, +}, WITH_CALLBACK(&smm_bwp_callback)); + +struct sm_object watchdog_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "watchdog_enable", + .ui_name = "Enable watchdog timer", + .ui_helptext = "The watchdog will reset the platform once the timer expires", + .default_value = CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE), +}); + +struct sm_object watchdog_timeout = SM_DECLARE_NUMBER({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "watchdog_timeout", + .ui_name = "Watchdog timeout", + .ui_helptext = "After this timeout expires, the platform will be re-set", + .default_value = CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS, +}, WITH_DEP(&watchdog_enable)); + +struct sm_object power_on_after_fail = SM_DECLARE_ENUM({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "power_on_after_fail", + .ui_name = "Power state after fail", + .ui_helptext = "State of the platform after external power is restored", + .default_value = CONFIG_MAINBOARD_POWER_FAILURE_STATE, + .values = (const struct sm_enum_value[]) { + { "Off", 0 }, + { "On", 1 }, + { "Previous", 2 }, + SM_ENUM_VALUE_END }, +}); + +struct sm_object me_mode = SM_DECLARE_ENUM({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "me_mode", + .ui_name = "Intel ME mode", + .ui_helptext = "Operational mode of Intel Management Engine", + .default_value = CONFIG_INTEL_ME_DEFAULT_STATE, + .values = (const struct sm_enum_value[]) { + { "Enabled", ME_MODE_ENABLE }, + { "Disabled (Soft)", ME_MODE_DISABLE_HECI }, +#if CONFIG(HAVE_INTEL_ME_HAP) + { "Disabled (HAP)", ME_MODE_DISABLE_HAP }, +#endif + SM_ENUM_VALUE_END }, +}); + +static void ps2_enable_callback(const struct sm_object *obj, struct sm_object *new) +{ + if (!CONFIG(EDK2_PS2_SUPPORT)) + new->sm_bool.flags |= CFR_OPTFLAG_SUPPRESS; +} + +struct sm_object ps2_enable = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "ps2_enable", + .ui_name = "Enable PS/2 controller", + .ui_helptext = "Enable or disable the PS/2 controller. Enabling PS/2 slightly increases boot time.", + .default_value = true, +}, WITH_CALLBACK(&ps2_enable_callback)); + +struct sm_object hyper_threading = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "hyper_threading", + .ui_name = "Enable Hyper-Threading", + .ui_helptext = "Enable or disable Hyper-Threading", + .default_value = true, +}); + +struct sm_object throttle_offset = SM_DECLARE_NUMBER({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "throttle_offset", + .ui_name = "Thermal throttling offset", + .ui_helptext = "Adjust the temperature at which the processor will thermal throttle. " \ + "Lower offset means higher temperature, and vice versa.", + .default_value = CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT, +}); + +static void update_throttling_temp(const struct sm_object *obj, struct sm_object *new) +{ + new->sm_number.default_value = CONFIG_CPU_MAX_TEMPERATURE - get_uint_option("throttle_offset", CONFIG_EDK2_CPU_THROTTLING_THRESHOLD_DEFAULT); +} + +struct sm_object throttle_temp = SM_DECLARE_NUMBER({ + .flags = CFR_OPTFLAG_READONLY | CFR_OPTFLAG_VOLATILE, + .opt_name = "throttle_temp", + .ui_name = "Current thermal throttling temperature", +}, WITH_CALLBACK(update_throttling_temp)); + + +struct sm_object network_boot = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "network_boot", + .ui_name = "Network Boot", + .ui_helptext = "Enable or disable network boot functionality", + .default_value = CONFIG(EDK2_DASHARO_NETWORK_BOOT_DEFAULT_ENABLE), +}); + +struct sm_object uefi_usb_stack = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "uefi_usb_stack", + .ui_name = "UEFI USB stack", + .ui_helptext = "Enable or disable UEFI USB Stack", + .default_value = true, +}); + +struct sm_object uefi_usb_msc = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "uefi_usb_msc", + .ui_name = "UEFI USB Mass Storage driver", + .ui_helptext = "Enable or disable UEFI USB Mass Storage driver", + .default_value = true, +}, WITH_DEP(&uefi_usb_stack)); + +struct sm_object com0_redirection = SM_DECLARE_BOOL({ + .flags = CFR_OPTFLAG_RUNTIME, + .opt_name = "com0_redirection", + .ui_name = "COM0 Console Redirection", + .ui_helptext = "Enable or disable console on COM0 serial port", + .default_value = true, +}); + +#endif // DASHARO_CFG_H diff --git a/src/vendorcode/dasharo/include/dasharo/options.h b/src/vendorcode/dasharo/include/dasharo/options.h new file mode 100644 index 00000000000..b2653d27577 --- /dev/null +++ b/src/vendorcode/dasharo/include/dasharo/options.h @@ -0,0 +1,312 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DASHARO_OPTIONS_H +#define DASHARO_OPTIONS_H + +#include +#include + +#define SLEEP_TYPE_OPTION_S0IX 0 +#define SLEEP_TYPE_OPTION_S3 1 + +#define FAN_CURVE_OPTION_SILENT 0 +#define FAN_CURVE_OPTION_PERFORMANCE 1 +#define FAN_CURVE_OPTION_OFF 2 + +#define FAN_CURVE_OPTION_DEFAULT FAN_CURVE_OPTION_SILENT + +#define SLEEP_TYPE_OPTION_S0IX 0 +#define SLEEP_TYPE_OPTION_S3 1 + +#define CAMERA_ENABLED_OPTION 1 +#define CAMERA_DISABLED_OPTION 0 + +#define CAMERA_ENABLEMENT_DEFAULT CAMERA_ENABLED_OPTION + +#define BATTERY_START_THRESHOLD_DEFAULT 95 +#define BATTERY_STOP_THRESHOLD_DEFAULT 98 + +#define ALL_CORES_ACTIVE 0xff + +enum cse_disable_mode { + ME_MODE_ENABLE = 0, + ME_MODE_DISABLE_HECI = 1, + ME_MODE_DISABLE_HAP = 2, + /* Not a variable value, but serves a purpose of disabling ME in boot flow */ + ME_MODE_DISABLE_HMRFPO = 10 +}; + +enum usb_port_power_opt { + USB_PORT_ON_WHEN_POWERED = 0, + USB_PORT_ALWAYS_ON = 1, +}; + +struct watchdog_config { + bool wdt_enable; + uint16_t wdt_timeout; +} __packed; + +struct fan_point { + uint8_t temp; + uint8_t duty; +} __packed; + +struct fan_curve { + struct fan_point point1; + struct fan_point point2; + struct fan_point point3; + struct fan_point point4; +} __packed; + +struct battery_config { + uint8_t start_threshold; + uint8_t stop_threshold; +} __packed; + +/* Attempts to wipe the SMMSTORE region in order to reset EFI options. + * UEFIPayload will populate it with default values upon boot. + * + * Result: + * - CB_SUCCESS - Success + * - CB_ERR - Failure, including partial wipe + */ +enum cb_err dasharo_reset_options(void); + +/* Looks up "power_on_after_fail" option and Dasharo/"PowerFailureState" + * variable. + * + * Result (same as MAINBOARD_POWER_STATE_*): + * - 0 - stay powered OFF + * - 1 - power ON + * - 2 - restore previous state + */ +uint8_t dasharo_get_power_on_after_fail(void); + +/* Looks up Dasharo/"UsbPortPower" variable. + * + * Result: + * - 0 - Only when powered on (default) + * - 1 - Always Enabled + */ +uint8_t dasharo_get_usb_port_power(void); + +/* Looks up Dasharo/"PCIeResizeableBarsEnabled" variable if resizable PCIe BARs + * support was enabled at compile-time. + * + * Result: + * - true - resizeable PCIe BARs are supported and enabled + * - false - resizeable PCIe BARs are disabled or not supported + */ +bool dasharo_resizeable_bars_enabled(void); + +/* Looks Dasharo/"LockBios" variable if bootmedia lock was enabled at compile + * time. + * + * Result: + * - true - bootmedia lock is supported and enabled + * - false - bootmedia lock is disabled or not supported + */ +bool is_vboot_locking_permitted(void); + +/* Looks Dasharo/"IommuConfig" variable if early DMA protection lock was + * enabled at compile time. + * + * Result: + * - true - DMA protection is supported and enabled + * - false - DMA protection is disabled or not supported + */ +bool dma_protection_enabled(void); + +/* Looks Dasharo/"MeMode" variable if ME should be enabeld or disabled. + * + * Result: + * - 0 - ME enabled + * - 1 - ME soft disabled + * - 2 - ME HAP disabled + */ +uint8_t cse_get_me_disable_mode(void); + +/* Looks Dasharo/"SmmBwp" variable if SMM BIOS Write Protection was + * enabled at compile time. + * + * Result: + * - true - DMA protection is supported and enabled + * - false - DMA protection is disabled or not supported + */ +bool is_smm_bwp_permitted(void); + +/* Looks Dasharo/"WatchdogCOnfig" variable if OC Watchdog was + * enabled at compile time. + * + * Result: + * - true - DMA protection is supported and enabled + * - false - DMA protection is disabled or not supported + */ +void get_watchdog_config(struct watchdog_config *wdt_cfg); + +/* Looks Dasharo/"WatchdogCOnfig" variable if PS/2 controller should be + * enabled. The function should be called from mainboard code to disable + * appropriate PNP device in devicetree. + * + * Result: + * - true - PS/2 controller enabled + * - false - PS/2 controller disabled + */ +bool get_ps2_option(void); + +/* Looks Dasharo/"SleepType" variable to check which sleep type should be + * enabled. + * + * Result: + * - 0 - S0ix + * - 1 - S3 + */ +uint8_t get_sleep_type_option(void); + +/* Looks Dasharo/"FanCurveOption" variable to check which fan curve EC should + * apply. + * + * + * Result: + * - 0 - Silent profile + * - 1 - Performance profile + */ +uint8_t get_fan_curve_option(void); + +/* Looks Dasharo/"EnableCamera" variable to checkif camera USB port should be + * emabled. + * + * Result: + * - true - camera enabled + * - false - camera disabled + */ +bool get_camera_option(void); + +/* Looks Dasharo/"EnableWifiBt" variable to check if WiFi and Bluetooth should + * be enabled. + * + * Result: + * - true - Wireless radios enabled + * - false - Wireless radios disabled + */ +bool get_wireless_option(void); + +/* Looks Dasharo/"BatteryConfig" variable to check battery configuration + * (charge thresholds) + * + * Arguments: + * - bat_cfg - battery configuration parameters + */ +void get_battery_config(struct battery_config *bat_cfg); + +/* Looks Dasharo/"Type2SN" variable to check if Serial Number was saved. + * + * Arguments: + * - serial_number - pointer where the serial number should be returned + * Result: + * - true - Serial Number present in EFI variables + * - false - Serial Number not present in EFI variables + */ +bool get_serial_number_from_efivar(char *serial_number); + +/* Looks Dasharo/"Type1UUID" variable to check if system UUID was saved. + * + * Arguments: + * - uuid - pointer where the UUID should be returned + * Result: + * - true - System UUID present in EFI variables + * - false - SystemUUID not present in EFI variables + */ +bool get_uuid_from_efivar(uint8_t *uuid); + +/* Looks up Dasharo/"MemoryProfile" variable to know which memory profile to + * enable. + * + * Result (values of FSP_M_CONFIG::SpdProfileSelected): + * - 0 - Default SPD Profile + * - 1 - Custom Profile + * - 2 - XMP Profile 1 + * - 3 - XMP Profile 2 + * - 4 - XMP Profile 3 + * - 5 - XMP User Profile 4 + * - 6 - XMP User Profile 5 + */ +uint8_t dasharo_get_memory_profile(void); + +/* Looks up PciePwrMgmt field in APU/"ApuConfig" to know whether to enable + * Clock Power Management, ASPM L0s and L1 features on PCI Express ports. + * + * Result: + * - true - PM features on PCI express ports are enabled + * - false - PM features on PCI express ports are disabled + */ +bool dasharo_apu_pcie_pm_enabled(void); + +/* Looks up WatchdogEnable and WatchdogTimeout fields in APU/"ApuConfig" to + * know whether to enable watchdog on boot and what period to use. + * + * Result: + * - = 0 - watchdog is disabled + * - > 0 - watchdog is enabled and should be configured to reboot after + * returned number of seconds has passed + */ +uint16_t dasharo_apu_watchdog_timeout(void); + +/* Looks up CorePerfBoost field in APU/"ApuConfig" to know whether to enable + * CPU boost. + * + * Result: + * - true - CPU boost should be enabled on boot + * - false - CPU boost should not be enabled on boot + */ +bool dasharo_apu_cpu_boost_enabled(void); + +/* Looks Dasharo/"CoreActiveCount" variable to check how many cores should be + * active. + * + * + * Result: + * - Number of active cores + */ +uint8_t get_active_core_count_option(void); + +/* Looks Dasharo/"SmallCoreActiveCount" variable to check how many small cores + * should be active. + * + * + * Result: + * - Number of active cores + */ +uint8_t get_active_small_core_count_option(void); + +/* Looks Dasharo/"HyperThreading" variable to check Hyper-Threading should be + * enabled. + * + * + * Result: + * - true - Hyper-Threading enabled + * - false - Hyper-Threading disabled + */ +bool get_hyper_threading_option(void); + +/* Looks up Dasharo/"CpuThrottlingOffset" variable to return the CPU + * TCC offset temperature. + * + * Arguments: + * - tcc_offset - default platform value of TCC offset + * Result: + * returns uint8 - TCC offset from Tjmax + */ +uint8_t get_cpu_throttling_offset(uint8_t tcc_offset); + +/* + * Disable DGPU for power savings. + * + * + * Result: + * - true - DGPU enabled + * - false - DGPU disabled + */ + bool dasharo_is_dgpu_enabled(void); + +#endif /* DASHARO_OPTIONS_H */ diff --git a/src/vendorcode/dasharo/options.c b/src/vendorcode/dasharo/options.c new file mode 100644 index 00000000000..48aa642568a --- /dev/null +++ b/src/vendorcode/dasharo/options.c @@ -0,0 +1,552 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_CSE) +#include +#endif + +_Static_assert(sizeof(bool) == 1, "Size of bool, must be 1"); + +/* Keeping field names as in EDK to make things easier to follow, types are + * different though. */ +struct apu_config_t { + bool CorePerfBoost; + bool WatchdogEnable; + uint16_t WatchdogTimeout; /* in seconds */ + bool PciePwrMgmt; +} __packed; + +static const EFI_GUID dasharo_system_features_guid = { + 0xd15b327e, 0xff2d, 0x4fc1, { 0xab, 0xf6, 0xc1, 0x2b, 0xd0, 0x8c, 0x13, 0x59 } +}; + +static const EFI_GUID dasharo_apu_features_guid = { + 0x6f4e051b, 0x1c10, 0x422a, { 0x98, 0xcf, 0x96, 0x2e, 0x78, 0x36, 0x5c, 0x74 } +}; + +/* Value of *var is not changed on failure, so it's safe to initialize it with + * a default before the call. */ +static enum cb_err read_u8_var(const char *var_name, uint8_t *var) +{ + struct region_device rdev; + + if (CONFIG(SMMSTORE_V2) && !smmstore_lookup_region(&rdev)) { + uint8_t tmp; + uint32_t size = sizeof(tmp); + enum cb_err ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, + var_name, &tmp, &size); + if (ret == CB_SUCCESS) { + if (size == sizeof(tmp)) { + *var = tmp; + return CB_SUCCESS; + } + + printk(BIOS_WARNING, + "dasharo: EFI variable \"%s\" of wrong size (%d instead of 1)\n", + var_name, size); + } + } + + return CB_ERR; +} + +/* Value of *var is not changed on failure, so it's safe to initialize it with + * a default before the call. */ +static enum cb_err read_bool_var(const char *var_name, bool *var) +{ + uint8_t tmp; + + if (read_u8_var(var_name, &tmp) == CB_SUCCESS) { + *var = tmp != 0; + return CB_SUCCESS; + } + + return CB_ERR; +} + +/* Never fails, just returns defaults on error. */ +static struct apu_config_t get_apu_config(void) +{ + static bool init_done; + static struct apu_config_t cfg; + + if (init_done) + return cfg; + + /* Start with defaults as in EDK. */ + struct apu_config_t val = { + .CorePerfBoost = true, + .WatchdogEnable = false, + .WatchdogTimeout = 60, + .PciePwrMgmt = false, + }; + + cfg = val; + + struct region_device rdev; + if (CONFIG(SMMSTORE_V2) && !smmstore_lookup_region(&rdev)) { + uint32_t size = sizeof(val); + enum cb_err ret = efi_fv_get_option(&rdev, + &dasharo_apu_features_guid, + "ApuConfig", &val, &size); + /* Deliberately allowing mismatched size of structure to allow + * compatible changes. All known fields are initialized and + * extra fields are irrelevant. */ + if (ret == CB_SUCCESS) + cfg = val; + } + + init_done = true; + return cfg; +} + +enum cb_err dasharo_reset_options(void) +{ + struct region_device rdev; + ssize_t res; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return CB_ERR; + + res = rdev_eraseat(&rdev, 0, region_device_sz(&rdev)); + if (res != region_device_sz(&rdev)) + return CB_ERR; + + return CB_SUCCESS; +} + +uint8_t dasharo_get_power_on_after_fail(void) +{ + uint8_t power_status; + + power_status = get_uint_option("power_on_after_fail", + CONFIG_MAINBOARD_POWER_FAILURE_STATE); + + /* When present, EFI variable has higher priority. */ + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("PowerFailureState", &power_status); + + return power_status; +} + +uint8_t dasharo_get_usb_port_power(void) +{ + uint8_t usb_port_power = USB_PORT_ON_WHEN_POWERED; + + /* When present, EFI variable has higher priority. */ + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("UsbPortPower", &usb_port_power); + + if (usb_port_power > USB_PORT_ALWAYS_ON) + return USB_PORT_ON_WHEN_POWERED; + + return usb_port_power; +} + +bool dasharo_resizeable_bars_enabled(void) +{ + static bool enabled = false; + static bool read_once = false; + + if (!CONFIG(PCIEXP_SUPPORT_RESIZABLE_BARS)) + return false; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) { + if (!read_once) + read_bool_var("PCIeResizeableBarsEnabled", &enabled); + /* + * This variable would be read for each PCIe device. + * Avoid it by reading the variable only once. + */ + read_once = true; + } else { + /* If no variables are not enabled, follow Kconfig */ + return true; + } + + return enabled; +} + +bool is_vboot_locking_permitted(void) +{ + bool lock = true; + bool fum = false; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("FirmwareUpdateMode", &fum); + else + return !CONFIG(BOOTMEDIA_LOCK_NONE); + + /* Disable lock if in Firmware Update Mode */ + if (CONFIG(DASHARO_FIRMWARE_UPDATE_MODE) && fum) + return false; + + if (CONFIG(DRIVERS_OPTION_CFR)) + lock = get_uint_option("lock_bios", false); + else if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("LockBios", &lock); + + return lock; +} + +bool dma_protection_enabled(void) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + struct iommu_config { + bool iommu_enable; + bool iommu_handoff; + } __packed iommu_var; + uint32_t size; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return false; + + size = sizeof(iommu_var); + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "IommuConfig", + &iommu_var, &size); + + if (ret != CB_SUCCESS) + return false; + + return iommu_var.iommu_enable; +} + +#if CONFIG(SOC_INTEL_COMMON_BLOCK_CSE) +static void disable_me_hmrfpo(uint8_t *var) +{ + int hmrfpo_sts = cse_hmrfpo_get_status(); + + if (hmrfpo_sts == -1) { + printk (BIOS_DEBUG, "ME HMRFPO Get Status failed\n"); + goto hmrfpo_error; + } + + printk (BIOS_DEBUG, "ME HMRFPO status: "); + switch (hmrfpo_sts) { + case 0: + printk (BIOS_DEBUG, "DISABLED\n"); + if (cse_hmrfpo_enable() != CB_SUCCESS) + goto hmrfpo_error; + else + do_global_reset(); /* No return */ + break; + case 1: + printk (BIOS_DEBUG, "LOCKED\n"); + goto hmrfpo_error; + case 2: + printk (BIOS_DEBUG, "ENABLED\n"); + /* Override ME disable method to not switch ME mode */ + *var = ME_MODE_DISABLE_HMRFPO; + /* TODO: disable HMRFPO here if not in FUM? Reboot disables HMRFPO. */ + break; + default: + printk (BIOS_DEBUG, "UNKNOWN\n"); + goto hmrfpo_error; + } + + return; + +hmrfpo_error: + /* Try other available methods if something goes wrong */ + *var = CONFIG(HAVE_INTEL_ME_HAP) ? ME_MODE_DISABLE_HAP + : ME_MODE_DISABLE_HECI; +} + +uint8_t cse_get_me_disable_mode(void) +{ + uint8_t var = CONFIG_INTEL_ME_DEFAULT_STATE; + bool fum = false; + + if (CONFIG(DRIVERS_OPTION_CFR)) { + var = get_uint_option("me_mode", CONFIG_INTEL_ME_DEFAULT_STATE); + } else if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) { + read_bool_var("FirmwareUpdateMode", &fum); + read_u8_var("MeMode", &var); + } + + /* Disable ME via HMRPFO if in Firmware Update Mode */ + if (CONFIG(DASHARO_FIRMWARE_UPDATE_MODE) && fum) { + /* Check if already in HMRFPO mode */ + if (cse_is_hfs1_com_secover_mei_msg()) + return ME_MODE_DISABLE_HMRFPO; + else + disable_me_hmrfpo(&var); + } + + return var; +} + +bool dasharo_is_dgpu_enabled(void) +{ + printk(BIOS_DEBUG, "dasharo_is_dgpu_enabled() called\n"); + bool dgpu_enabled = true; + + /* Functionally, it is a 0 or 1 value. For the desired UI however, the VFR + * requires it to be handled as a uint8. + */ + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)){ + uint8_t tmp = 0; + read_u8_var("DGPUEnabled", &tmp); + printk(BIOS_DEBUG, "DGPUEnabled value: %d\n", tmp); + dgpu_enabled = tmp != 0; + } + + printk(BIOS_DEBUG, "dgpu_enabled value: %d\n", dgpu_enabled); + return dgpu_enabled; +} + +#else +uint8_t cse_get_me_disable_mode(void) +{ + return 0; +} +#endif + +bool is_smm_bwp_permitted(void) +{ + bool smm_bwp = false; + bool fum = false; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("FirmwareUpdateMode", &fum); + + /* Disable SMM BWP if in Firmware Update Mode */ + if (CONFIG(DASHARO_FIRMWARE_UPDATE_MODE) && fum) + return false; + + if (CONFIG(DRIVERS_OPTION_CFR)) + smm_bwp = get_uint_option("smm_bwp", false); + else if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("SmmBwp", &smm_bwp); + else + return CONFIG(BOOTMEDIA_SMM_BWP); + + return smm_bwp; +} + +void get_watchdog_config(struct watchdog_config *wdt_cfg) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + uint32_t size; + + wdt_cfg->wdt_enable = CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE); + wdt_cfg->wdt_timeout = CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return; + + size = sizeof(*wdt_cfg); + if (CONFIG(DRIVERS_OPTION_CFR)) { + wdt_cfg->wdt_enable = get_uint_option("watchdog_enable", CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE)); + wdt_cfg->wdt_timeout = get_uint_option("watchdog_timeout", CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS); + ret = CB_SUCCESS; + } else if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) { + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "WatchdogConfig", + wdt_cfg, &size); + } + + if (ret != CB_SUCCESS || size != sizeof(*wdt_cfg)) { + wdt_cfg->wdt_enable = CONFIG(SOC_INTEL_COMMON_OC_WDT_ENABLE); + wdt_cfg->wdt_timeout = CONFIG_SOC_INTEL_COMMON_OC_WDT_TIMEOUT_SECONDS; + } +} + +bool get_ps2_option(void) +{ + bool ps2_en = true; + + if (CONFIG(DRIVERS_OPTION_CFR)) + ps2_en = get_uint_option("ps2_enable", true); + else if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("Ps2Controller", &ps2_en); + + return ps2_en; +} + +uint8_t get_sleep_type_option(void) +{ + uint8_t sleep_type = CONFIG(DASHARO_PREFER_S3_SLEEP) ? SLEEP_TYPE_OPTION_S3 + : SLEEP_TYPE_OPTION_S0IX; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("SleepType", &sleep_type); + + return sleep_type; +} + +uint8_t get_fan_curve_option(void) +{ + uint8_t fan_curve = FAN_CURVE_OPTION_SILENT; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("FanCurveOption", &fan_curve); + + return fan_curve; +} + +bool get_camera_option(void) +{ + bool cam_en = CAMERA_ENABLED_OPTION; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("EnableCamera", &cam_en); + + return cam_en; +} + +bool get_wireless_option(void) +{ + bool wireless_en = true; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("EnableWifiBt", &wireless_en); + + return wireless_en; +} + +void get_battery_config(struct battery_config *bat_cfg) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + uint32_t size; + + bat_cfg->start_threshold = BATTERY_START_THRESHOLD_DEFAULT; + bat_cfg->stop_threshold = BATTERY_STOP_THRESHOLD_DEFAULT; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return; + + size = sizeof(*bat_cfg); + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "BatteryConfig", + bat_cfg, &size); + + if (ret != CB_SUCCESS || size != sizeof(*bat_cfg)) { + bat_cfg->start_threshold = BATTERY_START_THRESHOLD_DEFAULT; + bat_cfg->stop_threshold = BATTERY_STOP_THRESHOLD_DEFAULT; + } +} + +#define MAX_SERIAL_LENGTH 0x100 + +bool get_serial_number_from_efivar(char *serial_number) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + uint32_t size; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return false; + + size = MAX_SERIAL_LENGTH; + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "Type2SN", serial_number, &size); + + if (ret != CB_SUCCESS || size > MAX_SERIAL_LENGTH) + return false; + + serial_number[size] = '\0'; + + return true; +} + + +bool get_uuid_from_efivar(uint8_t *uuid) +{ + struct region_device rdev; + enum cb_err ret = CB_EFI_OPTION_NOT_FOUND; + uint32_t size; + + if (!CONFIG(SMMSTORE_V2) || smmstore_lookup_region(&rdev)) + return false; + + size = UUID_LEN; + ret = efi_fv_get_option(&rdev, &dasharo_system_features_guid, "Type1UUID", uuid, &size); + if (ret != CB_SUCCESS || size != UUID_LEN) + return false; + + return true; +} + +uint8_t dasharo_get_memory_profile(void) +{ + /* Using default SPD/JEDEC profile by default. */ + uint8_t profile = 0; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("MemoryProfile", &profile); + + return profile; +} + +bool dasharo_apu_pcie_pm_enabled(void) +{ + return get_apu_config().PciePwrMgmt; +} + +uint16_t dasharo_apu_watchdog_timeout(void) +{ + struct apu_config_t cfg = get_apu_config(); + return cfg.WatchdogEnable ? cfg.WatchdogTimeout : 0; +} + +bool dasharo_apu_cpu_boost_enabled(void) +{ + return get_apu_config().CorePerfBoost; +} + + +uint8_t get_active_core_count_option(void) +{ + uint8_t count = ALL_CORES_ACTIVE; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("CoreActiveCount", &count); + + return count; +} + +uint8_t get_active_small_core_count_option(void) +{ + uint8_t count = ALL_CORES_ACTIVE; + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("SmallCoreActiveCount", &count); + + return count; +} + +bool get_hyper_threading_option(void) +{ + bool ht_en; + + ht_en = get_uint_option("hyper_threading", CONFIG(FSP_HYPERTHREADING)); + + if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_bool_var("HyperThreading", &ht_en); + + return ht_en; +} + +uint8_t get_cpu_throttling_offset(uint8_t tcc_offset) +{ + uint8_t offset = tcc_offset; + + if (CONFIG(DRIVERS_OPTION_CFR)) + offset = get_uint_option("throttle_offset", tcc_offset); + else if (CONFIG(DRIVERS_EFI_VARIABLE_STORE)) + read_u8_var("CpuThrottlingOffset", &offset); + + return offset; +} diff --git a/src/vendorcode/dasharo/smbios.c b/src/vendorcode/dasharo/smbios.c new file mode 100644 index 00000000000..407a3cde8a5 --- /dev/null +++ b/src/vendorcode/dasharo/smbios.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +const char *smbios_mainboard_bios_version(void) +{ + + if (CONFIG(PAYLOAD_SEABIOS)) { + if (strlen(CONFIG_LOCALVERSION) != 0) + return "Dasharo (coreboot+SeaBIOS) " CONFIG_LOCALVERSION; + else + return "Dasharo (coreboot+SeaBIOS)"; + } + + if (CONFIG(PAYLOAD_EDK2)) { + if (strlen(CONFIG_LOCALVERSION) != 0) + return "Dasharo (coreboot+UEFI) " CONFIG_LOCALVERSION; + else + return "Dasharo (coreboot+UEFI)"; + } + + if (strlen(CONFIG_LOCALVERSION) != 0) + return "Dasharo " CONFIG_LOCALVERSION; + + return "Dasharo"; +} diff --git a/src/vendorcode/intel/Kconfig b/src/vendorcode/intel/Kconfig index 1fd81dce669..28b5e0e6353 100644 --- a/src/vendorcode/intel/Kconfig +++ b/src/vendorcode/intel/Kconfig @@ -12,7 +12,8 @@ config UDK_2017_BINDING select UDK_BASE config UDK_202005_BINDING - def_bool n + bool "UDK 202005 BINDING" + default n select UDK_BASE config UDK_202111_BINDING diff --git a/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FirmwareVersionInfo.h b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FirmwareVersionInfo.h new file mode 100644 index 00000000000..4a9053c551f --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FirmwareVersionInfo.h @@ -0,0 +1,61 @@ +/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2015 - 2022, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + + @par Specification Reference: + System Management BIOS (SMBIOS) Reference Specification v3.0.0 dated 2015-Feb-12 + http://www.dmtf.org/sites/default/files/standards/documents/DSP0134_3.0.0.pdf + +**/ + +#ifndef __FIRMWARE_VERSION_INFO_H__ +#define __FIRMWARE_VERSION_INFO_H__ + +#include + +#define INTEL_FIRMWARE_VERSION_INFO_GROUP_NAME "Firmware Version Info" +#define INTEL_FVI_SMBIOS_TYPE 0xDD + +#pragma pack(1) + +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} INTEL_FIRMWARE_VERSION; + +/// +/// Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_TABLE_STRING ComponentName; ///< String Index of Component Name + SMBIOS_TABLE_STRING VersionString; ///< String Index of Version String + INTEL_FIRMWARE_VERSION Version; ///< Firmware version +} INTEL_FIRMWARE_VERSION_INFO; + +/// +/// SMBIOS OEM Type Intel Firmware Version Info (FVI) Structure +/// +typedef struct { + SMBIOS_STRUCTURE Header; ///< SMBIOS structure header + UINT8 Count; ///< Number of FVI entries in this structure + INTEL_FIRMWARE_VERSION_INFO Fvi[1]; ///< FVI structure(s) +} SMBIOS_TABLE_TYPE_OEM_INTEL_FVI; + +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FspProducerDataHeader.h b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FspProducerDataHeader.h new file mode 100644 index 00000000000..f7861710aff --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/FspProducerDataHeader.h @@ -0,0 +1,79 @@ +/** @file + + Copyright (c) 2023, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +**/ +#ifndef _FSP_PRODUCER_DATA_HEADER_H_ +#define _FSP_PRODUCER_DATA_HEADER_H_ + +#include + +#define BUILD_TIME_STAMP_SIZE 12 +// +// FSP Header Data structure from FspHeader driver. +// +#pragma pack(1) +/// +/// FSP Producer Data Subtype - 1 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of RC version which is used to build this FSP image. + /// + UINT32 RcVersion; + /// + /// Byte 0x08: Represents the build time stamp "YYYYMMDDHHMM". + /// + UINT8 BuildTimeStamp[BUILD_TIME_STAMP_SIZE]; +} FSP_PRODUCER_DATA_TYPE1; + +/// +/// FSP Producer Data Subtype - 2 +/// +typedef struct { + /// + /// Byte 0x00: Length of this FSP producer data type record. + /// + UINT16 Length; + /// + /// Byte 0x02: FSP producer data type. + /// + UINT8 Type; + /// + /// Byte 0x03: Revision of this FSP producer data type. + /// + UINT8 Revision; + /// + /// Byte 0x04: 4 byte field of Mrc version which is used to build this FSP image. + /// + UINT8 MrcVersion [4]; +} FSP_PRODUCER_DATA_TYPE2; + +typedef struct { + FSP_INFO_HEADER FspInfoHeader; + FSP_INFO_EXTENDED_HEADER FspInfoExtendedHeader; + FSP_PRODUCER_DATA_TYPE1 FspProduceDataType1; + FSP_PRODUCER_DATA_TYPE2 FspProduceDataType2; + FSP_PATCH_TABLE FspPatchTable; +} FSP_PRODUCER_DATA_TABLES; +#pragma pack() + +#endif // _FSP_PRODUCER_DATA_HEADER_H diff --git a/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/MemInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/MemInfoHob.h new file mode 100644 index 00000000000..ff57176221b --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/iot/meteorlake/MemInfoHob.h @@ -0,0 +1,326 @@ +/** @file + This file contains definitions required for creation of + Memory S3 Save data, Memory Info data and Memory Platform + data hobs. + + @copyright + Copyright (c) 1999 - 2022, Intel Corporation. All rights reserved.
+ This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License that accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php. + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +@par Specification Reference: +**/ +#ifndef _MEM_INFO_HOB_H_ +#define _MEM_INFO_HOB_H_ + + +#pragma pack (push, 1) + +extern EFI_GUID gSiMemoryS3DataGuid; +extern EFI_GUID gSiMemoryS3Data2Guid; +extern EFI_GUID gSiMemoryInfoDataGuid; +extern EFI_GUID gSiMemoryPlatformDataGuid; + +#define MAX_NODE 2 +#define MAX_CH 4 +#define MAX_DDR5_CH 2 +#define MAX_DIMM 2 +// Must match definitions in +// Intel\ClientOneSiliconPkg\IpBlock\MemoryInit\Mtl\Include\MrcInterface.h +#define HOB_MAX_SAGV_POINTS 4 + +/// +/// Host reset states from MRC. +/// +#define WARM_BOOT 2 + +#define R_MC_CHNL_RANK_PRESENT 0x7C +#define B_RANK0_PRS BIT0 +#define B_RANK1_PRS BIT1 +#define B_RANK2_PRS BIT4 +#define B_RANK3_PRS BIT5 + +// @todo remove and use the MdePkg\Include\Pi\PiHob.h +#if !defined(_PEI_HOB_H_) && !defined(__PI_HOB_H__) +#ifndef __HOB__H__ +typedef struct _EFI_HOB_GENERIC_HEADER { + UINT16 HobType; + UINT16 HobLength; + UINT32 Reserved; +} EFI_HOB_GENERIC_HEADER; + +typedef struct _EFI_HOB_GUID_TYPE { + EFI_HOB_GENERIC_HEADER Header; + EFI_GUID Name; + /// + /// Guid specific data goes here + /// +} EFI_HOB_GUID_TYPE; +#endif +#endif + +/// +/// Defines taken from MRC so avoid having to include MrcInterface.h +/// + +// +// Matches MAX_SPD_SAVE define in MRC +// +#ifndef MAX_SPD_SAVE +#define MAX_SPD_SAVE 29 +#endif + +// +// MRC version description. +// +typedef struct { + UINT8 Major; ///< Major version number + UINT8 Minor; ///< Minor version number + UINT8 Rev; ///< Revision number + UINT8 Build; ///< Build number +} SiMrcVersion; + +// +// Matches MrcChannelSts enum in MRC +// +#ifndef CHANNEL_NOT_PRESENT +#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller. +#endif +#ifndef CHANNEL_DISABLED +#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled. +#endif +#ifndef CHANNEL_PRESENT +#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled. +#endif + +// +// Matches MrcDimmSts enum in MRC +// +#ifndef DIMM_ENABLED +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected. +#endif +#ifndef DIMM_DISABLED +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence. +#endif +#ifndef DIMM_PRESENT +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used. +#endif +#ifndef DIMM_NOT_PRESENT +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair. +#endif + +// +// Matches MrcBootMode enum in MRC +// +#ifndef __MRC_BOOT_MODE__ +#define __MRC_BOOT_MODE__ //The below values are originated from MrcCommonTypes.h + #ifndef INT32_MAX + #define INT32_MAX (0x7FFFFFFF) + #endif //INT32_MAX +typedef enum { + bmCold, ///< Cold boot + bmWarm, ///< Warm boot + bmS3, ///< S3 resume + bmFast, ///< Fast boot + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration maximum value. + MrcBootModeDelim = INT32_MAX ///< This value ensures the enum size is consistent on both sides of the PPI. +} MRC_BOOT_MODE; +#endif //__MRC_BOOT_MODE__ + +// +// Matches MrcDdrType enum in MRC +// +#ifndef MRC_DDR_TYPE_DDR5 +#define MRC_DDR_TYPE_DDR5 1 +#endif +#ifndef MRC_DDR_TYPE_LPDDR5 +#define MRC_DDR_TYPE_LPDDR5 2 +#endif +#ifndef MRC_DDR_TYPE_LPDDR4 +#define MRC_DDR_TYPE_LPDDR4 3 +#endif +#ifndef MRC_DDR_TYPE_UNKNOWN +#define MRC_DDR_TYPE_UNKNOWN 4 +#endif + +#define MAX_PROFILE_NUM 7 // number of memory profiles supported +#define MAX_XMP_PROFILE_NUM 5 // number of XMP profiles supported + +#ifndef MAX_RCOMP_TARGETS +#define MAX_RCOMP_TARGETS 5 +#endif + +#ifndef MAX_ODT_ENTRIES +#define MAX_ODT_ENTRIES 11 +#endif + +#define MAX_TRACE_REGION 5 +#define MAX_TRACE_CACHE_TYPE 2 + +// +// DIMM timings +// +typedef struct { + UINT32 tCK; ///< Memory cycle time, in femtoseconds. + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode. + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency. + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time. + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time. + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time. + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time. + UINT32 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval. + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time. + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time. + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks. + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time. + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups. + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups. + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time. + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time. + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time. + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups. + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups. + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group. + UINT16 tCCD_L_WR; ///< Number of tCK cycles for the channel DIMM's minimum Write-to-Write delay for same bank group. + UINT8 Resv[2]; ///< Resv +} MRC_CH_TIMING; + +typedef struct { + UINT16 tRDPRE; ///< Read CAS to Precharge cmd delay +} MRC_IP_TIMING; + +/// +/// Memory SMBIOS & OC Memory Data Hob +/// +typedef struct { + UINT8 Status; ///< See MrcDimmStatus for the definition of this field. + UINT8 DimmId; + UINT32 DimmCapacity; ///< DIMM size in MBytes. + UINT16 MfgId; + UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DDR4 20 bytes as per JEDEC Spec, so reserving 20 bytes + UINT8 RankInDimm; ///< The number of ranks in this DIMM. + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation. + UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation. + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation. + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation. + UINT16 Speed; ///< The maximum capable speed of the device, in MHz + UINT8 MdSocket; ///< MdSocket: 0 = Memory Down, 1 = Socketed. Needed for SMBIOS structure creation. +} DIMM_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this channel should be used. + UINT8 ChannelId; + UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel. + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values. + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics. +} CHANNEL_INFO; + +typedef struct { + UINT8 Status; ///< Indicates whether this controller should be used. + UINT16 DeviceId; ///< The PCI device id of this memory controller. + UINT8 RevisionId; ///< The PCI revision id of this memory controller. + UINT8 ChannelCount; ///< Number of valid channels that exist on the controller. + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions. +} CONTROLLER_INFO; + +typedef struct { + UINT64 BaseAddress; ///< Trace Base Address + UINT64 TotalSize; ///< Total Trace Region of Same Cache type + UINT8 CacheType; ///< Trace Cache Type + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code + UINT8 Rsvd[2]; +} PSMI_MEM_INFO; + +/// This data structure contains per-SaGv timing values that are considered output by the MRC. +typedef struct { + UINT32 DataRate; ///< The memory rate for the current SaGv Point in units of MT/s + MRC_CH_TIMING JedecTiming; ///< Timings used for this entry's corresponding SaGv Point - derived from JEDEC SPD spec + MRC_IP_TIMING IpTiming; ///< Timings used for this entry's corresponding SaGv Point - IP specific +} HOB_SAGV_TIMING_OUT; + +/// This data structure contains SAGV config values that are considered output by the MRC. +typedef struct { + UINT32 NumSaGvPointsEnabled; ///< Count of the total number of SAGV Points enabled. + UINT32 SaGvPointMask; ///< Bit mask where each bit indicates an enabled SAGV point. + HOB_SAGV_TIMING_OUT SaGvTiming[HOB_MAX_SAGV_POINTS]; +} HOB_SAGV_INFO; + +typedef struct { + UINT8 Revision; + UINT16 DataWidth; ///< Data width, in bits, of this memory device + /** As defined in SMBIOS 3.0 spec + Section 7.18.2 and Table 75 + **/ + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3 + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz) + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz) + /** As defined in SMBIOS 3.0 spec + Section 7.17.3 and Table 72 + **/ + UINT8 ErrorCorrectionType; + + SiMrcVersion Version; + BOOLEAN EccSupport; + UINT8 MemoryProfile; + UINT32 TotalPhysicalMemorySize; + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist. + UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs. + UINT8 XmpConfigWarning; ///< If XMP capable DIMMs config support only 1DPC, but 2DPC is installed + BOOLEAN DynamicMemoryBoostTrainingFailed; ///< TRUE if Dynamic Memory Boost failed to train and was force disabled on the last full training boot. FALSE otherwise. + UINT16 Ratio; ///< DDR Frequency Ratio, used for programs that require ratios higher then 255 + UINT8 RefClk; + UINT32 VddVoltage[MAX_PROFILE_NUM]; + UINT32 VddqVoltage[MAX_PROFILE_NUM]; + UINT32 VppVoltage[MAX_PROFILE_NUM]; + UINT16 RcompTarget[MAX_PROFILE_NUM][MAX_RCOMP_TARGETS]; + UINT16 DimmOdt[MAX_PROFILE_NUM][MAX_DIMM][MAX_ODT_ENTRIES]; + CONTROLLER_INFO Controller[MAX_NODE]; + UINT32 NumPopulatedChannels; ///< Total number of memory channels populated + HOB_SAGV_INFO SagvConfigInfo; ///< This data structure contains SAGV config values that are considered output by the MRC. + BOOLEAN IsIbeccEnabled; + UINT16 TotalMemWidth; ///< Total Memory Width in bits from all populated channels + UINT16 PprDetectedErrors; ///< PPR: Counts of detected bad rows + UINT16 PprRepairFails; ///< PPR: Counts of repair failure + UINT16 PprForceRepairStatus; ///< PPR: Force Repair Status +} MEMORY_INFO_DATA_HOB; + +/** + Memory Platform Data Hob + + Revision 1: + - Initial version. + Revision 2: + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields +**/ +typedef struct { + UINT8 Revision; + UINT8 Reserved[3]; + UINT32 BootMode; + UINT32 TsegSize; + UINT32 TsegBase; + UINT32 PrmrrSize; + UINT64 PrmrrBase; + UINT32 GttBase; + UINT32 MmioSize; + UINT32 PciEBaseAddress; + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE]; + PSMI_MEM_INFO PsmiRegionInfo[MAX_TRACE_REGION]; + BOOLEAN MrcBasicMemoryTestPass; +} MEMORY_PLATFORM_DATA; + +typedef struct { + EFI_HOB_GUID_TYPE EfiHobGuidType; + MEMORY_PLATFORM_DATA Data; + UINT8 *Buffer; +} MEMORY_PLATFORM_DATA_HOB; + +#pragma pack (pop) + +#endif // _MEM_INFO_HOB_H_ diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 15b67703152..47444d38c1b 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -862,7 +862,7 @@ static void print_event_type(uint32_t event_type) printf("%s", tpm_event_types[event_type]); } -static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log) +static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log, size_t size) { const uint8_t zero_block[sizeof(struct tcpa_spec_entry)] = {0}; @@ -883,6 +883,13 @@ static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log) uint32_t len; struct tcpa_log_entry *log_entry = (void *)current; uint32_t event_type = le32toh(log_entry->event_type); + current += sizeof(struct tcpa_log_entry); + len = le32toh(log_entry->event_data_size); + + if (current + len >= (uintptr_t)spec_log + size) { + fprintf(stderr, "Invalid TPM1.2 log entry overflowing cbmem area\n"); + break; + } printf("TCPA log entry %u:\n", ++counter); printf("\tPCR: %d\n", le32toh(log_entry->pcr)); @@ -891,8 +898,6 @@ static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log) printf("\n"); printf("\tDigest: "); print_hex_line(log_entry->digest, SHA1_DIGEST_SIZE); - current += sizeof(struct tcpa_log_entry); - len = le32toh(log_entry->event_data_size); if (len != 0) { current += len; printf("\tEvent data: "); @@ -947,7 +952,7 @@ static uint32_t print_tpm2_digests(struct tcg_pcr_event2_header *log_entry) return current - (uintptr_t)&log_entry->digest_count; } -static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log) +static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log, size_t size) { const uint8_t zero_block[12] = {0}; /* Only PCR index, event type and digest count */ @@ -990,6 +995,12 @@ static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log) /* Now event size and event are left to be parsed */ len = le32toh(*(uint32_t *)current); current += sizeof(uint32_t); + + if (current + len >= (uintptr_t)tpm2_log + size) { + fprintf(stderr, "Invalid TPM2.0 log entry overflowing cbmem area\n"); + break; + } + if (len != 0) { printf("\tEvent data: %.*s\n", len, (const char *)current); current += len; @@ -1017,7 +1028,7 @@ static void dump_tpm_std_log(uint64_t addr, size_t size) tspec_entry->spec_version_minor == 2 && tspec_entry->spec_errata >= 1 && le32toh(tspec_entry->entry.event_type) == EV_NO_ACTION) { - parse_tpm12_log(tspec_entry); + parse_tpm12_log(tspec_entry, size); } else { fprintf(stderr, "Unknown TPM1.2 log specification\n"); } @@ -1030,7 +1041,7 @@ static void dump_tpm_std_log(uint64_t addr, size_t size) if (tcg_spec_entry->spec_version_major == 2 && tcg_spec_entry->spec_version_minor == 0 && le32toh(tcg_spec_entry->event_type) == EV_NO_ACTION) { - parse_tpm2_log(tcg_spec_entry); + parse_tpm2_log(tcg_spec_entry, size); } else { fprintf(stderr, "Unknown TPM2 log specification.\n"); } diff --git a/util/genbuild_h/genbuild_h.sh b/util/genbuild_h/genbuild_h.sh index b381ab27767..5a456cf88b7 100755 --- a/util/genbuild_h/genbuild_h.sh +++ b/util/genbuild_h/genbuild_h.sh @@ -79,6 +79,11 @@ printf "/* timesource: %s */\n" "${TIMESOURCE}" printf "#define COREBOOT_VERSION_TIMESTAMP %s\n" "${DATE}" printf "#define COREBOOT_ORIGIN_GIT_REVISION \"%s\"\n" "${GITREV}" +printf "#define DASHARO_VERSION \"%s\"\n" "$DASHARO_VERSION" +printf "#define DASHARO_MAJOR_VERSION %d\\n" "$DASHARO_MAJOR_VERSION" +printf "#define DASHARO_MINOR_VERSION %d\\n" "$DASHARO_MINOR_VERSION" +printf "#define DASHARO_PATCH_VERSION %d\\n" "$DASHARO_PATCH_VERSION" + printf "#define COREBOOT_EXTRA_VERSION \"%s\"\n" "${COREBOOT_EXTRA_VERSION}" printf "#define COREBOOT_MAJOR_VERSION %s\n" "${MAJOR_VER:-0}" printf "#define COREBOOT_MINOR_VERSION %s\n" "${MINOR_VER:-0}" diff --git a/util/ifdtool/ifdtool.c b/util/ifdtool/ifdtool.c index ace05e22652..cf726feacae 100644 --- a/util/ifdtool/ifdtool.c +++ b/util/ifdtool/ifdtool.c @@ -794,19 +794,220 @@ static void dump_fcba(const struct fcba *fcba, const struct fpsba *fpsba) } } +static int ifd2_platform_get_hap_location(const struct fpsba *fpsba) +{ + switch (platform) { + case PLATFORM_SKLKBL: + /* No exceptions, always strap 0 */ + return 0; + case PLATFORM_IFD2: + printf("To change the AltMeDisable/HAP bit please provide the platform as parameter\n"); + return -1; + case PLATFORM_CNL: + /* + * This gets little tricky here. + * 1. CNL/CFL/CML-LP strap 106 (FPSBA + 0x70), but + * FSPBA + 0x70 bits 15:4 set to 0x1b + * FPSBA + 0x80 strap has configurable bits, + * FPSBA + 0x82/0x83 bytes are set to zeros, + * FPSBA + 0x00 is set to zeros, + * 2. CML-V strap 0 (FPSBA + 0x00) with bits 15:2 set to 0x00, but + * FSPBA + 0x00 bits 15:2 must be set to 0, + * FPSBA + 0x00 bits 23:22 must be set to 0x2, + * FPSBA + 0x70 is set to all zeros, + * FPSBA + 0x80 byte has configurable bits, + * FPSBA + 0x81/0x82 bytes are set to zeros. + * 3. CML-H/S strap 123 (FPSBA + 0x80), but + * FSPBA + 0x80 bits 15:4 set to 0x1b + * FPSBA + 0x00/0x70 is set to all zeros. + * + * So we do like this: + * + * 1. Prioritize CML-V detection as strap 0 cannot be all zeros. + * 2. Then heck if FSPBA + 0x70 is zero for CML-H/S, CNL/CFL/CML-LP + * cannot have FPSBA + 0x70 all zeros. + */ + if (fpsba->pchstrp[0] != 0) { + /* CML-V, one more safetycheck ot exclude other SKUs */ + if (fpsba->pchstrp[0x70 / 4] == 0) { + printf("Detected Comet Lake V platform flash descriptor\n"); + return 0; + } + } else { + /* Do safety check for CML-H/S to be sure */ + if (fpsba->pchstrp[0x70 / 4] == 0) { + printf("Detected Comet Lake H/S platform flash descriptor\n"); + return 0x80 / 4; + } + /* Do safety check for CNL/CFL/CML-LP to be sure */ + if (((fpsba->pchstrp[0x70 / 4] >> 4) & 0xfff) == 0x1b) { + printf("Detected Cannon Lake/Coffee Lake/Comet Lake LP " + "platform flash descriptor\n"); + return 0x70 / 4; + } + } + printf("Unusual Cannon Lake/Coffee Lake/Comet Lake flash descriptor detected\n" + "Not modifying flash descriptor\n"); + return -1; + case PLATFORM_TGL: + /* + * RKL-H/TGL-H strap 141 (FPSBA + 0x94), but + * FPSBA + 0x94 bits 8:1 set to 0x18. + * FPSBA + 0x7c must be zero. + * TGL-LP has non-zero FPSBA + 0x7c. + */ + if ((((fpsba->pchstrp[0x94 / 4] >> 1) & 0xff) == 0x18) && + (fpsba->pchstrp[0x7c / 4] == 0)) { + printf("Detected Rocket Lake H/Tiger Lake H platform " + "flash descriptor\n"); + return 0x94 / 4; + } + /* + * TGL-LP strap 114 (FPSBA + 0x7c), but + * FSPBA + 0x7c bits 8:1 set to 0x18 + * FPSBA + 0x92/0x93/0x94/0x95 must be all zeros. + * TGL-H has non-zero FPSBA + 0x94/0x95. + */ + if ((((fpsba->pchstrp[0x7c / 4] >> 1) & 0xff) == 0x18) && + (((fpsba->pchstrp[0x94 / 4] >> 16) & 0xffff) == 0)) { + printf("Detected Tiger Lake LP platform flash descriptor\n"); + return 0x7c / 4; + } + + printf("Unusual Tiger Lake flash descriptor detected\n" + "Not modifying flash descriptor\n"); + return -1; + case PLATFORM_ADL: + /* + * This gets little tricky here. + * 1. RPL-P/ADL-N/P strap 114 (FSPBA + 0x7c), but + * FPSBA + 0x7c bits 8:1 set to 0x18, + * FPSBA + 0xdc strap has configurable bits, + * FPSBA + 0xd0 must be set to 0x00000300. + * 2. ADL-S B0 step/RPL-S strap 193 (FSPBA + 0xdc), but + * FPSBA + 0xdc bits 8:1 set to 0x58, + * FPSBA + 0x7c strap has configurable bits, + * FPSBA + 0xd0 must be set to 0x10081008. + * 3. ADL-S A0 step strap 183 (FSPBA + 0xd0), but + * FPSBA + 0xd0 bits 8:1 set to 0x58, + * FPSBA + 0x7c/0xdc straps have configurable bits, however + * analogically to 0xdc vs. 0xd0, the FPSBA + (0xd0 - 0x0c) + * must be 0x10081008. + * + * So we do like this: + * + * 1. Prioritize ADL-S detection by checking 0xd0/0xdc bits 8:1 + * and 0xd0/0xc4 straps are set to 0x10081008. + * 2. ADL-S and ADL-N/P is mutually exclusive due to 0xd0 + * reserved values. SO 0xd0 can be used to distinguish all + * SKUs. + */ + if (fpsba->pchstrp[0xd0 / 4] == 0x10081008) { + /* ADL-S B0 step/RPL-S, do safety check to be sure */ + if (((fpsba->pchstrp[0xdc / 4] >> 1) & 0xff) == 0x58) { + printf("Detected Raptor Lake S/Alder Lake S B0" + " step platform flash descriptor\n"); + return 0xdc / 4; + } + } else if (fpsba->pchstrp[0xd0 / 4] == 0x00000300) { + /* RPL-P/ADL-N/P, do safety check to be sure */ + if (((fpsba->pchstrp[0x7c / 4] >> 1) & 0xff) == 0x18) { + printf("Detected Raptor Lake P/Alder Lake P/N" + " platform flash descriptor\n"); + return 0x7c / 4; + } + } else if (((fpsba->pchstrp[0xd0 / 4] >> 1) & 0xff) == 0x58) { + /* ADL-S A0 step, do safety check to be sure */ + if (fpsba->pchstrp[0xc4 / 4] == 0x10081008) { + printf("Detected Alder Lake S A0 step platform" + " flash descriptor\n"); + return 0xd0 / 4; + } + } + printf("Unusual Alder Lake flash descriptor detected\n" + "Not modifying flash descriptor\n"); + return -1; + case PLATFORM_MTL: + /* MTL-U/H strap 225 (FPSBA + 0x11c) */ + return 0x11c / 4; + case PLATFORM_ICL: + /* + * ICX-D strap 56 (FPSBA + 0xe0), unconfirmed. + * ICX-D FPSBA + 0x78 must be zero. + */ + if ((((fpsba->pchstrp[0xe0 / 4] >> 1) & 0xff) == 0x98) && + (fpsba->pchstrp[0x78 / 4] == 0)) { + printf("Detected Ice Lake D platform flash descriptor\n"); + return 0xe0 / 4; + } + /* + * ICL-LP strap 113 (FPSBA + 0x78), but + * FSPBA + 0x78 bits 9:1 set to 0x98. + * FPSBA + 0xe0 must be 0x68070000. + */ + if ((((fpsba->pchstrp[0x78 / 4] >> 1) & 0xff) == 0x98) && + (fpsba->pchstrp[0xe0 / 4] == 0x68070000)) { + printf("Detected Ice Lake LP platform flash descriptor\n"); + return 0x94 / 4; + } + + printf("Unusual Ice Lake flash descriptor detected\n" + "Not modifying flash descriptor\n"); + return -1; + case PLATFORM_LBG: + /* LBG strap 53 (FPSBA + 0xd4) */ + return 0xd4 / 4; + case PLATFORM_DNV: + /* DNV strap 14 (FPSBA + 0x38) */ + return 0x38 / 4; + case PLATFORM_APL: + case PLATFORM_GLK: + /* + * Strap 10 (FPSBA + 0x2c), but can be only set through SMIP? + * Couldn't get it to work on GLK. + */ + return 0x2c / 4; + case PLATFORM_JSL: + /* JSL strap 113 (FSPBA + 0x68) */ + return 0x68 / 4; + case PLATFORM_EHL: + /* EHL strap 122 (FSPBA + 0x84) */ + return 0x84 / 4; + default: + printf("HAP bit location unknown for selected platform\n" + "Not modifying flash descriptor\n"); + return -1; + } +} + static void dump_fpsba(const struct fdbar *fdb, const struct fpsba *fpsba) { unsigned int i; /* SoC Straps, aka PSL, aka ISL */ unsigned int SS = (fdb->flmap1 >> 24) & 0xff; + int loc; + bool hap_state; printf("Found PCH Strap Section\n"); for (i = 0; i < SS; i++) printf("PCHSTRP%-3u: 0x%08x\n", i, fpsba->pchstrp[i]); if (ifd_version >= IFD_VERSION_2) { + loc = ifd2_platform_get_hap_location(fpsba); + + if (loc == -1) { + printf("\n"); + return; + } + + /* Special case for APL/GLK */ + if (platform == PLATFORM_APL || platform == PLATFORM_GLK) + hap_state = !!(fpsba->pchstrp[loc] & (1 << 7)); + else + hap_state = !!(fpsba->pchstrp[loc] & (1 << 16)); + printf("HAP bit is %sset\n", - fpsba->pchstrp[0] & (1 << 16) ? "" : "not "); + hap_state ? "" : "not "); } else if (chipset >= CHIPSET_ICH8 && chipset <= CHIPSET_ICH10) { printf("ICH_MeDisable bit is %sset\n", fpsba->pchstrp[0] & 1 ? "" : "not "); @@ -1890,14 +2091,29 @@ static void set_pchstrap(struct fpsba *fpsba, const struct fdbar *fdb, const int /* Set the AltMeDisable (or HAP for >= IFD_VERSION_2) */ static void fpsba_set_altmedisable(struct fpsba *fpsba, struct fmsba *fmsba, bool altmedisable) { + int loc; + if (ifd_version >= IFD_VERSION_2) { + loc = ifd2_platform_get_hap_location((const struct fpsba *)fpsba); + + if (loc == -1) + return; + printf("%sting the HAP bit to %s Intel ME...\n", altmedisable ? "Set" : "Unset", altmedisable ? "disable" : "enable"); - if (altmedisable) - fpsba->pchstrp[0] |= (1 << 16); - else - fpsba->pchstrp[0] &= ~(1 << 16); + /* Special case for APL/GLK */ + if (platform == PLATFORM_APL || platform == PLATFORM_GLK) { + if (altmedisable) + fpsba->pchstrp[loc] |= (1 << 7); + else + fpsba->pchstrp[loc] &= ~(1 << 7); + } else { + if (altmedisable) + fpsba->pchstrp[loc] |= (1 << 16); + else + fpsba->pchstrp[loc] &= ~(1 << 16); + } } else { if (chipset >= CHIPSET_ICH8 && chipset <= CHIPSET_ICH10) { printf("%sting the ICH_MeDisable, MCH_MeDisable, " diff --git a/util/msi/Makefile.mk b/util/msi/Makefile.mk new file mode 100644 index 00000000000..6079cbf24d8 --- /dev/null +++ b/util/msi/Makefile.mk @@ -0,0 +1,39 @@ +TOOLCPPFLAGS += -include $(top)/src/commonlib/bsd/include/commonlib/bsd/compiler.h + +MSIROMHOLETOOL:= $(objutil)/msi/romholetool + +$(MSIROMHOLETOOL): $(dir)/romholetool/romholetool.c + printf " HOSTCC Creating MSI ROMHOLE tool\n" + mkdir -p $(objutil)/msi + $(HOSTCC) $(TOOLCPPFLAGS) $< -o $@ + +ifeq ($(CONFIG_VENDOR_MSI)$(CONFIG_BOARD_HAS_MSI_ROMHOLE),yy) + +ifeq ($(CONFIG_MSI_ROMHOLE_IN_CBFS),y) + +$(obj)/mainboard/$(MAINBOARDDIR)/romhole.bin: $(MSIROMHOLETOOL) + printf " TOOL Creating MSI ROMHOLE blob\n" + $(MSIROMHOLETOOL) -a $(CONFIG_MSI_ROMHOLE_ADDRESS_IN_CBFS) \ + -s $(CONFIG_MSI_ROMHOLE_SIZE_IN_CBFS) -o $@ + + +cbfs-files-y += msi_romhole.bin + +msi_romhole.bin-file := $(obj)/mainboard/$(MAINBOARDDIR)/romhole.bin +msi_romhole.bin-type := raw +msi_romhole.bin-compression := none +msi_romhole.bin-position := $(CONFIG_MSI_ROMHOLE_ADDRESS_IN_CBFS) + +else + +$(obj)/mainboard/$(MAINBOARDDIR)/romhole.bin: $(MSIROMHOLETOOL) $(obj)/fmap_config.h + printf " TOOL Creating MSI ROMHOLE blob\n" + $(MSIROMHOLETOOL) -l $(obj)/fmap_config.h -o $@ + +build_complete:: $(obj)/mainboard/$(MAINBOARDDIR)/romhole.bin + @printf " WRITE MSI ROMHOLE\n" + $(CBFSTOOL) $(obj)/coreboot.rom write -u -i 255 -r ROMHOLE -f $< + +endif + +endif diff --git a/util/msi/description.md b/util/msi/description.md new file mode 100644 index 00000000000..46305865bd4 --- /dev/null +++ b/util/msi/description.md @@ -0,0 +1,3 @@ +Tools for MSI platforms + +* _romholetool_ - Generates default MSI ROMHOLE blob for BIOS updates `C` diff --git a/util/msi/romholetool/romholetool.c b/util/msi/romholetool/romholetool.c new file mode 100644 index 00000000000..4fa8a2341ff --- /dev/null +++ b/util/msi/romholetool/romholetool.c @@ -0,0 +1,469 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define MiB (1024*1024) + +// TODO: take it as an input +#define ROMHOLE_MAGIC 0x10012501 +#define NUM_PWD_ENTRIES 2 +#define PWD_SIZE 40 +#define NUM_GD_ENTRIES 8 +#define GD_SIZE 48 +#define NUM_US_ENTRIES 8 +#define US_SIZE 0x3851 +#define TYPE2_SIZE 256 +#define FTB_SIZE 105 +#define FIB_SIZE 512 +#define FDP_SIZE 1024 +#define BUV_SIZE 1024 +#define NUM_VOLUMES 7 + +struct uuid_structure { + uint8_t magic0[4]; // always sSiD + uint16_t length; // structure length, always 0x1a + uint8_t magic1[3]; // awlays $uD + uint8_t space; // always 0x1 + uint8_t uuid[16]; // SMBIOS type 1 UUID +} __packed; + +struct pwd_entry { + uint8_t magic[3]; // always $s$ + uint8_t number; // ordinal number + uint8_t length; // length of pwd + uint8_t pwd[PWD_SIZE]; // password? +} __packed; + +struct pwd_structure { + uint8_t magic[4]; // always spWd + uint16_t length; // structure length + struct pwd_entry entries[NUM_PWD_ENTRIES]; +} __packed; + +struct gd_entry { + uint8_t magic[3]; // always $gD + uint8_t number; // ordinal number + uint16_t length; // length of gd + uint8_t gd[GD_SIZE]; // global data? +} __packed; + +struct gpdt_structure { + uint8_t magic[4]; // always gPdT + uint16_t length; // structure length + uint8_t num_entries; // number of entries + uint8_t space; // awlays zero + struct gd_entry entries[NUM_GD_ENTRIES]; +} __packed; + +struct us_entry { + uint8_t magic[3]; // always $uS + uint8_t number; // ordinal number + uint16_t length; // length of us + uint8_t us[US_SIZE]; // user data? +} __packed; + +struct ucsc_structure { + uint8_t magic[4]; // always uCsC + uint16_t length; // structure length + struct us_entry entries[NUM_US_ENTRIES]; +} __packed; + +struct type2_rw { + uint8_t magic0[4]; // always t2Rw + uint16_t length; // structure length + uint8_t magic1[3]; // always $tW + uint8_t space; // always 0x1 + uint8_t smbios_type2[TYPE2_SIZE]; // SMBIOS type2 table +} __packed; + +struct ftb_structure { + uint8_t magic0[4]; // always $FTB + uint16_t length; // structure length + uint8_t magic1[4]; // always $DIB + uint16_t space0; // always 0x2 + uint16_t size; // size of data field, always 105 + uint16_t space1; // always 0x0 + uint8_t magic2[4]; // always MFTD + uint8_t data[FTB_SIZE]; // default 0xfe +} __packed; + +struct fib_structure { + uint8_t magic0[4]; // always $FIB + uint16_t length; // structure length + uint16_t size; // size of data field, always 512 + uint8_t magic1[4]; // always $MFX + uint8_t data[FIB_SIZE]; // default 0xfa +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P since A.40/1.40 */ +struct fdp_structure { + uint8_t magic0[4]; // always $FDP + uint16_t length; // structure length + uint8_t magic1[3]; // always $Fd + uint8_t number; // always 0x1 + uint8_t data[FDP_SIZE]; // default 0xff +} __packed; + +/* Structure present in newer releases of MSI PRO Z790-P A.40/1.40 */ +struct buv_structure { + uint8_t magic0[4]; // always $BuV + uint16_t length; // structure length + uint8_t magic1[3]; // always $Bv + uint8_t number; // always 0x1 + uint8_t data[BUV_SIZE]; // default 0xff +} __packed; + +struct volume_entry { + uint8_t number; // ordinal number in ascii + uint32_t address; // volume base address + uint32_t size; // volume size + uint8_t space; // always 0xff +} __packed; + +struct ris_structure { + uint8_t magic0[4]; // always $RiS + uint16_t length; // structure length + uint8_t magic1[4]; // always $RiT + /* Array below keep the addresses and sizes of UEFI Firmware Volumes */ + struct volume_entry volumes[NUM_VOLUMES]; +} __packed; + +/* Place the following struct in the ROMHOLE flash region with 64K/128K alignment */ +struct msi_romhole { + uint32_t magic0; // 0x10012501 + uint16_t length; // length of the structure + char magic1[4]; // always SYSD + uint32_t address; // romhole address in flash + uint32_t size; // romhole total size + uint8_t pad0[48]; // always 0xff + struct uuid_structure uuid; + struct pwd_structure pwd; + struct gpdt_structure gpdt; + struct ucsc_structure ucsc; + struct type2_rw t2rw; + struct ftb_structure ftb; + struct fib_structure fib; + struct fdp_structure fdp; + struct buv_structure buv; + struct ris_structure ris; + // the rest is padded with 0xff by cbfstool +} __packed; + +static const char *optstring = "i:a:s:l:o:h"; + +static struct option long_options[] = { + {"layout", required_argument, 0, 'l' }, + {"address", required_argument, 0, 'a' }, + {"size", required_argument, 0, 's' }, + {"output", required_argument, 0, 'o' }, + {"help", no_argument, 0, 'h' }, +}; + +static void usage(void) +{ + printf("romholetool: Create ROMHOLE for MSI BIOS updates compatibility\n"); + printf("Usage: romholetool [options] -i build.h -l fmap_config.h -o \n"); + printf(" romholetool [options] -i build.h -a 0xff7c0000 -s 0x20000 -o \n"); + printf("-l | --layout The fmap_config.h file to parse\n"); + printf("-a | --address The address of ROMHOLE in CBFS\n"); + printf("-s | --size The size of ROMHOLE in CBFS\n"); + printf("-o | --output The file to generate\n"); + printf("-h | --help Print this help\n"); +} + +static int bcd2int(int hex) +{ + if (hex > 0xff) + return -1; + return ((hex & 0xF0) >> 4) * 10 + (hex & 0x0F); +} + +static char *get_line(char *fn, char *match) +{ + ssize_t read; + char *line = NULL; + char *ret = NULL; + size_t len = 0; + + FILE *fp = fopen(fn, "r"); + if (fp == NULL) { + fprintf(stderr, "E: Couldn't open file '%s'\n", fn); + return NULL; + } + + while ((read = getline(&line, &len, fp)) != -1) { + if (strstr(line, match) != NULL) { + ret = strdup(strstr(line, match) + strlen(match)); + break; + } + } + + if (!ret) + fprintf(stderr, "E: %s not found in %s\n", match, fn); + + fclose(fp); + return ret; +} + +static int get_line_as_int(char *fn, char *match, int bcd) +{ + int ret = -1; + char *s = get_line(fn, match); + if (s && strlen(s) > 0) { + char *endptr; + ret = strtol(s, &endptr, 0); + if (*endptr != '\0' && *endptr != '\n') { + fprintf(stderr, "E: Couldn't parse number for key '%s'\n", match); + return -1; + } + if (bcd) + ret = bcd2int(ret); + free(s); + } else { + fprintf(stderr, "E: Got invalid line for key '%s'\n", match); + } + + return ret; +} + +int main(int argc, char **argv) +{ + int c, i; + int ret = 1; + char *filename = NULL; + char *layoutfile = NULL; + char *addr_param = NULL; + char *size_param = NULL; + uint32_t flash_start, flash_size, romhole_addr, romhole_size; + struct msi_romhole *romhole = NULL; + + while (1) { + int optindex = 0; + + c = getopt_long(argc, argv, optstring, long_options, &optindex); + + if (c == -1) + break; + + switch (c) { + case 'a': + addr_param = strdup(optarg); + break; + case 's': + size_param = strdup(optarg); + break; + case 'l': + layoutfile = strdup(optarg); + break; + case 'o': + filename = strdup(optarg); + break; + case 'h': + ret = 0; /* fallthrough */ + case '?': + usage(); + goto out; + default: + break; + } + } + if (!layoutfile && (!addr_param || !size_param)) { + fprintf(stderr, "E: Must specify either a fmap_config.h filename or address and size\n"); + goto out; + } + if (!filename) { + fprintf(stderr, "E: Must specify a destination filename\n"); + goto out; + } + + if (layoutfile) { + flash_start = get_line_as_int(layoutfile, "FMAP_SECTION_FLASH_START", 0); + flash_size = get_line_as_int(layoutfile, "FMAP_SECTION_FLASH_SIZE", 0); + romhole_addr = get_line_as_int(layoutfile, "FMAP_SECTION_ROMHOLE_START", 0); + romhole_size = get_line_as_int(layoutfile, "FMAP_SECTION_ROMHOLE_SIZE", 0); + + // If flash is greater than 16 MiB, we have to adjust the start offset. + // Only 16MiB long BIOS region is mapped under 4G. + romhole_addr -= flash_start; + if ((flash_size > 16*MiB) && (romhole_addr > 16*MiB)) + romhole_addr -= 16*MiB; + + // The ROMHOLE structure needs the 32bit flash base address in host memory + romhole_addr += 0xff000000; + } else if (addr_param && size_param) { + romhole_addr = strtol(addr_param, NULL, 16); + romhole_size = strtol(size_param, NULL, 16); + } else { + fprintf(stderr, "E: Incorrect input parameters\n"); + goto out; + } + + if (romhole_size < 0x20000) { + fprintf(stderr, "E: The romhole flash region should be at least 128K\n"); + goto out; + } + + romhole = (struct msi_romhole *)malloc(romhole_size); + if (!romhole) { + fprintf(stderr, "E: Failed to allocate memory for the romhole\n"); + goto out; + } + + // Generate the table + + // Header + romhole->magic0 = ROMHOLE_MAGIC; + strncpy(romhole->magic1, "SYSD", 4); + romhole->address = romhole_addr; + romhole->size = romhole_size; + memset(romhole->pad0, 0xff, 48); + romhole->length = (uint16_t)sizeof(*romhole); + + // For some reason the actual data size is reduced by 64K + if (romhole_size > 0x10000) + romhole->length -= 0x10000; + + // Structures + + // UUID + strncpy(romhole->uuid.magic0, "sSiD", 4); + romhole->uuid.length = (uint16_t)sizeof(struct uuid_structure); + strncpy(romhole->uuid.magic1, "$uD", 3); + romhole->uuid.space = 1; + memset(romhole->uuid.uuid, 0xff, 16); + + // PWD + strncpy(romhole->pwd.magic, "spWd", 4); + romhole->pwd.length = (uint16_t)sizeof(struct pwd_structure); + for (i = 0; i < NUM_PWD_ENTRIES; i++) { + strncpy(romhole->pwd.entries[i].magic, "$s$", 3); + romhole->pwd.entries[i].number = i + 1; + romhole->pwd.entries[i].length = 0; + memset(romhole->pwd.entries[i].pwd, 0, 20); + } + + // GPDT + strncpy(romhole->gpdt.magic, "gPdT", 4); + romhole->gpdt.length = (uint16_t)sizeof(struct gpdt_structure); + romhole->gpdt.num_entries = NUM_GD_ENTRIES; + romhole->gpdt.space = 0; + for (i = 0; i < NUM_GD_ENTRIES; i++) { + strncpy(romhole->gpdt.entries[i].magic, "$gD", 3); + romhole->gpdt.entries[i].number = i + 1; + romhole->gpdt.entries[i].length = GD_SIZE; + memset(romhole->gpdt.entries[i].gd, 0xff, GD_SIZE); + } + + // UCSC + strncpy(romhole->ucsc.magic, "uCsC", 4); + romhole->ucsc.length = (uint16_t)sizeof(struct ucsc_structure); + for (i = 0; i < NUM_US_ENTRIES; i++) { + strncpy(romhole->ucsc.entries[i].magic, "$uS", 3); + // The first 6 entries are in order + if (i <= 5) + romhole->ucsc.entries[i].number = i + 1; + // The 7th entry and later start numeration from 'A' ascii + else + romhole->ucsc.entries[i].number = 0x41 + i - 6; + + romhole->ucsc.entries[i].length = US_SIZE; + memset(romhole->ucsc.entries[i].us, 0xff, US_SIZE); + } + + // T2RW + strncpy(romhole->t2rw.magic0, "t2Rw", 4); + romhole->t2rw.length = (uint16_t)sizeof(struct type2_rw); + strncpy(romhole->t2rw.magic1, "$tW", 3); + romhole->t2rw.space = 1; + memset(romhole->t2rw.smbios_type2, 0xff, TYPE2_SIZE); + + // FTB + strncpy(romhole->ftb.magic0, "$FTB", 4); + romhole->ftb.length = (uint16_t)sizeof(struct ftb_structure); + strncpy(romhole->ftb.magic1, "$DIB", 4); + romhole->ftb.space0 = 2; + romhole->ftb.size = FTB_SIZE; + romhole->ftb.space1 = 0; + strncpy(romhole->ftb.magic2, "MFTD", 4); + memset(romhole->ftb.data, 0xfe, FTB_SIZE); + + // FIB + strncpy(romhole->fib.magic0, "$FIB", 4); + romhole->fib.length = (uint16_t)sizeof(struct fib_structure); + romhole->fib.size = FIB_SIZE; + strncpy(romhole->fib.magic1, "$MFX", 4); + memset(romhole->fib.data, 0xfa, FIB_SIZE); + + // FDP + strncpy(romhole->fdp.magic0, "$FDP", 4); + romhole->fdp.length = (uint16_t)sizeof(struct fdp_structure); + strncpy(romhole->fdp.magic1, "$Fd", 3); + romhole->fdp.number = 1; + memset(romhole->fdp.data, 0xff, FDP_SIZE); + + // BUV + strncpy(romhole->buv.magic0, "$BuV", 4); + romhole->buv.length = (uint16_t)sizeof(struct buv_structure); + strncpy(romhole->buv.magic1, "$Bv", 3); + romhole->buv.number = 1; + memset(romhole->buv.data, 0xff, BUV_SIZE); + + // RIS + strncpy(romhole->ris.magic0, "$RiS", 4); + romhole->ris.length = (uint16_t)sizeof(struct ris_structure); + strncpy(romhole->ris.magic1, "$RiT", 4); + // We don't need to cary much about the UEFI volumes. The MSI BIOS update + // utilities will just copy the right values from the currently running BIOS. + memset(romhole->ris.volumes, 0xff, sizeof(romhole->ris.volumes)); + for (i = 0; i < NUM_VOLUMES; i++) { + // It seems there can be up to 8 volumes in total depending on the UEFI image + // layout, but last 8th entry did not match any of the UEFI volume addresses + // and additionally 7th entry is skipped. + if (i == NUM_VOLUMES - 1) + romhole->ris.volumes[i].number = 0x31 + NUM_VOLUMES; // ascii + else + romhole->ris.volumes[i].number = 0x31 + i; // ascii + romhole->ris.volumes[i].space = 0xff; + } + + // write the table + FILE *fd = fopen(filename, "wb"); + if (!fd) { + fprintf(stderr, "E: %s open failed: %s\n", filename, strerror(errno)); + goto out; + } + + if (fwrite(romhole, 1, sizeof(*romhole), fd) != sizeof(*romhole)) { + fprintf(stderr, "E: %s write failed: %s\n", filename, strerror(errno)); + fclose(fd); + goto out; + } + + if (fclose(fd)) { + fprintf(stderr, "E: %s close failed: %s\n", filename, strerror(errno)); + goto out; + } + + ret = 0; +out: + if (ret > 0) + fprintf(stderr, "E: Error creating '%s'\n", filename); + + free(filename); + + if (romhole) + free(romhole); + + exit(ret); + + return 0; +} diff --git a/util/txesbmantool/.gitignore b/util/txesbmantool/.gitignore new file mode 100644 index 00000000000..ed281d79ba6 --- /dev/null +++ b/util/txesbmantool/.gitignore @@ -0,0 +1 @@ +txesbmantool diff --git a/util/txesbmantool/Makefile b/util/txesbmantool/Makefile new file mode 100644 index 00000000000..2888361620d --- /dev/null +++ b/util/txesbmantool/Makefile @@ -0,0 +1,35 @@ +# txesbmantool - Utility for generating TXE Secure Boot manifests +# SPDX-License-Identifier: GPL-2.0-only + +CC ?= gcc +INSTALL ?= /usr/bin/env install +PREFIX ?= /usr/local + +HOSTCC ?= $(CC) +HOSTCFLAGS ?= $(CFLAGS) +top := ../.. +objutil ?= .. + +ifneq ($(PKG_CONFIG),) +HOSTPKGCONFIG ?= $(PKG_CONFIG) +else +HOSTPKGCONFIG ?= pkg-config +endif +HOSTCFLAGS += $(shell $(HOSTPKGCONFIG) --cflags wolfssl) +LDFLAGS ?= $(shell $(HOSTPKGCONFIG) --libs wolfssl) + +include Makefile.mk + +PROGRAM=$(objutil)/txesbmantool/txesbmantool + +all: $(PROGRAM) + +clean: + rm -f $(PROGRAM) *.o *~ .dependencies +distclean: clean + +install: $(PROGRAM) + $(INSTALL) -d $(DESTDIR)$(PREFIX)/bin + $(INSTALL) $(PROGRAM) $(DESTDIR)$(PREFIX)/bin + +.PHONY: all clean distclean install diff --git a/util/txesbmantool/Makefile.mk b/util/txesbmantool/Makefile.mk new file mode 100644 index 00000000000..ad03419ad70 --- /dev/null +++ b/util/txesbmantool/Makefile.mk @@ -0,0 +1,11 @@ +# SPDX-License-Identifier: BSD-3-Clause + +txesbmantoolsrc = txesbmantool.c + +TXESBMANTOOLCFLAGS = -Wall -Wextra -Wmissing-prototypes -Werror +TXESBMANTOOLCFLAGS += $(shell $(HOSTPKGCONFIG) --libs wolfssl) + +$(objutil)/txesbmantool/txesbmantool: $(addprefix $(top)/util/txesbmantool/,$(txesbmantoolsrc)) + printf " TXESBMANTOOL\n" + mkdir -p $(objutil)/txesbmantool + $(HOSTCC) $(HOSTCFLAGS) -o $@ $< $(TXESBMANTOOLCFLAGS) diff --git a/util/txesbmantool/README.md b/util/txesbmantool/README.md new file mode 100644 index 00000000000..2f095244f10 --- /dev/null +++ b/util/txesbmantool/README.md @@ -0,0 +1,247 @@ +# txesbmantool + +`txesbmantool` - utility generating the TXE Secure Boot manifests +(abbreviation of TXE Secure Boot Manifest Tool). The utility aims to help +develop, sign, and automate the creation process of TXE Secure Boot-supported +images. + +## Suported commands + +The txesbmantool supports the following commands: + +```txt +txesbmantool: Utility for generating TXE Secure Boot manifests +USAGE: + ./txesbmantool FILE COMMAND + + ./txesbmantool --help + + ./txesbmantool --version + +COMMANDs: + print + keyhash + verify --sbm-key-file [--km-key-file ] + generate-km --sbm-key-file --km-key-file [--km-id ] [--svn ] [-o ] + generate-sbm --sbm-key-file [--oem-data ] [--svn ] [-o ] + +OPTIONS: + -o : Output manifest file (optional) + --sbm-key-file : Secure Boot (SB) Manifest key file + --km-key-file : Key Manifest key file + --km-id : Key Manifest ID number (default 1) + --oem-data : Optional OEM data file to be included in SB Manifest + --svn : Security Version Number for the manifest (default 2), + Key Manifest SVN range 1-15, SB Manifest SVN range 0-63 +``` + +### `print` + +`print` - parses the input `FILE` and prints Key Manifest and Secure Boot +Manifest if found. Example output: + +```txt +./txesbmantool coreboot.rom print +Key Manifest: + Magic: $SKM + Version: 1 + Size: 1024 + Svn: 2 + Key Manifest ID: 0x01 + SB Key hash: E671B83E4BB9AAC11D1578D10999922EB4EBFCFB0A1E30A7A37DAF33163FA2BB + Key modulus: + 45 40 DC B5 21 AF 0A ED A0 1F DF 15 66 92 98 E1 + D6 3E 08 61 3E BC 45 8B 9B E7 A7 66 F3 56 DC 56 + 94 12 D1 D3 CB D1 F7 25 60 DA C9 DC 3C 8A 94 68 + 73 59 AB 99 CE 5F B8 CE F9 FD 9F 2B 5C FB FA B7 + 35 0C 5B 23 68 64 81 44 AB F3 BE 27 A3 10 A2 2E + F7 A1 F4 31 6A 59 17 6A A0 89 4B 6C 39 58 1F 4D + 97 6A 62 05 48 1C 21 22 A5 35 1A 64 A7 A0 A3 42 + 20 0E CC C7 71 99 24 83 DD 8F 4B 14 61 1A E0 2E + 70 52 2C 82 00 22 08 02 C7 17 0B 4D 9B DD BB A7 + 66 63 12 E7 74 4C 5E 9B C0 0C BC EC 49 D3 5B 6D + 49 E5 E0 20 96 8E 4B 39 74 28 DA 7A 7F 20 95 E4 + 7F 5C 4D 38 C9 57 12 49 04 BC B7 0B ED ED A2 69 + 12 83 0C C8 CE 56 3B 8D 04 A2 27 EA D1 05 52 51 + E4 A6 E8 3B 00 58 1D 9E 4D 33 00 9D 91 B6 36 AC + AA 48 C9 24 AD 50 59 E2 E4 00 B7 A5 9C 0E BC 0A + DF CB 47 A1 B7 F1 20 38 09 F2 BF EE 34 CA 52 C9 + Key exponent: 0x10001 + Signature: + 4C 00 31 A2 E6 DB 99 EC C6 B3 84 AE 9E 28 BC AE + 18 1A F8 09 B9 5A 38 6F A4 15 93 D5 F6 E6 C2 A5 + FC 9D 37 3E 80 41 0B AB 44 C7 86 33 26 1A CB AF + BC FD D6 8B 18 CA 65 75 15 5D 32 75 85 0B AB 86 + 82 B4 24 67 2C FE DD 2E BB 69 9F B8 4B 1D 80 84 + DE 09 C6 80 8B 46 0D D8 4C 4C 75 EC F2 61 67 CA + 6B A5 39 20 20 D3 29 72 65 98 82 A0 41 ED FF 9E + 68 44 CE 47 5D 90 DC C1 8E 7F 19 C6 A9 9A 27 DE + 16 B7 12 A5 5D EA 61 53 4B 17 E7 E3 5E 71 04 FE + 29 DE D4 0C 44 B2 19 1E A3 41 29 C6 C6 AE 4D C0 + CA 97 A0 53 B2 55 D5 CE E6 B1 45 5B 38 34 2A C1 + 16 5F 56 F4 66 87 8D 8C 75 89 D1 6F 2D 9E 0B FC + BF 16 C1 2F 53 DD AA 0A 0B 46 14 A5 0D 68 8F 24 + 45 F4 FB 4E 4A 99 8F 33 B6 D0 F9 70 42 ED F5 F6 + 63 87 BB 8C EB DD 6C 8E B5 62 EE EB C5 CC 94 DA + E5 B6 BF 1F 4A CA F6 F1 E8 D7 7C 79 AF 3B 6A C7 +Secure Boot Manifest: + Magic: $VBM + Version: 1 + Size: 1024 + Svn: 2 + IBB hash: C27838A5EB12A57CE3880896C83E7E437EF6D4DF94B8808A36C2779B0B3DE731 + OEM Data: + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 + Key modulus: + 59 8E 0E 9C 78 BA 84 9E 08 70 A0 2E 03 C9 EC 60 + 51 AD 75 77 6A BD D8 51 1E 2A B4 2C 3E 14 8C A9 + 5A AF 36 0F 6F 17 8C E3 C2 E6 40 0F 8A DF E0 1F + FC 31 74 31 A6 D3 E0 D5 01 4A D6 40 11 A5 CB 3A + 19 01 D6 4C 52 E0 47 B2 2E C2 3F CD E0 1B 53 51 + 9D C0 7D 6E D8 8D D7 D9 8E C3 FE 85 19 19 29 92 + 11 C3 B4 53 63 E6 61 12 C4 8B F9 0D 5F DB D1 50 + 64 CD 78 CB 10 0B 84 92 42 AE 1E 81 4E 57 CF 9F + D9 85 CA 4A F4 CE DA 03 BC 5E 0D 7C BD E9 EB 13 + C3 C3 C2 4D EF 21 08 15 5A EC EA E8 F8 CD C0 DE + 9B 57 55 DF B8 C4 40 27 18 29 A5 98 85 09 5C EF + DE 39 B5 A8 F5 69 D7 D2 1F A9 A4 9F D2 61 C5 82 + 1D 5E D0 3B 69 CA DF 8B A0 3F E4 C4 85 15 2D EB + F6 32 5F 70 1E DF 93 21 AD F7 65 40 E2 4B B0 26 + D2 DA F1 3C F0 9A A9 80 3C E6 F9 71 46 C1 5F 50 + 65 BE 70 80 3A 1A DA 51 79 75 04 B3 3F 17 FF AF + Key exponent: 0x10001 + Signature: + DF 5F B8 66 76 0F CC A9 93 C7 28 0F EF 32 14 7A + 1A 23 04 2A 75 85 24 0A 85 7F E5 B8 CE 24 44 C1 + D6 73 5B D6 30 BD A3 66 15 85 6A 3A 8E FC 8F 56 + 75 71 28 86 0F F3 E3 1C 20 A4 2E 33 15 45 E5 24 + 1A BB 69 A0 FD D8 7A A1 34 2E 7A 40 60 E1 4C 51 + D3 BB 73 BC 1A A5 43 E5 6F B6 54 4F 31 2A 65 9B + DD 1A BE 45 5A 7A E5 15 44 76 EC 94 89 33 14 11 + C6 18 39 ED 02 D7 B3 5C 56 23 2A 58 18 87 EE 2A + 0A F5 FD E9 5F 94 B3 92 17 21 59 3E A4 0F CF 4A + 99 95 33 FB AD 73 CF 1C 7F 1F CB 31 EC 2D 57 0D + 8B 3E DB CF D4 F0 62 26 26 0F D9 17 DD BC 3C 1F + 28 76 E4 81 D5 CF 04 BB 5D 33 82 D8 EB DA 64 45 + 14 A9 24 90 5D 93 E8 D6 34 1C 0C 2B 6F 18 4F DF + 45 6E EE 2A FB 00 D2 B7 BC 36 9D D9 91 FF A7 39 + 39 4D 96 48 DD 7C 43 29 73 7F 6A 8A 73 F2 B0 57 + E4 B7 2A 34 A1 F1 83 A5 7F A7 17 6C 1A E2 EC 26 +``` + +### `verify` + +`verify` - parses the input `FILE` and verifies whether the input `FILE` has +been correctly signed for TXE Secure Boot. Additional input parameters are +paths to the private signing keys to perform verification. If the image is +expected to have a Key Manifest, one must also pass the key used to sign Key +Manifest. The tool will also print the expected TXE image configuration. +Example output: + +```txt +./txesbmantool coreboot.rom verify \ + --sbm-key-file sb_privkey_sample.pem \ + --km-key-file oem_privkey_sample.pem +Verifying Key Manifest... +Key Manifest verification successful! + +TXE image should be provisioned with the following key hash: +AE6491B401B639DB9FA6E86D22FACE37F846E506328FDBF4327802C271FFE6FF +TXE should be provisioned with the following Key Manifest ID: 0x01 + +Verifying Secure Boot Manifest... +Secure Boot Manifest verification is successful! +``` + +If the Key Manifest is found in the binary but the `--km-key-file` was not +passed with a valid key, the tool will output an error: + +```txt +ERROR: Key Manifest key file not given, but Key Manifest found in the input file +ERROR: Can not verify Key Manifest! +``` + +### `generate-km` + +`generate-km` - creates a signed Key Manifest and injects it into the input +`FILE`. Secure Boot Manifest key is taken as `--sbm-key-file ` parameter +and Key Manifest key as `--km-key-file ` parameter. Key Manifest is used +to authorize a Secure Boot Manifest key that will be eligible to sign Secure +Boot Manifests. One may optionally provide a custom Key Manifest ID +(`--km-id`), SVN (`--svn`), and save the resulting Key Manifest as a separate +file with `-o` parameter. Example: + +```txt +./txesbmantool coreboot.rom generate-km \ + --sbm-key-file sb_privkey_sample.pem \ + --km-key-file oem_privkey_sample.pem \ + --km-id 1 --svn 2 +SHA256 of the Secure Boot Manifest Key (Little Endian): +E671B83E4BB9AAC11D1578D10999922EB4EBFCFB0A1E30A7A37DAF33163FA2BB + +Key Manifest generated successfully +``` + +### `generate-sbm` + +`generate-sbm` - creates a signed Secure Boot Manifest and injects it to the +input `FILE`. Secure Boot Manifest key is taken as `--sbm-key-file ` +parameter. The Secure Boot Manifest contains the hash of the IBB that is being +verified by TXE. One may optionally provide a custom SVN (`--svn`) and save +the resulting Key Manifest as a separate file with `-o` parameter. Example: + +```txt +./txesbmantool coreboot.rom generate-sbm \ + --sbm-key-file sb_privkey_sample.pem \ + --svn 2 +SHA256 of the IBB (Little Endian): +C27838A5EB12A57CE3880896C83E7E437EF6D4DF94B8808A36C2779B0B3DE731 + +Secure Boot Manifest generated successfully +``` + +The utility may also take an additional max 400 bytes block of data as +`--oem-data` parameter. It is not used by hardware, however, it is verified as +a part of the manifest verification and can be used for any purpose. +Currently, coreboot does not use it at all, as there is no need for it. + +### `keyhash` + +`keyhash` - takes a key as an input `FILE` and prints out the SHA256 of the +key modulus+exponent. It is useful when preparing the TXE image for Secure +Boot, where one needs to provide the SHA256 of the key to be set in the +fuses/emulated fuses. Example: + +```txt +./txesbmantool oem_privkey_sample.pem keyhash +SHA256 of RSA key 'oem_privkey_sample.pem': +AE6491B401B639DB9FA6E86D22FACE37F846E506328FDBF4327802C271FFE6FF +``` + +In the above example, the hash corresponds to the key used to sign the Key +Manifest. The same hash can be found in the example output of `verify` +command. diff --git a/util/txesbmantool/description.md b/util/txesbmantool/description.md new file mode 100644 index 00000000000..f16c10f2d00 --- /dev/null +++ b/util/txesbmantool/description.md @@ -0,0 +1 @@ +Generates Secure Boot Manifests for TXE Secure Boot `C` diff --git a/util/txesbmantool/txesbmantool.c b/util/txesbmantool/txesbmantool.c new file mode 100644 index 00000000000..22b001ff425 --- /dev/null +++ b/util/txesbmantool/txesbmantool.c @@ -0,0 +1,1455 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +#ifndef WOLFSSL_USER_SETTINGS + #include +#endif + +#include +#include +#include +#include +#include + +#ifndef ARRAY_SIZE +#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0])) +#endif + +#define WARN(...) fprintf(stderr, "WARNING: " __VA_ARGS__) +#define ERROR(...) fprintf(stderr, "ERROR: " __VA_ARGS__) + +#define RSA_KEY_SIZE 2048 +#define RSA_KEY_EXPONENT 0x10001 +#define DER_FILE_BUFFER 2048 /* max DER size */ + +#define MANIFEST_SIZE 1024 + +#define SB_MANIFEST_MAGIC 0x4d425624 /* $VBM in LE */ +#define SB_MANIFEST_VERSION 0x1 +#define SB_MANIFEST_SIZE MANIFEST_SIZE + +#define KEY_MANIFEST_MAGIC 0x4d4b5324 /* $SKM in LE */ +#define KEY_MANIFEST_VERSION 0x1 +#define KEY_MANIFEST_PAD_SIZE (4096 - MANIFEST_SIZE) +#define KEY_MANIFEST_RESERVED_SIZE 456 +#define KEY_MANIFEST_SIZE (MANIFEST_SIZE + KEY_MANIFEST_PAD_SIZE) + +#define IBB_SIZE (0x20000 - SB_MANIFEST_SIZE) + +static const char tool_version[] = "0.1"; + +struct manifest_header { + uint32_t magic; + uint32_t version; + uint32_t size; + uint32_t svn; +} __attribute__((packed)); + +struct key_signature { + uint8_t modulus[256]; + uint32_t exponent; + uint8_t signature[256]; +} __attribute__((packed)); + +struct manifest { + struct manifest_header header; + uint32_t km_id; /* Only for Key Manifest */ + uint8_t hash[WC_SHA256_DIGEST_SIZE]; /* IBB hash of SBM, Key hash for KM */ + union { + struct { + uint32_t reserved1; + uint32_t reserved2[8]; + uint8_t oem_data[400]; + uint8_t reserved3[20]; + } sb; + uint8_t reserved[KEY_MANIFEST_RESERVED_SIZE]; + }; + struct key_signature key_sig; +} __attribute__((packed)); + +_Static_assert(sizeof(struct manifest) == MANIFEST_SIZE, "Wrong size of Manifest structure"); + +static struct params { + const char *output; + const char *file_name; + const char *oem_data_file; + const char *sbm_key_file; + const char *km_key_file; + bool override_km_id; + uint32_t km_id; + bool override_svn; + uint32_t svn; +} params; + +static off_t get_file_size(FILE *f) +{ + off_t fsize; + fseek(f, 0, SEEK_END); + fsize = ftell(f); + fseek(f, 0, SEEK_SET); + return fsize; +} + +static bool mem_is_zero(const byte *memory, word32 size) +{ + for (word32 i = 0; i < size; i++) { + if (memory[i] == 0) + continue; + else + return false; + } + + return true; +} + +static void hexdump(const void *buffer, word32 len, byte cols, word32 indent) +{ + word32 i, j; + + if (len > 0) { + for (j = 0; j < indent; j++) + printf("\t"); + } + + for (i = 0; i < len + ((len % cols) ? (cols - len % cols) : 0); i++) + { + /* print hex data */ + if (i < len) { + printf("%02X ", ((byte*)buffer)[i] & 0xFF); + } + + if (i % cols == (word32)(cols - 1)) { + printf("\n"); + if (i != (len - 1)) { + for (j = 0; j < indent; j++) + printf("\t"); + } + } + } +} + +static void print_sha256(const byte *buffer) +{ + for (word32 i = 0; i < WC_SHA256_DIGEST_SIZE; i++) + printf("%02X", buffer[i]); + + printf("\n"); +} + +static void print_magic(uint32_t magic) +{ + printf("%c%c%c%c\n", + (unsigned char)(magic & 0xff), + (unsigned char)((magic >> 8) & 0xff), + (unsigned char)((magic >> 16) & 0xff), + (unsigned char)((magic >> 24) & 0xff)); +} + +static int swap_bytes(byte *buffer, word32 len) +{ + byte *tmp; + + if (len <= 0 || buffer == NULL) + return EXIT_FAILURE; + + tmp = malloc(len); + + if (!tmp) + return EXIT_FAILURE; + + memcpy(tmp, buffer, len); + + for (word32 i = 0; i < len; i++) { + buffer[i] = tmp[len - 1 - i]; + } + + free(tmp); + + return 0; +} + +static int rsa_load_key_file(const char *keyFile, RsaKey *rsaKey) +{ + int ret = EXIT_FAILURE; + FILE *file; + byte *buffer = NULL; + word32 bufSize = DER_FILE_BUFFER; + byte *derBuffer = NULL; + word32 derBufSize = DER_FILE_BUFFER; + word32 bytes = 0; + word32 idx = 0; + + file = fopen(keyFile, "rb"); + if (file) { + buffer = malloc(bufSize); + if (buffer) { + bytes = fread(buffer, 1, bufSize, file); + } + fclose(file); + } + + derBuffer = malloc(derBufSize); + + if (buffer != NULL && bytes > 0 && derBuffer != NULL) { + ret = wc_KeyPemToDer(buffer, bytes, derBuffer, derBufSize, NULL); + + if (ret < 0) { + free(derBuffer); + } else { + free(buffer); + buffer = derBuffer; + bytes = (word32)ret; + } + + ret = wc_RsaPrivateKeyDecode(buffer, &idx, rsaKey, (word32)bytes); + } + + if (buffer) { + free(buffer); + } + + return ret; +} + +static int calculate_key_hash(RsaKey *rsaKey, byte *key_hash) +{ + int ret; + wc_Sha256 sha256; + uint8_t modulus[256]; + uint32_t exponent = 0; + word32 e_size = sizeof(exponent); + word32 n_size = sizeof(modulus); + + ret = wc_RsaFlattenPublicKey(rsaKey, (byte *)&exponent, &e_size, + (byte *)&modulus, &n_size); + if (ret != 0) { + ERROR("Failed to extract Secure Boot Manifest Key exponent and modulus!\n"); + return ret; + } + + if (swap_bytes(modulus, n_size)) { + ERROR("Failed to change RSA key modulus endianess!\n"); + return EXIT_FAILURE; + } + + ret = wc_InitSha256(&sha256); + if (ret != 0) { + ERROR("Failed to initialize SHA256 context\n"); + return ret; + } + + ret = wc_Sha256Update(&sha256, modulus, n_size); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + /* e_size returned is 3, but we have to take whole uint32_t */ + ret = wc_Sha256Update(&sha256, (byte *)&exponent, sizeof(exponent)); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + ret = wc_Sha256Final(&sha256, key_hash); + if (ret != 0) { + ERROR("Failed to generate SHA256 hash\n"); + return ret; + } + + if (swap_bytes(key_hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Failed to change SHA256 hash endianess!\n"); + return EXIT_FAILURE; + } + + return ret; +} + +static int calculate_ibb_hash(const byte *buffer, byte *ibb_hash) +{ + int ret; + wc_Sha256 sha256; + + ret = wc_InitSha256(&sha256); + if (ret != 0) { + ERROR("Failed to initialize SHA256 context\n"); + return ret; + } + + ret = wc_Sha256Update(&sha256, buffer, IBB_SIZE); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + ret = wc_Sha256Final(&sha256, ibb_hash); + if (ret != 0) { + ERROR("Failed to generate SHA256 hash\n"); + return ret; + } + + if (swap_bytes(ibb_hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Failed to change SHA256 hash endianess!\n"); + return EXIT_FAILURE; + } + + return ret; +} + +static int create_sb_manifest(struct manifest *man, byte* romBuf, word32 romLen, byte* oemData, + word32 oemDataLen, word32 manifestSVN) +{ + int ret; + byte *sha256_buffer; + size_t file_size = IBB_SIZE + SB_MANIFEST_SIZE; + + if (romLen < file_size) { + ERROR("ROM file too small\n"); + return EXIT_FAILURE; + } + + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != 32) { + ERROR("Hash type SHA256 not supported!\n"); + return EXIT_FAILURE; + } + + memset((byte *)man, 0, MANIFEST_SIZE); + + man->header.magic = SB_MANIFEST_MAGIC; + man->header.version = SB_MANIFEST_VERSION; + man->header.svn = manifestSVN; + man->header.size = MANIFEST_SIZE; + + if (oemData != NULL && oemDataLen > 0) { + if (oemDataLen <= sizeof(man->sb.oem_data)) + memcpy((byte *)man->sb.oem_data, oemData, oemDataLen); + else + WARN("OEM Data file length too big, ignoring it.\n"); + } + + ret = calculate_ibb_hash(&romBuf[romLen - IBB_SIZE], man->hash); + if (ret != 0) { + ERROR("Failed to calcualte IBB hash!\n"); + return ret; + } + + sha256_buffer = man->hash; + printf("SHA256 of the IBB (Little Endian):\n"); + print_sha256(sha256_buffer); + printf("\n"); + + return ret; +} + +static int create_key_manifest(struct manifest *man, word32 romLen, word32 manifestSVN) +{ + int ret; + RsaKey sbmKey; + size_t file_size = IBB_SIZE + SB_MANIFEST_SIZE + KEY_MANIFEST_SIZE; + + if (romLen < file_size) { + ERROR("ROM file too small\n"); + return EXIT_FAILURE; + } + + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != 32) { + ERROR("Hash type SHA256 not supported!\n"); + return EXIT_FAILURE; + } + + memset((byte *)man, 0, MANIFEST_SIZE); + + man->header.magic = KEY_MANIFEST_MAGIC; + man->header.version = KEY_MANIFEST_VERSION; + man->header.svn = manifestSVN; + man->header.size = MANIFEST_SIZE; + + if (params.override_km_id) + man->km_id = params.km_id; + else + man->km_id = 1; + + ret = wc_InitRsaKey(&sbmKey, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + return ret; + } + + ret = rsa_load_key_file(params.sbm_key_file, &sbmKey); + if (ret != 0) { + ERROR("Failed to load Secure Boot Manifest Key!\n"); + return ret; + } + + ret = calculate_key_hash(&sbmKey, man->hash); + if (ret != 0) { + ERROR("Failed to calcualte Secure Boot key hash!\n"); + wc_FreeRsaKey(&sbmKey); + return ret; + } + + printf("SHA256 of the Secure Boot Manifest Key (Little Endian):\n"); + print_sha256(man->hash); + printf("\n"); + + wc_FreeRsaKey(&sbmKey); + return ret; +} + +static int rsa_sign_manifest(struct manifest *man, const char *key_path) +{ + int ret; + RsaKey rsaKey; + WC_RNG rng; + byte *sigBuf = NULL; + word32 sigLen; + word32 e_size, n_size; + struct key_signature *key_struct = &man->key_sig; + + ret = wc_InitRng(&rng); + if (ret != 0) { + ERROR("Init RNG failed! %d\n", ret); + goto exit; + } + + ret = wc_InitRsaKey(&rsaKey, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + goto exit; + } + + ret = rsa_load_key_file(key_path, &rsaKey); + if (ret != 0) { + ERROR("Failed to load RSA key %s! (%d)\n", key_path, ret); + goto exit; + } + + e_size = sizeof(key_struct->exponent); + n_size = sizeof(key_struct->modulus); + + ret = wc_RsaFlattenPublicKey(&rsaKey, (byte *)&key_struct->exponent, &e_size, + (byte *)key_struct->modulus, &n_size); + + if (ret != 0) { + ERROR("Failed to write key modulus and exponent! %d\n", ret); + goto exit; + } + + /* Change endianess of the modulus to LE */ + if (swap_bytes((byte *)key_struct->modulus, n_size)) { + ERROR("Failed to change RSA Key modulus endianess!\n"); + goto exit; + } + + if (n_size * 8 != RSA_KEY_SIZE) { + ERROR("Incorrect RSA key size! %d != 2048\n", n_size * 8); + ret = EXIT_FAILURE; + goto exit; + } + + if (key_struct->exponent != RSA_KEY_EXPONENT) { + ERROR("Incorrect RSA key size! 0x%x != 0x10001\n", key_struct->exponent); + ret = EXIT_FAILURE; + goto exit; + } + + /* Verify hash type is supported */ + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != 32) { + ERROR("Hash type SHA256 not supported!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + sigLen = wc_SignatureGetSize(WC_SIGNATURE_TYPE_RSA_W_ENC, &rsaKey, sizeof(rsaKey)); + if (sigLen != sizeof(key_struct->signature)) { + ERROR("RSA Signature size check fail! %d\n", sigLen); + ret = EXIT_FAILURE; + goto exit; + } + + sigBuf = malloc(sigLen); + if (!sigBuf) { + ERROR("RSA Signature malloc failed!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + ret = wc_SignatureGenerate(WC_HASH_TYPE_SHA256, WC_SIGNATURE_TYPE_RSA_W_ENC, + (byte *)man, + MANIFEST_SIZE - sizeof(struct key_signature), + sigBuf, &sigLen, + &rsaKey, sizeof(rsaKey), + &rng); + if (ret < 0) { + ERROR("RSA signature generation failed (%d)!\n", ret); + goto exit; + } + + ret = wc_SignatureVerify(WC_HASH_TYPE_SHA256, WC_SIGNATURE_TYPE_RSA_W_ENC, + (byte *)man, + MANIFEST_SIZE - sizeof(struct key_signature), + sigBuf, sigLen, + &rsaKey, sizeof(rsaKey)); + if (ret < 0) { + ERROR("RSA Signature Verification failed: (%d)\n", ret); + goto exit; + } + + if (swap_bytes(sigBuf, sigLen)) { + ERROR("Failed to change RSA Signature endianess!\n"); + goto exit; + } + + memcpy(key_struct->signature, sigBuf, sigLen); +exit: + if (sigBuf) { + free(sigBuf); + } + wc_FreeRsaKey(&rsaKey); + wc_FreeRng(&rng); + + return ret; +} + +static int save_buffer_to_file(const char *filename, byte *buffer, word32 bufLen) +{ + int ret = 0; + FILE* file = NULL; + + file = fopen(filename, "wb"); + if (file == NULL) { + ERROR("Failed to create file %s!\n", filename); + ret = EXIT_FAILURE; + goto exit; + } + + if (fwrite(buffer, 1, bufLen, file) != bufLen) { + ERROR("Error writing %s file! %d", filename, ret); + ret = EXIT_FAILURE; + goto exit; + } + +exit: + if (file) { + fclose(file); + } + + return ret; +} + +static int load_file_to_buffer(const char *filename, byte **fileBuf, word32 *fileLen) +{ + int ret = 0; + FILE *file = NULL; + + file = fopen(filename, "rb"); + if (file == NULL) { + ERROR("File %s does not exist!\n", filename); + ret = EXIT_FAILURE; + goto exit; + } + + *fileLen = get_file_size(file); + /* + * To avoid undefined behavior when reading from potentially unaligned + * pointer, check that the file size is divisible by 4 bytes. Both manifests + * have such sizes (see SB_MANIFEST_SIZE and KEY_MANIFEST_SIZE), so this + * wouldn't fail for valid manifests. In case of coreboot.rom, the offsets are + * calculated relatively to the end of file, so the result may be misaligned if + * file size is misaligned. Instead of repeating checks for proper alignment in + * cmd_verify() and cmd_print(), do it here. + */ + if (*fileLen % sizeof(uint32_t)) { + ERROR("File size isn't a multiple of 4 bytes!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + *fileBuf = malloc(*fileLen); + if (!*fileBuf) { + ERROR("File buffer malloc failed!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (fread(*fileBuf, 1, *fileLen, file) != *fileLen) { + ERROR("Error reading file! %d", ret); + ret = EXIT_FAILURE; + goto exit; + } + +exit: + if (file) { + fclose(file); + } + + return ret; +} + +static int inject_manifest_to_binary(const char *filename, byte *fileBuf, word32 fileLen, + struct manifest *man) +{ + word32 file_size, offset; + + file_size = IBB_SIZE + SB_MANIFEST_SIZE; + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE; + + if (man->header.magic == KEY_MANIFEST_MAGIC) { + file_size += KEY_MANIFEST_SIZE; + offset -= KEY_MANIFEST_SIZE; + /* Key Manifest is 4K big with 3K padded with zeros after the manifest */ + memset(&fileBuf[offset], 0, KEY_MANIFEST_SIZE); + } else if (man->header.magic != SB_MANIFEST_MAGIC) { + ERROR("Invalid manifest type\n"); + return EXIT_FAILURE; + } + + if (fileLen < file_size) { + ERROR("ROM file too small to fit IBB and manifest(s)\n"); + return EXIT_FAILURE; + } + + memcpy(&fileBuf[offset], (byte *)man, MANIFEST_SIZE); + + return save_buffer_to_file(filename, fileBuf, fileLen); +} + +static int cmd_generate_sbm(void) +{ + int ret = 0; + word32 fileLen; + byte *fileBuf = NULL; + word32 oemDataFileLen = 0; + byte *oemDataFileBuf = NULL; + word32 manifest_svn = params.override_svn ? params.svn : 2; + struct manifest man; + + if (params.oem_data_file) { + ret = load_file_to_buffer(params.oem_data_file, &oemDataFileBuf, &oemDataFileLen); + if (ret < 0) { + ERROR("Failed to load OEM Data file\n"); + goto exit; + } + } + + if (params.file_name) { + ret = load_file_to_buffer(params.file_name, &fileBuf, &fileLen); + if (ret < 0) { + goto exit; + } + } else { + ERROR("coreboot image file not given\n"); + return -1; + } + + if (!params.sbm_key_file) { + ERROR("Secure Boot Manifest key file not given\n"); + return -1; + } + + if (manifest_svn > 63) { + ERROR("Secure Boot Manifest SVN %d invalid, allowed range: 0-63\n", manifest_svn); + ret = EXIT_FAILURE; + goto exit; + } + + ret = create_sb_manifest(&man, fileBuf, fileLen, oemDataFileBuf, oemDataFileLen, manifest_svn); + if (ret < 0) { + goto exit; + } + + ret = rsa_sign_manifest(&man, params.sbm_key_file); + if (ret < 0) { + goto exit; + } + + ret = inject_manifest_to_binary(params.file_name, fileBuf, fileLen, &man); + if (ret < 0) { + goto exit; + } + + printf("Secure Boot Manifest generated successfully\n"); + + if (params.output) { + printf("Saving Secure Boot Manifest as %s\n", params.output); + ret = save_buffer_to_file(params.output, (byte *)&man, MANIFEST_SIZE); + } else { + printf("Not saving Secure Boot Manifest as a file, not requested to\n"); + } + +exit: + if (fileBuf) { + free(fileBuf); + } + + if (oemDataFileBuf) { + free(oemDataFileBuf); + } + + return ret; +} + +static int cmd_generate_km(void) +{ + int ret = 0; + word32 fileLen; + byte *fileBuf = NULL; + word32 manifest_svn = params.override_svn ? params.svn : 2; + struct manifest man; + + if (params.file_name) { + ret = load_file_to_buffer(params.file_name, &fileBuf, &fileLen); + if (ret < 0) { + goto exit; + } + } else { + ERROR("coreboot image file not given\n"); + return EXIT_FAILURE; + } + + if (!params.km_key_file) { + ERROR("Key Manifest key file not given\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (!params.sbm_key_file) { + ERROR("Secure Boot Manifest key file not given\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (manifest_svn > 15 || manifest_svn == 0) { + ERROR("Key Manifest SVN %d invalid, allowed range: 1-15\n", manifest_svn); + ret = EXIT_FAILURE; + goto exit; + } + + if (params.override_km_id) { + if (params.km_id == 0 || params.km_id > 15) { + ERROR("Key Manifest ID %d invalid, allowed range: 1-15\n", + params.km_id); + ret = EXIT_FAILURE; + goto exit; + } + } + + ret = create_key_manifest(&man, fileLen, manifest_svn); + if (ret < 0) { + goto exit; + } + + ret = rsa_sign_manifest(&man, params.km_key_file); + if (ret < 0) { + goto exit; + } + + ret = inject_manifest_to_binary(params.file_name, fileBuf, fileLen, &man); + if (ret < 0) { + goto exit; + } + + printf("Key Manifest generated successfully\n"); + + if (params.output) { + printf("Saving Key Manifest as %s\n", params.output); + ret = save_buffer_to_file(params.output, (byte *)&man, MANIFEST_SIZE); + } else { + printf("Not saving Key Manifest as a file, not requested to\n"); + } + +exit: + /* Free */ + if (fileBuf) { + free(fileBuf); + } + + return ret; +} + +static int print_key_hash_from_manifest(const struct manifest *man) +{ + int ret; + wc_Sha256 sha256; + const struct key_signature *key_struct; + uint8_t key_hash[WC_SHA256_DIGEST_SIZE]; + + key_struct = &man->key_sig; + + ret = wc_InitSha256(&sha256); + if (ret != 0) { + ERROR("Failed to initialize SHA256 context\n"); + return ret; + } + + ret = wc_Sha256Update(&sha256, key_struct->modulus, sizeof(key_struct->modulus)); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + ret = wc_Sha256Update(&sha256, (byte *)&key_struct->exponent, + sizeof(key_struct->exponent)); + if (ret != 0) { + ERROR("Failed to calculate SHA256\n"); + return ret; + } + + ret = wc_Sha256Final(&sha256, key_hash); + if (ret != 0) { + ERROR("Failed to generate SHA256 hash\n"); + return ret; + } + + if (swap_bytes(key_hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Failed to change SHA256 hash endianess!\n"); + return EXIT_FAILURE; + } + + print_sha256(key_hash); + + return ret; +} + +static void print_manifest_header(const struct manifest_header *mh) +{ + printf("\tMagic: "); + print_magic(mh->magic); + printf("\tVersion: %d\n", mh->version); + printf("\tSize: %d\n", mh->size); + printf("\tSvn: %d\n", mh->svn); +} + + +static void print_key_signature(const struct key_signature *ks) +{ + printf("\tKey modulus:\n"); + hexdump(ks->modulus, sizeof(ks->modulus), 16, 2); + printf("\tKey exponent: 0x%x\n", ks->exponent); + printf("\tSignature:\n"); + hexdump(ks->signature, sizeof(ks->signature), 16, 2); +} + +static void print_key_manifest(const struct manifest *km) +{ + printf("Key Manifest:\n"); + print_manifest_header(&km->header); + printf("\tKey Manifest ID: 0x%02x\n", km->km_id); + printf("\tSB Key hash: "); + print_sha256(km->hash); + print_key_signature(&km->key_sig); + printf("\n"); + printf("\tFYI: Secure Boot Key Manifest Key SHA256 hash:\n\n\t"); + print_key_hash_from_manifest(km); + printf("\n\n"); +} + +static void print_sb_manifest(const struct manifest *sbm) +{ + printf("Secure Boot Manifest:\n"); + print_manifest_header(&sbm->header); + printf("\tIBB hash: "); + print_sha256(sbm->hash); + printf("\tOEM Data:\n"); + hexdump(sbm->sb.oem_data, sizeof(sbm->sb.oem_data), 16, 2); + print_key_signature(&sbm->key_sig); + printf("\n"); + printf("\tFYI: Secure Boot Manifest Key SHA256 hash:\n\n\t"); + print_key_hash_from_manifest(sbm); + printf("\n\n"); +} + +static int cmd_print(void) +{ + int ret = 0; + word32 fileLen; + byte *fileBuf = NULL; + bool sbm_found = false; + bool km_found = false; + word32 offset; + + if (params.file_name) { + ret = load_file_to_buffer(params.file_name, &fileBuf, &fileLen); + if (ret < 0) { + goto exit; + } + } else { + ERROR("Image file not given\n"); + return EXIT_FAILURE; + } + + /* Maybe it is SB manifest or KM manifest file (with IBB or not) */ + if (fileLen == MANIFEST_SIZE || fileLen == (IBB_SIZE + SB_MANIFEST_SIZE)) { + if (*(uint32_t *)fileBuf == SB_MANIFEST_MAGIC) { + printf("Input file seems to be a Secure Boot Manifest\n\n"); + print_sb_manifest((struct manifest *)fileBuf); + } else if (*(uint32_t *)fileBuf == KEY_MANIFEST_MAGIC) { + printf("Input file seems to be a Key Manifest\n\n"); + print_key_manifest((struct manifest *)fileBuf); + } else { + ERROR("Input file invalid size\n"); + ret = EXIT_FAILURE; + } + } else if (fileLen == KEY_MANIFEST_SIZE || + fileLen == (IBB_SIZE + SB_MANIFEST_SIZE + KEY_MANIFEST_SIZE)) { + if (*(uint32_t *)fileBuf == KEY_MANIFEST_MAGIC) { + printf("Input file seems to be a Key Manifest\n\n"); + print_key_manifest((struct manifest *)fileBuf); + if (fileLen > KEY_MANIFEST_SIZE && + *(uint32_t *)&fileBuf[KEY_MANIFEST_SIZE] == SB_MANIFEST_MAGIC) { + print_sb_manifest((struct manifest *) + &fileBuf[KEY_MANIFEST_SIZE]); + } + } else { + ERROR("Input file invalid size\n"); + ret = EXIT_FAILURE; + } + } else if (fileLen > (IBB_SIZE + SB_MANIFEST_SIZE + KEY_MANIFEST_SIZE)) { + /* Treat it as a full binary */ + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE - KEY_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == KEY_MANIFEST_MAGIC) { + print_key_manifest((struct manifest *)&fileBuf[offset]); + km_found = true; + } + + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == SB_MANIFEST_MAGIC) { + print_sb_manifest((struct manifest *)&fileBuf[offset]); + sbm_found = true; + } + + if (!sbm_found && !km_found) { + ERROR("Input file invalid, manifests not found\n"); + ret = EXIT_FAILURE; + } + } else { + ERROR("Input file invalid size\n"); + ret = EXIT_FAILURE; + } + +exit: + if (fileBuf) { + free(fileBuf); + } + + return ret; +} + +static int rsa_verify_manifest_signature(const struct manifest *man, const char *key_path) +{ + int ret; + RsaKey rsaKey; + struct key_signature key_struct; + uint8_t modulus[256]; + uint32_t exponent = 0; + word32 e_size = sizeof(exponent); + word32 n_size = sizeof(modulus); + + memcpy(&key_struct, &man->key_sig, sizeof(key_struct)); + + ret = wc_InitRsaKey(&rsaKey, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + goto exit; + } + + ret = rsa_load_key_file(key_path, &rsaKey); + if (ret != 0) { + ERROR("Failed to load RSA key %s! (%d)\n", key_path, ret); + goto exit; + } + + ret = wc_RsaFlattenPublicKey(&rsaKey, (byte *)&exponent, &e_size, + (byte *)&modulus, &n_size); + if (ret != 0) { + ERROR("Failed to extract Secure Boot Manifest Key exponent and modulus!\n"); + return ret; + } + + if (swap_bytes(modulus, sizeof(modulus))) { + ERROR("Failed to change RSA Signature endianess!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (memcmp(modulus, key_struct.modulus, sizeof(modulus))) { + ERROR("RSA key modulus does not match the key used in manifest!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (exponent != key_struct.exponent) { + ERROR("RSA key exponent does not match the key used in manifest!\n"); + ERROR("%x != %x\n", exponent, key_struct.exponent); + ret = EXIT_FAILURE; + goto exit; + } + + if (swap_bytes(key_struct.signature, sizeof(key_struct.signature))) { + ERROR("Failed to change RSA Signature endianess!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + ret = wc_SignatureVerify(WC_HASH_TYPE_SHA256, WC_SIGNATURE_TYPE_RSA_W_ENC, + (byte *)man, + MANIFEST_SIZE - sizeof(struct key_signature), + key_struct.signature, sizeof(key_struct.signature), + &rsaKey, sizeof(rsaKey)); + + if (ret != 0) { + ERROR("Manifest signature verification failed!\n"); + goto exit; + } + +exit: + wc_FreeRsaKey(&rsaKey); + + return ret; +} + +static int verify_sb_key_hash(const struct manifest *man) +{ + int ret; + RsaKey rsaKey; + uint8_t key_hash[32]; + + ret = wc_InitRsaKey(&rsaKey, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + goto exit; + } + + ret = rsa_load_key_file(params.sbm_key_file, &rsaKey); + if (ret != 0) { + ERROR("Failed to load RSA key %s!\n", params.sbm_key_file); + goto exit; + } + + ret = calculate_key_hash(&rsaKey, key_hash); + if (ret != 0) { + ERROR("Failed to calculate RSA key hash %s!\n", params.sbm_key_file); + goto exit; + } + + if (memcmp(key_hash, man->hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Secure Boot Key SHA256 hash does not match the key hash in the Key" + " Manifest!\n"); + print_sha256(key_hash); + print_sha256(man->hash); + ret = EXIT_FAILURE; + } + +exit: + wc_FreeRsaKey(&rsaKey); + + return ret; +} + +static int verify_ibb_hash(const struct manifest *man, const byte *fileBuf, int fileLen) +{ + int ret; + uint8_t ibb_hash[32]; + + ret = calculate_ibb_hash(&fileBuf[fileLen - IBB_SIZE], ibb_hash); + if (ret != 0) { + ERROR("Failed to calcualte IBB hash!\n"); + return ret; + } + + if (memcmp(ibb_hash, man->hash, WC_SHA256_DIGEST_SIZE)) { + ERROR("Calculated IBB SHA256 hash does not match the IBB hash in Secure Boot" + " Manifest!\n"); + ret = EXIT_FAILURE; + } + + return ret; +} + +static int cmd_verify(void) +{ + int ret = 0; + word32 fileLen; + byte *fileBuf = NULL; + word32 offset; + const struct manifest *km = NULL; + const struct manifest *sbm = NULL; + + if (params.file_name) { + ret = load_file_to_buffer(params.file_name, &fileBuf, &fileLen); + if (ret < 0) { + goto exit; + } + } else { + ERROR("Image file not given\n"); + return EXIT_FAILURE; + } + + if (fileLen >= (IBB_SIZE + SB_MANIFEST_SIZE + KEY_MANIFEST_SIZE)) { + /* Treat it as a full binary */ + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE - KEY_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == KEY_MANIFEST_MAGIC) { + km = (struct manifest *)&fileBuf[offset]; + } + + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == SB_MANIFEST_MAGIC) { + sbm = (struct manifest *)&fileBuf[offset]; + } + + if (km == NULL && sbm == NULL) { + ERROR("Input file invalid, manifests not found\n"); + ret = EXIT_FAILURE; + goto exit; + } + } else if (fileLen == (IBB_SIZE + SB_MANIFEST_SIZE)) { + offset = fileLen - IBB_SIZE - SB_MANIFEST_SIZE; + + if (*(uint32_t *)&fileBuf[offset] == SB_MANIFEST_MAGIC) { + sbm = (struct manifest *)&fileBuf[offset]; + } + } else { + ERROR("Input file invalid size\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (!params.sbm_key_file) { + ERROR("Secure Boot Manifest key file not given\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (km != NULL && !params.km_key_file) { + ERROR("Key Manifest key file not given, but Key Manifest found in the input" + " file\n"); + ERROR("Can not verify Key Manifest!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (sbm == NULL) { + ERROR("Secure Boot Manifest not found in the input file, but is required!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + /* Verify hash type is supported */ + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != 32) { + ERROR("Hash type SHA256 not supported!\n"); + ret = EXIT_FAILURE; + goto exit; + } + + if (km != NULL) { + printf("Verifying Key Manifest...\n"); + + ret = 0; + if (km->header.size != MANIFEST_SIZE) { + ERROR("Invalid Key Manifest size field! (%d != 1024)\n", + km->header.size); + ret--; + } + + if (km->km_id == 0 || km->km_id > 15) { + ERROR("Invalid Key Manifest ID field! (%d %s)\n", + km->km_id, km->km_id == 0 ? "== 0" : "> 15"); + ret--; + } + + if (km->key_sig.exponent != RSA_KEY_EXPONENT) { + ERROR("Incorrect RSA key exponent in the Key Manifest!" + " 0x%x != 0x10001\n", km->key_sig.exponent); + ret--; + } + + if (!mem_is_zero(km->reserved, sizeof(km->reserved))) { + ERROR("Key Manifest reserved space is not zeroed!\n"); + ret--; + } + + if (!mem_is_zero((byte *)(km + 1), KEY_MANIFEST_PAD_SIZE)) { + ERROR("Key Manifest is not zero-padded to 4KB!\n"); + ret--; + } + + ret -= verify_sb_key_hash(km); + ret -= rsa_verify_manifest_signature(km, params.km_key_file); + + if (ret == 0) { + printf("Key Manifest verification successful!\n\n"); + printf("TXE should be provisioned with the following key hash:\n"); + print_key_hash_from_manifest(km); + printf("TXE should be provisioned with the following Key Manifest ID:" + " 0x%02x\n\n", km->km_id); + } else { + printf("Key Manifest verification FAILED!\n\n"); + goto exit; + } + } + + printf("Verifying Secure Boot Manifest...\n"); + + ret = 0; + if (sbm->header.size != MANIFEST_SIZE) { + ERROR("Invalid Secure Boot Manifest size field! (%d != 1024)\n", + sbm->header.size); + ret--; + } + + if (sbm->key_sig.exponent != RSA_KEY_EXPONENT) { + ERROR("Incorrect RSA key exponent in the Secure Boot Manifest!" + " 0x%x != 0x10001\n", sbm->key_sig.exponent); + ret--; + } + + ret -= verify_ibb_hash(sbm, fileBuf, fileLen); + ret -= rsa_verify_manifest_signature(sbm, params.sbm_key_file); + + if (ret == 0) { + printf("Secure Boot Manifest verification successful!\n\n"); + if (km == NULL) { + printf("TXE should be provisioned with the following key hash:\n"); + print_key_hash_from_manifest(sbm); + } + } else { + printf("Secure Boot Manifest verification FAILED!\n\n"); + } + +exit: + if (fileBuf) { + free(fileBuf); + } + + return ret; +} + +static int cmd_keyhash(void) +{ + int ret; + RsaKey key; + byte keyhash[WC_SHA256_DIGEST_SIZE]; + + if (!params.file_name) { + ERROR("Key file not given\n"); + return EXIT_FAILURE; + } + + if (wc_HashGetDigestSize(WC_HASH_TYPE_SHA256) != WC_SHA256_DIGEST_SIZE) { + ERROR("Hash type SHA256 not supported!\n"); + return EXIT_FAILURE; + } + + ret = wc_InitRsaKey(&key, NULL); + if (ret != 0) { + ERROR("Init RSA key failed! %d\n", ret); + return ret; + } + + ret = rsa_load_key_file(params.file_name, &key); + if (ret != 0) { + ERROR("Failed to load Secure Boot Manifest Key!\n"); + goto exit; + } + + ret = calculate_key_hash(&key, keyhash); + if (ret != 0) { + ERROR("Failed to calculate RSA key hash of '%s'!\n", params.file_name); + goto exit; + } + + printf("SHA256 of RSA key '%s':\n", params.file_name); + print_sha256(keyhash); + +exit: + wc_FreeRsaKey(&key); + return ret; +} + +static struct command { + const char *name; + const char *optstring; + int (*cb)(void); +} commands[] = { + { "print", "h?", cmd_print }, + { "keyhash", "h?", cmd_keyhash }, + { "verify", "h?", cmd_verify }, + { "generate-sbm", "o:h?", cmd_generate_sbm }, + { "generate-km", "o:h?", cmd_generate_km }, +}; + +enum { + LONGOPT_START = 256, + LONGOPT_SBM_KEY_FILE = LONGOPT_START, + LONGOPT_SBM_OEM_DATA, + LONGOPT_KM_KEY_FILE, + LONGOPT_KM_ID, + LONGOPT_MANIFEST_SVN, + LONGOPT_END, +}; + +static struct option long_options[] = { + {"help", 0, 0, 'h'}, + {"version", 0, 0, 'v'}, + {"output", required_argument, 0, 'o'}, + {"sbm-key-file", required_argument, 0, LONGOPT_SBM_KEY_FILE}, + {"oem-data", required_argument, 0, LONGOPT_SBM_OEM_DATA}, + {"km-key-file", required_argument, 0, LONGOPT_KM_KEY_FILE}, + {"km-id", required_argument, 0, LONGOPT_KM_ID}, + {"svn", required_argument, 0, LONGOPT_MANIFEST_SVN}, + {NULL, 0, 0, 0 } +}; + +static bool valid_opt(word32 i, int c) +{ + /* Check if it is one of the optstrings supported by the command. */ + if (strchr(commands[i].optstring, c)) + return true; + + /* + * Check if it is one of the non-ASCII characters. Currently, the + * non-ASCII characters are only checked against the valid list + * irrespective of the command. + */ + return c >= LONGOPT_START && c < LONGOPT_END; +} + +static void usage(const char *name) +{ + printf("txesbmantool: Utility for generating TXE Secure Boot manifests\n" + "USAGE:\n" + " %s FILE COMMAND\n\n" + " %s --help\n\n" + " %s --version\n\n" + "COMMANDs:\n" + " print\n" + " keyhash\n" + " verify --sbm-key-file [--km-key-file ]\n" + " generate-km --sbm-key-file --km-key-file [--km-id ] [--svn ] [-o ]\n" + " generate-sbm --sbm-key-file [--oem-data ] [--svn ] [-o ]\n" + "\nOPTIONS:\n" + " -o : Output manifest file (optional)\n" + " --sbm-key-file : Secure Boot (SB) Manifest key file\n" + " --km-key-file : Key Manifest key file\n" + " --km-id : Key Manifest ID number (default 1)\n" + " --oem-data : Optional OEM data file to be included in SB Manifest\n" + " --svn : Security Version Number for the manifest (default 2),\n" + " Key Manifest SVN range 1-15, SB Manifest SVN range 0-63\n" + "\n", + name, name, name); +} + +static int no_file_cmd_args(int argc, char **argv) +{ + int c; + int option_index; + + c = getopt_long(argc, argv, "?hv", long_options, &option_index); + + switch (c) { + case 'v': + printf("Version: %s\n", tool_version); + return 0; + case 'h': + case '?': + usage(argv[0]); + return 0; + default: + usage(argv[0]); + return 1; + } + + usage(argv[0]); + return 1; +} + +int main(int argc, char **argv) +{ + if (argc < 3) { + return no_file_cmd_args(argc, argv); + } + + const char *prog_name = argv[0]; + const char *file_name = argv[1]; + const char *cmd = argv[2]; + + word32 i; + params.file_name = file_name; + params.override_km_id = false; + params.override_svn = false; + + for (i = 0; i < ARRAY_SIZE(commands); i++) { + if (strcmp(cmd, commands[i].name)) + continue; + + int c; + int option_index; + + while (1) { + c = getopt_long(argc, argv, commands[i].optstring, + long_options, &option_index); + + if (c == -1) + break; + + if (!valid_opt(i, c)) { + if (c < LONGOPT_START) { + ERROR("Invalid option -- '%c'\n", c); + } else { + ERROR("Invalid option -- '%d'\n", c); + } + usage(prog_name); + return 1; + } + + switch (c) { + case 'o': + params.output = optarg; + break; + case LONGOPT_SBM_KEY_FILE: + params.sbm_key_file = optarg; + break; + case LONGOPT_SBM_OEM_DATA: + params.oem_data_file = optarg; + break; + case LONGOPT_KM_KEY_FILE: + params.km_key_file = optarg; + break; + case LONGOPT_KM_ID: + params.km_id = atoi(optarg); + params.override_km_id = true; + break; + case LONGOPT_MANIFEST_SVN: + params.svn = atoi(optarg); + params.override_svn = true; + break; + case 'h': + case '?': + default: + usage(prog_name); + return 1; + } + } + + break; + } + + if (i == ARRAY_SIZE(commands)) { + printf("No command matches %s!\n", cmd); + usage(prog_name); + return 1; + } + + if (commands[i].cb()) + return 1; + + return 0; +}